arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23 #include "cpuid.h"
  24
  25 #include <linux/module.h>
  26 #include <linux/mod_devicetable.h>
  27 #include <linux/kernel.h>
  28 #include <linux/vmalloc.h>
  29 #include <linux/highmem.h>
  30 #include <linux/sched.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33
  34 #include <asm/perf_event.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/desc.h>
  37 #include <asm/kvm_para.h>
  38
  39 #include <asm/virtext.h>
  40 #include "trace.h"
  41
  42 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  43
  44 MODULE_AUTHOR("Qumranet");
  45 MODULE_LICENSE("GPL");
  46
  47 static const struct x86_cpu_id svm_cpu_id[] = {
  48         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  49         {}
  50 };
  51 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  52
  53 #define IOPM_ALLOC_ORDER 2
  54 #define MSRPM_ALLOC_ORDER 1
  55
  56 #define SEG_TYPE_LDT 2
  57 #define SEG_TYPE_BUSY_TSS16 3
  58
  59 #define SVM_FEATURE_NPT            (1 <<  0)
  60 #define SVM_FEATURE_LBRV           (1 <<  1)
  61 #define SVM_FEATURE_SVML           (1 <<  2)
  62 #define SVM_FEATURE_NRIP           (1 <<  3)
  63 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  64 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  65 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  66 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  67 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  68
  69 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  70 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  71 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  72
  73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  74
  75 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  76 #define TSC_RATIO_MIN           0x0000000000000001ULL
  77 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  78
  79 static bool erratum_383_found __read_mostly;
  80
  81 static const u32 host_save_user_msrs[] = {
  82 #ifdef CONFIG_X86_64
  83         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  84         MSR_FS_BASE,
  85 #endif
  86         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  87 };
  88
  89 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  90
  91 struct kvm_vcpu;
  92
  93 struct nested_state {
  94         struct vmcb *hsave;
  95         u64 hsave_msr;
  96         u64 vm_cr_msr;
  97         u64 vmcb;
  98
  99         /* These are the merged vectors */
 100         u32 *msrpm;
 101
 102         /* gpa pointers to the real vectors */
 103         u64 vmcb_msrpm;
 104         u64 vmcb_iopm;
 105
 106         /* A VMEXIT is required but not yet emulated */
 107         bool exit_required;
 108
 109         /* cache for intercepts of the guest */
 110         u32 intercept_cr;
 111         u32 intercept_dr;
 112         u32 intercept_exceptions;
 113         u64 intercept;
 114
 115         /* Nested Paging related state */
 116         u64 nested_cr3;
 117 };
 118
 119 #define MSRPM_OFFSETS   16
 120 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 121
 122 /*
 123  * Set osvw_len to higher value when updated Revision Guides
 124  * are published and we know what the new status bits are
 125  */
 126 static uint64_t osvw_len = 4, osvw_status;
 127
 128 struct vcpu_svm {
 129         struct kvm_vcpu vcpu;
 130         struct vmcb *vmcb;
 131         unsigned long vmcb_pa;
 132         struct svm_cpu_data *svm_data;
 133         uint64_t asid_generation;
 134         uint64_t sysenter_esp;
 135         uint64_t sysenter_eip;
 136
 137         u64 next_rip;
 138
 139         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 140         struct {
 141                 u16 fs;
 142                 u16 gs;
 143                 u16 ldt;
 144                 u64 gs_base;
 145         } host;
 146
 147         u32 *msrpm;
 148
 149         ulong nmi_iret_rip;
 150
 151         struct nested_state nested;
 152
 153         bool nmi_singlestep;
 154
 155         unsigned int3_injected;
 156         unsigned long int3_rip;
 157         u32 apf_reason;
 158
 159         u64  tsc_ratio;
 160 };
 161
 162 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 163 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 164
 165 #define MSR_INVALID                     0xffffffffU
 166
 167 static const struct svm_direct_access_msrs {
 168         u32 index;   /* Index of the MSR */
 169         bool always; /* True if intercept is always on */
 170 } direct_access_msrs[] = {
 171         { .index = MSR_STAR,                            .always = true  },
 172         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 173 #ifdef CONFIG_X86_64
 174         { .index = MSR_GS_BASE,                         .always = true  },
 175         { .index = MSR_FS_BASE,                         .always = true  },
 176         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 177         { .index = MSR_LSTAR,                           .always = true  },
 178         { .index = MSR_CSTAR,                           .always = true  },
 179         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 180 #endif
 181         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 182         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 183         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 184         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 185         { .index = MSR_INVALID,                         .always = false },
 186 };
 187
 188 /* enable NPT for AMD64 and X86 with PAE */
 189 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 190 static bool npt_enabled = true;
 191 #else
 192 static bool npt_enabled;
 193 #endif
 194
 195 /* allow nested paging (virtualized MMU) for all guests */
 196 static int npt = true;
 197 module_param(npt, int, S_IRUGO);
 198
 199 /* allow nested virtualization in KVM/SVM */
 200 static int nested = true;
 201 module_param(nested, int, S_IRUGO);
 202
 203 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 204 static void svm_complete_interrupts(struct vcpu_svm *svm);
 205
 206 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 207 static int nested_svm_intercept(struct vcpu_svm *svm);
 208 static int nested_svm_vmexit(struct vcpu_svm *svm);
 209 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 210                                       bool has_error_code, u32 error_code);
 211 static u64 __scale_tsc(u64 ratio, u64 tsc);
 212
 213 enum {
 214         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 215                             pause filter count */
 216         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 217         VMCB_ASID,       /* ASID */
 218         VMCB_INTR,       /* int_ctl, int_vector */
 219         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 220         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 221         VMCB_DR,         /* DR6, DR7 */
 222         VMCB_DT,         /* GDT, IDT */
 223         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 224         VMCB_CR2,        /* CR2 only */
 225         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 226         VMCB_DIRTY_MAX,
 227 };
 228
 229 /* TPR and CR2 are always written before VMRUN */
 230 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 231
 232 static inline void mark_all_dirty(struct vmcb *vmcb)
 233 {
 234         vmcb->control.clean = 0;
 235 }
 236
 237 static inline void mark_all_clean(struct vmcb *vmcb)
 238 {
 239         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 240                                & ~VMCB_ALWAYS_DIRTY_MASK;
 241 }
 242
 243 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 244 {
 245         vmcb->control.clean &= ~(1 << bit);
 246 }
 247
 248 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 249 {
 250         return container_of(vcpu, struct vcpu_svm, vcpu);
 251 }
 252
 253 static void recalc_intercepts(struct vcpu_svm *svm)
 254 {
 255         struct vmcb_control_area *c, *h;
 256         struct nested_state *g;
 257
 258         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 259
 260         if (!is_guest_mode(&svm->vcpu))
 261                 return;
 262
 263         c = &svm->vmcb->control;
 264         h = &svm->nested.hsave->control;
 265         g = &svm->nested;
 266
 267         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 268         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 269         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 270         c->intercept = h->intercept | g->intercept;
 271 }
 272
 273 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 274 {
 275         if (is_guest_mode(&svm->vcpu))
 276                 return svm->nested.hsave;
 277         else
 278                 return svm->vmcb;
 279 }
 280
 281 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 282 {
 283         struct vmcb *vmcb = get_host_vmcb(svm);
 284
 285         vmcb->control.intercept_cr |= (1U << bit);
 286
 287         recalc_intercepts(svm);
 288 }
 289
 290 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 291 {
 292         struct vmcb *vmcb = get_host_vmcb(svm);
 293
 294         vmcb->control.intercept_cr &= ~(1U << bit);
 295
 296         recalc_intercepts(svm);
 297 }
 298
 299 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 300 {
 301         struct vmcb *vmcb = get_host_vmcb(svm);
 302
 303         return vmcb->control.intercept_cr & (1U << bit);
 304 }
 305
 306 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
 307 {
 308         struct vmcb *vmcb = get_host_vmcb(svm);
 309
 310         vmcb->control.intercept_dr |= (1U << bit);
 311
 312         recalc_intercepts(svm);
 313 }
 314
 315 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
 316 {
 317         struct vmcb *vmcb = get_host_vmcb(svm);
 318
 319         vmcb->control.intercept_dr &= ~(1U << bit);
 320
 321         recalc_intercepts(svm);
 322 }
 323
 324 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 325 {
 326         struct vmcb *vmcb = get_host_vmcb(svm);
 327
 328         vmcb->control.intercept_exceptions |= (1U << bit);
 329
 330         recalc_intercepts(svm);
 331 }
 332
 333 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 334 {
 335         struct vmcb *vmcb = get_host_vmcb(svm);
 336
 337         vmcb->control.intercept_exceptions &= ~(1U << bit);
 338
 339         recalc_intercepts(svm);
 340 }
 341
 342 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 343 {
 344         struct vmcb *vmcb = get_host_vmcb(svm);
 345
 346         vmcb->control.intercept |= (1ULL << bit);
 347
 348         recalc_intercepts(svm);
 349 }
 350
 351 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 352 {
 353         struct vmcb *vmcb = get_host_vmcb(svm);
 354
 355         vmcb->control.intercept &= ~(1ULL << bit);
 356
 357         recalc_intercepts(svm);
 358 }
 359
 360 static inline void enable_gif(struct vcpu_svm *svm)
 361 {
 362         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 363 }
 364
 365 static inline void disable_gif(struct vcpu_svm *svm)
 366 {
 367         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 368 }
 369
 370 static inline bool gif_set(struct vcpu_svm *svm)
 371 {
 372         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 373 }
 374
 375 static unsigned long iopm_base;
 376
 377 struct kvm_ldttss_desc {
 378         u16 limit0;
 379         u16 base0;
 380         unsigned base1:8, type:5, dpl:2, p:1;
 381         unsigned limit1:4, zero0:3, g:1, base2:8;
 382         u32 base3;
 383         u32 zero1;
 384 } __attribute__((packed));
 385
 386 struct svm_cpu_data {
 387         int cpu;
 388
 389         u64 asid_generation;
 390         u32 max_asid;
 391         u32 next_asid;
 392         struct kvm_ldttss_desc *tss_desc;
 393
 394         struct page *save_area;
 395 };
 396
 397 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 398
 399 struct svm_init_data {
 400         int cpu;
 401         int r;
 402 };
 403
 404 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 405
 406 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 407 #define MSRS_RANGE_SIZE 2048
 408 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 409
 410 static u32 svm_msrpm_offset(u32 msr)
 411 {
 412         u32 offset;
 413         int i;
 414
 415         for (i = 0; i < NUM_MSR_MAPS; i++) {
 416                 if (msr < msrpm_ranges[i] ||
 417                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 418                         continue;
 419
 420                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 421                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 422
 423                 /* Now we have the u8 offset - but need the u32 offset */
 424                 return offset / 4;
 425         }
 426
 427         /* MSR not in any range */
 428         return MSR_INVALID;
 429 }
 430
 431 #define MAX_INST_SIZE 15
 432
 433 static inline void clgi(void)
 434 {
 435         asm volatile (__ex(SVM_CLGI));
 436 }
 437
 438 static inline void stgi(void)
 439 {
 440         asm volatile (__ex(SVM_STGI));
 441 }
 442
 443 static inline void invlpga(unsigned long addr, u32 asid)
 444 {
 445         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 446 }
 447
 448 static int get_npt_level(void)
 449 {
 450 #ifdef CONFIG_X86_64
 451         return PT64_ROOT_LEVEL;
 452 #else
 453         return PT32E_ROOT_LEVEL;
 454 #endif
 455 }
 456
 457 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 458 {
 459         vcpu->arch.efer = efer;
 460         if (!npt_enabled && !(efer & EFER_LMA))
 461                 efer &= ~EFER_LME;
 462
 463         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 464         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 465 }
 466
 467 static int is_external_interrupt(u32 info)
 468 {
 469         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 470         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 471 }
 472
 473 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 474 {
 475         struct vcpu_svm *svm = to_svm(vcpu);
 476         u32 ret = 0;
 477
 478         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 479                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 480         return ret & mask;
 481 }
 482
 483 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 484 {
 485         struct vcpu_svm *svm = to_svm(vcpu);
 486
 487         if (mask == 0)
 488                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 489         else
 490                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 491
 492 }
 493
 494 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 495 {
 496         struct vcpu_svm *svm = to_svm(vcpu);
 497
 498         if (svm->vmcb->control.next_rip != 0) {
 499                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 500                 svm->next_rip = svm->vmcb->control.next_rip;
 501         }
 502
 503         if (!svm->next_rip) {
 504                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 505                                 EMULATE_DONE)
 506                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 507                 return;
 508         }
 509         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 510                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 511                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 512
 513         kvm_rip_write(vcpu, svm->next_rip);
 514         svm_set_interrupt_shadow(vcpu, 0);
 515 }
 516
 517 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 518                                 bool has_error_code, u32 error_code,
 519                                 bool reinject)
 520 {
 521         struct vcpu_svm *svm = to_svm(vcpu);
 522
 523         /*
 524          * If we are within a nested VM we'd better #VMEXIT and let the guest
 525          * handle the exception
 526          */
 527         if (!reinject &&
 528             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 529                 return;
 530
 531         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 532                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 533
 534                 /*
 535                  * For guest debugging where we have to reinject #BP if some
 536                  * INT3 is guest-owned:
 537                  * Emulate nRIP by moving RIP forward. Will fail if injection
 538                  * raises a fault that is not intercepted. Still better than
 539                  * failing in all cases.
 540                  */
 541                 skip_emulated_instruction(&svm->vcpu);
 542                 rip = kvm_rip_read(&svm->vcpu);
 543                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 544                 svm->int3_injected = rip - old_rip;
 545         }
 546
 547         svm->vmcb->control.event_inj = nr
 548                 | SVM_EVTINJ_VALID
 549                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 550                 | SVM_EVTINJ_TYPE_EXEPT;
 551         svm->vmcb->control.event_inj_err = error_code;
 552 }
 553
 554 static void svm_init_erratum_383(void)
 555 {
 556         u32 low, high;
 557         int err;
 558         u64 val;
 559
 560         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 561                 return;
 562
 563         /* Use _safe variants to not break nested virtualization */
 564         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 565         if (err)
 566                 return;
 567
 568         val |= (1ULL << 47);
 569
 570         low  = lower_32_bits(val);
 571         high = upper_32_bits(val);
 572
 573         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 574
 575         erratum_383_found = true;
 576 }
 577
 578 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 579 {
 580         /*
 581          * Guests should see errata 400 and 415 as fixed (assuming that
 582          * HLT and IO instructions are intercepted).
 583          */
 584         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 585         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 586
 587         /*
 588          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 589          * all osvw.status bits inside that length, including bit 0 (which is
 590          * reserved for erratum 298), are valid. However, if host processor's
 591          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 592          * be conservative here and therefore we tell the guest that erratum 298
 593          * is present (because we really don't know).
 594          */
 595         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 596                 vcpu->arch.osvw.status |= 1;
 597 }
 598
 599 static int has_svm(void)
 600 {
 601         const char *msg;
 602
 603         if (!cpu_has_svm(&msg)) {
 604                 printk(KERN_INFO "has_svm: %s\n", msg);
 605                 return 0;
 606         }
 607
 608         return 1;
 609 }
 610
 611 static void svm_hardware_disable(void)
 612 {
 613         /* Make sure we clean up behind us */
 614         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 615                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 616
 617         cpu_svm_disable();
 618
 619         amd_pmu_disable_virt();
 620 }
 621
 622 static int svm_hardware_enable(void)
 623 {
 624
 625         struct svm_cpu_data *sd;
 626         uint64_t efer;
 627         struct desc_ptr gdt_descr;
 628         struct desc_struct *gdt;
 629         int me = raw_smp_processor_id();
 630
 631         rdmsrl(MSR_EFER, efer);
 632         if (efer & EFER_SVME)
 633                 return -EBUSY;
 634
 635         if (!has_svm()) {
 636                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 637                 return -EINVAL;
 638         }
 639         sd = per_cpu(svm_data, me);
 640         if (!sd) {
 641                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 642                 return -EINVAL;
 643         }
 644
 645         sd->asid_generation = 1;
 646         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 647         sd->next_asid = sd->max_asid + 1;
 648
 649         native_store_gdt(&gdt_descr);
 650         gdt = (struct desc_struct *)gdt_descr.address;
 651         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 652
 653         wrmsrl(MSR_EFER, efer | EFER_SVME);
 654
 655         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 656
 657         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 658                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 659                 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
 660         }
 661
 662
 663         /*
 664          * Get OSVW bits.
 665          *
 666          * Note that it is possible to have a system with mixed processor
 667          * revisions and therefore different OSVW bits. If bits are not the same
 668          * on different processors then choose the worst case (i.e. if erratum
 669          * is present on one processor and not on another then assume that the
 670          * erratum is present everywhere).
 671          */
 672         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 673                 uint64_t len, status = 0;
 674                 int err;
 675
 676                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 677                 if (!err)
 678                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 679                                                       &err);
 680
 681                 if (err)
 682                         osvw_status = osvw_len = 0;
 683                 else {
 684                         if (len < osvw_len)
 685                                 osvw_len = len;
 686                         osvw_status |= status;
 687                         osvw_status &= (1ULL << osvw_len) - 1;
 688                 }
 689         } else
 690                 osvw_status = osvw_len = 0;
 691
 692         svm_init_erratum_383();
 693
 694         amd_pmu_enable_virt();
 695
 696         return 0;
 697 }
 698
 699 static void svm_cpu_uninit(int cpu)
 700 {
 701         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 702
 703         if (!sd)
 704                 return;
 705
 706         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 707         __free_page(sd->save_area);
 708         kfree(sd);
 709 }
 710
 711 static int svm_cpu_init(int cpu)
 712 {
 713         struct svm_cpu_data *sd;
 714         int r;
 715
 716         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 717         if (!sd)
 718                 return -ENOMEM;
 719         sd->cpu = cpu;
 720         sd->save_area = alloc_page(GFP_KERNEL);
 721         r = -ENOMEM;
 722         if (!sd->save_area)
 723                 goto err_1;
 724
 725         per_cpu(svm_data, cpu) = sd;
 726
 727         return 0;
 728
 729 err_1:
 730         kfree(sd);
 731         return r;
 732
 733 }
 734
 735 static bool valid_msr_intercept(u32 index)
 736 {
 737         int i;
 738
 739         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 740                 if (direct_access_msrs[i].index == index)
 741                         return true;
 742
 743         return false;
 744 }
 745
 746 static void set_msr_interception(u32 *msrpm, unsigned msr,
 747                                  int read, int write)
 748 {
 749         u8 bit_read, bit_write;
 750         unsigned long tmp;
 751         u32 offset;
 752
 753         /*
 754          * If this warning triggers extend the direct_access_msrs list at the
 755          * beginning of the file
 756          */
 757         WARN_ON(!valid_msr_intercept(msr));
 758
 759         offset    = svm_msrpm_offset(msr);
 760         bit_read  = 2 * (msr & 0x0f);
 761         bit_write = 2 * (msr & 0x0f) + 1;
 762         tmp       = msrpm[offset];
 763
 764         BUG_ON(offset == MSR_INVALID);
 765
 766         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 767         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 768
 769         msrpm[offset] = tmp;
 770 }
 771
 772 static void svm_vcpu_init_msrpm(u32 *msrpm)
 773 {
 774         int i;
 775
 776         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 777
 778         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 779                 if (!direct_access_msrs[i].always)
 780                         continue;
 781
 782                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 783         }
 784 }
 785
 786 static void add_msr_offset(u32 offset)
 787 {
 788         int i;
 789
 790         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 791
 792                 /* Offset already in list? */
 793                 if (msrpm_offsets[i] == offset)
 794                         return;
 795
 796                 /* Slot used by another offset? */
 797                 if (msrpm_offsets[i] != MSR_INVALID)
 798                         continue;
 799
 800                 /* Add offset to list */
 801                 msrpm_offsets[i] = offset;
 802
 803                 return;
 804         }
 805
 806         /*
 807          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 808          * increase MSRPM_OFFSETS in this case.
 809          */
 810         BUG();
 811 }
 812
 813 static void init_msrpm_offsets(void)
 814 {
 815         int i;
 816
 817         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 818
 819         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 820                 u32 offset;
 821
 822                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 823                 BUG_ON(offset == MSR_INVALID);
 824
 825                 add_msr_offset(offset);
 826         }
 827 }
 828
 829 static void svm_enable_lbrv(struct vcpu_svm *svm)
 830 {
 831         u32 *msrpm = svm->msrpm;
 832
 833         svm->vmcb->control.lbr_ctl = 1;
 834         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 835         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 836         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 837         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 838 }
 839
 840 static void svm_disable_lbrv(struct vcpu_svm *svm)
 841 {
 842         u32 *msrpm = svm->msrpm;
 843
 844         svm->vmcb->control.lbr_ctl = 0;
 845         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 846         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 847         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 848         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 849 }
 850
 851 static __init int svm_hardware_setup(void)
 852 {
 853         int cpu;
 854         struct page *iopm_pages;
 855         void *iopm_va;
 856         int r;
 857
 858         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 859
 860         if (!iopm_pages)
 861                 return -ENOMEM;
 862
 863         iopm_va = page_address(iopm_pages);
 864         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 865         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 866
 867         init_msrpm_offsets();
 868
 869         if (boot_cpu_has(X86_FEATURE_NX))
 870                 kvm_enable_efer_bits(EFER_NX);
 871
 872         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 873                 kvm_enable_efer_bits(EFER_FFXSR);
 874
 875         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 876                 u64 max;
 877
 878                 kvm_has_tsc_control = true;
 879
 880                 /*
 881                  * Make sure the user can only configure tsc_khz values that
 882                  * fit into a signed integer.
 883                  * A min value is not calculated needed because it will always
 884                  * be 1 on all machines and a value of 0 is used to disable
 885                  * tsc-scaling for the vcpu.
 886                  */
 887                 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
 888
 889                 kvm_max_guest_tsc_khz = max;
 890         }
 891
 892         if (nested) {
 893                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 894                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 895         }
 896
 897         for_each_possible_cpu(cpu) {
 898                 r = svm_cpu_init(cpu);
 899                 if (r)
 900                         goto err;
 901         }
 902
 903         if (!boot_cpu_has(X86_FEATURE_NPT))
 904                 npt_enabled = false;
 905
 906         if (npt_enabled && !npt) {
 907                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 908                 npt_enabled = false;
 909         }
 910
 911         if (npt_enabled) {
 912                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 913                 kvm_enable_tdp();
 914         } else
 915                 kvm_disable_tdp();
 916
 917         return 0;
 918
 919 err:
 920         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 921         iopm_base = 0;
 922         return r;
 923 }
 924
 925 static __exit void svm_hardware_unsetup(void)
 926 {
 927         int cpu;
 928
 929         for_each_possible_cpu(cpu)
 930                 svm_cpu_uninit(cpu);
 931
 932         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 933         iopm_base = 0;
 934 }
 935
 936 static void init_seg(struct vmcb_seg *seg)
 937 {
 938         seg->selector = 0;
 939         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 940                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 941         seg->limit = 0xffff;
 942         seg->base = 0;
 943 }
 944
 945 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 946 {
 947         seg->selector = 0;
 948         seg->attrib = SVM_SELECTOR_P_MASK | type;
 949         seg->limit = 0xffff;
 950         seg->base = 0;
 951 }
 952
 953 static u64 __scale_tsc(u64 ratio, u64 tsc)
 954 {
 955         u64 mult, frac, _tsc;
 956
 957         mult  = ratio >> 32;
 958         frac  = ratio & ((1ULL << 32) - 1);
 959
 960         _tsc  = tsc;
 961         _tsc *= mult;
 962         _tsc += (tsc >> 32) * frac;
 963         _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
 964
 965         return _tsc;
 966 }
 967
 968 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
 969 {
 970         struct vcpu_svm *svm = to_svm(vcpu);
 971         u64 _tsc = tsc;
 972
 973         if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
 974                 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
 975
 976         return _tsc;
 977 }
 978
 979 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
 980 {
 981         struct vcpu_svm *svm = to_svm(vcpu);
 982         u64 ratio;
 983         u64 khz;
 984
 985         /* Guest TSC same frequency as host TSC? */
 986         if (!scale) {
 987                 svm->tsc_ratio = TSC_RATIO_DEFAULT;
 988                 return;
 989         }
 990
 991         /* TSC scaling supported? */
 992         if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 993                 if (user_tsc_khz > tsc_khz) {
 994                         vcpu->arch.tsc_catchup = 1;
 995                         vcpu->arch.tsc_always_catchup = 1;
 996                 } else
 997                         WARN(1, "user requested TSC rate below hardware speed\n");
 998                 return;
 999         }
1000
1001         khz = user_tsc_khz;
1002
1003         /* TSC scaling required  - calculate ratio */
1004         ratio = khz << 32;
1005         do_div(ratio, tsc_khz);
1006
1007         if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1008                 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1009                                 user_tsc_khz);
1010                 return;
1011         }
1012         svm->tsc_ratio             = ratio;
1013 }
1014
1015 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1016 {
1017         struct vcpu_svm *svm = to_svm(vcpu);
1018
1019         return svm->vmcb->control.tsc_offset;
1020 }
1021
1022 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1023 {
1024         struct vcpu_svm *svm = to_svm(vcpu);
1025         u64 g_tsc_offset = 0;
1026
1027         if (is_guest_mode(vcpu)) {
1028                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1029                                svm->nested.hsave->control.tsc_offset;
1030                 svm->nested.hsave->control.tsc_offset = offset;
1031         }
1032
1033         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1034
1035         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1036 }
1037
1038 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1039 {
1040         struct vcpu_svm *svm = to_svm(vcpu);
1041
1042         WARN_ON(adjustment < 0);
1043         if (host)
1044                 adjustment = svm_scale_tsc(vcpu, adjustment);
1045
1046         svm->vmcb->control.tsc_offset += adjustment;
1047         if (is_guest_mode(vcpu))
1048                 svm->nested.hsave->control.tsc_offset += adjustment;
1049         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1050 }
1051
1052 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1053 {
1054         u64 tsc;
1055
1056         tsc = svm_scale_tsc(vcpu, native_read_tsc());
1057
1058         return target_tsc - tsc;
1059 }
1060
1061 static void init_vmcb(struct vcpu_svm *svm)
1062 {
1063         struct vmcb_control_area *control = &svm->vmcb->control;
1064         struct vmcb_save_area *save = &svm->vmcb->save;
1065
1066         svm->vcpu.fpu_active = 1;
1067         svm->vcpu.arch.hflags = 0;
1068
1069         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1070         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1071         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1072         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1073         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1074         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1075         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1076
1077         set_dr_intercept(svm, INTERCEPT_DR0_READ);
1078         set_dr_intercept(svm, INTERCEPT_DR1_READ);
1079         set_dr_intercept(svm, INTERCEPT_DR2_READ);
1080         set_dr_intercept(svm, INTERCEPT_DR3_READ);
1081         set_dr_intercept(svm, INTERCEPT_DR4_READ);
1082         set_dr_intercept(svm, INTERCEPT_DR5_READ);
1083         set_dr_intercept(svm, INTERCEPT_DR6_READ);
1084         set_dr_intercept(svm, INTERCEPT_DR7_READ);
1085
1086         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1087         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1088         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1089         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1090         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1091         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1092         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1093         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1094
1095         set_exception_intercept(svm, PF_VECTOR);
1096         set_exception_intercept(svm, UD_VECTOR);
1097         set_exception_intercept(svm, MC_VECTOR);
1098
1099         set_intercept(svm, INTERCEPT_INTR);
1100         set_intercept(svm, INTERCEPT_NMI);
1101         set_intercept(svm, INTERCEPT_SMI);
1102         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1103         set_intercept(svm, INTERCEPT_RDPMC);
1104         set_intercept(svm, INTERCEPT_CPUID);
1105         set_intercept(svm, INTERCEPT_INVD);
1106         set_intercept(svm, INTERCEPT_HLT);
1107         set_intercept(svm, INTERCEPT_INVLPG);
1108         set_intercept(svm, INTERCEPT_INVLPGA);
1109         set_intercept(svm, INTERCEPT_IOIO_PROT);
1110         set_intercept(svm, INTERCEPT_MSR_PROT);
1111         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1112         set_intercept(svm, INTERCEPT_SHUTDOWN);
1113         set_intercept(svm, INTERCEPT_VMRUN);
1114         set_intercept(svm, INTERCEPT_VMMCALL);
1115         set_intercept(svm, INTERCEPT_VMLOAD);
1116         set_intercept(svm, INTERCEPT_VMSAVE);
1117         set_intercept(svm, INTERCEPT_STGI);
1118         set_intercept(svm, INTERCEPT_CLGI);
1119         set_intercept(svm, INTERCEPT_SKINIT);
1120         set_intercept(svm, INTERCEPT_WBINVD);
1121         set_intercept(svm, INTERCEPT_MONITOR);
1122         set_intercept(svm, INTERCEPT_MWAIT);
1123         set_intercept(svm, INTERCEPT_XSETBV);
1124
1125         control->iopm_base_pa = iopm_base;
1126         control->msrpm_base_pa = __pa(svm->msrpm);
1127         control->int_ctl = V_INTR_MASKING_MASK;
1128
1129         init_seg(&save->es);
1130         init_seg(&save->ss);
1131         init_seg(&save->ds);
1132         init_seg(&save->fs);
1133         init_seg(&save->gs);
1134
1135         save->cs.selector = 0xf000;
1136         save->cs.base = 0xffff0000;
1137         /* Executable/Readable Code Segment */
1138         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1139                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1140         save->cs.limit = 0xffff;
1141
1142         save->gdtr.limit = 0xffff;
1143         save->idtr.limit = 0xffff;
1144
1145         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1146         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1147
1148         svm_set_efer(&svm->vcpu, 0);
1149         save->dr6 = 0xffff0ff0;
1150         kvm_set_rflags(&svm->vcpu, 2);
1151         save->rip = 0x0000fff0;
1152         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1153
1154         /*
1155          * This is the guest-visible cr0 value.
1156          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1157          */
1158         svm->vcpu.arch.cr0 = 0;
1159         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1160
1161         save->cr4 = X86_CR4_PAE;
1162         /* rdx = ?? */
1163
1164         if (npt_enabled) {
1165                 /* Setup VMCB for Nested Paging */
1166                 control->nested_ctl = 1;
1167                 clr_intercept(svm, INTERCEPT_INVLPG);
1168                 clr_exception_intercept(svm, PF_VECTOR);
1169                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1170                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1171                 save->g_pat = 0x0007040600070406ULL;
1172                 save->cr3 = 0;
1173                 save->cr4 = 0;
1174         }
1175         svm->asid_generation = 0;
1176
1177         svm->nested.vmcb = 0;
1178         svm->vcpu.arch.hflags = 0;
1179
1180         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1181                 control->pause_filter_count = 3000;
1182                 set_intercept(svm, INTERCEPT_PAUSE);
1183         }
1184
1185         mark_all_dirty(svm->vmcb);
1186
1187         enable_gif(svm);
1188 }
1189
1190 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1191 {
1192         struct vcpu_svm *svm = to_svm(vcpu);
1193         u32 dummy;
1194         u32 eax = 1;
1195
1196         init_vmcb(svm);
1197
1198         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1199         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1200 }
1201
1202 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1203 {
1204         struct vcpu_svm *svm;
1205         struct page *page;
1206         struct page *msrpm_pages;
1207         struct page *hsave_page;
1208         struct page *nested_msrpm_pages;
1209         int err;
1210
1211         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1212         if (!svm) {
1213                 err = -ENOMEM;
1214                 goto out;
1215         }
1216
1217         svm->tsc_ratio = TSC_RATIO_DEFAULT;
1218
1219         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1220         if (err)
1221                 goto free_svm;
1222
1223         err = -ENOMEM;
1224         page = alloc_page(GFP_KERNEL);
1225         if (!page)
1226                 goto uninit;
1227
1228         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1229         if (!msrpm_pages)
1230                 goto free_page1;
1231
1232         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1233         if (!nested_msrpm_pages)
1234                 goto free_page2;
1235
1236         hsave_page = alloc_page(GFP_KERNEL);
1237         if (!hsave_page)
1238                 goto free_page3;
1239
1240         svm->nested.hsave = page_address(hsave_page);
1241
1242         svm->msrpm = page_address(msrpm_pages);
1243         svm_vcpu_init_msrpm(svm->msrpm);
1244
1245         svm->nested.msrpm = page_address(nested_msrpm_pages);
1246         svm_vcpu_init_msrpm(svm->nested.msrpm);
1247
1248         svm->vmcb = page_address(page);
1249         clear_page(svm->vmcb);
1250         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1251         svm->asid_generation = 0;
1252         init_vmcb(svm);
1253
1254         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1255         if (kvm_vcpu_is_bsp(&svm->vcpu))
1256                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1257
1258         svm_init_osvw(&svm->vcpu);
1259
1260         return &svm->vcpu;
1261
1262 free_page3:
1263         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1264 free_page2:
1265         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1266 free_page1:
1267         __free_page(page);
1268 uninit:
1269         kvm_vcpu_uninit(&svm->vcpu);
1270 free_svm:
1271         kmem_cache_free(kvm_vcpu_cache, svm);
1272 out:
1273         return ERR_PTR(err);
1274 }
1275
1276 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1277 {
1278         struct vcpu_svm *svm = to_svm(vcpu);
1279
1280         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1281         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1282         __free_page(virt_to_page(svm->nested.hsave));
1283         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1284         kvm_vcpu_uninit(vcpu);
1285         kmem_cache_free(kvm_vcpu_cache, svm);
1286 }
1287
1288 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1289 {
1290         struct vcpu_svm *svm = to_svm(vcpu);
1291         int i;
1292
1293         if (unlikely(cpu != vcpu->cpu)) {
1294                 svm->asid_generation = 0;
1295                 mark_all_dirty(svm->vmcb);
1296         }
1297
1298 #ifdef CONFIG_X86_64
1299         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1300 #endif
1301         savesegment(fs, svm->host.fs);
1302         savesegment(gs, svm->host.gs);
1303         svm->host.ldt = kvm_read_ldt();
1304
1305         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1306                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1307
1308         if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1309             svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1310                 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1311                 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1312         }
1313 }
1314
1315 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1316 {
1317         struct vcpu_svm *svm = to_svm(vcpu);
1318         int i;
1319
1320         ++vcpu->stat.host_state_reload;
1321         kvm_load_ldt(svm->host.ldt);
1322 #ifdef CONFIG_X86_64
1323         loadsegment(fs, svm->host.fs);
1324         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1325         load_gs_index(svm->host.gs);
1326 #else
1327 #ifdef CONFIG_X86_32_LAZY_GS
1328         loadsegment(gs, svm->host.gs);
1329 #endif
1330 #endif
1331         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1332                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1333 }
1334
1335 static void svm_update_cpl(struct kvm_vcpu *vcpu)
1336 {
1337         struct vcpu_svm *svm = to_svm(vcpu);
1338         int cpl;
1339
1340         if (!is_protmode(vcpu))
1341                 cpl = 0;
1342         else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
1343                 cpl = 3;
1344         else
1345                 cpl = svm->vmcb->save.cs.selector & 0x3;
1346
1347         svm->vmcb->save.cpl = cpl;
1348 }
1349
1350 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1351 {
1352         return to_svm(vcpu)->vmcb->save.rflags;
1353 }
1354
1355 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1356 {
1357         unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
1358
1359         to_svm(vcpu)->vmcb->save.rflags = rflags;
1360         if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
1361                 svm_update_cpl(vcpu);
1362 }
1363
1364 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1365 {
1366         switch (reg) {
1367         case VCPU_EXREG_PDPTR:
1368                 BUG_ON(!npt_enabled);
1369                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1370                 break;
1371         default:
1372                 BUG();
1373         }
1374 }
1375
1376 static void svm_set_vintr(struct vcpu_svm *svm)
1377 {
1378         set_intercept(svm, INTERCEPT_VINTR);
1379 }
1380
1381 static void svm_clear_vintr(struct vcpu_svm *svm)
1382 {
1383         clr_intercept(svm, INTERCEPT_VINTR);
1384 }
1385
1386 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1387 {
1388         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1389
1390         switch (seg) {
1391         case VCPU_SREG_CS: return &save->cs;
1392         case VCPU_SREG_DS: return &save->ds;
1393         case VCPU_SREG_ES: return &save->es;
1394         case VCPU_SREG_FS: return &save->fs;
1395         case VCPU_SREG_GS: return &save->gs;
1396         case VCPU_SREG_SS: return &save->ss;
1397         case VCPU_SREG_TR: return &save->tr;
1398         case VCPU_SREG_LDTR: return &save->ldtr;
1399         }
1400         BUG();
1401         return NULL;
1402 }
1403
1404 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1405 {
1406         struct vmcb_seg *s = svm_seg(vcpu, seg);
1407
1408         return s->base;
1409 }
1410
1411 static void svm_get_segment(struct kvm_vcpu *vcpu,
1412                             struct kvm_segment *var, int seg)
1413 {
1414         struct vmcb_seg *s = svm_seg(vcpu, seg);
1415
1416         var->base = s->base;
1417         var->limit = s->limit;
1418         var->selector = s->selector;
1419         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1420         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1421         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1422         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1423         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1424         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1425         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1426         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1427
1428         /*
1429          * AMD's VMCB does not have an explicit unusable field, so emulate it
1430          * for cross vendor migration purposes by "not present"
1431          */
1432         var->unusable = !var->present || (var->type == 0);
1433
1434         switch (seg) {
1435         case VCPU_SREG_CS:
1436                 /*
1437                  * SVM always stores 0 for the 'G' bit in the CS selector in
1438                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1439                  * Intel's VMENTRY has a check on the 'G' bit.
1440                  */
1441                 var->g = s->limit > 0xfffff;
1442                 break;
1443         case VCPU_SREG_TR:
1444                 /*
1445                  * Work around a bug where the busy flag in the tr selector
1446                  * isn't exposed
1447                  */
1448                 var->type |= 0x2;
1449                 break;
1450         case VCPU_SREG_DS:
1451         case VCPU_SREG_ES:
1452         case VCPU_SREG_FS:
1453         case VCPU_SREG_GS:
1454                 /*
1455                  * The accessed bit must always be set in the segment
1456                  * descriptor cache, although it can be cleared in the
1457                  * descriptor, the cached bit always remains at 1. Since
1458                  * Intel has a check on this, set it here to support
1459                  * cross-vendor migration.
1460                  */
1461                 if (!var->unusable)
1462                         var->type |= 0x1;
1463                 break;
1464         case VCPU_SREG_SS:
1465                 /*
1466                  * On AMD CPUs sometimes the DB bit in the segment
1467                  * descriptor is left as 1, although the whole segment has
1468                  * been made unusable. Clear it here to pass an Intel VMX
1469                  * entry check when cross vendor migrating.
1470                  */
1471                 if (var->unusable)
1472                         var->db = 0;
1473                 break;
1474         }
1475 }
1476
1477 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1478 {
1479         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1480
1481         return save->cpl;
1482 }
1483
1484 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1485 {
1486         struct vcpu_svm *svm = to_svm(vcpu);
1487
1488         dt->size = svm->vmcb->save.idtr.limit;
1489         dt->address = svm->vmcb->save.idtr.base;
1490 }
1491
1492 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1493 {
1494         struct vcpu_svm *svm = to_svm(vcpu);
1495
1496         svm->vmcb->save.idtr.limit = dt->size;
1497         svm->vmcb->save.idtr.base = dt->address ;
1498         mark_dirty(svm->vmcb, VMCB_DT);
1499 }
1500
1501 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1502 {
1503         struct vcpu_svm *svm = to_svm(vcpu);
1504
1505         dt->size = svm->vmcb->save.gdtr.limit;
1506         dt->address = svm->vmcb->save.gdtr.base;
1507 }
1508
1509 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1510 {
1511         struct vcpu_svm *svm = to_svm(vcpu);
1512
1513         svm->vmcb->save.gdtr.limit = dt->size;
1514         svm->vmcb->save.gdtr.base = dt->address ;
1515         mark_dirty(svm->vmcb, VMCB_DT);
1516 }
1517
1518 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1519 {
1520 }
1521
1522 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1523 {
1524 }
1525
1526 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1527 {
1528 }
1529
1530 static void update_cr0_intercept(struct vcpu_svm *svm)
1531 {
1532         ulong gcr0 = svm->vcpu.arch.cr0;
1533         u64 *hcr0 = &svm->vmcb->save.cr0;
1534
1535         if (!svm->vcpu.fpu_active)
1536                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1537         else
1538                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1539                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1540
1541         mark_dirty(svm->vmcb, VMCB_CR);
1542
1543         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1544                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1545                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1546         } else {
1547                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1548                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1549         }
1550 }
1551
1552 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1553 {
1554         struct vcpu_svm *svm = to_svm(vcpu);
1555
1556 #ifdef CONFIG_X86_64
1557         if (vcpu->arch.efer & EFER_LME) {
1558                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1559                         vcpu->arch.efer |= EFER_LMA;
1560                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1561                 }
1562
1563                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1564                         vcpu->arch.efer &= ~EFER_LMA;
1565                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1566                 }
1567         }
1568 #endif
1569         vcpu->arch.cr0 = cr0;
1570
1571         if (!npt_enabled)
1572                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1573
1574         if (!vcpu->fpu_active)
1575                 cr0 |= X86_CR0_TS;
1576         /*
1577          * re-enable caching here because the QEMU bios
1578          * does not do it - this results in some delay at
1579          * reboot
1580          */
1581         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1582         svm->vmcb->save.cr0 = cr0;
1583         mark_dirty(svm->vmcb, VMCB_CR);
1584         update_cr0_intercept(svm);
1585 }
1586
1587 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1588 {
1589         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1590         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1591
1592         if (cr4 & X86_CR4_VMXE)
1593                 return 1;
1594
1595         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1596                 svm_flush_tlb(vcpu);
1597
1598         vcpu->arch.cr4 = cr4;
1599         if (!npt_enabled)
1600                 cr4 |= X86_CR4_PAE;
1601         cr4 |= host_cr4_mce;
1602         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1603         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1604         return 0;
1605 }
1606
1607 static void svm_set_segment(struct kvm_vcpu *vcpu,
1608                             struct kvm_segment *var, int seg)
1609 {
1610         struct vcpu_svm *svm = to_svm(vcpu);
1611         struct vmcb_seg *s = svm_seg(vcpu, seg);
1612
1613         s->base = var->base;
1614         s->limit = var->limit;
1615         s->selector = var->selector;
1616         if (var->unusable)
1617                 s->attrib = 0;
1618         else {
1619                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1620                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1621                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1622                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1623                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1624                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1625                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1626                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1627         }
1628         if (seg == VCPU_SREG_CS)
1629                 svm_update_cpl(vcpu);
1630
1631         mark_dirty(svm->vmcb, VMCB_SEG);
1632 }
1633
1634 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1635 {
1636         struct vcpu_svm *svm = to_svm(vcpu);
1637
1638         clr_exception_intercept(svm, DB_VECTOR);
1639         clr_exception_intercept(svm, BP_VECTOR);
1640
1641         if (svm->nmi_singlestep)
1642                 set_exception_intercept(svm, DB_VECTOR);
1643
1644         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1645                 if (vcpu->guest_debug &
1646                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1647                         set_exception_intercept(svm, DB_VECTOR);
1648                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1649                         set_exception_intercept(svm, BP_VECTOR);
1650         } else
1651                 vcpu->guest_debug = 0;
1652 }
1653
1654 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1655 {
1656         if (sd->next_asid > sd->max_asid) {
1657                 ++sd->asid_generation;
1658                 sd->next_asid = 1;
1659                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1660         }
1661
1662         svm->asid_generation = sd->asid_generation;
1663         svm->vmcb->control.asid = sd->next_asid++;
1664
1665         mark_dirty(svm->vmcb, VMCB_ASID);
1666 }
1667
1668 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1669 {
1670         struct vcpu_svm *svm = to_svm(vcpu);
1671
1672         svm->vmcb->save.dr7 = value;
1673         mark_dirty(svm->vmcb, VMCB_DR);
1674 }
1675
1676 static int pf_interception(struct vcpu_svm *svm)
1677 {
1678         u64 fault_address = svm->vmcb->control.exit_info_2;
1679         u32 error_code;
1680         int r = 1;
1681
1682         switch (svm->apf_reason) {
1683         default:
1684                 error_code = svm->vmcb->control.exit_info_1;
1685
1686                 trace_kvm_page_fault(fault_address, error_code);
1687                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1688                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1689                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1690                         svm->vmcb->control.insn_bytes,
1691                         svm->vmcb->control.insn_len);
1692                 break;
1693         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1694                 svm->apf_reason = 0;
1695                 local_irq_disable();
1696                 kvm_async_pf_task_wait(fault_address);
1697                 local_irq_enable();
1698                 break;
1699         case KVM_PV_REASON_PAGE_READY:
1700                 svm->apf_reason = 0;
1701                 local_irq_disable();
1702                 kvm_async_pf_task_wake(fault_address);
1703                 local_irq_enable();
1704                 break;
1705         }
1706         return r;
1707 }
1708
1709 static int db_interception(struct vcpu_svm *svm)
1710 {
1711         struct kvm_run *kvm_run = svm->vcpu.run;
1712
1713         if (!(svm->vcpu.guest_debug &
1714               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1715                 !svm->nmi_singlestep) {
1716                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1717                 return 1;
1718         }
1719
1720         if (svm->nmi_singlestep) {
1721                 svm->nmi_singlestep = false;
1722                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1723                         svm->vmcb->save.rflags &=
1724                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1725                 update_db_bp_intercept(&svm->vcpu);
1726         }
1727
1728         if (svm->vcpu.guest_debug &
1729             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1730                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1731                 kvm_run->debug.arch.pc =
1732                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1733                 kvm_run->debug.arch.exception = DB_VECTOR;
1734                 return 0;
1735         }
1736
1737         return 1;
1738 }
1739
1740 static int bp_interception(struct vcpu_svm *svm)
1741 {
1742         struct kvm_run *kvm_run = svm->vcpu.run;
1743
1744         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1745         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1746         kvm_run->debug.arch.exception = BP_VECTOR;
1747         return 0;
1748 }
1749
1750 static int ud_interception(struct vcpu_svm *svm)
1751 {
1752         int er;
1753
1754         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1755         if (er != EMULATE_DONE)
1756                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1757         return 1;
1758 }
1759
1760 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1761 {
1762         struct vcpu_svm *svm = to_svm(vcpu);
1763
1764         clr_exception_intercept(svm, NM_VECTOR);
1765
1766         svm->vcpu.fpu_active = 1;
1767         update_cr0_intercept(svm);
1768 }
1769
1770 static int nm_interception(struct vcpu_svm *svm)
1771 {
1772         svm_fpu_activate(&svm->vcpu);
1773         return 1;
1774 }
1775
1776 static bool is_erratum_383(void)
1777 {
1778         int err, i;
1779         u64 value;
1780
1781         if (!erratum_383_found)
1782                 return false;
1783
1784         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1785         if (err)
1786                 return false;
1787
1788         /* Bit 62 may or may not be set for this mce */
1789         value &= ~(1ULL << 62);
1790
1791         if (value != 0xb600000000010015ULL)
1792                 return false;
1793
1794         /* Clear MCi_STATUS registers */
1795         for (i = 0; i < 6; ++i)
1796                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1797
1798         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1799         if (!err) {
1800                 u32 low, high;
1801
1802                 value &= ~(1ULL << 2);
1803                 low    = lower_32_bits(value);
1804                 high   = upper_32_bits(value);
1805
1806                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1807         }
1808
1809         /* Flush tlb to evict multi-match entries */
1810         __flush_tlb_all();
1811
1812         return true;
1813 }
1814
1815 static void svm_handle_mce(struct vcpu_svm *svm)
1816 {
1817         if (is_erratum_383()) {
1818                 /*
1819                  * Erratum 383 triggered. Guest state is corrupt so kill the
1820                  * guest.
1821                  */
1822                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1823
1824                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1825
1826                 return;
1827         }
1828
1829         /*
1830          * On an #MC intercept the MCE handler is not called automatically in
1831          * the host. So do it by hand here.
1832          */
1833         asm volatile (
1834                 "int $0x12\n");
1835         /* not sure if we ever come back to this point */
1836
1837         return;
1838 }
1839
1840 static int mc_interception(struct vcpu_svm *svm)
1841 {
1842         return 1;
1843 }
1844
1845 static int shutdown_interception(struct vcpu_svm *svm)
1846 {
1847         struct kvm_run *kvm_run = svm->vcpu.run;
1848
1849         /*
1850          * VMCB is undefined after a SHUTDOWN intercept
1851          * so reinitialize it.
1852          */
1853         clear_page(svm->vmcb);
1854         init_vmcb(svm);
1855
1856         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1857         return 0;
1858 }
1859
1860 static int io_interception(struct vcpu_svm *svm)
1861 {
1862         struct kvm_vcpu *vcpu = &svm->vcpu;
1863         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1864         int size, in, string;
1865         unsigned port;
1866
1867         ++svm->vcpu.stat.io_exits;
1868         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1869         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1870         if (string || in)
1871                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1872
1873         port = io_info >> 16;
1874         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1875         svm->next_rip = svm->vmcb->control.exit_info_2;
1876         skip_emulated_instruction(&svm->vcpu);
1877
1878         return kvm_fast_pio_out(vcpu, size, port);
1879 }
1880
1881 static int nmi_interception(struct vcpu_svm *svm)
1882 {
1883         return 1;
1884 }
1885
1886 static int intr_interception(struct vcpu_svm *svm)
1887 {
1888         ++svm->vcpu.stat.irq_exits;
1889         return 1;
1890 }
1891
1892 static int nop_on_interception(struct vcpu_svm *svm)
1893 {
1894         return 1;
1895 }
1896
1897 static int halt_interception(struct vcpu_svm *svm)
1898 {
1899         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1900         skip_emulated_instruction(&svm->vcpu);
1901         return kvm_emulate_halt(&svm->vcpu);
1902 }
1903
1904 static int vmmcall_interception(struct vcpu_svm *svm)
1905 {
1906         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1907         skip_emulated_instruction(&svm->vcpu);
1908         kvm_emulate_hypercall(&svm->vcpu);
1909         return 1;
1910 }
1911
1912 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1913 {
1914         struct vcpu_svm *svm = to_svm(vcpu);
1915
1916         return svm->nested.nested_cr3;
1917 }
1918
1919 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1920 {
1921         struct vcpu_svm *svm = to_svm(vcpu);
1922         u64 cr3 = svm->nested.nested_cr3;
1923         u64 pdpte;
1924         int ret;
1925
1926         ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1927                                   offset_in_page(cr3) + index * 8, 8);
1928         if (ret)
1929                 return 0;
1930         return pdpte;
1931 }
1932
1933 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1934                                    unsigned long root)
1935 {
1936         struct vcpu_svm *svm = to_svm(vcpu);
1937
1938         svm->vmcb->control.nested_cr3 = root;
1939         mark_dirty(svm->vmcb, VMCB_NPT);
1940         svm_flush_tlb(vcpu);
1941 }
1942
1943 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1944                                        struct x86_exception *fault)
1945 {
1946         struct vcpu_svm *svm = to_svm(vcpu);
1947
1948         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1949         svm->vmcb->control.exit_code_hi = 0;
1950         svm->vmcb->control.exit_info_1 = fault->error_code;
1951         svm->vmcb->control.exit_info_2 = fault->address;
1952
1953         nested_svm_vmexit(svm);
1954 }
1955
1956 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1957 {
1958         int r;
1959
1960         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1961
1962         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1963         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1964         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
1965         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1966         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1967         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1968
1969         return r;
1970 }
1971
1972 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1973 {
1974         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1975 }
1976
1977 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1978 {
1979         if (!(svm->vcpu.arch.efer & EFER_SVME)
1980             || !is_paging(&svm->vcpu)) {
1981                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1982                 return 1;
1983         }
1984
1985         if (svm->vmcb->save.cpl) {
1986                 kvm_inject_gp(&svm->vcpu, 0);
1987                 return 1;
1988         }
1989
1990        return 0;
1991 }
1992
1993 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1994                                       bool has_error_code, u32 error_code)
1995 {
1996         int vmexit;
1997
1998         if (!is_guest_mode(&svm->vcpu))
1999                 return 0;
2000
2001         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2002         svm->vmcb->control.exit_code_hi = 0;
2003         svm->vmcb->control.exit_info_1 = error_code;
2004         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2005
2006         vmexit = nested_svm_intercept(svm);
2007         if (vmexit == NESTED_EXIT_DONE)
2008                 svm->nested.exit_required = true;
2009
2010         return vmexit;
2011 }
2012
2013 /* This function returns true if it is save to enable the irq window */
2014 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2015 {
2016         if (!is_guest_mode(&svm->vcpu))
2017                 return true;
2018
2019         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2020                 return true;
2021
2022         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2023                 return false;
2024
2025         /*
2026          * if vmexit was already requested (by intercepted exception
2027          * for instance) do not overwrite it with "external interrupt"
2028          * vmexit.
2029          */
2030         if (svm->nested.exit_required)
2031                 return false;
2032
2033         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2034         svm->vmcb->control.exit_info_1 = 0;
2035         svm->vmcb->control.exit_info_2 = 0;
2036
2037         if (svm->nested.intercept & 1ULL) {
2038                 /*
2039                  * The #vmexit can't be emulated here directly because this
2040                  * code path runs with irqs and preemption disabled. A
2041                  * #vmexit emulation might sleep. Only signal request for
2042                  * the #vmexit here.
2043                  */
2044                 svm->nested.exit_required = true;
2045                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2046                 return false;
2047         }
2048
2049         return true;
2050 }
2051
2052 /* This function returns true if it is save to enable the nmi window */
2053 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2054 {
2055         if (!is_guest_mode(&svm->vcpu))
2056                 return true;
2057
2058         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2059                 return true;
2060
2061         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2062         svm->nested.exit_required = true;
2063
2064         return false;
2065 }
2066
2067 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2068 {
2069         struct page *page;
2070
2071         might_sleep();
2072
2073         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2074         if (is_error_page(page))
2075                 goto error;
2076
2077         *_page = page;
2078
2079         return kmap(page);
2080
2081 error:
2082         kvm_inject_gp(&svm->vcpu, 0);
2083
2084         return NULL;
2085 }
2086
2087 static void nested_svm_unmap(struct page *page)
2088 {
2089         kunmap(page);
2090         kvm_release_page_dirty(page);
2091 }
2092
2093 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2094 {
2095         unsigned port;
2096         u8 val, bit;
2097         u64 gpa;
2098
2099         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2100                 return NESTED_EXIT_HOST;
2101
2102         port = svm->vmcb->control.exit_info_1 >> 16;
2103         gpa  = svm->nested.vmcb_iopm + (port / 8);
2104         bit  = port % 8;
2105         val  = 0;
2106
2107         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2108                 val &= (1 << bit);
2109
2110         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2111 }
2112
2113 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2114 {
2115         u32 offset, msr, value;
2116         int write, mask;
2117
2118         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2119                 return NESTED_EXIT_HOST;
2120
2121         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2122         offset = svm_msrpm_offset(msr);
2123         write  = svm->vmcb->control.exit_info_1 & 1;
2124         mask   = 1 << ((2 * (msr & 0xf)) + write);
2125
2126         if (offset == MSR_INVALID)
2127                 return NESTED_EXIT_DONE;
2128
2129         /* Offset is in 32 bit units but need in 8 bit units */
2130         offset *= 4;
2131
2132         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2133                 return NESTED_EXIT_DONE;
2134
2135         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2136 }
2137
2138 static int nested_svm_exit_special(struct vcpu_svm *svm)
2139 {
2140         u32 exit_code = svm->vmcb->control.exit_code;
2141
2142         switch (exit_code) {
2143         case SVM_EXIT_INTR:
2144         case SVM_EXIT_NMI:
2145         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2146                 return NESTED_EXIT_HOST;
2147         case SVM_EXIT_NPF:
2148                 /* For now we are always handling NPFs when using them */
2149                 if (npt_enabled)
2150                         return NESTED_EXIT_HOST;
2151                 break;
2152         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2153                 /* When we're shadowing, trap PFs, but not async PF */
2154                 if (!npt_enabled && svm->apf_reason == 0)
2155                         return NESTED_EXIT_HOST;
2156                 break;
2157         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2158                 nm_interception(svm);
2159                 break;
2160         default:
2161                 break;
2162         }
2163
2164         return NESTED_EXIT_CONTINUE;
2165 }
2166
2167 /*
2168  * If this function returns true, this #vmexit was already handled
2169  */
2170 static int nested_svm_intercept(struct vcpu_svm *svm)
2171 {
2172         u32 exit_code = svm->vmcb->control.exit_code;
2173         int vmexit = NESTED_EXIT_HOST;
2174
2175         switch (exit_code) {
2176         case SVM_EXIT_MSR:
2177                 vmexit = nested_svm_exit_handled_msr(svm);
2178                 break;
2179         case SVM_EXIT_IOIO:
2180                 vmexit = nested_svm_intercept_ioio(svm);
2181                 break;
2182         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2183                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2184                 if (svm->nested.intercept_cr & bit)
2185                         vmexit = NESTED_EXIT_DONE;
2186                 break;
2187         }
2188         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2189                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2190                 if (svm->nested.intercept_dr & bit)
2191                         vmexit = NESTED_EXIT_DONE;
2192                 break;
2193         }
2194         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2195                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2196                 if (svm->nested.intercept_exceptions & excp_bits)
2197                         vmexit = NESTED_EXIT_DONE;
2198                 /* async page fault always cause vmexit */
2199                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2200                          svm->apf_reason != 0)
2201                         vmexit = NESTED_EXIT_DONE;
2202                 break;
2203         }
2204         case SVM_EXIT_ERR: {
2205                 vmexit = NESTED_EXIT_DONE;
2206                 break;
2207         }
2208         default: {
2209                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2210                 if (svm->nested.intercept & exit_bits)
2211                         vmexit = NESTED_EXIT_DONE;
2212         }
2213         }
2214
2215         return vmexit;
2216 }
2217
2218 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2219 {
2220         int vmexit;
2221
2222         vmexit = nested_svm_intercept(svm);
2223
2224         if (vmexit == NESTED_EXIT_DONE)
2225                 nested_svm_vmexit(svm);
2226
2227         return vmexit;
2228 }
2229
2230 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2231 {
2232         struct vmcb_control_area *dst  = &dst_vmcb->control;
2233         struct vmcb_control_area *from = &from_vmcb->control;
2234
2235         dst->intercept_cr         = from->intercept_cr;
2236         dst->intercept_dr         = from->intercept_dr;
2237         dst->intercept_exceptions = from->intercept_exceptions;
2238         dst->intercept            = from->intercept;
2239         dst->iopm_base_pa         = from->iopm_base_pa;
2240         dst->msrpm_base_pa        = from->msrpm_base_pa;
2241         dst->tsc_offset           = from->tsc_offset;
2242         dst->asid                 = from->asid;
2243         dst->tlb_ctl              = from->tlb_ctl;
2244         dst->int_ctl              = from->int_ctl;
2245         dst->int_vector           = from->int_vector;
2246         dst->int_state            = from->int_state;
2247         dst->exit_code            = from->exit_code;
2248         dst->exit_code_hi         = from->exit_code_hi;
2249         dst->exit_info_1          = from->exit_info_1;
2250         dst->exit_info_2          = from->exit_info_2;
2251         dst->exit_int_info        = from->exit_int_info;
2252         dst->exit_int_info_err    = from->exit_int_info_err;
2253         dst->nested_ctl           = from->nested_ctl;
2254         dst->event_inj            = from->event_inj;
2255         dst->event_inj_err        = from->event_inj_err;
2256         dst->nested_cr3           = from->nested_cr3;
2257         dst->lbr_ctl              = from->lbr_ctl;
2258 }
2259
2260 static int nested_svm_vmexit(struct vcpu_svm *svm)
2261 {
2262         struct vmcb *nested_vmcb;
2263         struct vmcb *hsave = svm->nested.hsave;
2264         struct vmcb *vmcb = svm->vmcb;
2265         struct page *page;
2266
2267         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2268                                        vmcb->control.exit_info_1,
2269                                        vmcb->control.exit_info_2,
2270                                        vmcb->control.exit_int_info,
2271                                        vmcb->control.exit_int_info_err,
2272                                        KVM_ISA_SVM);
2273
2274         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2275         if (!nested_vmcb)
2276                 return 1;
2277
2278         /* Exit Guest-Mode */
2279         leave_guest_mode(&svm->vcpu);
2280         svm->nested.vmcb = 0;
2281
2282         /* Give the current vmcb to the guest */
2283         disable_gif(svm);
2284
2285         nested_vmcb->save.es     = vmcb->save.es;
2286         nested_vmcb->save.cs     = vmcb->save.cs;
2287         nested_vmcb->save.ss     = vmcb->save.ss;
2288         nested_vmcb->save.ds     = vmcb->save.ds;
2289         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2290         nested_vmcb->save.idtr   = vmcb->save.idtr;
2291         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2292         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2293         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2294         nested_vmcb->save.cr2    = vmcb->save.cr2;
2295         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2296         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2297         nested_vmcb->save.rip    = vmcb->save.rip;
2298         nested_vmcb->save.rsp    = vmcb->save.rsp;
2299         nested_vmcb->save.rax    = vmcb->save.rax;
2300         nested_vmcb->save.dr7    = vmcb->save.dr7;
2301         nested_vmcb->save.dr6    = vmcb->save.dr6;
2302         nested_vmcb->save.cpl    = vmcb->save.cpl;
2303
2304         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2305         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2306         nested_vmcb->control.int_state         = vmcb->control.int_state;
2307         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2308         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2309         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2310         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2311         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2312         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2313         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2314
2315         /*
2316          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2317          * to make sure that we do not lose injected events. So check event_inj
2318          * here and copy it to exit_int_info if it is valid.
2319          * Exit_int_info and event_inj can't be both valid because the case
2320          * below only happens on a VMRUN instruction intercept which has
2321          * no valid exit_int_info set.
2322          */
2323         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2324                 struct vmcb_control_area *nc = &nested_vmcb->control;
2325
2326                 nc->exit_int_info     = vmcb->control.event_inj;
2327                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2328         }
2329
2330         nested_vmcb->control.tlb_ctl           = 0;
2331         nested_vmcb->control.event_inj         = 0;
2332         nested_vmcb->control.event_inj_err     = 0;
2333
2334         /* We always set V_INTR_MASKING and remember the old value in hflags */
2335         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2336                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2337
2338         /* Restore the original control entries */
2339         copy_vmcb_control_area(vmcb, hsave);
2340
2341         kvm_clear_exception_queue(&svm->vcpu);
2342         kvm_clear_interrupt_queue(&svm->vcpu);
2343
2344         svm->nested.nested_cr3 = 0;
2345
2346         /* Restore selected save entries */
2347         svm->vmcb->save.es = hsave->save.es;
2348         svm->vmcb->save.cs = hsave->save.cs;
2349         svm->vmcb->save.ss = hsave->save.ss;
2350         svm->vmcb->save.ds = hsave->save.ds;
2351         svm->vmcb->save.gdtr = hsave->save.gdtr;
2352         svm->vmcb->save.idtr = hsave->save.idtr;
2353         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2354         svm_set_efer(&svm->vcpu, hsave->save.efer);
2355         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2356         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2357         if (npt_enabled) {
2358                 svm->vmcb->save.cr3 = hsave->save.cr3;
2359                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2360         } else {
2361                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2362         }
2363         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2364         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2365         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2366         svm->vmcb->save.dr7 = 0;
2367         svm->vmcb->save.cpl = 0;
2368         svm->vmcb->control.exit_int_info = 0;
2369
2370         mark_all_dirty(svm->vmcb);
2371
2372         nested_svm_unmap(page);
2373
2374         nested_svm_uninit_mmu_context(&svm->vcpu);
2375         kvm_mmu_reset_context(&svm->vcpu);
2376         kvm_mmu_load(&svm->vcpu);
2377
2378         return 0;
2379 }
2380
2381 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2382 {
2383         /*
2384          * This function merges the msr permission bitmaps of kvm and the
2385          * nested vmcb. It is optimized in that it only merges the parts where
2386          * the kvm msr permission bitmap may contain zero bits
2387          */
2388         int i;
2389
2390         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2391                 return true;
2392
2393         for (i = 0; i < MSRPM_OFFSETS; i++) {
2394                 u32 value, p;
2395                 u64 offset;
2396
2397                 if (msrpm_offsets[i] == 0xffffffff)
2398                         break;
2399
2400                 p      = msrpm_offsets[i];
2401                 offset = svm->nested.vmcb_msrpm + (p * 4);
2402
2403                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2404                         return false;
2405
2406                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2407         }
2408
2409         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2410
2411         return true;
2412 }
2413
2414 static bool nested_vmcb_checks(struct vmcb *vmcb)
2415 {
2416         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2417                 return false;
2418
2419         if (vmcb->control.asid == 0)
2420                 return false;
2421
2422         if (vmcb->control.nested_ctl && !npt_enabled)
2423                 return false;
2424
2425         return true;
2426 }
2427
2428 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2429 {
2430         struct vmcb *nested_vmcb;
2431         struct vmcb *hsave = svm->nested.hsave;
2432         struct vmcb *vmcb = svm->vmcb;
2433         struct page *page;
2434         u64 vmcb_gpa;
2435
2436         vmcb_gpa = svm->vmcb->save.rax;
2437
2438         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2439         if (!nested_vmcb)
2440                 return false;
2441
2442         if (!nested_vmcb_checks(nested_vmcb)) {
2443                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2444                 nested_vmcb->control.exit_code_hi = 0;
2445                 nested_vmcb->control.exit_info_1  = 0;
2446                 nested_vmcb->control.exit_info_2  = 0;
2447
2448                 nested_svm_unmap(page);
2449
2450                 return false;
2451         }
2452
2453         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2454                                nested_vmcb->save.rip,
2455                                nested_vmcb->control.int_ctl,
2456                                nested_vmcb->control.event_inj,
2457                                nested_vmcb->control.nested_ctl);
2458
2459         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2460                                     nested_vmcb->control.intercept_cr >> 16,
2461                                     nested_vmcb->control.intercept_exceptions,
2462                                     nested_vmcb->control.intercept);
2463
2464         /* Clear internal status */
2465         kvm_clear_exception_queue(&svm->vcpu);
2466         kvm_clear_interrupt_queue(&svm->vcpu);
2467
2468         /*
2469          * Save the old vmcb, so we don't need to pick what we save, but can
2470          * restore everything when a VMEXIT occurs
2471          */
2472         hsave->save.es     = vmcb->save.es;
2473         hsave->save.cs     = vmcb->save.cs;
2474         hsave->save.ss     = vmcb->save.ss;
2475         hsave->save.ds     = vmcb->save.ds;
2476         hsave->save.gdtr   = vmcb->save.gdtr;
2477         hsave->save.idtr   = vmcb->save.idtr;
2478         hsave->save.efer   = svm->vcpu.arch.efer;
2479         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2480         hsave->save.cr4    = svm->vcpu.arch.cr4;
2481         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2482         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2483         hsave->save.rsp    = vmcb->save.rsp;
2484         hsave->save.rax    = vmcb->save.rax;
2485         if (npt_enabled)
2486                 hsave->save.cr3    = vmcb->save.cr3;
2487         else
2488                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2489
2490         copy_vmcb_control_area(hsave, vmcb);
2491
2492         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2493                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2494         else
2495                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2496
2497         if (nested_vmcb->control.nested_ctl) {
2498                 kvm_mmu_unload(&svm->vcpu);
2499                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2500                 nested_svm_init_mmu_context(&svm->vcpu);
2501         }
2502
2503         /* Load the nested guest state */
2504         svm->vmcb->save.es = nested_vmcb->save.es;
2505         svm->vmcb->save.cs = nested_vmcb->save.cs;
2506         svm->vmcb->save.ss = nested_vmcb->save.ss;
2507         svm->vmcb->save.ds = nested_vmcb->save.ds;
2508         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2509         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2510         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2511         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2512         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2513         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2514         if (npt_enabled) {
2515                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2516                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2517         } else
2518                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2519
2520         /* Guest paging mode is active - reset mmu */
2521         kvm_mmu_reset_context(&svm->vcpu);
2522
2523         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2524         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2525         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2526         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2527
2528         /* In case we don't even reach vcpu_run, the fields are not updated */
2529         svm->vmcb->save.rax = nested_vmcb->save.rax;
2530         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2531         svm->vmcb->save.rip = nested_vmcb->save.rip;
2532         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2533         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2534         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2535
2536         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2537         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2538
2539         /* cache intercepts */
2540         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2541         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2542         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2543         svm->nested.intercept            = nested_vmcb->control.intercept;
2544
2545         svm_flush_tlb(&svm->vcpu);
2546         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2547         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2548                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2549         else
2550                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2551
2552         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2553                 /* We only want the cr8 intercept bits of the guest */
2554                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2555                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2556         }
2557
2558         /* We don't want to see VMMCALLs from a nested guest */
2559         clr_intercept(svm, INTERCEPT_VMMCALL);
2560
2561         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2562         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2563         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2564         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2565         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2566         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2567
2568         nested_svm_unmap(page);
2569
2570         /* Enter Guest-Mode */
2571         enter_guest_mode(&svm->vcpu);
2572
2573         /*
2574          * Merge guest and host intercepts - must be called  with vcpu in
2575          * guest-mode to take affect here
2576          */
2577         recalc_intercepts(svm);
2578
2579         svm->nested.vmcb = vmcb_gpa;
2580
2581         enable_gif(svm);
2582
2583         mark_all_dirty(svm->vmcb);
2584
2585         return true;
2586 }
2587
2588 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2589 {
2590         to_vmcb->save.fs = from_vmcb->save.fs;
2591         to_vmcb->save.gs = from_vmcb->save.gs;
2592         to_vmcb->save.tr = from_vmcb->save.tr;
2593         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2594         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2595         to_vmcb->save.star = from_vmcb->save.star;
2596         to_vmcb->save.lstar = from_vmcb->save.lstar;
2597         to_vmcb->save.cstar = from_vmcb->save.cstar;
2598         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2599         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2600         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2601         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2602 }
2603
2604 static int vmload_interception(struct vcpu_svm *svm)
2605 {
2606         struct vmcb *nested_vmcb;
2607         struct page *page;
2608
2609         if (nested_svm_check_permissions(svm))
2610                 return 1;
2611
2612         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2613         if (!nested_vmcb)
2614                 return 1;
2615
2616         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2617         skip_emulated_instruction(&svm->vcpu);
2618
2619         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2620         nested_svm_unmap(page);
2621
2622         return 1;
2623 }
2624
2625 static int vmsave_interception(struct vcpu_svm *svm)
2626 {
2627         struct vmcb *nested_vmcb;
2628         struct page *page;
2629
2630         if (nested_svm_check_permissions(svm))
2631                 return 1;
2632
2633         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2634         if (!nested_vmcb)
2635                 return 1;
2636
2637         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2638         skip_emulated_instruction(&svm->vcpu);
2639
2640         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2641         nested_svm_unmap(page);
2642
2643         return 1;
2644 }
2645
2646 static int vmrun_interception(struct vcpu_svm *svm)
2647 {
2648         if (nested_svm_check_permissions(svm))
2649                 return 1;
2650
2651         /* Save rip after vmrun instruction */
2652         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2653
2654         if (!nested_svm_vmrun(svm))
2655                 return 1;
2656
2657         if (!nested_svm_vmrun_msrpm(svm))
2658                 goto failed;
2659
2660         return 1;
2661
2662 failed:
2663
2664         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2665         svm->vmcb->control.exit_code_hi = 0;
2666         svm->vmcb->control.exit_info_1  = 0;
2667         svm->vmcb->control.exit_info_2  = 0;
2668
2669         nested_svm_vmexit(svm);
2670
2671         return 1;
2672 }
2673
2674 static int stgi_interception(struct vcpu_svm *svm)
2675 {
2676         if (nested_svm_check_permissions(svm))
2677                 return 1;
2678
2679         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2680         skip_emulated_instruction(&svm->vcpu);
2681         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2682
2683         enable_gif(svm);
2684
2685         return 1;
2686 }
2687
2688 static int clgi_interception(struct vcpu_svm *svm)
2689 {
2690         if (nested_svm_check_permissions(svm))
2691                 return 1;
2692
2693         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2694         skip_emulated_instruction(&svm->vcpu);
2695
2696         disable_gif(svm);
2697
2698         /* After a CLGI no interrupts should come */
2699         svm_clear_vintr(svm);
2700         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2701
2702         mark_dirty(svm->vmcb, VMCB_INTR);
2703
2704         return 1;
2705 }
2706
2707 static int invlpga_interception(struct vcpu_svm *svm)
2708 {
2709         struct kvm_vcpu *vcpu = &svm->vcpu;
2710
2711         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2712                           vcpu->arch.regs[VCPU_REGS_RAX]);
2713
2714         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2715         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2716
2717         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2718         skip_emulated_instruction(&svm->vcpu);
2719         return 1;
2720 }
2721
2722 static int skinit_interception(struct vcpu_svm *svm)
2723 {
2724         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2725
2726         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2727         return 1;
2728 }
2729
2730 static int xsetbv_interception(struct vcpu_svm *svm)
2731 {
2732         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2733         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2734
2735         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2736                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2737                 skip_emulated_instruction(&svm->vcpu);
2738         }
2739
2740         return 1;
2741 }
2742
2743 static int invalid_op_interception(struct vcpu_svm *svm)
2744 {
2745         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2746         return 1;
2747 }
2748
2749 static int task_switch_interception(struct vcpu_svm *svm)
2750 {
2751         u16 tss_selector;
2752         int reason;
2753         int int_type = svm->vmcb->control.exit_int_info &
2754                 SVM_EXITINTINFO_TYPE_MASK;
2755         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2756         uint32_t type =
2757                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2758         uint32_t idt_v =
2759                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2760         bool has_error_code = false;
2761         u32 error_code = 0;
2762
2763         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2764
2765         if (svm->vmcb->control.exit_info_2 &
2766             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2767                 reason = TASK_SWITCH_IRET;
2768         else if (svm->vmcb->control.exit_info_2 &
2769                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2770                 reason = TASK_SWITCH_JMP;
2771         else if (idt_v)
2772                 reason = TASK_SWITCH_GATE;
2773         else
2774                 reason = TASK_SWITCH_CALL;
2775
2776         if (reason == TASK_SWITCH_GATE) {
2777                 switch (type) {
2778                 case SVM_EXITINTINFO_TYPE_NMI:
2779                         svm->vcpu.arch.nmi_injected = false;
2780                         break;
2781                 case SVM_EXITINTINFO_TYPE_EXEPT:
2782                         if (svm->vmcb->control.exit_info_2 &
2783                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2784                                 has_error_code = true;
2785                                 error_code =
2786                                         (u32)svm->vmcb->control.exit_info_2;
2787                         }
2788                         kvm_clear_exception_queue(&svm->vcpu);
2789                         break;
2790                 case SVM_EXITINTINFO_TYPE_INTR:
2791                         kvm_clear_interrupt_queue(&svm->vcpu);
2792                         break;
2793                 default:
2794                         break;
2795                 }
2796         }
2797
2798         if (reason != TASK_SWITCH_GATE ||
2799             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2800             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2801              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2802                 skip_emulated_instruction(&svm->vcpu);
2803
2804         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2805                 int_vec = -1;
2806
2807         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2808                                 has_error_code, error_code) == EMULATE_FAIL) {
2809                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2810                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2811                 svm->vcpu.run->internal.ndata = 0;
2812                 return 0;
2813         }
2814         return 1;
2815 }
2816
2817 static int cpuid_interception(struct vcpu_svm *svm)
2818 {
2819         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2820         kvm_emulate_cpuid(&svm->vcpu);
2821         return 1;
2822 }
2823
2824 static int iret_interception(struct vcpu_svm *svm)
2825 {
2826         ++svm->vcpu.stat.nmi_window_exits;
2827         clr_intercept(svm, INTERCEPT_IRET);
2828         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2829         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2830         return 1;
2831 }
2832
2833 static int invlpg_interception(struct vcpu_svm *svm)
2834 {
2835         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2836                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2837
2838         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2839         skip_emulated_instruction(&svm->vcpu);
2840         return 1;
2841 }
2842
2843 static int emulate_on_interception(struct vcpu_svm *svm)
2844 {
2845         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2846 }
2847
2848 static int rdpmc_interception(struct vcpu_svm *svm)
2849 {
2850         int err;
2851
2852         if (!static_cpu_has(X86_FEATURE_NRIPS))
2853                 return emulate_on_interception(svm);
2854
2855         err = kvm_rdpmc(&svm->vcpu);
2856         kvm_complete_insn_gp(&svm->vcpu, err);
2857
2858         return 1;
2859 }
2860
2861 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2862 {
2863         unsigned long cr0 = svm->vcpu.arch.cr0;
2864         bool ret = false;
2865         u64 intercept;
2866
2867         intercept = svm->nested.intercept;
2868
2869         if (!is_guest_mode(&svm->vcpu) ||
2870             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2871                 return false;
2872
2873         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2874         val &= ~SVM_CR0_SELECTIVE_MASK;
2875
2876         if (cr0 ^ val) {
2877                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2878                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2879         }
2880
2881         return ret;
2882 }
2883
2884 #define CR_VALID (1ULL << 63)
2885
2886 static int cr_interception(struct vcpu_svm *svm)
2887 {
2888         int reg, cr;
2889         unsigned long val;
2890         int err;
2891
2892         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2893                 return emulate_on_interception(svm);
2894
2895         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2896                 return emulate_on_interception(svm);
2897
2898         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2899         cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2900
2901         err = 0;
2902         if (cr >= 16) { /* mov to cr */
2903                 cr -= 16;
2904                 val = kvm_register_read(&svm->vcpu, reg);
2905                 switch (cr) {
2906                 case 0:
2907                         if (!check_selective_cr0_intercepted(svm, val))
2908                                 err = kvm_set_cr0(&svm->vcpu, val);
2909                         else
2910                                 return 1;
2911
2912                         break;
2913                 case 3:
2914                         err = kvm_set_cr3(&svm->vcpu, val);
2915                         break;
2916                 case 4:
2917                         err = kvm_set_cr4(&svm->vcpu, val);
2918                         break;
2919                 case 8:
2920                         err = kvm_set_cr8(&svm->vcpu, val);
2921                         break;
2922                 default:
2923                         WARN(1, "unhandled write to CR%d", cr);
2924                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2925                         return 1;
2926                 }
2927         } else { /* mov from cr */
2928                 switch (cr) {
2929                 case 0:
2930                         val = kvm_read_cr0(&svm->vcpu);
2931                         break;
2932                 case 2:
2933                         val = svm->vcpu.arch.cr2;
2934                         break;
2935                 case 3:
2936                         val = kvm_read_cr3(&svm->vcpu);
2937                         break;
2938                 case 4:
2939                         val = kvm_read_cr4(&svm->vcpu);
2940                         break;
2941                 case 8:
2942                         val = kvm_get_cr8(&svm->vcpu);
2943                         break;
2944                 default:
2945                         WARN(1, "unhandled read from CR%d", cr);
2946                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2947                         return 1;
2948                 }
2949                 kvm_register_write(&svm->vcpu, reg, val);
2950         }
2951         kvm_complete_insn_gp(&svm->vcpu, err);
2952
2953         return 1;
2954 }
2955
2956 static int dr_interception(struct vcpu_svm *svm)
2957 {
2958         int reg, dr;
2959         unsigned long val;
2960         int err;
2961
2962         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2963                 return emulate_on_interception(svm);
2964
2965         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2966         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2967
2968         if (dr >= 16) { /* mov to DRn */
2969                 val = kvm_register_read(&svm->vcpu, reg);
2970                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2971         } else {
2972                 err = kvm_get_dr(&svm->vcpu, dr, &val);
2973                 if (!err)
2974                         kvm_register_write(&svm->vcpu, reg, val);
2975         }
2976
2977         skip_emulated_instruction(&svm->vcpu);
2978
2979         return 1;
2980 }
2981
2982 static int cr8_write_interception(struct vcpu_svm *svm)
2983 {
2984         struct kvm_run *kvm_run = svm->vcpu.run;
2985         int r;
2986
2987         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2988         /* instruction emulation calls kvm_set_cr8() */
2989         r = cr_interception(svm);
2990         if (irqchip_in_kernel(svm->vcpu.kvm))
2991                 return r;
2992         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2993                 return r;
2994         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2995         return 0;
2996 }
2997
2998 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2999 {
3000         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3001         return vmcb->control.tsc_offset +
3002                 svm_scale_tsc(vcpu, host_tsc);
3003 }
3004
3005 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3006 {
3007         struct vcpu_svm *svm = to_svm(vcpu);
3008
3009         switch (ecx) {
3010         case MSR_IA32_TSC: {
3011                 *data = svm->vmcb->control.tsc_offset +
3012                         svm_scale_tsc(vcpu, native_read_tsc());
3013
3014                 break;
3015         }
3016         case MSR_STAR:
3017                 *data = svm->vmcb->save.star;
3018                 break;
3019 #ifdef CONFIG_X86_64
3020         case MSR_LSTAR:
3021                 *data = svm->vmcb->save.lstar;
3022                 break;
3023         case MSR_CSTAR:
3024                 *data = svm->vmcb->save.cstar;
3025                 break;
3026         case MSR_KERNEL_GS_BASE:
3027                 *data = svm->vmcb->save.kernel_gs_base;
3028                 break;
3029         case MSR_SYSCALL_MASK:
3030                 *data = svm->vmcb->save.sfmask;
3031                 break;
3032 #endif
3033         case MSR_IA32_SYSENTER_CS:
3034                 *data = svm->vmcb->save.sysenter_cs;
3035                 break;
3036         case MSR_IA32_SYSENTER_EIP:
3037                 *data = svm->sysenter_eip;
3038                 break;
3039         case MSR_IA32_SYSENTER_ESP:
3040                 *data = svm->sysenter_esp;
3041                 break;
3042         /*
3043          * Nobody will change the following 5 values in the VMCB so we can
3044          * safely return them on rdmsr. They will always be 0 until LBRV is
3045          * implemented.
3046          */
3047         case MSR_IA32_DEBUGCTLMSR:
3048                 *data = svm->vmcb->save.dbgctl;
3049                 break;
3050         case MSR_IA32_LASTBRANCHFROMIP:
3051                 *data = svm->vmcb->save.br_from;
3052                 break;
3053         case MSR_IA32_LASTBRANCHTOIP:
3054                 *data = svm->vmcb->save.br_to;
3055                 break;
3056         case MSR_IA32_LASTINTFROMIP:
3057                 *data = svm->vmcb->save.last_excp_from;
3058                 break;
3059         case MSR_IA32_LASTINTTOIP:
3060                 *data = svm->vmcb->save.last_excp_to;
3061                 break;
3062         case MSR_VM_HSAVE_PA:
3063                 *data = svm->nested.hsave_msr;
3064                 break;
3065         case MSR_VM_CR:
3066                 *data = svm->nested.vm_cr_msr;
3067                 break;
3068         case MSR_IA32_UCODE_REV:
3069                 *data = 0x01000065;
3070                 break;
3071         default:
3072                 return kvm_get_msr_common(vcpu, ecx, data);
3073         }
3074         return 0;
3075 }
3076
3077 static int rdmsr_interception(struct vcpu_svm *svm)
3078 {
3079         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3080         u64 data;
3081
3082         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3083                 trace_kvm_msr_read_ex(ecx);
3084                 kvm_inject_gp(&svm->vcpu, 0);
3085         } else {
3086                 trace_kvm_msr_read(ecx, data);
3087
3088                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3089                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3090                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3091                 skip_emulated_instruction(&svm->vcpu);
3092         }
3093         return 1;
3094 }
3095
3096 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3097 {
3098         struct vcpu_svm *svm = to_svm(vcpu);
3099         int svm_dis, chg_mask;
3100
3101         if (data & ~SVM_VM_CR_VALID_MASK)
3102                 return 1;
3103
3104         chg_mask = SVM_VM_CR_VALID_MASK;
3105
3106         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3107                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3108
3109         svm->nested.vm_cr_msr &= ~chg_mask;
3110         svm->nested.vm_cr_msr |= (data & chg_mask);
3111
3112         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3113
3114         /* check for svm_disable while efer.svme is set */
3115         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3116                 return 1;
3117
3118         return 0;
3119 }
3120
3121 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3122 {
3123         struct vcpu_svm *svm = to_svm(vcpu);
3124
3125         u32 ecx = msr->index;
3126         u64 data = msr->data;
3127         switch (ecx) {
3128         case MSR_IA32_TSC:
3129                 kvm_write_tsc(vcpu, msr);
3130                 break;
3131         case MSR_STAR:
3132                 svm->vmcb->save.star = data;
3133                 break;
3134 #ifdef CONFIG_X86_64
3135         case MSR_LSTAR:
3136                 svm->vmcb->save.lstar = data;
3137                 break;
3138         case MSR_CSTAR:
3139                 svm->vmcb->save.cstar = data;
3140                 break;
3141         case MSR_KERNEL_GS_BASE:
3142                 svm->vmcb->save.kernel_gs_base = data;
3143                 break;
3144         case MSR_SYSCALL_MASK:
3145                 svm->vmcb->save.sfmask = data;
3146                 break;
3147 #endif
3148         case MSR_IA32_SYSENTER_CS:
3149                 svm->vmcb->save.sysenter_cs = data;
3150                 break;
3151         case MSR_IA32_SYSENTER_EIP:
3152                 svm->sysenter_eip = data;
3153                 svm->vmcb->save.sysenter_eip = data;
3154                 break;
3155         case MSR_IA32_SYSENTER_ESP:
3156                 svm->sysenter_esp = data;
3157                 svm->vmcb->save.sysenter_esp = data;
3158                 break;
3159         case MSR_IA32_DEBUGCTLMSR:
3160                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3161                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3162                                     __func__, data);
3163                         break;
3164                 }
3165                 if (data & DEBUGCTL_RESERVED_BITS)
3166                         return 1;
3167
3168                 svm->vmcb->save.dbgctl = data;
3169                 mark_dirty(svm->vmcb, VMCB_LBR);
3170                 if (data & (1ULL<<0))
3171                         svm_enable_lbrv(svm);
3172                 else
3173                         svm_disable_lbrv(svm);
3174                 break;
3175         case MSR_VM_HSAVE_PA:
3176                 svm->nested.hsave_msr = data;
3177                 break;
3178         case MSR_VM_CR:
3179                 return svm_set_vm_cr(vcpu, data);
3180         case MSR_VM_IGNNE:
3181                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3182                 break;
3183         default:
3184                 return kvm_set_msr_common(vcpu, msr);
3185         }
3186         return 0;
3187 }
3188
3189 static int wrmsr_interception(struct vcpu_svm *svm)
3190 {
3191         struct msr_data msr;
3192         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3193         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3194                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3195
3196         msr.data = data;
3197         msr.index = ecx;
3198         msr.host_initiated = false;
3199
3200         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3201         if (kvm_set_msr(&svm->vcpu, &msr)) {
3202                 trace_kvm_msr_write_ex(ecx, data);
3203                 kvm_inject_gp(&svm->vcpu, 0);
3204         } else {
3205                 trace_kvm_msr_write(ecx, data);
3206                 skip_emulated_instruction(&svm->vcpu);
3207         }
3208         return 1;
3209 }
3210
3211 static int msr_interception(struct vcpu_svm *svm)
3212 {
3213         if (svm->vmcb->control.exit_info_1)
3214                 return wrmsr_interception(svm);
3215         else
3216                 return rdmsr_interception(svm);
3217 }
3218
3219 static int interrupt_window_interception(struct vcpu_svm *svm)
3220 {
3221         struct kvm_run *kvm_run = svm->vcpu.run;
3222
3223         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3224         svm_clear_vintr(svm);
3225         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3226         mark_dirty(svm->vmcb, VMCB_INTR);
3227         ++svm->vcpu.stat.irq_window_exits;
3228         /*
3229          * If the user space waits to inject interrupts, exit as soon as
3230          * possible
3231          */
3232         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3233             kvm_run->request_interrupt_window &&
3234             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3235                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3236                 return 0;
3237         }
3238
3239         return 1;
3240 }
3241
3242 static int pause_interception(struct vcpu_svm *svm)
3243 {
3244         kvm_vcpu_on_spin(&(svm->vcpu));
3245         return 1;
3246 }
3247
3248 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3249         [SVM_EXIT_READ_CR0]                     = cr_interception,
3250         [SVM_EXIT_READ_CR3]                     = cr_interception,
3251         [SVM_EXIT_READ_CR4]                     = cr_interception,
3252         [SVM_EXIT_READ_CR8]                     = cr_interception,
3253         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
3254         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3255         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3256         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3257         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3258         [SVM_EXIT_READ_DR0]                     = dr_interception,
3259         [SVM_EXIT_READ_DR1]                     = dr_interception,
3260         [SVM_EXIT_READ_DR2]                     = dr_interception,
3261         [SVM_EXIT_READ_DR3]                     = dr_interception,
3262         [SVM_EXIT_READ_DR4]                     = dr_interception,
3263         [SVM_EXIT_READ_DR5]                     = dr_interception,
3264         [SVM_EXIT_READ_DR6]                     = dr_interception,
3265         [SVM_EXIT_READ_DR7]                     = dr_interception,
3266         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3267         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3268         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3269         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3270         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3271         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3272         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3273         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3274         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3275         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3276         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3277         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3278         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3279         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3280         [SVM_EXIT_INTR]                         = intr_interception,
3281         [SVM_EXIT_NMI]                          = nmi_interception,
3282         [SVM_EXIT_SMI]                          = nop_on_interception,
3283         [SVM_EXIT_INIT]                         = nop_on_interception,
3284         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3285         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3286         [SVM_EXIT_CPUID]                        = cpuid_interception,
3287         [SVM_EXIT_IRET]                         = iret_interception,
3288         [SVM_EXIT_INVD]                         = emulate_on_interception,
3289         [SVM_EXIT_PAUSE]                        = pause_interception,
3290         [SVM_EXIT_HLT]                          = halt_interception,
3291         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3292         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3293         [SVM_EXIT_IOIO]                         = io_interception,
3294         [SVM_EXIT_MSR]                          = msr_interception,
3295         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3296         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3297         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3298         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3299         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3300         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3301         [SVM_EXIT_STGI]                         = stgi_interception,
3302         [SVM_EXIT_CLGI]                         = clgi_interception,
3303         [SVM_EXIT_SKINIT]                       = skinit_interception,
3304         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
3305         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
3306         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
3307         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3308         [SVM_EXIT_NPF]                          = pf_interception,
3309 };
3310
3311 static void dump_vmcb(struct kvm_vcpu *vcpu)
3312 {
3313         struct vcpu_svm *svm = to_svm(vcpu);
3314         struct vmcb_control_area *control = &svm->vmcb->control;
3315         struct vmcb_save_area *save = &svm->vmcb->save;
3316
3317         pr_err("VMCB Control Area:\n");
3318         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3319         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3320         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3321         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3322         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3323         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3324         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3325         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3326         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3327         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3328         pr_err("%-20s%d\n", "asid:", control->asid);
3329         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3330         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3331         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3332         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3333         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3334         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3335         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3336         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3337         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3338         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3339         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3340         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3341         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3342         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3343         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3344         pr_err("VMCB State Save Area:\n");
3345         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3346                "es:",
3347                save->es.selector, save->es.attrib,
3348                save->es.limit, save->es.base);
3349         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3350                "cs:",
3351                save->cs.selector, save->cs.attrib,
3352                save->cs.limit, save->cs.base);
3353         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3354                "ss:",
3355                save->ss.selector, save->ss.attrib,
3356                save->ss.limit, save->ss.base);
3357         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3358                "ds:",
3359                save->ds.selector, save->ds.attrib,
3360                save->ds.limit, save->ds.base);
3361         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3362                "fs:",
3363                save->fs.selector, save->fs.attrib,
3364                save->fs.limit, save->fs.base);
3365         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3366                "gs:",
3367                save->gs.selector, save->gs.attrib,
3368                save->gs.limit, save->gs.base);
3369         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3370                "gdtr:",
3371                save->gdtr.selector, save->gdtr.attrib,
3372                save->gdtr.limit, save->gdtr.base);
3373         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3374                "ldtr:",
3375                save->ldtr.selector, save->ldtr.attrib,
3376                save->ldtr.limit, save->ldtr.base);
3377         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3378                "idtr:",
3379                save->idtr.selector, save->idtr.attrib,
3380                save->idtr.limit, save->idtr.base);
3381         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3382                "tr:",
3383                save->tr.selector, save->tr.attrib,
3384                save->tr.limit, save->tr.base);
3385         pr_err("cpl:            %d                efer:         %016llx\n",
3386                 save->cpl, save->efer);
3387         pr_err("%-15s %016llx %-13s %016llx\n",
3388                "cr0:", save->cr0, "cr2:", save->cr2);
3389         pr_err("%-15s %016llx %-13s %016llx\n",
3390                "cr3:", save->cr3, "cr4:", save->cr4);
3391         pr_err("%-15s %016llx %-13s %016llx\n",
3392                "dr6:", save->dr6, "dr7:", save->dr7);
3393         pr_err("%-15s %016llx %-13s %016llx\n",
3394                "rip:", save->rip, "rflags:", save->rflags);
3395         pr_err("%-15s %016llx %-13s %016llx\n",
3396                "rsp:", save->rsp, "rax:", save->rax);
3397         pr_err("%-15s %016llx %-13s %016llx\n",
3398                "star:", save->star, "lstar:", save->lstar);
3399         pr_err("%-15s %016llx %-13s %016llx\n",
3400                "cstar:", save->cstar, "sfmask:", save->sfmask);
3401         pr_err("%-15s %016llx %-13s %016llx\n",
3402                "kernel_gs_base:", save->kernel_gs_base,
3403                "sysenter_cs:", save->sysenter_cs);
3404         pr_err("%-15s %016llx %-13s %016llx\n",
3405                "sysenter_esp:", save->sysenter_esp,
3406                "sysenter_eip:", save->sysenter_eip);
3407         pr_err("%-15s %016llx %-13s %016llx\n",
3408                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3409         pr_err("%-15s %016llx %-13s %016llx\n",
3410                "br_from:", save->br_from, "br_to:", save->br_to);
3411         pr_err("%-15s %016llx %-13s %016llx\n",
3412                "excp_from:", save->last_excp_from,
3413                "excp_to:", save->last_excp_to);
3414 }
3415
3416 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3417 {
3418         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3419
3420         *info1 = control->exit_info_1;
3421         *info2 = control->exit_info_2;
3422 }
3423
3424 static int handle_exit(struct kvm_vcpu *vcpu)
3425 {
3426         struct vcpu_svm *svm = to_svm(vcpu);
3427         struct kvm_run *kvm_run = vcpu->run;
3428         u32 exit_code = svm->vmcb->control.exit_code;
3429
3430         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3431                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3432         if (npt_enabled)
3433                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3434
3435         if (unlikely(svm->nested.exit_required)) {
3436                 nested_svm_vmexit(svm);
3437                 svm->nested.exit_required = false;
3438
3439                 return 1;
3440         }
3441
3442         if (is_guest_mode(vcpu)) {
3443                 int vmexit;
3444
3445                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3446                                         svm->vmcb->control.exit_info_1,
3447                                         svm->vmcb->control.exit_info_2,
3448                                         svm->vmcb->control.exit_int_info,
3449                                         svm->vmcb->control.exit_int_info_err,
3450                                         KVM_ISA_SVM);
3451
3452                 vmexit = nested_svm_exit_special(svm);
3453
3454                 if (vmexit == NESTED_EXIT_CONTINUE)
3455                         vmexit = nested_svm_exit_handled(svm);
3456
3457                 if (vmexit == NESTED_EXIT_DONE)
3458                         return 1;
3459         }
3460
3461         svm_complete_interrupts(svm);
3462
3463         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3464                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3465                 kvm_run->fail_entry.hardware_entry_failure_reason
3466                         = svm->vmcb->control.exit_code;
3467                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3468                 dump_vmcb(vcpu);
3469                 return 0;
3470         }
3471
3472         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3473             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3474             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3475             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3476                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3477                        "exit_code 0x%x\n",
3478                        __func__, svm->vmcb->control.exit_int_info,
3479                        exit_code);
3480
3481         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3482             || !svm_exit_handlers[exit_code]) {
3483                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_code);
3484                 kvm_queue_exception(vcpu, UD_VECTOR);
3485                 return 1;
3486         }
3487
3488         return svm_exit_handlers[exit_code](svm);
3489 }
3490
3491 static void reload_tss(struct kvm_vcpu *vcpu)
3492 {
3493         int cpu = raw_smp_processor_id();
3494
3495         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3496         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3497         load_TR_desc();
3498 }
3499
3500 static void pre_svm_run(struct vcpu_svm *svm)
3501 {
3502         int cpu = raw_smp_processor_id();
3503
3504         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3505
3506         /* FIXME: handle wraparound of asid_generation */
3507         if (svm->asid_generation != sd->asid_generation)
3508                 new_asid(svm, sd);
3509 }
3510
3511 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3512 {
3513         struct vcpu_svm *svm = to_svm(vcpu);
3514
3515         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3516         vcpu->arch.hflags |= HF_NMI_MASK;
3517         set_intercept(svm, INTERCEPT_IRET);
3518         ++vcpu->stat.nmi_injections;
3519 }
3520
3521 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3522 {
3523         struct vmcb_control_area *control;
3524
3525         control = &svm->vmcb->control;
3526         control->int_vector = irq;
3527         control->int_ctl &= ~V_INTR_PRIO_MASK;
3528         control->int_ctl |= V_IRQ_MASK |
3529                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3530         mark_dirty(svm->vmcb, VMCB_INTR);
3531 }
3532
3533 static void svm_set_irq(struct kvm_vcpu *vcpu)
3534 {
3535         struct vcpu_svm *svm = to_svm(vcpu);
3536
3537         BUG_ON(!(gif_set(svm)));
3538
3539         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3540         ++vcpu->stat.irq_injections;
3541
3542         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3543                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3544 }
3545
3546 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3547 {
3548         struct vcpu_svm *svm = to_svm(vcpu);
3549
3550         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3551                 return;
3552
3553         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3554
3555         if (irr == -1)
3556                 return;
3557
3558         if (tpr >= irr)
3559                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3560 }
3561
3562 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3563 {
3564         return;
3565 }
3566
3567 static int svm_vm_has_apicv(struct kvm *kvm)
3568 {
3569         return 0;
3570 }
3571
3572 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3573 {
3574         return;
3575 }
3576
3577 static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
3578 {
3579         return;
3580 }
3581
3582 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3583 {
3584         return;
3585 }
3586
3587 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3588 {
3589         struct vcpu_svm *svm = to_svm(vcpu);
3590         struct vmcb *vmcb = svm->vmcb;
3591         int ret;
3592         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3593               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3594         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3595
3596         return ret;
3597 }
3598
3599 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3600 {
3601         struct vcpu_svm *svm = to_svm(vcpu);
3602
3603         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3604 }
3605
3606 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3607 {
3608         struct vcpu_svm *svm = to_svm(vcpu);
3609
3610         if (masked) {
3611                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3612                 set_intercept(svm, INTERCEPT_IRET);
3613         } else {
3614                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3615                 clr_intercept(svm, INTERCEPT_IRET);
3616         }
3617 }
3618
3619 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3620 {
3621         struct vcpu_svm *svm = to_svm(vcpu);
3622         struct vmcb *vmcb = svm->vmcb;
3623         int ret;
3624
3625         if (!gif_set(svm) ||
3626              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3627                 return 0;
3628
3629         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3630
3631         if (is_guest_mode(vcpu))
3632                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3633
3634         return ret;
3635 }
3636
3637 static int enable_irq_window(struct kvm_vcpu *vcpu)
3638 {
3639         struct vcpu_svm *svm = to_svm(vcpu);
3640
3641         /*
3642          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3643          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3644          * get that intercept, this function will be called again though and
3645          * we'll get the vintr intercept.
3646          */
3647         if (gif_set(svm) && nested_svm_intr(svm)) {
3648                 svm_set_vintr(svm);
3649                 svm_inject_irq(svm, 0x0);
3650         }
3651         return 0;
3652 }
3653
3654 static int enable_nmi_window(struct kvm_vcpu *vcpu)
3655 {
3656         struct vcpu_svm *svm = to_svm(vcpu);
3657
3658         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3659             == HF_NMI_MASK)
3660                 return 0; /* IRET will cause a vm exit */
3661
3662         /*
3663          * Something prevents NMI from been injected. Single step over possible
3664          * problem (IRET or exception injection or interrupt shadow)
3665          */
3666         svm->nmi_singlestep = true;
3667         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3668         update_db_bp_intercept(vcpu);
3669         return 0;
3670 }
3671
3672 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3673 {
3674         return 0;
3675 }
3676
3677 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3678 {
3679         struct vcpu_svm *svm = to_svm(vcpu);
3680
3681         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3682                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3683         else
3684                 svm->asid_generation--;
3685 }
3686
3687 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3688 {
3689 }
3690
3691 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3692 {
3693         struct vcpu_svm *svm = to_svm(vcpu);
3694
3695         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3696                 return;
3697
3698         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3699                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3700                 kvm_set_cr8(vcpu, cr8);
3701         }
3702 }
3703
3704 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3705 {
3706         struct vcpu_svm *svm = to_svm(vcpu);
3707         u64 cr8;
3708
3709         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3710                 return;
3711
3712         cr8 = kvm_get_cr8(vcpu);
3713         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3714         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3715 }
3716
3717 static void svm_complete_interrupts(struct vcpu_svm *svm)
3718 {
3719         u8 vector;
3720         int type;
3721         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3722         unsigned int3_injected = svm->int3_injected;
3723
3724         svm->int3_injected = 0;
3725
3726         /*
3727          * If we've made progress since setting HF_IRET_MASK, we've
3728          * executed an IRET and can allow NMI injection.
3729          */
3730         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3731             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3732                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3733                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3734         }
3735
3736         svm->vcpu.arch.nmi_injected = false;
3737         kvm_clear_exception_queue(&svm->vcpu);
3738         kvm_clear_interrupt_queue(&svm->vcpu);
3739
3740         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3741                 return;
3742
3743         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3744
3745         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3746         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3747
3748         switch (type) {
3749         case SVM_EXITINTINFO_TYPE_NMI:
3750                 svm->vcpu.arch.nmi_injected = true;
3751                 break;
3752         case SVM_EXITINTINFO_TYPE_EXEPT:
3753                 /*
3754                  * In case of software exceptions, do not reinject the vector,
3755                  * but re-execute the instruction instead. Rewind RIP first
3756                  * if we emulated INT3 before.
3757                  */
3758                 if (kvm_exception_is_soft(vector)) {
3759                         if (vector == BP_VECTOR && int3_injected &&
3760                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3761                                 kvm_rip_write(&svm->vcpu,
3762                                               kvm_rip_read(&svm->vcpu) -
3763                                               int3_injected);
3764                         break;
3765                 }
3766                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3767                         u32 err = svm->vmcb->control.exit_int_info_err;
3768                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3769
3770                 } else
3771                         kvm_requeue_exception(&svm->vcpu, vector);
3772                 break;
3773         case SVM_EXITINTINFO_TYPE_INTR:
3774                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3775                 break;
3776         default:
3777                 break;
3778         }
3779 }
3780
3781 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3782 {
3783         struct vcpu_svm *svm = to_svm(vcpu);
3784         struct vmcb_control_area *control = &svm->vmcb->control;
3785
3786         control->exit_int_info = control->event_inj;
3787         control->exit_int_info_err = control->event_inj_err;
3788         control->event_inj = 0;
3789         svm_complete_interrupts(svm);
3790 }
3791
3792 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3793 {
3794         struct vcpu_svm *svm = to_svm(vcpu);
3795
3796         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3797         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3798         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3799
3800         /*
3801          * A vmexit emulation is required before the vcpu can be executed
3802          * again.
3803          */
3804         if (unlikely(svm->nested.exit_required))
3805                 return;
3806
3807         pre_svm_run(svm);
3808
3809         sync_lapic_to_cr8(vcpu);
3810
3811         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3812
3813         clgi();
3814
3815         local_irq_enable();
3816
3817         asm volatile (
3818                 "push %%" _ASM_BP "; \n\t"
3819                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3820                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3821                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3822                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3823                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3824                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3825 #ifdef CONFIG_X86_64
3826                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3827                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3828                 "mov %c[r10](%[svm]), %%r10 \n\t"
3829                 "mov %c[r11](%[svm]), %%r11 \n\t"
3830                 "mov %c[r12](%[svm]), %%r12 \n\t"
3831                 "mov %c[r13](%[svm]), %%r13 \n\t"
3832                 "mov %c[r14](%[svm]), %%r14 \n\t"
3833                 "mov %c[r15](%[svm]), %%r15 \n\t"
3834 #endif
3835
3836                 /* Enter guest mode */
3837                 "push %%" _ASM_AX " \n\t"
3838                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3839                 __ex(SVM_VMLOAD) "\n\t"
3840                 __ex(SVM_VMRUN) "\n\t"
3841                 __ex(SVM_VMSAVE) "\n\t"
3842                 "pop %%" _ASM_AX " \n\t"
3843
3844                 /* Save guest registers, load host registers */
3845                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3846                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3847                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3848                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3849                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3850                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3851 #ifdef CONFIG_X86_64
3852                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3853                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3854                 "mov %%r10, %c[r10](%[svm]) \n\t"
3855                 "mov %%r11, %c[r11](%[svm]) \n\t"
3856                 "mov %%r12, %c[r12](%[svm]) \n\t"
3857                 "mov %%r13, %c[r13](%[svm]) \n\t"
3858                 "mov %%r14, %c[r14](%[svm]) \n\t"
3859                 "mov %%r15, %c[r15](%[svm]) \n\t"
3860 #endif
3861                 "pop %%" _ASM_BP
3862                 :
3863                 : [svm]"a"(svm),
3864                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3865                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3866                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3867                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3868                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3869                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3870                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3871 #ifdef CONFIG_X86_64
3872                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3873                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3874                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3875                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3876                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3877                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3878                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3879                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3880 #endif
3881                 : "cc", "memory"
3882 #ifdef CONFIG_X86_64
3883                 , "rbx", "rcx", "rdx", "rsi", "rdi"
3884                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3885 #else
3886                 , "ebx", "ecx", "edx", "esi", "edi"
3887 #endif
3888                 );
3889
3890 #ifdef CONFIG_X86_64
3891         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3892 #else
3893         loadsegment(fs, svm->host.fs);
3894 #ifndef CONFIG_X86_32_LAZY_GS
3895         loadsegment(gs, svm->host.gs);
3896 #endif
3897 #endif
3898
3899         reload_tss(vcpu);
3900
3901         local_irq_disable();
3902
3903         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3904         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3905         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3906         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3907
3908         trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3909
3910         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3911                 kvm_before_handle_nmi(&svm->vcpu);
3912
3913         stgi();
3914
3915         /* Any pending NMI will happen here */
3916
3917         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3918                 kvm_after_handle_nmi(&svm->vcpu);
3919
3920         sync_cr8_to_lapic(vcpu);
3921
3922         svm->next_rip = 0;
3923
3924         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3925
3926         /* if exit due to PF check for async PF */
3927         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3928                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3929
3930         if (npt_enabled) {
3931                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3932                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3933         }
3934
3935         /*
3936          * We need to handle MC intercepts here before the vcpu has a chance to
3937          * change the physical cpu
3938          */
3939         if (unlikely(svm->vmcb->control.exit_code ==
3940                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3941                 svm_handle_mce(svm);
3942
3943         mark_all_clean(svm->vmcb);
3944 }
3945
3946 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3947 {
3948         struct vcpu_svm *svm = to_svm(vcpu);
3949
3950         svm->vmcb->save.cr3 = root;
3951         mark_dirty(svm->vmcb, VMCB_CR);
3952         svm_flush_tlb(vcpu);
3953 }
3954
3955 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3956 {
3957         struct vcpu_svm *svm = to_svm(vcpu);
3958
3959         svm->vmcb->control.nested_cr3 = root;
3960         mark_dirty(svm->vmcb, VMCB_NPT);
3961
3962         /* Also sync guest cr3 here in case we live migrate */
3963         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3964         mark_dirty(svm->vmcb, VMCB_CR);
3965
3966         svm_flush_tlb(vcpu);
3967 }
3968
3969 static int is_disabled(void)
3970 {
3971         u64 vm_cr;
3972
3973         rdmsrl(MSR_VM_CR, vm_cr);
3974         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3975                 return 1;
3976
3977         return 0;
3978 }
3979
3980 static void
3981 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3982 {
3983         /*
3984          * Patch in the VMMCALL instruction:
3985          */
3986         hypercall[0] = 0x0f;
3987         hypercall[1] = 0x01;
3988         hypercall[2] = 0xd9;
3989 }
3990
3991 static void svm_check_processor_compat(void *rtn)
3992 {
3993         *(int *)rtn = 0;
3994 }
3995
3996 static bool svm_cpu_has_accelerated_tpr(void)
3997 {
3998         return false;
3999 }
4000
4001 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4002 {
4003         return 0;
4004 }
4005
4006 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4007 {
4008 }
4009
4010 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4011 {
4012         switch (func) {
4013         case 0x80000001:
4014                 if (nested)
4015                         entry->ecx |= (1 << 2); /* Set SVM bit */
4016                 break;
4017         case 0x8000000A:
4018                 entry->eax = 1; /* SVM revision 1 */
4019                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4020                                    ASID emulation to nested SVM */
4021                 entry->ecx = 0; /* Reserved */
4022                 entry->edx = 0; /* Per default do not support any
4023                                    additional features */
4024
4025                 /* Support next_rip if host supports it */
4026                 if (boot_cpu_has(X86_FEATURE_NRIPS))
4027                         entry->edx |= SVM_FEATURE_NRIP;
4028
4029                 /* Support NPT for the guest if enabled */
4030                 if (npt_enabled)
4031                         entry->edx |= SVM_FEATURE_NPT;
4032
4033                 break;
4034         }
4035 }
4036
4037 static int svm_get_lpage_level(void)
4038 {
4039         return PT_PDPE_LEVEL;
4040 }
4041
4042 static bool svm_rdtscp_supported(void)
4043 {
4044         return false;
4045 }
4046
4047 static bool svm_invpcid_supported(void)
4048 {
4049         return false;
4050 }
4051
4052 static bool svm_has_wbinvd_exit(void)
4053 {
4054         return true;
4055 }
4056
4057 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4058 {
4059         struct vcpu_svm *svm = to_svm(vcpu);
4060
4061         set_exception_intercept(svm, NM_VECTOR);
4062         update_cr0_intercept(svm);
4063 }
4064
4065 #define PRE_EX(exit)  { .exit_code = (exit), \
4066                         .stage = X86_ICPT_PRE_EXCEPT, }
4067 #define POST_EX(exit) { .exit_code = (exit), \
4068                         .stage = X86_ICPT_POST_EXCEPT, }
4069 #define POST_MEM(exit) { .exit_code = (exit), \
4070                         .stage = X86_ICPT_POST_MEMACCESS, }
4071
4072 static const struct __x86_intercept {
4073         u32 exit_code;
4074         enum x86_intercept_stage stage;
4075 } x86_intercept_map[] = {
4076         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4077         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4078         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4079         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4080         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4081         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4082         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4083         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4084         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4085         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4086         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4087         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4088         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4089         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4090         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4091         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4092         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4093         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4094         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4095         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4096         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4097         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4098         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4099         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4100         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4101         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4102         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4103         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4104         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4105         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4106         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4107         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4108         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4109         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4110         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4111         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4112         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4113         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4114         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4115         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4116         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4117         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4118         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4119         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4120         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4121         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4122 };
4123
4124 #undef PRE_EX
4125 #undef POST_EX
4126 #undef POST_MEM
4127
4128 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4129                                struct x86_instruction_info *info,
4130                                enum x86_intercept_stage stage)
4131 {
4132         struct vcpu_svm *svm = to_svm(vcpu);
4133         int vmexit, ret = X86EMUL_CONTINUE;
4134         struct __x86_intercept icpt_info;
4135         struct vmcb *vmcb = svm->vmcb;
4136
4137         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4138                 goto out;
4139
4140         icpt_info = x86_intercept_map[info->intercept];
4141
4142         if (stage != icpt_info.stage)
4143                 goto out;
4144
4145         switch (icpt_info.exit_code) {
4146         case SVM_EXIT_READ_CR0:
4147                 if (info->intercept == x86_intercept_cr_read)
4148                         icpt_info.exit_code += info->modrm_reg;
4149                 break;
4150         case SVM_EXIT_WRITE_CR0: {
4151                 unsigned long cr0, val;
4152                 u64 intercept;
4153
4154                 if (info->intercept == x86_intercept_cr_write)
4155                         icpt_info.exit_code += info->modrm_reg;
4156
4157                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4158                         break;
4159
4160                 intercept = svm->nested.intercept;
4161
4162                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4163                         break;
4164
4165                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4166                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4167
4168                 if (info->intercept == x86_intercept_lmsw) {
4169                         cr0 &= 0xfUL;
4170                         val &= 0xfUL;
4171                         /* lmsw can't clear PE - catch this here */
4172                         if (cr0 & X86_CR0_PE)
4173                                 val |= X86_CR0_PE;
4174                 }
4175
4176                 if (cr0 ^ val)
4177                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4178
4179                 break;
4180         }
4181         case SVM_EXIT_READ_DR0:
4182         case SVM_EXIT_WRITE_DR0:
4183                 icpt_info.exit_code += info->modrm_reg;
4184                 break;
4185         case SVM_EXIT_MSR:
4186                 if (info->intercept == x86_intercept_wrmsr)
4187                         vmcb->control.exit_info_1 = 1;
4188                 else
4189                         vmcb->control.exit_info_1 = 0;
4190                 break;
4191         case SVM_EXIT_PAUSE:
4192                 /*
4193                  * We get this for NOP only, but pause
4194                  * is rep not, check this here
4195                  */
4196                 if (info->rep_prefix != REPE_PREFIX)
4197                         goto out;
4198         case SVM_EXIT_IOIO: {
4199                 u64 exit_info;
4200                 u32 bytes;
4201
4202                 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4203
4204                 if (info->intercept == x86_intercept_in ||
4205                     info->intercept == x86_intercept_ins) {
4206                         exit_info |= SVM_IOIO_TYPE_MASK;
4207                         bytes = info->src_bytes;
4208                 } else {
4209                         bytes = info->dst_bytes;
4210                 }
4211
4212                 if (info->intercept == x86_intercept_outs ||
4213                     info->intercept == x86_intercept_ins)
4214                         exit_info |= SVM_IOIO_STR_MASK;
4215
4216                 if (info->rep_prefix)
4217                         exit_info |= SVM_IOIO_REP_MASK;
4218
4219                 bytes = min(bytes, 4u);
4220
4221                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4222
4223                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4224
4225                 vmcb->control.exit_info_1 = exit_info;
4226                 vmcb->control.exit_info_2 = info->next_rip;
4227
4228                 break;
4229         }
4230         default:
4231                 break;
4232         }
4233
4234         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4235         if (static_cpu_has(X86_FEATURE_NRIPS))
4236                 vmcb->control.next_rip  = info->next_rip;
4237         vmcb->control.exit_code = icpt_info.exit_code;
4238         vmexit = nested_svm_exit_handled(svm);
4239
4240         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4241                                            : X86EMUL_CONTINUE;
4242
4243 out:
4244         return ret;
4245 }
4246
4247 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4248 {
4249         local_irq_enable();
4250 }
4251
4252 static struct kvm_x86_ops svm_x86_ops = {
4253         .cpu_has_kvm_support = has_svm,
4254         .disabled_by_bios = is_disabled,
4255         .hardware_setup = svm_hardware_setup,
4256         .hardware_unsetup = svm_hardware_unsetup,
4257         .check_processor_compatibility = svm_check_processor_compat,
4258         .hardware_enable = svm_hardware_enable,
4259         .hardware_disable = svm_hardware_disable,
4260         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4261
4262         .vcpu_create = svm_create_vcpu,
4263         .vcpu_free = svm_free_vcpu,
4264         .vcpu_reset = svm_vcpu_reset,
4265
4266         .prepare_guest_switch = svm_prepare_guest_switch,
4267         .vcpu_load = svm_vcpu_load,
4268         .vcpu_put = svm_vcpu_put,
4269
4270         .update_db_bp_intercept = update_db_bp_intercept,
4271         .get_msr = svm_get_msr,
4272         .set_msr = svm_set_msr,
4273         .get_segment_base = svm_get_segment_base,
4274         .get_segment = svm_get_segment,
4275         .set_segment = svm_set_segment,
4276         .get_cpl = svm_get_cpl,
4277         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4278         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4279         .decache_cr3 = svm_decache_cr3,
4280         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4281         .set_cr0 = svm_set_cr0,
4282         .set_cr3 = svm_set_cr3,
4283         .set_cr4 = svm_set_cr4,
4284         .set_efer = svm_set_efer,
4285         .get_idt = svm_get_idt,
4286         .set_idt = svm_set_idt,
4287         .get_gdt = svm_get_gdt,
4288         .set_gdt = svm_set_gdt,
4289         .set_dr7 = svm_set_dr7,
4290         .cache_reg = svm_cache_reg,
4291         .get_rflags = svm_get_rflags,
4292         .set_rflags = svm_set_rflags,
4293         .fpu_activate = svm_fpu_activate,
4294         .fpu_deactivate = svm_fpu_deactivate,
4295
4296         .tlb_flush = svm_flush_tlb,
4297
4298         .run = svm_vcpu_run,
4299         .handle_exit = handle_exit,
4300         .skip_emulated_instruction = skip_emulated_instruction,
4301         .set_interrupt_shadow = svm_set_interrupt_shadow,
4302         .get_interrupt_shadow = svm_get_interrupt_shadow,
4303         .patch_hypercall = svm_patch_hypercall,
4304         .set_irq = svm_set_irq,
4305         .set_nmi = svm_inject_nmi,
4306         .queue_exception = svm_queue_exception,
4307         .cancel_injection = svm_cancel_injection,
4308         .interrupt_allowed = svm_interrupt_allowed,
4309         .nmi_allowed = svm_nmi_allowed,
4310         .get_nmi_mask = svm_get_nmi_mask,
4311         .set_nmi_mask = svm_set_nmi_mask,
4312         .enable_nmi_window = enable_nmi_window,
4313         .enable_irq_window = enable_irq_window,
4314         .update_cr8_intercept = update_cr8_intercept,
4315         .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4316         .vm_has_apicv = svm_vm_has_apicv,
4317         .load_eoi_exitmap = svm_load_eoi_exitmap,
4318         .hwapic_isr_update = svm_hwapic_isr_update,
4319         .sync_pir_to_irr = svm_sync_pir_to_irr,
4320
4321         .set_tss_addr = svm_set_tss_addr,
4322         .get_tdp_level = get_npt_level,
4323         .get_mt_mask = svm_get_mt_mask,
4324
4325         .get_exit_info = svm_get_exit_info,
4326
4327         .get_lpage_level = svm_get_lpage_level,
4328
4329         .cpuid_update = svm_cpuid_update,
4330
4331         .rdtscp_supported = svm_rdtscp_supported,
4332         .invpcid_supported = svm_invpcid_supported,
4333
4334         .set_supported_cpuid = svm_set_supported_cpuid,
4335
4336         .has_wbinvd_exit = svm_has_wbinvd_exit,
4337
4338         .set_tsc_khz = svm_set_tsc_khz,
4339         .read_tsc_offset = svm_read_tsc_offset,
4340         .write_tsc_offset = svm_write_tsc_offset,
4341         .adjust_tsc_offset = svm_adjust_tsc_offset,
4342         .compute_tsc_offset = svm_compute_tsc_offset,
4343         .read_l1_tsc = svm_read_l1_tsc,
4344
4345         .set_tdp_cr3 = set_tdp_cr3,
4346
4347         .check_intercept = svm_check_intercept,
4348         .handle_external_intr = svm_handle_external_intr,
4349 };
4350
4351 static int __init svm_init(void)
4352 {
4353         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4354                         __alignof__(struct vcpu_svm), THIS_MODULE);
4355 }
4356
4357 static void __exit svm_exit(void)
4358 {
4359         kvm_exit();
4360 }
4361
4362 module_init(svm_init)
4363 module_exit(svm_exit)