2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/kernel.h>
28 #include <linux/vmalloc.h>
29 #include <linux/highmem.h>
30 #include <linux/sched.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
34 #include <asm/perf_event.h>
35 #include <asm/tlbflush.h>
37 #include <asm/debugreg.h>
38 #include <asm/kvm_para.h>
40 #include <asm/virtext.h>
43 #define __ex(x) __kvm_handle_fault_on_reboot(x)
45 MODULE_AUTHOR("Qumranet");
46 MODULE_LICENSE("GPL");
48 static const struct x86_cpu_id svm_cpu_id[] = {
49 X86_FEATURE_MATCH(X86_FEATURE_SVM),
52 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
54 #define IOPM_ALLOC_ORDER 2
55 #define MSRPM_ALLOC_ORDER 1
57 #define SEG_TYPE_LDT 2
58 #define SEG_TYPE_BUSY_TSS16 3
60 #define SVM_FEATURE_NPT (1 << 0)
61 #define SVM_FEATURE_LBRV (1 << 1)
62 #define SVM_FEATURE_SVML (1 << 2)
63 #define SVM_FEATURE_NRIP (1 << 3)
64 #define SVM_FEATURE_TSC_RATE (1 << 4)
65 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
66 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
67 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
68 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
70 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
71 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
72 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
74 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
76 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
77 #define TSC_RATIO_MIN 0x0000000000000001ULL
78 #define TSC_RATIO_MAX 0x000000ffffffffffULL
80 static bool erratum_383_found __read_mostly;
82 static const u32 host_save_user_msrs[] = {
84 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
87 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
90 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
100 /* These are the merged vectors */
103 /* gpa pointers to the real vectors */
107 /* A VMEXIT is required but not yet emulated */
110 /* cache for intercepts of the guest */
113 u32 intercept_exceptions;
116 /* Nested Paging related state */
120 #define MSRPM_OFFSETS 16
121 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
124 * Set osvw_len to higher value when updated Revision Guides
125 * are published and we know what the new status bits are
127 static uint64_t osvw_len = 4, osvw_status;
130 struct kvm_vcpu vcpu;
132 unsigned long vmcb_pa;
133 struct svm_cpu_data *svm_data;
134 uint64_t asid_generation;
135 uint64_t sysenter_esp;
136 uint64_t sysenter_eip;
140 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
152 struct nested_state nested;
156 unsigned int3_injected;
157 unsigned long int3_rip;
163 static DEFINE_PER_CPU(u64, current_tsc_ratio);
164 #define TSC_RATIO_DEFAULT 0x0100000000ULL
166 #define MSR_INVALID 0xffffffffU
168 static const struct svm_direct_access_msrs {
169 u32 index; /* Index of the MSR */
170 bool always; /* True if intercept is always on */
171 } direct_access_msrs[] = {
172 { .index = MSR_STAR, .always = true },
173 { .index = MSR_IA32_SYSENTER_CS, .always = true },
175 { .index = MSR_GS_BASE, .always = true },
176 { .index = MSR_FS_BASE, .always = true },
177 { .index = MSR_KERNEL_GS_BASE, .always = true },
178 { .index = MSR_LSTAR, .always = true },
179 { .index = MSR_CSTAR, .always = true },
180 { .index = MSR_SYSCALL_MASK, .always = true },
182 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
183 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
184 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
185 { .index = MSR_IA32_LASTINTTOIP, .always = false },
186 { .index = MSR_INVALID, .always = false },
189 /* enable NPT for AMD64 and X86 with PAE */
190 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
191 static bool npt_enabled = true;
193 static bool npt_enabled;
196 /* allow nested paging (virtualized MMU) for all guests */
197 static int npt = true;
198 module_param(npt, int, S_IRUGO);
200 /* allow nested virtualization in KVM/SVM */
201 static int nested = true;
202 module_param(nested, int, S_IRUGO);
204 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
205 static void svm_complete_interrupts(struct vcpu_svm *svm);
207 static int nested_svm_exit_handled(struct vcpu_svm *svm);
208 static int nested_svm_intercept(struct vcpu_svm *svm);
209 static int nested_svm_vmexit(struct vcpu_svm *svm);
210 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
211 bool has_error_code, u32 error_code);
212 static u64 __scale_tsc(u64 ratio, u64 tsc);
215 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
216 pause filter count */
217 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
218 VMCB_ASID, /* ASID */
219 VMCB_INTR, /* int_ctl, int_vector */
220 VMCB_NPT, /* npt_en, nCR3, gPAT */
221 VMCB_CR, /* CR0, CR3, CR4, EFER */
222 VMCB_DR, /* DR6, DR7 */
223 VMCB_DT, /* GDT, IDT */
224 VMCB_SEG, /* CS, DS, SS, ES, CPL */
225 VMCB_CR2, /* CR2 only */
226 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
230 /* TPR and CR2 are always written before VMRUN */
231 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
233 static inline void mark_all_dirty(struct vmcb *vmcb)
235 vmcb->control.clean = 0;
238 static inline void mark_all_clean(struct vmcb *vmcb)
240 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
241 & ~VMCB_ALWAYS_DIRTY_MASK;
244 static inline void mark_dirty(struct vmcb *vmcb, int bit)
246 vmcb->control.clean &= ~(1 << bit);
249 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
251 return container_of(vcpu, struct vcpu_svm, vcpu);
254 static void recalc_intercepts(struct vcpu_svm *svm)
256 struct vmcb_control_area *c, *h;
257 struct nested_state *g;
259 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
261 if (!is_guest_mode(&svm->vcpu))
264 c = &svm->vmcb->control;
265 h = &svm->nested.hsave->control;
268 c->intercept_cr = h->intercept_cr | g->intercept_cr;
269 c->intercept_dr = h->intercept_dr | g->intercept_dr;
270 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
271 c->intercept = h->intercept | g->intercept;
274 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
276 if (is_guest_mode(&svm->vcpu))
277 return svm->nested.hsave;
282 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
284 struct vmcb *vmcb = get_host_vmcb(svm);
286 vmcb->control.intercept_cr |= (1U << bit);
288 recalc_intercepts(svm);
291 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
293 struct vmcb *vmcb = get_host_vmcb(svm);
295 vmcb->control.intercept_cr &= ~(1U << bit);
297 recalc_intercepts(svm);
300 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
302 struct vmcb *vmcb = get_host_vmcb(svm);
304 return vmcb->control.intercept_cr & (1U << bit);
307 static inline void set_dr_intercepts(struct vcpu_svm *svm)
309 struct vmcb *vmcb = get_host_vmcb(svm);
311 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
312 | (1 << INTERCEPT_DR1_READ)
313 | (1 << INTERCEPT_DR2_READ)
314 | (1 << INTERCEPT_DR3_READ)
315 | (1 << INTERCEPT_DR4_READ)
316 | (1 << INTERCEPT_DR5_READ)
317 | (1 << INTERCEPT_DR6_READ)
318 | (1 << INTERCEPT_DR7_READ)
319 | (1 << INTERCEPT_DR0_WRITE)
320 | (1 << INTERCEPT_DR1_WRITE)
321 | (1 << INTERCEPT_DR2_WRITE)
322 | (1 << INTERCEPT_DR3_WRITE)
323 | (1 << INTERCEPT_DR4_WRITE)
324 | (1 << INTERCEPT_DR5_WRITE)
325 | (1 << INTERCEPT_DR6_WRITE)
326 | (1 << INTERCEPT_DR7_WRITE);
328 recalc_intercepts(svm);
331 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
333 struct vmcb *vmcb = get_host_vmcb(svm);
335 vmcb->control.intercept_dr = 0;
337 recalc_intercepts(svm);
340 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
342 struct vmcb *vmcb = get_host_vmcb(svm);
344 vmcb->control.intercept_exceptions |= (1U << bit);
346 recalc_intercepts(svm);
349 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
351 struct vmcb *vmcb = get_host_vmcb(svm);
353 vmcb->control.intercept_exceptions &= ~(1U << bit);
355 recalc_intercepts(svm);
358 static inline void set_intercept(struct vcpu_svm *svm, int bit)
360 struct vmcb *vmcb = get_host_vmcb(svm);
362 vmcb->control.intercept |= (1ULL << bit);
364 recalc_intercepts(svm);
367 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
369 struct vmcb *vmcb = get_host_vmcb(svm);
371 vmcb->control.intercept &= ~(1ULL << bit);
373 recalc_intercepts(svm);
376 static inline void enable_gif(struct vcpu_svm *svm)
378 svm->vcpu.arch.hflags |= HF_GIF_MASK;
381 static inline void disable_gif(struct vcpu_svm *svm)
383 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
386 static inline bool gif_set(struct vcpu_svm *svm)
388 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
391 static unsigned long iopm_base;
393 struct kvm_ldttss_desc {
396 unsigned base1:8, type:5, dpl:2, p:1;
397 unsigned limit1:4, zero0:3, g:1, base2:8;
400 } __attribute__((packed));
402 struct svm_cpu_data {
408 struct kvm_ldttss_desc *tss_desc;
410 struct page *save_area;
413 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
415 struct svm_init_data {
420 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
422 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
423 #define MSRS_RANGE_SIZE 2048
424 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
426 static u32 svm_msrpm_offset(u32 msr)
431 for (i = 0; i < NUM_MSR_MAPS; i++) {
432 if (msr < msrpm_ranges[i] ||
433 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
436 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
437 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
439 /* Now we have the u8 offset - but need the u32 offset */
443 /* MSR not in any range */
447 #define MAX_INST_SIZE 15
449 static inline void clgi(void)
451 asm volatile (__ex(SVM_CLGI));
454 static inline void stgi(void)
456 asm volatile (__ex(SVM_STGI));
459 static inline void invlpga(unsigned long addr, u32 asid)
461 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
464 static int get_npt_level(void)
467 return PT64_ROOT_LEVEL;
469 return PT32E_ROOT_LEVEL;
473 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
475 vcpu->arch.efer = efer;
476 if (!npt_enabled && !(efer & EFER_LMA))
479 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
480 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
483 static int is_external_interrupt(u32 info)
485 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
486 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
489 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
491 struct vcpu_svm *svm = to_svm(vcpu);
494 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
495 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
499 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
501 struct vcpu_svm *svm = to_svm(vcpu);
504 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
506 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
510 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
512 struct vcpu_svm *svm = to_svm(vcpu);
514 if (svm->vmcb->control.next_rip != 0)
515 svm->next_rip = svm->vmcb->control.next_rip;
517 if (!svm->next_rip) {
518 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
520 printk(KERN_DEBUG "%s: NOP\n", __func__);
523 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
524 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
525 __func__, kvm_rip_read(vcpu), svm->next_rip);
527 kvm_rip_write(vcpu, svm->next_rip);
528 svm_set_interrupt_shadow(vcpu, 0);
531 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
532 bool has_error_code, u32 error_code,
535 struct vcpu_svm *svm = to_svm(vcpu);
538 * If we are within a nested VM we'd better #VMEXIT and let the guest
539 * handle the exception
542 nested_svm_check_exception(svm, nr, has_error_code, error_code))
545 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
546 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
549 * For guest debugging where we have to reinject #BP if some
550 * INT3 is guest-owned:
551 * Emulate nRIP by moving RIP forward. Will fail if injection
552 * raises a fault that is not intercepted. Still better than
553 * failing in all cases.
555 skip_emulated_instruction(&svm->vcpu);
556 rip = kvm_rip_read(&svm->vcpu);
557 svm->int3_rip = rip + svm->vmcb->save.cs.base;
558 svm->int3_injected = rip - old_rip;
561 svm->vmcb->control.event_inj = nr
563 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
564 | SVM_EVTINJ_TYPE_EXEPT;
565 svm->vmcb->control.event_inj_err = error_code;
568 static void svm_init_erratum_383(void)
574 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
577 /* Use _safe variants to not break nested virtualization */
578 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
584 low = lower_32_bits(val);
585 high = upper_32_bits(val);
587 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
589 erratum_383_found = true;
592 static void svm_init_osvw(struct kvm_vcpu *vcpu)
595 * Guests should see errata 400 and 415 as fixed (assuming that
596 * HLT and IO instructions are intercepted).
598 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
599 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
602 * By increasing VCPU's osvw.length to 3 we are telling the guest that
603 * all osvw.status bits inside that length, including bit 0 (which is
604 * reserved for erratum 298), are valid. However, if host processor's
605 * osvw_len is 0 then osvw_status[0] carries no information. We need to
606 * be conservative here and therefore we tell the guest that erratum 298
607 * is present (because we really don't know).
609 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
610 vcpu->arch.osvw.status |= 1;
613 static int has_svm(void)
617 if (!cpu_has_svm(&msg)) {
618 printk(KERN_INFO "has_svm: %s\n", msg);
625 static void svm_hardware_disable(void)
627 /* Make sure we clean up behind us */
628 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
629 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
633 amd_pmu_disable_virt();
636 static int svm_hardware_enable(void)
639 struct svm_cpu_data *sd;
641 struct desc_ptr gdt_descr;
642 struct desc_struct *gdt;
643 int me = raw_smp_processor_id();
645 rdmsrl(MSR_EFER, efer);
646 if (efer & EFER_SVME)
650 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
653 sd = per_cpu(svm_data, me);
655 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
659 sd->asid_generation = 1;
660 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
661 sd->next_asid = sd->max_asid + 1;
663 native_store_gdt(&gdt_descr);
664 gdt = (struct desc_struct *)gdt_descr.address;
665 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
667 wrmsrl(MSR_EFER, efer | EFER_SVME);
669 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
671 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
672 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
673 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
680 * Note that it is possible to have a system with mixed processor
681 * revisions and therefore different OSVW bits. If bits are not the same
682 * on different processors then choose the worst case (i.e. if erratum
683 * is present on one processor and not on another then assume that the
684 * erratum is present everywhere).
686 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
687 uint64_t len, status = 0;
690 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
692 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
696 osvw_status = osvw_len = 0;
700 osvw_status |= status;
701 osvw_status &= (1ULL << osvw_len) - 1;
704 osvw_status = osvw_len = 0;
706 svm_init_erratum_383();
708 amd_pmu_enable_virt();
713 static void svm_cpu_uninit(int cpu)
715 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
720 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
721 __free_page(sd->save_area);
725 static int svm_cpu_init(int cpu)
727 struct svm_cpu_data *sd;
730 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
734 sd->save_area = alloc_page(GFP_KERNEL);
739 per_cpu(svm_data, cpu) = sd;
749 static bool valid_msr_intercept(u32 index)
753 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
754 if (direct_access_msrs[i].index == index)
760 static void set_msr_interception(u32 *msrpm, unsigned msr,
763 u8 bit_read, bit_write;
768 * If this warning triggers extend the direct_access_msrs list at the
769 * beginning of the file
771 WARN_ON(!valid_msr_intercept(msr));
773 offset = svm_msrpm_offset(msr);
774 bit_read = 2 * (msr & 0x0f);
775 bit_write = 2 * (msr & 0x0f) + 1;
778 BUG_ON(offset == MSR_INVALID);
780 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
781 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
786 static void svm_vcpu_init_msrpm(u32 *msrpm)
790 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
792 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
793 if (!direct_access_msrs[i].always)
796 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
800 static void add_msr_offset(u32 offset)
804 for (i = 0; i < MSRPM_OFFSETS; ++i) {
806 /* Offset already in list? */
807 if (msrpm_offsets[i] == offset)
810 /* Slot used by another offset? */
811 if (msrpm_offsets[i] != MSR_INVALID)
814 /* Add offset to list */
815 msrpm_offsets[i] = offset;
821 * If this BUG triggers the msrpm_offsets table has an overflow. Just
822 * increase MSRPM_OFFSETS in this case.
827 static void init_msrpm_offsets(void)
831 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
833 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
836 offset = svm_msrpm_offset(direct_access_msrs[i].index);
837 BUG_ON(offset == MSR_INVALID);
839 add_msr_offset(offset);
843 static void svm_enable_lbrv(struct vcpu_svm *svm)
845 u32 *msrpm = svm->msrpm;
847 svm->vmcb->control.lbr_ctl = 1;
848 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
849 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
850 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
851 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
854 static void svm_disable_lbrv(struct vcpu_svm *svm)
856 u32 *msrpm = svm->msrpm;
858 svm->vmcb->control.lbr_ctl = 0;
859 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
860 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
861 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
862 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
865 static __init int svm_hardware_setup(void)
868 struct page *iopm_pages;
872 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
877 iopm_va = page_address(iopm_pages);
878 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
879 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
881 init_msrpm_offsets();
883 if (boot_cpu_has(X86_FEATURE_NX))
884 kvm_enable_efer_bits(EFER_NX);
886 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
887 kvm_enable_efer_bits(EFER_FFXSR);
889 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
892 kvm_has_tsc_control = true;
895 * Make sure the user can only configure tsc_khz values that
896 * fit into a signed integer.
897 * A min value is not calculated needed because it will always
898 * be 1 on all machines and a value of 0 is used to disable
899 * tsc-scaling for the vcpu.
901 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
903 kvm_max_guest_tsc_khz = max;
907 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
908 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
911 for_each_possible_cpu(cpu) {
912 r = svm_cpu_init(cpu);
917 if (!boot_cpu_has(X86_FEATURE_NPT))
920 if (npt_enabled && !npt) {
921 printk(KERN_INFO "kvm: Nested Paging disabled\n");
926 printk(KERN_INFO "kvm: Nested Paging enabled\n");
934 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
939 static __exit void svm_hardware_unsetup(void)
943 for_each_possible_cpu(cpu)
946 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
950 static void init_seg(struct vmcb_seg *seg)
953 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
954 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
959 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
962 seg->attrib = SVM_SELECTOR_P_MASK | type;
967 static u64 __scale_tsc(u64 ratio, u64 tsc)
969 u64 mult, frac, _tsc;
972 frac = ratio & ((1ULL << 32) - 1);
976 _tsc += (tsc >> 32) * frac;
977 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
982 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
984 struct vcpu_svm *svm = to_svm(vcpu);
987 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
988 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
993 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
995 struct vcpu_svm *svm = to_svm(vcpu);
999 /* Guest TSC same frequency as host TSC? */
1001 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1005 /* TSC scaling supported? */
1006 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1007 if (user_tsc_khz > tsc_khz) {
1008 vcpu->arch.tsc_catchup = 1;
1009 vcpu->arch.tsc_always_catchup = 1;
1011 WARN(1, "user requested TSC rate below hardware speed\n");
1017 /* TSC scaling required - calculate ratio */
1019 do_div(ratio, tsc_khz);
1021 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1022 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1026 svm->tsc_ratio = ratio;
1029 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1031 struct vcpu_svm *svm = to_svm(vcpu);
1033 return svm->vmcb->control.tsc_offset;
1036 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1038 struct vcpu_svm *svm = to_svm(vcpu);
1039 u64 g_tsc_offset = 0;
1041 if (is_guest_mode(vcpu)) {
1042 g_tsc_offset = svm->vmcb->control.tsc_offset -
1043 svm->nested.hsave->control.tsc_offset;
1044 svm->nested.hsave->control.tsc_offset = offset;
1046 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1047 svm->vmcb->control.tsc_offset,
1050 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1052 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1055 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1057 struct vcpu_svm *svm = to_svm(vcpu);
1060 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1061 WARN_ON(adjustment < 0);
1062 adjustment = svm_scale_tsc(vcpu, (u64)adjustment);
1065 svm->vmcb->control.tsc_offset += adjustment;
1066 if (is_guest_mode(vcpu))
1067 svm->nested.hsave->control.tsc_offset += adjustment;
1069 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1070 svm->vmcb->control.tsc_offset - adjustment,
1071 svm->vmcb->control.tsc_offset);
1073 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1076 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1080 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1082 return target_tsc - tsc;
1085 static void init_vmcb(struct vcpu_svm *svm, bool init_event)
1087 struct vmcb_control_area *control = &svm->vmcb->control;
1088 struct vmcb_save_area *save = &svm->vmcb->save;
1090 svm->vcpu.fpu_active = 1;
1091 svm->vcpu.arch.hflags = 0;
1093 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1094 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1095 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1096 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1097 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1098 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1099 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1101 set_dr_intercepts(svm);
1103 set_exception_intercept(svm, PF_VECTOR);
1104 set_exception_intercept(svm, UD_VECTOR);
1105 set_exception_intercept(svm, MC_VECTOR);
1107 set_intercept(svm, INTERCEPT_INTR);
1108 set_intercept(svm, INTERCEPT_NMI);
1109 set_intercept(svm, INTERCEPT_SMI);
1110 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1111 set_intercept(svm, INTERCEPT_RDPMC);
1112 set_intercept(svm, INTERCEPT_CPUID);
1113 set_intercept(svm, INTERCEPT_INVD);
1114 set_intercept(svm, INTERCEPT_HLT);
1115 set_intercept(svm, INTERCEPT_INVLPG);
1116 set_intercept(svm, INTERCEPT_INVLPGA);
1117 set_intercept(svm, INTERCEPT_IOIO_PROT);
1118 set_intercept(svm, INTERCEPT_MSR_PROT);
1119 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1120 set_intercept(svm, INTERCEPT_SHUTDOWN);
1121 set_intercept(svm, INTERCEPT_VMRUN);
1122 set_intercept(svm, INTERCEPT_VMMCALL);
1123 set_intercept(svm, INTERCEPT_VMLOAD);
1124 set_intercept(svm, INTERCEPT_VMSAVE);
1125 set_intercept(svm, INTERCEPT_STGI);
1126 set_intercept(svm, INTERCEPT_CLGI);
1127 set_intercept(svm, INTERCEPT_SKINIT);
1128 set_intercept(svm, INTERCEPT_WBINVD);
1129 set_intercept(svm, INTERCEPT_MONITOR);
1130 set_intercept(svm, INTERCEPT_MWAIT);
1131 set_intercept(svm, INTERCEPT_XSETBV);
1133 control->iopm_base_pa = iopm_base;
1134 control->msrpm_base_pa = __pa(svm->msrpm);
1135 control->int_ctl = V_INTR_MASKING_MASK;
1137 init_seg(&save->es);
1138 init_seg(&save->ss);
1139 init_seg(&save->ds);
1140 init_seg(&save->fs);
1141 init_seg(&save->gs);
1143 save->cs.selector = 0xf000;
1144 save->cs.base = 0xffff0000;
1145 /* Executable/Readable Code Segment */
1146 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1147 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1148 save->cs.limit = 0xffff;
1150 save->gdtr.limit = 0xffff;
1151 save->idtr.limit = 0xffff;
1153 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1154 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1157 svm_set_efer(&svm->vcpu, 0);
1158 save->dr6 = 0xffff0ff0;
1159 kvm_set_rflags(&svm->vcpu, 2);
1160 save->rip = 0x0000fff0;
1161 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1164 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1165 * It also updates the guest-visible cr0 value.
1167 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1169 save->cr4 = X86_CR4_PAE;
1173 /* Setup VMCB for Nested Paging */
1174 control->nested_ctl = 1;
1175 clr_intercept(svm, INTERCEPT_INVLPG);
1176 clr_exception_intercept(svm, PF_VECTOR);
1177 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1178 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1179 save->g_pat = svm->vcpu.arch.pat;
1183 svm->asid_generation = 0;
1185 svm->nested.vmcb = 0;
1186 svm->vcpu.arch.hflags = 0;
1188 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1189 control->pause_filter_count = 3000;
1190 set_intercept(svm, INTERCEPT_PAUSE);
1193 mark_all_dirty(svm->vmcb);
1198 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1200 struct vcpu_svm *svm = to_svm(vcpu);
1205 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1206 MSR_IA32_APICBASE_ENABLE;
1207 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1208 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1210 init_vmcb(svm, init_event);
1212 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1213 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1216 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1218 struct vcpu_svm *svm;
1220 struct page *msrpm_pages;
1221 struct page *hsave_page;
1222 struct page *nested_msrpm_pages;
1225 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1231 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1233 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1238 page = alloc_page(GFP_KERNEL);
1242 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1246 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1247 if (!nested_msrpm_pages)
1250 hsave_page = alloc_page(GFP_KERNEL);
1254 svm->nested.hsave = page_address(hsave_page);
1256 svm->msrpm = page_address(msrpm_pages);
1257 svm_vcpu_init_msrpm(svm->msrpm);
1259 svm->nested.msrpm = page_address(nested_msrpm_pages);
1260 svm_vcpu_init_msrpm(svm->nested.msrpm);
1262 svm->vmcb = page_address(page);
1263 clear_page(svm->vmcb);
1264 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1265 svm->asid_generation = 0;
1266 init_vmcb(svm, false);
1268 svm_init_osvw(&svm->vcpu);
1273 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1275 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1279 kvm_vcpu_uninit(&svm->vcpu);
1281 kmem_cache_free(kvm_vcpu_cache, svm);
1283 return ERR_PTR(err);
1286 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1288 struct vcpu_svm *svm = to_svm(vcpu);
1290 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1291 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1292 __free_page(virt_to_page(svm->nested.hsave));
1293 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1294 kvm_vcpu_uninit(vcpu);
1295 kmem_cache_free(kvm_vcpu_cache, svm);
1298 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1300 struct vcpu_svm *svm = to_svm(vcpu);
1303 if (unlikely(cpu != vcpu->cpu)) {
1304 svm->asid_generation = 0;
1305 mark_all_dirty(svm->vmcb);
1308 #ifdef CONFIG_X86_64
1309 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1311 savesegment(fs, svm->host.fs);
1312 savesegment(gs, svm->host.gs);
1313 svm->host.ldt = kvm_read_ldt();
1315 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1316 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1318 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1319 svm->tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1320 __this_cpu_write(current_tsc_ratio, svm->tsc_ratio);
1321 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1325 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1327 struct vcpu_svm *svm = to_svm(vcpu);
1330 ++vcpu->stat.host_state_reload;
1331 kvm_load_ldt(svm->host.ldt);
1332 #ifdef CONFIG_X86_64
1333 loadsegment(fs, svm->host.fs);
1334 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1335 load_gs_index(svm->host.gs);
1337 #ifdef CONFIG_X86_32_LAZY_GS
1338 loadsegment(gs, svm->host.gs);
1341 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1342 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1345 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1347 return to_svm(vcpu)->vmcb->save.rflags;
1350 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1353 * Any change of EFLAGS.VM is accompained by a reload of SS
1354 * (caused by either a task switch or an inter-privilege IRET),
1355 * so we do not need to update the CPL here.
1357 to_svm(vcpu)->vmcb->save.rflags = rflags;
1360 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1363 case VCPU_EXREG_PDPTR:
1364 BUG_ON(!npt_enabled);
1365 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1372 static void svm_set_vintr(struct vcpu_svm *svm)
1374 set_intercept(svm, INTERCEPT_VINTR);
1377 static void svm_clear_vintr(struct vcpu_svm *svm)
1379 clr_intercept(svm, INTERCEPT_VINTR);
1382 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1384 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1387 case VCPU_SREG_CS: return &save->cs;
1388 case VCPU_SREG_DS: return &save->ds;
1389 case VCPU_SREG_ES: return &save->es;
1390 case VCPU_SREG_FS: return &save->fs;
1391 case VCPU_SREG_GS: return &save->gs;
1392 case VCPU_SREG_SS: return &save->ss;
1393 case VCPU_SREG_TR: return &save->tr;
1394 case VCPU_SREG_LDTR: return &save->ldtr;
1400 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1402 struct vmcb_seg *s = svm_seg(vcpu, seg);
1407 static void svm_get_segment(struct kvm_vcpu *vcpu,
1408 struct kvm_segment *var, int seg)
1410 struct vmcb_seg *s = svm_seg(vcpu, seg);
1412 var->base = s->base;
1413 var->limit = s->limit;
1414 var->selector = s->selector;
1415 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1416 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1417 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1418 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1419 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1420 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1421 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1424 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1425 * However, the SVM spec states that the G bit is not observed by the
1426 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1427 * So let's synthesize a legal G bit for all segments, this helps
1428 * running KVM nested. It also helps cross-vendor migration, because
1429 * Intel's vmentry has a check on the 'G' bit.
1431 var->g = s->limit > 0xfffff;
1434 * AMD's VMCB does not have an explicit unusable field, so emulate it
1435 * for cross vendor migration purposes by "not present"
1437 var->unusable = !var->present || (var->type == 0);
1442 * Work around a bug where the busy flag in the tr selector
1452 * The accessed bit must always be set in the segment
1453 * descriptor cache, although it can be cleared in the
1454 * descriptor, the cached bit always remains at 1. Since
1455 * Intel has a check on this, set it here to support
1456 * cross-vendor migration.
1463 * On AMD CPUs sometimes the DB bit in the segment
1464 * descriptor is left as 1, although the whole segment has
1465 * been made unusable. Clear it here to pass an Intel VMX
1466 * entry check when cross vendor migrating.
1470 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1475 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1477 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1482 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1484 struct vcpu_svm *svm = to_svm(vcpu);
1486 dt->size = svm->vmcb->save.idtr.limit;
1487 dt->address = svm->vmcb->save.idtr.base;
1490 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1492 struct vcpu_svm *svm = to_svm(vcpu);
1494 svm->vmcb->save.idtr.limit = dt->size;
1495 svm->vmcb->save.idtr.base = dt->address ;
1496 mark_dirty(svm->vmcb, VMCB_DT);
1499 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1501 struct vcpu_svm *svm = to_svm(vcpu);
1503 dt->size = svm->vmcb->save.gdtr.limit;
1504 dt->address = svm->vmcb->save.gdtr.base;
1507 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1509 struct vcpu_svm *svm = to_svm(vcpu);
1511 svm->vmcb->save.gdtr.limit = dt->size;
1512 svm->vmcb->save.gdtr.base = dt->address ;
1513 mark_dirty(svm->vmcb, VMCB_DT);
1516 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1520 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1524 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1528 static void update_cr0_intercept(struct vcpu_svm *svm)
1530 ulong gcr0 = svm->vcpu.arch.cr0;
1531 u64 *hcr0 = &svm->vmcb->save.cr0;
1533 if (!svm->vcpu.fpu_active)
1534 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1536 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1537 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1539 mark_dirty(svm->vmcb, VMCB_CR);
1541 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1542 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1543 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1545 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1546 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1550 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1552 struct vcpu_svm *svm = to_svm(vcpu);
1554 #ifdef CONFIG_X86_64
1555 if (vcpu->arch.efer & EFER_LME) {
1556 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1557 vcpu->arch.efer |= EFER_LMA;
1558 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1561 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1562 vcpu->arch.efer &= ~EFER_LMA;
1563 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1567 vcpu->arch.cr0 = cr0;
1570 cr0 |= X86_CR0_PG | X86_CR0_WP;
1572 if (!vcpu->fpu_active)
1575 * re-enable caching here because the QEMU bios
1576 * does not do it - this results in some delay at
1579 if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_CD_NW_CLEARED))
1580 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1581 svm->vmcb->save.cr0 = cr0;
1582 mark_dirty(svm->vmcb, VMCB_CR);
1583 update_cr0_intercept(svm);
1586 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1588 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1589 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1591 if (cr4 & X86_CR4_VMXE)
1594 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1595 svm_flush_tlb(vcpu);
1597 vcpu->arch.cr4 = cr4;
1600 cr4 |= host_cr4_mce;
1601 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1602 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1606 static void svm_set_segment(struct kvm_vcpu *vcpu,
1607 struct kvm_segment *var, int seg)
1609 struct vcpu_svm *svm = to_svm(vcpu);
1610 struct vmcb_seg *s = svm_seg(vcpu, seg);
1612 s->base = var->base;
1613 s->limit = var->limit;
1614 s->selector = var->selector;
1618 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1619 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1620 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1621 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1622 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1623 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1624 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1625 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1629 * This is always accurate, except if SYSRET returned to a segment
1630 * with SS.DPL != 3. Intel does not have this quirk, and always
1631 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1632 * would entail passing the CPL to userspace and back.
1634 if (seg == VCPU_SREG_SS)
1635 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1637 mark_dirty(svm->vmcb, VMCB_SEG);
1640 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1642 struct vcpu_svm *svm = to_svm(vcpu);
1644 clr_exception_intercept(svm, DB_VECTOR);
1645 clr_exception_intercept(svm, BP_VECTOR);
1647 if (svm->nmi_singlestep)
1648 set_exception_intercept(svm, DB_VECTOR);
1650 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1651 if (vcpu->guest_debug &
1652 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1653 set_exception_intercept(svm, DB_VECTOR);
1654 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1655 set_exception_intercept(svm, BP_VECTOR);
1657 vcpu->guest_debug = 0;
1660 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1662 if (sd->next_asid > sd->max_asid) {
1663 ++sd->asid_generation;
1665 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1668 svm->asid_generation = sd->asid_generation;
1669 svm->vmcb->control.asid = sd->next_asid++;
1671 mark_dirty(svm->vmcb, VMCB_ASID);
1674 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1676 return to_svm(vcpu)->vmcb->save.dr6;
1679 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1681 struct vcpu_svm *svm = to_svm(vcpu);
1683 svm->vmcb->save.dr6 = value;
1684 mark_dirty(svm->vmcb, VMCB_DR);
1687 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1689 struct vcpu_svm *svm = to_svm(vcpu);
1691 get_debugreg(vcpu->arch.db[0], 0);
1692 get_debugreg(vcpu->arch.db[1], 1);
1693 get_debugreg(vcpu->arch.db[2], 2);
1694 get_debugreg(vcpu->arch.db[3], 3);
1695 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1696 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1698 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1699 set_dr_intercepts(svm);
1702 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1704 struct vcpu_svm *svm = to_svm(vcpu);
1706 svm->vmcb->save.dr7 = value;
1707 mark_dirty(svm->vmcb, VMCB_DR);
1710 static int pf_interception(struct vcpu_svm *svm)
1712 u64 fault_address = svm->vmcb->control.exit_info_2;
1716 switch (svm->apf_reason) {
1718 error_code = svm->vmcb->control.exit_info_1;
1720 trace_kvm_page_fault(fault_address, error_code);
1721 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1722 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1723 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1724 svm->vmcb->control.insn_bytes,
1725 svm->vmcb->control.insn_len);
1727 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1728 svm->apf_reason = 0;
1729 local_irq_disable();
1730 kvm_async_pf_task_wait(fault_address);
1733 case KVM_PV_REASON_PAGE_READY:
1734 svm->apf_reason = 0;
1735 local_irq_disable();
1736 kvm_async_pf_task_wake(fault_address);
1743 static int db_interception(struct vcpu_svm *svm)
1745 struct kvm_run *kvm_run = svm->vcpu.run;
1747 if (!(svm->vcpu.guest_debug &
1748 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1749 !svm->nmi_singlestep) {
1750 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1754 if (svm->nmi_singlestep) {
1755 svm->nmi_singlestep = false;
1756 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1757 svm->vmcb->save.rflags &=
1758 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1759 update_db_bp_intercept(&svm->vcpu);
1762 if (svm->vcpu.guest_debug &
1763 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1764 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1765 kvm_run->debug.arch.pc =
1766 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1767 kvm_run->debug.arch.exception = DB_VECTOR;
1774 static int bp_interception(struct vcpu_svm *svm)
1776 struct kvm_run *kvm_run = svm->vcpu.run;
1778 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1779 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1780 kvm_run->debug.arch.exception = BP_VECTOR;
1784 static int ud_interception(struct vcpu_svm *svm)
1788 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1789 if (er != EMULATE_DONE)
1790 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1794 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1796 struct vcpu_svm *svm = to_svm(vcpu);
1798 clr_exception_intercept(svm, NM_VECTOR);
1800 svm->vcpu.fpu_active = 1;
1801 update_cr0_intercept(svm);
1804 static int nm_interception(struct vcpu_svm *svm)
1806 svm_fpu_activate(&svm->vcpu);
1810 static bool is_erratum_383(void)
1815 if (!erratum_383_found)
1818 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1822 /* Bit 62 may or may not be set for this mce */
1823 value &= ~(1ULL << 62);
1825 if (value != 0xb600000000010015ULL)
1828 /* Clear MCi_STATUS registers */
1829 for (i = 0; i < 6; ++i)
1830 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1832 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1836 value &= ~(1ULL << 2);
1837 low = lower_32_bits(value);
1838 high = upper_32_bits(value);
1840 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1843 /* Flush tlb to evict multi-match entries */
1849 static void svm_handle_mce(struct vcpu_svm *svm)
1851 if (is_erratum_383()) {
1853 * Erratum 383 triggered. Guest state is corrupt so kill the
1856 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1858 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1864 * On an #MC intercept the MCE handler is not called automatically in
1865 * the host. So do it by hand here.
1869 /* not sure if we ever come back to this point */
1874 static int mc_interception(struct vcpu_svm *svm)
1879 static int shutdown_interception(struct vcpu_svm *svm)
1881 struct kvm_run *kvm_run = svm->vcpu.run;
1884 * VMCB is undefined after a SHUTDOWN intercept
1885 * so reinitialize it.
1887 clear_page(svm->vmcb);
1888 init_vmcb(svm, false);
1890 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1894 static int io_interception(struct vcpu_svm *svm)
1896 struct kvm_vcpu *vcpu = &svm->vcpu;
1897 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1898 int size, in, string;
1901 ++svm->vcpu.stat.io_exits;
1902 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1903 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1905 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1907 port = io_info >> 16;
1908 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1909 svm->next_rip = svm->vmcb->control.exit_info_2;
1910 skip_emulated_instruction(&svm->vcpu);
1912 return kvm_fast_pio_out(vcpu, size, port);
1915 static int nmi_interception(struct vcpu_svm *svm)
1920 static int intr_interception(struct vcpu_svm *svm)
1922 ++svm->vcpu.stat.irq_exits;
1926 static int nop_on_interception(struct vcpu_svm *svm)
1931 static int halt_interception(struct vcpu_svm *svm)
1933 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1934 return kvm_emulate_halt(&svm->vcpu);
1937 static int vmmcall_interception(struct vcpu_svm *svm)
1939 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1940 kvm_emulate_hypercall(&svm->vcpu);
1944 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1946 struct vcpu_svm *svm = to_svm(vcpu);
1948 return svm->nested.nested_cr3;
1951 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1953 struct vcpu_svm *svm = to_svm(vcpu);
1954 u64 cr3 = svm->nested.nested_cr3;
1958 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
1959 offset_in_page(cr3) + index * 8, 8);
1965 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1968 struct vcpu_svm *svm = to_svm(vcpu);
1970 svm->vmcb->control.nested_cr3 = root;
1971 mark_dirty(svm->vmcb, VMCB_NPT);
1972 svm_flush_tlb(vcpu);
1975 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1976 struct x86_exception *fault)
1978 struct vcpu_svm *svm = to_svm(vcpu);
1980 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
1982 * TODO: track the cause of the nested page fault, and
1983 * correctly fill in the high bits of exit_info_1.
1985 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1986 svm->vmcb->control.exit_code_hi = 0;
1987 svm->vmcb->control.exit_info_1 = (1ULL << 32);
1988 svm->vmcb->control.exit_info_2 = fault->address;
1991 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
1992 svm->vmcb->control.exit_info_1 |= fault->error_code;
1995 * The present bit is always zero for page structure faults on real
1998 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
1999 svm->vmcb->control.exit_info_1 &= ~1;
2001 nested_svm_vmexit(svm);
2004 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2006 WARN_ON(mmu_is_nested(vcpu));
2007 kvm_init_shadow_mmu(vcpu);
2008 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2009 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2010 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2011 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2012 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2013 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2016 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2018 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2021 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2023 if (!(svm->vcpu.arch.efer & EFER_SVME)
2024 || !is_paging(&svm->vcpu)) {
2025 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2029 if (svm->vmcb->save.cpl) {
2030 kvm_inject_gp(&svm->vcpu, 0);
2037 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2038 bool has_error_code, u32 error_code)
2042 if (!is_guest_mode(&svm->vcpu))
2045 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2046 svm->vmcb->control.exit_code_hi = 0;
2047 svm->vmcb->control.exit_info_1 = error_code;
2048 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2050 vmexit = nested_svm_intercept(svm);
2051 if (vmexit == NESTED_EXIT_DONE)
2052 svm->nested.exit_required = true;
2057 /* This function returns true if it is save to enable the irq window */
2058 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2060 if (!is_guest_mode(&svm->vcpu))
2063 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2066 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2070 * if vmexit was already requested (by intercepted exception
2071 * for instance) do not overwrite it with "external interrupt"
2074 if (svm->nested.exit_required)
2077 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2078 svm->vmcb->control.exit_info_1 = 0;
2079 svm->vmcb->control.exit_info_2 = 0;
2081 if (svm->nested.intercept & 1ULL) {
2083 * The #vmexit can't be emulated here directly because this
2084 * code path runs with irqs and preemption disabled. A
2085 * #vmexit emulation might sleep. Only signal request for
2088 svm->nested.exit_required = true;
2089 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2096 /* This function returns true if it is save to enable the nmi window */
2097 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2099 if (!is_guest_mode(&svm->vcpu))
2102 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2105 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2106 svm->nested.exit_required = true;
2111 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2117 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2118 if (is_error_page(page))
2126 kvm_inject_gp(&svm->vcpu, 0);
2131 static void nested_svm_unmap(struct page *page)
2134 kvm_release_page_dirty(page);
2137 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2139 unsigned port, size, iopm_len;
2144 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2145 return NESTED_EXIT_HOST;
2147 port = svm->vmcb->control.exit_info_1 >> 16;
2148 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2149 SVM_IOIO_SIZE_SHIFT;
2150 gpa = svm->nested.vmcb_iopm + (port / 8);
2151 start_bit = port % 8;
2152 iopm_len = (start_bit + size > 8) ? 2 : 1;
2153 mask = (0xf >> (4 - size)) << start_bit;
2156 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2157 return NESTED_EXIT_DONE;
2159 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2162 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2164 u32 offset, msr, value;
2167 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2168 return NESTED_EXIT_HOST;
2170 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2171 offset = svm_msrpm_offset(msr);
2172 write = svm->vmcb->control.exit_info_1 & 1;
2173 mask = 1 << ((2 * (msr & 0xf)) + write);
2175 if (offset == MSR_INVALID)
2176 return NESTED_EXIT_DONE;
2178 /* Offset is in 32 bit units but need in 8 bit units */
2181 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2182 return NESTED_EXIT_DONE;
2184 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2187 static int nested_svm_exit_special(struct vcpu_svm *svm)
2189 u32 exit_code = svm->vmcb->control.exit_code;
2191 switch (exit_code) {
2194 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2195 return NESTED_EXIT_HOST;
2197 /* For now we are always handling NPFs when using them */
2199 return NESTED_EXIT_HOST;
2201 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2202 /* When we're shadowing, trap PFs, but not async PF */
2203 if (!npt_enabled && svm->apf_reason == 0)
2204 return NESTED_EXIT_HOST;
2206 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2207 nm_interception(svm);
2213 return NESTED_EXIT_CONTINUE;
2217 * If this function returns true, this #vmexit was already handled
2219 static int nested_svm_intercept(struct vcpu_svm *svm)
2221 u32 exit_code = svm->vmcb->control.exit_code;
2222 int vmexit = NESTED_EXIT_HOST;
2224 switch (exit_code) {
2226 vmexit = nested_svm_exit_handled_msr(svm);
2229 vmexit = nested_svm_intercept_ioio(svm);
2231 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2232 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2233 if (svm->nested.intercept_cr & bit)
2234 vmexit = NESTED_EXIT_DONE;
2237 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2238 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2239 if (svm->nested.intercept_dr & bit)
2240 vmexit = NESTED_EXIT_DONE;
2243 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2244 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2245 if (svm->nested.intercept_exceptions & excp_bits)
2246 vmexit = NESTED_EXIT_DONE;
2247 /* async page fault always cause vmexit */
2248 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2249 svm->apf_reason != 0)
2250 vmexit = NESTED_EXIT_DONE;
2253 case SVM_EXIT_ERR: {
2254 vmexit = NESTED_EXIT_DONE;
2258 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2259 if (svm->nested.intercept & exit_bits)
2260 vmexit = NESTED_EXIT_DONE;
2267 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2271 vmexit = nested_svm_intercept(svm);
2273 if (vmexit == NESTED_EXIT_DONE)
2274 nested_svm_vmexit(svm);
2279 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2281 struct vmcb_control_area *dst = &dst_vmcb->control;
2282 struct vmcb_control_area *from = &from_vmcb->control;
2284 dst->intercept_cr = from->intercept_cr;
2285 dst->intercept_dr = from->intercept_dr;
2286 dst->intercept_exceptions = from->intercept_exceptions;
2287 dst->intercept = from->intercept;
2288 dst->iopm_base_pa = from->iopm_base_pa;
2289 dst->msrpm_base_pa = from->msrpm_base_pa;
2290 dst->tsc_offset = from->tsc_offset;
2291 dst->asid = from->asid;
2292 dst->tlb_ctl = from->tlb_ctl;
2293 dst->int_ctl = from->int_ctl;
2294 dst->int_vector = from->int_vector;
2295 dst->int_state = from->int_state;
2296 dst->exit_code = from->exit_code;
2297 dst->exit_code_hi = from->exit_code_hi;
2298 dst->exit_info_1 = from->exit_info_1;
2299 dst->exit_info_2 = from->exit_info_2;
2300 dst->exit_int_info = from->exit_int_info;
2301 dst->exit_int_info_err = from->exit_int_info_err;
2302 dst->nested_ctl = from->nested_ctl;
2303 dst->event_inj = from->event_inj;
2304 dst->event_inj_err = from->event_inj_err;
2305 dst->nested_cr3 = from->nested_cr3;
2306 dst->lbr_ctl = from->lbr_ctl;
2309 static int nested_svm_vmexit(struct vcpu_svm *svm)
2311 struct vmcb *nested_vmcb;
2312 struct vmcb *hsave = svm->nested.hsave;
2313 struct vmcb *vmcb = svm->vmcb;
2316 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2317 vmcb->control.exit_info_1,
2318 vmcb->control.exit_info_2,
2319 vmcb->control.exit_int_info,
2320 vmcb->control.exit_int_info_err,
2323 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2327 /* Exit Guest-Mode */
2328 leave_guest_mode(&svm->vcpu);
2329 svm->nested.vmcb = 0;
2331 /* Give the current vmcb to the guest */
2334 nested_vmcb->save.es = vmcb->save.es;
2335 nested_vmcb->save.cs = vmcb->save.cs;
2336 nested_vmcb->save.ss = vmcb->save.ss;
2337 nested_vmcb->save.ds = vmcb->save.ds;
2338 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2339 nested_vmcb->save.idtr = vmcb->save.idtr;
2340 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2341 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2342 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2343 nested_vmcb->save.cr2 = vmcb->save.cr2;
2344 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2345 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2346 nested_vmcb->save.rip = vmcb->save.rip;
2347 nested_vmcb->save.rsp = vmcb->save.rsp;
2348 nested_vmcb->save.rax = vmcb->save.rax;
2349 nested_vmcb->save.dr7 = vmcb->save.dr7;
2350 nested_vmcb->save.dr6 = vmcb->save.dr6;
2351 nested_vmcb->save.cpl = vmcb->save.cpl;
2353 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2354 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2355 nested_vmcb->control.int_state = vmcb->control.int_state;
2356 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2357 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2358 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2359 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2360 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2361 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2362 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2365 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2366 * to make sure that we do not lose injected events. So check event_inj
2367 * here and copy it to exit_int_info if it is valid.
2368 * Exit_int_info and event_inj can't be both valid because the case
2369 * below only happens on a VMRUN instruction intercept which has
2370 * no valid exit_int_info set.
2372 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2373 struct vmcb_control_area *nc = &nested_vmcb->control;
2375 nc->exit_int_info = vmcb->control.event_inj;
2376 nc->exit_int_info_err = vmcb->control.event_inj_err;
2379 nested_vmcb->control.tlb_ctl = 0;
2380 nested_vmcb->control.event_inj = 0;
2381 nested_vmcb->control.event_inj_err = 0;
2383 /* We always set V_INTR_MASKING and remember the old value in hflags */
2384 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2385 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2387 /* Restore the original control entries */
2388 copy_vmcb_control_area(vmcb, hsave);
2390 kvm_clear_exception_queue(&svm->vcpu);
2391 kvm_clear_interrupt_queue(&svm->vcpu);
2393 svm->nested.nested_cr3 = 0;
2395 /* Restore selected save entries */
2396 svm->vmcb->save.es = hsave->save.es;
2397 svm->vmcb->save.cs = hsave->save.cs;
2398 svm->vmcb->save.ss = hsave->save.ss;
2399 svm->vmcb->save.ds = hsave->save.ds;
2400 svm->vmcb->save.gdtr = hsave->save.gdtr;
2401 svm->vmcb->save.idtr = hsave->save.idtr;
2402 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2403 svm_set_efer(&svm->vcpu, hsave->save.efer);
2404 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2405 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2407 svm->vmcb->save.cr3 = hsave->save.cr3;
2408 svm->vcpu.arch.cr3 = hsave->save.cr3;
2410 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2412 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2413 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2414 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2415 svm->vmcb->save.dr7 = 0;
2416 svm->vmcb->save.cpl = 0;
2417 svm->vmcb->control.exit_int_info = 0;
2419 mark_all_dirty(svm->vmcb);
2421 nested_svm_unmap(page);
2423 nested_svm_uninit_mmu_context(&svm->vcpu);
2424 kvm_mmu_reset_context(&svm->vcpu);
2425 kvm_mmu_load(&svm->vcpu);
2430 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2433 * This function merges the msr permission bitmaps of kvm and the
2434 * nested vmcb. It is optimized in that it only merges the parts where
2435 * the kvm msr permission bitmap may contain zero bits
2439 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2442 for (i = 0; i < MSRPM_OFFSETS; i++) {
2446 if (msrpm_offsets[i] == 0xffffffff)
2449 p = msrpm_offsets[i];
2450 offset = svm->nested.vmcb_msrpm + (p * 4);
2452 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2455 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2458 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2463 static bool nested_vmcb_checks(struct vmcb *vmcb)
2465 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2468 if (vmcb->control.asid == 0)
2471 if (vmcb->control.nested_ctl && !npt_enabled)
2477 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2479 struct vmcb *nested_vmcb;
2480 struct vmcb *hsave = svm->nested.hsave;
2481 struct vmcb *vmcb = svm->vmcb;
2485 vmcb_gpa = svm->vmcb->save.rax;
2487 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2491 if (!nested_vmcb_checks(nested_vmcb)) {
2492 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2493 nested_vmcb->control.exit_code_hi = 0;
2494 nested_vmcb->control.exit_info_1 = 0;
2495 nested_vmcb->control.exit_info_2 = 0;
2497 nested_svm_unmap(page);
2502 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2503 nested_vmcb->save.rip,
2504 nested_vmcb->control.int_ctl,
2505 nested_vmcb->control.event_inj,
2506 nested_vmcb->control.nested_ctl);
2508 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2509 nested_vmcb->control.intercept_cr >> 16,
2510 nested_vmcb->control.intercept_exceptions,
2511 nested_vmcb->control.intercept);
2513 /* Clear internal status */
2514 kvm_clear_exception_queue(&svm->vcpu);
2515 kvm_clear_interrupt_queue(&svm->vcpu);
2518 * Save the old vmcb, so we don't need to pick what we save, but can
2519 * restore everything when a VMEXIT occurs
2521 hsave->save.es = vmcb->save.es;
2522 hsave->save.cs = vmcb->save.cs;
2523 hsave->save.ss = vmcb->save.ss;
2524 hsave->save.ds = vmcb->save.ds;
2525 hsave->save.gdtr = vmcb->save.gdtr;
2526 hsave->save.idtr = vmcb->save.idtr;
2527 hsave->save.efer = svm->vcpu.arch.efer;
2528 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2529 hsave->save.cr4 = svm->vcpu.arch.cr4;
2530 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2531 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2532 hsave->save.rsp = vmcb->save.rsp;
2533 hsave->save.rax = vmcb->save.rax;
2535 hsave->save.cr3 = vmcb->save.cr3;
2537 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2539 copy_vmcb_control_area(hsave, vmcb);
2541 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2542 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2544 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2546 if (nested_vmcb->control.nested_ctl) {
2547 kvm_mmu_unload(&svm->vcpu);
2548 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2549 nested_svm_init_mmu_context(&svm->vcpu);
2552 /* Load the nested guest state */
2553 svm->vmcb->save.es = nested_vmcb->save.es;
2554 svm->vmcb->save.cs = nested_vmcb->save.cs;
2555 svm->vmcb->save.ss = nested_vmcb->save.ss;
2556 svm->vmcb->save.ds = nested_vmcb->save.ds;
2557 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2558 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2559 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2560 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2561 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2562 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2564 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2565 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2567 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2569 /* Guest paging mode is active - reset mmu */
2570 kvm_mmu_reset_context(&svm->vcpu);
2572 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2573 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2574 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2575 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2577 /* In case we don't even reach vcpu_run, the fields are not updated */
2578 svm->vmcb->save.rax = nested_vmcb->save.rax;
2579 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2580 svm->vmcb->save.rip = nested_vmcb->save.rip;
2581 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2582 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2583 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2585 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2586 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2588 /* cache intercepts */
2589 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2590 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2591 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2592 svm->nested.intercept = nested_vmcb->control.intercept;
2594 svm_flush_tlb(&svm->vcpu);
2595 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2596 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2597 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2599 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2601 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2602 /* We only want the cr8 intercept bits of the guest */
2603 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2604 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2607 /* We don't want to see VMMCALLs from a nested guest */
2608 clr_intercept(svm, INTERCEPT_VMMCALL);
2610 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2611 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2612 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2613 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2614 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2615 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2617 nested_svm_unmap(page);
2619 /* Enter Guest-Mode */
2620 enter_guest_mode(&svm->vcpu);
2623 * Merge guest and host intercepts - must be called with vcpu in
2624 * guest-mode to take affect here
2626 recalc_intercepts(svm);
2628 svm->nested.vmcb = vmcb_gpa;
2632 mark_all_dirty(svm->vmcb);
2637 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2639 to_vmcb->save.fs = from_vmcb->save.fs;
2640 to_vmcb->save.gs = from_vmcb->save.gs;
2641 to_vmcb->save.tr = from_vmcb->save.tr;
2642 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2643 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2644 to_vmcb->save.star = from_vmcb->save.star;
2645 to_vmcb->save.lstar = from_vmcb->save.lstar;
2646 to_vmcb->save.cstar = from_vmcb->save.cstar;
2647 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2648 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2649 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2650 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2653 static int vmload_interception(struct vcpu_svm *svm)
2655 struct vmcb *nested_vmcb;
2658 if (nested_svm_check_permissions(svm))
2661 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2665 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2666 skip_emulated_instruction(&svm->vcpu);
2668 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2669 nested_svm_unmap(page);
2674 static int vmsave_interception(struct vcpu_svm *svm)
2676 struct vmcb *nested_vmcb;
2679 if (nested_svm_check_permissions(svm))
2682 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2686 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2687 skip_emulated_instruction(&svm->vcpu);
2689 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2690 nested_svm_unmap(page);
2695 static int vmrun_interception(struct vcpu_svm *svm)
2697 if (nested_svm_check_permissions(svm))
2700 /* Save rip after vmrun instruction */
2701 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2703 if (!nested_svm_vmrun(svm))
2706 if (!nested_svm_vmrun_msrpm(svm))
2713 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2714 svm->vmcb->control.exit_code_hi = 0;
2715 svm->vmcb->control.exit_info_1 = 0;
2716 svm->vmcb->control.exit_info_2 = 0;
2718 nested_svm_vmexit(svm);
2723 static int stgi_interception(struct vcpu_svm *svm)
2725 if (nested_svm_check_permissions(svm))
2728 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2729 skip_emulated_instruction(&svm->vcpu);
2730 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2737 static int clgi_interception(struct vcpu_svm *svm)
2739 if (nested_svm_check_permissions(svm))
2742 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2743 skip_emulated_instruction(&svm->vcpu);
2747 /* After a CLGI no interrupts should come */
2748 svm_clear_vintr(svm);
2749 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2751 mark_dirty(svm->vmcb, VMCB_INTR);
2756 static int invlpga_interception(struct vcpu_svm *svm)
2758 struct kvm_vcpu *vcpu = &svm->vcpu;
2760 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2761 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2763 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2764 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2766 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2767 skip_emulated_instruction(&svm->vcpu);
2771 static int skinit_interception(struct vcpu_svm *svm)
2773 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2775 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2779 static int wbinvd_interception(struct vcpu_svm *svm)
2781 kvm_emulate_wbinvd(&svm->vcpu);
2785 static int xsetbv_interception(struct vcpu_svm *svm)
2787 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2788 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2790 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2791 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2792 skip_emulated_instruction(&svm->vcpu);
2798 static int task_switch_interception(struct vcpu_svm *svm)
2802 int int_type = svm->vmcb->control.exit_int_info &
2803 SVM_EXITINTINFO_TYPE_MASK;
2804 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2806 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2808 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2809 bool has_error_code = false;
2812 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2814 if (svm->vmcb->control.exit_info_2 &
2815 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2816 reason = TASK_SWITCH_IRET;
2817 else if (svm->vmcb->control.exit_info_2 &
2818 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2819 reason = TASK_SWITCH_JMP;
2821 reason = TASK_SWITCH_GATE;
2823 reason = TASK_SWITCH_CALL;
2825 if (reason == TASK_SWITCH_GATE) {
2827 case SVM_EXITINTINFO_TYPE_NMI:
2828 svm->vcpu.arch.nmi_injected = false;
2830 case SVM_EXITINTINFO_TYPE_EXEPT:
2831 if (svm->vmcb->control.exit_info_2 &
2832 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2833 has_error_code = true;
2835 (u32)svm->vmcb->control.exit_info_2;
2837 kvm_clear_exception_queue(&svm->vcpu);
2839 case SVM_EXITINTINFO_TYPE_INTR:
2840 kvm_clear_interrupt_queue(&svm->vcpu);
2847 if (reason != TASK_SWITCH_GATE ||
2848 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2849 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2850 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2851 skip_emulated_instruction(&svm->vcpu);
2853 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2856 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2857 has_error_code, error_code) == EMULATE_FAIL) {
2858 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2859 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2860 svm->vcpu.run->internal.ndata = 0;
2866 static int cpuid_interception(struct vcpu_svm *svm)
2868 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2869 kvm_emulate_cpuid(&svm->vcpu);
2873 static int iret_interception(struct vcpu_svm *svm)
2875 ++svm->vcpu.stat.nmi_window_exits;
2876 clr_intercept(svm, INTERCEPT_IRET);
2877 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2878 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2879 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2883 static int invlpg_interception(struct vcpu_svm *svm)
2885 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2886 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2888 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2889 skip_emulated_instruction(&svm->vcpu);
2893 static int emulate_on_interception(struct vcpu_svm *svm)
2895 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2898 static int rdpmc_interception(struct vcpu_svm *svm)
2902 if (!static_cpu_has(X86_FEATURE_NRIPS))
2903 return emulate_on_interception(svm);
2905 err = kvm_rdpmc(&svm->vcpu);
2906 kvm_complete_insn_gp(&svm->vcpu, err);
2911 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2914 unsigned long cr0 = svm->vcpu.arch.cr0;
2918 intercept = svm->nested.intercept;
2920 if (!is_guest_mode(&svm->vcpu) ||
2921 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2924 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2925 val &= ~SVM_CR0_SELECTIVE_MASK;
2928 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2929 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2935 #define CR_VALID (1ULL << 63)
2937 static int cr_interception(struct vcpu_svm *svm)
2943 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2944 return emulate_on_interception(svm);
2946 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2947 return emulate_on_interception(svm);
2949 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2950 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2951 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2953 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2956 if (cr >= 16) { /* mov to cr */
2958 val = kvm_register_read(&svm->vcpu, reg);
2961 if (!check_selective_cr0_intercepted(svm, val))
2962 err = kvm_set_cr0(&svm->vcpu, val);
2968 err = kvm_set_cr3(&svm->vcpu, val);
2971 err = kvm_set_cr4(&svm->vcpu, val);
2974 err = kvm_set_cr8(&svm->vcpu, val);
2977 WARN(1, "unhandled write to CR%d", cr);
2978 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2981 } else { /* mov from cr */
2984 val = kvm_read_cr0(&svm->vcpu);
2987 val = svm->vcpu.arch.cr2;
2990 val = kvm_read_cr3(&svm->vcpu);
2993 val = kvm_read_cr4(&svm->vcpu);
2996 val = kvm_get_cr8(&svm->vcpu);
2999 WARN(1, "unhandled read from CR%d", cr);
3000 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3003 kvm_register_write(&svm->vcpu, reg, val);
3005 kvm_complete_insn_gp(&svm->vcpu, err);
3010 static int dr_interception(struct vcpu_svm *svm)
3015 if (svm->vcpu.guest_debug == 0) {
3017 * No more DR vmexits; force a reload of the debug registers
3018 * and reenter on this instruction. The next vmexit will
3019 * retrieve the full state of the debug registers.
3021 clr_dr_intercepts(svm);
3022 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3026 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3027 return emulate_on_interception(svm);
3029 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3030 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3032 if (dr >= 16) { /* mov to DRn */
3033 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3035 val = kvm_register_read(&svm->vcpu, reg);
3036 kvm_set_dr(&svm->vcpu, dr - 16, val);
3038 if (!kvm_require_dr(&svm->vcpu, dr))
3040 kvm_get_dr(&svm->vcpu, dr, &val);
3041 kvm_register_write(&svm->vcpu, reg, val);
3044 skip_emulated_instruction(&svm->vcpu);
3049 static int cr8_write_interception(struct vcpu_svm *svm)
3051 struct kvm_run *kvm_run = svm->vcpu.run;
3054 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3055 /* instruction emulation calls kvm_set_cr8() */
3056 r = cr_interception(svm);
3057 if (irqchip_in_kernel(svm->vcpu.kvm))
3059 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3061 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3065 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3067 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3068 return vmcb->control.tsc_offset +
3069 svm_scale_tsc(vcpu, host_tsc);
3072 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3074 struct vcpu_svm *svm = to_svm(vcpu);
3076 switch (msr_info->index) {
3077 case MSR_IA32_TSC: {
3078 msr_info->data = svm->vmcb->control.tsc_offset +
3079 svm_scale_tsc(vcpu, native_read_tsc());
3084 msr_info->data = svm->vmcb->save.star;
3086 #ifdef CONFIG_X86_64
3088 msr_info->data = svm->vmcb->save.lstar;
3091 msr_info->data = svm->vmcb->save.cstar;
3093 case MSR_KERNEL_GS_BASE:
3094 msr_info->data = svm->vmcb->save.kernel_gs_base;
3096 case MSR_SYSCALL_MASK:
3097 msr_info->data = svm->vmcb->save.sfmask;
3100 case MSR_IA32_SYSENTER_CS:
3101 msr_info->data = svm->vmcb->save.sysenter_cs;
3103 case MSR_IA32_SYSENTER_EIP:
3104 msr_info->data = svm->sysenter_eip;
3106 case MSR_IA32_SYSENTER_ESP:
3107 msr_info->data = svm->sysenter_esp;
3110 * Nobody will change the following 5 values in the VMCB so we can
3111 * safely return them on rdmsr. They will always be 0 until LBRV is
3114 case MSR_IA32_DEBUGCTLMSR:
3115 msr_info->data = svm->vmcb->save.dbgctl;
3117 case MSR_IA32_LASTBRANCHFROMIP:
3118 msr_info->data = svm->vmcb->save.br_from;
3120 case MSR_IA32_LASTBRANCHTOIP:
3121 msr_info->data = svm->vmcb->save.br_to;
3123 case MSR_IA32_LASTINTFROMIP:
3124 msr_info->data = svm->vmcb->save.last_excp_from;
3126 case MSR_IA32_LASTINTTOIP:
3127 msr_info->data = svm->vmcb->save.last_excp_to;
3129 case MSR_VM_HSAVE_PA:
3130 msr_info->data = svm->nested.hsave_msr;
3133 msr_info->data = svm->nested.vm_cr_msr;
3135 case MSR_IA32_UCODE_REV:
3136 msr_info->data = 0x01000065;
3139 return kvm_get_msr_common(vcpu, msr_info);
3144 static int rdmsr_interception(struct vcpu_svm *svm)
3146 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3147 struct msr_data msr_info;
3149 msr_info.index = ecx;
3150 msr_info.host_initiated = false;
3151 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3152 trace_kvm_msr_read_ex(ecx);
3153 kvm_inject_gp(&svm->vcpu, 0);
3155 trace_kvm_msr_read(ecx, msr_info.data);
3157 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3158 msr_info.data & 0xffffffff);
3159 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3160 msr_info.data >> 32);
3161 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3162 skip_emulated_instruction(&svm->vcpu);
3167 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3169 struct vcpu_svm *svm = to_svm(vcpu);
3170 int svm_dis, chg_mask;
3172 if (data & ~SVM_VM_CR_VALID_MASK)
3175 chg_mask = SVM_VM_CR_VALID_MASK;
3177 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3178 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3180 svm->nested.vm_cr_msr &= ~chg_mask;
3181 svm->nested.vm_cr_msr |= (data & chg_mask);
3183 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3185 /* check for svm_disable while efer.svme is set */
3186 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3192 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3194 struct vcpu_svm *svm = to_svm(vcpu);
3196 u32 ecx = msr->index;
3197 u64 data = msr->data;
3200 kvm_write_tsc(vcpu, msr);
3203 svm->vmcb->save.star = data;
3205 #ifdef CONFIG_X86_64
3207 svm->vmcb->save.lstar = data;
3210 svm->vmcb->save.cstar = data;
3212 case MSR_KERNEL_GS_BASE:
3213 svm->vmcb->save.kernel_gs_base = data;
3215 case MSR_SYSCALL_MASK:
3216 svm->vmcb->save.sfmask = data;
3219 case MSR_IA32_SYSENTER_CS:
3220 svm->vmcb->save.sysenter_cs = data;
3222 case MSR_IA32_SYSENTER_EIP:
3223 svm->sysenter_eip = data;
3224 svm->vmcb->save.sysenter_eip = data;
3226 case MSR_IA32_SYSENTER_ESP:
3227 svm->sysenter_esp = data;
3228 svm->vmcb->save.sysenter_esp = data;
3230 case MSR_IA32_DEBUGCTLMSR:
3231 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3232 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3236 if (data & DEBUGCTL_RESERVED_BITS)
3239 svm->vmcb->save.dbgctl = data;
3240 mark_dirty(svm->vmcb, VMCB_LBR);
3241 if (data & (1ULL<<0))
3242 svm_enable_lbrv(svm);
3244 svm_disable_lbrv(svm);
3246 case MSR_VM_HSAVE_PA:
3247 svm->nested.hsave_msr = data;
3250 return svm_set_vm_cr(vcpu, data);
3252 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3255 return kvm_set_msr_common(vcpu, msr);
3260 static int wrmsr_interception(struct vcpu_svm *svm)
3262 struct msr_data msr;
3263 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3264 u64 data = kvm_read_edx_eax(&svm->vcpu);
3268 msr.host_initiated = false;
3270 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3271 if (kvm_set_msr(&svm->vcpu, &msr)) {
3272 trace_kvm_msr_write_ex(ecx, data);
3273 kvm_inject_gp(&svm->vcpu, 0);
3275 trace_kvm_msr_write(ecx, data);
3276 skip_emulated_instruction(&svm->vcpu);
3281 static int msr_interception(struct vcpu_svm *svm)
3283 if (svm->vmcb->control.exit_info_1)
3284 return wrmsr_interception(svm);
3286 return rdmsr_interception(svm);
3289 static int interrupt_window_interception(struct vcpu_svm *svm)
3291 struct kvm_run *kvm_run = svm->vcpu.run;
3293 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3294 svm_clear_vintr(svm);
3295 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3296 mark_dirty(svm->vmcb, VMCB_INTR);
3297 ++svm->vcpu.stat.irq_window_exits;
3299 * If the user space waits to inject interrupts, exit as soon as
3302 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3303 kvm_run->request_interrupt_window &&
3304 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3305 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3312 static int pause_interception(struct vcpu_svm *svm)
3314 kvm_vcpu_on_spin(&(svm->vcpu));
3318 static int nop_interception(struct vcpu_svm *svm)
3320 skip_emulated_instruction(&(svm->vcpu));
3324 static int monitor_interception(struct vcpu_svm *svm)
3326 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3327 return nop_interception(svm);
3330 static int mwait_interception(struct vcpu_svm *svm)
3332 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3333 return nop_interception(svm);
3336 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3337 [SVM_EXIT_READ_CR0] = cr_interception,
3338 [SVM_EXIT_READ_CR3] = cr_interception,
3339 [SVM_EXIT_READ_CR4] = cr_interception,
3340 [SVM_EXIT_READ_CR8] = cr_interception,
3341 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3342 [SVM_EXIT_WRITE_CR0] = cr_interception,
3343 [SVM_EXIT_WRITE_CR3] = cr_interception,
3344 [SVM_EXIT_WRITE_CR4] = cr_interception,
3345 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3346 [SVM_EXIT_READ_DR0] = dr_interception,
3347 [SVM_EXIT_READ_DR1] = dr_interception,
3348 [SVM_EXIT_READ_DR2] = dr_interception,
3349 [SVM_EXIT_READ_DR3] = dr_interception,
3350 [SVM_EXIT_READ_DR4] = dr_interception,
3351 [SVM_EXIT_READ_DR5] = dr_interception,
3352 [SVM_EXIT_READ_DR6] = dr_interception,
3353 [SVM_EXIT_READ_DR7] = dr_interception,
3354 [SVM_EXIT_WRITE_DR0] = dr_interception,
3355 [SVM_EXIT_WRITE_DR1] = dr_interception,
3356 [SVM_EXIT_WRITE_DR2] = dr_interception,
3357 [SVM_EXIT_WRITE_DR3] = dr_interception,
3358 [SVM_EXIT_WRITE_DR4] = dr_interception,
3359 [SVM_EXIT_WRITE_DR5] = dr_interception,
3360 [SVM_EXIT_WRITE_DR6] = dr_interception,
3361 [SVM_EXIT_WRITE_DR7] = dr_interception,
3362 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3363 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3364 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3365 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3366 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3367 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3368 [SVM_EXIT_INTR] = intr_interception,
3369 [SVM_EXIT_NMI] = nmi_interception,
3370 [SVM_EXIT_SMI] = nop_on_interception,
3371 [SVM_EXIT_INIT] = nop_on_interception,
3372 [SVM_EXIT_VINTR] = interrupt_window_interception,
3373 [SVM_EXIT_RDPMC] = rdpmc_interception,
3374 [SVM_EXIT_CPUID] = cpuid_interception,
3375 [SVM_EXIT_IRET] = iret_interception,
3376 [SVM_EXIT_INVD] = emulate_on_interception,
3377 [SVM_EXIT_PAUSE] = pause_interception,
3378 [SVM_EXIT_HLT] = halt_interception,
3379 [SVM_EXIT_INVLPG] = invlpg_interception,
3380 [SVM_EXIT_INVLPGA] = invlpga_interception,
3381 [SVM_EXIT_IOIO] = io_interception,
3382 [SVM_EXIT_MSR] = msr_interception,
3383 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3384 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3385 [SVM_EXIT_VMRUN] = vmrun_interception,
3386 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3387 [SVM_EXIT_VMLOAD] = vmload_interception,
3388 [SVM_EXIT_VMSAVE] = vmsave_interception,
3389 [SVM_EXIT_STGI] = stgi_interception,
3390 [SVM_EXIT_CLGI] = clgi_interception,
3391 [SVM_EXIT_SKINIT] = skinit_interception,
3392 [SVM_EXIT_WBINVD] = wbinvd_interception,
3393 [SVM_EXIT_MONITOR] = monitor_interception,
3394 [SVM_EXIT_MWAIT] = mwait_interception,
3395 [SVM_EXIT_XSETBV] = xsetbv_interception,
3396 [SVM_EXIT_NPF] = pf_interception,
3397 [SVM_EXIT_RSM] = emulate_on_interception,
3400 static void dump_vmcb(struct kvm_vcpu *vcpu)
3402 struct vcpu_svm *svm = to_svm(vcpu);
3403 struct vmcb_control_area *control = &svm->vmcb->control;
3404 struct vmcb_save_area *save = &svm->vmcb->save;
3406 pr_err("VMCB Control Area:\n");
3407 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3408 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3409 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3410 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3411 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3412 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3413 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3414 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3415 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3416 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3417 pr_err("%-20s%d\n", "asid:", control->asid);
3418 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3419 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3420 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3421 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3422 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3423 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3424 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3425 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3426 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3427 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3428 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3429 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3430 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3431 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3432 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3433 pr_err("VMCB State Save Area:\n");
3434 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3436 save->es.selector, save->es.attrib,
3437 save->es.limit, save->es.base);
3438 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3440 save->cs.selector, save->cs.attrib,
3441 save->cs.limit, save->cs.base);
3442 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3444 save->ss.selector, save->ss.attrib,
3445 save->ss.limit, save->ss.base);
3446 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3448 save->ds.selector, save->ds.attrib,
3449 save->ds.limit, save->ds.base);
3450 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3452 save->fs.selector, save->fs.attrib,
3453 save->fs.limit, save->fs.base);
3454 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3456 save->gs.selector, save->gs.attrib,
3457 save->gs.limit, save->gs.base);
3458 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3460 save->gdtr.selector, save->gdtr.attrib,
3461 save->gdtr.limit, save->gdtr.base);
3462 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3464 save->ldtr.selector, save->ldtr.attrib,
3465 save->ldtr.limit, save->ldtr.base);
3466 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3468 save->idtr.selector, save->idtr.attrib,
3469 save->idtr.limit, save->idtr.base);
3470 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3472 save->tr.selector, save->tr.attrib,
3473 save->tr.limit, save->tr.base);
3474 pr_err("cpl: %d efer: %016llx\n",
3475 save->cpl, save->efer);
3476 pr_err("%-15s %016llx %-13s %016llx\n",
3477 "cr0:", save->cr0, "cr2:", save->cr2);
3478 pr_err("%-15s %016llx %-13s %016llx\n",
3479 "cr3:", save->cr3, "cr4:", save->cr4);
3480 pr_err("%-15s %016llx %-13s %016llx\n",
3481 "dr6:", save->dr6, "dr7:", save->dr7);
3482 pr_err("%-15s %016llx %-13s %016llx\n",
3483 "rip:", save->rip, "rflags:", save->rflags);
3484 pr_err("%-15s %016llx %-13s %016llx\n",
3485 "rsp:", save->rsp, "rax:", save->rax);
3486 pr_err("%-15s %016llx %-13s %016llx\n",
3487 "star:", save->star, "lstar:", save->lstar);
3488 pr_err("%-15s %016llx %-13s %016llx\n",
3489 "cstar:", save->cstar, "sfmask:", save->sfmask);
3490 pr_err("%-15s %016llx %-13s %016llx\n",
3491 "kernel_gs_base:", save->kernel_gs_base,
3492 "sysenter_cs:", save->sysenter_cs);
3493 pr_err("%-15s %016llx %-13s %016llx\n",
3494 "sysenter_esp:", save->sysenter_esp,
3495 "sysenter_eip:", save->sysenter_eip);
3496 pr_err("%-15s %016llx %-13s %016llx\n",
3497 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3498 pr_err("%-15s %016llx %-13s %016llx\n",
3499 "br_from:", save->br_from, "br_to:", save->br_to);
3500 pr_err("%-15s %016llx %-13s %016llx\n",
3501 "excp_from:", save->last_excp_from,
3502 "excp_to:", save->last_excp_to);
3505 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3507 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3509 *info1 = control->exit_info_1;
3510 *info2 = control->exit_info_2;
3513 static int handle_exit(struct kvm_vcpu *vcpu)
3515 struct vcpu_svm *svm = to_svm(vcpu);
3516 struct kvm_run *kvm_run = vcpu->run;
3517 u32 exit_code = svm->vmcb->control.exit_code;
3519 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3520 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3522 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3524 if (unlikely(svm->nested.exit_required)) {
3525 nested_svm_vmexit(svm);
3526 svm->nested.exit_required = false;
3531 if (is_guest_mode(vcpu)) {
3534 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3535 svm->vmcb->control.exit_info_1,
3536 svm->vmcb->control.exit_info_2,
3537 svm->vmcb->control.exit_int_info,
3538 svm->vmcb->control.exit_int_info_err,
3541 vmexit = nested_svm_exit_special(svm);
3543 if (vmexit == NESTED_EXIT_CONTINUE)
3544 vmexit = nested_svm_exit_handled(svm);
3546 if (vmexit == NESTED_EXIT_DONE)
3550 svm_complete_interrupts(svm);
3552 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3553 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3554 kvm_run->fail_entry.hardware_entry_failure_reason
3555 = svm->vmcb->control.exit_code;
3556 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3561 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3562 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3563 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3564 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3565 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3567 __func__, svm->vmcb->control.exit_int_info,
3570 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3571 || !svm_exit_handlers[exit_code]) {
3572 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
3573 kvm_queue_exception(vcpu, UD_VECTOR);
3577 return svm_exit_handlers[exit_code](svm);
3580 static void reload_tss(struct kvm_vcpu *vcpu)
3582 int cpu = raw_smp_processor_id();
3584 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3585 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3589 static void pre_svm_run(struct vcpu_svm *svm)
3591 int cpu = raw_smp_processor_id();
3593 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3595 /* FIXME: handle wraparound of asid_generation */
3596 if (svm->asid_generation != sd->asid_generation)
3600 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3602 struct vcpu_svm *svm = to_svm(vcpu);
3604 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3605 vcpu->arch.hflags |= HF_NMI_MASK;
3606 set_intercept(svm, INTERCEPT_IRET);
3607 ++vcpu->stat.nmi_injections;
3610 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3612 struct vmcb_control_area *control;
3614 control = &svm->vmcb->control;
3615 control->int_vector = irq;
3616 control->int_ctl &= ~V_INTR_PRIO_MASK;
3617 control->int_ctl |= V_IRQ_MASK |
3618 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3619 mark_dirty(svm->vmcb, VMCB_INTR);
3622 static void svm_set_irq(struct kvm_vcpu *vcpu)
3624 struct vcpu_svm *svm = to_svm(vcpu);
3626 BUG_ON(!(gif_set(svm)));
3628 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3629 ++vcpu->stat.irq_injections;
3631 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3632 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3635 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3637 struct vcpu_svm *svm = to_svm(vcpu);
3639 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3642 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3648 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3651 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3656 static int svm_vm_has_apicv(struct kvm *kvm)
3661 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3666 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3671 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3673 struct vcpu_svm *svm = to_svm(vcpu);
3674 struct vmcb *vmcb = svm->vmcb;
3676 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3677 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3678 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3683 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3685 struct vcpu_svm *svm = to_svm(vcpu);
3687 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3690 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3692 struct vcpu_svm *svm = to_svm(vcpu);
3695 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3696 set_intercept(svm, INTERCEPT_IRET);
3698 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3699 clr_intercept(svm, INTERCEPT_IRET);
3703 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3705 struct vcpu_svm *svm = to_svm(vcpu);
3706 struct vmcb *vmcb = svm->vmcb;
3709 if (!gif_set(svm) ||
3710 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3713 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3715 if (is_guest_mode(vcpu))
3716 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3721 static void enable_irq_window(struct kvm_vcpu *vcpu)
3723 struct vcpu_svm *svm = to_svm(vcpu);
3726 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3727 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3728 * get that intercept, this function will be called again though and
3729 * we'll get the vintr intercept.
3731 if (gif_set(svm) && nested_svm_intr(svm)) {
3733 svm_inject_irq(svm, 0x0);
3737 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3739 struct vcpu_svm *svm = to_svm(vcpu);
3741 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3743 return; /* IRET will cause a vm exit */
3746 * Something prevents NMI from been injected. Single step over possible
3747 * problem (IRET or exception injection or interrupt shadow)
3749 svm->nmi_singlestep = true;
3750 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3751 update_db_bp_intercept(vcpu);
3754 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3759 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3761 struct vcpu_svm *svm = to_svm(vcpu);
3763 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3764 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3766 svm->asid_generation--;
3769 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3773 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3775 struct vcpu_svm *svm = to_svm(vcpu);
3777 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3780 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3781 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3782 kvm_set_cr8(vcpu, cr8);
3786 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3788 struct vcpu_svm *svm = to_svm(vcpu);
3791 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3794 cr8 = kvm_get_cr8(vcpu);
3795 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3796 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3799 static void svm_complete_interrupts(struct vcpu_svm *svm)
3803 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3804 unsigned int3_injected = svm->int3_injected;
3806 svm->int3_injected = 0;
3809 * If we've made progress since setting HF_IRET_MASK, we've
3810 * executed an IRET and can allow NMI injection.
3812 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3813 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3814 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3815 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3818 svm->vcpu.arch.nmi_injected = false;
3819 kvm_clear_exception_queue(&svm->vcpu);
3820 kvm_clear_interrupt_queue(&svm->vcpu);
3822 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3825 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3827 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3828 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3831 case SVM_EXITINTINFO_TYPE_NMI:
3832 svm->vcpu.arch.nmi_injected = true;
3834 case SVM_EXITINTINFO_TYPE_EXEPT:
3836 * In case of software exceptions, do not reinject the vector,
3837 * but re-execute the instruction instead. Rewind RIP first
3838 * if we emulated INT3 before.
3840 if (kvm_exception_is_soft(vector)) {
3841 if (vector == BP_VECTOR && int3_injected &&
3842 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3843 kvm_rip_write(&svm->vcpu,
3844 kvm_rip_read(&svm->vcpu) -
3848 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3849 u32 err = svm->vmcb->control.exit_int_info_err;
3850 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3853 kvm_requeue_exception(&svm->vcpu, vector);
3855 case SVM_EXITINTINFO_TYPE_INTR:
3856 kvm_queue_interrupt(&svm->vcpu, vector, false);
3863 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3865 struct vcpu_svm *svm = to_svm(vcpu);
3866 struct vmcb_control_area *control = &svm->vmcb->control;
3868 control->exit_int_info = control->event_inj;
3869 control->exit_int_info_err = control->event_inj_err;
3870 control->event_inj = 0;
3871 svm_complete_interrupts(svm);
3874 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3876 struct vcpu_svm *svm = to_svm(vcpu);
3878 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3879 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3880 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3883 * A vmexit emulation is required before the vcpu can be executed
3886 if (unlikely(svm->nested.exit_required))
3891 sync_lapic_to_cr8(vcpu);
3893 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3900 "push %%" _ASM_BP "; \n\t"
3901 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3902 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3903 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3904 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3905 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3906 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3907 #ifdef CONFIG_X86_64
3908 "mov %c[r8](%[svm]), %%r8 \n\t"
3909 "mov %c[r9](%[svm]), %%r9 \n\t"
3910 "mov %c[r10](%[svm]), %%r10 \n\t"
3911 "mov %c[r11](%[svm]), %%r11 \n\t"
3912 "mov %c[r12](%[svm]), %%r12 \n\t"
3913 "mov %c[r13](%[svm]), %%r13 \n\t"
3914 "mov %c[r14](%[svm]), %%r14 \n\t"
3915 "mov %c[r15](%[svm]), %%r15 \n\t"
3918 /* Enter guest mode */
3919 "push %%" _ASM_AX " \n\t"
3920 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3921 __ex(SVM_VMLOAD) "\n\t"
3922 __ex(SVM_VMRUN) "\n\t"
3923 __ex(SVM_VMSAVE) "\n\t"
3924 "pop %%" _ASM_AX " \n\t"
3926 /* Save guest registers, load host registers */
3927 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3928 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3929 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3930 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3931 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3932 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3933 #ifdef CONFIG_X86_64
3934 "mov %%r8, %c[r8](%[svm]) \n\t"
3935 "mov %%r9, %c[r9](%[svm]) \n\t"
3936 "mov %%r10, %c[r10](%[svm]) \n\t"
3937 "mov %%r11, %c[r11](%[svm]) \n\t"
3938 "mov %%r12, %c[r12](%[svm]) \n\t"
3939 "mov %%r13, %c[r13](%[svm]) \n\t"
3940 "mov %%r14, %c[r14](%[svm]) \n\t"
3941 "mov %%r15, %c[r15](%[svm]) \n\t"
3946 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3947 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3948 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3949 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3950 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3951 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3952 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3953 #ifdef CONFIG_X86_64
3954 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3955 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3956 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3957 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3958 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3959 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3960 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3961 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3964 #ifdef CONFIG_X86_64
3965 , "rbx", "rcx", "rdx", "rsi", "rdi"
3966 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3968 , "ebx", "ecx", "edx", "esi", "edi"
3972 #ifdef CONFIG_X86_64
3973 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3975 loadsegment(fs, svm->host.fs);
3976 #ifndef CONFIG_X86_32_LAZY_GS
3977 loadsegment(gs, svm->host.gs);
3983 local_irq_disable();
3985 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3986 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3987 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3988 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3990 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3992 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3993 kvm_before_handle_nmi(&svm->vcpu);
3997 /* Any pending NMI will happen here */
3999 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4000 kvm_after_handle_nmi(&svm->vcpu);
4002 sync_cr8_to_lapic(vcpu);
4006 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4008 /* if exit due to PF check for async PF */
4009 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4010 svm->apf_reason = kvm_read_and_reset_pf_reason();
4013 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4014 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4018 * We need to handle MC intercepts here before the vcpu has a chance to
4019 * change the physical cpu
4021 if (unlikely(svm->vmcb->control.exit_code ==
4022 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4023 svm_handle_mce(svm);
4025 mark_all_clean(svm->vmcb);
4028 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4030 struct vcpu_svm *svm = to_svm(vcpu);
4032 svm->vmcb->save.cr3 = root;
4033 mark_dirty(svm->vmcb, VMCB_CR);
4034 svm_flush_tlb(vcpu);
4037 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4039 struct vcpu_svm *svm = to_svm(vcpu);
4041 svm->vmcb->control.nested_cr3 = root;
4042 mark_dirty(svm->vmcb, VMCB_NPT);
4044 /* Also sync guest cr3 here in case we live migrate */
4045 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4046 mark_dirty(svm->vmcb, VMCB_CR);
4048 svm_flush_tlb(vcpu);
4051 static int is_disabled(void)
4055 rdmsrl(MSR_VM_CR, vm_cr);
4056 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4063 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4066 * Patch in the VMMCALL instruction:
4068 hypercall[0] = 0x0f;
4069 hypercall[1] = 0x01;
4070 hypercall[2] = 0xd9;
4073 static void svm_check_processor_compat(void *rtn)
4078 static bool svm_cpu_has_accelerated_tpr(void)
4083 static bool svm_has_high_real_mode_segbase(void)
4088 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4093 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4097 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4102 entry->ecx |= (1 << 2); /* Set SVM bit */
4105 entry->eax = 1; /* SVM revision 1 */
4106 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4107 ASID emulation to nested SVM */
4108 entry->ecx = 0; /* Reserved */
4109 entry->edx = 0; /* Per default do not support any
4110 additional features */
4112 /* Support next_rip if host supports it */
4113 if (boot_cpu_has(X86_FEATURE_NRIPS))
4114 entry->edx |= SVM_FEATURE_NRIP;
4116 /* Support NPT for the guest if enabled */
4118 entry->edx |= SVM_FEATURE_NPT;
4124 static int svm_get_lpage_level(void)
4126 return PT_PDPE_LEVEL;
4129 static bool svm_rdtscp_supported(void)
4134 static bool svm_invpcid_supported(void)
4139 static bool svm_mpx_supported(void)
4144 static bool svm_xsaves_supported(void)
4149 static bool svm_has_wbinvd_exit(void)
4154 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4156 struct vcpu_svm *svm = to_svm(vcpu);
4158 set_exception_intercept(svm, NM_VECTOR);
4159 update_cr0_intercept(svm);
4162 #define PRE_EX(exit) { .exit_code = (exit), \
4163 .stage = X86_ICPT_PRE_EXCEPT, }
4164 #define POST_EX(exit) { .exit_code = (exit), \
4165 .stage = X86_ICPT_POST_EXCEPT, }
4166 #define POST_MEM(exit) { .exit_code = (exit), \
4167 .stage = X86_ICPT_POST_MEMACCESS, }
4169 static const struct __x86_intercept {
4171 enum x86_intercept_stage stage;
4172 } x86_intercept_map[] = {
4173 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4174 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4175 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4176 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4177 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4178 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4179 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4180 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4181 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4182 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4183 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4184 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4185 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4186 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4187 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4188 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4189 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4190 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4191 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4192 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4193 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4194 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4195 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4196 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4197 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4198 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4199 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4200 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4201 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4202 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4203 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4204 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4205 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4206 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4207 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4208 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4209 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4210 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4211 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4212 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4213 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4214 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4215 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4216 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4217 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4218 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4225 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4226 struct x86_instruction_info *info,
4227 enum x86_intercept_stage stage)
4229 struct vcpu_svm *svm = to_svm(vcpu);
4230 int vmexit, ret = X86EMUL_CONTINUE;
4231 struct __x86_intercept icpt_info;
4232 struct vmcb *vmcb = svm->vmcb;
4234 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4237 icpt_info = x86_intercept_map[info->intercept];
4239 if (stage != icpt_info.stage)
4242 switch (icpt_info.exit_code) {
4243 case SVM_EXIT_READ_CR0:
4244 if (info->intercept == x86_intercept_cr_read)
4245 icpt_info.exit_code += info->modrm_reg;
4247 case SVM_EXIT_WRITE_CR0: {
4248 unsigned long cr0, val;
4251 if (info->intercept == x86_intercept_cr_write)
4252 icpt_info.exit_code += info->modrm_reg;
4254 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4255 info->intercept == x86_intercept_clts)
4258 intercept = svm->nested.intercept;
4260 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4263 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4264 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4266 if (info->intercept == x86_intercept_lmsw) {
4269 /* lmsw can't clear PE - catch this here */
4270 if (cr0 & X86_CR0_PE)
4275 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4279 case SVM_EXIT_READ_DR0:
4280 case SVM_EXIT_WRITE_DR0:
4281 icpt_info.exit_code += info->modrm_reg;
4284 if (info->intercept == x86_intercept_wrmsr)
4285 vmcb->control.exit_info_1 = 1;
4287 vmcb->control.exit_info_1 = 0;
4289 case SVM_EXIT_PAUSE:
4291 * We get this for NOP only, but pause
4292 * is rep not, check this here
4294 if (info->rep_prefix != REPE_PREFIX)
4296 case SVM_EXIT_IOIO: {
4300 if (info->intercept == x86_intercept_in ||
4301 info->intercept == x86_intercept_ins) {
4302 exit_info = ((info->src_val & 0xffff) << 16) |
4304 bytes = info->dst_bytes;
4306 exit_info = (info->dst_val & 0xffff) << 16;
4307 bytes = info->src_bytes;
4310 if (info->intercept == x86_intercept_outs ||
4311 info->intercept == x86_intercept_ins)
4312 exit_info |= SVM_IOIO_STR_MASK;
4314 if (info->rep_prefix)
4315 exit_info |= SVM_IOIO_REP_MASK;
4317 bytes = min(bytes, 4u);
4319 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4321 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4323 vmcb->control.exit_info_1 = exit_info;
4324 vmcb->control.exit_info_2 = info->next_rip;
4332 vmcb->control.next_rip = info->next_rip;
4333 vmcb->control.exit_code = icpt_info.exit_code;
4334 vmexit = nested_svm_exit_handled(svm);
4336 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4343 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4348 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4352 static struct kvm_x86_ops svm_x86_ops = {
4353 .cpu_has_kvm_support = has_svm,
4354 .disabled_by_bios = is_disabled,
4355 .hardware_setup = svm_hardware_setup,
4356 .hardware_unsetup = svm_hardware_unsetup,
4357 .check_processor_compatibility = svm_check_processor_compat,
4358 .hardware_enable = svm_hardware_enable,
4359 .hardware_disable = svm_hardware_disable,
4360 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4361 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
4363 .vcpu_create = svm_create_vcpu,
4364 .vcpu_free = svm_free_vcpu,
4365 .vcpu_reset = svm_vcpu_reset,
4367 .prepare_guest_switch = svm_prepare_guest_switch,
4368 .vcpu_load = svm_vcpu_load,
4369 .vcpu_put = svm_vcpu_put,
4371 .update_db_bp_intercept = update_db_bp_intercept,
4372 .get_msr = svm_get_msr,
4373 .set_msr = svm_set_msr,
4374 .get_segment_base = svm_get_segment_base,
4375 .get_segment = svm_get_segment,
4376 .set_segment = svm_set_segment,
4377 .get_cpl = svm_get_cpl,
4378 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4379 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4380 .decache_cr3 = svm_decache_cr3,
4381 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4382 .set_cr0 = svm_set_cr0,
4383 .set_cr3 = svm_set_cr3,
4384 .set_cr4 = svm_set_cr4,
4385 .set_efer = svm_set_efer,
4386 .get_idt = svm_get_idt,
4387 .set_idt = svm_set_idt,
4388 .get_gdt = svm_get_gdt,
4389 .set_gdt = svm_set_gdt,
4390 .get_dr6 = svm_get_dr6,
4391 .set_dr6 = svm_set_dr6,
4392 .set_dr7 = svm_set_dr7,
4393 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4394 .cache_reg = svm_cache_reg,
4395 .get_rflags = svm_get_rflags,
4396 .set_rflags = svm_set_rflags,
4397 .fpu_activate = svm_fpu_activate,
4398 .fpu_deactivate = svm_fpu_deactivate,
4400 .tlb_flush = svm_flush_tlb,
4402 .run = svm_vcpu_run,
4403 .handle_exit = handle_exit,
4404 .skip_emulated_instruction = skip_emulated_instruction,
4405 .set_interrupt_shadow = svm_set_interrupt_shadow,
4406 .get_interrupt_shadow = svm_get_interrupt_shadow,
4407 .patch_hypercall = svm_patch_hypercall,
4408 .set_irq = svm_set_irq,
4409 .set_nmi = svm_inject_nmi,
4410 .queue_exception = svm_queue_exception,
4411 .cancel_injection = svm_cancel_injection,
4412 .interrupt_allowed = svm_interrupt_allowed,
4413 .nmi_allowed = svm_nmi_allowed,
4414 .get_nmi_mask = svm_get_nmi_mask,
4415 .set_nmi_mask = svm_set_nmi_mask,
4416 .enable_nmi_window = enable_nmi_window,
4417 .enable_irq_window = enable_irq_window,
4418 .update_cr8_intercept = update_cr8_intercept,
4419 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4420 .vm_has_apicv = svm_vm_has_apicv,
4421 .load_eoi_exitmap = svm_load_eoi_exitmap,
4422 .sync_pir_to_irr = svm_sync_pir_to_irr,
4424 .set_tss_addr = svm_set_tss_addr,
4425 .get_tdp_level = get_npt_level,
4426 .get_mt_mask = svm_get_mt_mask,
4428 .get_exit_info = svm_get_exit_info,
4430 .get_lpage_level = svm_get_lpage_level,
4432 .cpuid_update = svm_cpuid_update,
4434 .rdtscp_supported = svm_rdtscp_supported,
4435 .invpcid_supported = svm_invpcid_supported,
4436 .mpx_supported = svm_mpx_supported,
4437 .xsaves_supported = svm_xsaves_supported,
4439 .set_supported_cpuid = svm_set_supported_cpuid,
4441 .has_wbinvd_exit = svm_has_wbinvd_exit,
4443 .set_tsc_khz = svm_set_tsc_khz,
4444 .read_tsc_offset = svm_read_tsc_offset,
4445 .write_tsc_offset = svm_write_tsc_offset,
4446 .adjust_tsc_offset = svm_adjust_tsc_offset,
4447 .compute_tsc_offset = svm_compute_tsc_offset,
4448 .read_l1_tsc = svm_read_l1_tsc,
4450 .set_tdp_cr3 = set_tdp_cr3,
4452 .check_intercept = svm_check_intercept,
4453 .handle_external_intr = svm_handle_external_intr,
4455 .sched_in = svm_sched_in,
4458 static int __init svm_init(void)
4460 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4461 __alignof__(struct vcpu_svm), THIS_MODULE);
4464 static void __exit svm_exit(void)
4469 module_init(svm_init)
4470 module_exit(svm_exit)