2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
35 #include <asm/perf_event.h>
36 #include <asm/tlbflush.h>
38 #include <asm/debugreg.h>
39 #include <asm/kvm_para.h>
41 #include <asm/virtext.h>
44 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 MODULE_AUTHOR("Qumranet");
47 MODULE_LICENSE("GPL");
49 static const struct x86_cpu_id svm_cpu_id[] = {
50 X86_FEATURE_MATCH(X86_FEATURE_SVM),
53 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
55 #define IOPM_ALLOC_ORDER 2
56 #define MSRPM_ALLOC_ORDER 1
58 #define SEG_TYPE_LDT 2
59 #define SEG_TYPE_BUSY_TSS16 3
61 #define SVM_FEATURE_NPT (1 << 0)
62 #define SVM_FEATURE_LBRV (1 << 1)
63 #define SVM_FEATURE_SVML (1 << 2)
64 #define SVM_FEATURE_NRIP (1 << 3)
65 #define SVM_FEATURE_TSC_RATE (1 << 4)
66 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
67 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
68 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
69 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
71 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
72 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
73 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
75 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
77 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
78 #define TSC_RATIO_MIN 0x0000000000000001ULL
79 #define TSC_RATIO_MAX 0x000000ffffffffffULL
81 static bool erratum_383_found __read_mostly;
83 static const u32 host_save_user_msrs[] = {
85 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
88 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
91 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
101 /* These are the merged vectors */
104 /* gpa pointers to the real vectors */
108 /* A VMEXIT is required but not yet emulated */
111 /* cache for intercepts of the guest */
114 u32 intercept_exceptions;
117 /* Nested Paging related state */
121 #define MSRPM_OFFSETS 16
122 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
125 * Set osvw_len to higher value when updated Revision Guides
126 * are published and we know what the new status bits are
128 static uint64_t osvw_len = 4, osvw_status;
131 struct kvm_vcpu vcpu;
133 unsigned long vmcb_pa;
134 struct svm_cpu_data *svm_data;
135 uint64_t asid_generation;
136 uint64_t sysenter_esp;
137 uint64_t sysenter_eip;
141 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
153 struct nested_state nested;
157 unsigned int3_injected;
158 unsigned long int3_rip;
161 /* cached guest cpuid flags for faster access */
162 bool nrips_enabled : 1;
165 static DEFINE_PER_CPU(u64, current_tsc_ratio);
166 #define TSC_RATIO_DEFAULT 0x0100000000ULL
168 #define MSR_INVALID 0xffffffffU
170 static const struct svm_direct_access_msrs {
171 u32 index; /* Index of the MSR */
172 bool always; /* True if intercept is always on */
173 } direct_access_msrs[] = {
174 { .index = MSR_STAR, .always = true },
175 { .index = MSR_IA32_SYSENTER_CS, .always = true },
177 { .index = MSR_GS_BASE, .always = true },
178 { .index = MSR_FS_BASE, .always = true },
179 { .index = MSR_KERNEL_GS_BASE, .always = true },
180 { .index = MSR_LSTAR, .always = true },
181 { .index = MSR_CSTAR, .always = true },
182 { .index = MSR_SYSCALL_MASK, .always = true },
184 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
185 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
186 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
187 { .index = MSR_IA32_LASTINTTOIP, .always = false },
188 { .index = MSR_INVALID, .always = false },
191 /* enable NPT for AMD64 and X86 with PAE */
192 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
193 static bool npt_enabled = true;
195 static bool npt_enabled;
198 /* allow nested paging (virtualized MMU) for all guests */
199 static int npt = true;
200 module_param(npt, int, S_IRUGO);
202 /* allow nested virtualization in KVM/SVM */
203 static int nested = true;
204 module_param(nested, int, S_IRUGO);
206 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
207 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
208 static void svm_complete_interrupts(struct vcpu_svm *svm);
210 static int nested_svm_exit_handled(struct vcpu_svm *svm);
211 static int nested_svm_intercept(struct vcpu_svm *svm);
212 static int nested_svm_vmexit(struct vcpu_svm *svm);
213 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
214 bool has_error_code, u32 error_code);
217 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
218 pause filter count */
219 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
220 VMCB_ASID, /* ASID */
221 VMCB_INTR, /* int_ctl, int_vector */
222 VMCB_NPT, /* npt_en, nCR3, gPAT */
223 VMCB_CR, /* CR0, CR3, CR4, EFER */
224 VMCB_DR, /* DR6, DR7 */
225 VMCB_DT, /* GDT, IDT */
226 VMCB_SEG, /* CS, DS, SS, ES, CPL */
227 VMCB_CR2, /* CR2 only */
228 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
232 /* TPR and CR2 are always written before VMRUN */
233 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
235 static inline void mark_all_dirty(struct vmcb *vmcb)
237 vmcb->control.clean = 0;
240 static inline void mark_all_clean(struct vmcb *vmcb)
242 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
243 & ~VMCB_ALWAYS_DIRTY_MASK;
246 static inline void mark_dirty(struct vmcb *vmcb, int bit)
248 vmcb->control.clean &= ~(1 << bit);
251 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
253 return container_of(vcpu, struct vcpu_svm, vcpu);
256 static void recalc_intercepts(struct vcpu_svm *svm)
258 struct vmcb_control_area *c, *h;
259 struct nested_state *g;
261 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
263 if (!is_guest_mode(&svm->vcpu))
266 c = &svm->vmcb->control;
267 h = &svm->nested.hsave->control;
270 c->intercept_cr = h->intercept_cr | g->intercept_cr;
271 c->intercept_dr = h->intercept_dr | g->intercept_dr;
272 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
273 c->intercept = h->intercept | g->intercept;
276 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
278 if (is_guest_mode(&svm->vcpu))
279 return svm->nested.hsave;
284 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
286 struct vmcb *vmcb = get_host_vmcb(svm);
288 vmcb->control.intercept_cr |= (1U << bit);
290 recalc_intercepts(svm);
293 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
295 struct vmcb *vmcb = get_host_vmcb(svm);
297 vmcb->control.intercept_cr &= ~(1U << bit);
299 recalc_intercepts(svm);
302 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
304 struct vmcb *vmcb = get_host_vmcb(svm);
306 return vmcb->control.intercept_cr & (1U << bit);
309 static inline void set_dr_intercepts(struct vcpu_svm *svm)
311 struct vmcb *vmcb = get_host_vmcb(svm);
313 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
314 | (1 << INTERCEPT_DR1_READ)
315 | (1 << INTERCEPT_DR2_READ)
316 | (1 << INTERCEPT_DR3_READ)
317 | (1 << INTERCEPT_DR4_READ)
318 | (1 << INTERCEPT_DR5_READ)
319 | (1 << INTERCEPT_DR6_READ)
320 | (1 << INTERCEPT_DR7_READ)
321 | (1 << INTERCEPT_DR0_WRITE)
322 | (1 << INTERCEPT_DR1_WRITE)
323 | (1 << INTERCEPT_DR2_WRITE)
324 | (1 << INTERCEPT_DR3_WRITE)
325 | (1 << INTERCEPT_DR4_WRITE)
326 | (1 << INTERCEPT_DR5_WRITE)
327 | (1 << INTERCEPT_DR6_WRITE)
328 | (1 << INTERCEPT_DR7_WRITE);
330 recalc_intercepts(svm);
333 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
335 struct vmcb *vmcb = get_host_vmcb(svm);
337 vmcb->control.intercept_dr = 0;
339 recalc_intercepts(svm);
342 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
344 struct vmcb *vmcb = get_host_vmcb(svm);
346 vmcb->control.intercept_exceptions |= (1U << bit);
348 recalc_intercepts(svm);
351 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
353 struct vmcb *vmcb = get_host_vmcb(svm);
355 vmcb->control.intercept_exceptions &= ~(1U << bit);
357 recalc_intercepts(svm);
360 static inline void set_intercept(struct vcpu_svm *svm, int bit)
362 struct vmcb *vmcb = get_host_vmcb(svm);
364 vmcb->control.intercept |= (1ULL << bit);
366 recalc_intercepts(svm);
369 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
371 struct vmcb *vmcb = get_host_vmcb(svm);
373 vmcb->control.intercept &= ~(1ULL << bit);
375 recalc_intercepts(svm);
378 static inline void enable_gif(struct vcpu_svm *svm)
380 svm->vcpu.arch.hflags |= HF_GIF_MASK;
383 static inline void disable_gif(struct vcpu_svm *svm)
385 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
388 static inline bool gif_set(struct vcpu_svm *svm)
390 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
393 static unsigned long iopm_base;
395 struct kvm_ldttss_desc {
398 unsigned base1:8, type:5, dpl:2, p:1;
399 unsigned limit1:4, zero0:3, g:1, base2:8;
402 } __attribute__((packed));
404 struct svm_cpu_data {
410 struct kvm_ldttss_desc *tss_desc;
412 struct page *save_area;
415 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
417 struct svm_init_data {
422 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
424 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
425 #define MSRS_RANGE_SIZE 2048
426 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
428 static u32 svm_msrpm_offset(u32 msr)
433 for (i = 0; i < NUM_MSR_MAPS; i++) {
434 if (msr < msrpm_ranges[i] ||
435 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
438 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
439 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
441 /* Now we have the u8 offset - but need the u32 offset */
445 /* MSR not in any range */
449 #define MAX_INST_SIZE 15
451 static inline void clgi(void)
453 asm volatile (__ex(SVM_CLGI));
456 static inline void stgi(void)
458 asm volatile (__ex(SVM_STGI));
461 static inline void invlpga(unsigned long addr, u32 asid)
463 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
466 static int get_npt_level(void)
469 return PT64_ROOT_LEVEL;
471 return PT32E_ROOT_LEVEL;
475 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
477 vcpu->arch.efer = efer;
478 if (!npt_enabled && !(efer & EFER_LMA))
481 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
482 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
485 static int is_external_interrupt(u32 info)
487 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
488 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
491 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
493 struct vcpu_svm *svm = to_svm(vcpu);
496 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
497 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
501 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
503 struct vcpu_svm *svm = to_svm(vcpu);
506 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
508 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
512 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
514 struct vcpu_svm *svm = to_svm(vcpu);
516 if (svm->vmcb->control.next_rip != 0) {
517 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
518 svm->next_rip = svm->vmcb->control.next_rip;
521 if (!svm->next_rip) {
522 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
524 printk(KERN_DEBUG "%s: NOP\n", __func__);
527 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
528 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
529 __func__, kvm_rip_read(vcpu), svm->next_rip);
531 kvm_rip_write(vcpu, svm->next_rip);
532 svm_set_interrupt_shadow(vcpu, 0);
535 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
536 bool has_error_code, u32 error_code,
539 struct vcpu_svm *svm = to_svm(vcpu);
542 * If we are within a nested VM we'd better #VMEXIT and let the guest
543 * handle the exception
546 nested_svm_check_exception(svm, nr, has_error_code, error_code))
549 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
550 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
553 * For guest debugging where we have to reinject #BP if some
554 * INT3 is guest-owned:
555 * Emulate nRIP by moving RIP forward. Will fail if injection
556 * raises a fault that is not intercepted. Still better than
557 * failing in all cases.
559 skip_emulated_instruction(&svm->vcpu);
560 rip = kvm_rip_read(&svm->vcpu);
561 svm->int3_rip = rip + svm->vmcb->save.cs.base;
562 svm->int3_injected = rip - old_rip;
565 svm->vmcb->control.event_inj = nr
567 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
568 | SVM_EVTINJ_TYPE_EXEPT;
569 svm->vmcb->control.event_inj_err = error_code;
572 static void svm_init_erratum_383(void)
578 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
581 /* Use _safe variants to not break nested virtualization */
582 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
588 low = lower_32_bits(val);
589 high = upper_32_bits(val);
591 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
593 erratum_383_found = true;
596 static void svm_init_osvw(struct kvm_vcpu *vcpu)
599 * Guests should see errata 400 and 415 as fixed (assuming that
600 * HLT and IO instructions are intercepted).
602 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
603 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
606 * By increasing VCPU's osvw.length to 3 we are telling the guest that
607 * all osvw.status bits inside that length, including bit 0 (which is
608 * reserved for erratum 298), are valid. However, if host processor's
609 * osvw_len is 0 then osvw_status[0] carries no information. We need to
610 * be conservative here and therefore we tell the guest that erratum 298
611 * is present (because we really don't know).
613 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
614 vcpu->arch.osvw.status |= 1;
617 static int has_svm(void)
621 if (!cpu_has_svm(&msg)) {
622 printk(KERN_INFO "has_svm: %s\n", msg);
629 static void svm_hardware_disable(void)
631 /* Make sure we clean up behind us */
632 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
633 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
637 amd_pmu_disable_virt();
640 static int svm_hardware_enable(void)
643 struct svm_cpu_data *sd;
645 struct desc_ptr gdt_descr;
646 struct desc_struct *gdt;
647 int me = raw_smp_processor_id();
649 rdmsrl(MSR_EFER, efer);
650 if (efer & EFER_SVME)
654 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
657 sd = per_cpu(svm_data, me);
659 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
663 sd->asid_generation = 1;
664 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
665 sd->next_asid = sd->max_asid + 1;
667 native_store_gdt(&gdt_descr);
668 gdt = (struct desc_struct *)gdt_descr.address;
669 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
671 wrmsrl(MSR_EFER, efer | EFER_SVME);
673 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
675 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
676 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
677 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
684 * Note that it is possible to have a system with mixed processor
685 * revisions and therefore different OSVW bits. If bits are not the same
686 * on different processors then choose the worst case (i.e. if erratum
687 * is present on one processor and not on another then assume that the
688 * erratum is present everywhere).
690 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
691 uint64_t len, status = 0;
694 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
696 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
700 osvw_status = osvw_len = 0;
704 osvw_status |= status;
705 osvw_status &= (1ULL << osvw_len) - 1;
708 osvw_status = osvw_len = 0;
710 svm_init_erratum_383();
712 amd_pmu_enable_virt();
717 static void svm_cpu_uninit(int cpu)
719 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
724 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
725 __free_page(sd->save_area);
729 static int svm_cpu_init(int cpu)
731 struct svm_cpu_data *sd;
734 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
738 sd->save_area = alloc_page(GFP_KERNEL);
743 per_cpu(svm_data, cpu) = sd;
753 static bool valid_msr_intercept(u32 index)
757 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
758 if (direct_access_msrs[i].index == index)
764 static void set_msr_interception(u32 *msrpm, unsigned msr,
767 u8 bit_read, bit_write;
772 * If this warning triggers extend the direct_access_msrs list at the
773 * beginning of the file
775 WARN_ON(!valid_msr_intercept(msr));
777 offset = svm_msrpm_offset(msr);
778 bit_read = 2 * (msr & 0x0f);
779 bit_write = 2 * (msr & 0x0f) + 1;
782 BUG_ON(offset == MSR_INVALID);
784 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
785 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
790 static void svm_vcpu_init_msrpm(u32 *msrpm)
794 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
796 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
797 if (!direct_access_msrs[i].always)
800 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
804 static void add_msr_offset(u32 offset)
808 for (i = 0; i < MSRPM_OFFSETS; ++i) {
810 /* Offset already in list? */
811 if (msrpm_offsets[i] == offset)
814 /* Slot used by another offset? */
815 if (msrpm_offsets[i] != MSR_INVALID)
818 /* Add offset to list */
819 msrpm_offsets[i] = offset;
825 * If this BUG triggers the msrpm_offsets table has an overflow. Just
826 * increase MSRPM_OFFSETS in this case.
831 static void init_msrpm_offsets(void)
835 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
837 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
840 offset = svm_msrpm_offset(direct_access_msrs[i].index);
841 BUG_ON(offset == MSR_INVALID);
843 add_msr_offset(offset);
847 static void svm_enable_lbrv(struct vcpu_svm *svm)
849 u32 *msrpm = svm->msrpm;
851 svm->vmcb->control.lbr_ctl = 1;
852 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
853 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
854 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
855 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
858 static void svm_disable_lbrv(struct vcpu_svm *svm)
860 u32 *msrpm = svm->msrpm;
862 svm->vmcb->control.lbr_ctl = 0;
863 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
864 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
865 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
866 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
869 static __init int svm_hardware_setup(void)
872 struct page *iopm_pages;
876 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
881 iopm_va = page_address(iopm_pages);
882 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
883 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
885 init_msrpm_offsets();
887 if (boot_cpu_has(X86_FEATURE_NX))
888 kvm_enable_efer_bits(EFER_NX);
890 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
891 kvm_enable_efer_bits(EFER_FFXSR);
893 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
894 kvm_has_tsc_control = true;
895 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
896 kvm_tsc_scaling_ratio_frac_bits = 32;
900 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
901 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
904 for_each_possible_cpu(cpu) {
905 r = svm_cpu_init(cpu);
910 if (!boot_cpu_has(X86_FEATURE_NPT))
913 if (npt_enabled && !npt) {
914 printk(KERN_INFO "kvm: Nested Paging disabled\n");
919 printk(KERN_INFO "kvm: Nested Paging enabled\n");
927 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
932 static __exit void svm_hardware_unsetup(void)
936 for_each_possible_cpu(cpu)
939 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
943 static void init_seg(struct vmcb_seg *seg)
946 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
947 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
952 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
955 seg->attrib = SVM_SELECTOR_P_MASK | type;
960 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
962 struct vcpu_svm *svm = to_svm(vcpu);
964 return svm->vmcb->control.tsc_offset;
967 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
969 struct vcpu_svm *svm = to_svm(vcpu);
970 u64 g_tsc_offset = 0;
972 if (is_guest_mode(vcpu)) {
973 g_tsc_offset = svm->vmcb->control.tsc_offset -
974 svm->nested.hsave->control.tsc_offset;
975 svm->nested.hsave->control.tsc_offset = offset;
977 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
978 svm->vmcb->control.tsc_offset,
981 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
983 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
986 static void svm_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
988 struct vcpu_svm *svm = to_svm(vcpu);
990 svm->vmcb->control.tsc_offset += adjustment;
991 if (is_guest_mode(vcpu))
992 svm->nested.hsave->control.tsc_offset += adjustment;
994 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
995 svm->vmcb->control.tsc_offset - adjustment,
996 svm->vmcb->control.tsc_offset);
998 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1001 static void init_vmcb(struct vcpu_svm *svm)
1003 struct vmcb_control_area *control = &svm->vmcb->control;
1004 struct vmcb_save_area *save = &svm->vmcb->save;
1006 svm->vcpu.fpu_active = 1;
1007 svm->vcpu.arch.hflags = 0;
1009 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1010 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1011 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1012 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1013 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1014 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1015 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1017 set_dr_intercepts(svm);
1019 set_exception_intercept(svm, PF_VECTOR);
1020 set_exception_intercept(svm, UD_VECTOR);
1021 set_exception_intercept(svm, MC_VECTOR);
1022 set_exception_intercept(svm, AC_VECTOR);
1023 set_exception_intercept(svm, DB_VECTOR);
1025 set_intercept(svm, INTERCEPT_INTR);
1026 set_intercept(svm, INTERCEPT_NMI);
1027 set_intercept(svm, INTERCEPT_SMI);
1028 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1029 set_intercept(svm, INTERCEPT_RDPMC);
1030 set_intercept(svm, INTERCEPT_CPUID);
1031 set_intercept(svm, INTERCEPT_INVD);
1032 set_intercept(svm, INTERCEPT_HLT);
1033 set_intercept(svm, INTERCEPT_INVLPG);
1034 set_intercept(svm, INTERCEPT_INVLPGA);
1035 set_intercept(svm, INTERCEPT_IOIO_PROT);
1036 set_intercept(svm, INTERCEPT_MSR_PROT);
1037 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1038 set_intercept(svm, INTERCEPT_SHUTDOWN);
1039 set_intercept(svm, INTERCEPT_VMRUN);
1040 set_intercept(svm, INTERCEPT_VMMCALL);
1041 set_intercept(svm, INTERCEPT_VMLOAD);
1042 set_intercept(svm, INTERCEPT_VMSAVE);
1043 set_intercept(svm, INTERCEPT_STGI);
1044 set_intercept(svm, INTERCEPT_CLGI);
1045 set_intercept(svm, INTERCEPT_SKINIT);
1046 set_intercept(svm, INTERCEPT_WBINVD);
1047 set_intercept(svm, INTERCEPT_MONITOR);
1048 set_intercept(svm, INTERCEPT_MWAIT);
1049 set_intercept(svm, INTERCEPT_XSETBV);
1051 control->iopm_base_pa = iopm_base;
1052 control->msrpm_base_pa = __pa(svm->msrpm);
1053 control->int_ctl = V_INTR_MASKING_MASK;
1055 init_seg(&save->es);
1056 init_seg(&save->ss);
1057 init_seg(&save->ds);
1058 init_seg(&save->fs);
1059 init_seg(&save->gs);
1061 save->cs.selector = 0xf000;
1062 save->cs.base = 0xffff0000;
1063 /* Executable/Readable Code Segment */
1064 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1065 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1066 save->cs.limit = 0xffff;
1068 save->gdtr.limit = 0xffff;
1069 save->idtr.limit = 0xffff;
1071 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1072 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1074 svm_set_efer(&svm->vcpu, 0);
1075 save->dr6 = 0xffff0ff0;
1076 kvm_set_rflags(&svm->vcpu, 2);
1077 save->rip = 0x0000fff0;
1078 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1081 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1082 * It also updates the guest-visible cr0 value.
1084 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1085 kvm_mmu_reset_context(&svm->vcpu);
1087 save->cr4 = X86_CR4_PAE;
1091 /* Setup VMCB for Nested Paging */
1092 control->nested_ctl = 1;
1093 clr_intercept(svm, INTERCEPT_INVLPG);
1094 clr_exception_intercept(svm, PF_VECTOR);
1095 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1096 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1097 save->g_pat = svm->vcpu.arch.pat;
1101 svm->asid_generation = 0;
1103 svm->nested.vmcb = 0;
1104 svm->vcpu.arch.hflags = 0;
1106 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1107 control->pause_filter_count = 3000;
1108 set_intercept(svm, INTERCEPT_PAUSE);
1111 mark_all_dirty(svm->vmcb);
1116 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1118 struct vcpu_svm *svm = to_svm(vcpu);
1123 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1124 MSR_IA32_APICBASE_ENABLE;
1125 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1126 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1130 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1131 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1134 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1136 struct vcpu_svm *svm;
1138 struct page *msrpm_pages;
1139 struct page *hsave_page;
1140 struct page *nested_msrpm_pages;
1143 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1149 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1154 page = alloc_page(GFP_KERNEL);
1158 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1162 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1163 if (!nested_msrpm_pages)
1166 hsave_page = alloc_page(GFP_KERNEL);
1170 svm->nested.hsave = page_address(hsave_page);
1172 svm->msrpm = page_address(msrpm_pages);
1173 svm_vcpu_init_msrpm(svm->msrpm);
1175 svm->nested.msrpm = page_address(nested_msrpm_pages);
1176 svm_vcpu_init_msrpm(svm->nested.msrpm);
1178 svm->vmcb = page_address(page);
1179 clear_page(svm->vmcb);
1180 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1181 svm->asid_generation = 0;
1184 svm_init_osvw(&svm->vcpu);
1189 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1191 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1195 kvm_vcpu_uninit(&svm->vcpu);
1197 kmem_cache_free(kvm_vcpu_cache, svm);
1199 return ERR_PTR(err);
1202 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1204 struct vcpu_svm *svm = to_svm(vcpu);
1206 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1207 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1208 __free_page(virt_to_page(svm->nested.hsave));
1209 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1210 kvm_vcpu_uninit(vcpu);
1211 kmem_cache_free(kvm_vcpu_cache, svm);
1214 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1216 struct vcpu_svm *svm = to_svm(vcpu);
1219 if (unlikely(cpu != vcpu->cpu)) {
1220 svm->asid_generation = 0;
1221 mark_all_dirty(svm->vmcb);
1224 #ifdef CONFIG_X86_64
1225 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1227 savesegment(fs, svm->host.fs);
1228 savesegment(gs, svm->host.gs);
1229 svm->host.ldt = kvm_read_ldt();
1231 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1232 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1234 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1235 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1236 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1237 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1238 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1243 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1245 struct vcpu_svm *svm = to_svm(vcpu);
1248 ++vcpu->stat.host_state_reload;
1249 kvm_load_ldt(svm->host.ldt);
1250 #ifdef CONFIG_X86_64
1251 loadsegment(fs, svm->host.fs);
1252 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1253 load_gs_index(svm->host.gs);
1255 #ifdef CONFIG_X86_32_LAZY_GS
1256 loadsegment(gs, svm->host.gs);
1259 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1260 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1263 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1265 return to_svm(vcpu)->vmcb->save.rflags;
1268 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1271 * Any change of EFLAGS.VM is accompained by a reload of SS
1272 * (caused by either a task switch or an inter-privilege IRET),
1273 * so we do not need to update the CPL here.
1275 to_svm(vcpu)->vmcb->save.rflags = rflags;
1278 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1281 case VCPU_EXREG_PDPTR:
1282 BUG_ON(!npt_enabled);
1283 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1290 static void svm_set_vintr(struct vcpu_svm *svm)
1292 set_intercept(svm, INTERCEPT_VINTR);
1295 static void svm_clear_vintr(struct vcpu_svm *svm)
1297 clr_intercept(svm, INTERCEPT_VINTR);
1300 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1302 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1305 case VCPU_SREG_CS: return &save->cs;
1306 case VCPU_SREG_DS: return &save->ds;
1307 case VCPU_SREG_ES: return &save->es;
1308 case VCPU_SREG_FS: return &save->fs;
1309 case VCPU_SREG_GS: return &save->gs;
1310 case VCPU_SREG_SS: return &save->ss;
1311 case VCPU_SREG_TR: return &save->tr;
1312 case VCPU_SREG_LDTR: return &save->ldtr;
1318 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1320 struct vmcb_seg *s = svm_seg(vcpu, seg);
1325 static void svm_get_segment(struct kvm_vcpu *vcpu,
1326 struct kvm_segment *var, int seg)
1328 struct vmcb_seg *s = svm_seg(vcpu, seg);
1330 var->base = s->base;
1331 var->limit = s->limit;
1332 var->selector = s->selector;
1333 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1334 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1335 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1336 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1337 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1338 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1339 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1342 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1343 * However, the SVM spec states that the G bit is not observed by the
1344 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1345 * So let's synthesize a legal G bit for all segments, this helps
1346 * running KVM nested. It also helps cross-vendor migration, because
1347 * Intel's vmentry has a check on the 'G' bit.
1349 var->g = s->limit > 0xfffff;
1352 * AMD's VMCB does not have an explicit unusable field, so emulate it
1353 * for cross vendor migration purposes by "not present"
1355 var->unusable = !var->present || (var->type == 0);
1360 * Work around a bug where the busy flag in the tr selector
1370 * The accessed bit must always be set in the segment
1371 * descriptor cache, although it can be cleared in the
1372 * descriptor, the cached bit always remains at 1. Since
1373 * Intel has a check on this, set it here to support
1374 * cross-vendor migration.
1381 * On AMD CPUs sometimes the DB bit in the segment
1382 * descriptor is left as 1, although the whole segment has
1383 * been made unusable. Clear it here to pass an Intel VMX
1384 * entry check when cross vendor migrating.
1388 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1393 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1395 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1400 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1402 struct vcpu_svm *svm = to_svm(vcpu);
1404 dt->size = svm->vmcb->save.idtr.limit;
1405 dt->address = svm->vmcb->save.idtr.base;
1408 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1410 struct vcpu_svm *svm = to_svm(vcpu);
1412 svm->vmcb->save.idtr.limit = dt->size;
1413 svm->vmcb->save.idtr.base = dt->address ;
1414 mark_dirty(svm->vmcb, VMCB_DT);
1417 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1419 struct vcpu_svm *svm = to_svm(vcpu);
1421 dt->size = svm->vmcb->save.gdtr.limit;
1422 dt->address = svm->vmcb->save.gdtr.base;
1425 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1427 struct vcpu_svm *svm = to_svm(vcpu);
1429 svm->vmcb->save.gdtr.limit = dt->size;
1430 svm->vmcb->save.gdtr.base = dt->address ;
1431 mark_dirty(svm->vmcb, VMCB_DT);
1434 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1438 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1442 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1446 static void update_cr0_intercept(struct vcpu_svm *svm)
1448 ulong gcr0 = svm->vcpu.arch.cr0;
1449 u64 *hcr0 = &svm->vmcb->save.cr0;
1451 if (!svm->vcpu.fpu_active)
1452 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1454 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1455 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1457 mark_dirty(svm->vmcb, VMCB_CR);
1459 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1460 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1461 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1463 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1464 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1468 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1470 struct vcpu_svm *svm = to_svm(vcpu);
1472 #ifdef CONFIG_X86_64
1473 if (vcpu->arch.efer & EFER_LME) {
1474 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1475 vcpu->arch.efer |= EFER_LMA;
1476 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1479 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1480 vcpu->arch.efer &= ~EFER_LMA;
1481 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1485 vcpu->arch.cr0 = cr0;
1488 cr0 |= X86_CR0_PG | X86_CR0_WP;
1490 if (!vcpu->fpu_active)
1493 * re-enable caching here because the QEMU bios
1494 * does not do it - this results in some delay at
1497 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1498 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1499 svm->vmcb->save.cr0 = cr0;
1500 mark_dirty(svm->vmcb, VMCB_CR);
1501 update_cr0_intercept(svm);
1504 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1506 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1507 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1509 if (cr4 & X86_CR4_VMXE)
1512 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1513 svm_flush_tlb(vcpu);
1515 vcpu->arch.cr4 = cr4;
1518 cr4 |= host_cr4_mce;
1519 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1520 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1524 static void svm_set_segment(struct kvm_vcpu *vcpu,
1525 struct kvm_segment *var, int seg)
1527 struct vcpu_svm *svm = to_svm(vcpu);
1528 struct vmcb_seg *s = svm_seg(vcpu, seg);
1530 s->base = var->base;
1531 s->limit = var->limit;
1532 s->selector = var->selector;
1536 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1537 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1538 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1539 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1540 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1541 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1542 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1543 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1547 * This is always accurate, except if SYSRET returned to a segment
1548 * with SS.DPL != 3. Intel does not have this quirk, and always
1549 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1550 * would entail passing the CPL to userspace and back.
1552 if (seg == VCPU_SREG_SS)
1553 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1555 mark_dirty(svm->vmcb, VMCB_SEG);
1558 static void update_bp_intercept(struct kvm_vcpu *vcpu)
1560 struct vcpu_svm *svm = to_svm(vcpu);
1562 clr_exception_intercept(svm, BP_VECTOR);
1564 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1565 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1566 set_exception_intercept(svm, BP_VECTOR);
1568 vcpu->guest_debug = 0;
1571 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1573 if (sd->next_asid > sd->max_asid) {
1574 ++sd->asid_generation;
1576 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1579 svm->asid_generation = sd->asid_generation;
1580 svm->vmcb->control.asid = sd->next_asid++;
1582 mark_dirty(svm->vmcb, VMCB_ASID);
1585 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1587 return to_svm(vcpu)->vmcb->save.dr6;
1590 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1592 struct vcpu_svm *svm = to_svm(vcpu);
1594 svm->vmcb->save.dr6 = value;
1595 mark_dirty(svm->vmcb, VMCB_DR);
1598 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1600 struct vcpu_svm *svm = to_svm(vcpu);
1602 get_debugreg(vcpu->arch.db[0], 0);
1603 get_debugreg(vcpu->arch.db[1], 1);
1604 get_debugreg(vcpu->arch.db[2], 2);
1605 get_debugreg(vcpu->arch.db[3], 3);
1606 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1607 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1609 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1610 set_dr_intercepts(svm);
1613 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1615 struct vcpu_svm *svm = to_svm(vcpu);
1617 svm->vmcb->save.dr7 = value;
1618 mark_dirty(svm->vmcb, VMCB_DR);
1621 static int pf_interception(struct vcpu_svm *svm)
1623 u64 fault_address = svm->vmcb->control.exit_info_2;
1627 switch (svm->apf_reason) {
1629 error_code = svm->vmcb->control.exit_info_1;
1631 trace_kvm_page_fault(fault_address, error_code);
1632 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1633 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1634 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1635 svm->vmcb->control.insn_bytes,
1636 svm->vmcb->control.insn_len);
1638 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1639 svm->apf_reason = 0;
1640 local_irq_disable();
1641 kvm_async_pf_task_wait(fault_address);
1644 case KVM_PV_REASON_PAGE_READY:
1645 svm->apf_reason = 0;
1646 local_irq_disable();
1647 kvm_async_pf_task_wake(fault_address);
1654 static int db_interception(struct vcpu_svm *svm)
1656 struct kvm_run *kvm_run = svm->vcpu.run;
1658 if (!(svm->vcpu.guest_debug &
1659 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1660 !svm->nmi_singlestep) {
1661 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1665 if (svm->nmi_singlestep) {
1666 svm->nmi_singlestep = false;
1667 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1668 svm->vmcb->save.rflags &=
1669 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1672 if (svm->vcpu.guest_debug &
1673 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1674 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1675 kvm_run->debug.arch.pc =
1676 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1677 kvm_run->debug.arch.exception = DB_VECTOR;
1684 static int bp_interception(struct vcpu_svm *svm)
1686 struct kvm_run *kvm_run = svm->vcpu.run;
1688 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1689 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1690 kvm_run->debug.arch.exception = BP_VECTOR;
1694 static int ud_interception(struct vcpu_svm *svm)
1698 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1699 if (er != EMULATE_DONE)
1700 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1704 static int ac_interception(struct vcpu_svm *svm)
1706 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1710 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1712 struct vcpu_svm *svm = to_svm(vcpu);
1714 clr_exception_intercept(svm, NM_VECTOR);
1716 svm->vcpu.fpu_active = 1;
1717 update_cr0_intercept(svm);
1720 static int nm_interception(struct vcpu_svm *svm)
1722 svm_fpu_activate(&svm->vcpu);
1726 static bool is_erratum_383(void)
1731 if (!erratum_383_found)
1734 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1738 /* Bit 62 may or may not be set for this mce */
1739 value &= ~(1ULL << 62);
1741 if (value != 0xb600000000010015ULL)
1744 /* Clear MCi_STATUS registers */
1745 for (i = 0; i < 6; ++i)
1746 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1748 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1752 value &= ~(1ULL << 2);
1753 low = lower_32_bits(value);
1754 high = upper_32_bits(value);
1756 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1759 /* Flush tlb to evict multi-match entries */
1765 static void svm_handle_mce(struct vcpu_svm *svm)
1767 if (is_erratum_383()) {
1769 * Erratum 383 triggered. Guest state is corrupt so kill the
1772 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1774 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1780 * On an #MC intercept the MCE handler is not called automatically in
1781 * the host. So do it by hand here.
1785 /* not sure if we ever come back to this point */
1790 static int mc_interception(struct vcpu_svm *svm)
1795 static int shutdown_interception(struct vcpu_svm *svm)
1797 struct kvm_run *kvm_run = svm->vcpu.run;
1800 * VMCB is undefined after a SHUTDOWN intercept
1801 * so reinitialize it.
1803 clear_page(svm->vmcb);
1806 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1810 static int io_interception(struct vcpu_svm *svm)
1812 struct kvm_vcpu *vcpu = &svm->vcpu;
1813 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1814 int size, in, string;
1817 ++svm->vcpu.stat.io_exits;
1818 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1819 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1821 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1823 port = io_info >> 16;
1824 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1825 svm->next_rip = svm->vmcb->control.exit_info_2;
1826 skip_emulated_instruction(&svm->vcpu);
1828 return kvm_fast_pio_out(vcpu, size, port);
1831 static int nmi_interception(struct vcpu_svm *svm)
1836 static int intr_interception(struct vcpu_svm *svm)
1838 ++svm->vcpu.stat.irq_exits;
1842 static int nop_on_interception(struct vcpu_svm *svm)
1847 static int halt_interception(struct vcpu_svm *svm)
1849 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1850 return kvm_emulate_halt(&svm->vcpu);
1853 static int vmmcall_interception(struct vcpu_svm *svm)
1855 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1856 kvm_emulate_hypercall(&svm->vcpu);
1860 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1862 struct vcpu_svm *svm = to_svm(vcpu);
1864 return svm->nested.nested_cr3;
1867 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1869 struct vcpu_svm *svm = to_svm(vcpu);
1870 u64 cr3 = svm->nested.nested_cr3;
1874 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
1875 offset_in_page(cr3) + index * 8, 8);
1881 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1884 struct vcpu_svm *svm = to_svm(vcpu);
1886 svm->vmcb->control.nested_cr3 = root;
1887 mark_dirty(svm->vmcb, VMCB_NPT);
1888 svm_flush_tlb(vcpu);
1891 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1892 struct x86_exception *fault)
1894 struct vcpu_svm *svm = to_svm(vcpu);
1896 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
1898 * TODO: track the cause of the nested page fault, and
1899 * correctly fill in the high bits of exit_info_1.
1901 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1902 svm->vmcb->control.exit_code_hi = 0;
1903 svm->vmcb->control.exit_info_1 = (1ULL << 32);
1904 svm->vmcb->control.exit_info_2 = fault->address;
1907 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
1908 svm->vmcb->control.exit_info_1 |= fault->error_code;
1911 * The present bit is always zero for page structure faults on real
1914 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
1915 svm->vmcb->control.exit_info_1 &= ~1;
1917 nested_svm_vmexit(svm);
1920 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1922 WARN_ON(mmu_is_nested(vcpu));
1923 kvm_init_shadow_mmu(vcpu);
1924 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1925 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1926 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1927 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1928 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1929 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
1930 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1933 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1935 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1938 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1940 if (!(svm->vcpu.arch.efer & EFER_SVME)
1941 || !is_paging(&svm->vcpu)) {
1942 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1946 if (svm->vmcb->save.cpl) {
1947 kvm_inject_gp(&svm->vcpu, 0);
1954 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1955 bool has_error_code, u32 error_code)
1959 if (!is_guest_mode(&svm->vcpu))
1962 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1963 svm->vmcb->control.exit_code_hi = 0;
1964 svm->vmcb->control.exit_info_1 = error_code;
1965 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1967 vmexit = nested_svm_intercept(svm);
1968 if (vmexit == NESTED_EXIT_DONE)
1969 svm->nested.exit_required = true;
1974 /* This function returns true if it is save to enable the irq window */
1975 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1977 if (!is_guest_mode(&svm->vcpu))
1980 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1983 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1987 * if vmexit was already requested (by intercepted exception
1988 * for instance) do not overwrite it with "external interrupt"
1991 if (svm->nested.exit_required)
1994 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1995 svm->vmcb->control.exit_info_1 = 0;
1996 svm->vmcb->control.exit_info_2 = 0;
1998 if (svm->nested.intercept & 1ULL) {
2000 * The #vmexit can't be emulated here directly because this
2001 * code path runs with irqs and preemption disabled. A
2002 * #vmexit emulation might sleep. Only signal request for
2005 svm->nested.exit_required = true;
2006 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2013 /* This function returns true if it is save to enable the nmi window */
2014 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2016 if (!is_guest_mode(&svm->vcpu))
2019 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2022 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2023 svm->nested.exit_required = true;
2028 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2034 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2035 if (is_error_page(page))
2043 kvm_inject_gp(&svm->vcpu, 0);
2048 static void nested_svm_unmap(struct page *page)
2051 kvm_release_page_dirty(page);
2054 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2056 unsigned port, size, iopm_len;
2061 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2062 return NESTED_EXIT_HOST;
2064 port = svm->vmcb->control.exit_info_1 >> 16;
2065 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2066 SVM_IOIO_SIZE_SHIFT;
2067 gpa = svm->nested.vmcb_iopm + (port / 8);
2068 start_bit = port % 8;
2069 iopm_len = (start_bit + size > 8) ? 2 : 1;
2070 mask = (0xf >> (4 - size)) << start_bit;
2073 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2074 return NESTED_EXIT_DONE;
2076 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2079 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2081 u32 offset, msr, value;
2084 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2085 return NESTED_EXIT_HOST;
2087 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2088 offset = svm_msrpm_offset(msr);
2089 write = svm->vmcb->control.exit_info_1 & 1;
2090 mask = 1 << ((2 * (msr & 0xf)) + write);
2092 if (offset == MSR_INVALID)
2093 return NESTED_EXIT_DONE;
2095 /* Offset is in 32 bit units but need in 8 bit units */
2098 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2099 return NESTED_EXIT_DONE;
2101 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2104 static int nested_svm_exit_special(struct vcpu_svm *svm)
2106 u32 exit_code = svm->vmcb->control.exit_code;
2108 switch (exit_code) {
2111 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2112 return NESTED_EXIT_HOST;
2114 /* For now we are always handling NPFs when using them */
2116 return NESTED_EXIT_HOST;
2118 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2119 /* When we're shadowing, trap PFs, but not async PF */
2120 if (!npt_enabled && svm->apf_reason == 0)
2121 return NESTED_EXIT_HOST;
2123 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2124 nm_interception(svm);
2130 return NESTED_EXIT_CONTINUE;
2134 * If this function returns true, this #vmexit was already handled
2136 static int nested_svm_intercept(struct vcpu_svm *svm)
2138 u32 exit_code = svm->vmcb->control.exit_code;
2139 int vmexit = NESTED_EXIT_HOST;
2141 switch (exit_code) {
2143 vmexit = nested_svm_exit_handled_msr(svm);
2146 vmexit = nested_svm_intercept_ioio(svm);
2148 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2149 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2150 if (svm->nested.intercept_cr & bit)
2151 vmexit = NESTED_EXIT_DONE;
2154 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2155 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2156 if (svm->nested.intercept_dr & bit)
2157 vmexit = NESTED_EXIT_DONE;
2160 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2161 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2162 if (svm->nested.intercept_exceptions & excp_bits)
2163 vmexit = NESTED_EXIT_DONE;
2164 /* async page fault always cause vmexit */
2165 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2166 svm->apf_reason != 0)
2167 vmexit = NESTED_EXIT_DONE;
2170 case SVM_EXIT_ERR: {
2171 vmexit = NESTED_EXIT_DONE;
2175 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2176 if (svm->nested.intercept & exit_bits)
2177 vmexit = NESTED_EXIT_DONE;
2184 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2188 vmexit = nested_svm_intercept(svm);
2190 if (vmexit == NESTED_EXIT_DONE)
2191 nested_svm_vmexit(svm);
2196 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2198 struct vmcb_control_area *dst = &dst_vmcb->control;
2199 struct vmcb_control_area *from = &from_vmcb->control;
2201 dst->intercept_cr = from->intercept_cr;
2202 dst->intercept_dr = from->intercept_dr;
2203 dst->intercept_exceptions = from->intercept_exceptions;
2204 dst->intercept = from->intercept;
2205 dst->iopm_base_pa = from->iopm_base_pa;
2206 dst->msrpm_base_pa = from->msrpm_base_pa;
2207 dst->tsc_offset = from->tsc_offset;
2208 dst->asid = from->asid;
2209 dst->tlb_ctl = from->tlb_ctl;
2210 dst->int_ctl = from->int_ctl;
2211 dst->int_vector = from->int_vector;
2212 dst->int_state = from->int_state;
2213 dst->exit_code = from->exit_code;
2214 dst->exit_code_hi = from->exit_code_hi;
2215 dst->exit_info_1 = from->exit_info_1;
2216 dst->exit_info_2 = from->exit_info_2;
2217 dst->exit_int_info = from->exit_int_info;
2218 dst->exit_int_info_err = from->exit_int_info_err;
2219 dst->nested_ctl = from->nested_ctl;
2220 dst->event_inj = from->event_inj;
2221 dst->event_inj_err = from->event_inj_err;
2222 dst->nested_cr3 = from->nested_cr3;
2223 dst->lbr_ctl = from->lbr_ctl;
2226 static int nested_svm_vmexit(struct vcpu_svm *svm)
2228 struct vmcb *nested_vmcb;
2229 struct vmcb *hsave = svm->nested.hsave;
2230 struct vmcb *vmcb = svm->vmcb;
2233 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2234 vmcb->control.exit_info_1,
2235 vmcb->control.exit_info_2,
2236 vmcb->control.exit_int_info,
2237 vmcb->control.exit_int_info_err,
2240 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2244 /* Exit Guest-Mode */
2245 leave_guest_mode(&svm->vcpu);
2246 svm->nested.vmcb = 0;
2248 /* Give the current vmcb to the guest */
2251 nested_vmcb->save.es = vmcb->save.es;
2252 nested_vmcb->save.cs = vmcb->save.cs;
2253 nested_vmcb->save.ss = vmcb->save.ss;
2254 nested_vmcb->save.ds = vmcb->save.ds;
2255 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2256 nested_vmcb->save.idtr = vmcb->save.idtr;
2257 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2258 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2259 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2260 nested_vmcb->save.cr2 = vmcb->save.cr2;
2261 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2262 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2263 nested_vmcb->save.rip = vmcb->save.rip;
2264 nested_vmcb->save.rsp = vmcb->save.rsp;
2265 nested_vmcb->save.rax = vmcb->save.rax;
2266 nested_vmcb->save.dr7 = vmcb->save.dr7;
2267 nested_vmcb->save.dr6 = vmcb->save.dr6;
2268 nested_vmcb->save.cpl = vmcb->save.cpl;
2270 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2271 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2272 nested_vmcb->control.int_state = vmcb->control.int_state;
2273 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2274 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2275 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2276 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2277 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2278 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2280 if (svm->nrips_enabled)
2281 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2284 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2285 * to make sure that we do not lose injected events. So check event_inj
2286 * here and copy it to exit_int_info if it is valid.
2287 * Exit_int_info and event_inj can't be both valid because the case
2288 * below only happens on a VMRUN instruction intercept which has
2289 * no valid exit_int_info set.
2291 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2292 struct vmcb_control_area *nc = &nested_vmcb->control;
2294 nc->exit_int_info = vmcb->control.event_inj;
2295 nc->exit_int_info_err = vmcb->control.event_inj_err;
2298 nested_vmcb->control.tlb_ctl = 0;
2299 nested_vmcb->control.event_inj = 0;
2300 nested_vmcb->control.event_inj_err = 0;
2302 /* We always set V_INTR_MASKING and remember the old value in hflags */
2303 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2304 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2306 /* Restore the original control entries */
2307 copy_vmcb_control_area(vmcb, hsave);
2309 kvm_clear_exception_queue(&svm->vcpu);
2310 kvm_clear_interrupt_queue(&svm->vcpu);
2312 svm->nested.nested_cr3 = 0;
2314 /* Restore selected save entries */
2315 svm->vmcb->save.es = hsave->save.es;
2316 svm->vmcb->save.cs = hsave->save.cs;
2317 svm->vmcb->save.ss = hsave->save.ss;
2318 svm->vmcb->save.ds = hsave->save.ds;
2319 svm->vmcb->save.gdtr = hsave->save.gdtr;
2320 svm->vmcb->save.idtr = hsave->save.idtr;
2321 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2322 svm_set_efer(&svm->vcpu, hsave->save.efer);
2323 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2324 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2326 svm->vmcb->save.cr3 = hsave->save.cr3;
2327 svm->vcpu.arch.cr3 = hsave->save.cr3;
2329 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2331 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2332 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2333 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2334 svm->vmcb->save.dr7 = 0;
2335 svm->vmcb->save.cpl = 0;
2336 svm->vmcb->control.exit_int_info = 0;
2338 mark_all_dirty(svm->vmcb);
2340 nested_svm_unmap(page);
2342 nested_svm_uninit_mmu_context(&svm->vcpu);
2343 kvm_mmu_reset_context(&svm->vcpu);
2344 kvm_mmu_load(&svm->vcpu);
2349 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2352 * This function merges the msr permission bitmaps of kvm and the
2353 * nested vmcb. It is optimized in that it only merges the parts where
2354 * the kvm msr permission bitmap may contain zero bits
2358 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2361 for (i = 0; i < MSRPM_OFFSETS; i++) {
2365 if (msrpm_offsets[i] == 0xffffffff)
2368 p = msrpm_offsets[i];
2369 offset = svm->nested.vmcb_msrpm + (p * 4);
2371 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2374 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2377 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2382 static bool nested_vmcb_checks(struct vmcb *vmcb)
2384 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2387 if (vmcb->control.asid == 0)
2390 if (vmcb->control.nested_ctl && !npt_enabled)
2396 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2398 struct vmcb *nested_vmcb;
2399 struct vmcb *hsave = svm->nested.hsave;
2400 struct vmcb *vmcb = svm->vmcb;
2404 vmcb_gpa = svm->vmcb->save.rax;
2406 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2410 if (!nested_vmcb_checks(nested_vmcb)) {
2411 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2412 nested_vmcb->control.exit_code_hi = 0;
2413 nested_vmcb->control.exit_info_1 = 0;
2414 nested_vmcb->control.exit_info_2 = 0;
2416 nested_svm_unmap(page);
2421 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2422 nested_vmcb->save.rip,
2423 nested_vmcb->control.int_ctl,
2424 nested_vmcb->control.event_inj,
2425 nested_vmcb->control.nested_ctl);
2427 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2428 nested_vmcb->control.intercept_cr >> 16,
2429 nested_vmcb->control.intercept_exceptions,
2430 nested_vmcb->control.intercept);
2432 /* Clear internal status */
2433 kvm_clear_exception_queue(&svm->vcpu);
2434 kvm_clear_interrupt_queue(&svm->vcpu);
2437 * Save the old vmcb, so we don't need to pick what we save, but can
2438 * restore everything when a VMEXIT occurs
2440 hsave->save.es = vmcb->save.es;
2441 hsave->save.cs = vmcb->save.cs;
2442 hsave->save.ss = vmcb->save.ss;
2443 hsave->save.ds = vmcb->save.ds;
2444 hsave->save.gdtr = vmcb->save.gdtr;
2445 hsave->save.idtr = vmcb->save.idtr;
2446 hsave->save.efer = svm->vcpu.arch.efer;
2447 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2448 hsave->save.cr4 = svm->vcpu.arch.cr4;
2449 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2450 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2451 hsave->save.rsp = vmcb->save.rsp;
2452 hsave->save.rax = vmcb->save.rax;
2454 hsave->save.cr3 = vmcb->save.cr3;
2456 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2458 copy_vmcb_control_area(hsave, vmcb);
2460 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2461 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2463 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2465 if (nested_vmcb->control.nested_ctl) {
2466 kvm_mmu_unload(&svm->vcpu);
2467 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2468 nested_svm_init_mmu_context(&svm->vcpu);
2471 /* Load the nested guest state */
2472 svm->vmcb->save.es = nested_vmcb->save.es;
2473 svm->vmcb->save.cs = nested_vmcb->save.cs;
2474 svm->vmcb->save.ss = nested_vmcb->save.ss;
2475 svm->vmcb->save.ds = nested_vmcb->save.ds;
2476 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2477 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2478 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2479 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2480 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2481 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2483 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2484 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2486 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2488 /* Guest paging mode is active - reset mmu */
2489 kvm_mmu_reset_context(&svm->vcpu);
2491 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2492 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2493 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2494 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2496 /* In case we don't even reach vcpu_run, the fields are not updated */
2497 svm->vmcb->save.rax = nested_vmcb->save.rax;
2498 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2499 svm->vmcb->save.rip = nested_vmcb->save.rip;
2500 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2501 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2502 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2504 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2505 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2507 /* cache intercepts */
2508 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2509 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2510 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2511 svm->nested.intercept = nested_vmcb->control.intercept;
2513 svm_flush_tlb(&svm->vcpu);
2514 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2515 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2516 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2518 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2520 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2521 /* We only want the cr8 intercept bits of the guest */
2522 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2523 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2526 /* We don't want to see VMMCALLs from a nested guest */
2527 clr_intercept(svm, INTERCEPT_VMMCALL);
2529 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2530 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2531 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2532 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2533 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2534 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2536 nested_svm_unmap(page);
2538 /* Enter Guest-Mode */
2539 enter_guest_mode(&svm->vcpu);
2542 * Merge guest and host intercepts - must be called with vcpu in
2543 * guest-mode to take affect here
2545 recalc_intercepts(svm);
2547 svm->nested.vmcb = vmcb_gpa;
2551 mark_all_dirty(svm->vmcb);
2556 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2558 to_vmcb->save.fs = from_vmcb->save.fs;
2559 to_vmcb->save.gs = from_vmcb->save.gs;
2560 to_vmcb->save.tr = from_vmcb->save.tr;
2561 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2562 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2563 to_vmcb->save.star = from_vmcb->save.star;
2564 to_vmcb->save.lstar = from_vmcb->save.lstar;
2565 to_vmcb->save.cstar = from_vmcb->save.cstar;
2566 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2567 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2568 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2569 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2572 static int vmload_interception(struct vcpu_svm *svm)
2574 struct vmcb *nested_vmcb;
2577 if (nested_svm_check_permissions(svm))
2580 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2584 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2585 skip_emulated_instruction(&svm->vcpu);
2587 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2588 nested_svm_unmap(page);
2593 static int vmsave_interception(struct vcpu_svm *svm)
2595 struct vmcb *nested_vmcb;
2598 if (nested_svm_check_permissions(svm))
2601 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2605 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2606 skip_emulated_instruction(&svm->vcpu);
2608 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2609 nested_svm_unmap(page);
2614 static int vmrun_interception(struct vcpu_svm *svm)
2616 if (nested_svm_check_permissions(svm))
2619 /* Save rip after vmrun instruction */
2620 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2622 if (!nested_svm_vmrun(svm))
2625 if (!nested_svm_vmrun_msrpm(svm))
2632 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2633 svm->vmcb->control.exit_code_hi = 0;
2634 svm->vmcb->control.exit_info_1 = 0;
2635 svm->vmcb->control.exit_info_2 = 0;
2637 nested_svm_vmexit(svm);
2642 static int stgi_interception(struct vcpu_svm *svm)
2644 if (nested_svm_check_permissions(svm))
2647 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2648 skip_emulated_instruction(&svm->vcpu);
2649 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2656 static int clgi_interception(struct vcpu_svm *svm)
2658 if (nested_svm_check_permissions(svm))
2661 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2662 skip_emulated_instruction(&svm->vcpu);
2666 /* After a CLGI no interrupts should come */
2667 svm_clear_vintr(svm);
2668 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2670 mark_dirty(svm->vmcb, VMCB_INTR);
2675 static int invlpga_interception(struct vcpu_svm *svm)
2677 struct kvm_vcpu *vcpu = &svm->vcpu;
2679 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2680 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2682 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2683 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2685 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2686 skip_emulated_instruction(&svm->vcpu);
2690 static int skinit_interception(struct vcpu_svm *svm)
2692 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2694 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2698 static int wbinvd_interception(struct vcpu_svm *svm)
2700 kvm_emulate_wbinvd(&svm->vcpu);
2704 static int xsetbv_interception(struct vcpu_svm *svm)
2706 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2707 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2709 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2710 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2711 skip_emulated_instruction(&svm->vcpu);
2717 static int task_switch_interception(struct vcpu_svm *svm)
2721 int int_type = svm->vmcb->control.exit_int_info &
2722 SVM_EXITINTINFO_TYPE_MASK;
2723 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2725 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2727 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2728 bool has_error_code = false;
2731 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2733 if (svm->vmcb->control.exit_info_2 &
2734 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2735 reason = TASK_SWITCH_IRET;
2736 else if (svm->vmcb->control.exit_info_2 &
2737 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2738 reason = TASK_SWITCH_JMP;
2740 reason = TASK_SWITCH_GATE;
2742 reason = TASK_SWITCH_CALL;
2744 if (reason == TASK_SWITCH_GATE) {
2746 case SVM_EXITINTINFO_TYPE_NMI:
2747 svm->vcpu.arch.nmi_injected = false;
2749 case SVM_EXITINTINFO_TYPE_EXEPT:
2750 if (svm->vmcb->control.exit_info_2 &
2751 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2752 has_error_code = true;
2754 (u32)svm->vmcb->control.exit_info_2;
2756 kvm_clear_exception_queue(&svm->vcpu);
2758 case SVM_EXITINTINFO_TYPE_INTR:
2759 kvm_clear_interrupt_queue(&svm->vcpu);
2766 if (reason != TASK_SWITCH_GATE ||
2767 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2768 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2769 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2770 skip_emulated_instruction(&svm->vcpu);
2772 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2775 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2776 has_error_code, error_code) == EMULATE_FAIL) {
2777 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2778 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2779 svm->vcpu.run->internal.ndata = 0;
2785 static int cpuid_interception(struct vcpu_svm *svm)
2787 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2788 kvm_emulate_cpuid(&svm->vcpu);
2792 static int iret_interception(struct vcpu_svm *svm)
2794 ++svm->vcpu.stat.nmi_window_exits;
2795 clr_intercept(svm, INTERCEPT_IRET);
2796 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2797 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2798 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2802 static int invlpg_interception(struct vcpu_svm *svm)
2804 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2805 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2807 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2808 skip_emulated_instruction(&svm->vcpu);
2812 static int emulate_on_interception(struct vcpu_svm *svm)
2814 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2817 static int rdpmc_interception(struct vcpu_svm *svm)
2821 if (!static_cpu_has(X86_FEATURE_NRIPS))
2822 return emulate_on_interception(svm);
2824 err = kvm_rdpmc(&svm->vcpu);
2825 kvm_complete_insn_gp(&svm->vcpu, err);
2830 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2833 unsigned long cr0 = svm->vcpu.arch.cr0;
2837 intercept = svm->nested.intercept;
2839 if (!is_guest_mode(&svm->vcpu) ||
2840 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2843 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2844 val &= ~SVM_CR0_SELECTIVE_MASK;
2847 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2848 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2854 #define CR_VALID (1ULL << 63)
2856 static int cr_interception(struct vcpu_svm *svm)
2862 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2863 return emulate_on_interception(svm);
2865 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2866 return emulate_on_interception(svm);
2868 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2869 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2870 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2872 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2875 if (cr >= 16) { /* mov to cr */
2877 val = kvm_register_read(&svm->vcpu, reg);
2880 if (!check_selective_cr0_intercepted(svm, val))
2881 err = kvm_set_cr0(&svm->vcpu, val);
2887 err = kvm_set_cr3(&svm->vcpu, val);
2890 err = kvm_set_cr4(&svm->vcpu, val);
2893 err = kvm_set_cr8(&svm->vcpu, val);
2896 WARN(1, "unhandled write to CR%d", cr);
2897 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2900 } else { /* mov from cr */
2903 val = kvm_read_cr0(&svm->vcpu);
2906 val = svm->vcpu.arch.cr2;
2909 val = kvm_read_cr3(&svm->vcpu);
2912 val = kvm_read_cr4(&svm->vcpu);
2915 val = kvm_get_cr8(&svm->vcpu);
2918 WARN(1, "unhandled read from CR%d", cr);
2919 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2922 kvm_register_write(&svm->vcpu, reg, val);
2924 kvm_complete_insn_gp(&svm->vcpu, err);
2929 static int dr_interception(struct vcpu_svm *svm)
2934 if (svm->vcpu.guest_debug == 0) {
2936 * No more DR vmexits; force a reload of the debug registers
2937 * and reenter on this instruction. The next vmexit will
2938 * retrieve the full state of the debug registers.
2940 clr_dr_intercepts(svm);
2941 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2945 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2946 return emulate_on_interception(svm);
2948 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2949 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2951 if (dr >= 16) { /* mov to DRn */
2952 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2954 val = kvm_register_read(&svm->vcpu, reg);
2955 kvm_set_dr(&svm->vcpu, dr - 16, val);
2957 if (!kvm_require_dr(&svm->vcpu, dr))
2959 kvm_get_dr(&svm->vcpu, dr, &val);
2960 kvm_register_write(&svm->vcpu, reg, val);
2963 skip_emulated_instruction(&svm->vcpu);
2968 static int cr8_write_interception(struct vcpu_svm *svm)
2970 struct kvm_run *kvm_run = svm->vcpu.run;
2973 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2974 /* instruction emulation calls kvm_set_cr8() */
2975 r = cr_interception(svm);
2976 if (lapic_in_kernel(&svm->vcpu))
2978 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2980 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2984 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2986 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
2987 return vmcb->control.tsc_offset + host_tsc;
2990 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2992 struct vcpu_svm *svm = to_svm(vcpu);
2994 switch (msr_info->index) {
2995 case MSR_IA32_TSC: {
2996 msr_info->data = svm->vmcb->control.tsc_offset +
2997 kvm_scale_tsc(vcpu, rdtsc());
3002 msr_info->data = svm->vmcb->save.star;
3004 #ifdef CONFIG_X86_64
3006 msr_info->data = svm->vmcb->save.lstar;
3009 msr_info->data = svm->vmcb->save.cstar;
3011 case MSR_KERNEL_GS_BASE:
3012 msr_info->data = svm->vmcb->save.kernel_gs_base;
3014 case MSR_SYSCALL_MASK:
3015 msr_info->data = svm->vmcb->save.sfmask;
3018 case MSR_IA32_SYSENTER_CS:
3019 msr_info->data = svm->vmcb->save.sysenter_cs;
3021 case MSR_IA32_SYSENTER_EIP:
3022 msr_info->data = svm->sysenter_eip;
3024 case MSR_IA32_SYSENTER_ESP:
3025 msr_info->data = svm->sysenter_esp;
3028 * Nobody will change the following 5 values in the VMCB so we can
3029 * safely return them on rdmsr. They will always be 0 until LBRV is
3032 case MSR_IA32_DEBUGCTLMSR:
3033 msr_info->data = svm->vmcb->save.dbgctl;
3035 case MSR_IA32_LASTBRANCHFROMIP:
3036 msr_info->data = svm->vmcb->save.br_from;
3038 case MSR_IA32_LASTBRANCHTOIP:
3039 msr_info->data = svm->vmcb->save.br_to;
3041 case MSR_IA32_LASTINTFROMIP:
3042 msr_info->data = svm->vmcb->save.last_excp_from;
3044 case MSR_IA32_LASTINTTOIP:
3045 msr_info->data = svm->vmcb->save.last_excp_to;
3047 case MSR_VM_HSAVE_PA:
3048 msr_info->data = svm->nested.hsave_msr;
3051 msr_info->data = svm->nested.vm_cr_msr;
3053 case MSR_IA32_UCODE_REV:
3054 msr_info->data = 0x01000065;
3057 return kvm_get_msr_common(vcpu, msr_info);
3062 static int rdmsr_interception(struct vcpu_svm *svm)
3064 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3065 struct msr_data msr_info;
3067 msr_info.index = ecx;
3068 msr_info.host_initiated = false;
3069 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3070 trace_kvm_msr_read_ex(ecx);
3071 kvm_inject_gp(&svm->vcpu, 0);
3073 trace_kvm_msr_read(ecx, msr_info.data);
3075 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3076 msr_info.data & 0xffffffff);
3077 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3078 msr_info.data >> 32);
3079 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3080 skip_emulated_instruction(&svm->vcpu);
3085 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3087 struct vcpu_svm *svm = to_svm(vcpu);
3088 int svm_dis, chg_mask;
3090 if (data & ~SVM_VM_CR_VALID_MASK)
3093 chg_mask = SVM_VM_CR_VALID_MASK;
3095 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3096 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3098 svm->nested.vm_cr_msr &= ~chg_mask;
3099 svm->nested.vm_cr_msr |= (data & chg_mask);
3101 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3103 /* check for svm_disable while efer.svme is set */
3104 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3110 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3112 struct vcpu_svm *svm = to_svm(vcpu);
3114 u32 ecx = msr->index;
3115 u64 data = msr->data;
3118 kvm_write_tsc(vcpu, msr);
3121 svm->vmcb->save.star = data;
3123 #ifdef CONFIG_X86_64
3125 svm->vmcb->save.lstar = data;
3128 svm->vmcb->save.cstar = data;
3130 case MSR_KERNEL_GS_BASE:
3131 svm->vmcb->save.kernel_gs_base = data;
3133 case MSR_SYSCALL_MASK:
3134 svm->vmcb->save.sfmask = data;
3137 case MSR_IA32_SYSENTER_CS:
3138 svm->vmcb->save.sysenter_cs = data;
3140 case MSR_IA32_SYSENTER_EIP:
3141 svm->sysenter_eip = data;
3142 svm->vmcb->save.sysenter_eip = data;
3144 case MSR_IA32_SYSENTER_ESP:
3145 svm->sysenter_esp = data;
3146 svm->vmcb->save.sysenter_esp = data;
3148 case MSR_IA32_DEBUGCTLMSR:
3149 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3150 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3154 if (data & DEBUGCTL_RESERVED_BITS)
3157 svm->vmcb->save.dbgctl = data;
3158 mark_dirty(svm->vmcb, VMCB_LBR);
3159 if (data & (1ULL<<0))
3160 svm_enable_lbrv(svm);
3162 svm_disable_lbrv(svm);
3164 case MSR_VM_HSAVE_PA:
3165 svm->nested.hsave_msr = data;
3168 return svm_set_vm_cr(vcpu, data);
3170 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3173 return kvm_set_msr_common(vcpu, msr);
3178 static int wrmsr_interception(struct vcpu_svm *svm)
3180 struct msr_data msr;
3181 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3182 u64 data = kvm_read_edx_eax(&svm->vcpu);
3186 msr.host_initiated = false;
3188 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3189 if (kvm_set_msr(&svm->vcpu, &msr)) {
3190 trace_kvm_msr_write_ex(ecx, data);
3191 kvm_inject_gp(&svm->vcpu, 0);
3193 trace_kvm_msr_write(ecx, data);
3194 skip_emulated_instruction(&svm->vcpu);
3199 static int msr_interception(struct vcpu_svm *svm)
3201 if (svm->vmcb->control.exit_info_1)
3202 return wrmsr_interception(svm);
3204 return rdmsr_interception(svm);
3207 static int interrupt_window_interception(struct vcpu_svm *svm)
3209 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3210 svm_clear_vintr(svm);
3211 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3212 mark_dirty(svm->vmcb, VMCB_INTR);
3213 ++svm->vcpu.stat.irq_window_exits;
3217 static int pause_interception(struct vcpu_svm *svm)
3219 kvm_vcpu_on_spin(&(svm->vcpu));
3223 static int nop_interception(struct vcpu_svm *svm)
3225 skip_emulated_instruction(&(svm->vcpu));
3229 static int monitor_interception(struct vcpu_svm *svm)
3231 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3232 return nop_interception(svm);
3235 static int mwait_interception(struct vcpu_svm *svm)
3237 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3238 return nop_interception(svm);
3241 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3242 [SVM_EXIT_READ_CR0] = cr_interception,
3243 [SVM_EXIT_READ_CR3] = cr_interception,
3244 [SVM_EXIT_READ_CR4] = cr_interception,
3245 [SVM_EXIT_READ_CR8] = cr_interception,
3246 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3247 [SVM_EXIT_WRITE_CR0] = cr_interception,
3248 [SVM_EXIT_WRITE_CR3] = cr_interception,
3249 [SVM_EXIT_WRITE_CR4] = cr_interception,
3250 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3251 [SVM_EXIT_READ_DR0] = dr_interception,
3252 [SVM_EXIT_READ_DR1] = dr_interception,
3253 [SVM_EXIT_READ_DR2] = dr_interception,
3254 [SVM_EXIT_READ_DR3] = dr_interception,
3255 [SVM_EXIT_READ_DR4] = dr_interception,
3256 [SVM_EXIT_READ_DR5] = dr_interception,
3257 [SVM_EXIT_READ_DR6] = dr_interception,
3258 [SVM_EXIT_READ_DR7] = dr_interception,
3259 [SVM_EXIT_WRITE_DR0] = dr_interception,
3260 [SVM_EXIT_WRITE_DR1] = dr_interception,
3261 [SVM_EXIT_WRITE_DR2] = dr_interception,
3262 [SVM_EXIT_WRITE_DR3] = dr_interception,
3263 [SVM_EXIT_WRITE_DR4] = dr_interception,
3264 [SVM_EXIT_WRITE_DR5] = dr_interception,
3265 [SVM_EXIT_WRITE_DR6] = dr_interception,
3266 [SVM_EXIT_WRITE_DR7] = dr_interception,
3267 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3268 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3269 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3270 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3271 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3272 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3273 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3274 [SVM_EXIT_INTR] = intr_interception,
3275 [SVM_EXIT_NMI] = nmi_interception,
3276 [SVM_EXIT_SMI] = nop_on_interception,
3277 [SVM_EXIT_INIT] = nop_on_interception,
3278 [SVM_EXIT_VINTR] = interrupt_window_interception,
3279 [SVM_EXIT_RDPMC] = rdpmc_interception,
3280 [SVM_EXIT_CPUID] = cpuid_interception,
3281 [SVM_EXIT_IRET] = iret_interception,
3282 [SVM_EXIT_INVD] = emulate_on_interception,
3283 [SVM_EXIT_PAUSE] = pause_interception,
3284 [SVM_EXIT_HLT] = halt_interception,
3285 [SVM_EXIT_INVLPG] = invlpg_interception,
3286 [SVM_EXIT_INVLPGA] = invlpga_interception,
3287 [SVM_EXIT_IOIO] = io_interception,
3288 [SVM_EXIT_MSR] = msr_interception,
3289 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3290 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3291 [SVM_EXIT_VMRUN] = vmrun_interception,
3292 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3293 [SVM_EXIT_VMLOAD] = vmload_interception,
3294 [SVM_EXIT_VMSAVE] = vmsave_interception,
3295 [SVM_EXIT_STGI] = stgi_interception,
3296 [SVM_EXIT_CLGI] = clgi_interception,
3297 [SVM_EXIT_SKINIT] = skinit_interception,
3298 [SVM_EXIT_WBINVD] = wbinvd_interception,
3299 [SVM_EXIT_MONITOR] = monitor_interception,
3300 [SVM_EXIT_MWAIT] = mwait_interception,
3301 [SVM_EXIT_XSETBV] = xsetbv_interception,
3302 [SVM_EXIT_NPF] = pf_interception,
3303 [SVM_EXIT_RSM] = emulate_on_interception,
3306 static void dump_vmcb(struct kvm_vcpu *vcpu)
3308 struct vcpu_svm *svm = to_svm(vcpu);
3309 struct vmcb_control_area *control = &svm->vmcb->control;
3310 struct vmcb_save_area *save = &svm->vmcb->save;
3312 pr_err("VMCB Control Area:\n");
3313 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3314 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3315 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3316 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3317 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3318 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3319 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3320 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3321 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3322 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3323 pr_err("%-20s%d\n", "asid:", control->asid);
3324 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3325 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3326 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3327 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3328 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3329 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3330 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3331 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3332 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3333 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3334 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3335 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3336 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3337 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3338 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3339 pr_err("VMCB State Save Area:\n");
3340 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3342 save->es.selector, save->es.attrib,
3343 save->es.limit, save->es.base);
3344 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3346 save->cs.selector, save->cs.attrib,
3347 save->cs.limit, save->cs.base);
3348 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3350 save->ss.selector, save->ss.attrib,
3351 save->ss.limit, save->ss.base);
3352 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3354 save->ds.selector, save->ds.attrib,
3355 save->ds.limit, save->ds.base);
3356 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3358 save->fs.selector, save->fs.attrib,
3359 save->fs.limit, save->fs.base);
3360 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3362 save->gs.selector, save->gs.attrib,
3363 save->gs.limit, save->gs.base);
3364 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3366 save->gdtr.selector, save->gdtr.attrib,
3367 save->gdtr.limit, save->gdtr.base);
3368 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3370 save->ldtr.selector, save->ldtr.attrib,
3371 save->ldtr.limit, save->ldtr.base);
3372 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3374 save->idtr.selector, save->idtr.attrib,
3375 save->idtr.limit, save->idtr.base);
3376 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3378 save->tr.selector, save->tr.attrib,
3379 save->tr.limit, save->tr.base);
3380 pr_err("cpl: %d efer: %016llx\n",
3381 save->cpl, save->efer);
3382 pr_err("%-15s %016llx %-13s %016llx\n",
3383 "cr0:", save->cr0, "cr2:", save->cr2);
3384 pr_err("%-15s %016llx %-13s %016llx\n",
3385 "cr3:", save->cr3, "cr4:", save->cr4);
3386 pr_err("%-15s %016llx %-13s %016llx\n",
3387 "dr6:", save->dr6, "dr7:", save->dr7);
3388 pr_err("%-15s %016llx %-13s %016llx\n",
3389 "rip:", save->rip, "rflags:", save->rflags);
3390 pr_err("%-15s %016llx %-13s %016llx\n",
3391 "rsp:", save->rsp, "rax:", save->rax);
3392 pr_err("%-15s %016llx %-13s %016llx\n",
3393 "star:", save->star, "lstar:", save->lstar);
3394 pr_err("%-15s %016llx %-13s %016llx\n",
3395 "cstar:", save->cstar, "sfmask:", save->sfmask);
3396 pr_err("%-15s %016llx %-13s %016llx\n",
3397 "kernel_gs_base:", save->kernel_gs_base,
3398 "sysenter_cs:", save->sysenter_cs);
3399 pr_err("%-15s %016llx %-13s %016llx\n",
3400 "sysenter_esp:", save->sysenter_esp,
3401 "sysenter_eip:", save->sysenter_eip);
3402 pr_err("%-15s %016llx %-13s %016llx\n",
3403 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3404 pr_err("%-15s %016llx %-13s %016llx\n",
3405 "br_from:", save->br_from, "br_to:", save->br_to);
3406 pr_err("%-15s %016llx %-13s %016llx\n",
3407 "excp_from:", save->last_excp_from,
3408 "excp_to:", save->last_excp_to);
3411 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3413 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3415 *info1 = control->exit_info_1;
3416 *info2 = control->exit_info_2;
3419 static int handle_exit(struct kvm_vcpu *vcpu)
3421 struct vcpu_svm *svm = to_svm(vcpu);
3422 struct kvm_run *kvm_run = vcpu->run;
3423 u32 exit_code = svm->vmcb->control.exit_code;
3425 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3426 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3428 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3430 if (unlikely(svm->nested.exit_required)) {
3431 nested_svm_vmexit(svm);
3432 svm->nested.exit_required = false;
3437 if (is_guest_mode(vcpu)) {
3440 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3441 svm->vmcb->control.exit_info_1,
3442 svm->vmcb->control.exit_info_2,
3443 svm->vmcb->control.exit_int_info,
3444 svm->vmcb->control.exit_int_info_err,
3447 vmexit = nested_svm_exit_special(svm);
3449 if (vmexit == NESTED_EXIT_CONTINUE)
3450 vmexit = nested_svm_exit_handled(svm);
3452 if (vmexit == NESTED_EXIT_DONE)
3456 svm_complete_interrupts(svm);
3458 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3459 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3460 kvm_run->fail_entry.hardware_entry_failure_reason
3461 = svm->vmcb->control.exit_code;
3462 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3467 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3468 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3469 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3470 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3471 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3473 __func__, svm->vmcb->control.exit_int_info,
3476 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3477 || !svm_exit_handlers[exit_code]) {
3478 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
3479 kvm_queue_exception(vcpu, UD_VECTOR);
3483 return svm_exit_handlers[exit_code](svm);
3486 static void reload_tss(struct kvm_vcpu *vcpu)
3488 int cpu = raw_smp_processor_id();
3490 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3491 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3495 static void pre_svm_run(struct vcpu_svm *svm)
3497 int cpu = raw_smp_processor_id();
3499 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3501 /* FIXME: handle wraparound of asid_generation */
3502 if (svm->asid_generation != sd->asid_generation)
3506 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3508 struct vcpu_svm *svm = to_svm(vcpu);
3510 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3511 vcpu->arch.hflags |= HF_NMI_MASK;
3512 set_intercept(svm, INTERCEPT_IRET);
3513 ++vcpu->stat.nmi_injections;
3516 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3518 struct vmcb_control_area *control;
3520 control = &svm->vmcb->control;
3521 control->int_vector = irq;
3522 control->int_ctl &= ~V_INTR_PRIO_MASK;
3523 control->int_ctl |= V_IRQ_MASK |
3524 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3525 mark_dirty(svm->vmcb, VMCB_INTR);
3528 static void svm_set_irq(struct kvm_vcpu *vcpu)
3530 struct vcpu_svm *svm = to_svm(vcpu);
3532 BUG_ON(!(gif_set(svm)));
3534 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3535 ++vcpu->stat.irq_injections;
3537 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3538 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3541 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3543 struct vcpu_svm *svm = to_svm(vcpu);
3545 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3548 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3554 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3557 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3562 static int svm_cpu_uses_apicv(struct kvm_vcpu *vcpu)
3567 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu)
3572 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3577 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3579 struct vcpu_svm *svm = to_svm(vcpu);
3580 struct vmcb *vmcb = svm->vmcb;
3582 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3583 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3584 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3589 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3591 struct vcpu_svm *svm = to_svm(vcpu);
3593 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3596 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3598 struct vcpu_svm *svm = to_svm(vcpu);
3601 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3602 set_intercept(svm, INTERCEPT_IRET);
3604 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3605 clr_intercept(svm, INTERCEPT_IRET);
3609 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3611 struct vcpu_svm *svm = to_svm(vcpu);
3612 struct vmcb *vmcb = svm->vmcb;
3615 if (!gif_set(svm) ||
3616 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3619 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3621 if (is_guest_mode(vcpu))
3622 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3627 static void enable_irq_window(struct kvm_vcpu *vcpu)
3629 struct vcpu_svm *svm = to_svm(vcpu);
3632 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3633 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3634 * get that intercept, this function will be called again though and
3635 * we'll get the vintr intercept.
3637 if (gif_set(svm) && nested_svm_intr(svm)) {
3639 svm_inject_irq(svm, 0x0);
3643 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3645 struct vcpu_svm *svm = to_svm(vcpu);
3647 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3649 return; /* IRET will cause a vm exit */
3652 * Something prevents NMI from been injected. Single step over possible
3653 * problem (IRET or exception injection or interrupt shadow)
3655 svm->nmi_singlestep = true;
3656 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3659 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3664 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3666 struct vcpu_svm *svm = to_svm(vcpu);
3668 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3669 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3671 svm->asid_generation--;
3674 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3678 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3680 struct vcpu_svm *svm = to_svm(vcpu);
3682 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3685 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3686 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3687 kvm_set_cr8(vcpu, cr8);
3691 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3693 struct vcpu_svm *svm = to_svm(vcpu);
3696 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3699 cr8 = kvm_get_cr8(vcpu);
3700 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3701 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3704 static void svm_complete_interrupts(struct vcpu_svm *svm)
3708 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3709 unsigned int3_injected = svm->int3_injected;
3711 svm->int3_injected = 0;
3714 * If we've made progress since setting HF_IRET_MASK, we've
3715 * executed an IRET and can allow NMI injection.
3717 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3718 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3719 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3720 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3723 svm->vcpu.arch.nmi_injected = false;
3724 kvm_clear_exception_queue(&svm->vcpu);
3725 kvm_clear_interrupt_queue(&svm->vcpu);
3727 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3730 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3732 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3733 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3736 case SVM_EXITINTINFO_TYPE_NMI:
3737 svm->vcpu.arch.nmi_injected = true;
3739 case SVM_EXITINTINFO_TYPE_EXEPT:
3741 * In case of software exceptions, do not reinject the vector,
3742 * but re-execute the instruction instead. Rewind RIP first
3743 * if we emulated INT3 before.
3745 if (kvm_exception_is_soft(vector)) {
3746 if (vector == BP_VECTOR && int3_injected &&
3747 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3748 kvm_rip_write(&svm->vcpu,
3749 kvm_rip_read(&svm->vcpu) -
3753 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3754 u32 err = svm->vmcb->control.exit_int_info_err;
3755 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3758 kvm_requeue_exception(&svm->vcpu, vector);
3760 case SVM_EXITINTINFO_TYPE_INTR:
3761 kvm_queue_interrupt(&svm->vcpu, vector, false);
3768 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3770 struct vcpu_svm *svm = to_svm(vcpu);
3771 struct vmcb_control_area *control = &svm->vmcb->control;
3773 control->exit_int_info = control->event_inj;
3774 control->exit_int_info_err = control->event_inj_err;
3775 control->event_inj = 0;
3776 svm_complete_interrupts(svm);
3779 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3781 struct vcpu_svm *svm = to_svm(vcpu);
3783 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3784 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3785 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3788 * A vmexit emulation is required before the vcpu can be executed
3791 if (unlikely(svm->nested.exit_required))
3796 sync_lapic_to_cr8(vcpu);
3798 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3805 "push %%" _ASM_BP "; \n\t"
3806 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3807 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3808 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3809 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3810 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3811 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3812 #ifdef CONFIG_X86_64
3813 "mov %c[r8](%[svm]), %%r8 \n\t"
3814 "mov %c[r9](%[svm]), %%r9 \n\t"
3815 "mov %c[r10](%[svm]), %%r10 \n\t"
3816 "mov %c[r11](%[svm]), %%r11 \n\t"
3817 "mov %c[r12](%[svm]), %%r12 \n\t"
3818 "mov %c[r13](%[svm]), %%r13 \n\t"
3819 "mov %c[r14](%[svm]), %%r14 \n\t"
3820 "mov %c[r15](%[svm]), %%r15 \n\t"
3823 /* Enter guest mode */
3824 "push %%" _ASM_AX " \n\t"
3825 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3826 __ex(SVM_VMLOAD) "\n\t"
3827 __ex(SVM_VMRUN) "\n\t"
3828 __ex(SVM_VMSAVE) "\n\t"
3829 "pop %%" _ASM_AX " \n\t"
3831 /* Save guest registers, load host registers */
3832 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3833 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3834 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3835 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3836 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3837 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3838 #ifdef CONFIG_X86_64
3839 "mov %%r8, %c[r8](%[svm]) \n\t"
3840 "mov %%r9, %c[r9](%[svm]) \n\t"
3841 "mov %%r10, %c[r10](%[svm]) \n\t"
3842 "mov %%r11, %c[r11](%[svm]) \n\t"
3843 "mov %%r12, %c[r12](%[svm]) \n\t"
3844 "mov %%r13, %c[r13](%[svm]) \n\t"
3845 "mov %%r14, %c[r14](%[svm]) \n\t"
3846 "mov %%r15, %c[r15](%[svm]) \n\t"
3851 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3852 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3853 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3854 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3855 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3856 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3857 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3858 #ifdef CONFIG_X86_64
3859 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3860 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3861 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3862 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3863 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3864 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3865 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3866 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3869 #ifdef CONFIG_X86_64
3870 , "rbx", "rcx", "rdx", "rsi", "rdi"
3871 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3873 , "ebx", "ecx", "edx", "esi", "edi"
3877 #ifdef CONFIG_X86_64
3878 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3880 loadsegment(fs, svm->host.fs);
3881 #ifndef CONFIG_X86_32_LAZY_GS
3882 loadsegment(gs, svm->host.gs);
3888 local_irq_disable();
3890 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3891 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3892 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3893 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3895 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3897 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3898 kvm_before_handle_nmi(&svm->vcpu);
3902 /* Any pending NMI will happen here */
3904 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3905 kvm_after_handle_nmi(&svm->vcpu);
3907 sync_cr8_to_lapic(vcpu);
3911 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3913 /* if exit due to PF check for async PF */
3914 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3915 svm->apf_reason = kvm_read_and_reset_pf_reason();
3918 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3919 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3923 * We need to handle MC intercepts here before the vcpu has a chance to
3924 * change the physical cpu
3926 if (unlikely(svm->vmcb->control.exit_code ==
3927 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3928 svm_handle_mce(svm);
3930 mark_all_clean(svm->vmcb);
3933 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3935 struct vcpu_svm *svm = to_svm(vcpu);
3937 svm->vmcb->save.cr3 = root;
3938 mark_dirty(svm->vmcb, VMCB_CR);
3939 svm_flush_tlb(vcpu);
3942 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3944 struct vcpu_svm *svm = to_svm(vcpu);
3946 svm->vmcb->control.nested_cr3 = root;
3947 mark_dirty(svm->vmcb, VMCB_NPT);
3949 /* Also sync guest cr3 here in case we live migrate */
3950 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3951 mark_dirty(svm->vmcb, VMCB_CR);
3953 svm_flush_tlb(vcpu);
3956 static int is_disabled(void)
3960 rdmsrl(MSR_VM_CR, vm_cr);
3961 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3968 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3971 * Patch in the VMMCALL instruction:
3973 hypercall[0] = 0x0f;
3974 hypercall[1] = 0x01;
3975 hypercall[2] = 0xd9;
3978 static void svm_check_processor_compat(void *rtn)
3983 static bool svm_cpu_has_accelerated_tpr(void)
3988 static bool svm_has_high_real_mode_segbase(void)
3993 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3998 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4000 struct vcpu_svm *svm = to_svm(vcpu);
4002 /* Update nrips enabled cache */
4003 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
4006 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4011 entry->ecx |= (1 << 2); /* Set SVM bit */
4014 entry->eax = 1; /* SVM revision 1 */
4015 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4016 ASID emulation to nested SVM */
4017 entry->ecx = 0; /* Reserved */
4018 entry->edx = 0; /* Per default do not support any
4019 additional features */
4021 /* Support next_rip if host supports it */
4022 if (boot_cpu_has(X86_FEATURE_NRIPS))
4023 entry->edx |= SVM_FEATURE_NRIP;
4025 /* Support NPT for the guest if enabled */
4027 entry->edx |= SVM_FEATURE_NPT;
4033 static int svm_get_lpage_level(void)
4035 return PT_PDPE_LEVEL;
4038 static bool svm_rdtscp_supported(void)
4043 static bool svm_invpcid_supported(void)
4048 static bool svm_mpx_supported(void)
4053 static bool svm_xsaves_supported(void)
4058 static bool svm_has_wbinvd_exit(void)
4063 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4065 struct vcpu_svm *svm = to_svm(vcpu);
4067 set_exception_intercept(svm, NM_VECTOR);
4068 update_cr0_intercept(svm);
4071 #define PRE_EX(exit) { .exit_code = (exit), \
4072 .stage = X86_ICPT_PRE_EXCEPT, }
4073 #define POST_EX(exit) { .exit_code = (exit), \
4074 .stage = X86_ICPT_POST_EXCEPT, }
4075 #define POST_MEM(exit) { .exit_code = (exit), \
4076 .stage = X86_ICPT_POST_MEMACCESS, }
4078 static const struct __x86_intercept {
4080 enum x86_intercept_stage stage;
4081 } x86_intercept_map[] = {
4082 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4083 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4084 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4085 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4086 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4087 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4088 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4089 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4090 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4091 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4092 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4093 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4094 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4095 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4096 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4097 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4098 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4099 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4100 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4101 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4102 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4103 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4104 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4105 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4106 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4107 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4108 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4109 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4110 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4111 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4112 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4113 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4114 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4115 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4116 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4117 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4118 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4119 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4120 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4121 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4122 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4123 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4124 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4125 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4126 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4127 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4134 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4135 struct x86_instruction_info *info,
4136 enum x86_intercept_stage stage)
4138 struct vcpu_svm *svm = to_svm(vcpu);
4139 int vmexit, ret = X86EMUL_CONTINUE;
4140 struct __x86_intercept icpt_info;
4141 struct vmcb *vmcb = svm->vmcb;
4143 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4146 icpt_info = x86_intercept_map[info->intercept];
4148 if (stage != icpt_info.stage)
4151 switch (icpt_info.exit_code) {
4152 case SVM_EXIT_READ_CR0:
4153 if (info->intercept == x86_intercept_cr_read)
4154 icpt_info.exit_code += info->modrm_reg;
4156 case SVM_EXIT_WRITE_CR0: {
4157 unsigned long cr0, val;
4160 if (info->intercept == x86_intercept_cr_write)
4161 icpt_info.exit_code += info->modrm_reg;
4163 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4164 info->intercept == x86_intercept_clts)
4167 intercept = svm->nested.intercept;
4169 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4172 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4173 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4175 if (info->intercept == x86_intercept_lmsw) {
4178 /* lmsw can't clear PE - catch this here */
4179 if (cr0 & X86_CR0_PE)
4184 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4188 case SVM_EXIT_READ_DR0:
4189 case SVM_EXIT_WRITE_DR0:
4190 icpt_info.exit_code += info->modrm_reg;
4193 if (info->intercept == x86_intercept_wrmsr)
4194 vmcb->control.exit_info_1 = 1;
4196 vmcb->control.exit_info_1 = 0;
4198 case SVM_EXIT_PAUSE:
4200 * We get this for NOP only, but pause
4201 * is rep not, check this here
4203 if (info->rep_prefix != REPE_PREFIX)
4205 case SVM_EXIT_IOIO: {
4209 if (info->intercept == x86_intercept_in ||
4210 info->intercept == x86_intercept_ins) {
4211 exit_info = ((info->src_val & 0xffff) << 16) |
4213 bytes = info->dst_bytes;
4215 exit_info = (info->dst_val & 0xffff) << 16;
4216 bytes = info->src_bytes;
4219 if (info->intercept == x86_intercept_outs ||
4220 info->intercept == x86_intercept_ins)
4221 exit_info |= SVM_IOIO_STR_MASK;
4223 if (info->rep_prefix)
4224 exit_info |= SVM_IOIO_REP_MASK;
4226 bytes = min(bytes, 4u);
4228 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4230 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4232 vmcb->control.exit_info_1 = exit_info;
4233 vmcb->control.exit_info_2 = info->next_rip;
4241 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4242 if (static_cpu_has(X86_FEATURE_NRIPS))
4243 vmcb->control.next_rip = info->next_rip;
4244 vmcb->control.exit_code = icpt_info.exit_code;
4245 vmexit = nested_svm_exit_handled(svm);
4247 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4254 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4259 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4263 static struct kvm_x86_ops svm_x86_ops = {
4264 .cpu_has_kvm_support = has_svm,
4265 .disabled_by_bios = is_disabled,
4266 .hardware_setup = svm_hardware_setup,
4267 .hardware_unsetup = svm_hardware_unsetup,
4268 .check_processor_compatibility = svm_check_processor_compat,
4269 .hardware_enable = svm_hardware_enable,
4270 .hardware_disable = svm_hardware_disable,
4271 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4272 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
4274 .vcpu_create = svm_create_vcpu,
4275 .vcpu_free = svm_free_vcpu,
4276 .vcpu_reset = svm_vcpu_reset,
4278 .prepare_guest_switch = svm_prepare_guest_switch,
4279 .vcpu_load = svm_vcpu_load,
4280 .vcpu_put = svm_vcpu_put,
4282 .update_bp_intercept = update_bp_intercept,
4283 .get_msr = svm_get_msr,
4284 .set_msr = svm_set_msr,
4285 .get_segment_base = svm_get_segment_base,
4286 .get_segment = svm_get_segment,
4287 .set_segment = svm_set_segment,
4288 .get_cpl = svm_get_cpl,
4289 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4290 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4291 .decache_cr3 = svm_decache_cr3,
4292 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4293 .set_cr0 = svm_set_cr0,
4294 .set_cr3 = svm_set_cr3,
4295 .set_cr4 = svm_set_cr4,
4296 .set_efer = svm_set_efer,
4297 .get_idt = svm_get_idt,
4298 .set_idt = svm_set_idt,
4299 .get_gdt = svm_get_gdt,
4300 .set_gdt = svm_set_gdt,
4301 .get_dr6 = svm_get_dr6,
4302 .set_dr6 = svm_set_dr6,
4303 .set_dr7 = svm_set_dr7,
4304 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4305 .cache_reg = svm_cache_reg,
4306 .get_rflags = svm_get_rflags,
4307 .set_rflags = svm_set_rflags,
4308 .fpu_activate = svm_fpu_activate,
4309 .fpu_deactivate = svm_fpu_deactivate,
4311 .tlb_flush = svm_flush_tlb,
4313 .run = svm_vcpu_run,
4314 .handle_exit = handle_exit,
4315 .skip_emulated_instruction = skip_emulated_instruction,
4316 .set_interrupt_shadow = svm_set_interrupt_shadow,
4317 .get_interrupt_shadow = svm_get_interrupt_shadow,
4318 .patch_hypercall = svm_patch_hypercall,
4319 .set_irq = svm_set_irq,
4320 .set_nmi = svm_inject_nmi,
4321 .queue_exception = svm_queue_exception,
4322 .cancel_injection = svm_cancel_injection,
4323 .interrupt_allowed = svm_interrupt_allowed,
4324 .nmi_allowed = svm_nmi_allowed,
4325 .get_nmi_mask = svm_get_nmi_mask,
4326 .set_nmi_mask = svm_set_nmi_mask,
4327 .enable_nmi_window = enable_nmi_window,
4328 .enable_irq_window = enable_irq_window,
4329 .update_cr8_intercept = update_cr8_intercept,
4330 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4331 .cpu_uses_apicv = svm_cpu_uses_apicv,
4332 .load_eoi_exitmap = svm_load_eoi_exitmap,
4333 .sync_pir_to_irr = svm_sync_pir_to_irr,
4335 .set_tss_addr = svm_set_tss_addr,
4336 .get_tdp_level = get_npt_level,
4337 .get_mt_mask = svm_get_mt_mask,
4339 .get_exit_info = svm_get_exit_info,
4341 .get_lpage_level = svm_get_lpage_level,
4343 .cpuid_update = svm_cpuid_update,
4345 .rdtscp_supported = svm_rdtscp_supported,
4346 .invpcid_supported = svm_invpcid_supported,
4347 .mpx_supported = svm_mpx_supported,
4348 .xsaves_supported = svm_xsaves_supported,
4350 .set_supported_cpuid = svm_set_supported_cpuid,
4352 .has_wbinvd_exit = svm_has_wbinvd_exit,
4354 .read_tsc_offset = svm_read_tsc_offset,
4355 .write_tsc_offset = svm_write_tsc_offset,
4356 .adjust_tsc_offset_guest = svm_adjust_tsc_offset_guest,
4357 .read_l1_tsc = svm_read_l1_tsc,
4359 .set_tdp_cr3 = set_tdp_cr3,
4361 .check_intercept = svm_check_intercept,
4362 .handle_external_intr = svm_handle_external_intr,
4364 .sched_in = svm_sched_in,
4366 .pmu_ops = &amd_pmu_ops,
4369 static int __init svm_init(void)
4371 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4372 __alignof__(struct vcpu_svm), THIS_MODULE);
4375 static void __exit svm_exit(void)
4380 module_init(svm_init)
4381 module_exit(svm_exit)