2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
32 #include <asm/virtext.h>
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
40 #define IOPM_ALLOC_ORDER 2
41 #define MSRPM_ALLOC_ORDER 1
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_FEATURE_SVML (1 << 2)
49 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
51 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
52 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
53 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
55 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
57 static const u32 host_save_user_msrs[] = {
59 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
74 /* These are the merged vectors */
77 /* gpa pointers to the real vectors */
80 /* A VMEXIT is required but not yet emulated */
83 /* cache for intercepts of the guest */
84 u16 intercept_cr_read;
85 u16 intercept_cr_write;
86 u16 intercept_dr_read;
87 u16 intercept_dr_write;
88 u32 intercept_exceptions;
96 unsigned long vmcb_pa;
97 struct svm_cpu_data *svm_data;
98 uint64_t asid_generation;
99 uint64_t sysenter_esp;
100 uint64_t sysenter_eip;
104 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
109 struct nested_state nested;
114 /* enable NPT for AMD64 and X86 with PAE */
115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116 static bool npt_enabled = true;
118 static bool npt_enabled = false;
122 module_param(npt, int, S_IRUGO);
124 static int nested = 1;
125 module_param(nested, int, S_IRUGO);
127 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
128 static void svm_complete_interrupts(struct vcpu_svm *svm);
130 static int nested_svm_exit_handled(struct vcpu_svm *svm);
131 static int nested_svm_vmexit(struct vcpu_svm *svm);
132 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
133 bool has_error_code, u32 error_code);
135 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
137 return container_of(vcpu, struct vcpu_svm, vcpu);
140 static inline bool is_nested(struct vcpu_svm *svm)
142 return svm->nested.vmcb;
145 static inline void enable_gif(struct vcpu_svm *svm)
147 svm->vcpu.arch.hflags |= HF_GIF_MASK;
150 static inline void disable_gif(struct vcpu_svm *svm)
152 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
155 static inline bool gif_set(struct vcpu_svm *svm)
157 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
160 static unsigned long iopm_base;
162 struct kvm_ldttss_desc {
165 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
166 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
169 } __attribute__((packed));
171 struct svm_cpu_data {
177 struct kvm_ldttss_desc *tss_desc;
179 struct page *save_area;
182 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
183 static uint32_t svm_features;
185 struct svm_init_data {
190 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
192 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
193 #define MSRS_RANGE_SIZE 2048
194 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
196 #define MAX_INST_SIZE 15
198 static inline u32 svm_has(u32 feat)
200 return svm_features & feat;
203 static inline void clgi(void)
205 asm volatile (__ex(SVM_CLGI));
208 static inline void stgi(void)
210 asm volatile (__ex(SVM_STGI));
213 static inline void invlpga(unsigned long addr, u32 asid)
215 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
218 static inline void force_new_asid(struct kvm_vcpu *vcpu)
220 to_svm(vcpu)->asid_generation--;
223 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
225 force_new_asid(vcpu);
228 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
230 if (!npt_enabled && !(efer & EFER_LMA))
233 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
234 vcpu->arch.shadow_efer = efer;
237 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
238 bool has_error_code, u32 error_code)
240 struct vcpu_svm *svm = to_svm(vcpu);
242 /* If we are within a nested VM we'd better #VMEXIT and let the
243 guest handle the exception */
244 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
247 svm->vmcb->control.event_inj = nr
249 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
250 | SVM_EVTINJ_TYPE_EXEPT;
251 svm->vmcb->control.event_inj_err = error_code;
254 static int is_external_interrupt(u32 info)
256 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
257 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
260 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
262 struct vcpu_svm *svm = to_svm(vcpu);
265 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
266 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
270 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
272 struct vcpu_svm *svm = to_svm(vcpu);
275 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
277 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
281 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
283 struct vcpu_svm *svm = to_svm(vcpu);
285 if (!svm->next_rip) {
286 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
288 printk(KERN_DEBUG "%s: NOP\n", __func__);
291 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
292 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
293 __func__, kvm_rip_read(vcpu), svm->next_rip);
295 kvm_rip_write(vcpu, svm->next_rip);
296 svm_set_interrupt_shadow(vcpu, 0);
299 static int has_svm(void)
303 if (!cpu_has_svm(&msg)) {
304 printk(KERN_INFO "has_svm: %s\n", msg);
311 static void svm_hardware_disable(void *garbage)
316 static int svm_hardware_enable(void *garbage)
319 struct svm_cpu_data *sd;
321 struct descriptor_table gdt_descr;
322 struct desc_struct *gdt;
323 int me = raw_smp_processor_id();
325 rdmsrl(MSR_EFER, efer);
326 if (efer & EFER_SVME)
330 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
334 sd = per_cpu(svm_data, me);
337 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
342 sd->asid_generation = 1;
343 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
344 sd->next_asid = sd->max_asid + 1;
346 kvm_get_gdt(&gdt_descr);
347 gdt = (struct desc_struct *)gdt_descr.base;
348 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
350 wrmsrl(MSR_EFER, efer | EFER_SVME);
352 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
357 static void svm_cpu_uninit(int cpu)
359 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
364 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
365 __free_page(sd->save_area);
369 static int svm_cpu_init(int cpu)
371 struct svm_cpu_data *sd;
374 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
378 sd->save_area = alloc_page(GFP_KERNEL);
383 per_cpu(svm_data, cpu) = sd;
393 static void set_msr_interception(u32 *msrpm, unsigned msr,
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr >= msrpm_ranges[i] &&
400 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
401 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
402 msrpm_ranges[i]) * 2;
404 u32 *base = msrpm + (msr_offset / 32);
405 u32 msr_shift = msr_offset % 32;
406 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
407 *base = (*base & ~(0x3 << msr_shift)) |
415 static void svm_vcpu_init_msrpm(u32 *msrpm)
417 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
420 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
425 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
427 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
428 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
431 static void svm_enable_lbrv(struct vcpu_svm *svm)
433 u32 *msrpm = svm->msrpm;
435 svm->vmcb->control.lbr_ctl = 1;
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
442 static void svm_disable_lbrv(struct vcpu_svm *svm)
444 u32 *msrpm = svm->msrpm;
446 svm->vmcb->control.lbr_ctl = 0;
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
453 static __init int svm_hardware_setup(void)
456 struct page *iopm_pages;
460 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
465 iopm_va = page_address(iopm_pages);
466 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
467 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
469 if (boot_cpu_has(X86_FEATURE_NX))
470 kvm_enable_efer_bits(EFER_NX);
472 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
473 kvm_enable_efer_bits(EFER_FFXSR);
476 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
477 kvm_enable_efer_bits(EFER_SVME);
480 for_each_possible_cpu(cpu) {
481 r = svm_cpu_init(cpu);
486 svm_features = cpuid_edx(SVM_CPUID_FUNC);
488 if (!svm_has(SVM_FEATURE_NPT))
491 if (npt_enabled && !npt) {
492 printk(KERN_INFO "kvm: Nested Paging disabled\n");
497 printk(KERN_INFO "kvm: Nested Paging enabled\n");
505 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
510 static __exit void svm_hardware_unsetup(void)
514 for_each_possible_cpu(cpu)
517 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
521 static void init_seg(struct vmcb_seg *seg)
524 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
525 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
530 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
533 seg->attrib = SVM_SELECTOR_P_MASK | type;
538 static void init_vmcb(struct vcpu_svm *svm)
540 struct vmcb_control_area *control = &svm->vmcb->control;
541 struct vmcb_save_area *save = &svm->vmcb->save;
543 svm->vcpu.fpu_active = 1;
545 control->intercept_cr_read = INTERCEPT_CR0_MASK |
549 control->intercept_cr_write = INTERCEPT_CR0_MASK |
554 control->intercept_dr_read = INTERCEPT_DR0_MASK |
559 control->intercept_dr_write = INTERCEPT_DR0_MASK |
566 control->intercept_exceptions = (1 << PF_VECTOR) |
571 control->intercept = (1ULL << INTERCEPT_INTR) |
572 (1ULL << INTERCEPT_NMI) |
573 (1ULL << INTERCEPT_SMI) |
574 (1ULL << INTERCEPT_SELECTIVE_CR0) |
575 (1ULL << INTERCEPT_CPUID) |
576 (1ULL << INTERCEPT_INVD) |
577 (1ULL << INTERCEPT_HLT) |
578 (1ULL << INTERCEPT_INVLPG) |
579 (1ULL << INTERCEPT_INVLPGA) |
580 (1ULL << INTERCEPT_IOIO_PROT) |
581 (1ULL << INTERCEPT_MSR_PROT) |
582 (1ULL << INTERCEPT_TASK_SWITCH) |
583 (1ULL << INTERCEPT_SHUTDOWN) |
584 (1ULL << INTERCEPT_VMRUN) |
585 (1ULL << INTERCEPT_VMMCALL) |
586 (1ULL << INTERCEPT_VMLOAD) |
587 (1ULL << INTERCEPT_VMSAVE) |
588 (1ULL << INTERCEPT_STGI) |
589 (1ULL << INTERCEPT_CLGI) |
590 (1ULL << INTERCEPT_SKINIT) |
591 (1ULL << INTERCEPT_WBINVD) |
592 (1ULL << INTERCEPT_MONITOR) |
593 (1ULL << INTERCEPT_MWAIT);
595 control->iopm_base_pa = iopm_base;
596 control->msrpm_base_pa = __pa(svm->msrpm);
597 control->tsc_offset = 0;
598 control->int_ctl = V_INTR_MASKING_MASK;
606 save->cs.selector = 0xf000;
607 /* Executable/Readable Code Segment */
608 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
609 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
610 save->cs.limit = 0xffff;
612 * cs.base should really be 0xffff0000, but vmx can't handle that, so
613 * be consistent with it.
615 * Replace when we have real mode working for vmx.
617 save->cs.base = 0xf0000;
619 save->gdtr.limit = 0xffff;
620 save->idtr.limit = 0xffff;
622 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
623 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
625 save->efer = EFER_SVME;
626 save->dr6 = 0xffff0ff0;
629 save->rip = 0x0000fff0;
630 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
632 /* This is the guest-visible cr0 value.
633 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
635 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
636 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
638 save->cr4 = X86_CR4_PAE;
642 /* Setup VMCB for Nested Paging */
643 control->nested_ctl = 1;
644 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
645 (1ULL << INTERCEPT_INVLPG));
646 control->intercept_exceptions &= ~(1 << PF_VECTOR);
647 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
648 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
649 save->g_pat = 0x0007040600070406ULL;
653 force_new_asid(&svm->vcpu);
655 svm->nested.vmcb = 0;
656 svm->vcpu.arch.hflags = 0;
658 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
659 control->pause_filter_count = 3000;
660 control->intercept |= (1ULL << INTERCEPT_PAUSE);
666 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
668 struct vcpu_svm *svm = to_svm(vcpu);
672 if (!kvm_vcpu_is_bsp(vcpu)) {
673 kvm_rip_write(vcpu, 0);
674 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
675 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
677 vcpu->arch.regs_avail = ~0;
678 vcpu->arch.regs_dirty = ~0;
683 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
685 struct vcpu_svm *svm;
687 struct page *msrpm_pages;
688 struct page *hsave_page;
689 struct page *nested_msrpm_pages;
692 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
698 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
702 page = alloc_page(GFP_KERNEL);
709 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
713 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
714 if (!nested_msrpm_pages)
717 svm->msrpm = page_address(msrpm_pages);
718 svm_vcpu_init_msrpm(svm->msrpm);
720 hsave_page = alloc_page(GFP_KERNEL);
723 svm->nested.hsave = page_address(hsave_page);
725 svm->nested.msrpm = page_address(nested_msrpm_pages);
727 svm->vmcb = page_address(page);
728 clear_page(svm->vmcb);
729 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
730 svm->asid_generation = 0;
734 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
735 if (kvm_vcpu_is_bsp(&svm->vcpu))
736 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
741 kvm_vcpu_uninit(&svm->vcpu);
743 kmem_cache_free(kvm_vcpu_cache, svm);
748 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
750 struct vcpu_svm *svm = to_svm(vcpu);
752 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
753 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
754 __free_page(virt_to_page(svm->nested.hsave));
755 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
756 kvm_vcpu_uninit(vcpu);
757 kmem_cache_free(kvm_vcpu_cache, svm);
760 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
762 struct vcpu_svm *svm = to_svm(vcpu);
765 if (unlikely(cpu != vcpu->cpu)) {
768 if (check_tsc_unstable()) {
770 * Make sure that the guest sees a monotonically
773 delta = vcpu->arch.host_tsc - native_read_tsc();
774 svm->vmcb->control.tsc_offset += delta;
776 svm->nested.hsave->control.tsc_offset += delta;
779 kvm_migrate_timers(vcpu);
780 svm->asid_generation = 0;
783 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
784 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
787 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
789 struct vcpu_svm *svm = to_svm(vcpu);
792 ++vcpu->stat.host_state_reload;
793 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
794 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
796 vcpu->arch.host_tsc = native_read_tsc();
799 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
801 return to_svm(vcpu)->vmcb->save.rflags;
804 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
806 to_svm(vcpu)->vmcb->save.rflags = rflags;
809 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
812 case VCPU_EXREG_PDPTR:
813 BUG_ON(!npt_enabled);
814 load_pdptrs(vcpu, vcpu->arch.cr3);
821 static void svm_set_vintr(struct vcpu_svm *svm)
823 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
826 static void svm_clear_vintr(struct vcpu_svm *svm)
828 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
831 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
833 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
836 case VCPU_SREG_CS: return &save->cs;
837 case VCPU_SREG_DS: return &save->ds;
838 case VCPU_SREG_ES: return &save->es;
839 case VCPU_SREG_FS: return &save->fs;
840 case VCPU_SREG_GS: return &save->gs;
841 case VCPU_SREG_SS: return &save->ss;
842 case VCPU_SREG_TR: return &save->tr;
843 case VCPU_SREG_LDTR: return &save->ldtr;
849 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
851 struct vmcb_seg *s = svm_seg(vcpu, seg);
856 static void svm_get_segment(struct kvm_vcpu *vcpu,
857 struct kvm_segment *var, int seg)
859 struct vmcb_seg *s = svm_seg(vcpu, seg);
862 var->limit = s->limit;
863 var->selector = s->selector;
864 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
865 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
866 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
867 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
868 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
869 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
870 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
871 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
873 /* AMD's VMCB does not have an explicit unusable field, so emulate it
874 * for cross vendor migration purposes by "not present"
876 var->unusable = !var->present || (var->type == 0);
881 * SVM always stores 0 for the 'G' bit in the CS selector in
882 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
883 * Intel's VMENTRY has a check on the 'G' bit.
885 var->g = s->limit > 0xfffff;
889 * Work around a bug where the busy flag in the tr selector
899 * The accessed bit must always be set in the segment
900 * descriptor cache, although it can be cleared in the
901 * descriptor, the cached bit always remains at 1. Since
902 * Intel has a check on this, set it here to support
903 * cross-vendor migration.
909 /* On AMD CPUs sometimes the DB bit in the segment
910 * descriptor is left as 1, although the whole segment has
911 * been made unusable. Clear it here to pass an Intel VMX
912 * entry check when cross vendor migrating.
920 static int svm_get_cpl(struct kvm_vcpu *vcpu)
922 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
927 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
929 struct vcpu_svm *svm = to_svm(vcpu);
931 dt->limit = svm->vmcb->save.idtr.limit;
932 dt->base = svm->vmcb->save.idtr.base;
935 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
937 struct vcpu_svm *svm = to_svm(vcpu);
939 svm->vmcb->save.idtr.limit = dt->limit;
940 svm->vmcb->save.idtr.base = dt->base ;
943 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
945 struct vcpu_svm *svm = to_svm(vcpu);
947 dt->limit = svm->vmcb->save.gdtr.limit;
948 dt->base = svm->vmcb->save.gdtr.base;
951 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
953 struct vcpu_svm *svm = to_svm(vcpu);
955 svm->vmcb->save.gdtr.limit = dt->limit;
956 svm->vmcb->save.gdtr.base = dt->base ;
959 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
963 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
967 static void update_cr0_intercept(struct vcpu_svm *svm)
969 ulong gcr0 = svm->vcpu.arch.cr0;
970 u64 *hcr0 = &svm->vmcb->save.cr0;
972 if (!svm->vcpu.fpu_active)
973 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
975 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
976 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
979 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
980 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
981 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
983 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
984 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
988 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
990 struct vcpu_svm *svm = to_svm(vcpu);
993 if (vcpu->arch.shadow_efer & EFER_LME) {
994 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
995 vcpu->arch.shadow_efer |= EFER_LMA;
996 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
999 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1000 vcpu->arch.shadow_efer &= ~EFER_LMA;
1001 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1005 vcpu->arch.cr0 = cr0;
1008 cr0 |= X86_CR0_PG | X86_CR0_WP;
1010 if (!vcpu->fpu_active)
1013 * re-enable caching here because the QEMU bios
1014 * does not do it - this results in some delay at
1017 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1018 svm->vmcb->save.cr0 = cr0;
1019 update_cr0_intercept(svm);
1022 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1024 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1025 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1027 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1028 force_new_asid(vcpu);
1030 vcpu->arch.cr4 = cr4;
1033 cr4 |= host_cr4_mce;
1034 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1037 static void svm_set_segment(struct kvm_vcpu *vcpu,
1038 struct kvm_segment *var, int seg)
1040 struct vcpu_svm *svm = to_svm(vcpu);
1041 struct vmcb_seg *s = svm_seg(vcpu, seg);
1043 s->base = var->base;
1044 s->limit = var->limit;
1045 s->selector = var->selector;
1049 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1050 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1051 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1052 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1053 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1054 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1055 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1056 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1058 if (seg == VCPU_SREG_CS)
1060 = (svm->vmcb->save.cs.attrib
1061 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1065 static void update_db_intercept(struct kvm_vcpu *vcpu)
1067 struct vcpu_svm *svm = to_svm(vcpu);
1069 svm->vmcb->control.intercept_exceptions &=
1070 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1072 if (svm->nmi_singlestep)
1073 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1075 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1076 if (vcpu->guest_debug &
1077 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1078 svm->vmcb->control.intercept_exceptions |=
1080 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1081 svm->vmcb->control.intercept_exceptions |=
1084 vcpu->guest_debug = 0;
1087 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1089 struct vcpu_svm *svm = to_svm(vcpu);
1091 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1092 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1094 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1096 update_db_intercept(vcpu);
1099 static void load_host_msrs(struct kvm_vcpu *vcpu)
1101 #ifdef CONFIG_X86_64
1102 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1106 static void save_host_msrs(struct kvm_vcpu *vcpu)
1108 #ifdef CONFIG_X86_64
1109 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1113 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1115 if (sd->next_asid > sd->max_asid) {
1116 ++sd->asid_generation;
1118 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1121 svm->asid_generation = sd->asid_generation;
1122 svm->vmcb->control.asid = sd->next_asid++;
1125 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1127 struct vcpu_svm *svm = to_svm(vcpu);
1132 val = vcpu->arch.db[dr];
1135 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1136 val = vcpu->arch.dr6;
1138 val = svm->vmcb->save.dr6;
1141 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1142 val = vcpu->arch.dr7;
1144 val = svm->vmcb->save.dr7;
1153 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1156 struct vcpu_svm *svm = to_svm(vcpu);
1162 vcpu->arch.db[dr] = value;
1163 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1164 vcpu->arch.eff_db[dr] = value;
1167 if (vcpu->arch.cr4 & X86_CR4_DE)
1168 *exception = UD_VECTOR;
1171 if (value & 0xffffffff00000000ULL) {
1172 *exception = GP_VECTOR;
1175 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1178 if (value & 0xffffffff00000000ULL) {
1179 *exception = GP_VECTOR;
1182 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1183 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1184 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1185 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1189 /* FIXME: Possible case? */
1190 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1192 *exception = UD_VECTOR;
1197 static int pf_interception(struct vcpu_svm *svm)
1202 fault_address = svm->vmcb->control.exit_info_2;
1203 error_code = svm->vmcb->control.exit_info_1;
1205 trace_kvm_page_fault(fault_address, error_code);
1206 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1207 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1208 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1211 static int db_interception(struct vcpu_svm *svm)
1213 struct kvm_run *kvm_run = svm->vcpu.run;
1215 if (!(svm->vcpu.guest_debug &
1216 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1217 !svm->nmi_singlestep) {
1218 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1222 if (svm->nmi_singlestep) {
1223 svm->nmi_singlestep = false;
1224 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1225 svm->vmcb->save.rflags &=
1226 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1227 update_db_intercept(&svm->vcpu);
1230 if (svm->vcpu.guest_debug &
1231 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1232 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1233 kvm_run->debug.arch.pc =
1234 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1235 kvm_run->debug.arch.exception = DB_VECTOR;
1242 static int bp_interception(struct vcpu_svm *svm)
1244 struct kvm_run *kvm_run = svm->vcpu.run;
1246 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1247 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1248 kvm_run->debug.arch.exception = BP_VECTOR;
1252 static int ud_interception(struct vcpu_svm *svm)
1256 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1257 if (er != EMULATE_DONE)
1258 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1262 static int nm_interception(struct vcpu_svm *svm)
1264 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1265 svm->vcpu.fpu_active = 1;
1266 update_cr0_intercept(svm);
1271 static int mc_interception(struct vcpu_svm *svm)
1274 * On an #MC intercept the MCE handler is not called automatically in
1275 * the host. So do it by hand here.
1279 /* not sure if we ever come back to this point */
1284 static int shutdown_interception(struct vcpu_svm *svm)
1286 struct kvm_run *kvm_run = svm->vcpu.run;
1289 * VMCB is undefined after a SHUTDOWN intercept
1290 * so reinitialize it.
1292 clear_page(svm->vmcb);
1295 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1299 static int io_interception(struct vcpu_svm *svm)
1301 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1302 int size, in, string;
1305 ++svm->vcpu.stat.io_exits;
1307 svm->next_rip = svm->vmcb->control.exit_info_2;
1309 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1312 if (emulate_instruction(&svm->vcpu,
1313 0, 0, 0) == EMULATE_DO_MMIO)
1318 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1319 port = io_info >> 16;
1320 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1322 skip_emulated_instruction(&svm->vcpu);
1323 return kvm_emulate_pio(&svm->vcpu, in, size, port);
1326 static int nmi_interception(struct vcpu_svm *svm)
1331 static int intr_interception(struct vcpu_svm *svm)
1333 ++svm->vcpu.stat.irq_exits;
1337 static int nop_on_interception(struct vcpu_svm *svm)
1342 static int halt_interception(struct vcpu_svm *svm)
1344 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1345 skip_emulated_instruction(&svm->vcpu);
1346 return kvm_emulate_halt(&svm->vcpu);
1349 static int vmmcall_interception(struct vcpu_svm *svm)
1351 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1352 skip_emulated_instruction(&svm->vcpu);
1353 kvm_emulate_hypercall(&svm->vcpu);
1357 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1359 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1360 || !is_paging(&svm->vcpu)) {
1361 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1365 if (svm->vmcb->save.cpl) {
1366 kvm_inject_gp(&svm->vcpu, 0);
1373 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1374 bool has_error_code, u32 error_code)
1376 if (!is_nested(svm))
1379 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1380 svm->vmcb->control.exit_code_hi = 0;
1381 svm->vmcb->control.exit_info_1 = error_code;
1382 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1384 return nested_svm_exit_handled(svm);
1387 static inline int nested_svm_intr(struct vcpu_svm *svm)
1389 if (!is_nested(svm))
1392 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1395 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1398 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1400 if (svm->nested.intercept & 1ULL) {
1402 * The #vmexit can't be emulated here directly because this
1403 * code path runs with irqs and preemtion disabled. A
1404 * #vmexit emulation might sleep. Only signal request for
1407 svm->nested.exit_required = true;
1408 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1415 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1419 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1420 if (is_error_page(page))
1423 return kmap_atomic(page, idx);
1426 kvm_release_page_clean(page);
1427 kvm_inject_gp(&svm->vcpu, 0);
1432 static void nested_svm_unmap(void *addr, enum km_type idx)
1439 page = kmap_atomic_to_page(addr);
1441 kunmap_atomic(addr, idx);
1442 kvm_release_page_dirty(page);
1445 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1447 u32 param = svm->vmcb->control.exit_info_1 & 1;
1448 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1453 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1456 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1466 case 0xc0000000 ... 0xc0001fff:
1467 t0 = (8192 + msr - 0xc0000000) * 2;
1471 case 0xc0010000 ... 0xc0011fff:
1472 t0 = (16384 + msr - 0xc0010000) * 2;
1481 ret = msrpm[t1] & ((1 << param) << t0);
1484 nested_svm_unmap(msrpm, KM_USER0);
1489 static int nested_svm_exit_special(struct vcpu_svm *svm)
1491 u32 exit_code = svm->vmcb->control.exit_code;
1493 switch (exit_code) {
1496 return NESTED_EXIT_HOST;
1497 /* For now we are always handling NPFs when using them */
1500 return NESTED_EXIT_HOST;
1502 /* When we're shadowing, trap PFs */
1503 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1505 return NESTED_EXIT_HOST;
1511 return NESTED_EXIT_CONTINUE;
1515 * If this function returns true, this #vmexit was already handled
1517 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1519 u32 exit_code = svm->vmcb->control.exit_code;
1520 int vmexit = NESTED_EXIT_HOST;
1522 switch (exit_code) {
1524 vmexit = nested_svm_exit_handled_msr(svm);
1526 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1527 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1528 if (svm->nested.intercept_cr_read & cr_bits)
1529 vmexit = NESTED_EXIT_DONE;
1532 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1533 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1534 if (svm->nested.intercept_cr_write & cr_bits)
1535 vmexit = NESTED_EXIT_DONE;
1538 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1539 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1540 if (svm->nested.intercept_dr_read & dr_bits)
1541 vmexit = NESTED_EXIT_DONE;
1544 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1545 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1546 if (svm->nested.intercept_dr_write & dr_bits)
1547 vmexit = NESTED_EXIT_DONE;
1550 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1551 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1552 if (svm->nested.intercept_exceptions & excp_bits)
1553 vmexit = NESTED_EXIT_DONE;
1557 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1558 if (svm->nested.intercept & exit_bits)
1559 vmexit = NESTED_EXIT_DONE;
1563 if (vmexit == NESTED_EXIT_DONE) {
1564 nested_svm_vmexit(svm);
1570 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1572 struct vmcb_control_area *dst = &dst_vmcb->control;
1573 struct vmcb_control_area *from = &from_vmcb->control;
1575 dst->intercept_cr_read = from->intercept_cr_read;
1576 dst->intercept_cr_write = from->intercept_cr_write;
1577 dst->intercept_dr_read = from->intercept_dr_read;
1578 dst->intercept_dr_write = from->intercept_dr_write;
1579 dst->intercept_exceptions = from->intercept_exceptions;
1580 dst->intercept = from->intercept;
1581 dst->iopm_base_pa = from->iopm_base_pa;
1582 dst->msrpm_base_pa = from->msrpm_base_pa;
1583 dst->tsc_offset = from->tsc_offset;
1584 dst->asid = from->asid;
1585 dst->tlb_ctl = from->tlb_ctl;
1586 dst->int_ctl = from->int_ctl;
1587 dst->int_vector = from->int_vector;
1588 dst->int_state = from->int_state;
1589 dst->exit_code = from->exit_code;
1590 dst->exit_code_hi = from->exit_code_hi;
1591 dst->exit_info_1 = from->exit_info_1;
1592 dst->exit_info_2 = from->exit_info_2;
1593 dst->exit_int_info = from->exit_int_info;
1594 dst->exit_int_info_err = from->exit_int_info_err;
1595 dst->nested_ctl = from->nested_ctl;
1596 dst->event_inj = from->event_inj;
1597 dst->event_inj_err = from->event_inj_err;
1598 dst->nested_cr3 = from->nested_cr3;
1599 dst->lbr_ctl = from->lbr_ctl;
1602 static int nested_svm_vmexit(struct vcpu_svm *svm)
1604 struct vmcb *nested_vmcb;
1605 struct vmcb *hsave = svm->nested.hsave;
1606 struct vmcb *vmcb = svm->vmcb;
1608 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1609 vmcb->control.exit_info_1,
1610 vmcb->control.exit_info_2,
1611 vmcb->control.exit_int_info,
1612 vmcb->control.exit_int_info_err);
1614 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1618 /* Give the current vmcb to the guest */
1621 nested_vmcb->save.es = vmcb->save.es;
1622 nested_vmcb->save.cs = vmcb->save.cs;
1623 nested_vmcb->save.ss = vmcb->save.ss;
1624 nested_vmcb->save.ds = vmcb->save.ds;
1625 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1626 nested_vmcb->save.idtr = vmcb->save.idtr;
1628 nested_vmcb->save.cr3 = vmcb->save.cr3;
1629 nested_vmcb->save.cr2 = vmcb->save.cr2;
1630 nested_vmcb->save.rflags = vmcb->save.rflags;
1631 nested_vmcb->save.rip = vmcb->save.rip;
1632 nested_vmcb->save.rsp = vmcb->save.rsp;
1633 nested_vmcb->save.rax = vmcb->save.rax;
1634 nested_vmcb->save.dr7 = vmcb->save.dr7;
1635 nested_vmcb->save.dr6 = vmcb->save.dr6;
1636 nested_vmcb->save.cpl = vmcb->save.cpl;
1638 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1639 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1640 nested_vmcb->control.int_state = vmcb->control.int_state;
1641 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1642 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1643 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1644 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1645 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1646 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1649 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1650 * to make sure that we do not lose injected events. So check event_inj
1651 * here and copy it to exit_int_info if it is valid.
1652 * Exit_int_info and event_inj can't be both valid because the case
1653 * below only happens on a VMRUN instruction intercept which has
1654 * no valid exit_int_info set.
1656 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1657 struct vmcb_control_area *nc = &nested_vmcb->control;
1659 nc->exit_int_info = vmcb->control.event_inj;
1660 nc->exit_int_info_err = vmcb->control.event_inj_err;
1663 nested_vmcb->control.tlb_ctl = 0;
1664 nested_vmcb->control.event_inj = 0;
1665 nested_vmcb->control.event_inj_err = 0;
1667 /* We always set V_INTR_MASKING and remember the old value in hflags */
1668 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1669 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1671 /* Restore the original control entries */
1672 copy_vmcb_control_area(vmcb, hsave);
1674 kvm_clear_exception_queue(&svm->vcpu);
1675 kvm_clear_interrupt_queue(&svm->vcpu);
1677 /* Restore selected save entries */
1678 svm->vmcb->save.es = hsave->save.es;
1679 svm->vmcb->save.cs = hsave->save.cs;
1680 svm->vmcb->save.ss = hsave->save.ss;
1681 svm->vmcb->save.ds = hsave->save.ds;
1682 svm->vmcb->save.gdtr = hsave->save.gdtr;
1683 svm->vmcb->save.idtr = hsave->save.idtr;
1684 svm->vmcb->save.rflags = hsave->save.rflags;
1685 svm_set_efer(&svm->vcpu, hsave->save.efer);
1686 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1687 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1689 svm->vmcb->save.cr3 = hsave->save.cr3;
1690 svm->vcpu.arch.cr3 = hsave->save.cr3;
1692 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1694 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1695 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1696 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1697 svm->vmcb->save.dr7 = 0;
1698 svm->vmcb->save.cpl = 0;
1699 svm->vmcb->control.exit_int_info = 0;
1701 /* Exit nested SVM mode */
1702 svm->nested.vmcb = 0;
1704 nested_svm_unmap(nested_vmcb, KM_USER0);
1706 kvm_mmu_reset_context(&svm->vcpu);
1707 kvm_mmu_load(&svm->vcpu);
1712 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1717 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1721 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1722 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1724 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1726 nested_svm_unmap(nested_msrpm, KM_USER0);
1731 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1733 struct vmcb *nested_vmcb;
1734 struct vmcb *hsave = svm->nested.hsave;
1735 struct vmcb *vmcb = svm->vmcb;
1737 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1741 /* nested_vmcb is our indicator if nested SVM is activated */
1742 svm->nested.vmcb = svm->vmcb->save.rax;
1744 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1745 nested_vmcb->save.rip,
1746 nested_vmcb->control.int_ctl,
1747 nested_vmcb->control.event_inj,
1748 nested_vmcb->control.nested_ctl);
1750 /* Clear internal status */
1751 kvm_clear_exception_queue(&svm->vcpu);
1752 kvm_clear_interrupt_queue(&svm->vcpu);
1754 /* Save the old vmcb, so we don't need to pick what we save, but
1755 can restore everything when a VMEXIT occurs */
1756 hsave->save.es = vmcb->save.es;
1757 hsave->save.cs = vmcb->save.cs;
1758 hsave->save.ss = vmcb->save.ss;
1759 hsave->save.ds = vmcb->save.ds;
1760 hsave->save.gdtr = vmcb->save.gdtr;
1761 hsave->save.idtr = vmcb->save.idtr;
1762 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1763 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
1764 hsave->save.cr4 = svm->vcpu.arch.cr4;
1765 hsave->save.rflags = vmcb->save.rflags;
1766 hsave->save.rip = svm->next_rip;
1767 hsave->save.rsp = vmcb->save.rsp;
1768 hsave->save.rax = vmcb->save.rax;
1770 hsave->save.cr3 = vmcb->save.cr3;
1772 hsave->save.cr3 = svm->vcpu.arch.cr3;
1774 copy_vmcb_control_area(hsave, vmcb);
1776 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1777 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1779 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1781 /* Load the nested guest state */
1782 svm->vmcb->save.es = nested_vmcb->save.es;
1783 svm->vmcb->save.cs = nested_vmcb->save.cs;
1784 svm->vmcb->save.ss = nested_vmcb->save.ss;
1785 svm->vmcb->save.ds = nested_vmcb->save.ds;
1786 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1787 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1788 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1789 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1790 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1791 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1793 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1794 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1796 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1797 kvm_mmu_reset_context(&svm->vcpu);
1799 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1800 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1801 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1802 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1803 /* In case we don't even reach vcpu_run, the fields are not updated */
1804 svm->vmcb->save.rax = nested_vmcb->save.rax;
1805 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1806 svm->vmcb->save.rip = nested_vmcb->save.rip;
1807 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1808 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1809 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1811 /* We don't want a nested guest to be more powerful than the guest,
1812 so all intercepts are ORed */
1813 svm->vmcb->control.intercept_cr_read |=
1814 nested_vmcb->control.intercept_cr_read;
1815 svm->vmcb->control.intercept_cr_write |=
1816 nested_vmcb->control.intercept_cr_write;
1817 svm->vmcb->control.intercept_dr_read |=
1818 nested_vmcb->control.intercept_dr_read;
1819 svm->vmcb->control.intercept_dr_write |=
1820 nested_vmcb->control.intercept_dr_write;
1821 svm->vmcb->control.intercept_exceptions |=
1822 nested_vmcb->control.intercept_exceptions;
1824 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1826 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1828 /* cache intercepts */
1829 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1830 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1831 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1832 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1833 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1834 svm->nested.intercept = nested_vmcb->control.intercept;
1836 force_new_asid(&svm->vcpu);
1837 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1838 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1839 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1841 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1843 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1844 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1845 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1846 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1847 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1849 nested_svm_unmap(nested_vmcb, KM_USER0);
1856 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1858 to_vmcb->save.fs = from_vmcb->save.fs;
1859 to_vmcb->save.gs = from_vmcb->save.gs;
1860 to_vmcb->save.tr = from_vmcb->save.tr;
1861 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1862 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1863 to_vmcb->save.star = from_vmcb->save.star;
1864 to_vmcb->save.lstar = from_vmcb->save.lstar;
1865 to_vmcb->save.cstar = from_vmcb->save.cstar;
1866 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1867 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1868 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1869 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1872 static int vmload_interception(struct vcpu_svm *svm)
1874 struct vmcb *nested_vmcb;
1876 if (nested_svm_check_permissions(svm))
1879 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1880 skip_emulated_instruction(&svm->vcpu);
1882 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1886 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1887 nested_svm_unmap(nested_vmcb, KM_USER0);
1892 static int vmsave_interception(struct vcpu_svm *svm)
1894 struct vmcb *nested_vmcb;
1896 if (nested_svm_check_permissions(svm))
1899 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1900 skip_emulated_instruction(&svm->vcpu);
1902 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1906 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1907 nested_svm_unmap(nested_vmcb, KM_USER0);
1912 static int vmrun_interception(struct vcpu_svm *svm)
1914 if (nested_svm_check_permissions(svm))
1917 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1918 skip_emulated_instruction(&svm->vcpu);
1920 if (!nested_svm_vmrun(svm))
1923 if (!nested_svm_vmrun_msrpm(svm))
1930 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1931 svm->vmcb->control.exit_code_hi = 0;
1932 svm->vmcb->control.exit_info_1 = 0;
1933 svm->vmcb->control.exit_info_2 = 0;
1935 nested_svm_vmexit(svm);
1940 static int stgi_interception(struct vcpu_svm *svm)
1942 if (nested_svm_check_permissions(svm))
1945 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1946 skip_emulated_instruction(&svm->vcpu);
1953 static int clgi_interception(struct vcpu_svm *svm)
1955 if (nested_svm_check_permissions(svm))
1958 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1959 skip_emulated_instruction(&svm->vcpu);
1963 /* After a CLGI no interrupts should come */
1964 svm_clear_vintr(svm);
1965 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1970 static int invlpga_interception(struct vcpu_svm *svm)
1972 struct kvm_vcpu *vcpu = &svm->vcpu;
1974 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1975 vcpu->arch.regs[VCPU_REGS_RAX]);
1977 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1978 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1980 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1981 skip_emulated_instruction(&svm->vcpu);
1985 static int skinit_interception(struct vcpu_svm *svm)
1987 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1989 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1993 static int invalid_op_interception(struct vcpu_svm *svm)
1995 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1999 static int task_switch_interception(struct vcpu_svm *svm)
2003 int int_type = svm->vmcb->control.exit_int_info &
2004 SVM_EXITINTINFO_TYPE_MASK;
2005 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2007 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2009 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2011 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2013 if (svm->vmcb->control.exit_info_2 &
2014 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2015 reason = TASK_SWITCH_IRET;
2016 else if (svm->vmcb->control.exit_info_2 &
2017 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2018 reason = TASK_SWITCH_JMP;
2020 reason = TASK_SWITCH_GATE;
2022 reason = TASK_SWITCH_CALL;
2024 if (reason == TASK_SWITCH_GATE) {
2026 case SVM_EXITINTINFO_TYPE_NMI:
2027 svm->vcpu.arch.nmi_injected = false;
2029 case SVM_EXITINTINFO_TYPE_EXEPT:
2030 kvm_clear_exception_queue(&svm->vcpu);
2032 case SVM_EXITINTINFO_TYPE_INTR:
2033 kvm_clear_interrupt_queue(&svm->vcpu);
2040 if (reason != TASK_SWITCH_GATE ||
2041 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2042 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2043 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2044 skip_emulated_instruction(&svm->vcpu);
2046 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2049 static int cpuid_interception(struct vcpu_svm *svm)
2051 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2052 kvm_emulate_cpuid(&svm->vcpu);
2056 static int iret_interception(struct vcpu_svm *svm)
2058 ++svm->vcpu.stat.nmi_window_exits;
2059 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2060 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2064 static int invlpg_interception(struct vcpu_svm *svm)
2066 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2067 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2071 static int emulate_on_interception(struct vcpu_svm *svm)
2073 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2074 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2078 static int cr8_write_interception(struct vcpu_svm *svm)
2080 struct kvm_run *kvm_run = svm->vcpu.run;
2082 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2083 /* instruction emulation calls kvm_set_cr8() */
2084 emulate_instruction(&svm->vcpu, 0, 0, 0);
2085 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2086 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2089 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2091 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2095 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2097 struct vcpu_svm *svm = to_svm(vcpu);
2100 case MSR_IA32_TSC: {
2104 tsc_offset = svm->nested.hsave->control.tsc_offset;
2106 tsc_offset = svm->vmcb->control.tsc_offset;
2108 *data = tsc_offset + native_read_tsc();
2112 *data = svm->vmcb->save.star;
2114 #ifdef CONFIG_X86_64
2116 *data = svm->vmcb->save.lstar;
2119 *data = svm->vmcb->save.cstar;
2121 case MSR_KERNEL_GS_BASE:
2122 *data = svm->vmcb->save.kernel_gs_base;
2124 case MSR_SYSCALL_MASK:
2125 *data = svm->vmcb->save.sfmask;
2128 case MSR_IA32_SYSENTER_CS:
2129 *data = svm->vmcb->save.sysenter_cs;
2131 case MSR_IA32_SYSENTER_EIP:
2132 *data = svm->sysenter_eip;
2134 case MSR_IA32_SYSENTER_ESP:
2135 *data = svm->sysenter_esp;
2137 /* Nobody will change the following 5 values in the VMCB so
2138 we can safely return them on rdmsr. They will always be 0
2139 until LBRV is implemented. */
2140 case MSR_IA32_DEBUGCTLMSR:
2141 *data = svm->vmcb->save.dbgctl;
2143 case MSR_IA32_LASTBRANCHFROMIP:
2144 *data = svm->vmcb->save.br_from;
2146 case MSR_IA32_LASTBRANCHTOIP:
2147 *data = svm->vmcb->save.br_to;
2149 case MSR_IA32_LASTINTFROMIP:
2150 *data = svm->vmcb->save.last_excp_from;
2152 case MSR_IA32_LASTINTTOIP:
2153 *data = svm->vmcb->save.last_excp_to;
2155 case MSR_VM_HSAVE_PA:
2156 *data = svm->nested.hsave_msr;
2161 case MSR_IA32_UCODE_REV:
2165 return kvm_get_msr_common(vcpu, ecx, data);
2170 static int rdmsr_interception(struct vcpu_svm *svm)
2172 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2175 if (svm_get_msr(&svm->vcpu, ecx, &data))
2176 kvm_inject_gp(&svm->vcpu, 0);
2178 trace_kvm_msr_read(ecx, data);
2180 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2181 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2182 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2183 skip_emulated_instruction(&svm->vcpu);
2188 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2190 struct vcpu_svm *svm = to_svm(vcpu);
2193 case MSR_IA32_TSC: {
2194 u64 tsc_offset = data - native_read_tsc();
2195 u64 g_tsc_offset = 0;
2197 if (is_nested(svm)) {
2198 g_tsc_offset = svm->vmcb->control.tsc_offset -
2199 svm->nested.hsave->control.tsc_offset;
2200 svm->nested.hsave->control.tsc_offset = tsc_offset;
2203 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2208 svm->vmcb->save.star = data;
2210 #ifdef CONFIG_X86_64
2212 svm->vmcb->save.lstar = data;
2215 svm->vmcb->save.cstar = data;
2217 case MSR_KERNEL_GS_BASE:
2218 svm->vmcb->save.kernel_gs_base = data;
2220 case MSR_SYSCALL_MASK:
2221 svm->vmcb->save.sfmask = data;
2224 case MSR_IA32_SYSENTER_CS:
2225 svm->vmcb->save.sysenter_cs = data;
2227 case MSR_IA32_SYSENTER_EIP:
2228 svm->sysenter_eip = data;
2229 svm->vmcb->save.sysenter_eip = data;
2231 case MSR_IA32_SYSENTER_ESP:
2232 svm->sysenter_esp = data;
2233 svm->vmcb->save.sysenter_esp = data;
2235 case MSR_IA32_DEBUGCTLMSR:
2236 if (!svm_has(SVM_FEATURE_LBRV)) {
2237 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2241 if (data & DEBUGCTL_RESERVED_BITS)
2244 svm->vmcb->save.dbgctl = data;
2245 if (data & (1ULL<<0))
2246 svm_enable_lbrv(svm);
2248 svm_disable_lbrv(svm);
2250 case MSR_VM_HSAVE_PA:
2251 svm->nested.hsave_msr = data;
2255 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2258 return kvm_set_msr_common(vcpu, ecx, data);
2263 static int wrmsr_interception(struct vcpu_svm *svm)
2265 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2266 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2267 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2269 trace_kvm_msr_write(ecx, data);
2271 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2272 if (svm_set_msr(&svm->vcpu, ecx, data))
2273 kvm_inject_gp(&svm->vcpu, 0);
2275 skip_emulated_instruction(&svm->vcpu);
2279 static int msr_interception(struct vcpu_svm *svm)
2281 if (svm->vmcb->control.exit_info_1)
2282 return wrmsr_interception(svm);
2284 return rdmsr_interception(svm);
2287 static int interrupt_window_interception(struct vcpu_svm *svm)
2289 struct kvm_run *kvm_run = svm->vcpu.run;
2291 svm_clear_vintr(svm);
2292 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2294 * If the user space waits to inject interrupts, exit as soon as
2297 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2298 kvm_run->request_interrupt_window &&
2299 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2300 ++svm->vcpu.stat.irq_window_exits;
2301 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2308 static int pause_interception(struct vcpu_svm *svm)
2310 kvm_vcpu_on_spin(&(svm->vcpu));
2314 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2315 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2316 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2317 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2318 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2319 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2320 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2321 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2322 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2323 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2324 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2325 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2326 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2327 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2328 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2329 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2330 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2331 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2332 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2333 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2334 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2335 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2336 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2337 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2338 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2339 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2340 [SVM_EXIT_INTR] = intr_interception,
2341 [SVM_EXIT_NMI] = nmi_interception,
2342 [SVM_EXIT_SMI] = nop_on_interception,
2343 [SVM_EXIT_INIT] = nop_on_interception,
2344 [SVM_EXIT_VINTR] = interrupt_window_interception,
2345 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2346 [SVM_EXIT_CPUID] = cpuid_interception,
2347 [SVM_EXIT_IRET] = iret_interception,
2348 [SVM_EXIT_INVD] = emulate_on_interception,
2349 [SVM_EXIT_PAUSE] = pause_interception,
2350 [SVM_EXIT_HLT] = halt_interception,
2351 [SVM_EXIT_INVLPG] = invlpg_interception,
2352 [SVM_EXIT_INVLPGA] = invlpga_interception,
2353 [SVM_EXIT_IOIO] = io_interception,
2354 [SVM_EXIT_MSR] = msr_interception,
2355 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2356 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2357 [SVM_EXIT_VMRUN] = vmrun_interception,
2358 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2359 [SVM_EXIT_VMLOAD] = vmload_interception,
2360 [SVM_EXIT_VMSAVE] = vmsave_interception,
2361 [SVM_EXIT_STGI] = stgi_interception,
2362 [SVM_EXIT_CLGI] = clgi_interception,
2363 [SVM_EXIT_SKINIT] = skinit_interception,
2364 [SVM_EXIT_WBINVD] = emulate_on_interception,
2365 [SVM_EXIT_MONITOR] = invalid_op_interception,
2366 [SVM_EXIT_MWAIT] = invalid_op_interception,
2367 [SVM_EXIT_NPF] = pf_interception,
2370 static int handle_exit(struct kvm_vcpu *vcpu)
2372 struct vcpu_svm *svm = to_svm(vcpu);
2373 struct kvm_run *kvm_run = vcpu->run;
2374 u32 exit_code = svm->vmcb->control.exit_code;
2376 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2378 if (unlikely(svm->nested.exit_required)) {
2379 nested_svm_vmexit(svm);
2380 svm->nested.exit_required = false;
2385 if (is_nested(svm)) {
2388 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2389 svm->vmcb->control.exit_info_1,
2390 svm->vmcb->control.exit_info_2,
2391 svm->vmcb->control.exit_int_info,
2392 svm->vmcb->control.exit_int_info_err);
2394 vmexit = nested_svm_exit_special(svm);
2396 if (vmexit == NESTED_EXIT_CONTINUE)
2397 vmexit = nested_svm_exit_handled(svm);
2399 if (vmexit == NESTED_EXIT_DONE)
2403 svm_complete_interrupts(svm);
2405 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2406 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2408 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2410 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2411 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2412 kvm_run->fail_entry.hardware_entry_failure_reason
2413 = svm->vmcb->control.exit_code;
2417 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2418 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2419 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2420 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2422 __func__, svm->vmcb->control.exit_int_info,
2425 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2426 || !svm_exit_handlers[exit_code]) {
2427 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2428 kvm_run->hw.hardware_exit_reason = exit_code;
2432 return svm_exit_handlers[exit_code](svm);
2435 static void reload_tss(struct kvm_vcpu *vcpu)
2437 int cpu = raw_smp_processor_id();
2439 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2440 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2444 static void pre_svm_run(struct vcpu_svm *svm)
2446 int cpu = raw_smp_processor_id();
2448 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2450 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2451 /* FIXME: handle wraparound of asid_generation */
2452 if (svm->asid_generation != sd->asid_generation)
2456 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2458 struct vcpu_svm *svm = to_svm(vcpu);
2460 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2461 vcpu->arch.hflags |= HF_NMI_MASK;
2462 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2463 ++vcpu->stat.nmi_injections;
2466 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2468 struct vmcb_control_area *control;
2470 trace_kvm_inj_virq(irq);
2472 ++svm->vcpu.stat.irq_injections;
2473 control = &svm->vmcb->control;
2474 control->int_vector = irq;
2475 control->int_ctl &= ~V_INTR_PRIO_MASK;
2476 control->int_ctl |= V_IRQ_MASK |
2477 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2480 static void svm_set_irq(struct kvm_vcpu *vcpu)
2482 struct vcpu_svm *svm = to_svm(vcpu);
2484 BUG_ON(!(gif_set(svm)));
2486 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2487 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2490 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2492 struct vcpu_svm *svm = to_svm(vcpu);
2498 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2501 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2503 struct vcpu_svm *svm = to_svm(vcpu);
2504 struct vmcb *vmcb = svm->vmcb;
2505 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2506 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2509 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2511 struct vcpu_svm *svm = to_svm(vcpu);
2513 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2516 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2518 struct vcpu_svm *svm = to_svm(vcpu);
2521 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2522 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2524 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2525 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2529 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2531 struct vcpu_svm *svm = to_svm(vcpu);
2532 struct vmcb *vmcb = svm->vmcb;
2535 if (!gif_set(svm) ||
2536 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2539 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2542 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2547 static void enable_irq_window(struct kvm_vcpu *vcpu)
2549 struct vcpu_svm *svm = to_svm(vcpu);
2551 nested_svm_intr(svm);
2553 /* In case GIF=0 we can't rely on the CPU to tell us when
2554 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2555 * The next time we get that intercept, this function will be
2556 * called again though and we'll get the vintr intercept. */
2559 svm_inject_irq(svm, 0x0);
2563 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2565 struct vcpu_svm *svm = to_svm(vcpu);
2567 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2569 return; /* IRET will cause a vm exit */
2571 /* Something prevents NMI from been injected. Single step over
2572 possible problem (IRET or exception injection or interrupt
2574 svm->nmi_singlestep = true;
2575 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2576 update_db_intercept(vcpu);
2579 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2584 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2586 force_new_asid(vcpu);
2589 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2593 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2595 struct vcpu_svm *svm = to_svm(vcpu);
2597 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2598 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2599 kvm_set_cr8(vcpu, cr8);
2603 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2605 struct vcpu_svm *svm = to_svm(vcpu);
2608 cr8 = kvm_get_cr8(vcpu);
2609 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2610 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2613 static void svm_complete_interrupts(struct vcpu_svm *svm)
2617 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2619 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2620 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2622 svm->vcpu.arch.nmi_injected = false;
2623 kvm_clear_exception_queue(&svm->vcpu);
2624 kvm_clear_interrupt_queue(&svm->vcpu);
2626 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2629 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2630 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2633 case SVM_EXITINTINFO_TYPE_NMI:
2634 svm->vcpu.arch.nmi_injected = true;
2636 case SVM_EXITINTINFO_TYPE_EXEPT:
2637 /* In case of software exception do not reinject an exception
2638 vector, but re-execute and instruction instead */
2641 if (kvm_exception_is_soft(vector))
2643 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2644 u32 err = svm->vmcb->control.exit_int_info_err;
2645 kvm_queue_exception_e(&svm->vcpu, vector, err);
2648 kvm_queue_exception(&svm->vcpu, vector);
2650 case SVM_EXITINTINFO_TYPE_INTR:
2651 kvm_queue_interrupt(&svm->vcpu, vector, false);
2658 #ifdef CONFIG_X86_64
2664 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2666 struct vcpu_svm *svm = to_svm(vcpu);
2672 * A vmexit emulation is required before the vcpu can be executed
2675 if (unlikely(svm->nested.exit_required))
2678 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2679 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2680 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2684 sync_lapic_to_cr8(vcpu);
2686 save_host_msrs(vcpu);
2687 fs_selector = kvm_read_fs();
2688 gs_selector = kvm_read_gs();
2689 ldt_selector = kvm_read_ldt();
2690 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2691 /* required for live migration with NPT */
2693 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2700 "push %%"R"bp; \n\t"
2701 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2702 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2703 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2704 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2705 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2706 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2707 #ifdef CONFIG_X86_64
2708 "mov %c[r8](%[svm]), %%r8 \n\t"
2709 "mov %c[r9](%[svm]), %%r9 \n\t"
2710 "mov %c[r10](%[svm]), %%r10 \n\t"
2711 "mov %c[r11](%[svm]), %%r11 \n\t"
2712 "mov %c[r12](%[svm]), %%r12 \n\t"
2713 "mov %c[r13](%[svm]), %%r13 \n\t"
2714 "mov %c[r14](%[svm]), %%r14 \n\t"
2715 "mov %c[r15](%[svm]), %%r15 \n\t"
2718 /* Enter guest mode */
2720 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2721 __ex(SVM_VMLOAD) "\n\t"
2722 __ex(SVM_VMRUN) "\n\t"
2723 __ex(SVM_VMSAVE) "\n\t"
2726 /* Save guest registers, load host registers */
2727 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2728 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2729 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2730 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2731 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2732 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2733 #ifdef CONFIG_X86_64
2734 "mov %%r8, %c[r8](%[svm]) \n\t"
2735 "mov %%r9, %c[r9](%[svm]) \n\t"
2736 "mov %%r10, %c[r10](%[svm]) \n\t"
2737 "mov %%r11, %c[r11](%[svm]) \n\t"
2738 "mov %%r12, %c[r12](%[svm]) \n\t"
2739 "mov %%r13, %c[r13](%[svm]) \n\t"
2740 "mov %%r14, %c[r14](%[svm]) \n\t"
2741 "mov %%r15, %c[r15](%[svm]) \n\t"
2746 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2747 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2748 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2749 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2750 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2751 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2752 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2753 #ifdef CONFIG_X86_64
2754 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2755 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2756 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2757 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2758 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2759 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2760 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2761 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2764 , R"bx", R"cx", R"dx", R"si", R"di"
2765 #ifdef CONFIG_X86_64
2766 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2770 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2771 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2772 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2773 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2775 kvm_load_fs(fs_selector);
2776 kvm_load_gs(gs_selector);
2777 kvm_load_ldt(ldt_selector);
2778 load_host_msrs(vcpu);
2782 local_irq_disable();
2786 sync_cr8_to_lapic(vcpu);
2791 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2792 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2798 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2800 struct vcpu_svm *svm = to_svm(vcpu);
2803 svm->vmcb->control.nested_cr3 = root;
2804 force_new_asid(vcpu);
2808 svm->vmcb->save.cr3 = root;
2809 force_new_asid(vcpu);
2812 static int is_disabled(void)
2816 rdmsrl(MSR_VM_CR, vm_cr);
2817 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2824 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2827 * Patch in the VMMCALL instruction:
2829 hypercall[0] = 0x0f;
2830 hypercall[1] = 0x01;
2831 hypercall[2] = 0xd9;
2834 static void svm_check_processor_compat(void *rtn)
2839 static bool svm_cpu_has_accelerated_tpr(void)
2844 static int get_npt_level(void)
2846 #ifdef CONFIG_X86_64
2847 return PT64_ROOT_LEVEL;
2849 return PT32E_ROOT_LEVEL;
2853 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2858 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2862 static const struct trace_print_flags svm_exit_reasons_str[] = {
2863 { SVM_EXIT_READ_CR0, "read_cr0" },
2864 { SVM_EXIT_READ_CR3, "read_cr3" },
2865 { SVM_EXIT_READ_CR4, "read_cr4" },
2866 { SVM_EXIT_READ_CR8, "read_cr8" },
2867 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2868 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2869 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2870 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2871 { SVM_EXIT_READ_DR0, "read_dr0" },
2872 { SVM_EXIT_READ_DR1, "read_dr1" },
2873 { SVM_EXIT_READ_DR2, "read_dr2" },
2874 { SVM_EXIT_READ_DR3, "read_dr3" },
2875 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2876 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2877 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2878 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2879 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2880 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2881 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2882 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2883 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2884 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2885 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2886 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2887 { SVM_EXIT_INTR, "interrupt" },
2888 { SVM_EXIT_NMI, "nmi" },
2889 { SVM_EXIT_SMI, "smi" },
2890 { SVM_EXIT_INIT, "init" },
2891 { SVM_EXIT_VINTR, "vintr" },
2892 { SVM_EXIT_CPUID, "cpuid" },
2893 { SVM_EXIT_INVD, "invd" },
2894 { SVM_EXIT_HLT, "hlt" },
2895 { SVM_EXIT_INVLPG, "invlpg" },
2896 { SVM_EXIT_INVLPGA, "invlpga" },
2897 { SVM_EXIT_IOIO, "io" },
2898 { SVM_EXIT_MSR, "msr" },
2899 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2900 { SVM_EXIT_SHUTDOWN, "shutdown" },
2901 { SVM_EXIT_VMRUN, "vmrun" },
2902 { SVM_EXIT_VMMCALL, "hypercall" },
2903 { SVM_EXIT_VMLOAD, "vmload" },
2904 { SVM_EXIT_VMSAVE, "vmsave" },
2905 { SVM_EXIT_STGI, "stgi" },
2906 { SVM_EXIT_CLGI, "clgi" },
2907 { SVM_EXIT_SKINIT, "skinit" },
2908 { SVM_EXIT_WBINVD, "wbinvd" },
2909 { SVM_EXIT_MONITOR, "monitor" },
2910 { SVM_EXIT_MWAIT, "mwait" },
2911 { SVM_EXIT_NPF, "npf" },
2915 static int svm_get_lpage_level(void)
2917 return PT_PDPE_LEVEL;
2920 static bool svm_rdtscp_supported(void)
2925 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2927 struct vcpu_svm *svm = to_svm(vcpu);
2929 update_cr0_intercept(svm);
2930 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
2933 static struct kvm_x86_ops svm_x86_ops = {
2934 .cpu_has_kvm_support = has_svm,
2935 .disabled_by_bios = is_disabled,
2936 .hardware_setup = svm_hardware_setup,
2937 .hardware_unsetup = svm_hardware_unsetup,
2938 .check_processor_compatibility = svm_check_processor_compat,
2939 .hardware_enable = svm_hardware_enable,
2940 .hardware_disable = svm_hardware_disable,
2941 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2943 .vcpu_create = svm_create_vcpu,
2944 .vcpu_free = svm_free_vcpu,
2945 .vcpu_reset = svm_vcpu_reset,
2947 .prepare_guest_switch = svm_prepare_guest_switch,
2948 .vcpu_load = svm_vcpu_load,
2949 .vcpu_put = svm_vcpu_put,
2951 .set_guest_debug = svm_guest_debug,
2952 .get_msr = svm_get_msr,
2953 .set_msr = svm_set_msr,
2954 .get_segment_base = svm_get_segment_base,
2955 .get_segment = svm_get_segment,
2956 .set_segment = svm_set_segment,
2957 .get_cpl = svm_get_cpl,
2958 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2959 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
2960 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2961 .set_cr0 = svm_set_cr0,
2962 .set_cr3 = svm_set_cr3,
2963 .set_cr4 = svm_set_cr4,
2964 .set_efer = svm_set_efer,
2965 .get_idt = svm_get_idt,
2966 .set_idt = svm_set_idt,
2967 .get_gdt = svm_get_gdt,
2968 .set_gdt = svm_set_gdt,
2969 .get_dr = svm_get_dr,
2970 .set_dr = svm_set_dr,
2971 .cache_reg = svm_cache_reg,
2972 .get_rflags = svm_get_rflags,
2973 .set_rflags = svm_set_rflags,
2974 .fpu_deactivate = svm_fpu_deactivate,
2976 .tlb_flush = svm_flush_tlb,
2978 .run = svm_vcpu_run,
2979 .handle_exit = handle_exit,
2980 .skip_emulated_instruction = skip_emulated_instruction,
2981 .set_interrupt_shadow = svm_set_interrupt_shadow,
2982 .get_interrupt_shadow = svm_get_interrupt_shadow,
2983 .patch_hypercall = svm_patch_hypercall,
2984 .set_irq = svm_set_irq,
2985 .set_nmi = svm_inject_nmi,
2986 .queue_exception = svm_queue_exception,
2987 .interrupt_allowed = svm_interrupt_allowed,
2988 .nmi_allowed = svm_nmi_allowed,
2989 .get_nmi_mask = svm_get_nmi_mask,
2990 .set_nmi_mask = svm_set_nmi_mask,
2991 .enable_nmi_window = enable_nmi_window,
2992 .enable_irq_window = enable_irq_window,
2993 .update_cr8_intercept = update_cr8_intercept,
2995 .set_tss_addr = svm_set_tss_addr,
2996 .get_tdp_level = get_npt_level,
2997 .get_mt_mask = svm_get_mt_mask,
2999 .exit_reasons_str = svm_exit_reasons_str,
3000 .get_lpage_level = svm_get_lpage_level,
3002 .cpuid_update = svm_cpuid_update,
3004 .rdtscp_supported = svm_rdtscp_supported,
3007 static int __init svm_init(void)
3009 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3013 static void __exit svm_exit(void)
3018 module_init(svm_init)
3019 module_exit(svm_exit)