2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
35 #include <asm/perf_event.h>
36 #include <asm/tlbflush.h>
38 #include <asm/debugreg.h>
39 #include <asm/kvm_para.h>
41 #include <asm/virtext.h>
44 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 MODULE_AUTHOR("Qumranet");
47 MODULE_LICENSE("GPL");
49 static const struct x86_cpu_id svm_cpu_id[] = {
50 X86_FEATURE_MATCH(X86_FEATURE_SVM),
53 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
55 #define IOPM_ALLOC_ORDER 2
56 #define MSRPM_ALLOC_ORDER 1
58 #define SEG_TYPE_LDT 2
59 #define SEG_TYPE_BUSY_TSS16 3
61 #define SVM_FEATURE_NPT (1 << 0)
62 #define SVM_FEATURE_LBRV (1 << 1)
63 #define SVM_FEATURE_SVML (1 << 2)
64 #define SVM_FEATURE_NRIP (1 << 3)
65 #define SVM_FEATURE_TSC_RATE (1 << 4)
66 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
67 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
68 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
69 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
71 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
72 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
73 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
75 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
77 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
78 #define TSC_RATIO_MIN 0x0000000000000001ULL
79 #define TSC_RATIO_MAX 0x000000ffffffffffULL
81 static bool erratum_383_found __read_mostly;
83 static const u32 host_save_user_msrs[] = {
85 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
88 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
91 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
101 /* These are the merged vectors */
104 /* gpa pointers to the real vectors */
108 /* A VMEXIT is required but not yet emulated */
111 /* cache for intercepts of the guest */
114 u32 intercept_exceptions;
117 /* Nested Paging related state */
121 #define MSRPM_OFFSETS 16
122 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
125 * Set osvw_len to higher value when updated Revision Guides
126 * are published and we know what the new status bits are
128 static uint64_t osvw_len = 4, osvw_status;
131 struct kvm_vcpu vcpu;
133 unsigned long vmcb_pa;
134 struct svm_cpu_data *svm_data;
135 uint64_t asid_generation;
136 uint64_t sysenter_esp;
137 uint64_t sysenter_eip;
141 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
153 struct nested_state nested;
157 unsigned int3_injected;
158 unsigned long int3_rip;
164 static DEFINE_PER_CPU(u64, current_tsc_ratio);
165 #define TSC_RATIO_DEFAULT 0x0100000000ULL
167 #define MSR_INVALID 0xffffffffU
169 static const struct svm_direct_access_msrs {
170 u32 index; /* Index of the MSR */
171 bool always; /* True if intercept is always on */
172 } direct_access_msrs[] = {
173 { .index = MSR_STAR, .always = true },
174 { .index = MSR_IA32_SYSENTER_CS, .always = true },
176 { .index = MSR_GS_BASE, .always = true },
177 { .index = MSR_FS_BASE, .always = true },
178 { .index = MSR_KERNEL_GS_BASE, .always = true },
179 { .index = MSR_LSTAR, .always = true },
180 { .index = MSR_CSTAR, .always = true },
181 { .index = MSR_SYSCALL_MASK, .always = true },
183 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
184 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
185 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
186 { .index = MSR_IA32_LASTINTTOIP, .always = false },
187 { .index = MSR_INVALID, .always = false },
190 /* enable NPT for AMD64 and X86 with PAE */
191 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
192 static bool npt_enabled = true;
194 static bool npt_enabled;
197 /* allow nested paging (virtualized MMU) for all guests */
198 static int npt = true;
199 module_param(npt, int, S_IRUGO);
201 /* allow nested virtualization in KVM/SVM */
202 static int nested = true;
203 module_param(nested, int, S_IRUGO);
205 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
206 static void svm_complete_interrupts(struct vcpu_svm *svm);
208 static int nested_svm_exit_handled(struct vcpu_svm *svm);
209 static int nested_svm_intercept(struct vcpu_svm *svm);
210 static int nested_svm_vmexit(struct vcpu_svm *svm);
211 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
212 bool has_error_code, u32 error_code);
213 static u64 __scale_tsc(u64 ratio, u64 tsc);
216 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
217 pause filter count */
218 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
219 VMCB_ASID, /* ASID */
220 VMCB_INTR, /* int_ctl, int_vector */
221 VMCB_NPT, /* npt_en, nCR3, gPAT */
222 VMCB_CR, /* CR0, CR3, CR4, EFER */
223 VMCB_DR, /* DR6, DR7 */
224 VMCB_DT, /* GDT, IDT */
225 VMCB_SEG, /* CS, DS, SS, ES, CPL */
226 VMCB_CR2, /* CR2 only */
227 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
231 /* TPR and CR2 are always written before VMRUN */
232 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
234 static inline void mark_all_dirty(struct vmcb *vmcb)
236 vmcb->control.clean = 0;
239 static inline void mark_all_clean(struct vmcb *vmcb)
241 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
242 & ~VMCB_ALWAYS_DIRTY_MASK;
245 static inline void mark_dirty(struct vmcb *vmcb, int bit)
247 vmcb->control.clean &= ~(1 << bit);
250 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
252 return container_of(vcpu, struct vcpu_svm, vcpu);
255 static void recalc_intercepts(struct vcpu_svm *svm)
257 struct vmcb_control_area *c, *h;
258 struct nested_state *g;
260 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
262 if (!is_guest_mode(&svm->vcpu))
265 c = &svm->vmcb->control;
266 h = &svm->nested.hsave->control;
269 c->intercept_cr = h->intercept_cr | g->intercept_cr;
270 c->intercept_dr = h->intercept_dr | g->intercept_dr;
271 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
272 c->intercept = h->intercept | g->intercept;
275 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
277 if (is_guest_mode(&svm->vcpu))
278 return svm->nested.hsave;
283 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
285 struct vmcb *vmcb = get_host_vmcb(svm);
287 vmcb->control.intercept_cr |= (1U << bit);
289 recalc_intercepts(svm);
292 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
294 struct vmcb *vmcb = get_host_vmcb(svm);
296 vmcb->control.intercept_cr &= ~(1U << bit);
298 recalc_intercepts(svm);
301 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
303 struct vmcb *vmcb = get_host_vmcb(svm);
305 return vmcb->control.intercept_cr & (1U << bit);
308 static inline void set_dr_intercepts(struct vcpu_svm *svm)
310 struct vmcb *vmcb = get_host_vmcb(svm);
312 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
313 | (1 << INTERCEPT_DR1_READ)
314 | (1 << INTERCEPT_DR2_READ)
315 | (1 << INTERCEPT_DR3_READ)
316 | (1 << INTERCEPT_DR4_READ)
317 | (1 << INTERCEPT_DR5_READ)
318 | (1 << INTERCEPT_DR6_READ)
319 | (1 << INTERCEPT_DR7_READ)
320 | (1 << INTERCEPT_DR0_WRITE)
321 | (1 << INTERCEPT_DR1_WRITE)
322 | (1 << INTERCEPT_DR2_WRITE)
323 | (1 << INTERCEPT_DR3_WRITE)
324 | (1 << INTERCEPT_DR4_WRITE)
325 | (1 << INTERCEPT_DR5_WRITE)
326 | (1 << INTERCEPT_DR6_WRITE)
327 | (1 << INTERCEPT_DR7_WRITE);
329 recalc_intercepts(svm);
332 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
334 struct vmcb *vmcb = get_host_vmcb(svm);
336 vmcb->control.intercept_dr = 0;
338 recalc_intercepts(svm);
341 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
343 struct vmcb *vmcb = get_host_vmcb(svm);
345 vmcb->control.intercept_exceptions |= (1U << bit);
347 recalc_intercepts(svm);
350 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
352 struct vmcb *vmcb = get_host_vmcb(svm);
354 vmcb->control.intercept_exceptions &= ~(1U << bit);
356 recalc_intercepts(svm);
359 static inline void set_intercept(struct vcpu_svm *svm, int bit)
361 struct vmcb *vmcb = get_host_vmcb(svm);
363 vmcb->control.intercept |= (1ULL << bit);
365 recalc_intercepts(svm);
368 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
370 struct vmcb *vmcb = get_host_vmcb(svm);
372 vmcb->control.intercept &= ~(1ULL << bit);
374 recalc_intercepts(svm);
377 static inline void enable_gif(struct vcpu_svm *svm)
379 svm->vcpu.arch.hflags |= HF_GIF_MASK;
382 static inline void disable_gif(struct vcpu_svm *svm)
384 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
387 static inline bool gif_set(struct vcpu_svm *svm)
389 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
392 static unsigned long iopm_base;
394 struct kvm_ldttss_desc {
397 unsigned base1:8, type:5, dpl:2, p:1;
398 unsigned limit1:4, zero0:3, g:1, base2:8;
401 } __attribute__((packed));
403 struct svm_cpu_data {
409 struct kvm_ldttss_desc *tss_desc;
411 struct page *save_area;
414 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
416 struct svm_init_data {
421 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
423 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
424 #define MSRS_RANGE_SIZE 2048
425 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
427 static u32 svm_msrpm_offset(u32 msr)
432 for (i = 0; i < NUM_MSR_MAPS; i++) {
433 if (msr < msrpm_ranges[i] ||
434 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
437 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
438 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
440 /* Now we have the u8 offset - but need the u32 offset */
444 /* MSR not in any range */
448 #define MAX_INST_SIZE 15
450 static inline void clgi(void)
452 asm volatile (__ex(SVM_CLGI));
455 static inline void stgi(void)
457 asm volatile (__ex(SVM_STGI));
460 static inline void invlpga(unsigned long addr, u32 asid)
462 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
465 static int get_npt_level(void)
468 return PT64_ROOT_LEVEL;
470 return PT32E_ROOT_LEVEL;
474 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
476 vcpu->arch.efer = efer;
477 if (!npt_enabled && !(efer & EFER_LMA))
480 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
481 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
484 static int is_external_interrupt(u32 info)
486 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
487 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
490 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
492 struct vcpu_svm *svm = to_svm(vcpu);
495 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
496 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
500 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
502 struct vcpu_svm *svm = to_svm(vcpu);
505 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
507 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
511 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
513 struct vcpu_svm *svm = to_svm(vcpu);
515 if (svm->vmcb->control.next_rip != 0) {
516 WARN_ON(!static_cpu_has(X86_FEATURE_NRIPS));
517 svm->next_rip = svm->vmcb->control.next_rip;
520 if (!svm->next_rip) {
521 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
523 printk(KERN_DEBUG "%s: NOP\n", __func__);
526 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
527 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
528 __func__, kvm_rip_read(vcpu), svm->next_rip);
530 kvm_rip_write(vcpu, svm->next_rip);
531 svm_set_interrupt_shadow(vcpu, 0);
534 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
535 bool has_error_code, u32 error_code,
538 struct vcpu_svm *svm = to_svm(vcpu);
541 * If we are within a nested VM we'd better #VMEXIT and let the guest
542 * handle the exception
545 nested_svm_check_exception(svm, nr, has_error_code, error_code))
548 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
549 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
552 * For guest debugging where we have to reinject #BP if some
553 * INT3 is guest-owned:
554 * Emulate nRIP by moving RIP forward. Will fail if injection
555 * raises a fault that is not intercepted. Still better than
556 * failing in all cases.
558 skip_emulated_instruction(&svm->vcpu);
559 rip = kvm_rip_read(&svm->vcpu);
560 svm->int3_rip = rip + svm->vmcb->save.cs.base;
561 svm->int3_injected = rip - old_rip;
564 svm->vmcb->control.event_inj = nr
566 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
567 | SVM_EVTINJ_TYPE_EXEPT;
568 svm->vmcb->control.event_inj_err = error_code;
571 static void svm_init_erratum_383(void)
577 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
580 /* Use _safe variants to not break nested virtualization */
581 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
587 low = lower_32_bits(val);
588 high = upper_32_bits(val);
590 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
592 erratum_383_found = true;
595 static void svm_init_osvw(struct kvm_vcpu *vcpu)
598 * Guests should see errata 400 and 415 as fixed (assuming that
599 * HLT and IO instructions are intercepted).
601 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
602 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
605 * By increasing VCPU's osvw.length to 3 we are telling the guest that
606 * all osvw.status bits inside that length, including bit 0 (which is
607 * reserved for erratum 298), are valid. However, if host processor's
608 * osvw_len is 0 then osvw_status[0] carries no information. We need to
609 * be conservative here and therefore we tell the guest that erratum 298
610 * is present (because we really don't know).
612 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
613 vcpu->arch.osvw.status |= 1;
616 static int has_svm(void)
620 if (!cpu_has_svm(&msg)) {
621 printk(KERN_INFO "has_svm: %s\n", msg);
628 static void svm_hardware_disable(void)
630 /* Make sure we clean up behind us */
631 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
632 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
636 amd_pmu_disable_virt();
639 static int svm_hardware_enable(void)
642 struct svm_cpu_data *sd;
644 struct desc_ptr gdt_descr;
645 struct desc_struct *gdt;
646 int me = raw_smp_processor_id();
648 rdmsrl(MSR_EFER, efer);
649 if (efer & EFER_SVME)
653 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
656 sd = per_cpu(svm_data, me);
658 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
662 sd->asid_generation = 1;
663 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
664 sd->next_asid = sd->max_asid + 1;
666 native_store_gdt(&gdt_descr);
667 gdt = (struct desc_struct *)gdt_descr.address;
668 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
670 wrmsrl(MSR_EFER, efer | EFER_SVME);
672 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
674 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
675 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
676 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
683 * Note that it is possible to have a system with mixed processor
684 * revisions and therefore different OSVW bits. If bits are not the same
685 * on different processors then choose the worst case (i.e. if erratum
686 * is present on one processor and not on another then assume that the
687 * erratum is present everywhere).
689 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
690 uint64_t len, status = 0;
693 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
695 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
699 osvw_status = osvw_len = 0;
703 osvw_status |= status;
704 osvw_status &= (1ULL << osvw_len) - 1;
707 osvw_status = osvw_len = 0;
709 svm_init_erratum_383();
711 amd_pmu_enable_virt();
716 static void svm_cpu_uninit(int cpu)
718 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
723 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
724 __free_page(sd->save_area);
728 static int svm_cpu_init(int cpu)
730 struct svm_cpu_data *sd;
733 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
737 sd->save_area = alloc_page(GFP_KERNEL);
742 per_cpu(svm_data, cpu) = sd;
752 static bool valid_msr_intercept(u32 index)
756 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
757 if (direct_access_msrs[i].index == index)
763 static void set_msr_interception(u32 *msrpm, unsigned msr,
766 u8 bit_read, bit_write;
771 * If this warning triggers extend the direct_access_msrs list at the
772 * beginning of the file
774 WARN_ON(!valid_msr_intercept(msr));
776 offset = svm_msrpm_offset(msr);
777 bit_read = 2 * (msr & 0x0f);
778 bit_write = 2 * (msr & 0x0f) + 1;
781 BUG_ON(offset == MSR_INVALID);
783 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
784 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
789 static void svm_vcpu_init_msrpm(u32 *msrpm)
793 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
795 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
796 if (!direct_access_msrs[i].always)
799 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
803 static void add_msr_offset(u32 offset)
807 for (i = 0; i < MSRPM_OFFSETS; ++i) {
809 /* Offset already in list? */
810 if (msrpm_offsets[i] == offset)
813 /* Slot used by another offset? */
814 if (msrpm_offsets[i] != MSR_INVALID)
817 /* Add offset to list */
818 msrpm_offsets[i] = offset;
824 * If this BUG triggers the msrpm_offsets table has an overflow. Just
825 * increase MSRPM_OFFSETS in this case.
830 static void init_msrpm_offsets(void)
834 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
836 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
839 offset = svm_msrpm_offset(direct_access_msrs[i].index);
840 BUG_ON(offset == MSR_INVALID);
842 add_msr_offset(offset);
846 static void svm_enable_lbrv(struct vcpu_svm *svm)
848 u32 *msrpm = svm->msrpm;
850 svm->vmcb->control.lbr_ctl = 1;
851 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
852 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
853 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
854 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
857 static void svm_disable_lbrv(struct vcpu_svm *svm)
859 u32 *msrpm = svm->msrpm;
861 svm->vmcb->control.lbr_ctl = 0;
862 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
863 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
864 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
865 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
868 static __init int svm_hardware_setup(void)
871 struct page *iopm_pages;
875 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
880 iopm_va = page_address(iopm_pages);
881 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
882 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
884 init_msrpm_offsets();
886 if (boot_cpu_has(X86_FEATURE_NX))
887 kvm_enable_efer_bits(EFER_NX);
889 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
890 kvm_enable_efer_bits(EFER_FFXSR);
892 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
895 kvm_has_tsc_control = true;
898 * Make sure the user can only configure tsc_khz values that
899 * fit into a signed integer.
900 * A min value is not calculated needed because it will always
901 * be 1 on all machines and a value of 0 is used to disable
902 * tsc-scaling for the vcpu.
904 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
906 kvm_max_guest_tsc_khz = max;
910 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
911 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
914 for_each_possible_cpu(cpu) {
915 r = svm_cpu_init(cpu);
920 if (!boot_cpu_has(X86_FEATURE_NPT))
923 if (npt_enabled && !npt) {
924 printk(KERN_INFO "kvm: Nested Paging disabled\n");
929 printk(KERN_INFO "kvm: Nested Paging enabled\n");
937 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
942 static __exit void svm_hardware_unsetup(void)
946 for_each_possible_cpu(cpu)
949 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
953 static void init_seg(struct vmcb_seg *seg)
956 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
957 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
962 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
965 seg->attrib = SVM_SELECTOR_P_MASK | type;
970 static u64 __scale_tsc(u64 ratio, u64 tsc)
972 u64 mult, frac, _tsc;
975 frac = ratio & ((1ULL << 32) - 1);
979 _tsc += (tsc >> 32) * frac;
980 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
985 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
987 struct vcpu_svm *svm = to_svm(vcpu);
990 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
991 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
996 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
998 struct vcpu_svm *svm = to_svm(vcpu);
1002 /* Guest TSC same frequency as host TSC? */
1004 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1008 /* TSC scaling supported? */
1009 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1010 if (user_tsc_khz > tsc_khz) {
1011 vcpu->arch.tsc_catchup = 1;
1012 vcpu->arch.tsc_always_catchup = 1;
1014 WARN(1, "user requested TSC rate below hardware speed\n");
1020 /* TSC scaling required - calculate ratio */
1022 do_div(ratio, tsc_khz);
1024 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1025 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1029 svm->tsc_ratio = ratio;
1032 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1034 struct vcpu_svm *svm = to_svm(vcpu);
1036 return svm->vmcb->control.tsc_offset;
1039 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1041 struct vcpu_svm *svm = to_svm(vcpu);
1042 u64 g_tsc_offset = 0;
1044 if (is_guest_mode(vcpu)) {
1045 g_tsc_offset = svm->vmcb->control.tsc_offset -
1046 svm->nested.hsave->control.tsc_offset;
1047 svm->nested.hsave->control.tsc_offset = offset;
1049 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1050 svm->vmcb->control.tsc_offset,
1053 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1055 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1058 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1060 struct vcpu_svm *svm = to_svm(vcpu);
1063 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1064 WARN_ON(adjustment < 0);
1065 adjustment = svm_scale_tsc(vcpu, (u64)adjustment);
1068 svm->vmcb->control.tsc_offset += adjustment;
1069 if (is_guest_mode(vcpu))
1070 svm->nested.hsave->control.tsc_offset += adjustment;
1072 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1073 svm->vmcb->control.tsc_offset - adjustment,
1074 svm->vmcb->control.tsc_offset);
1076 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1079 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1083 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1085 return target_tsc - tsc;
1088 static void init_vmcb(struct vcpu_svm *svm, bool init_event)
1090 struct vmcb_control_area *control = &svm->vmcb->control;
1091 struct vmcb_save_area *save = &svm->vmcb->save;
1093 svm->vcpu.fpu_active = 1;
1094 svm->vcpu.arch.hflags = 0;
1096 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1097 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1098 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1099 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1100 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1101 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1102 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1104 set_dr_intercepts(svm);
1106 set_exception_intercept(svm, PF_VECTOR);
1107 set_exception_intercept(svm, UD_VECTOR);
1108 set_exception_intercept(svm, MC_VECTOR);
1110 set_intercept(svm, INTERCEPT_INTR);
1111 set_intercept(svm, INTERCEPT_NMI);
1112 set_intercept(svm, INTERCEPT_SMI);
1113 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1114 set_intercept(svm, INTERCEPT_RDPMC);
1115 set_intercept(svm, INTERCEPT_CPUID);
1116 set_intercept(svm, INTERCEPT_INVD);
1117 set_intercept(svm, INTERCEPT_HLT);
1118 set_intercept(svm, INTERCEPT_INVLPG);
1119 set_intercept(svm, INTERCEPT_INVLPGA);
1120 set_intercept(svm, INTERCEPT_IOIO_PROT);
1121 set_intercept(svm, INTERCEPT_MSR_PROT);
1122 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1123 set_intercept(svm, INTERCEPT_SHUTDOWN);
1124 set_intercept(svm, INTERCEPT_VMRUN);
1125 set_intercept(svm, INTERCEPT_VMMCALL);
1126 set_intercept(svm, INTERCEPT_VMLOAD);
1127 set_intercept(svm, INTERCEPT_VMSAVE);
1128 set_intercept(svm, INTERCEPT_STGI);
1129 set_intercept(svm, INTERCEPT_CLGI);
1130 set_intercept(svm, INTERCEPT_SKINIT);
1131 set_intercept(svm, INTERCEPT_WBINVD);
1132 set_intercept(svm, INTERCEPT_MONITOR);
1133 set_intercept(svm, INTERCEPT_MWAIT);
1134 set_intercept(svm, INTERCEPT_XSETBV);
1136 control->iopm_base_pa = iopm_base;
1137 control->msrpm_base_pa = __pa(svm->msrpm);
1138 control->int_ctl = V_INTR_MASKING_MASK;
1140 init_seg(&save->es);
1141 init_seg(&save->ss);
1142 init_seg(&save->ds);
1143 init_seg(&save->fs);
1144 init_seg(&save->gs);
1146 save->cs.selector = 0xf000;
1147 save->cs.base = 0xffff0000;
1148 /* Executable/Readable Code Segment */
1149 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1150 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1151 save->cs.limit = 0xffff;
1153 save->gdtr.limit = 0xffff;
1154 save->idtr.limit = 0xffff;
1156 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1157 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1160 svm_set_efer(&svm->vcpu, 0);
1161 save->dr6 = 0xffff0ff0;
1162 kvm_set_rflags(&svm->vcpu, 2);
1163 save->rip = 0x0000fff0;
1164 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1167 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1168 * It also updates the guest-visible cr0 value.
1170 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1172 save->cr4 = X86_CR4_PAE;
1176 /* Setup VMCB for Nested Paging */
1177 control->nested_ctl = 1;
1178 clr_intercept(svm, INTERCEPT_INVLPG);
1179 clr_exception_intercept(svm, PF_VECTOR);
1180 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1181 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1182 save->g_pat = svm->vcpu.arch.pat;
1186 svm->asid_generation = 0;
1188 svm->nested.vmcb = 0;
1189 svm->vcpu.arch.hflags = 0;
1191 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1192 control->pause_filter_count = 3000;
1193 set_intercept(svm, INTERCEPT_PAUSE);
1196 mark_all_dirty(svm->vmcb);
1201 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1203 struct vcpu_svm *svm = to_svm(vcpu);
1208 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1209 MSR_IA32_APICBASE_ENABLE;
1210 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1211 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1213 init_vmcb(svm, init_event);
1215 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1216 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1219 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1221 struct vcpu_svm *svm;
1223 struct page *msrpm_pages;
1224 struct page *hsave_page;
1225 struct page *nested_msrpm_pages;
1228 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1234 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1236 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1241 page = alloc_page(GFP_KERNEL);
1245 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1249 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1250 if (!nested_msrpm_pages)
1253 hsave_page = alloc_page(GFP_KERNEL);
1257 svm->nested.hsave = page_address(hsave_page);
1259 svm->msrpm = page_address(msrpm_pages);
1260 svm_vcpu_init_msrpm(svm->msrpm);
1262 svm->nested.msrpm = page_address(nested_msrpm_pages);
1263 svm_vcpu_init_msrpm(svm->nested.msrpm);
1265 svm->vmcb = page_address(page);
1266 clear_page(svm->vmcb);
1267 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1268 svm->asid_generation = 0;
1269 init_vmcb(svm, false);
1271 svm_init_osvw(&svm->vcpu);
1276 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1278 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1282 kvm_vcpu_uninit(&svm->vcpu);
1284 kmem_cache_free(kvm_vcpu_cache, svm);
1286 return ERR_PTR(err);
1289 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1291 struct vcpu_svm *svm = to_svm(vcpu);
1293 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1294 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1295 __free_page(virt_to_page(svm->nested.hsave));
1296 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1297 kvm_vcpu_uninit(vcpu);
1298 kmem_cache_free(kvm_vcpu_cache, svm);
1301 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1303 struct vcpu_svm *svm = to_svm(vcpu);
1306 if (unlikely(cpu != vcpu->cpu)) {
1307 svm->asid_generation = 0;
1308 mark_all_dirty(svm->vmcb);
1311 #ifdef CONFIG_X86_64
1312 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1314 savesegment(fs, svm->host.fs);
1315 savesegment(gs, svm->host.gs);
1316 svm->host.ldt = kvm_read_ldt();
1318 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1319 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1321 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1322 svm->tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1323 __this_cpu_write(current_tsc_ratio, svm->tsc_ratio);
1324 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1328 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1330 struct vcpu_svm *svm = to_svm(vcpu);
1333 ++vcpu->stat.host_state_reload;
1334 kvm_load_ldt(svm->host.ldt);
1335 #ifdef CONFIG_X86_64
1336 loadsegment(fs, svm->host.fs);
1337 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1338 load_gs_index(svm->host.gs);
1340 #ifdef CONFIG_X86_32_LAZY_GS
1341 loadsegment(gs, svm->host.gs);
1344 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1345 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1348 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1350 return to_svm(vcpu)->vmcb->save.rflags;
1353 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1356 * Any change of EFLAGS.VM is accompained by a reload of SS
1357 * (caused by either a task switch or an inter-privilege IRET),
1358 * so we do not need to update the CPL here.
1360 to_svm(vcpu)->vmcb->save.rflags = rflags;
1363 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1366 case VCPU_EXREG_PDPTR:
1367 BUG_ON(!npt_enabled);
1368 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1375 static void svm_set_vintr(struct vcpu_svm *svm)
1377 set_intercept(svm, INTERCEPT_VINTR);
1380 static void svm_clear_vintr(struct vcpu_svm *svm)
1382 clr_intercept(svm, INTERCEPT_VINTR);
1385 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1387 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1390 case VCPU_SREG_CS: return &save->cs;
1391 case VCPU_SREG_DS: return &save->ds;
1392 case VCPU_SREG_ES: return &save->es;
1393 case VCPU_SREG_FS: return &save->fs;
1394 case VCPU_SREG_GS: return &save->gs;
1395 case VCPU_SREG_SS: return &save->ss;
1396 case VCPU_SREG_TR: return &save->tr;
1397 case VCPU_SREG_LDTR: return &save->ldtr;
1403 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1405 struct vmcb_seg *s = svm_seg(vcpu, seg);
1410 static void svm_get_segment(struct kvm_vcpu *vcpu,
1411 struct kvm_segment *var, int seg)
1413 struct vmcb_seg *s = svm_seg(vcpu, seg);
1415 var->base = s->base;
1416 var->limit = s->limit;
1417 var->selector = s->selector;
1418 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1419 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1420 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1421 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1422 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1423 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1424 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1427 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1428 * However, the SVM spec states that the G bit is not observed by the
1429 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1430 * So let's synthesize a legal G bit for all segments, this helps
1431 * running KVM nested. It also helps cross-vendor migration, because
1432 * Intel's vmentry has a check on the 'G' bit.
1434 var->g = s->limit > 0xfffff;
1437 * AMD's VMCB does not have an explicit unusable field, so emulate it
1438 * for cross vendor migration purposes by "not present"
1440 var->unusable = !var->present || (var->type == 0);
1445 * Work around a bug where the busy flag in the tr selector
1455 * The accessed bit must always be set in the segment
1456 * descriptor cache, although it can be cleared in the
1457 * descriptor, the cached bit always remains at 1. Since
1458 * Intel has a check on this, set it here to support
1459 * cross-vendor migration.
1466 * On AMD CPUs sometimes the DB bit in the segment
1467 * descriptor is left as 1, although the whole segment has
1468 * been made unusable. Clear it here to pass an Intel VMX
1469 * entry check when cross vendor migrating.
1473 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1478 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1480 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1485 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1487 struct vcpu_svm *svm = to_svm(vcpu);
1489 dt->size = svm->vmcb->save.idtr.limit;
1490 dt->address = svm->vmcb->save.idtr.base;
1493 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1495 struct vcpu_svm *svm = to_svm(vcpu);
1497 svm->vmcb->save.idtr.limit = dt->size;
1498 svm->vmcb->save.idtr.base = dt->address ;
1499 mark_dirty(svm->vmcb, VMCB_DT);
1502 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1504 struct vcpu_svm *svm = to_svm(vcpu);
1506 dt->size = svm->vmcb->save.gdtr.limit;
1507 dt->address = svm->vmcb->save.gdtr.base;
1510 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1512 struct vcpu_svm *svm = to_svm(vcpu);
1514 svm->vmcb->save.gdtr.limit = dt->size;
1515 svm->vmcb->save.gdtr.base = dt->address ;
1516 mark_dirty(svm->vmcb, VMCB_DT);
1519 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1523 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1527 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1531 static void update_cr0_intercept(struct vcpu_svm *svm)
1533 ulong gcr0 = svm->vcpu.arch.cr0;
1534 u64 *hcr0 = &svm->vmcb->save.cr0;
1536 if (!svm->vcpu.fpu_active)
1537 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1539 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1540 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1542 mark_dirty(svm->vmcb, VMCB_CR);
1544 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1545 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1546 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1548 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1549 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1553 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1555 struct vcpu_svm *svm = to_svm(vcpu);
1557 #ifdef CONFIG_X86_64
1558 if (vcpu->arch.efer & EFER_LME) {
1559 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1560 vcpu->arch.efer |= EFER_LMA;
1561 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1564 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1565 vcpu->arch.efer &= ~EFER_LMA;
1566 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1570 vcpu->arch.cr0 = cr0;
1573 cr0 |= X86_CR0_PG | X86_CR0_WP;
1575 if (!vcpu->fpu_active)
1578 * re-enable caching here because the QEMU bios
1579 * does not do it - this results in some delay at
1582 if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_CD_NW_CLEARED))
1583 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1584 svm->vmcb->save.cr0 = cr0;
1585 mark_dirty(svm->vmcb, VMCB_CR);
1586 update_cr0_intercept(svm);
1589 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1591 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1592 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1594 if (cr4 & X86_CR4_VMXE)
1597 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1598 svm_flush_tlb(vcpu);
1600 vcpu->arch.cr4 = cr4;
1603 cr4 |= host_cr4_mce;
1604 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1605 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1609 static void svm_set_segment(struct kvm_vcpu *vcpu,
1610 struct kvm_segment *var, int seg)
1612 struct vcpu_svm *svm = to_svm(vcpu);
1613 struct vmcb_seg *s = svm_seg(vcpu, seg);
1615 s->base = var->base;
1616 s->limit = var->limit;
1617 s->selector = var->selector;
1621 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1622 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1623 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1624 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1625 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1626 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1627 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1628 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1632 * This is always accurate, except if SYSRET returned to a segment
1633 * with SS.DPL != 3. Intel does not have this quirk, and always
1634 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1635 * would entail passing the CPL to userspace and back.
1637 if (seg == VCPU_SREG_SS)
1638 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1640 mark_dirty(svm->vmcb, VMCB_SEG);
1643 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1645 struct vcpu_svm *svm = to_svm(vcpu);
1647 clr_exception_intercept(svm, DB_VECTOR);
1648 clr_exception_intercept(svm, BP_VECTOR);
1650 if (svm->nmi_singlestep)
1651 set_exception_intercept(svm, DB_VECTOR);
1653 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1654 if (vcpu->guest_debug &
1655 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1656 set_exception_intercept(svm, DB_VECTOR);
1657 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1658 set_exception_intercept(svm, BP_VECTOR);
1660 vcpu->guest_debug = 0;
1663 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1665 if (sd->next_asid > sd->max_asid) {
1666 ++sd->asid_generation;
1668 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1671 svm->asid_generation = sd->asid_generation;
1672 svm->vmcb->control.asid = sd->next_asid++;
1674 mark_dirty(svm->vmcb, VMCB_ASID);
1677 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1679 return to_svm(vcpu)->vmcb->save.dr6;
1682 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1684 struct vcpu_svm *svm = to_svm(vcpu);
1686 svm->vmcb->save.dr6 = value;
1687 mark_dirty(svm->vmcb, VMCB_DR);
1690 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1692 struct vcpu_svm *svm = to_svm(vcpu);
1694 get_debugreg(vcpu->arch.db[0], 0);
1695 get_debugreg(vcpu->arch.db[1], 1);
1696 get_debugreg(vcpu->arch.db[2], 2);
1697 get_debugreg(vcpu->arch.db[3], 3);
1698 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1699 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1701 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1702 set_dr_intercepts(svm);
1705 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1707 struct vcpu_svm *svm = to_svm(vcpu);
1709 svm->vmcb->save.dr7 = value;
1710 mark_dirty(svm->vmcb, VMCB_DR);
1713 static int pf_interception(struct vcpu_svm *svm)
1715 u64 fault_address = svm->vmcb->control.exit_info_2;
1719 switch (svm->apf_reason) {
1721 error_code = svm->vmcb->control.exit_info_1;
1723 trace_kvm_page_fault(fault_address, error_code);
1724 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1725 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1726 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1727 svm->vmcb->control.insn_bytes,
1728 svm->vmcb->control.insn_len);
1730 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1731 svm->apf_reason = 0;
1732 local_irq_disable();
1733 kvm_async_pf_task_wait(fault_address);
1736 case KVM_PV_REASON_PAGE_READY:
1737 svm->apf_reason = 0;
1738 local_irq_disable();
1739 kvm_async_pf_task_wake(fault_address);
1746 static int db_interception(struct vcpu_svm *svm)
1748 struct kvm_run *kvm_run = svm->vcpu.run;
1750 if (!(svm->vcpu.guest_debug &
1751 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1752 !svm->nmi_singlestep) {
1753 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1757 if (svm->nmi_singlestep) {
1758 svm->nmi_singlestep = false;
1759 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1760 svm->vmcb->save.rflags &=
1761 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1762 update_db_bp_intercept(&svm->vcpu);
1765 if (svm->vcpu.guest_debug &
1766 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1767 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1768 kvm_run->debug.arch.pc =
1769 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1770 kvm_run->debug.arch.exception = DB_VECTOR;
1777 static int bp_interception(struct vcpu_svm *svm)
1779 struct kvm_run *kvm_run = svm->vcpu.run;
1781 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1782 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1783 kvm_run->debug.arch.exception = BP_VECTOR;
1787 static int ud_interception(struct vcpu_svm *svm)
1791 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1792 if (er != EMULATE_DONE)
1793 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1797 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1799 struct vcpu_svm *svm = to_svm(vcpu);
1801 clr_exception_intercept(svm, NM_VECTOR);
1803 svm->vcpu.fpu_active = 1;
1804 update_cr0_intercept(svm);
1807 static int nm_interception(struct vcpu_svm *svm)
1809 svm_fpu_activate(&svm->vcpu);
1813 static bool is_erratum_383(void)
1818 if (!erratum_383_found)
1821 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1825 /* Bit 62 may or may not be set for this mce */
1826 value &= ~(1ULL << 62);
1828 if (value != 0xb600000000010015ULL)
1831 /* Clear MCi_STATUS registers */
1832 for (i = 0; i < 6; ++i)
1833 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1835 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1839 value &= ~(1ULL << 2);
1840 low = lower_32_bits(value);
1841 high = upper_32_bits(value);
1843 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1846 /* Flush tlb to evict multi-match entries */
1852 static void svm_handle_mce(struct vcpu_svm *svm)
1854 if (is_erratum_383()) {
1856 * Erratum 383 triggered. Guest state is corrupt so kill the
1859 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1861 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1867 * On an #MC intercept the MCE handler is not called automatically in
1868 * the host. So do it by hand here.
1872 /* not sure if we ever come back to this point */
1877 static int mc_interception(struct vcpu_svm *svm)
1882 static int shutdown_interception(struct vcpu_svm *svm)
1884 struct kvm_run *kvm_run = svm->vcpu.run;
1887 * VMCB is undefined after a SHUTDOWN intercept
1888 * so reinitialize it.
1890 clear_page(svm->vmcb);
1891 init_vmcb(svm, false);
1893 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1897 static int io_interception(struct vcpu_svm *svm)
1899 struct kvm_vcpu *vcpu = &svm->vcpu;
1900 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1901 int size, in, string;
1904 ++svm->vcpu.stat.io_exits;
1905 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1906 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1908 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1910 port = io_info >> 16;
1911 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1912 svm->next_rip = svm->vmcb->control.exit_info_2;
1913 skip_emulated_instruction(&svm->vcpu);
1915 return kvm_fast_pio_out(vcpu, size, port);
1918 static int nmi_interception(struct vcpu_svm *svm)
1923 static int intr_interception(struct vcpu_svm *svm)
1925 ++svm->vcpu.stat.irq_exits;
1929 static int nop_on_interception(struct vcpu_svm *svm)
1934 static int halt_interception(struct vcpu_svm *svm)
1936 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1937 return kvm_emulate_halt(&svm->vcpu);
1940 static int vmmcall_interception(struct vcpu_svm *svm)
1942 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1943 kvm_emulate_hypercall(&svm->vcpu);
1947 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1949 struct vcpu_svm *svm = to_svm(vcpu);
1951 return svm->nested.nested_cr3;
1954 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1956 struct vcpu_svm *svm = to_svm(vcpu);
1957 u64 cr3 = svm->nested.nested_cr3;
1961 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
1962 offset_in_page(cr3) + index * 8, 8);
1968 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1971 struct vcpu_svm *svm = to_svm(vcpu);
1973 svm->vmcb->control.nested_cr3 = root;
1974 mark_dirty(svm->vmcb, VMCB_NPT);
1975 svm_flush_tlb(vcpu);
1978 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1979 struct x86_exception *fault)
1981 struct vcpu_svm *svm = to_svm(vcpu);
1983 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
1985 * TODO: track the cause of the nested page fault, and
1986 * correctly fill in the high bits of exit_info_1.
1988 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1989 svm->vmcb->control.exit_code_hi = 0;
1990 svm->vmcb->control.exit_info_1 = (1ULL << 32);
1991 svm->vmcb->control.exit_info_2 = fault->address;
1994 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
1995 svm->vmcb->control.exit_info_1 |= fault->error_code;
1998 * The present bit is always zero for page structure faults on real
2001 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2002 svm->vmcb->control.exit_info_1 &= ~1;
2004 nested_svm_vmexit(svm);
2007 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2009 WARN_ON(mmu_is_nested(vcpu));
2010 kvm_init_shadow_mmu(vcpu);
2011 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2012 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2013 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2014 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2015 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2016 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2019 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2021 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2024 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2026 if (!(svm->vcpu.arch.efer & EFER_SVME)
2027 || !is_paging(&svm->vcpu)) {
2028 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2032 if (svm->vmcb->save.cpl) {
2033 kvm_inject_gp(&svm->vcpu, 0);
2040 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2041 bool has_error_code, u32 error_code)
2045 if (!is_guest_mode(&svm->vcpu))
2048 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2049 svm->vmcb->control.exit_code_hi = 0;
2050 svm->vmcb->control.exit_info_1 = error_code;
2051 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2053 vmexit = nested_svm_intercept(svm);
2054 if (vmexit == NESTED_EXIT_DONE)
2055 svm->nested.exit_required = true;
2060 /* This function returns true if it is save to enable the irq window */
2061 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2063 if (!is_guest_mode(&svm->vcpu))
2066 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2069 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2073 * if vmexit was already requested (by intercepted exception
2074 * for instance) do not overwrite it with "external interrupt"
2077 if (svm->nested.exit_required)
2080 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2081 svm->vmcb->control.exit_info_1 = 0;
2082 svm->vmcb->control.exit_info_2 = 0;
2084 if (svm->nested.intercept & 1ULL) {
2086 * The #vmexit can't be emulated here directly because this
2087 * code path runs with irqs and preemption disabled. A
2088 * #vmexit emulation might sleep. Only signal request for
2091 svm->nested.exit_required = true;
2092 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2099 /* This function returns true if it is save to enable the nmi window */
2100 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2102 if (!is_guest_mode(&svm->vcpu))
2105 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2108 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2109 svm->nested.exit_required = true;
2114 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2120 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2121 if (is_error_page(page))
2129 kvm_inject_gp(&svm->vcpu, 0);
2134 static void nested_svm_unmap(struct page *page)
2137 kvm_release_page_dirty(page);
2140 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2142 unsigned port, size, iopm_len;
2147 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2148 return NESTED_EXIT_HOST;
2150 port = svm->vmcb->control.exit_info_1 >> 16;
2151 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2152 SVM_IOIO_SIZE_SHIFT;
2153 gpa = svm->nested.vmcb_iopm + (port / 8);
2154 start_bit = port % 8;
2155 iopm_len = (start_bit + size > 8) ? 2 : 1;
2156 mask = (0xf >> (4 - size)) << start_bit;
2159 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2160 return NESTED_EXIT_DONE;
2162 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2165 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2167 u32 offset, msr, value;
2170 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2171 return NESTED_EXIT_HOST;
2173 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2174 offset = svm_msrpm_offset(msr);
2175 write = svm->vmcb->control.exit_info_1 & 1;
2176 mask = 1 << ((2 * (msr & 0xf)) + write);
2178 if (offset == MSR_INVALID)
2179 return NESTED_EXIT_DONE;
2181 /* Offset is in 32 bit units but need in 8 bit units */
2184 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2185 return NESTED_EXIT_DONE;
2187 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2190 static int nested_svm_exit_special(struct vcpu_svm *svm)
2192 u32 exit_code = svm->vmcb->control.exit_code;
2194 switch (exit_code) {
2197 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2198 return NESTED_EXIT_HOST;
2200 /* For now we are always handling NPFs when using them */
2202 return NESTED_EXIT_HOST;
2204 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2205 /* When we're shadowing, trap PFs, but not async PF */
2206 if (!npt_enabled && svm->apf_reason == 0)
2207 return NESTED_EXIT_HOST;
2209 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2210 nm_interception(svm);
2216 return NESTED_EXIT_CONTINUE;
2220 * If this function returns true, this #vmexit was already handled
2222 static int nested_svm_intercept(struct vcpu_svm *svm)
2224 u32 exit_code = svm->vmcb->control.exit_code;
2225 int vmexit = NESTED_EXIT_HOST;
2227 switch (exit_code) {
2229 vmexit = nested_svm_exit_handled_msr(svm);
2232 vmexit = nested_svm_intercept_ioio(svm);
2234 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2235 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2236 if (svm->nested.intercept_cr & bit)
2237 vmexit = NESTED_EXIT_DONE;
2240 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2241 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2242 if (svm->nested.intercept_dr & bit)
2243 vmexit = NESTED_EXIT_DONE;
2246 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2247 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2248 if (svm->nested.intercept_exceptions & excp_bits)
2249 vmexit = NESTED_EXIT_DONE;
2250 /* async page fault always cause vmexit */
2251 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2252 svm->apf_reason != 0)
2253 vmexit = NESTED_EXIT_DONE;
2256 case SVM_EXIT_ERR: {
2257 vmexit = NESTED_EXIT_DONE;
2261 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2262 if (svm->nested.intercept & exit_bits)
2263 vmexit = NESTED_EXIT_DONE;
2270 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2274 vmexit = nested_svm_intercept(svm);
2276 if (vmexit == NESTED_EXIT_DONE)
2277 nested_svm_vmexit(svm);
2282 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2284 struct vmcb_control_area *dst = &dst_vmcb->control;
2285 struct vmcb_control_area *from = &from_vmcb->control;
2287 dst->intercept_cr = from->intercept_cr;
2288 dst->intercept_dr = from->intercept_dr;
2289 dst->intercept_exceptions = from->intercept_exceptions;
2290 dst->intercept = from->intercept;
2291 dst->iopm_base_pa = from->iopm_base_pa;
2292 dst->msrpm_base_pa = from->msrpm_base_pa;
2293 dst->tsc_offset = from->tsc_offset;
2294 dst->asid = from->asid;
2295 dst->tlb_ctl = from->tlb_ctl;
2296 dst->int_ctl = from->int_ctl;
2297 dst->int_vector = from->int_vector;
2298 dst->int_state = from->int_state;
2299 dst->exit_code = from->exit_code;
2300 dst->exit_code_hi = from->exit_code_hi;
2301 dst->exit_info_1 = from->exit_info_1;
2302 dst->exit_info_2 = from->exit_info_2;
2303 dst->exit_int_info = from->exit_int_info;
2304 dst->exit_int_info_err = from->exit_int_info_err;
2305 dst->nested_ctl = from->nested_ctl;
2306 dst->event_inj = from->event_inj;
2307 dst->event_inj_err = from->event_inj_err;
2308 dst->nested_cr3 = from->nested_cr3;
2309 dst->lbr_ctl = from->lbr_ctl;
2312 static int nested_svm_vmexit(struct vcpu_svm *svm)
2314 struct vmcb *nested_vmcb;
2315 struct vmcb *hsave = svm->nested.hsave;
2316 struct vmcb *vmcb = svm->vmcb;
2319 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2320 vmcb->control.exit_info_1,
2321 vmcb->control.exit_info_2,
2322 vmcb->control.exit_int_info,
2323 vmcb->control.exit_int_info_err,
2326 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2330 /* Exit Guest-Mode */
2331 leave_guest_mode(&svm->vcpu);
2332 svm->nested.vmcb = 0;
2334 /* Give the current vmcb to the guest */
2337 nested_vmcb->save.es = vmcb->save.es;
2338 nested_vmcb->save.cs = vmcb->save.cs;
2339 nested_vmcb->save.ss = vmcb->save.ss;
2340 nested_vmcb->save.ds = vmcb->save.ds;
2341 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2342 nested_vmcb->save.idtr = vmcb->save.idtr;
2343 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2344 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2345 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2346 nested_vmcb->save.cr2 = vmcb->save.cr2;
2347 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2348 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2349 nested_vmcb->save.rip = vmcb->save.rip;
2350 nested_vmcb->save.rsp = vmcb->save.rsp;
2351 nested_vmcb->save.rax = vmcb->save.rax;
2352 nested_vmcb->save.dr7 = vmcb->save.dr7;
2353 nested_vmcb->save.dr6 = vmcb->save.dr6;
2354 nested_vmcb->save.cpl = vmcb->save.cpl;
2356 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2357 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2358 nested_vmcb->control.int_state = vmcb->control.int_state;
2359 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2360 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2361 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2362 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2363 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2364 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2365 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2368 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2369 * to make sure that we do not lose injected events. So check event_inj
2370 * here and copy it to exit_int_info if it is valid.
2371 * Exit_int_info and event_inj can't be both valid because the case
2372 * below only happens on a VMRUN instruction intercept which has
2373 * no valid exit_int_info set.
2375 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2376 struct vmcb_control_area *nc = &nested_vmcb->control;
2378 nc->exit_int_info = vmcb->control.event_inj;
2379 nc->exit_int_info_err = vmcb->control.event_inj_err;
2382 nested_vmcb->control.tlb_ctl = 0;
2383 nested_vmcb->control.event_inj = 0;
2384 nested_vmcb->control.event_inj_err = 0;
2386 /* We always set V_INTR_MASKING and remember the old value in hflags */
2387 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2388 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2390 /* Restore the original control entries */
2391 copy_vmcb_control_area(vmcb, hsave);
2393 kvm_clear_exception_queue(&svm->vcpu);
2394 kvm_clear_interrupt_queue(&svm->vcpu);
2396 svm->nested.nested_cr3 = 0;
2398 /* Restore selected save entries */
2399 svm->vmcb->save.es = hsave->save.es;
2400 svm->vmcb->save.cs = hsave->save.cs;
2401 svm->vmcb->save.ss = hsave->save.ss;
2402 svm->vmcb->save.ds = hsave->save.ds;
2403 svm->vmcb->save.gdtr = hsave->save.gdtr;
2404 svm->vmcb->save.idtr = hsave->save.idtr;
2405 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2406 svm_set_efer(&svm->vcpu, hsave->save.efer);
2407 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2408 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2410 svm->vmcb->save.cr3 = hsave->save.cr3;
2411 svm->vcpu.arch.cr3 = hsave->save.cr3;
2413 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2415 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2416 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2417 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2418 svm->vmcb->save.dr7 = 0;
2419 svm->vmcb->save.cpl = 0;
2420 svm->vmcb->control.exit_int_info = 0;
2422 mark_all_dirty(svm->vmcb);
2424 nested_svm_unmap(page);
2426 nested_svm_uninit_mmu_context(&svm->vcpu);
2427 kvm_mmu_reset_context(&svm->vcpu);
2428 kvm_mmu_load(&svm->vcpu);
2433 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2436 * This function merges the msr permission bitmaps of kvm and the
2437 * nested vmcb. It is optimized in that it only merges the parts where
2438 * the kvm msr permission bitmap may contain zero bits
2442 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2445 for (i = 0; i < MSRPM_OFFSETS; i++) {
2449 if (msrpm_offsets[i] == 0xffffffff)
2452 p = msrpm_offsets[i];
2453 offset = svm->nested.vmcb_msrpm + (p * 4);
2455 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2458 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2461 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2466 static bool nested_vmcb_checks(struct vmcb *vmcb)
2468 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2471 if (vmcb->control.asid == 0)
2474 if (vmcb->control.nested_ctl && !npt_enabled)
2480 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2482 struct vmcb *nested_vmcb;
2483 struct vmcb *hsave = svm->nested.hsave;
2484 struct vmcb *vmcb = svm->vmcb;
2488 vmcb_gpa = svm->vmcb->save.rax;
2490 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2494 if (!nested_vmcb_checks(nested_vmcb)) {
2495 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2496 nested_vmcb->control.exit_code_hi = 0;
2497 nested_vmcb->control.exit_info_1 = 0;
2498 nested_vmcb->control.exit_info_2 = 0;
2500 nested_svm_unmap(page);
2505 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2506 nested_vmcb->save.rip,
2507 nested_vmcb->control.int_ctl,
2508 nested_vmcb->control.event_inj,
2509 nested_vmcb->control.nested_ctl);
2511 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2512 nested_vmcb->control.intercept_cr >> 16,
2513 nested_vmcb->control.intercept_exceptions,
2514 nested_vmcb->control.intercept);
2516 /* Clear internal status */
2517 kvm_clear_exception_queue(&svm->vcpu);
2518 kvm_clear_interrupt_queue(&svm->vcpu);
2521 * Save the old vmcb, so we don't need to pick what we save, but can
2522 * restore everything when a VMEXIT occurs
2524 hsave->save.es = vmcb->save.es;
2525 hsave->save.cs = vmcb->save.cs;
2526 hsave->save.ss = vmcb->save.ss;
2527 hsave->save.ds = vmcb->save.ds;
2528 hsave->save.gdtr = vmcb->save.gdtr;
2529 hsave->save.idtr = vmcb->save.idtr;
2530 hsave->save.efer = svm->vcpu.arch.efer;
2531 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2532 hsave->save.cr4 = svm->vcpu.arch.cr4;
2533 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2534 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2535 hsave->save.rsp = vmcb->save.rsp;
2536 hsave->save.rax = vmcb->save.rax;
2538 hsave->save.cr3 = vmcb->save.cr3;
2540 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2542 copy_vmcb_control_area(hsave, vmcb);
2544 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2545 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2547 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2549 if (nested_vmcb->control.nested_ctl) {
2550 kvm_mmu_unload(&svm->vcpu);
2551 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2552 nested_svm_init_mmu_context(&svm->vcpu);
2555 /* Load the nested guest state */
2556 svm->vmcb->save.es = nested_vmcb->save.es;
2557 svm->vmcb->save.cs = nested_vmcb->save.cs;
2558 svm->vmcb->save.ss = nested_vmcb->save.ss;
2559 svm->vmcb->save.ds = nested_vmcb->save.ds;
2560 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2561 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2562 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2563 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2564 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2565 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2567 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2568 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2570 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2572 /* Guest paging mode is active - reset mmu */
2573 kvm_mmu_reset_context(&svm->vcpu);
2575 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2576 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2577 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2578 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2580 /* In case we don't even reach vcpu_run, the fields are not updated */
2581 svm->vmcb->save.rax = nested_vmcb->save.rax;
2582 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2583 svm->vmcb->save.rip = nested_vmcb->save.rip;
2584 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2585 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2586 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2588 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2589 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2591 /* cache intercepts */
2592 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2593 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2594 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2595 svm->nested.intercept = nested_vmcb->control.intercept;
2597 svm_flush_tlb(&svm->vcpu);
2598 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2599 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2600 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2602 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2604 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2605 /* We only want the cr8 intercept bits of the guest */
2606 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2607 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2610 /* We don't want to see VMMCALLs from a nested guest */
2611 clr_intercept(svm, INTERCEPT_VMMCALL);
2613 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2614 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2615 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2616 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2617 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2618 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2620 nested_svm_unmap(page);
2622 /* Enter Guest-Mode */
2623 enter_guest_mode(&svm->vcpu);
2626 * Merge guest and host intercepts - must be called with vcpu in
2627 * guest-mode to take affect here
2629 recalc_intercepts(svm);
2631 svm->nested.vmcb = vmcb_gpa;
2635 mark_all_dirty(svm->vmcb);
2640 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2642 to_vmcb->save.fs = from_vmcb->save.fs;
2643 to_vmcb->save.gs = from_vmcb->save.gs;
2644 to_vmcb->save.tr = from_vmcb->save.tr;
2645 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2646 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2647 to_vmcb->save.star = from_vmcb->save.star;
2648 to_vmcb->save.lstar = from_vmcb->save.lstar;
2649 to_vmcb->save.cstar = from_vmcb->save.cstar;
2650 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2651 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2652 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2653 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2656 static int vmload_interception(struct vcpu_svm *svm)
2658 struct vmcb *nested_vmcb;
2661 if (nested_svm_check_permissions(svm))
2664 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2668 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2669 skip_emulated_instruction(&svm->vcpu);
2671 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2672 nested_svm_unmap(page);
2677 static int vmsave_interception(struct vcpu_svm *svm)
2679 struct vmcb *nested_vmcb;
2682 if (nested_svm_check_permissions(svm))
2685 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2689 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2690 skip_emulated_instruction(&svm->vcpu);
2692 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2693 nested_svm_unmap(page);
2698 static int vmrun_interception(struct vcpu_svm *svm)
2700 if (nested_svm_check_permissions(svm))
2703 /* Save rip after vmrun instruction */
2704 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2706 if (!nested_svm_vmrun(svm))
2709 if (!nested_svm_vmrun_msrpm(svm))
2716 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2717 svm->vmcb->control.exit_code_hi = 0;
2718 svm->vmcb->control.exit_info_1 = 0;
2719 svm->vmcb->control.exit_info_2 = 0;
2721 nested_svm_vmexit(svm);
2726 static int stgi_interception(struct vcpu_svm *svm)
2728 if (nested_svm_check_permissions(svm))
2731 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2732 skip_emulated_instruction(&svm->vcpu);
2733 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2740 static int clgi_interception(struct vcpu_svm *svm)
2742 if (nested_svm_check_permissions(svm))
2745 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2746 skip_emulated_instruction(&svm->vcpu);
2750 /* After a CLGI no interrupts should come */
2751 svm_clear_vintr(svm);
2752 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2754 mark_dirty(svm->vmcb, VMCB_INTR);
2759 static int invlpga_interception(struct vcpu_svm *svm)
2761 struct kvm_vcpu *vcpu = &svm->vcpu;
2763 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2764 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2766 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2767 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2769 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2770 skip_emulated_instruction(&svm->vcpu);
2774 static int skinit_interception(struct vcpu_svm *svm)
2776 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2778 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2782 static int wbinvd_interception(struct vcpu_svm *svm)
2784 kvm_emulate_wbinvd(&svm->vcpu);
2788 static int xsetbv_interception(struct vcpu_svm *svm)
2790 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2791 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2793 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2794 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2795 skip_emulated_instruction(&svm->vcpu);
2801 static int task_switch_interception(struct vcpu_svm *svm)
2805 int int_type = svm->vmcb->control.exit_int_info &
2806 SVM_EXITINTINFO_TYPE_MASK;
2807 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2809 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2811 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2812 bool has_error_code = false;
2815 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2817 if (svm->vmcb->control.exit_info_2 &
2818 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2819 reason = TASK_SWITCH_IRET;
2820 else if (svm->vmcb->control.exit_info_2 &
2821 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2822 reason = TASK_SWITCH_JMP;
2824 reason = TASK_SWITCH_GATE;
2826 reason = TASK_SWITCH_CALL;
2828 if (reason == TASK_SWITCH_GATE) {
2830 case SVM_EXITINTINFO_TYPE_NMI:
2831 svm->vcpu.arch.nmi_injected = false;
2833 case SVM_EXITINTINFO_TYPE_EXEPT:
2834 if (svm->vmcb->control.exit_info_2 &
2835 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2836 has_error_code = true;
2838 (u32)svm->vmcb->control.exit_info_2;
2840 kvm_clear_exception_queue(&svm->vcpu);
2842 case SVM_EXITINTINFO_TYPE_INTR:
2843 kvm_clear_interrupt_queue(&svm->vcpu);
2850 if (reason != TASK_SWITCH_GATE ||
2851 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2852 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2853 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2854 skip_emulated_instruction(&svm->vcpu);
2856 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2859 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2860 has_error_code, error_code) == EMULATE_FAIL) {
2861 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2862 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2863 svm->vcpu.run->internal.ndata = 0;
2869 static int cpuid_interception(struct vcpu_svm *svm)
2871 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2872 kvm_emulate_cpuid(&svm->vcpu);
2876 static int iret_interception(struct vcpu_svm *svm)
2878 ++svm->vcpu.stat.nmi_window_exits;
2879 clr_intercept(svm, INTERCEPT_IRET);
2880 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2881 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2882 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2886 static int invlpg_interception(struct vcpu_svm *svm)
2888 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2889 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2891 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2892 skip_emulated_instruction(&svm->vcpu);
2896 static int emulate_on_interception(struct vcpu_svm *svm)
2898 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2901 static int rdpmc_interception(struct vcpu_svm *svm)
2905 if (!static_cpu_has(X86_FEATURE_NRIPS))
2906 return emulate_on_interception(svm);
2908 err = kvm_rdpmc(&svm->vcpu);
2909 kvm_complete_insn_gp(&svm->vcpu, err);
2914 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2917 unsigned long cr0 = svm->vcpu.arch.cr0;
2921 intercept = svm->nested.intercept;
2923 if (!is_guest_mode(&svm->vcpu) ||
2924 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2927 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2928 val &= ~SVM_CR0_SELECTIVE_MASK;
2931 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2932 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2938 #define CR_VALID (1ULL << 63)
2940 static int cr_interception(struct vcpu_svm *svm)
2946 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2947 return emulate_on_interception(svm);
2949 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2950 return emulate_on_interception(svm);
2952 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2953 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2954 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2956 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2959 if (cr >= 16) { /* mov to cr */
2961 val = kvm_register_read(&svm->vcpu, reg);
2964 if (!check_selective_cr0_intercepted(svm, val))
2965 err = kvm_set_cr0(&svm->vcpu, val);
2971 err = kvm_set_cr3(&svm->vcpu, val);
2974 err = kvm_set_cr4(&svm->vcpu, val);
2977 err = kvm_set_cr8(&svm->vcpu, val);
2980 WARN(1, "unhandled write to CR%d", cr);
2981 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2984 } else { /* mov from cr */
2987 val = kvm_read_cr0(&svm->vcpu);
2990 val = svm->vcpu.arch.cr2;
2993 val = kvm_read_cr3(&svm->vcpu);
2996 val = kvm_read_cr4(&svm->vcpu);
2999 val = kvm_get_cr8(&svm->vcpu);
3002 WARN(1, "unhandled read from CR%d", cr);
3003 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3006 kvm_register_write(&svm->vcpu, reg, val);
3008 kvm_complete_insn_gp(&svm->vcpu, err);
3013 static int dr_interception(struct vcpu_svm *svm)
3018 if (svm->vcpu.guest_debug == 0) {
3020 * No more DR vmexits; force a reload of the debug registers
3021 * and reenter on this instruction. The next vmexit will
3022 * retrieve the full state of the debug registers.
3024 clr_dr_intercepts(svm);
3025 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3029 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3030 return emulate_on_interception(svm);
3032 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3033 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3035 if (dr >= 16) { /* mov to DRn */
3036 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3038 val = kvm_register_read(&svm->vcpu, reg);
3039 kvm_set_dr(&svm->vcpu, dr - 16, val);
3041 if (!kvm_require_dr(&svm->vcpu, dr))
3043 kvm_get_dr(&svm->vcpu, dr, &val);
3044 kvm_register_write(&svm->vcpu, reg, val);
3047 skip_emulated_instruction(&svm->vcpu);
3052 static int cr8_write_interception(struct vcpu_svm *svm)
3054 struct kvm_run *kvm_run = svm->vcpu.run;
3057 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3058 /* instruction emulation calls kvm_set_cr8() */
3059 r = cr_interception(svm);
3060 if (irqchip_in_kernel(svm->vcpu.kvm))
3062 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3064 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3068 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3070 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3071 return vmcb->control.tsc_offset +
3072 svm_scale_tsc(vcpu, host_tsc);
3075 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3077 struct vcpu_svm *svm = to_svm(vcpu);
3079 switch (msr_info->index) {
3080 case MSR_IA32_TSC: {
3081 msr_info->data = svm->vmcb->control.tsc_offset +
3082 svm_scale_tsc(vcpu, native_read_tsc());
3087 msr_info->data = svm->vmcb->save.star;
3089 #ifdef CONFIG_X86_64
3091 msr_info->data = svm->vmcb->save.lstar;
3094 msr_info->data = svm->vmcb->save.cstar;
3096 case MSR_KERNEL_GS_BASE:
3097 msr_info->data = svm->vmcb->save.kernel_gs_base;
3099 case MSR_SYSCALL_MASK:
3100 msr_info->data = svm->vmcb->save.sfmask;
3103 case MSR_IA32_SYSENTER_CS:
3104 msr_info->data = svm->vmcb->save.sysenter_cs;
3106 case MSR_IA32_SYSENTER_EIP:
3107 msr_info->data = svm->sysenter_eip;
3109 case MSR_IA32_SYSENTER_ESP:
3110 msr_info->data = svm->sysenter_esp;
3113 * Nobody will change the following 5 values in the VMCB so we can
3114 * safely return them on rdmsr. They will always be 0 until LBRV is
3117 case MSR_IA32_DEBUGCTLMSR:
3118 msr_info->data = svm->vmcb->save.dbgctl;
3120 case MSR_IA32_LASTBRANCHFROMIP:
3121 msr_info->data = svm->vmcb->save.br_from;
3123 case MSR_IA32_LASTBRANCHTOIP:
3124 msr_info->data = svm->vmcb->save.br_to;
3126 case MSR_IA32_LASTINTFROMIP:
3127 msr_info->data = svm->vmcb->save.last_excp_from;
3129 case MSR_IA32_LASTINTTOIP:
3130 msr_info->data = svm->vmcb->save.last_excp_to;
3132 case MSR_VM_HSAVE_PA:
3133 msr_info->data = svm->nested.hsave_msr;
3136 msr_info->data = svm->nested.vm_cr_msr;
3138 case MSR_IA32_UCODE_REV:
3139 msr_info->data = 0x01000065;
3142 return kvm_get_msr_common(vcpu, msr_info);
3147 static int rdmsr_interception(struct vcpu_svm *svm)
3149 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3150 struct msr_data msr_info;
3152 msr_info.index = ecx;
3153 msr_info.host_initiated = false;
3154 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3155 trace_kvm_msr_read_ex(ecx);
3156 kvm_inject_gp(&svm->vcpu, 0);
3158 trace_kvm_msr_read(ecx, msr_info.data);
3160 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3161 msr_info.data & 0xffffffff);
3162 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3163 msr_info.data >> 32);
3164 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3165 skip_emulated_instruction(&svm->vcpu);
3170 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3172 struct vcpu_svm *svm = to_svm(vcpu);
3173 int svm_dis, chg_mask;
3175 if (data & ~SVM_VM_CR_VALID_MASK)
3178 chg_mask = SVM_VM_CR_VALID_MASK;
3180 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3181 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3183 svm->nested.vm_cr_msr &= ~chg_mask;
3184 svm->nested.vm_cr_msr |= (data & chg_mask);
3186 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3188 /* check for svm_disable while efer.svme is set */
3189 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3195 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3197 struct vcpu_svm *svm = to_svm(vcpu);
3199 u32 ecx = msr->index;
3200 u64 data = msr->data;
3203 kvm_write_tsc(vcpu, msr);
3206 svm->vmcb->save.star = data;
3208 #ifdef CONFIG_X86_64
3210 svm->vmcb->save.lstar = data;
3213 svm->vmcb->save.cstar = data;
3215 case MSR_KERNEL_GS_BASE:
3216 svm->vmcb->save.kernel_gs_base = data;
3218 case MSR_SYSCALL_MASK:
3219 svm->vmcb->save.sfmask = data;
3222 case MSR_IA32_SYSENTER_CS:
3223 svm->vmcb->save.sysenter_cs = data;
3225 case MSR_IA32_SYSENTER_EIP:
3226 svm->sysenter_eip = data;
3227 svm->vmcb->save.sysenter_eip = data;
3229 case MSR_IA32_SYSENTER_ESP:
3230 svm->sysenter_esp = data;
3231 svm->vmcb->save.sysenter_esp = data;
3233 case MSR_IA32_DEBUGCTLMSR:
3234 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3235 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3239 if (data & DEBUGCTL_RESERVED_BITS)
3242 svm->vmcb->save.dbgctl = data;
3243 mark_dirty(svm->vmcb, VMCB_LBR);
3244 if (data & (1ULL<<0))
3245 svm_enable_lbrv(svm);
3247 svm_disable_lbrv(svm);
3249 case MSR_VM_HSAVE_PA:
3250 svm->nested.hsave_msr = data;
3253 return svm_set_vm_cr(vcpu, data);
3255 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3258 return kvm_set_msr_common(vcpu, msr);
3263 static int wrmsr_interception(struct vcpu_svm *svm)
3265 struct msr_data msr;
3266 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3267 u64 data = kvm_read_edx_eax(&svm->vcpu);
3271 msr.host_initiated = false;
3273 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3274 if (kvm_set_msr(&svm->vcpu, &msr)) {
3275 trace_kvm_msr_write_ex(ecx, data);
3276 kvm_inject_gp(&svm->vcpu, 0);
3278 trace_kvm_msr_write(ecx, data);
3279 skip_emulated_instruction(&svm->vcpu);
3284 static int msr_interception(struct vcpu_svm *svm)
3286 if (svm->vmcb->control.exit_info_1)
3287 return wrmsr_interception(svm);
3289 return rdmsr_interception(svm);
3292 static int interrupt_window_interception(struct vcpu_svm *svm)
3294 struct kvm_run *kvm_run = svm->vcpu.run;
3296 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3297 svm_clear_vintr(svm);
3298 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3299 mark_dirty(svm->vmcb, VMCB_INTR);
3300 ++svm->vcpu.stat.irq_window_exits;
3302 * If the user space waits to inject interrupts, exit as soon as
3305 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3306 kvm_run->request_interrupt_window &&
3307 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3308 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3315 static int pause_interception(struct vcpu_svm *svm)
3317 kvm_vcpu_on_spin(&(svm->vcpu));
3321 static int nop_interception(struct vcpu_svm *svm)
3323 skip_emulated_instruction(&(svm->vcpu));
3327 static int monitor_interception(struct vcpu_svm *svm)
3329 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3330 return nop_interception(svm);
3333 static int mwait_interception(struct vcpu_svm *svm)
3335 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3336 return nop_interception(svm);
3339 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3340 [SVM_EXIT_READ_CR0] = cr_interception,
3341 [SVM_EXIT_READ_CR3] = cr_interception,
3342 [SVM_EXIT_READ_CR4] = cr_interception,
3343 [SVM_EXIT_READ_CR8] = cr_interception,
3344 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3345 [SVM_EXIT_WRITE_CR0] = cr_interception,
3346 [SVM_EXIT_WRITE_CR3] = cr_interception,
3347 [SVM_EXIT_WRITE_CR4] = cr_interception,
3348 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3349 [SVM_EXIT_READ_DR0] = dr_interception,
3350 [SVM_EXIT_READ_DR1] = dr_interception,
3351 [SVM_EXIT_READ_DR2] = dr_interception,
3352 [SVM_EXIT_READ_DR3] = dr_interception,
3353 [SVM_EXIT_READ_DR4] = dr_interception,
3354 [SVM_EXIT_READ_DR5] = dr_interception,
3355 [SVM_EXIT_READ_DR6] = dr_interception,
3356 [SVM_EXIT_READ_DR7] = dr_interception,
3357 [SVM_EXIT_WRITE_DR0] = dr_interception,
3358 [SVM_EXIT_WRITE_DR1] = dr_interception,
3359 [SVM_EXIT_WRITE_DR2] = dr_interception,
3360 [SVM_EXIT_WRITE_DR3] = dr_interception,
3361 [SVM_EXIT_WRITE_DR4] = dr_interception,
3362 [SVM_EXIT_WRITE_DR5] = dr_interception,
3363 [SVM_EXIT_WRITE_DR6] = dr_interception,
3364 [SVM_EXIT_WRITE_DR7] = dr_interception,
3365 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3366 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3367 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3368 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3369 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3370 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3371 [SVM_EXIT_INTR] = intr_interception,
3372 [SVM_EXIT_NMI] = nmi_interception,
3373 [SVM_EXIT_SMI] = nop_on_interception,
3374 [SVM_EXIT_INIT] = nop_on_interception,
3375 [SVM_EXIT_VINTR] = interrupt_window_interception,
3376 [SVM_EXIT_RDPMC] = rdpmc_interception,
3377 [SVM_EXIT_CPUID] = cpuid_interception,
3378 [SVM_EXIT_IRET] = iret_interception,
3379 [SVM_EXIT_INVD] = emulate_on_interception,
3380 [SVM_EXIT_PAUSE] = pause_interception,
3381 [SVM_EXIT_HLT] = halt_interception,
3382 [SVM_EXIT_INVLPG] = invlpg_interception,
3383 [SVM_EXIT_INVLPGA] = invlpga_interception,
3384 [SVM_EXIT_IOIO] = io_interception,
3385 [SVM_EXIT_MSR] = msr_interception,
3386 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3387 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3388 [SVM_EXIT_VMRUN] = vmrun_interception,
3389 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3390 [SVM_EXIT_VMLOAD] = vmload_interception,
3391 [SVM_EXIT_VMSAVE] = vmsave_interception,
3392 [SVM_EXIT_STGI] = stgi_interception,
3393 [SVM_EXIT_CLGI] = clgi_interception,
3394 [SVM_EXIT_SKINIT] = skinit_interception,
3395 [SVM_EXIT_WBINVD] = wbinvd_interception,
3396 [SVM_EXIT_MONITOR] = monitor_interception,
3397 [SVM_EXIT_MWAIT] = mwait_interception,
3398 [SVM_EXIT_XSETBV] = xsetbv_interception,
3399 [SVM_EXIT_NPF] = pf_interception,
3400 [SVM_EXIT_RSM] = emulate_on_interception,
3403 static void dump_vmcb(struct kvm_vcpu *vcpu)
3405 struct vcpu_svm *svm = to_svm(vcpu);
3406 struct vmcb_control_area *control = &svm->vmcb->control;
3407 struct vmcb_save_area *save = &svm->vmcb->save;
3409 pr_err("VMCB Control Area:\n");
3410 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3411 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3412 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3413 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3414 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3415 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3416 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3417 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3418 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3419 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3420 pr_err("%-20s%d\n", "asid:", control->asid);
3421 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3422 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3423 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3424 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3425 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3426 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3427 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3428 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3429 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3430 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3431 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3432 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3433 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3434 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3435 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3436 pr_err("VMCB State Save Area:\n");
3437 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3439 save->es.selector, save->es.attrib,
3440 save->es.limit, save->es.base);
3441 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3443 save->cs.selector, save->cs.attrib,
3444 save->cs.limit, save->cs.base);
3445 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3447 save->ss.selector, save->ss.attrib,
3448 save->ss.limit, save->ss.base);
3449 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3451 save->ds.selector, save->ds.attrib,
3452 save->ds.limit, save->ds.base);
3453 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3455 save->fs.selector, save->fs.attrib,
3456 save->fs.limit, save->fs.base);
3457 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3459 save->gs.selector, save->gs.attrib,
3460 save->gs.limit, save->gs.base);
3461 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3463 save->gdtr.selector, save->gdtr.attrib,
3464 save->gdtr.limit, save->gdtr.base);
3465 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3467 save->ldtr.selector, save->ldtr.attrib,
3468 save->ldtr.limit, save->ldtr.base);
3469 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3471 save->idtr.selector, save->idtr.attrib,
3472 save->idtr.limit, save->idtr.base);
3473 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3475 save->tr.selector, save->tr.attrib,
3476 save->tr.limit, save->tr.base);
3477 pr_err("cpl: %d efer: %016llx\n",
3478 save->cpl, save->efer);
3479 pr_err("%-15s %016llx %-13s %016llx\n",
3480 "cr0:", save->cr0, "cr2:", save->cr2);
3481 pr_err("%-15s %016llx %-13s %016llx\n",
3482 "cr3:", save->cr3, "cr4:", save->cr4);
3483 pr_err("%-15s %016llx %-13s %016llx\n",
3484 "dr6:", save->dr6, "dr7:", save->dr7);
3485 pr_err("%-15s %016llx %-13s %016llx\n",
3486 "rip:", save->rip, "rflags:", save->rflags);
3487 pr_err("%-15s %016llx %-13s %016llx\n",
3488 "rsp:", save->rsp, "rax:", save->rax);
3489 pr_err("%-15s %016llx %-13s %016llx\n",
3490 "star:", save->star, "lstar:", save->lstar);
3491 pr_err("%-15s %016llx %-13s %016llx\n",
3492 "cstar:", save->cstar, "sfmask:", save->sfmask);
3493 pr_err("%-15s %016llx %-13s %016llx\n",
3494 "kernel_gs_base:", save->kernel_gs_base,
3495 "sysenter_cs:", save->sysenter_cs);
3496 pr_err("%-15s %016llx %-13s %016llx\n",
3497 "sysenter_esp:", save->sysenter_esp,
3498 "sysenter_eip:", save->sysenter_eip);
3499 pr_err("%-15s %016llx %-13s %016llx\n",
3500 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3501 pr_err("%-15s %016llx %-13s %016llx\n",
3502 "br_from:", save->br_from, "br_to:", save->br_to);
3503 pr_err("%-15s %016llx %-13s %016llx\n",
3504 "excp_from:", save->last_excp_from,
3505 "excp_to:", save->last_excp_to);
3508 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3510 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3512 *info1 = control->exit_info_1;
3513 *info2 = control->exit_info_2;
3516 static int handle_exit(struct kvm_vcpu *vcpu)
3518 struct vcpu_svm *svm = to_svm(vcpu);
3519 struct kvm_run *kvm_run = vcpu->run;
3520 u32 exit_code = svm->vmcb->control.exit_code;
3522 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3523 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3525 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3527 if (unlikely(svm->nested.exit_required)) {
3528 nested_svm_vmexit(svm);
3529 svm->nested.exit_required = false;
3534 if (is_guest_mode(vcpu)) {
3537 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3538 svm->vmcb->control.exit_info_1,
3539 svm->vmcb->control.exit_info_2,
3540 svm->vmcb->control.exit_int_info,
3541 svm->vmcb->control.exit_int_info_err,
3544 vmexit = nested_svm_exit_special(svm);
3546 if (vmexit == NESTED_EXIT_CONTINUE)
3547 vmexit = nested_svm_exit_handled(svm);
3549 if (vmexit == NESTED_EXIT_DONE)
3553 svm_complete_interrupts(svm);
3555 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3556 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3557 kvm_run->fail_entry.hardware_entry_failure_reason
3558 = svm->vmcb->control.exit_code;
3559 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3564 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3565 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3566 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3567 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3568 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3570 __func__, svm->vmcb->control.exit_int_info,
3573 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3574 || !svm_exit_handlers[exit_code]) {
3575 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
3576 kvm_queue_exception(vcpu, UD_VECTOR);
3580 return svm_exit_handlers[exit_code](svm);
3583 static void reload_tss(struct kvm_vcpu *vcpu)
3585 int cpu = raw_smp_processor_id();
3587 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3588 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3592 static void pre_svm_run(struct vcpu_svm *svm)
3594 int cpu = raw_smp_processor_id();
3596 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3598 /* FIXME: handle wraparound of asid_generation */
3599 if (svm->asid_generation != sd->asid_generation)
3603 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3605 struct vcpu_svm *svm = to_svm(vcpu);
3607 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3608 vcpu->arch.hflags |= HF_NMI_MASK;
3609 set_intercept(svm, INTERCEPT_IRET);
3610 ++vcpu->stat.nmi_injections;
3613 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3615 struct vmcb_control_area *control;
3617 control = &svm->vmcb->control;
3618 control->int_vector = irq;
3619 control->int_ctl &= ~V_INTR_PRIO_MASK;
3620 control->int_ctl |= V_IRQ_MASK |
3621 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3622 mark_dirty(svm->vmcb, VMCB_INTR);
3625 static void svm_set_irq(struct kvm_vcpu *vcpu)
3627 struct vcpu_svm *svm = to_svm(vcpu);
3629 BUG_ON(!(gif_set(svm)));
3631 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3632 ++vcpu->stat.irq_injections;
3634 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3635 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3638 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3640 struct vcpu_svm *svm = to_svm(vcpu);
3642 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3645 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3651 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3654 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3659 static int svm_vm_has_apicv(struct kvm *kvm)
3664 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3669 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3674 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3676 struct vcpu_svm *svm = to_svm(vcpu);
3677 struct vmcb *vmcb = svm->vmcb;
3679 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3680 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3681 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3686 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3688 struct vcpu_svm *svm = to_svm(vcpu);
3690 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3693 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3695 struct vcpu_svm *svm = to_svm(vcpu);
3698 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3699 set_intercept(svm, INTERCEPT_IRET);
3701 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3702 clr_intercept(svm, INTERCEPT_IRET);
3706 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3708 struct vcpu_svm *svm = to_svm(vcpu);
3709 struct vmcb *vmcb = svm->vmcb;
3712 if (!gif_set(svm) ||
3713 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3716 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3718 if (is_guest_mode(vcpu))
3719 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3724 static void enable_irq_window(struct kvm_vcpu *vcpu)
3726 struct vcpu_svm *svm = to_svm(vcpu);
3729 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3730 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3731 * get that intercept, this function will be called again though and
3732 * we'll get the vintr intercept.
3734 if (gif_set(svm) && nested_svm_intr(svm)) {
3736 svm_inject_irq(svm, 0x0);
3740 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3742 struct vcpu_svm *svm = to_svm(vcpu);
3744 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3746 return; /* IRET will cause a vm exit */
3749 * Something prevents NMI from been injected. Single step over possible
3750 * problem (IRET or exception injection or interrupt shadow)
3752 svm->nmi_singlestep = true;
3753 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3754 update_db_bp_intercept(vcpu);
3757 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3762 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3764 struct vcpu_svm *svm = to_svm(vcpu);
3766 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3767 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3769 svm->asid_generation--;
3772 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3776 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3778 struct vcpu_svm *svm = to_svm(vcpu);
3780 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3783 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3784 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3785 kvm_set_cr8(vcpu, cr8);
3789 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3791 struct vcpu_svm *svm = to_svm(vcpu);
3794 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3797 cr8 = kvm_get_cr8(vcpu);
3798 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3799 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3802 static void svm_complete_interrupts(struct vcpu_svm *svm)
3806 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3807 unsigned int3_injected = svm->int3_injected;
3809 svm->int3_injected = 0;
3812 * If we've made progress since setting HF_IRET_MASK, we've
3813 * executed an IRET and can allow NMI injection.
3815 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3816 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3817 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3818 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3821 svm->vcpu.arch.nmi_injected = false;
3822 kvm_clear_exception_queue(&svm->vcpu);
3823 kvm_clear_interrupt_queue(&svm->vcpu);
3825 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3828 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3830 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3831 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3834 case SVM_EXITINTINFO_TYPE_NMI:
3835 svm->vcpu.arch.nmi_injected = true;
3837 case SVM_EXITINTINFO_TYPE_EXEPT:
3839 * In case of software exceptions, do not reinject the vector,
3840 * but re-execute the instruction instead. Rewind RIP first
3841 * if we emulated INT3 before.
3843 if (kvm_exception_is_soft(vector)) {
3844 if (vector == BP_VECTOR && int3_injected &&
3845 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3846 kvm_rip_write(&svm->vcpu,
3847 kvm_rip_read(&svm->vcpu) -
3851 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3852 u32 err = svm->vmcb->control.exit_int_info_err;
3853 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3856 kvm_requeue_exception(&svm->vcpu, vector);
3858 case SVM_EXITINTINFO_TYPE_INTR:
3859 kvm_queue_interrupt(&svm->vcpu, vector, false);
3866 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3868 struct vcpu_svm *svm = to_svm(vcpu);
3869 struct vmcb_control_area *control = &svm->vmcb->control;
3871 control->exit_int_info = control->event_inj;
3872 control->exit_int_info_err = control->event_inj_err;
3873 control->event_inj = 0;
3874 svm_complete_interrupts(svm);
3877 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3879 struct vcpu_svm *svm = to_svm(vcpu);
3881 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3882 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3883 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3886 * A vmexit emulation is required before the vcpu can be executed
3889 if (unlikely(svm->nested.exit_required))
3894 sync_lapic_to_cr8(vcpu);
3896 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3903 "push %%" _ASM_BP "; \n\t"
3904 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3905 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3906 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3907 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3908 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3909 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3910 #ifdef CONFIG_X86_64
3911 "mov %c[r8](%[svm]), %%r8 \n\t"
3912 "mov %c[r9](%[svm]), %%r9 \n\t"
3913 "mov %c[r10](%[svm]), %%r10 \n\t"
3914 "mov %c[r11](%[svm]), %%r11 \n\t"
3915 "mov %c[r12](%[svm]), %%r12 \n\t"
3916 "mov %c[r13](%[svm]), %%r13 \n\t"
3917 "mov %c[r14](%[svm]), %%r14 \n\t"
3918 "mov %c[r15](%[svm]), %%r15 \n\t"
3921 /* Enter guest mode */
3922 "push %%" _ASM_AX " \n\t"
3923 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3924 __ex(SVM_VMLOAD) "\n\t"
3925 __ex(SVM_VMRUN) "\n\t"
3926 __ex(SVM_VMSAVE) "\n\t"
3927 "pop %%" _ASM_AX " \n\t"
3929 /* Save guest registers, load host registers */
3930 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3931 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3932 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3933 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3934 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3935 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3936 #ifdef CONFIG_X86_64
3937 "mov %%r8, %c[r8](%[svm]) \n\t"
3938 "mov %%r9, %c[r9](%[svm]) \n\t"
3939 "mov %%r10, %c[r10](%[svm]) \n\t"
3940 "mov %%r11, %c[r11](%[svm]) \n\t"
3941 "mov %%r12, %c[r12](%[svm]) \n\t"
3942 "mov %%r13, %c[r13](%[svm]) \n\t"
3943 "mov %%r14, %c[r14](%[svm]) \n\t"
3944 "mov %%r15, %c[r15](%[svm]) \n\t"
3949 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3950 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3951 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3952 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3953 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3954 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3955 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3956 #ifdef CONFIG_X86_64
3957 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3958 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3959 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3960 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3961 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3962 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3963 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3964 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3967 #ifdef CONFIG_X86_64
3968 , "rbx", "rcx", "rdx", "rsi", "rdi"
3969 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3971 , "ebx", "ecx", "edx", "esi", "edi"
3975 #ifdef CONFIG_X86_64
3976 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3978 loadsegment(fs, svm->host.fs);
3979 #ifndef CONFIG_X86_32_LAZY_GS
3980 loadsegment(gs, svm->host.gs);
3986 local_irq_disable();
3988 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3989 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3990 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3991 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3993 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3995 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3996 kvm_before_handle_nmi(&svm->vcpu);
4000 /* Any pending NMI will happen here */
4002 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4003 kvm_after_handle_nmi(&svm->vcpu);
4005 sync_cr8_to_lapic(vcpu);
4009 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4011 /* if exit due to PF check for async PF */
4012 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4013 svm->apf_reason = kvm_read_and_reset_pf_reason();
4016 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4017 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4021 * We need to handle MC intercepts here before the vcpu has a chance to
4022 * change the physical cpu
4024 if (unlikely(svm->vmcb->control.exit_code ==
4025 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4026 svm_handle_mce(svm);
4028 mark_all_clean(svm->vmcb);
4031 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4033 struct vcpu_svm *svm = to_svm(vcpu);
4035 svm->vmcb->save.cr3 = root;
4036 mark_dirty(svm->vmcb, VMCB_CR);
4037 svm_flush_tlb(vcpu);
4040 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4042 struct vcpu_svm *svm = to_svm(vcpu);
4044 svm->vmcb->control.nested_cr3 = root;
4045 mark_dirty(svm->vmcb, VMCB_NPT);
4047 /* Also sync guest cr3 here in case we live migrate */
4048 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4049 mark_dirty(svm->vmcb, VMCB_CR);
4051 svm_flush_tlb(vcpu);
4054 static int is_disabled(void)
4058 rdmsrl(MSR_VM_CR, vm_cr);
4059 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4066 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4069 * Patch in the VMMCALL instruction:
4071 hypercall[0] = 0x0f;
4072 hypercall[1] = 0x01;
4073 hypercall[2] = 0xd9;
4076 static void svm_check_processor_compat(void *rtn)
4081 static bool svm_cpu_has_accelerated_tpr(void)
4086 static bool svm_has_high_real_mode_segbase(void)
4091 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4096 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4100 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4105 entry->ecx |= (1 << 2); /* Set SVM bit */
4108 entry->eax = 1; /* SVM revision 1 */
4109 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4110 ASID emulation to nested SVM */
4111 entry->ecx = 0; /* Reserved */
4112 entry->edx = 0; /* Per default do not support any
4113 additional features */
4115 /* Support next_rip if host supports it */
4116 if (boot_cpu_has(X86_FEATURE_NRIPS))
4117 entry->edx |= SVM_FEATURE_NRIP;
4119 /* Support NPT for the guest if enabled */
4121 entry->edx |= SVM_FEATURE_NPT;
4127 static int svm_get_lpage_level(void)
4129 return PT_PDPE_LEVEL;
4132 static bool svm_rdtscp_supported(void)
4137 static bool svm_invpcid_supported(void)
4142 static bool svm_mpx_supported(void)
4147 static bool svm_xsaves_supported(void)
4152 static bool svm_has_wbinvd_exit(void)
4157 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4159 struct vcpu_svm *svm = to_svm(vcpu);
4161 set_exception_intercept(svm, NM_VECTOR);
4162 update_cr0_intercept(svm);
4165 #define PRE_EX(exit) { .exit_code = (exit), \
4166 .stage = X86_ICPT_PRE_EXCEPT, }
4167 #define POST_EX(exit) { .exit_code = (exit), \
4168 .stage = X86_ICPT_POST_EXCEPT, }
4169 #define POST_MEM(exit) { .exit_code = (exit), \
4170 .stage = X86_ICPT_POST_MEMACCESS, }
4172 static const struct __x86_intercept {
4174 enum x86_intercept_stage stage;
4175 } x86_intercept_map[] = {
4176 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4177 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4178 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4179 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4180 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4181 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4182 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4183 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4184 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4185 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4186 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4187 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4188 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4189 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4190 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4191 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4192 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4193 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4194 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4195 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4196 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4197 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4198 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4199 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4200 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4201 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4202 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4203 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4204 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4205 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4206 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4207 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4208 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4209 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4210 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4211 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4212 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4213 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4214 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4215 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4216 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4217 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4218 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4219 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4220 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4221 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4228 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4229 struct x86_instruction_info *info,
4230 enum x86_intercept_stage stage)
4232 struct vcpu_svm *svm = to_svm(vcpu);
4233 int vmexit, ret = X86EMUL_CONTINUE;
4234 struct __x86_intercept icpt_info;
4235 struct vmcb *vmcb = svm->vmcb;
4237 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4240 icpt_info = x86_intercept_map[info->intercept];
4242 if (stage != icpt_info.stage)
4245 switch (icpt_info.exit_code) {
4246 case SVM_EXIT_READ_CR0:
4247 if (info->intercept == x86_intercept_cr_read)
4248 icpt_info.exit_code += info->modrm_reg;
4250 case SVM_EXIT_WRITE_CR0: {
4251 unsigned long cr0, val;
4254 if (info->intercept == x86_intercept_cr_write)
4255 icpt_info.exit_code += info->modrm_reg;
4257 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4258 info->intercept == x86_intercept_clts)
4261 intercept = svm->nested.intercept;
4263 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4266 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4267 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4269 if (info->intercept == x86_intercept_lmsw) {
4272 /* lmsw can't clear PE - catch this here */
4273 if (cr0 & X86_CR0_PE)
4278 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4282 case SVM_EXIT_READ_DR0:
4283 case SVM_EXIT_WRITE_DR0:
4284 icpt_info.exit_code += info->modrm_reg;
4287 if (info->intercept == x86_intercept_wrmsr)
4288 vmcb->control.exit_info_1 = 1;
4290 vmcb->control.exit_info_1 = 0;
4292 case SVM_EXIT_PAUSE:
4294 * We get this for NOP only, but pause
4295 * is rep not, check this here
4297 if (info->rep_prefix != REPE_PREFIX)
4299 case SVM_EXIT_IOIO: {
4303 if (info->intercept == x86_intercept_in ||
4304 info->intercept == x86_intercept_ins) {
4305 exit_info = ((info->src_val & 0xffff) << 16) |
4307 bytes = info->dst_bytes;
4309 exit_info = (info->dst_val & 0xffff) << 16;
4310 bytes = info->src_bytes;
4313 if (info->intercept == x86_intercept_outs ||
4314 info->intercept == x86_intercept_ins)
4315 exit_info |= SVM_IOIO_STR_MASK;
4317 if (info->rep_prefix)
4318 exit_info |= SVM_IOIO_REP_MASK;
4320 bytes = min(bytes, 4u);
4322 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4324 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4326 vmcb->control.exit_info_1 = exit_info;
4327 vmcb->control.exit_info_2 = info->next_rip;
4335 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4336 if (static_cpu_has(X86_FEATURE_NRIPS))
4337 vmcb->control.next_rip = info->next_rip;
4338 vmcb->control.exit_code = icpt_info.exit_code;
4339 vmexit = nested_svm_exit_handled(svm);
4341 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4348 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4353 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4357 static struct kvm_x86_ops svm_x86_ops = {
4358 .cpu_has_kvm_support = has_svm,
4359 .disabled_by_bios = is_disabled,
4360 .hardware_setup = svm_hardware_setup,
4361 .hardware_unsetup = svm_hardware_unsetup,
4362 .check_processor_compatibility = svm_check_processor_compat,
4363 .hardware_enable = svm_hardware_enable,
4364 .hardware_disable = svm_hardware_disable,
4365 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4366 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
4368 .vcpu_create = svm_create_vcpu,
4369 .vcpu_free = svm_free_vcpu,
4370 .vcpu_reset = svm_vcpu_reset,
4372 .prepare_guest_switch = svm_prepare_guest_switch,
4373 .vcpu_load = svm_vcpu_load,
4374 .vcpu_put = svm_vcpu_put,
4376 .update_db_bp_intercept = update_db_bp_intercept,
4377 .get_msr = svm_get_msr,
4378 .set_msr = svm_set_msr,
4379 .get_segment_base = svm_get_segment_base,
4380 .get_segment = svm_get_segment,
4381 .set_segment = svm_set_segment,
4382 .get_cpl = svm_get_cpl,
4383 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4384 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4385 .decache_cr3 = svm_decache_cr3,
4386 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4387 .set_cr0 = svm_set_cr0,
4388 .set_cr3 = svm_set_cr3,
4389 .set_cr4 = svm_set_cr4,
4390 .set_efer = svm_set_efer,
4391 .get_idt = svm_get_idt,
4392 .set_idt = svm_set_idt,
4393 .get_gdt = svm_get_gdt,
4394 .set_gdt = svm_set_gdt,
4395 .get_dr6 = svm_get_dr6,
4396 .set_dr6 = svm_set_dr6,
4397 .set_dr7 = svm_set_dr7,
4398 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4399 .cache_reg = svm_cache_reg,
4400 .get_rflags = svm_get_rflags,
4401 .set_rflags = svm_set_rflags,
4402 .fpu_activate = svm_fpu_activate,
4403 .fpu_deactivate = svm_fpu_deactivate,
4405 .tlb_flush = svm_flush_tlb,
4407 .run = svm_vcpu_run,
4408 .handle_exit = handle_exit,
4409 .skip_emulated_instruction = skip_emulated_instruction,
4410 .set_interrupt_shadow = svm_set_interrupt_shadow,
4411 .get_interrupt_shadow = svm_get_interrupt_shadow,
4412 .patch_hypercall = svm_patch_hypercall,
4413 .set_irq = svm_set_irq,
4414 .set_nmi = svm_inject_nmi,
4415 .queue_exception = svm_queue_exception,
4416 .cancel_injection = svm_cancel_injection,
4417 .interrupt_allowed = svm_interrupt_allowed,
4418 .nmi_allowed = svm_nmi_allowed,
4419 .get_nmi_mask = svm_get_nmi_mask,
4420 .set_nmi_mask = svm_set_nmi_mask,
4421 .enable_nmi_window = enable_nmi_window,
4422 .enable_irq_window = enable_irq_window,
4423 .update_cr8_intercept = update_cr8_intercept,
4424 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4425 .vm_has_apicv = svm_vm_has_apicv,
4426 .load_eoi_exitmap = svm_load_eoi_exitmap,
4427 .sync_pir_to_irr = svm_sync_pir_to_irr,
4429 .set_tss_addr = svm_set_tss_addr,
4430 .get_tdp_level = get_npt_level,
4431 .get_mt_mask = svm_get_mt_mask,
4433 .get_exit_info = svm_get_exit_info,
4435 .get_lpage_level = svm_get_lpage_level,
4437 .cpuid_update = svm_cpuid_update,
4439 .rdtscp_supported = svm_rdtscp_supported,
4440 .invpcid_supported = svm_invpcid_supported,
4441 .mpx_supported = svm_mpx_supported,
4442 .xsaves_supported = svm_xsaves_supported,
4444 .set_supported_cpuid = svm_set_supported_cpuid,
4446 .has_wbinvd_exit = svm_has_wbinvd_exit,
4448 .set_tsc_khz = svm_set_tsc_khz,
4449 .read_tsc_offset = svm_read_tsc_offset,
4450 .write_tsc_offset = svm_write_tsc_offset,
4451 .adjust_tsc_offset = svm_adjust_tsc_offset,
4452 .compute_tsc_offset = svm_compute_tsc_offset,
4453 .read_l1_tsc = svm_read_l1_tsc,
4455 .set_tdp_cr3 = set_tdp_cr3,
4457 .check_intercept = svm_check_intercept,
4458 .handle_external_intr = svm_handle_external_intr,
4460 .sched_in = svm_sched_in,
4462 .pmu_ops = &amd_pmu_ops,
4465 static int __init svm_init(void)
4467 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4468 __alignof__(struct vcpu_svm), THIS_MODULE);
4471 static void __exit svm_exit(void)
4476 module_init(svm_init)
4477 module_exit(svm_exit)