2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53 #define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
59 static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
63 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
65 static bool __read_mostly enable_vpid = 1;
66 module_param_named(vpid, enable_vpid, bool, 0444);
68 static bool __read_mostly flexpriority_enabled = 1;
69 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
71 static bool __read_mostly enable_ept = 1;
72 module_param_named(ept, enable_ept, bool, S_IRUGO);
74 static bool __read_mostly enable_unrestricted_guest = 1;
75 module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
78 static bool __read_mostly enable_ept_ad_bits = 1;
79 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
81 static bool __read_mostly emulate_invalid_guest_state = true;
82 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
84 static bool __read_mostly vmm_exclusive = 1;
85 module_param(vmm_exclusive, bool, S_IRUGO);
87 static bool __read_mostly fasteoi = 1;
88 module_param(fasteoi, bool, S_IRUGO);
90 static bool __read_mostly enable_apicv = 1;
91 module_param(enable_apicv, bool, S_IRUGO);
93 static bool __read_mostly enable_shadow_vmcs = 1;
94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
100 static bool __read_mostly nested = 0;
101 module_param(nested, bool, S_IRUGO);
103 static u64 __read_mostly host_xss;
105 static bool __read_mostly enable_pml = 1;
106 module_param_named(pml, enable_pml, bool, S_IRUGO);
108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
110 #define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
112 #define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
127 * According to test, this time is usually smaller than 128 cycles.
128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
134 #define KVM_VMX_DEFAULT_PLE_GAP 128
135 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
141 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142 module_param(ple_gap, int, S_IRUGO);
144 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145 module_param(ple_window, int, S_IRUGO);
147 /* Default doubles per-vcpu window every exit. */
148 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149 module_param(ple_window_grow, int, S_IRUGO);
151 /* Default resets per-vcpu window every exit to ple_window. */
152 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153 module_param(ple_window_shrink, int, S_IRUGO);
155 /* Default is to compute the maximum so we can never overflow. */
156 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158 module_param(ple_window_max, int, S_IRUGO);
160 extern const ulong vmx_return;
162 #define NR_AUTOLOAD_MSRS 8
163 #define VMCS02_POOL_SIZE 1
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
180 struct list_head loaded_vmcss_on_cpu_link;
183 struct shared_msr_entry {
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
202 typedef u64 natural_width;
203 struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
222 u64 posted_intr_desc_addr;
224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
234 u64 guest_ia32_perf_global_ctrl;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
323 u32 guest_ldtr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
341 u16 virtual_processor_id;
343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
351 u16 guest_intr_status;
352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
366 #define VMCS12_REVISION 0x11e57ed0
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
373 #define VMCS12_SIZE 0x1000
375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
377 struct list_head list;
379 struct loaded_vmcs vmcs02;
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
387 /* Has the level1 guest done vmxon? */
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
396 struct vmcs *current_shadow_vmcs;
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
401 bool sync_shadow_vmcs;
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
406 u64 vmcs01_tsc_offset;
407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
413 struct page *apic_access_page;
414 struct page *virtual_apic_page;
415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
419 u64 msr_ia32_feature_control;
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
445 #define POSTED_INTR_ON 0
446 /* Posted-Interrupt Descriptor */
448 u32 pir[8]; /* Posted interrupt requested */
449 u32 control; /* bit 0 of control is outstanding notification bit */
453 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
455 return test_and_set_bit(POSTED_INTR_ON,
456 (unsigned long *)&pi_desc->control);
459 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
461 return test_and_clear_bit(POSTED_INTR_ON,
462 (unsigned long *)&pi_desc->control);
465 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
467 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
471 struct kvm_vcpu vcpu;
472 unsigned long host_rsp;
474 bool nmi_known_unmasked;
476 u32 idt_vectoring_info;
478 struct shared_msr_entry *guest_msrs;
481 unsigned long host_idt_base;
483 u64 msr_host_kernel_gs_base;
484 u64 msr_guest_kernel_gs_base;
486 u32 vm_entry_controls_shadow;
487 u32 vm_exit_controls_shadow;
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
493 struct loaded_vmcs vmcs01;
494 struct loaded_vmcs *loaded_vmcs;
495 bool __launched; /* temporary, used in vmx_vcpu_run */
496 struct msr_autoload {
498 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
503 u16 fs_sel, gs_sel, ldt_sel;
507 int gs_ldt_reload_needed;
508 int fs_reload_needed;
509 u64 msr_host_bndcfgs;
510 unsigned long vmcs_host_cr4; /* May not match real cr4 */
515 struct kvm_segment segs[8];
518 u32 bitmask; /* 4 bits per segment (1 bit per field) */
519 struct kvm_save_segment {
527 bool emulation_required;
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked;
532 s64 vnmi_blocked_time;
537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc;
540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested;
543 /* Dynamic PLE window. */
545 bool ple_window_dirty;
547 /* Support for PML */
548 #define PML_ENTITY_NUM 512
552 enum segment_cache_field {
561 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
563 return container_of(vcpu, struct vcpu_vmx, vcpu);
566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
572 static unsigned long shadow_read_only_fields[] = {
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
587 VM_EXIT_INSTRUCTION_LEN,
588 IDT_VECTORING_INFO_FIELD,
589 IDT_VECTORING_ERROR_CODE,
590 VM_EXIT_INTR_ERROR_CODE,
592 GUEST_LINEAR_ADDRESS,
593 GUEST_PHYSICAL_ADDRESS
595 static int max_shadow_read_only_fields =
596 ARRAY_SIZE(shadow_read_only_fields);
598 static unsigned long shadow_read_write_fields[] = {
605 GUEST_INTERRUPTIBILITY_INFO,
618 CPU_BASED_VM_EXEC_CONTROL,
619 VM_ENTRY_EXCEPTION_ERROR_CODE,
620 VM_ENTRY_INTR_INFO_FIELD,
621 VM_ENTRY_INSTRUCTION_LEN,
622 VM_ENTRY_EXCEPTION_ERROR_CODE,
628 static int max_shadow_read_write_fields =
629 ARRAY_SIZE(shadow_read_write_fields);
631 static const unsigned short vmcs_field_to_offset_table[] = {
632 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
633 FIELD(POSTED_INTR_NV, posted_intr_nv),
634 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
642 FIELD(GUEST_INTR_STATUS, guest_intr_status),
643 FIELD(HOST_ES_SELECTOR, host_es_selector),
644 FIELD(HOST_CS_SELECTOR, host_cs_selector),
645 FIELD(HOST_SS_SELECTOR, host_ss_selector),
646 FIELD(HOST_DS_SELECTOR, host_ds_selector),
647 FIELD(HOST_FS_SELECTOR, host_fs_selector),
648 FIELD(HOST_GS_SELECTOR, host_gs_selector),
649 FIELD(HOST_TR_SELECTOR, host_tr_selector),
650 FIELD64(IO_BITMAP_A, io_bitmap_a),
651 FIELD64(IO_BITMAP_B, io_bitmap_b),
652 FIELD64(MSR_BITMAP, msr_bitmap),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656 FIELD64(TSC_OFFSET, tsc_offset),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
659 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
660 FIELD64(EPT_POINTER, ept_pointer),
661 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
665 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
666 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672 FIELD64(GUEST_PDPTR0, guest_pdptr0),
673 FIELD64(GUEST_PDPTR1, guest_pdptr1),
674 FIELD64(GUEST_PDPTR2, guest_pdptr2),
675 FIELD64(GUEST_PDPTR3, guest_pdptr3),
676 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
677 FIELD64(HOST_IA32_PAT, host_ia32_pat),
678 FIELD64(HOST_IA32_EFER, host_ia32_efer),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682 FIELD(EXCEPTION_BITMAP, exception_bitmap),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685 FIELD(CR3_TARGET_COUNT, cr3_target_count),
686 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694 FIELD(TPR_THRESHOLD, tpr_threshold),
695 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697 FIELD(VM_EXIT_REASON, vm_exit_reason),
698 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704 FIELD(GUEST_ES_LIMIT, guest_es_limit),
705 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
726 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
727 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735 FIELD(EXIT_QUALIFICATION, exit_qualification),
736 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737 FIELD(GUEST_CR0, guest_cr0),
738 FIELD(GUEST_CR3, guest_cr3),
739 FIELD(GUEST_CR4, guest_cr4),
740 FIELD(GUEST_ES_BASE, guest_es_base),
741 FIELD(GUEST_CS_BASE, guest_cs_base),
742 FIELD(GUEST_SS_BASE, guest_ss_base),
743 FIELD(GUEST_DS_BASE, guest_ds_base),
744 FIELD(GUEST_FS_BASE, guest_fs_base),
745 FIELD(GUEST_GS_BASE, guest_gs_base),
746 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747 FIELD(GUEST_TR_BASE, guest_tr_base),
748 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750 FIELD(GUEST_DR7, guest_dr7),
751 FIELD(GUEST_RSP, guest_rsp),
752 FIELD(GUEST_RIP, guest_rip),
753 FIELD(GUEST_RFLAGS, guest_rflags),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757 FIELD(HOST_CR0, host_cr0),
758 FIELD(HOST_CR3, host_cr3),
759 FIELD(HOST_CR4, host_cr4),
760 FIELD(HOST_FS_BASE, host_fs_base),
761 FIELD(HOST_GS_BASE, host_gs_base),
762 FIELD(HOST_TR_BASE, host_tr_base),
763 FIELD(HOST_GDTR_BASE, host_gdtr_base),
764 FIELD(HOST_IDTR_BASE, host_idtr_base),
765 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767 FIELD(HOST_RSP, host_rsp),
768 FIELD(HOST_RIP, host_rip),
771 static inline short vmcs_field_to_offset(unsigned long field)
773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
775 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776 vmcs_field_to_offset_table[field] == 0)
779 return vmcs_field_to_offset_table[field];
782 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
784 return to_vmx(vcpu)->nested.current_vmcs12;
787 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
789 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
790 if (is_error_page(page))
796 static void nested_release_page(struct page *page)
798 kvm_release_page_dirty(page);
801 static void nested_release_page_clean(struct page *page)
803 kvm_release_page_clean(page);
806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
807 static u64 construct_eptp(unsigned long root_hpa);
808 static void kvm_cpu_vmxon(u64 addr);
809 static void kvm_cpu_vmxoff(void);
810 static bool vmx_mpx_supported(void);
811 static bool vmx_xsaves_supported(void);
812 static int vmx_vm_has_apicv(struct kvm *kvm);
813 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
814 static void vmx_set_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg);
816 static void vmx_get_segment(struct kvm_vcpu *vcpu,
817 struct kvm_segment *var, int seg);
818 static bool guest_state_valid(struct kvm_vcpu *vcpu);
819 static u32 vmx_segment_access_rights(struct kvm_segment *var);
820 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
821 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
822 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
823 static int alloc_identity_pagetable(struct kvm *kvm);
825 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
828 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
831 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
832 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
834 static unsigned long *vmx_io_bitmap_a;
835 static unsigned long *vmx_io_bitmap_b;
836 static unsigned long *vmx_msr_bitmap_legacy;
837 static unsigned long *vmx_msr_bitmap_longmode;
838 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
840 static unsigned long *vmx_msr_bitmap_nested;
841 static unsigned long *vmx_vmread_bitmap;
842 static unsigned long *vmx_vmwrite_bitmap;
844 static bool cpu_has_load_ia32_efer;
845 static bool cpu_has_load_perf_global_ctrl;
847 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848 static DEFINE_SPINLOCK(vmx_vpid_lock);
850 static struct vmcs_config {
854 u32 pin_based_exec_ctrl;
855 u32 cpu_based_exec_ctrl;
856 u32 cpu_based_2nd_exec_ctrl;
861 static struct vmx_capability {
866 #define VMX_SEGMENT_FIELD(seg) \
867 [VCPU_SREG_##seg] = { \
868 .selector = GUEST_##seg##_SELECTOR, \
869 .base = GUEST_##seg##_BASE, \
870 .limit = GUEST_##seg##_LIMIT, \
871 .ar_bytes = GUEST_##seg##_AR_BYTES, \
874 static const struct kvm_vmx_segment_field {
879 } kvm_vmx_segment_fields[] = {
880 VMX_SEGMENT_FIELD(CS),
881 VMX_SEGMENT_FIELD(DS),
882 VMX_SEGMENT_FIELD(ES),
883 VMX_SEGMENT_FIELD(FS),
884 VMX_SEGMENT_FIELD(GS),
885 VMX_SEGMENT_FIELD(SS),
886 VMX_SEGMENT_FIELD(TR),
887 VMX_SEGMENT_FIELD(LDTR),
890 static u64 host_efer;
892 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
895 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
896 * away by decrementing the array size.
898 static const u32 vmx_msr_index[] = {
900 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
902 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
905 static inline bool is_page_fault(u32 intr_info)
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908 INTR_INFO_VALID_MASK)) ==
909 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
912 static inline bool is_no_device(u32 intr_info)
914 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915 INTR_INFO_VALID_MASK)) ==
916 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
919 static inline bool is_invalid_opcode(u32 intr_info)
921 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922 INTR_INFO_VALID_MASK)) ==
923 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
926 static inline bool is_external_interrupt(u32 intr_info)
928 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
932 static inline bool is_machine_check(u32 intr_info)
934 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935 INTR_INFO_VALID_MASK)) ==
936 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
939 static inline bool cpu_has_vmx_msr_bitmap(void)
941 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
944 static inline bool cpu_has_vmx_tpr_shadow(void)
946 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
949 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
951 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
954 static inline bool cpu_has_secondary_exec_ctrls(void)
956 return vmcs_config.cpu_based_exec_ctrl &
957 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
960 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
962 return vmcs_config.cpu_based_2nd_exec_ctrl &
963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
966 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
968 return vmcs_config.cpu_based_2nd_exec_ctrl &
969 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
972 static inline bool cpu_has_vmx_apic_register_virt(void)
974 return vmcs_config.cpu_based_2nd_exec_ctrl &
975 SECONDARY_EXEC_APIC_REGISTER_VIRT;
978 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
984 static inline bool cpu_has_vmx_posted_intr(void)
986 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
989 static inline bool cpu_has_vmx_apicv(void)
991 return cpu_has_vmx_apic_register_virt() &&
992 cpu_has_vmx_virtual_intr_delivery() &&
993 cpu_has_vmx_posted_intr();
996 static inline bool cpu_has_vmx_flexpriority(void)
998 return cpu_has_vmx_tpr_shadow() &&
999 cpu_has_vmx_virtualize_apic_accesses();
1002 static inline bool cpu_has_vmx_ept_execute_only(void)
1004 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1007 static inline bool cpu_has_vmx_ept_2m_page(void)
1009 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1012 static inline bool cpu_has_vmx_ept_1g_page(void)
1014 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1017 static inline bool cpu_has_vmx_ept_4levels(void)
1019 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1022 static inline bool cpu_has_vmx_ept_ad_bits(void)
1024 return vmx_capability.ept & VMX_EPT_AD_BIT;
1027 static inline bool cpu_has_vmx_invept_context(void)
1029 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1032 static inline bool cpu_has_vmx_invept_global(void)
1034 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1037 static inline bool cpu_has_vmx_invvpid_single(void)
1039 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1042 static inline bool cpu_has_vmx_invvpid_global(void)
1044 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1047 static inline bool cpu_has_vmx_ept(void)
1049 return vmcs_config.cpu_based_2nd_exec_ctrl &
1050 SECONDARY_EXEC_ENABLE_EPT;
1053 static inline bool cpu_has_vmx_unrestricted_guest(void)
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1059 static inline bool cpu_has_vmx_ple(void)
1061 return vmcs_config.cpu_based_2nd_exec_ctrl &
1062 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1065 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1067 return flexpriority_enabled && irqchip_in_kernel(kvm);
1070 static inline bool cpu_has_vmx_vpid(void)
1072 return vmcs_config.cpu_based_2nd_exec_ctrl &
1073 SECONDARY_EXEC_ENABLE_VPID;
1076 static inline bool cpu_has_vmx_rdtscp(void)
1078 return vmcs_config.cpu_based_2nd_exec_ctrl &
1079 SECONDARY_EXEC_RDTSCP;
1082 static inline bool cpu_has_vmx_invpcid(void)
1084 return vmcs_config.cpu_based_2nd_exec_ctrl &
1085 SECONDARY_EXEC_ENABLE_INVPCID;
1088 static inline bool cpu_has_virtual_nmis(void)
1090 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1093 static inline bool cpu_has_vmx_wbinvd_exit(void)
1095 return vmcs_config.cpu_based_2nd_exec_ctrl &
1096 SECONDARY_EXEC_WBINVD_EXITING;
1099 static inline bool cpu_has_vmx_shadow_vmcs(void)
1102 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103 /* check if the cpu supports writing r/o exit information fields */
1104 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1107 return vmcs_config.cpu_based_2nd_exec_ctrl &
1108 SECONDARY_EXEC_SHADOW_VMCS;
1111 static inline bool cpu_has_vmx_pml(void)
1113 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1116 static inline bool report_flexpriority(void)
1118 return flexpriority_enabled;
1121 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1123 return vmcs12->cpu_based_vm_exec_control & bit;
1126 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1128 return (vmcs12->cpu_based_vm_exec_control &
1129 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130 (vmcs12->secondary_vm_exec_control & bit);
1133 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1135 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1138 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1140 return vmcs12->pin_based_vm_exec_control &
1141 PIN_BASED_VMX_PREEMPTION_TIMER;
1144 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1146 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1149 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1151 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152 vmx_xsaves_supported();
1155 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1157 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1160 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1162 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1165 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1167 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1170 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1172 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1175 static inline bool is_exception(u32 intr_info)
1177 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1181 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1183 unsigned long exit_qualification);
1184 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185 struct vmcs12 *vmcs12,
1186 u32 reason, unsigned long qualification);
1188 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1192 for (i = 0; i < vmx->nmsrs; ++i)
1193 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1198 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1204 } operand = { vpid, 0, gva };
1206 asm volatile (__ex(ASM_VMX_INVVPID)
1207 /* CF==1 or ZF==1 --> rc = -1 */
1208 "; ja 1f ; ud2 ; 1:"
1209 : : "a"(&operand), "c"(ext) : "cc", "memory");
1212 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1216 } operand = {eptp, gpa};
1218 asm volatile (__ex(ASM_VMX_INVEPT)
1219 /* CF==1 or ZF==1 --> rc = -1 */
1220 "; ja 1f ; ud2 ; 1:\n"
1221 : : "a" (&operand), "c" (ext) : "cc", "memory");
1224 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1228 i = __find_msr_index(vmx, msr);
1230 return &vmx->guest_msrs[i];
1234 static void vmcs_clear(struct vmcs *vmcs)
1236 u64 phys_addr = __pa(vmcs);
1239 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1240 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1243 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1247 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1249 vmcs_clear(loaded_vmcs->vmcs);
1250 loaded_vmcs->cpu = -1;
1251 loaded_vmcs->launched = 0;
1254 static void vmcs_load(struct vmcs *vmcs)
1256 u64 phys_addr = __pa(vmcs);
1259 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1260 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1263 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1269 * This bitmap is used to indicate whether the vmclear
1270 * operation is enabled on all cpus. All disabled by
1273 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1275 static inline void crash_enable_local_vmclear(int cpu)
1277 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1280 static inline void crash_disable_local_vmclear(int cpu)
1282 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1285 static inline int crash_local_vmclear_enabled(int cpu)
1287 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1290 static void crash_vmclear_local_loaded_vmcss(void)
1292 int cpu = raw_smp_processor_id();
1293 struct loaded_vmcs *v;
1295 if (!crash_local_vmclear_enabled(cpu))
1298 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299 loaded_vmcss_on_cpu_link)
1300 vmcs_clear(v->vmcs);
1303 static inline void crash_enable_local_vmclear(int cpu) { }
1304 static inline void crash_disable_local_vmclear(int cpu) { }
1305 #endif /* CONFIG_KEXEC */
1307 static void __loaded_vmcs_clear(void *arg)
1309 struct loaded_vmcs *loaded_vmcs = arg;
1310 int cpu = raw_smp_processor_id();
1312 if (loaded_vmcs->cpu != cpu)
1313 return; /* vcpu migration can race with cpu offline */
1314 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1315 per_cpu(current_vmcs, cpu) = NULL;
1316 crash_disable_local_vmclear(cpu);
1317 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1320 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321 * is before setting loaded_vmcs->vcpu to -1 which is done in
1322 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323 * then adds the vmcs into percpu list before it is deleted.
1327 loaded_vmcs_init(loaded_vmcs);
1328 crash_enable_local_vmclear(cpu);
1331 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1333 int cpu = loaded_vmcs->cpu;
1336 smp_call_function_single(cpu,
1337 __loaded_vmcs_clear, loaded_vmcs, 1);
1340 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1345 if (cpu_has_vmx_invvpid_single())
1346 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1349 static inline void vpid_sync_vcpu_global(void)
1351 if (cpu_has_vmx_invvpid_global())
1352 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1355 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1357 if (cpu_has_vmx_invvpid_single())
1358 vpid_sync_vcpu_single(vmx);
1360 vpid_sync_vcpu_global();
1363 static inline void ept_sync_global(void)
1365 if (cpu_has_vmx_invept_global())
1366 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1369 static inline void ept_sync_context(u64 eptp)
1372 if (cpu_has_vmx_invept_context())
1373 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1379 static __always_inline unsigned long vmcs_readl(unsigned long field)
1381 unsigned long value;
1383 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384 : "=a"(value) : "d"(field) : "cc");
1388 static __always_inline u16 vmcs_read16(unsigned long field)
1390 return vmcs_readl(field);
1393 static __always_inline u32 vmcs_read32(unsigned long field)
1395 return vmcs_readl(field);
1398 static __always_inline u64 vmcs_read64(unsigned long field)
1400 #ifdef CONFIG_X86_64
1401 return vmcs_readl(field);
1403 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1407 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1409 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1414 static void vmcs_writel(unsigned long field, unsigned long value)
1418 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1419 : "=q"(error) : "a"(value), "d"(field) : "cc");
1420 if (unlikely(error))
1421 vmwrite_error(field, value);
1424 static void vmcs_write16(unsigned long field, u16 value)
1426 vmcs_writel(field, value);
1429 static void vmcs_write32(unsigned long field, u32 value)
1431 vmcs_writel(field, value);
1434 static void vmcs_write64(unsigned long field, u64 value)
1436 vmcs_writel(field, value);
1437 #ifndef CONFIG_X86_64
1439 vmcs_writel(field+1, value >> 32);
1443 static void vmcs_clear_bits(unsigned long field, u32 mask)
1445 vmcs_writel(field, vmcs_readl(field) & ~mask);
1448 static void vmcs_set_bits(unsigned long field, u32 mask)
1450 vmcs_writel(field, vmcs_readl(field) | mask);
1453 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1455 vmcs_write32(VM_ENTRY_CONTROLS, val);
1456 vmx->vm_entry_controls_shadow = val;
1459 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1461 if (vmx->vm_entry_controls_shadow != val)
1462 vm_entry_controls_init(vmx, val);
1465 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1467 return vmx->vm_entry_controls_shadow;
1471 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1473 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1476 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1478 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1481 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1483 vmcs_write32(VM_EXIT_CONTROLS, val);
1484 vmx->vm_exit_controls_shadow = val;
1487 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1489 if (vmx->vm_exit_controls_shadow != val)
1490 vm_exit_controls_init(vmx, val);
1493 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1495 return vmx->vm_exit_controls_shadow;
1499 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1501 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1504 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1506 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1509 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1511 vmx->segment_cache.bitmask = 0;
1514 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1518 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1520 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522 vmx->segment_cache.bitmask = 0;
1524 ret = vmx->segment_cache.bitmask & mask;
1525 vmx->segment_cache.bitmask |= mask;
1529 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1531 u16 *p = &vmx->segment_cache.seg[seg].selector;
1533 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1538 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1540 ulong *p = &vmx->segment_cache.seg[seg].base;
1542 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1547 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1549 u32 *p = &vmx->segment_cache.seg[seg].limit;
1551 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1556 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1558 u32 *p = &vmx->segment_cache.seg[seg].ar;
1560 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1569 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571 if ((vcpu->guest_debug &
1572 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574 eb |= 1u << BP_VECTOR;
1575 if (to_vmx(vcpu)->rmode.vm86_active)
1578 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1579 if (vcpu->fpu_active)
1580 eb &= ~(1u << NM_VECTOR);
1582 /* When we are running a nested L2 guest and L1 specified for it a
1583 * certain exception bitmap, we must trap the same exceptions and pass
1584 * them to L1. When running L2, we will only handle the exceptions
1585 * specified above if L1 did not want them.
1587 if (is_guest_mode(vcpu))
1588 eb |= get_vmcs12(vcpu)->exception_bitmap;
1590 vmcs_write32(EXCEPTION_BITMAP, eb);
1593 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594 unsigned long entry, unsigned long exit)
1596 vm_entry_controls_clearbit(vmx, entry);
1597 vm_exit_controls_clearbit(vmx, exit);
1600 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1603 struct msr_autoload *m = &vmx->msr_autoload;
1607 if (cpu_has_load_ia32_efer) {
1608 clear_atomic_switch_msr_special(vmx,
1609 VM_ENTRY_LOAD_IA32_EFER,
1610 VM_EXIT_LOAD_IA32_EFER);
1614 case MSR_CORE_PERF_GLOBAL_CTRL:
1615 if (cpu_has_load_perf_global_ctrl) {
1616 clear_atomic_switch_msr_special(vmx,
1617 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1624 for (i = 0; i < m->nr; ++i)
1625 if (m->guest[i].index == msr)
1631 m->guest[i] = m->guest[m->nr];
1632 m->host[i] = m->host[m->nr];
1633 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1637 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638 unsigned long entry, unsigned long exit,
1639 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640 u64 guest_val, u64 host_val)
1642 vmcs_write64(guest_val_vmcs, guest_val);
1643 vmcs_write64(host_val_vmcs, host_val);
1644 vm_entry_controls_setbit(vmx, entry);
1645 vm_exit_controls_setbit(vmx, exit);
1648 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649 u64 guest_val, u64 host_val)
1652 struct msr_autoload *m = &vmx->msr_autoload;
1656 if (cpu_has_load_ia32_efer) {
1657 add_atomic_switch_msr_special(vmx,
1658 VM_ENTRY_LOAD_IA32_EFER,
1659 VM_EXIT_LOAD_IA32_EFER,
1662 guest_val, host_val);
1666 case MSR_CORE_PERF_GLOBAL_CTRL:
1667 if (cpu_has_load_perf_global_ctrl) {
1668 add_atomic_switch_msr_special(vmx,
1669 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671 GUEST_IA32_PERF_GLOBAL_CTRL,
1672 HOST_IA32_PERF_GLOBAL_CTRL,
1673 guest_val, host_val);
1679 for (i = 0; i < m->nr; ++i)
1680 if (m->guest[i].index == msr)
1683 if (i == NR_AUTOLOAD_MSRS) {
1684 printk_once(KERN_WARNING "Not enough msr switch entries. "
1685 "Can't add msr %x\n", msr);
1687 } else if (i == m->nr) {
1689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1693 m->guest[i].index = msr;
1694 m->guest[i].value = guest_val;
1695 m->host[i].index = msr;
1696 m->host[i].value = host_val;
1699 static void reload_tss(void)
1702 * VT restores TR but not its size. Useless.
1704 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1705 struct desc_struct *descs;
1707 descs = (void *)gdt->address;
1708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1717 guest_efer = vmx->vcpu.arch.efer;
1720 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1723 ignore_bits = EFER_NX | EFER_SCE;
1724 #ifdef CONFIG_X86_64
1725 ignore_bits |= EFER_LMA | EFER_LME;
1726 /* SCE is meaningful only in long mode on Intel */
1727 if (guest_efer & EFER_LMA)
1728 ignore_bits &= ~(u64)EFER_SCE;
1730 guest_efer &= ~ignore_bits;
1731 guest_efer |= host_efer & ignore_bits;
1732 vmx->guest_msrs[efer_offset].data = guest_efer;
1733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1735 clear_atomic_switch_msr(vmx, MSR_EFER);
1738 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739 * On CPUs that support "load IA32_EFER", always switch EFER
1740 * atomically, since it's faster than switching it manually.
1742 if (cpu_has_load_ia32_efer ||
1743 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1744 guest_efer = vmx->vcpu.arch.efer;
1745 if (!(guest_efer & EFER_LMA))
1746 guest_efer &= ~EFER_LME;
1747 if (guest_efer != host_efer)
1748 add_atomic_switch_msr(vmx, MSR_EFER,
1749 guest_efer, host_efer);
1756 static unsigned long segment_base(u16 selector)
1758 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1759 struct desc_struct *d;
1760 unsigned long table_base;
1763 if (!(selector & ~3))
1766 table_base = gdt->address;
1768 if (selector & 4) { /* from ldt */
1769 u16 ldt_selector = kvm_read_ldt();
1771 if (!(ldt_selector & ~3))
1774 table_base = segment_base(ldt_selector);
1776 d = (struct desc_struct *)(table_base + (selector & ~7));
1777 v = get_desc_base(d);
1778 #ifdef CONFIG_X86_64
1779 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1785 static inline unsigned long kvm_read_tr_base(void)
1788 asm("str %0" : "=g"(tr));
1789 return segment_base(tr);
1792 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1794 struct vcpu_vmx *vmx = to_vmx(vcpu);
1797 if (vmx->host_state.loaded)
1800 vmx->host_state.loaded = 1;
1802 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1803 * allow segment selectors with cpl > 0 or ti == 1.
1805 vmx->host_state.ldt_sel = kvm_read_ldt();
1806 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1807 savesegment(fs, vmx->host_state.fs_sel);
1808 if (!(vmx->host_state.fs_sel & 7)) {
1809 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1810 vmx->host_state.fs_reload_needed = 0;
1812 vmcs_write16(HOST_FS_SELECTOR, 0);
1813 vmx->host_state.fs_reload_needed = 1;
1815 savesegment(gs, vmx->host_state.gs_sel);
1816 if (!(vmx->host_state.gs_sel & 7))
1817 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1819 vmcs_write16(HOST_GS_SELECTOR, 0);
1820 vmx->host_state.gs_ldt_reload_needed = 1;
1823 #ifdef CONFIG_X86_64
1824 savesegment(ds, vmx->host_state.ds_sel);
1825 savesegment(es, vmx->host_state.es_sel);
1828 #ifdef CONFIG_X86_64
1829 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1832 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1836 #ifdef CONFIG_X86_64
1837 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838 if (is_long_mode(&vmx->vcpu))
1839 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1841 if (boot_cpu_has(X86_FEATURE_MPX))
1842 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1843 for (i = 0; i < vmx->save_nmsrs; ++i)
1844 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1845 vmx->guest_msrs[i].data,
1846 vmx->guest_msrs[i].mask);
1849 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1851 if (!vmx->host_state.loaded)
1854 ++vmx->vcpu.stat.host_state_reload;
1855 vmx->host_state.loaded = 0;
1856 #ifdef CONFIG_X86_64
1857 if (is_long_mode(&vmx->vcpu))
1858 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1860 if (vmx->host_state.gs_ldt_reload_needed) {
1861 kvm_load_ldt(vmx->host_state.ldt_sel);
1862 #ifdef CONFIG_X86_64
1863 load_gs_index(vmx->host_state.gs_sel);
1865 loadsegment(gs, vmx->host_state.gs_sel);
1868 if (vmx->host_state.fs_reload_needed)
1869 loadsegment(fs, vmx->host_state.fs_sel);
1870 #ifdef CONFIG_X86_64
1871 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872 loadsegment(ds, vmx->host_state.ds_sel);
1873 loadsegment(es, vmx->host_state.es_sel);
1877 #ifdef CONFIG_X86_64
1878 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1880 if (vmx->host_state.msr_host_bndcfgs)
1881 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1883 * If the FPU is not active (through the host task or
1884 * the guest vcpu), then restore the cr0.TS bit.
1886 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1888 load_gdt(this_cpu_ptr(&host_gdt));
1891 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1894 __vmx_load_host_state(vmx);
1899 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900 * vcpu mutex is already taken.
1902 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1904 struct vcpu_vmx *vmx = to_vmx(vcpu);
1905 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1908 kvm_cpu_vmxon(phys_addr);
1909 else if (vmx->loaded_vmcs->cpu != cpu)
1910 loaded_vmcs_clear(vmx->loaded_vmcs);
1912 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914 vmcs_load(vmx->loaded_vmcs->vmcs);
1917 if (vmx->loaded_vmcs->cpu != cpu) {
1918 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1919 unsigned long sysenter_esp;
1921 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1922 local_irq_disable();
1923 crash_disable_local_vmclear(cpu);
1926 * Read loaded_vmcs->cpu should be before fetching
1927 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928 * See the comments in __loaded_vmcs_clear().
1932 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933 &per_cpu(loaded_vmcss_on_cpu, cpu));
1934 crash_enable_local_vmclear(cpu);
1938 * Linux uses per-cpu TSS and GDT, so set these when switching
1941 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1942 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1944 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1946 vmx->loaded_vmcs->cpu = cpu;
1950 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1952 __vmx_load_host_state(to_vmx(vcpu));
1953 if (!vmm_exclusive) {
1954 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1960 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1964 if (vcpu->fpu_active)
1966 vcpu->fpu_active = 1;
1967 cr0 = vmcs_readl(GUEST_CR0);
1968 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970 vmcs_writel(GUEST_CR0, cr0);
1971 update_exception_bitmap(vcpu);
1972 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1973 if (is_guest_mode(vcpu))
1974 vcpu->arch.cr0_guest_owned_bits &=
1975 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1976 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1979 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1982 * Return the cr0 value that a nested guest would read. This is a combination
1983 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984 * its hypervisor (cr0_read_shadow).
1986 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1988 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1991 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1993 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1997 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1999 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000 * set this *before* calling this function.
2002 vmx_decache_cr0_guest_bits(vcpu);
2003 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2004 update_exception_bitmap(vcpu);
2005 vcpu->arch.cr0_guest_owned_bits = 0;
2006 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2007 if (is_guest_mode(vcpu)) {
2009 * L1's specified read shadow might not contain the TS bit,
2010 * so now that we turned on shadowing of this bit, we need to
2011 * set this bit of the shadow. Like in nested_vmx_run we need
2012 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013 * up-to-date here because we just decached cr0.TS (and we'll
2014 * only update vmcs12->guest_cr0 on nested exit).
2016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018 (vcpu->arch.cr0 & X86_CR0_TS);
2019 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2021 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2024 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2026 unsigned long rflags, save_rflags;
2028 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030 rflags = vmcs_readl(GUEST_RFLAGS);
2031 if (to_vmx(vcpu)->rmode.vm86_active) {
2032 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2036 to_vmx(vcpu)->rflags = rflags;
2038 return to_vmx(vcpu)->rflags;
2041 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2043 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044 to_vmx(vcpu)->rflags = rflags;
2045 if (to_vmx(vcpu)->rmode.vm86_active) {
2046 to_vmx(vcpu)->rmode.save_rflags = rflags;
2047 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2049 vmcs_writel(GUEST_RFLAGS, rflags);
2052 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2054 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2057 if (interruptibility & GUEST_INTR_STATE_STI)
2058 ret |= KVM_X86_SHADOW_INT_STI;
2059 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2060 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2065 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2067 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068 u32 interruptibility = interruptibility_old;
2070 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2072 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2073 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2074 else if (mask & KVM_X86_SHADOW_INT_STI)
2075 interruptibility |= GUEST_INTR_STATE_STI;
2077 if ((interruptibility != interruptibility_old))
2078 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2081 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2085 rip = kvm_rip_read(vcpu);
2086 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2087 kvm_rip_write(vcpu, rip);
2089 /* skipping an emulated instruction also counts */
2090 vmx_set_interrupt_shadow(vcpu, 0);
2094 * KVM wants to inject page-faults which it got to the guest. This function
2095 * checks whether in a nested guest, we need to inject them to L1 or L2.
2097 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2101 if (!(vmcs12->exception_bitmap & (1u << nr)))
2104 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105 vmcs_read32(VM_EXIT_INTR_INFO),
2106 vmcs_readl(EXIT_QUALIFICATION));
2110 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2111 bool has_error_code, u32 error_code,
2114 struct vcpu_vmx *vmx = to_vmx(vcpu);
2115 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2117 if (!reinject && is_guest_mode(vcpu) &&
2118 nested_vmx_check_exception(vcpu, nr))
2121 if (has_error_code) {
2122 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2123 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2126 if (vmx->rmode.vm86_active) {
2128 if (kvm_exception_is_soft(nr))
2129 inc_eip = vcpu->arch.event_exit_inst_len;
2130 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2131 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2135 if (kvm_exception_is_soft(nr)) {
2136 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137 vmx->vcpu.arch.event_exit_inst_len);
2138 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2140 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2142 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2145 static bool vmx_rdtscp_supported(void)
2147 return cpu_has_vmx_rdtscp();
2150 static bool vmx_invpcid_supported(void)
2152 return cpu_has_vmx_invpcid() && enable_ept;
2156 * Swap MSR entry in host/guest MSR entry array.
2158 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2160 struct shared_msr_entry tmp;
2162 tmp = vmx->guest_msrs[to];
2163 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164 vmx->guest_msrs[from] = tmp;
2167 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2169 unsigned long *msr_bitmap;
2171 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2172 if (is_long_mode(vcpu))
2173 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2175 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2177 if (is_long_mode(vcpu))
2178 msr_bitmap = vmx_msr_bitmap_longmode;
2180 msr_bitmap = vmx_msr_bitmap_legacy;
2183 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2187 * Set up the vmcs to automatically save and restore system
2188 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2189 * mode, as fiddling with msrs is very expensive.
2191 static void setup_msrs(struct vcpu_vmx *vmx)
2193 int save_nmsrs, index;
2196 #ifdef CONFIG_X86_64
2197 if (is_long_mode(&vmx->vcpu)) {
2198 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2200 move_msr_up(vmx, index, save_nmsrs++);
2201 index = __find_msr_index(vmx, MSR_LSTAR);
2203 move_msr_up(vmx, index, save_nmsrs++);
2204 index = __find_msr_index(vmx, MSR_CSTAR);
2206 move_msr_up(vmx, index, save_nmsrs++);
2207 index = __find_msr_index(vmx, MSR_TSC_AUX);
2208 if (index >= 0 && vmx->rdtscp_enabled)
2209 move_msr_up(vmx, index, save_nmsrs++);
2211 * MSR_STAR is only needed on long mode guests, and only
2212 * if efer.sce is enabled.
2214 index = __find_msr_index(vmx, MSR_STAR);
2215 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2216 move_msr_up(vmx, index, save_nmsrs++);
2219 index = __find_msr_index(vmx, MSR_EFER);
2220 if (index >= 0 && update_transition_efer(vmx, index))
2221 move_msr_up(vmx, index, save_nmsrs++);
2223 vmx->save_nmsrs = save_nmsrs;
2225 if (cpu_has_vmx_msr_bitmap())
2226 vmx_set_msr_bitmap(&vmx->vcpu);
2230 * reads and returns guest's timestamp counter "register"
2231 * guest_tsc = host_tsc + tsc_offset -- 21.3
2233 static u64 guest_read_tsc(void)
2235 u64 host_tsc, tsc_offset;
2238 tsc_offset = vmcs_read64(TSC_OFFSET);
2239 return host_tsc + tsc_offset;
2243 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2244 * counter, even if a nested guest (L2) is currently running.
2246 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2250 tsc_offset = is_guest_mode(vcpu) ?
2251 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2252 vmcs_read64(TSC_OFFSET);
2253 return host_tsc + tsc_offset;
2257 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2258 * software catchup for faster rates on slower CPUs.
2260 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2265 if (user_tsc_khz > tsc_khz) {
2266 vcpu->arch.tsc_catchup = 1;
2267 vcpu->arch.tsc_always_catchup = 1;
2269 WARN(1, "user requested TSC rate below hardware speed\n");
2272 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2274 return vmcs_read64(TSC_OFFSET);
2278 * writes 'offset' into guest's timestamp counter offset register
2280 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2282 if (is_guest_mode(vcpu)) {
2284 * We're here if L1 chose not to trap WRMSR to TSC. According
2285 * to the spec, this should set L1's TSC; The offset that L1
2286 * set for L2 remains unchanged, and still needs to be added
2287 * to the newly set TSC to get L2's TSC.
2289 struct vmcs12 *vmcs12;
2290 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2291 /* recalculate vmcs02.TSC_OFFSET: */
2292 vmcs12 = get_vmcs12(vcpu);
2293 vmcs_write64(TSC_OFFSET, offset +
2294 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2295 vmcs12->tsc_offset : 0));
2297 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2298 vmcs_read64(TSC_OFFSET), offset);
2299 vmcs_write64(TSC_OFFSET, offset);
2303 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2305 u64 offset = vmcs_read64(TSC_OFFSET);
2307 vmcs_write64(TSC_OFFSET, offset + adjustment);
2308 if (is_guest_mode(vcpu)) {
2309 /* Even when running L2, the adjustment needs to apply to L1 */
2310 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2312 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2313 offset + adjustment);
2316 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2318 return target_tsc - native_read_tsc();
2321 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2323 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2324 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2328 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2329 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2330 * all guests if the "nested" module option is off, and can also be disabled
2331 * for a single guest by disabling its VMX cpuid bit.
2333 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2335 return nested && guest_cpuid_has_vmx(vcpu);
2339 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2340 * returned for the various VMX controls MSRs when nested VMX is enabled.
2341 * The same values should also be used to verify that vmcs12 control fields are
2342 * valid during nested entry from L1 to L2.
2343 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2344 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2345 * bit in the high half is on if the corresponding bit in the control field
2346 * may be on. See also vmx_control_verify().
2348 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2351 * Note that as a general rule, the high half of the MSRs (bits in
2352 * the control fields which may be 1) should be initialized by the
2353 * intersection of the underlying hardware's MSR (i.e., features which
2354 * can be supported) and the list of features we want to expose -
2355 * because they are known to be properly supported in our code.
2356 * Also, usually, the low half of the MSRs (bits which must be 1) can
2357 * be set to 0, meaning that L1 may turn off any of these bits. The
2358 * reason is that if one of these bits is necessary, it will appear
2359 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2360 * fields of vmcs01 and vmcs02, will turn these bits off - and
2361 * nested_vmx_exit_handled() will not pass related exits to L1.
2362 * These rules have exceptions below.
2365 /* pin-based controls */
2366 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2367 vmx->nested.nested_vmx_pinbased_ctls_low,
2368 vmx->nested.nested_vmx_pinbased_ctls_high);
2369 vmx->nested.nested_vmx_pinbased_ctls_low |=
2370 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2371 vmx->nested.nested_vmx_pinbased_ctls_high &=
2372 PIN_BASED_EXT_INTR_MASK |
2373 PIN_BASED_NMI_EXITING |
2374 PIN_BASED_VIRTUAL_NMIS;
2375 vmx->nested.nested_vmx_pinbased_ctls_high |=
2376 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2377 PIN_BASED_VMX_PREEMPTION_TIMER;
2378 if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2379 vmx->nested.nested_vmx_pinbased_ctls_high |=
2380 PIN_BASED_POSTED_INTR;
2383 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2384 vmx->nested.nested_vmx_exit_ctls_low,
2385 vmx->nested.nested_vmx_exit_ctls_high);
2386 vmx->nested.nested_vmx_exit_ctls_low =
2387 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2389 vmx->nested.nested_vmx_exit_ctls_high &=
2390 #ifdef CONFIG_X86_64
2391 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2393 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2394 vmx->nested.nested_vmx_exit_ctls_high |=
2395 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2396 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2397 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2399 if (vmx_mpx_supported())
2400 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2402 /* We support free control of debug control saving. */
2403 vmx->nested.nested_vmx_true_exit_ctls_low =
2404 vmx->nested.nested_vmx_exit_ctls_low &
2405 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2407 /* entry controls */
2408 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2409 vmx->nested.nested_vmx_entry_ctls_low,
2410 vmx->nested.nested_vmx_entry_ctls_high);
2411 vmx->nested.nested_vmx_entry_ctls_low =
2412 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2413 vmx->nested.nested_vmx_entry_ctls_high &=
2414 #ifdef CONFIG_X86_64
2415 VM_ENTRY_IA32E_MODE |
2417 VM_ENTRY_LOAD_IA32_PAT;
2418 vmx->nested.nested_vmx_entry_ctls_high |=
2419 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2420 if (vmx_mpx_supported())
2421 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2423 /* We support free control of debug control loading. */
2424 vmx->nested.nested_vmx_true_entry_ctls_low =
2425 vmx->nested.nested_vmx_entry_ctls_low &
2426 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2428 /* cpu-based controls */
2429 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2430 vmx->nested.nested_vmx_procbased_ctls_low,
2431 vmx->nested.nested_vmx_procbased_ctls_high);
2432 vmx->nested.nested_vmx_procbased_ctls_low =
2433 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2434 vmx->nested.nested_vmx_procbased_ctls_high &=
2435 CPU_BASED_VIRTUAL_INTR_PENDING |
2436 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2437 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2438 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2439 CPU_BASED_CR3_STORE_EXITING |
2440 #ifdef CONFIG_X86_64
2441 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2443 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2444 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2445 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2446 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2447 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2449 * We can allow some features even when not supported by the
2450 * hardware. For example, L1 can specify an MSR bitmap - and we
2451 * can use it to avoid exits to L1 - even when L0 runs L2
2452 * without MSR bitmaps.
2454 vmx->nested.nested_vmx_procbased_ctls_high |=
2455 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2456 CPU_BASED_USE_MSR_BITMAPS;
2458 /* We support free control of CR3 access interception. */
2459 vmx->nested.nested_vmx_true_procbased_ctls_low =
2460 vmx->nested.nested_vmx_procbased_ctls_low &
2461 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2463 /* secondary cpu-based controls */
2464 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2465 vmx->nested.nested_vmx_secondary_ctls_low,
2466 vmx->nested.nested_vmx_secondary_ctls_high);
2467 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2468 vmx->nested.nested_vmx_secondary_ctls_high &=
2469 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2470 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2471 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2472 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2473 SECONDARY_EXEC_WBINVD_EXITING |
2474 SECONDARY_EXEC_XSAVES;
2477 /* nested EPT: emulate EPT also to L1 */
2478 vmx->nested.nested_vmx_secondary_ctls_high |=
2479 SECONDARY_EXEC_ENABLE_EPT |
2480 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2481 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2482 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2484 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2486 * For nested guests, we don't do anything specific
2487 * for single context invalidation. Hence, only advertise
2488 * support for global context invalidation.
2490 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2492 vmx->nested.nested_vmx_ept_caps = 0;
2494 /* miscellaneous data */
2495 rdmsr(MSR_IA32_VMX_MISC,
2496 vmx->nested.nested_vmx_misc_low,
2497 vmx->nested.nested_vmx_misc_high);
2498 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2499 vmx->nested.nested_vmx_misc_low |=
2500 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2501 VMX_MISC_ACTIVITY_HLT;
2502 vmx->nested.nested_vmx_misc_high = 0;
2505 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2508 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2510 return ((control & high) | low) == control;
2513 static inline u64 vmx_control_msr(u32 low, u32 high)
2515 return low | ((u64)high << 32);
2518 /* Returns 0 on success, non-0 otherwise. */
2519 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2521 struct vcpu_vmx *vmx = to_vmx(vcpu);
2523 switch (msr_index) {
2524 case MSR_IA32_VMX_BASIC:
2526 * This MSR reports some information about VMX support. We
2527 * should return information about the VMX we emulate for the
2528 * guest, and the VMCS structure we give it - not about the
2529 * VMX support of the underlying hardware.
2531 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2532 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2533 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2535 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2536 case MSR_IA32_VMX_PINBASED_CTLS:
2537 *pdata = vmx_control_msr(
2538 vmx->nested.nested_vmx_pinbased_ctls_low,
2539 vmx->nested.nested_vmx_pinbased_ctls_high);
2541 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2542 *pdata = vmx_control_msr(
2543 vmx->nested.nested_vmx_true_procbased_ctls_low,
2544 vmx->nested.nested_vmx_procbased_ctls_high);
2546 case MSR_IA32_VMX_PROCBASED_CTLS:
2547 *pdata = vmx_control_msr(
2548 vmx->nested.nested_vmx_procbased_ctls_low,
2549 vmx->nested.nested_vmx_procbased_ctls_high);
2551 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2552 *pdata = vmx_control_msr(
2553 vmx->nested.nested_vmx_true_exit_ctls_low,
2554 vmx->nested.nested_vmx_exit_ctls_high);
2556 case MSR_IA32_VMX_EXIT_CTLS:
2557 *pdata = vmx_control_msr(
2558 vmx->nested.nested_vmx_exit_ctls_low,
2559 vmx->nested.nested_vmx_exit_ctls_high);
2561 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2562 *pdata = vmx_control_msr(
2563 vmx->nested.nested_vmx_true_entry_ctls_low,
2564 vmx->nested.nested_vmx_entry_ctls_high);
2566 case MSR_IA32_VMX_ENTRY_CTLS:
2567 *pdata = vmx_control_msr(
2568 vmx->nested.nested_vmx_entry_ctls_low,
2569 vmx->nested.nested_vmx_entry_ctls_high);
2571 case MSR_IA32_VMX_MISC:
2572 *pdata = vmx_control_msr(
2573 vmx->nested.nested_vmx_misc_low,
2574 vmx->nested.nested_vmx_misc_high);
2577 * These MSRs specify bits which the guest must keep fixed (on or off)
2578 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2579 * We picked the standard core2 setting.
2581 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2582 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2583 case MSR_IA32_VMX_CR0_FIXED0:
2584 *pdata = VMXON_CR0_ALWAYSON;
2586 case MSR_IA32_VMX_CR0_FIXED1:
2589 case MSR_IA32_VMX_CR4_FIXED0:
2590 *pdata = VMXON_CR4_ALWAYSON;
2592 case MSR_IA32_VMX_CR4_FIXED1:
2595 case MSR_IA32_VMX_VMCS_ENUM:
2596 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2598 case MSR_IA32_VMX_PROCBASED_CTLS2:
2599 *pdata = vmx_control_msr(
2600 vmx->nested.nested_vmx_secondary_ctls_low,
2601 vmx->nested.nested_vmx_secondary_ctls_high);
2603 case MSR_IA32_VMX_EPT_VPID_CAP:
2604 /* Currently, no nested vpid support */
2605 *pdata = vmx->nested.nested_vmx_ept_caps;
2615 * Reads an msr value (of 'msr_index') into 'pdata'.
2616 * Returns 0 on success, non-0 otherwise.
2617 * Assumes vcpu_load() was already called.
2619 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2622 struct shared_msr_entry *msr;
2625 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2629 switch (msr_index) {
2630 #ifdef CONFIG_X86_64
2632 data = vmcs_readl(GUEST_FS_BASE);
2635 data = vmcs_readl(GUEST_GS_BASE);
2637 case MSR_KERNEL_GS_BASE:
2638 vmx_load_host_state(to_vmx(vcpu));
2639 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2643 return kvm_get_msr_common(vcpu, msr_index, pdata);
2645 data = guest_read_tsc();
2647 case MSR_IA32_SYSENTER_CS:
2648 data = vmcs_read32(GUEST_SYSENTER_CS);
2650 case MSR_IA32_SYSENTER_EIP:
2651 data = vmcs_readl(GUEST_SYSENTER_EIP);
2653 case MSR_IA32_SYSENTER_ESP:
2654 data = vmcs_readl(GUEST_SYSENTER_ESP);
2656 case MSR_IA32_BNDCFGS:
2657 if (!vmx_mpx_supported())
2659 data = vmcs_read64(GUEST_BNDCFGS);
2661 case MSR_IA32_FEATURE_CONTROL:
2662 if (!nested_vmx_allowed(vcpu))
2664 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2666 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2667 if (!nested_vmx_allowed(vcpu))
2669 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2671 if (!vmx_xsaves_supported())
2673 data = vcpu->arch.ia32_xss;
2676 if (!to_vmx(vcpu)->rdtscp_enabled)
2678 /* Otherwise falls through */
2680 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2685 return kvm_get_msr_common(vcpu, msr_index, pdata);
2692 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2695 * Writes msr value into into the appropriate "register".
2696 * Returns 0 on success, non-0 otherwise.
2697 * Assumes vcpu_load() was already called.
2699 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2701 struct vcpu_vmx *vmx = to_vmx(vcpu);
2702 struct shared_msr_entry *msr;
2704 u32 msr_index = msr_info->index;
2705 u64 data = msr_info->data;
2707 switch (msr_index) {
2709 ret = kvm_set_msr_common(vcpu, msr_info);
2711 #ifdef CONFIG_X86_64
2713 vmx_segment_cache_clear(vmx);
2714 vmcs_writel(GUEST_FS_BASE, data);
2717 vmx_segment_cache_clear(vmx);
2718 vmcs_writel(GUEST_GS_BASE, data);
2720 case MSR_KERNEL_GS_BASE:
2721 vmx_load_host_state(vmx);
2722 vmx->msr_guest_kernel_gs_base = data;
2725 case MSR_IA32_SYSENTER_CS:
2726 vmcs_write32(GUEST_SYSENTER_CS, data);
2728 case MSR_IA32_SYSENTER_EIP:
2729 vmcs_writel(GUEST_SYSENTER_EIP, data);
2731 case MSR_IA32_SYSENTER_ESP:
2732 vmcs_writel(GUEST_SYSENTER_ESP, data);
2734 case MSR_IA32_BNDCFGS:
2735 if (!vmx_mpx_supported())
2737 vmcs_write64(GUEST_BNDCFGS, data);
2740 kvm_write_tsc(vcpu, msr_info);
2742 case MSR_IA32_CR_PAT:
2743 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2744 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2746 vmcs_write64(GUEST_IA32_PAT, data);
2747 vcpu->arch.pat = data;
2750 ret = kvm_set_msr_common(vcpu, msr_info);
2752 case MSR_IA32_TSC_ADJUST:
2753 ret = kvm_set_msr_common(vcpu, msr_info);
2755 case MSR_IA32_FEATURE_CONTROL:
2756 if (!nested_vmx_allowed(vcpu) ||
2757 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2758 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2760 vmx->nested.msr_ia32_feature_control = data;
2761 if (msr_info->host_initiated && data == 0)
2762 vmx_leave_nested(vcpu);
2764 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2765 return 1; /* they are read-only */
2767 if (!vmx_xsaves_supported())
2770 * The only supported bit as of Skylake is bit 8, but
2771 * it is not supported on KVM.
2775 vcpu->arch.ia32_xss = data;
2776 if (vcpu->arch.ia32_xss != host_xss)
2777 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2778 vcpu->arch.ia32_xss, host_xss);
2780 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2783 if (!vmx->rdtscp_enabled)
2785 /* Check reserved bit, higher 32 bits should be zero */
2786 if ((data >> 32) != 0)
2788 /* Otherwise falls through */
2790 msr = find_msr_entry(vmx, msr_index);
2792 u64 old_msr_data = msr->data;
2794 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2796 ret = kvm_set_shared_msr(msr->index, msr->data,
2800 msr->data = old_msr_data;
2804 ret = kvm_set_msr_common(vcpu, msr_info);
2810 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2812 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2815 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2818 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2820 case VCPU_EXREG_PDPTR:
2822 ept_save_pdptrs(vcpu);
2829 static __init int cpu_has_kvm_support(void)
2831 return cpu_has_vmx();
2834 static __init int vmx_disabled_by_bios(void)
2838 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2839 if (msr & FEATURE_CONTROL_LOCKED) {
2840 /* launched w/ TXT and VMX disabled */
2841 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2844 /* launched w/o TXT and VMX only enabled w/ TXT */
2845 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2846 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2847 && !tboot_enabled()) {
2848 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2849 "activate TXT before enabling KVM\n");
2852 /* launched w/o TXT and VMX disabled */
2853 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2854 && !tboot_enabled())
2861 static void kvm_cpu_vmxon(u64 addr)
2863 asm volatile (ASM_VMX_VMXON_RAX
2864 : : "a"(&addr), "m"(addr)
2868 static int hardware_enable(void)
2870 int cpu = raw_smp_processor_id();
2871 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2874 if (cr4_read_shadow() & X86_CR4_VMXE)
2877 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2880 * Now we can enable the vmclear operation in kdump
2881 * since the loaded_vmcss_on_cpu list on this cpu
2882 * has been initialized.
2884 * Though the cpu is not in VMX operation now, there
2885 * is no problem to enable the vmclear operation
2886 * for the loaded_vmcss_on_cpu list is empty!
2888 crash_enable_local_vmclear(cpu);
2890 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2892 test_bits = FEATURE_CONTROL_LOCKED;
2893 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2894 if (tboot_enabled())
2895 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2897 if ((old & test_bits) != test_bits) {
2898 /* enable and lock */
2899 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2901 cr4_set_bits(X86_CR4_VMXE);
2903 if (vmm_exclusive) {
2904 kvm_cpu_vmxon(phys_addr);
2908 native_store_gdt(this_cpu_ptr(&host_gdt));
2913 static void vmclear_local_loaded_vmcss(void)
2915 int cpu = raw_smp_processor_id();
2916 struct loaded_vmcs *v, *n;
2918 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2919 loaded_vmcss_on_cpu_link)
2920 __loaded_vmcs_clear(v);
2924 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2927 static void kvm_cpu_vmxoff(void)
2929 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2932 static void hardware_disable(void)
2934 if (vmm_exclusive) {
2935 vmclear_local_loaded_vmcss();
2938 cr4_clear_bits(X86_CR4_VMXE);
2941 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2942 u32 msr, u32 *result)
2944 u32 vmx_msr_low, vmx_msr_high;
2945 u32 ctl = ctl_min | ctl_opt;
2947 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2949 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2950 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2952 /* Ensure minimum (required) set of control bits are supported. */
2960 static __init bool allow_1_setting(u32 msr, u32 ctl)
2962 u32 vmx_msr_low, vmx_msr_high;
2964 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2965 return vmx_msr_high & ctl;
2968 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2970 u32 vmx_msr_low, vmx_msr_high;
2971 u32 min, opt, min2, opt2;
2972 u32 _pin_based_exec_control = 0;
2973 u32 _cpu_based_exec_control = 0;
2974 u32 _cpu_based_2nd_exec_control = 0;
2975 u32 _vmexit_control = 0;
2976 u32 _vmentry_control = 0;
2978 min = CPU_BASED_HLT_EXITING |
2979 #ifdef CONFIG_X86_64
2980 CPU_BASED_CR8_LOAD_EXITING |
2981 CPU_BASED_CR8_STORE_EXITING |
2983 CPU_BASED_CR3_LOAD_EXITING |
2984 CPU_BASED_CR3_STORE_EXITING |
2985 CPU_BASED_USE_IO_BITMAPS |
2986 CPU_BASED_MOV_DR_EXITING |
2987 CPU_BASED_USE_TSC_OFFSETING |
2988 CPU_BASED_MWAIT_EXITING |
2989 CPU_BASED_MONITOR_EXITING |
2990 CPU_BASED_INVLPG_EXITING |
2991 CPU_BASED_RDPMC_EXITING;
2993 opt = CPU_BASED_TPR_SHADOW |
2994 CPU_BASED_USE_MSR_BITMAPS |
2995 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2996 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2997 &_cpu_based_exec_control) < 0)
2999 #ifdef CONFIG_X86_64
3000 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3001 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3002 ~CPU_BASED_CR8_STORE_EXITING;
3004 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3006 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3007 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3008 SECONDARY_EXEC_WBINVD_EXITING |
3009 SECONDARY_EXEC_ENABLE_VPID |
3010 SECONDARY_EXEC_ENABLE_EPT |
3011 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3012 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3013 SECONDARY_EXEC_RDTSCP |
3014 SECONDARY_EXEC_ENABLE_INVPCID |
3015 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3016 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3017 SECONDARY_EXEC_SHADOW_VMCS |
3018 SECONDARY_EXEC_XSAVES |
3019 SECONDARY_EXEC_ENABLE_PML;
3020 if (adjust_vmx_controls(min2, opt2,
3021 MSR_IA32_VMX_PROCBASED_CTLS2,
3022 &_cpu_based_2nd_exec_control) < 0)
3025 #ifndef CONFIG_X86_64
3026 if (!(_cpu_based_2nd_exec_control &
3027 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3028 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3031 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3032 _cpu_based_2nd_exec_control &= ~(
3033 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3034 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3035 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3037 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3038 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3040 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3041 CPU_BASED_CR3_STORE_EXITING |
3042 CPU_BASED_INVLPG_EXITING);
3043 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3044 vmx_capability.ept, vmx_capability.vpid);
3047 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3048 #ifdef CONFIG_X86_64
3049 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3051 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3052 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3053 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3054 &_vmexit_control) < 0)
3057 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3058 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3059 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3060 &_pin_based_exec_control) < 0)
3063 if (!(_cpu_based_2nd_exec_control &
3064 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3065 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3066 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3068 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3069 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3070 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3071 &_vmentry_control) < 0)
3074 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3076 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3077 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3080 #ifdef CONFIG_X86_64
3081 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3082 if (vmx_msr_high & (1u<<16))
3086 /* Require Write-Back (WB) memory type for VMCS accesses. */
3087 if (((vmx_msr_high >> 18) & 15) != 6)
3090 vmcs_conf->size = vmx_msr_high & 0x1fff;
3091 vmcs_conf->order = get_order(vmcs_config.size);
3092 vmcs_conf->revision_id = vmx_msr_low;
3094 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3095 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3096 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3097 vmcs_conf->vmexit_ctrl = _vmexit_control;
3098 vmcs_conf->vmentry_ctrl = _vmentry_control;
3100 cpu_has_load_ia32_efer =
3101 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3102 VM_ENTRY_LOAD_IA32_EFER)
3103 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3104 VM_EXIT_LOAD_IA32_EFER);
3106 cpu_has_load_perf_global_ctrl =
3107 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3108 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3109 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3110 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3113 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3114 * but due to arrata below it can't be used. Workaround is to use
3115 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3117 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3122 * BC86,AAY89,BD102 (model 44)
3126 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3127 switch (boot_cpu_data.x86_model) {
3133 cpu_has_load_perf_global_ctrl = false;
3134 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3135 "does not work properly. Using workaround\n");
3143 rdmsrl(MSR_IA32_XSS, host_xss);
3148 static struct vmcs *alloc_vmcs_cpu(int cpu)
3150 int node = cpu_to_node(cpu);
3154 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3157 vmcs = page_address(pages);
3158 memset(vmcs, 0, vmcs_config.size);
3159 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3163 static struct vmcs *alloc_vmcs(void)
3165 return alloc_vmcs_cpu(raw_smp_processor_id());
3168 static void free_vmcs(struct vmcs *vmcs)
3170 free_pages((unsigned long)vmcs, vmcs_config.order);
3174 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3176 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3178 if (!loaded_vmcs->vmcs)
3180 loaded_vmcs_clear(loaded_vmcs);
3181 free_vmcs(loaded_vmcs->vmcs);
3182 loaded_vmcs->vmcs = NULL;
3185 static void free_kvm_area(void)
3189 for_each_possible_cpu(cpu) {
3190 free_vmcs(per_cpu(vmxarea, cpu));
3191 per_cpu(vmxarea, cpu) = NULL;
3195 static void init_vmcs_shadow_fields(void)
3199 /* No checks for read only fields yet */
3201 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3202 switch (shadow_read_write_fields[i]) {
3204 if (!vmx_mpx_supported())
3212 shadow_read_write_fields[j] =
3213 shadow_read_write_fields[i];
3216 max_shadow_read_write_fields = j;
3218 /* shadowed fields guest access without vmexit */
3219 for (i = 0; i < max_shadow_read_write_fields; i++) {
3220 clear_bit(shadow_read_write_fields[i],
3221 vmx_vmwrite_bitmap);
3222 clear_bit(shadow_read_write_fields[i],
3225 for (i = 0; i < max_shadow_read_only_fields; i++)
3226 clear_bit(shadow_read_only_fields[i],
3230 static __init int alloc_kvm_area(void)
3234 for_each_possible_cpu(cpu) {
3237 vmcs = alloc_vmcs_cpu(cpu);
3243 per_cpu(vmxarea, cpu) = vmcs;
3248 static bool emulation_required(struct kvm_vcpu *vcpu)
3250 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3253 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3254 struct kvm_segment *save)
3256 if (!emulate_invalid_guest_state) {
3258 * CS and SS RPL should be equal during guest entry according
3259 * to VMX spec, but in reality it is not always so. Since vcpu
3260 * is in the middle of the transition from real mode to
3261 * protected mode it is safe to assume that RPL 0 is a good
3264 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3265 save->selector &= ~SELECTOR_RPL_MASK;
3266 save->dpl = save->selector & SELECTOR_RPL_MASK;
3269 vmx_set_segment(vcpu, save, seg);
3272 static void enter_pmode(struct kvm_vcpu *vcpu)
3274 unsigned long flags;
3275 struct vcpu_vmx *vmx = to_vmx(vcpu);
3278 * Update real mode segment cache. It may be not up-to-date if sement
3279 * register was written while vcpu was in a guest mode.
3281 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3282 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3283 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3284 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3285 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3286 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3288 vmx->rmode.vm86_active = 0;
3290 vmx_segment_cache_clear(vmx);
3292 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3294 flags = vmcs_readl(GUEST_RFLAGS);
3295 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3296 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3297 vmcs_writel(GUEST_RFLAGS, flags);
3299 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3300 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3302 update_exception_bitmap(vcpu);
3304 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3305 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3306 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3307 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3308 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3309 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3312 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3314 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3315 struct kvm_segment var = *save;
3318 if (seg == VCPU_SREG_CS)
3321 if (!emulate_invalid_guest_state) {
3322 var.selector = var.base >> 4;
3323 var.base = var.base & 0xffff0;
3333 if (save->base & 0xf)
3334 printk_once(KERN_WARNING "kvm: segment base is not "
3335 "paragraph aligned when entering "
3336 "protected mode (seg=%d)", seg);
3339 vmcs_write16(sf->selector, var.selector);
3340 vmcs_write32(sf->base, var.base);
3341 vmcs_write32(sf->limit, var.limit);
3342 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3345 static void enter_rmode(struct kvm_vcpu *vcpu)
3347 unsigned long flags;
3348 struct vcpu_vmx *vmx = to_vmx(vcpu);
3350 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3351 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3352 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3353 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3354 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3355 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3356 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3358 vmx->rmode.vm86_active = 1;
3361 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3362 * vcpu. Warn the user that an update is overdue.
3364 if (!vcpu->kvm->arch.tss_addr)
3365 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3366 "called before entering vcpu\n");
3368 vmx_segment_cache_clear(vmx);
3370 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3371 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3372 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3374 flags = vmcs_readl(GUEST_RFLAGS);
3375 vmx->rmode.save_rflags = flags;
3377 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3379 vmcs_writel(GUEST_RFLAGS, flags);
3380 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3381 update_exception_bitmap(vcpu);
3383 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3384 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3385 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3386 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3387 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3388 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3390 kvm_mmu_reset_context(vcpu);
3393 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3395 struct vcpu_vmx *vmx = to_vmx(vcpu);
3396 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3402 * Force kernel_gs_base reloading before EFER changes, as control
3403 * of this msr depends on is_long_mode().
3405 vmx_load_host_state(to_vmx(vcpu));
3406 vcpu->arch.efer = efer;
3407 if (efer & EFER_LMA) {
3408 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3411 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3413 msr->data = efer & ~EFER_LME;
3418 #ifdef CONFIG_X86_64
3420 static void enter_lmode(struct kvm_vcpu *vcpu)
3424 vmx_segment_cache_clear(to_vmx(vcpu));
3426 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3427 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3428 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3430 vmcs_write32(GUEST_TR_AR_BYTES,
3431 (guest_tr_ar & ~AR_TYPE_MASK)
3432 | AR_TYPE_BUSY_64_TSS);
3434 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3437 static void exit_lmode(struct kvm_vcpu *vcpu)
3439 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3440 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3445 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3447 vpid_sync_context(to_vmx(vcpu));
3449 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3451 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3455 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3457 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3459 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3460 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3463 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3465 if (enable_ept && is_paging(vcpu))
3466 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3467 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3470 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3472 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3474 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3475 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3478 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3480 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3482 if (!test_bit(VCPU_EXREG_PDPTR,
3483 (unsigned long *)&vcpu->arch.regs_dirty))
3486 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3487 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3488 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3489 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3490 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3494 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3496 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3498 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3499 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3500 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3501 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3502 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3505 __set_bit(VCPU_EXREG_PDPTR,
3506 (unsigned long *)&vcpu->arch.regs_avail);
3507 __set_bit(VCPU_EXREG_PDPTR,
3508 (unsigned long *)&vcpu->arch.regs_dirty);
3511 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3513 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3515 struct kvm_vcpu *vcpu)
3517 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3518 vmx_decache_cr3(vcpu);
3519 if (!(cr0 & X86_CR0_PG)) {
3520 /* From paging/starting to nonpaging */
3521 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3522 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3523 (CPU_BASED_CR3_LOAD_EXITING |
3524 CPU_BASED_CR3_STORE_EXITING));
3525 vcpu->arch.cr0 = cr0;
3526 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3527 } else if (!is_paging(vcpu)) {
3528 /* From nonpaging to paging */
3529 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3530 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3531 ~(CPU_BASED_CR3_LOAD_EXITING |
3532 CPU_BASED_CR3_STORE_EXITING));
3533 vcpu->arch.cr0 = cr0;
3534 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3537 if (!(cr0 & X86_CR0_WP))
3538 *hw_cr0 &= ~X86_CR0_WP;
3541 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3543 struct vcpu_vmx *vmx = to_vmx(vcpu);
3544 unsigned long hw_cr0;
3546 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3547 if (enable_unrestricted_guest)
3548 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3550 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3552 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3555 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3559 #ifdef CONFIG_X86_64
3560 if (vcpu->arch.efer & EFER_LME) {
3561 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3563 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3569 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3571 if (!vcpu->fpu_active)
3572 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3574 vmcs_writel(CR0_READ_SHADOW, cr0);
3575 vmcs_writel(GUEST_CR0, hw_cr0);
3576 vcpu->arch.cr0 = cr0;
3578 /* depends on vcpu->arch.cr0 to be set to a new value */
3579 vmx->emulation_required = emulation_required(vcpu);
3582 static u64 construct_eptp(unsigned long root_hpa)
3586 /* TODO write the value reading from MSR */
3587 eptp = VMX_EPT_DEFAULT_MT |
3588 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3589 if (enable_ept_ad_bits)
3590 eptp |= VMX_EPT_AD_ENABLE_BIT;
3591 eptp |= (root_hpa & PAGE_MASK);
3596 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3598 unsigned long guest_cr3;
3603 eptp = construct_eptp(cr3);
3604 vmcs_write64(EPT_POINTER, eptp);
3605 if (is_paging(vcpu) || is_guest_mode(vcpu))
3606 guest_cr3 = kvm_read_cr3(vcpu);
3608 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3609 ept_load_pdptrs(vcpu);
3612 vmx_flush_tlb(vcpu);
3613 vmcs_writel(GUEST_CR3, guest_cr3);
3616 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3618 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3619 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3621 if (cr4 & X86_CR4_VMXE) {
3623 * To use VMXON (and later other VMX instructions), a guest
3624 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3625 * So basically the check on whether to allow nested VMX
3628 if (!nested_vmx_allowed(vcpu))
3631 if (to_vmx(vcpu)->nested.vmxon &&
3632 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3635 vcpu->arch.cr4 = cr4;
3637 if (!is_paging(vcpu)) {
3638 hw_cr4 &= ~X86_CR4_PAE;
3639 hw_cr4 |= X86_CR4_PSE;
3641 * SMEP/SMAP is disabled if CPU is in non-paging mode
3642 * in hardware. However KVM always uses paging mode to
3643 * emulate guest non-paging mode with TDP.
3644 * To emulate this behavior, SMEP/SMAP needs to be
3645 * manually disabled when guest switches to non-paging
3648 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3649 } else if (!(cr4 & X86_CR4_PAE)) {
3650 hw_cr4 &= ~X86_CR4_PAE;
3654 vmcs_writel(CR4_READ_SHADOW, cr4);
3655 vmcs_writel(GUEST_CR4, hw_cr4);
3659 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3660 struct kvm_segment *var, int seg)
3662 struct vcpu_vmx *vmx = to_vmx(vcpu);
3665 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3666 *var = vmx->rmode.segs[seg];
3667 if (seg == VCPU_SREG_TR
3668 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3670 var->base = vmx_read_guest_seg_base(vmx, seg);
3671 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3674 var->base = vmx_read_guest_seg_base(vmx, seg);
3675 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3676 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3677 ar = vmx_read_guest_seg_ar(vmx, seg);
3678 var->unusable = (ar >> 16) & 1;
3679 var->type = ar & 15;
3680 var->s = (ar >> 4) & 1;
3681 var->dpl = (ar >> 5) & 3;
3683 * Some userspaces do not preserve unusable property. Since usable
3684 * segment has to be present according to VMX spec we can use present
3685 * property to amend userspace bug by making unusable segment always
3686 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3687 * segment as unusable.
3689 var->present = !var->unusable;
3690 var->avl = (ar >> 12) & 1;
3691 var->l = (ar >> 13) & 1;
3692 var->db = (ar >> 14) & 1;
3693 var->g = (ar >> 15) & 1;
3696 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3698 struct kvm_segment s;
3700 if (to_vmx(vcpu)->rmode.vm86_active) {
3701 vmx_get_segment(vcpu, &s, seg);
3704 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3707 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3709 struct vcpu_vmx *vmx = to_vmx(vcpu);
3711 if (unlikely(vmx->rmode.vm86_active))
3714 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3719 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3723 if (var->unusable || !var->present)
3726 ar = var->type & 15;
3727 ar |= (var->s & 1) << 4;
3728 ar |= (var->dpl & 3) << 5;
3729 ar |= (var->present & 1) << 7;
3730 ar |= (var->avl & 1) << 12;
3731 ar |= (var->l & 1) << 13;
3732 ar |= (var->db & 1) << 14;
3733 ar |= (var->g & 1) << 15;
3739 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3740 struct kvm_segment *var, int seg)
3742 struct vcpu_vmx *vmx = to_vmx(vcpu);
3743 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3745 vmx_segment_cache_clear(vmx);
3747 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3748 vmx->rmode.segs[seg] = *var;
3749 if (seg == VCPU_SREG_TR)
3750 vmcs_write16(sf->selector, var->selector);
3752 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3756 vmcs_writel(sf->base, var->base);
3757 vmcs_write32(sf->limit, var->limit);
3758 vmcs_write16(sf->selector, var->selector);
3761 * Fix the "Accessed" bit in AR field of segment registers for older
3763 * IA32 arch specifies that at the time of processor reset the
3764 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3765 * is setting it to 0 in the userland code. This causes invalid guest
3766 * state vmexit when "unrestricted guest" mode is turned on.
3767 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3768 * tree. Newer qemu binaries with that qemu fix would not need this
3771 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3772 var->type |= 0x1; /* Accessed */
3774 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3777 vmx->emulation_required = emulation_required(vcpu);
3780 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3782 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3784 *db = (ar >> 14) & 1;
3785 *l = (ar >> 13) & 1;
3788 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3790 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3791 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3794 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3796 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3797 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3800 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3802 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3803 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3806 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3808 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3809 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3812 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3814 struct kvm_segment var;
3817 vmx_get_segment(vcpu, &var, seg);
3819 if (seg == VCPU_SREG_CS)
3821 ar = vmx_segment_access_rights(&var);
3823 if (var.base != (var.selector << 4))
3825 if (var.limit != 0xffff)
3833 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3835 struct kvm_segment cs;
3836 unsigned int cs_rpl;
3838 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3839 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3843 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3847 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3848 if (cs.dpl > cs_rpl)
3851 if (cs.dpl != cs_rpl)
3857 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3861 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3863 struct kvm_segment ss;
3864 unsigned int ss_rpl;
3866 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3867 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3871 if (ss.type != 3 && ss.type != 7)
3875 if (ss.dpl != ss_rpl) /* DPL != RPL */
3883 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3885 struct kvm_segment var;
3888 vmx_get_segment(vcpu, &var, seg);
3889 rpl = var.selector & SELECTOR_RPL_MASK;
3897 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3898 if (var.dpl < rpl) /* DPL < RPL */
3902 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3908 static bool tr_valid(struct kvm_vcpu *vcpu)
3910 struct kvm_segment tr;
3912 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3916 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3918 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3926 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3928 struct kvm_segment ldtr;
3930 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3934 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3944 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3946 struct kvm_segment cs, ss;
3948 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3949 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3951 return ((cs.selector & SELECTOR_RPL_MASK) ==
3952 (ss.selector & SELECTOR_RPL_MASK));
3956 * Check if guest state is valid. Returns true if valid, false if
3958 * We assume that registers are always usable
3960 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3962 if (enable_unrestricted_guest)
3965 /* real mode guest state checks */
3966 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3967 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3969 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3971 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3973 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3975 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3977 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3980 /* protected mode guest state checks */
3981 if (!cs_ss_rpl_check(vcpu))
3983 if (!code_segment_valid(vcpu))
3985 if (!stack_segment_valid(vcpu))
3987 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3989 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3991 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3993 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3995 if (!tr_valid(vcpu))
3997 if (!ldtr_valid(vcpu))
4001 * - Add checks on RIP
4002 * - Add checks on RFLAGS
4008 static int init_rmode_tss(struct kvm *kvm)
4014 idx = srcu_read_lock(&kvm->srcu);
4015 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4016 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4019 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4020 r = kvm_write_guest_page(kvm, fn++, &data,
4021 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4024 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4027 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4031 r = kvm_write_guest_page(kvm, fn, &data,
4032 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4035 srcu_read_unlock(&kvm->srcu, idx);
4039 static int init_rmode_identity_map(struct kvm *kvm)
4042 pfn_t identity_map_pfn;
4048 /* Protect kvm->arch.ept_identity_pagetable_done. */
4049 mutex_lock(&kvm->slots_lock);
4051 if (likely(kvm->arch.ept_identity_pagetable_done))
4054 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4056 r = alloc_identity_pagetable(kvm);
4060 idx = srcu_read_lock(&kvm->srcu);
4061 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4064 /* Set up identity-mapping pagetable for EPT in real mode */
4065 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4066 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4067 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4068 r = kvm_write_guest_page(kvm, identity_map_pfn,
4069 &tmp, i * sizeof(tmp), sizeof(tmp));
4073 kvm->arch.ept_identity_pagetable_done = true;
4076 srcu_read_unlock(&kvm->srcu, idx);
4079 mutex_unlock(&kvm->slots_lock);
4083 static void seg_setup(int seg)
4085 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4088 vmcs_write16(sf->selector, 0);
4089 vmcs_writel(sf->base, 0);
4090 vmcs_write32(sf->limit, 0xffff);
4092 if (seg == VCPU_SREG_CS)
4093 ar |= 0x08; /* code segment */
4095 vmcs_write32(sf->ar_bytes, ar);
4098 static int alloc_apic_access_page(struct kvm *kvm)
4101 struct kvm_userspace_memory_region kvm_userspace_mem;
4104 mutex_lock(&kvm->slots_lock);
4105 if (kvm->arch.apic_access_page_done)
4107 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4108 kvm_userspace_mem.flags = 0;
4109 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4110 kvm_userspace_mem.memory_size = PAGE_SIZE;
4111 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4115 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4116 if (is_error_page(page)) {
4122 * Do not pin the page in memory, so that memory hot-unplug
4123 * is able to migrate it.
4126 kvm->arch.apic_access_page_done = true;
4128 mutex_unlock(&kvm->slots_lock);
4132 static int alloc_identity_pagetable(struct kvm *kvm)
4134 /* Called with kvm->slots_lock held. */
4136 struct kvm_userspace_memory_region kvm_userspace_mem;
4139 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4141 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4142 kvm_userspace_mem.flags = 0;
4143 kvm_userspace_mem.guest_phys_addr =
4144 kvm->arch.ept_identity_map_addr;
4145 kvm_userspace_mem.memory_size = PAGE_SIZE;
4146 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4151 static void allocate_vpid(struct vcpu_vmx *vmx)
4158 spin_lock(&vmx_vpid_lock);
4159 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4160 if (vpid < VMX_NR_VPIDS) {
4162 __set_bit(vpid, vmx_vpid_bitmap);
4164 spin_unlock(&vmx_vpid_lock);
4167 static void free_vpid(struct vcpu_vmx *vmx)
4171 spin_lock(&vmx_vpid_lock);
4173 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4174 spin_unlock(&vmx_vpid_lock);
4177 #define MSR_TYPE_R 1
4178 #define MSR_TYPE_W 2
4179 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4182 int f = sizeof(unsigned long);
4184 if (!cpu_has_vmx_msr_bitmap())
4188 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4189 * have the write-low and read-high bitmap offsets the wrong way round.
4190 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4192 if (msr <= 0x1fff) {
4193 if (type & MSR_TYPE_R)
4195 __clear_bit(msr, msr_bitmap + 0x000 / f);
4197 if (type & MSR_TYPE_W)
4199 __clear_bit(msr, msr_bitmap + 0x800 / f);
4201 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4203 if (type & MSR_TYPE_R)
4205 __clear_bit(msr, msr_bitmap + 0x400 / f);
4207 if (type & MSR_TYPE_W)
4209 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4214 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4217 int f = sizeof(unsigned long);
4219 if (!cpu_has_vmx_msr_bitmap())
4223 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4224 * have the write-low and read-high bitmap offsets the wrong way round.
4225 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4227 if (msr <= 0x1fff) {
4228 if (type & MSR_TYPE_R)
4230 __set_bit(msr, msr_bitmap + 0x000 / f);
4232 if (type & MSR_TYPE_W)
4234 __set_bit(msr, msr_bitmap + 0x800 / f);
4236 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4238 if (type & MSR_TYPE_R)
4240 __set_bit(msr, msr_bitmap + 0x400 / f);
4242 if (type & MSR_TYPE_W)
4244 __set_bit(msr, msr_bitmap + 0xc00 / f);
4250 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4251 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4253 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4254 unsigned long *msr_bitmap_nested,
4257 int f = sizeof(unsigned long);
4259 if (!cpu_has_vmx_msr_bitmap()) {
4265 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4266 * have the write-low and read-high bitmap offsets the wrong way round.
4267 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4269 if (msr <= 0x1fff) {
4270 if (type & MSR_TYPE_R &&
4271 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4273 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4275 if (type & MSR_TYPE_W &&
4276 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4278 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4280 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4282 if (type & MSR_TYPE_R &&
4283 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4285 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4287 if (type & MSR_TYPE_W &&
4288 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4290 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4295 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4298 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4299 msr, MSR_TYPE_R | MSR_TYPE_W);
4300 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4301 msr, MSR_TYPE_R | MSR_TYPE_W);
4304 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4306 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4308 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4312 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4314 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4316 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4320 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4322 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4324 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4328 static int vmx_vm_has_apicv(struct kvm *kvm)
4330 return enable_apicv && irqchip_in_kernel(kvm);
4333 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4335 struct vcpu_vmx *vmx = to_vmx(vcpu);
4340 if (vmx->nested.pi_desc &&
4341 vmx->nested.pi_pending) {
4342 vmx->nested.pi_pending = false;
4343 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4346 max_irr = find_last_bit(
4347 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4352 vapic_page = kmap(vmx->nested.virtual_apic_page);
4357 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4358 kunmap(vmx->nested.virtual_apic_page);
4360 status = vmcs_read16(GUEST_INTR_STATUS);
4361 if ((u8)max_irr > ((u8)status & 0xff)) {
4363 status |= (u8)max_irr;
4364 vmcs_write16(GUEST_INTR_STATUS, status);
4370 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4373 struct vcpu_vmx *vmx = to_vmx(vcpu);
4375 if (is_guest_mode(vcpu) &&
4376 vector == vmx->nested.posted_intr_nv) {
4377 /* the PIR and ON have been set by L1. */
4378 if (vcpu->mode == IN_GUEST_MODE)
4379 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4380 POSTED_INTR_VECTOR);
4382 * If a posted intr is not recognized by hardware,
4383 * we will accomplish it in the next vmentry.
4385 vmx->nested.pi_pending = true;
4386 kvm_make_request(KVM_REQ_EVENT, vcpu);
4392 * Send interrupt to vcpu via posted interrupt way.
4393 * 1. If target vcpu is running(non-root mode), send posted interrupt
4394 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4395 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4396 * interrupt from PIR in next vmentry.
4398 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4400 struct vcpu_vmx *vmx = to_vmx(vcpu);
4403 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4407 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4410 r = pi_test_and_set_on(&vmx->pi_desc);
4411 kvm_make_request(KVM_REQ_EVENT, vcpu);
4413 if (!r && (vcpu->mode == IN_GUEST_MODE))
4414 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4415 POSTED_INTR_VECTOR);
4418 kvm_vcpu_kick(vcpu);
4421 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4423 struct vcpu_vmx *vmx = to_vmx(vcpu);
4425 if (!pi_test_and_clear_on(&vmx->pi_desc))
4428 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4431 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4437 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4438 * will not change in the lifetime of the guest.
4439 * Note that host-state that does change is set elsewhere. E.g., host-state
4440 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4442 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4449 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4450 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4452 /* Save the most likely value for this task's CR4 in the VMCS. */
4453 cr4 = cr4_read_shadow();
4454 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4455 vmx->host_state.vmcs_host_cr4 = cr4;
4457 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4458 #ifdef CONFIG_X86_64
4460 * Load null selectors, so we can avoid reloading them in
4461 * __vmx_load_host_state(), in case userspace uses the null selectors
4462 * too (the expected case).
4464 vmcs_write16(HOST_DS_SELECTOR, 0);
4465 vmcs_write16(HOST_ES_SELECTOR, 0);
4467 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4468 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4470 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4471 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4473 native_store_idt(&dt);
4474 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4475 vmx->host_idt_base = dt.address;
4477 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4479 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4480 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4481 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4482 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4484 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4485 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4486 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4490 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4492 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4494 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4495 if (is_guest_mode(&vmx->vcpu))
4496 vmx->vcpu.arch.cr4_guest_owned_bits &=
4497 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4498 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4501 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4503 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4505 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4506 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4507 return pin_based_exec_ctrl;
4510 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4512 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4514 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4515 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4517 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4518 exec_control &= ~CPU_BASED_TPR_SHADOW;
4519 #ifdef CONFIG_X86_64
4520 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4521 CPU_BASED_CR8_LOAD_EXITING;
4525 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4526 CPU_BASED_CR3_LOAD_EXITING |
4527 CPU_BASED_INVLPG_EXITING;
4528 return exec_control;
4531 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4533 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4534 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4535 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4537 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4539 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4540 enable_unrestricted_guest = 0;
4541 /* Enable INVPCID for non-ept guests may cause performance regression. */
4542 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4544 if (!enable_unrestricted_guest)
4545 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4547 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4548 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4549 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4550 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4551 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4552 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4554 We can NOT enable shadow_vmcs here because we don't have yet
4557 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4558 /* PML is enabled/disabled in creating/destorying vcpu */
4559 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4561 return exec_control;
4564 static void ept_set_mmio_spte_mask(void)
4567 * EPT Misconfigurations can be generated if the value of bits 2:0
4568 * of an EPT paging-structure entry is 110b (write/execute).
4569 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4572 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4575 #define VMX_XSS_EXIT_BITMAP 0
4577 * Sets up the vmcs for emulated real mode.
4579 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4581 #ifdef CONFIG_X86_64
4587 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4588 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4590 if (enable_shadow_vmcs) {
4591 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4592 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4594 if (cpu_has_vmx_msr_bitmap())
4595 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4597 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4600 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4602 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4604 if (cpu_has_secondary_exec_ctrls()) {
4605 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4606 vmx_secondary_exec_control(vmx));
4609 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4610 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4611 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4612 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4613 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4615 vmcs_write16(GUEST_INTR_STATUS, 0);
4617 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4618 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4622 vmcs_write32(PLE_GAP, ple_gap);
4623 vmx->ple_window = ple_window;
4624 vmx->ple_window_dirty = true;
4627 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4628 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4629 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4631 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4632 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4633 vmx_set_constant_host_state(vmx);
4634 #ifdef CONFIG_X86_64
4635 rdmsrl(MSR_FS_BASE, a);
4636 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4637 rdmsrl(MSR_GS_BASE, a);
4638 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4640 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4641 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4644 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4645 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4646 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4647 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4648 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4650 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4651 u32 msr_low, msr_high;
4653 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4654 host_pat = msr_low | ((u64) msr_high << 32);
4655 /* Write the default value follow host pat */
4656 vmcs_write64(GUEST_IA32_PAT, host_pat);
4657 /* Keep arch.pat sync with GUEST_IA32_PAT */
4658 vmx->vcpu.arch.pat = host_pat;
4661 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4662 u32 index = vmx_msr_index[i];
4663 u32 data_low, data_high;
4666 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4668 if (wrmsr_safe(index, data_low, data_high) < 0)
4670 vmx->guest_msrs[j].index = i;
4671 vmx->guest_msrs[j].data = 0;
4672 vmx->guest_msrs[j].mask = -1ull;
4677 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4679 /* 22.2.1, 20.8.1 */
4680 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4682 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4683 set_cr4_guest_host_mask(vmx);
4685 if (vmx_xsaves_supported())
4686 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4691 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4693 struct vcpu_vmx *vmx = to_vmx(vcpu);
4694 struct msr_data apic_base_msr;
4696 vmx->rmode.vm86_active = 0;
4698 vmx->soft_vnmi_blocked = 0;
4700 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4701 kvm_set_cr8(&vmx->vcpu, 0);
4702 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4703 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4704 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4705 apic_base_msr.host_initiated = true;
4706 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4708 vmx_segment_cache_clear(vmx);
4710 seg_setup(VCPU_SREG_CS);
4711 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4712 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4714 seg_setup(VCPU_SREG_DS);
4715 seg_setup(VCPU_SREG_ES);
4716 seg_setup(VCPU_SREG_FS);
4717 seg_setup(VCPU_SREG_GS);
4718 seg_setup(VCPU_SREG_SS);
4720 vmcs_write16(GUEST_TR_SELECTOR, 0);
4721 vmcs_writel(GUEST_TR_BASE, 0);
4722 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4723 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4725 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4726 vmcs_writel(GUEST_LDTR_BASE, 0);
4727 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4728 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4730 vmcs_write32(GUEST_SYSENTER_CS, 0);
4731 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4732 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4734 vmcs_writel(GUEST_RFLAGS, 0x02);
4735 kvm_rip_write(vcpu, 0xfff0);
4737 vmcs_writel(GUEST_GDTR_BASE, 0);
4738 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4740 vmcs_writel(GUEST_IDTR_BASE, 0);
4741 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4743 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4744 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4745 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4747 /* Special registers */
4748 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4752 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4754 if (cpu_has_vmx_tpr_shadow()) {
4755 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4756 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4757 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4758 __pa(vmx->vcpu.arch.apic->regs));
4759 vmcs_write32(TPR_THRESHOLD, 0);
4762 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4764 if (vmx_vm_has_apicv(vcpu->kvm))
4765 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4768 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4770 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4771 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4772 vmx_set_cr4(&vmx->vcpu, 0);
4773 vmx_set_efer(&vmx->vcpu, 0);
4774 vmx_fpu_activate(&vmx->vcpu);
4775 update_exception_bitmap(&vmx->vcpu);
4777 vpid_sync_context(vmx);
4781 * In nested virtualization, check if L1 asked to exit on external interrupts.
4782 * For most existing hypervisors, this will always return true.
4784 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4786 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4787 PIN_BASED_EXT_INTR_MASK;
4791 * In nested virtualization, check if L1 has set
4792 * VM_EXIT_ACK_INTR_ON_EXIT
4794 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4796 return get_vmcs12(vcpu)->vm_exit_controls &
4797 VM_EXIT_ACK_INTR_ON_EXIT;
4800 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4802 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4803 PIN_BASED_NMI_EXITING;
4806 static void enable_irq_window(struct kvm_vcpu *vcpu)
4808 u32 cpu_based_vm_exec_control;
4810 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4811 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4812 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4815 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4817 u32 cpu_based_vm_exec_control;
4819 if (!cpu_has_virtual_nmis() ||
4820 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4821 enable_irq_window(vcpu);
4825 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4826 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4827 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4830 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4832 struct vcpu_vmx *vmx = to_vmx(vcpu);
4834 int irq = vcpu->arch.interrupt.nr;
4836 trace_kvm_inj_virq(irq);
4838 ++vcpu->stat.irq_injections;
4839 if (vmx->rmode.vm86_active) {
4841 if (vcpu->arch.interrupt.soft)
4842 inc_eip = vcpu->arch.event_exit_inst_len;
4843 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4844 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4847 intr = irq | INTR_INFO_VALID_MASK;
4848 if (vcpu->arch.interrupt.soft) {
4849 intr |= INTR_TYPE_SOFT_INTR;
4850 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4851 vmx->vcpu.arch.event_exit_inst_len);
4853 intr |= INTR_TYPE_EXT_INTR;
4854 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4857 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4859 struct vcpu_vmx *vmx = to_vmx(vcpu);
4861 if (is_guest_mode(vcpu))
4864 if (!cpu_has_virtual_nmis()) {
4866 * Tracking the NMI-blocked state in software is built upon
4867 * finding the next open IRQ window. This, in turn, depends on
4868 * well-behaving guests: They have to keep IRQs disabled at
4869 * least as long as the NMI handler runs. Otherwise we may
4870 * cause NMI nesting, maybe breaking the guest. But as this is
4871 * highly unlikely, we can live with the residual risk.
4873 vmx->soft_vnmi_blocked = 1;
4874 vmx->vnmi_blocked_time = 0;
4877 ++vcpu->stat.nmi_injections;
4878 vmx->nmi_known_unmasked = false;
4879 if (vmx->rmode.vm86_active) {
4880 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4881 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4884 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4885 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4888 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4890 if (!cpu_has_virtual_nmis())
4891 return to_vmx(vcpu)->soft_vnmi_blocked;
4892 if (to_vmx(vcpu)->nmi_known_unmasked)
4894 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4897 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4899 struct vcpu_vmx *vmx = to_vmx(vcpu);
4901 if (!cpu_has_virtual_nmis()) {
4902 if (vmx->soft_vnmi_blocked != masked) {
4903 vmx->soft_vnmi_blocked = masked;
4904 vmx->vnmi_blocked_time = 0;
4907 vmx->nmi_known_unmasked = !masked;
4909 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4910 GUEST_INTR_STATE_NMI);
4912 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4913 GUEST_INTR_STATE_NMI);
4917 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4919 if (to_vmx(vcpu)->nested.nested_run_pending)
4922 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4925 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4926 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4927 | GUEST_INTR_STATE_NMI));
4930 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4932 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4933 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4934 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4935 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4938 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4941 struct kvm_userspace_memory_region tss_mem = {
4942 .slot = TSS_PRIVATE_MEMSLOT,
4943 .guest_phys_addr = addr,
4944 .memory_size = PAGE_SIZE * 3,
4948 ret = kvm_set_memory_region(kvm, &tss_mem);
4951 kvm->arch.tss_addr = addr;
4952 return init_rmode_tss(kvm);
4955 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4960 * Update instruction length as we may reinject the exception
4961 * from user space while in guest debugging mode.
4963 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4964 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4965 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4969 if (vcpu->guest_debug &
4970 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4987 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4988 int vec, u32 err_code)
4991 * Instruction with address size override prefix opcode 0x67
4992 * Cause the #SS fault with 0 error code in VM86 mode.
4994 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4995 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4996 if (vcpu->arch.halt_request) {
4997 vcpu->arch.halt_request = 0;
4998 return kvm_emulate_halt(vcpu);
5006 * Forward all other exceptions that are valid in real mode.
5007 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5008 * the required debugging infrastructure rework.
5010 kvm_queue_exception(vcpu, vec);
5015 * Trigger machine check on the host. We assume all the MSRs are already set up
5016 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5017 * We pass a fake environment to the machine check handler because we want
5018 * the guest to be always treated like user space, no matter what context
5019 * it used internally.
5021 static void kvm_machine_check(void)
5023 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5024 struct pt_regs regs = {
5025 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5026 .flags = X86_EFLAGS_IF,
5029 do_machine_check(®s, 0);
5033 static int handle_machine_check(struct kvm_vcpu *vcpu)
5035 /* already handled by vcpu_run */
5039 static int handle_exception(struct kvm_vcpu *vcpu)
5041 struct vcpu_vmx *vmx = to_vmx(vcpu);
5042 struct kvm_run *kvm_run = vcpu->run;
5043 u32 intr_info, ex_no, error_code;
5044 unsigned long cr2, rip, dr6;
5046 enum emulation_result er;
5048 vect_info = vmx->idt_vectoring_info;
5049 intr_info = vmx->exit_intr_info;
5051 if (is_machine_check(intr_info))
5052 return handle_machine_check(vcpu);
5054 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5055 return 1; /* already handled by vmx_vcpu_run() */
5057 if (is_no_device(intr_info)) {
5058 vmx_fpu_activate(vcpu);
5062 if (is_invalid_opcode(intr_info)) {
5063 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5064 if (er != EMULATE_DONE)
5065 kvm_queue_exception(vcpu, UD_VECTOR);
5070 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5071 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5074 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5075 * MMIO, it is better to report an internal error.
5076 * See the comments in vmx_handle_exit.
5078 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5079 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5080 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5081 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5082 vcpu->run->internal.ndata = 2;
5083 vcpu->run->internal.data[0] = vect_info;
5084 vcpu->run->internal.data[1] = intr_info;
5088 if (is_page_fault(intr_info)) {
5089 /* EPT won't cause page fault directly */
5091 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5092 trace_kvm_page_fault(cr2, error_code);
5094 if (kvm_event_needs_reinjection(vcpu))
5095 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5096 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5099 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5101 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5102 return handle_rmode_exception(vcpu, ex_no, error_code);
5106 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5107 if (!(vcpu->guest_debug &
5108 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5109 vcpu->arch.dr6 &= ~15;
5110 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5111 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5112 skip_emulated_instruction(vcpu);
5114 kvm_queue_exception(vcpu, DB_VECTOR);
5117 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5118 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5122 * Update instruction length as we may reinject #BP from
5123 * user space while in guest debugging mode. Reading it for
5124 * #DB as well causes no harm, it is not used in that case.
5126 vmx->vcpu.arch.event_exit_inst_len =
5127 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5128 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5129 rip = kvm_rip_read(vcpu);
5130 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5131 kvm_run->debug.arch.exception = ex_no;
5134 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5135 kvm_run->ex.exception = ex_no;
5136 kvm_run->ex.error_code = error_code;
5142 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5144 ++vcpu->stat.irq_exits;
5148 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5150 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5154 static int handle_io(struct kvm_vcpu *vcpu)
5156 unsigned long exit_qualification;
5157 int size, in, string;
5160 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5161 string = (exit_qualification & 16) != 0;
5162 in = (exit_qualification & 8) != 0;
5164 ++vcpu->stat.io_exits;
5167 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5169 port = exit_qualification >> 16;
5170 size = (exit_qualification & 7) + 1;
5171 skip_emulated_instruction(vcpu);
5173 return kvm_fast_pio_out(vcpu, size, port);
5177 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5180 * Patch in the VMCALL instruction:
5182 hypercall[0] = 0x0f;
5183 hypercall[1] = 0x01;
5184 hypercall[2] = 0xc1;
5187 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5189 unsigned long always_on = VMXON_CR0_ALWAYSON;
5190 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5192 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5193 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5194 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5195 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5196 return (val & always_on) == always_on;
5199 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5200 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5202 if (is_guest_mode(vcpu)) {
5203 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5204 unsigned long orig_val = val;
5207 * We get here when L2 changed cr0 in a way that did not change
5208 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5209 * but did change L0 shadowed bits. So we first calculate the
5210 * effective cr0 value that L1 would like to write into the
5211 * hardware. It consists of the L2-owned bits from the new
5212 * value combined with the L1-owned bits from L1's guest_cr0.
5214 val = (val & ~vmcs12->cr0_guest_host_mask) |
5215 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5217 if (!nested_cr0_valid(vcpu, val))
5220 if (kvm_set_cr0(vcpu, val))
5222 vmcs_writel(CR0_READ_SHADOW, orig_val);
5225 if (to_vmx(vcpu)->nested.vmxon &&
5226 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5228 return kvm_set_cr0(vcpu, val);
5232 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5234 if (is_guest_mode(vcpu)) {
5235 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5236 unsigned long orig_val = val;
5238 /* analogously to handle_set_cr0 */
5239 val = (val & ~vmcs12->cr4_guest_host_mask) |
5240 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5241 if (kvm_set_cr4(vcpu, val))
5243 vmcs_writel(CR4_READ_SHADOW, orig_val);
5246 return kvm_set_cr4(vcpu, val);
5249 /* called to set cr0 as approriate for clts instruction exit. */
5250 static void handle_clts(struct kvm_vcpu *vcpu)
5252 if (is_guest_mode(vcpu)) {
5254 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5255 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5256 * just pretend it's off (also in arch.cr0 for fpu_activate).
5258 vmcs_writel(CR0_READ_SHADOW,
5259 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5260 vcpu->arch.cr0 &= ~X86_CR0_TS;
5262 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5265 static int handle_cr(struct kvm_vcpu *vcpu)
5267 unsigned long exit_qualification, val;
5272 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5273 cr = exit_qualification & 15;
5274 reg = (exit_qualification >> 8) & 15;
5275 switch ((exit_qualification >> 4) & 3) {
5276 case 0: /* mov to cr */
5277 val = kvm_register_readl(vcpu, reg);
5278 trace_kvm_cr_write(cr, val);
5281 err = handle_set_cr0(vcpu, val);
5282 kvm_complete_insn_gp(vcpu, err);
5285 err = kvm_set_cr3(vcpu, val);
5286 kvm_complete_insn_gp(vcpu, err);
5289 err = handle_set_cr4(vcpu, val);
5290 kvm_complete_insn_gp(vcpu, err);
5293 u8 cr8_prev = kvm_get_cr8(vcpu);
5295 err = kvm_set_cr8(vcpu, cr8);
5296 kvm_complete_insn_gp(vcpu, err);
5297 if (irqchip_in_kernel(vcpu->kvm))
5299 if (cr8_prev <= cr8)
5301 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5308 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5309 skip_emulated_instruction(vcpu);
5310 vmx_fpu_activate(vcpu);
5312 case 1: /*mov from cr*/
5315 val = kvm_read_cr3(vcpu);
5316 kvm_register_write(vcpu, reg, val);
5317 trace_kvm_cr_read(cr, val);
5318 skip_emulated_instruction(vcpu);
5321 val = kvm_get_cr8(vcpu);
5322 kvm_register_write(vcpu, reg, val);
5323 trace_kvm_cr_read(cr, val);
5324 skip_emulated_instruction(vcpu);
5329 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5330 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5331 kvm_lmsw(vcpu, val);
5333 skip_emulated_instruction(vcpu);
5338 vcpu->run->exit_reason = 0;
5339 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5340 (int)(exit_qualification >> 4) & 3, cr);
5344 static int handle_dr(struct kvm_vcpu *vcpu)
5346 unsigned long exit_qualification;
5349 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5350 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5352 /* First, if DR does not exist, trigger UD */
5353 if (!kvm_require_dr(vcpu, dr))
5356 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5357 if (!kvm_require_cpl(vcpu, 0))
5359 dr7 = vmcs_readl(GUEST_DR7);
5362 * As the vm-exit takes precedence over the debug trap, we
5363 * need to emulate the latter, either for the host or the
5364 * guest debugging itself.
5366 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5367 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5368 vcpu->run->debug.arch.dr7 = dr7;
5369 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5370 vcpu->run->debug.arch.exception = DB_VECTOR;
5371 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5374 vcpu->arch.dr6 &= ~15;
5375 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5376 kvm_queue_exception(vcpu, DB_VECTOR);
5381 if (vcpu->guest_debug == 0) {
5382 u32 cpu_based_vm_exec_control;
5384 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5385 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5386 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5389 * No more DR vmexits; force a reload of the debug registers
5390 * and reenter on this instruction. The next vmexit will
5391 * retrieve the full state of the debug registers.
5393 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5397 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5398 if (exit_qualification & TYPE_MOV_FROM_DR) {
5401 if (kvm_get_dr(vcpu, dr, &val))
5403 kvm_register_write(vcpu, reg, val);
5405 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5408 skip_emulated_instruction(vcpu);
5412 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5414 return vcpu->arch.dr6;
5417 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5421 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5423 u32 cpu_based_vm_exec_control;
5425 get_debugreg(vcpu->arch.db[0], 0);
5426 get_debugreg(vcpu->arch.db[1], 1);
5427 get_debugreg(vcpu->arch.db[2], 2);
5428 get_debugreg(vcpu->arch.db[3], 3);
5429 get_debugreg(vcpu->arch.dr6, 6);
5430 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5432 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5434 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5435 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5436 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5439 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5441 vmcs_writel(GUEST_DR7, val);
5444 static int handle_cpuid(struct kvm_vcpu *vcpu)
5446 kvm_emulate_cpuid(vcpu);
5450 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5452 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5455 if (vmx_get_msr(vcpu, ecx, &data)) {
5456 trace_kvm_msr_read_ex(ecx);
5457 kvm_inject_gp(vcpu, 0);
5461 trace_kvm_msr_read(ecx, data);
5463 /* FIXME: handling of bits 32:63 of rax, rdx */
5464 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5465 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5466 skip_emulated_instruction(vcpu);
5470 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5472 struct msr_data msr;
5473 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5474 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5475 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5479 msr.host_initiated = false;
5480 if (kvm_set_msr(vcpu, &msr) != 0) {
5481 trace_kvm_msr_write_ex(ecx, data);
5482 kvm_inject_gp(vcpu, 0);
5486 trace_kvm_msr_write(ecx, data);
5487 skip_emulated_instruction(vcpu);
5491 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5493 kvm_make_request(KVM_REQ_EVENT, vcpu);
5497 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5499 u32 cpu_based_vm_exec_control;
5501 /* clear pending irq */
5502 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5503 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5504 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5506 kvm_make_request(KVM_REQ_EVENT, vcpu);
5508 ++vcpu->stat.irq_window_exits;
5511 * If the user space waits to inject interrupts, exit as soon as
5514 if (!irqchip_in_kernel(vcpu->kvm) &&
5515 vcpu->run->request_interrupt_window &&
5516 !kvm_cpu_has_interrupt(vcpu)) {
5517 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5523 static int handle_halt(struct kvm_vcpu *vcpu)
5525 skip_emulated_instruction(vcpu);
5526 return kvm_emulate_halt(vcpu);
5529 static int handle_vmcall(struct kvm_vcpu *vcpu)
5531 skip_emulated_instruction(vcpu);
5532 kvm_emulate_hypercall(vcpu);
5536 static int handle_invd(struct kvm_vcpu *vcpu)
5538 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5541 static int handle_invlpg(struct kvm_vcpu *vcpu)
5543 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5545 kvm_mmu_invlpg(vcpu, exit_qualification);
5546 skip_emulated_instruction(vcpu);
5550 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5554 err = kvm_rdpmc(vcpu);
5555 kvm_complete_insn_gp(vcpu, err);
5560 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5562 skip_emulated_instruction(vcpu);
5563 kvm_emulate_wbinvd(vcpu);
5567 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5569 u64 new_bv = kvm_read_edx_eax(vcpu);
5570 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5572 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5573 skip_emulated_instruction(vcpu);
5577 static int handle_xsaves(struct kvm_vcpu *vcpu)
5579 skip_emulated_instruction(vcpu);
5580 WARN(1, "this should never happen\n");
5584 static int handle_xrstors(struct kvm_vcpu *vcpu)
5586 skip_emulated_instruction(vcpu);
5587 WARN(1, "this should never happen\n");
5591 static int handle_apic_access(struct kvm_vcpu *vcpu)
5593 if (likely(fasteoi)) {
5594 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5595 int access_type, offset;
5597 access_type = exit_qualification & APIC_ACCESS_TYPE;
5598 offset = exit_qualification & APIC_ACCESS_OFFSET;
5600 * Sane guest uses MOV to write EOI, with written value
5601 * not cared. So make a short-circuit here by avoiding
5602 * heavy instruction emulation.
5604 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5605 (offset == APIC_EOI)) {
5606 kvm_lapic_set_eoi(vcpu);
5607 skip_emulated_instruction(vcpu);
5611 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5614 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5616 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5617 int vector = exit_qualification & 0xff;
5619 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5620 kvm_apic_set_eoi_accelerated(vcpu, vector);
5624 static int handle_apic_write(struct kvm_vcpu *vcpu)
5626 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5627 u32 offset = exit_qualification & 0xfff;
5629 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5630 kvm_apic_write_nodecode(vcpu, offset);
5634 static int handle_task_switch(struct kvm_vcpu *vcpu)
5636 struct vcpu_vmx *vmx = to_vmx(vcpu);
5637 unsigned long exit_qualification;
5638 bool has_error_code = false;
5641 int reason, type, idt_v, idt_index;
5643 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5644 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5645 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5647 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5649 reason = (u32)exit_qualification >> 30;
5650 if (reason == TASK_SWITCH_GATE && idt_v) {
5652 case INTR_TYPE_NMI_INTR:
5653 vcpu->arch.nmi_injected = false;
5654 vmx_set_nmi_mask(vcpu, true);
5656 case INTR_TYPE_EXT_INTR:
5657 case INTR_TYPE_SOFT_INTR:
5658 kvm_clear_interrupt_queue(vcpu);
5660 case INTR_TYPE_HARD_EXCEPTION:
5661 if (vmx->idt_vectoring_info &
5662 VECTORING_INFO_DELIVER_CODE_MASK) {
5663 has_error_code = true;
5665 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5668 case INTR_TYPE_SOFT_EXCEPTION:
5669 kvm_clear_exception_queue(vcpu);
5675 tss_selector = exit_qualification;
5677 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5678 type != INTR_TYPE_EXT_INTR &&
5679 type != INTR_TYPE_NMI_INTR))
5680 skip_emulated_instruction(vcpu);
5682 if (kvm_task_switch(vcpu, tss_selector,
5683 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5684 has_error_code, error_code) == EMULATE_FAIL) {
5685 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5686 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5687 vcpu->run->internal.ndata = 0;
5691 /* clear all local breakpoint enable flags */
5692 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5695 * TODO: What about debug traps on tss switch?
5696 * Are we supposed to inject them and update dr6?
5702 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5704 unsigned long exit_qualification;
5709 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5711 gla_validity = (exit_qualification >> 7) & 0x3;
5712 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5713 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5714 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5715 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5716 vmcs_readl(GUEST_LINEAR_ADDRESS));
5717 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5718 (long unsigned int)exit_qualification);
5719 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5720 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5725 * EPT violation happened while executing iret from NMI,
5726 * "blocked by NMI" bit has to be set before next VM entry.
5727 * There are errata that may cause this bit to not be set:
5730 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5731 cpu_has_virtual_nmis() &&
5732 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5733 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5735 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5736 trace_kvm_page_fault(gpa, exit_qualification);
5738 /* It is a write fault? */
5739 error_code = exit_qualification & PFERR_WRITE_MASK;
5740 /* It is a fetch fault? */
5741 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5742 /* ept page table is present? */
5743 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5745 vcpu->arch.exit_qualification = exit_qualification;
5747 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5750 static u64 ept_rsvd_mask(u64 spte, int level)
5755 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5756 mask |= (1ULL << i);
5759 /* bits 7:3 reserved */
5761 else if (spte & (1ULL << 7))
5763 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5764 * level == 1 if the hypervisor is using the ignored bit 7.
5766 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5768 /* bits 6:3 reserved */
5774 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5777 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5779 /* 010b (write-only) */
5780 WARN_ON((spte & 0x7) == 0x2);
5782 /* 110b (write/execute) */
5783 WARN_ON((spte & 0x7) == 0x6);
5785 /* 100b (execute-only) and value not supported by logical processor */
5786 if (!cpu_has_vmx_ept_execute_only())
5787 WARN_ON((spte & 0x7) == 0x4);
5791 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5793 if (rsvd_bits != 0) {
5794 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5795 __func__, rsvd_bits);
5799 /* bits 5:3 are _not_ reserved for large page or leaf page */
5800 if ((rsvd_bits & 0x38) == 0) {
5801 u64 ept_mem_type = (spte & 0x38) >> 3;
5803 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5804 ept_mem_type == 7) {
5805 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5806 __func__, ept_mem_type);
5813 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5816 int nr_sptes, i, ret;
5819 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5820 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5821 skip_emulated_instruction(vcpu);
5825 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5826 if (likely(ret == RET_MMIO_PF_EMULATE))
5827 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5830 if (unlikely(ret == RET_MMIO_PF_INVALID))
5831 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5833 if (unlikely(ret == RET_MMIO_PF_RETRY))
5836 /* It is the real ept misconfig */
5837 printk(KERN_ERR "EPT: Misconfiguration.\n");
5838 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5840 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5842 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5843 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5845 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5846 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5851 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5853 u32 cpu_based_vm_exec_control;
5855 /* clear pending NMI */
5856 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5857 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5858 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5859 ++vcpu->stat.nmi_window_exits;
5860 kvm_make_request(KVM_REQ_EVENT, vcpu);
5865 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5867 struct vcpu_vmx *vmx = to_vmx(vcpu);
5868 enum emulation_result err = EMULATE_DONE;
5871 bool intr_window_requested;
5872 unsigned count = 130;
5874 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5875 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5877 while (vmx->emulation_required && count-- != 0) {
5878 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5879 return handle_interrupt_window(&vmx->vcpu);
5881 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5884 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5886 if (err == EMULATE_USER_EXIT) {
5887 ++vcpu->stat.mmio_exits;
5892 if (err != EMULATE_DONE) {
5893 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5894 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5895 vcpu->run->internal.ndata = 0;
5899 if (vcpu->arch.halt_request) {
5900 vcpu->arch.halt_request = 0;
5901 ret = kvm_emulate_halt(vcpu);
5905 if (signal_pending(current))
5915 static int __grow_ple_window(int val)
5917 if (ple_window_grow < 1)
5920 val = min(val, ple_window_actual_max);
5922 if (ple_window_grow < ple_window)
5923 val *= ple_window_grow;
5925 val += ple_window_grow;
5930 static int __shrink_ple_window(int val, int modifier, int minimum)
5935 if (modifier < ple_window)
5940 return max(val, minimum);
5943 static void grow_ple_window(struct kvm_vcpu *vcpu)
5945 struct vcpu_vmx *vmx = to_vmx(vcpu);
5946 int old = vmx->ple_window;
5948 vmx->ple_window = __grow_ple_window(old);
5950 if (vmx->ple_window != old)
5951 vmx->ple_window_dirty = true;
5953 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5956 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5958 struct vcpu_vmx *vmx = to_vmx(vcpu);
5959 int old = vmx->ple_window;
5961 vmx->ple_window = __shrink_ple_window(old,
5962 ple_window_shrink, ple_window);
5964 if (vmx->ple_window != old)
5965 vmx->ple_window_dirty = true;
5967 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5971 * ple_window_actual_max is computed to be one grow_ple_window() below
5972 * ple_window_max. (See __grow_ple_window for the reason.)
5973 * This prevents overflows, because ple_window_max is int.
5974 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5976 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5978 static void update_ple_window_actual_max(void)
5980 ple_window_actual_max =
5981 __shrink_ple_window(max(ple_window_max, ple_window),
5982 ple_window_grow, INT_MIN);
5985 static __init int hardware_setup(void)
5987 int r = -ENOMEM, i, msr;
5989 rdmsrl_safe(MSR_EFER, &host_efer);
5991 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5992 kvm_define_shared_msr(i, vmx_msr_index[i]);
5994 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5995 if (!vmx_io_bitmap_a)
5998 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5999 if (!vmx_io_bitmap_b)
6002 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6003 if (!vmx_msr_bitmap_legacy)
6006 vmx_msr_bitmap_legacy_x2apic =
6007 (unsigned long *)__get_free_page(GFP_KERNEL);
6008 if (!vmx_msr_bitmap_legacy_x2apic)
6011 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6012 if (!vmx_msr_bitmap_longmode)
6015 vmx_msr_bitmap_longmode_x2apic =
6016 (unsigned long *)__get_free_page(GFP_KERNEL);
6017 if (!vmx_msr_bitmap_longmode_x2apic)
6021 vmx_msr_bitmap_nested =
6022 (unsigned long *)__get_free_page(GFP_KERNEL);
6023 if (!vmx_msr_bitmap_nested)
6027 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6028 if (!vmx_vmread_bitmap)
6031 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6032 if (!vmx_vmwrite_bitmap)
6035 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6036 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6039 * Allow direct access to the PC debug port (it is often used for I/O
6040 * delays, but the vmexits simply slow things down).
6042 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6043 clear_bit(0x80, vmx_io_bitmap_a);
6045 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6047 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6048 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6050 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6052 if (setup_vmcs_config(&vmcs_config) < 0) {
6057 if (boot_cpu_has(X86_FEATURE_NX))
6058 kvm_enable_efer_bits(EFER_NX);
6060 if (!cpu_has_vmx_vpid())
6062 if (!cpu_has_vmx_shadow_vmcs())
6063 enable_shadow_vmcs = 0;
6064 if (enable_shadow_vmcs)
6065 init_vmcs_shadow_fields();
6067 if (!cpu_has_vmx_ept() ||
6068 !cpu_has_vmx_ept_4levels()) {
6070 enable_unrestricted_guest = 0;
6071 enable_ept_ad_bits = 0;
6074 if (!cpu_has_vmx_ept_ad_bits())
6075 enable_ept_ad_bits = 0;
6077 if (!cpu_has_vmx_unrestricted_guest())
6078 enable_unrestricted_guest = 0;
6080 if (!cpu_has_vmx_flexpriority())
6081 flexpriority_enabled = 0;
6084 * set_apic_access_page_addr() is used to reload apic access
6085 * page upon invalidation. No need to do anything if not
6086 * using the APIC_ACCESS_ADDR VMCS field.
6088 if (!flexpriority_enabled)
6089 kvm_x86_ops->set_apic_access_page_addr = NULL;
6091 if (!cpu_has_vmx_tpr_shadow())
6092 kvm_x86_ops->update_cr8_intercept = NULL;
6094 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6095 kvm_disable_largepages();
6097 if (!cpu_has_vmx_ple())
6100 if (!cpu_has_vmx_apicv())
6104 kvm_x86_ops->update_cr8_intercept = NULL;
6106 kvm_x86_ops->hwapic_irr_update = NULL;
6107 kvm_x86_ops->hwapic_isr_update = NULL;
6108 kvm_x86_ops->deliver_posted_interrupt = NULL;
6109 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6112 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6113 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6114 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6115 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6116 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6117 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6118 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6120 memcpy(vmx_msr_bitmap_legacy_x2apic,
6121 vmx_msr_bitmap_legacy, PAGE_SIZE);
6122 memcpy(vmx_msr_bitmap_longmode_x2apic,
6123 vmx_msr_bitmap_longmode, PAGE_SIZE);
6126 for (msr = 0x800; msr <= 0x8ff; msr++)
6127 vmx_disable_intercept_msr_read_x2apic(msr);
6129 /* According SDM, in x2apic mode, the whole id reg is used.
6130 * But in KVM, it only use the highest eight bits. Need to
6132 vmx_enable_intercept_msr_read_x2apic(0x802);
6134 vmx_enable_intercept_msr_read_x2apic(0x839);
6136 vmx_disable_intercept_msr_write_x2apic(0x808);
6138 vmx_disable_intercept_msr_write_x2apic(0x80b);
6140 vmx_disable_intercept_msr_write_x2apic(0x83f);
6144 kvm_mmu_set_mask_ptes(0ull,
6145 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6146 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6147 0ull, VMX_EPT_EXECUTABLE_MASK);
6148 ept_set_mmio_spte_mask();
6153 update_ple_window_actual_max();
6156 * Only enable PML when hardware supports PML feature, and both EPT
6157 * and EPT A/D bit features are enabled -- PML depends on them to work.
6159 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6163 kvm_x86_ops->slot_enable_log_dirty = NULL;
6164 kvm_x86_ops->slot_disable_log_dirty = NULL;
6165 kvm_x86_ops->flush_log_dirty = NULL;
6166 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6169 return alloc_kvm_area();
6172 free_page((unsigned long)vmx_vmwrite_bitmap);
6174 free_page((unsigned long)vmx_vmread_bitmap);
6177 free_page((unsigned long)vmx_msr_bitmap_nested);
6179 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6181 free_page((unsigned long)vmx_msr_bitmap_longmode);
6183 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6185 free_page((unsigned long)vmx_msr_bitmap_legacy);
6187 free_page((unsigned long)vmx_io_bitmap_b);
6189 free_page((unsigned long)vmx_io_bitmap_a);
6194 static __exit void hardware_unsetup(void)
6196 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6197 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6198 free_page((unsigned long)vmx_msr_bitmap_legacy);
6199 free_page((unsigned long)vmx_msr_bitmap_longmode);
6200 free_page((unsigned long)vmx_io_bitmap_b);
6201 free_page((unsigned long)vmx_io_bitmap_a);
6202 free_page((unsigned long)vmx_vmwrite_bitmap);
6203 free_page((unsigned long)vmx_vmread_bitmap);
6205 free_page((unsigned long)vmx_msr_bitmap_nested);
6211 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6212 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6214 static int handle_pause(struct kvm_vcpu *vcpu)
6217 grow_ple_window(vcpu);
6219 skip_emulated_instruction(vcpu);
6220 kvm_vcpu_on_spin(vcpu);
6225 static int handle_nop(struct kvm_vcpu *vcpu)
6227 skip_emulated_instruction(vcpu);
6231 static int handle_mwait(struct kvm_vcpu *vcpu)
6233 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6234 return handle_nop(vcpu);
6237 static int handle_monitor(struct kvm_vcpu *vcpu)
6239 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6240 return handle_nop(vcpu);
6244 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6245 * We could reuse a single VMCS for all the L2 guests, but we also want the
6246 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6247 * allows keeping them loaded on the processor, and in the future will allow
6248 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6249 * every entry if they never change.
6250 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6251 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6253 * The following functions allocate and free a vmcs02 in this pool.
6256 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6257 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6259 struct vmcs02_list *item;
6260 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6261 if (item->vmptr == vmx->nested.current_vmptr) {
6262 list_move(&item->list, &vmx->nested.vmcs02_pool);
6263 return &item->vmcs02;
6266 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6267 /* Recycle the least recently used VMCS. */
6268 item = list_entry(vmx->nested.vmcs02_pool.prev,
6269 struct vmcs02_list, list);
6270 item->vmptr = vmx->nested.current_vmptr;
6271 list_move(&item->list, &vmx->nested.vmcs02_pool);
6272 return &item->vmcs02;
6275 /* Create a new VMCS */
6276 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6279 item->vmcs02.vmcs = alloc_vmcs();
6280 if (!item->vmcs02.vmcs) {
6284 loaded_vmcs_init(&item->vmcs02);
6285 item->vmptr = vmx->nested.current_vmptr;
6286 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6287 vmx->nested.vmcs02_num++;
6288 return &item->vmcs02;
6291 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6292 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6294 struct vmcs02_list *item;
6295 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6296 if (item->vmptr == vmptr) {
6297 free_loaded_vmcs(&item->vmcs02);
6298 list_del(&item->list);
6300 vmx->nested.vmcs02_num--;
6306 * Free all VMCSs saved for this vcpu, except the one pointed by
6307 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6308 * must be &vmx->vmcs01.
6310 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6312 struct vmcs02_list *item, *n;
6314 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6315 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6317 * Something will leak if the above WARN triggers. Better than
6320 if (vmx->loaded_vmcs == &item->vmcs02)
6323 free_loaded_vmcs(&item->vmcs02);
6324 list_del(&item->list);
6326 vmx->nested.vmcs02_num--;
6331 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6332 * set the success or error code of an emulated VMX instruction, as specified
6333 * by Vol 2B, VMX Instruction Reference, "Conventions".
6335 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6337 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6338 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6339 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6342 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6344 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6345 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6346 X86_EFLAGS_SF | X86_EFLAGS_OF))
6350 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6351 u32 vm_instruction_error)
6353 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6355 * failValid writes the error number to the current VMCS, which
6356 * can't be done there isn't a current VMCS.
6358 nested_vmx_failInvalid(vcpu);
6361 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6362 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6363 X86_EFLAGS_SF | X86_EFLAGS_OF))
6365 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6367 * We don't need to force a shadow sync because
6368 * VM_INSTRUCTION_ERROR is not shadowed
6372 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6374 /* TODO: not to reset guest simply here. */
6375 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6376 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6379 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6381 struct vcpu_vmx *vmx =
6382 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6384 vmx->nested.preemption_timer_expired = true;
6385 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6386 kvm_vcpu_kick(&vmx->vcpu);
6388 return HRTIMER_NORESTART;
6392 * Decode the memory-address operand of a vmx instruction, as recorded on an
6393 * exit caused by such an instruction (run by a guest hypervisor).
6394 * On success, returns 0. When the operand is invalid, returns 1 and throws
6397 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6398 unsigned long exit_qualification,
6399 u32 vmx_instruction_info, gva_t *ret)
6402 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6403 * Execution", on an exit, vmx_instruction_info holds most of the
6404 * addressing components of the operand. Only the displacement part
6405 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6406 * For how an actual address is calculated from all these components,
6407 * refer to Vol. 1, "Operand Addressing".
6409 int scaling = vmx_instruction_info & 3;
6410 int addr_size = (vmx_instruction_info >> 7) & 7;
6411 bool is_reg = vmx_instruction_info & (1u << 10);
6412 int seg_reg = (vmx_instruction_info >> 15) & 7;
6413 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6414 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6415 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6416 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6419 kvm_queue_exception(vcpu, UD_VECTOR);
6423 /* Addr = segment_base + offset */
6424 /* offset = base + [index * scale] + displacement */
6425 *ret = vmx_get_segment_base(vcpu, seg_reg);
6427 *ret += kvm_register_read(vcpu, base_reg);
6429 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6430 *ret += exit_qualification; /* holds the displacement */
6432 if (addr_size == 1) /* 32 bit */
6436 * TODO: throw #GP (and return 1) in various cases that the VM*
6437 * instructions require it - e.g., offset beyond segment limit,
6438 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6439 * address, and so on. Currently these are not checked.
6445 * This function performs the various checks including
6446 * - if it's 4KB aligned
6447 * - No bits beyond the physical address width are set
6448 * - Returns 0 on success or else 1
6449 * (Intel SDM Section 30.3)
6451 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6456 struct x86_exception e;
6458 struct vcpu_vmx *vmx = to_vmx(vcpu);
6459 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6461 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6462 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6465 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6466 sizeof(vmptr), &e)) {
6467 kvm_inject_page_fault(vcpu, &e);
6471 switch (exit_reason) {
6472 case EXIT_REASON_VMON:
6475 * The first 4 bytes of VMXON region contain the supported
6476 * VMCS revision identifier
6478 * Note - IA32_VMX_BASIC[48] will never be 1
6479 * for the nested case;
6480 * which replaces physical address width with 32
6483 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6484 nested_vmx_failInvalid(vcpu);
6485 skip_emulated_instruction(vcpu);
6489 page = nested_get_page(vcpu, vmptr);
6491 *(u32 *)kmap(page) != VMCS12_REVISION) {
6492 nested_vmx_failInvalid(vcpu);
6494 skip_emulated_instruction(vcpu);
6498 vmx->nested.vmxon_ptr = vmptr;
6500 case EXIT_REASON_VMCLEAR:
6501 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6502 nested_vmx_failValid(vcpu,
6503 VMXERR_VMCLEAR_INVALID_ADDRESS);
6504 skip_emulated_instruction(vcpu);
6508 if (vmptr == vmx->nested.vmxon_ptr) {
6509 nested_vmx_failValid(vcpu,
6510 VMXERR_VMCLEAR_VMXON_POINTER);
6511 skip_emulated_instruction(vcpu);
6515 case EXIT_REASON_VMPTRLD:
6516 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6517 nested_vmx_failValid(vcpu,
6518 VMXERR_VMPTRLD_INVALID_ADDRESS);
6519 skip_emulated_instruction(vcpu);
6523 if (vmptr == vmx->nested.vmxon_ptr) {
6524 nested_vmx_failValid(vcpu,
6525 VMXERR_VMCLEAR_VMXON_POINTER);
6526 skip_emulated_instruction(vcpu);
6531 return 1; /* shouldn't happen */
6540 * Emulate the VMXON instruction.
6541 * Currently, we just remember that VMX is active, and do not save or even
6542 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6543 * do not currently need to store anything in that guest-allocated memory
6544 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6545 * argument is different from the VMXON pointer (which the spec says they do).
6547 static int handle_vmon(struct kvm_vcpu *vcpu)
6549 struct kvm_segment cs;
6550 struct vcpu_vmx *vmx = to_vmx(vcpu);
6551 struct vmcs *shadow_vmcs;
6552 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6553 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6555 /* The Intel VMX Instruction Reference lists a bunch of bits that
6556 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6557 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6558 * Otherwise, we should fail with #UD. We test these now:
6560 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6561 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6562 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6563 kvm_queue_exception(vcpu, UD_VECTOR);
6567 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6568 if (is_long_mode(vcpu) && !cs.l) {
6569 kvm_queue_exception(vcpu, UD_VECTOR);
6573 if (vmx_get_cpl(vcpu)) {
6574 kvm_inject_gp(vcpu, 0);
6578 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6581 if (vmx->nested.vmxon) {
6582 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6583 skip_emulated_instruction(vcpu);
6587 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6588 != VMXON_NEEDED_FEATURES) {
6589 kvm_inject_gp(vcpu, 0);
6593 if (enable_shadow_vmcs) {
6594 shadow_vmcs = alloc_vmcs();
6597 /* mark vmcs as shadow */
6598 shadow_vmcs->revision_id |= (1u << 31);
6599 /* init shadow vmcs */
6600 vmcs_clear(shadow_vmcs);
6601 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6604 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6605 vmx->nested.vmcs02_num = 0;
6607 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6609 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6611 vmx->nested.vmxon = true;
6613 skip_emulated_instruction(vcpu);
6614 nested_vmx_succeed(vcpu);
6619 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6620 * for running VMX instructions (except VMXON, whose prerequisites are
6621 * slightly different). It also specifies what exception to inject otherwise.
6623 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6625 struct kvm_segment cs;
6626 struct vcpu_vmx *vmx = to_vmx(vcpu);
6628 if (!vmx->nested.vmxon) {
6629 kvm_queue_exception(vcpu, UD_VECTOR);
6633 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6634 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6635 (is_long_mode(vcpu) && !cs.l)) {
6636 kvm_queue_exception(vcpu, UD_VECTOR);
6640 if (vmx_get_cpl(vcpu)) {
6641 kvm_inject_gp(vcpu, 0);
6648 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6651 if (vmx->nested.current_vmptr == -1ull)
6654 /* current_vmptr and current_vmcs12 are always set/reset together */
6655 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6658 if (enable_shadow_vmcs) {
6659 /* copy to memory all shadowed fields in case
6660 they were modified */
6661 copy_shadow_to_vmcs12(vmx);
6662 vmx->nested.sync_shadow_vmcs = false;
6663 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6664 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6665 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6666 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6668 vmx->nested.posted_intr_nv = -1;
6669 kunmap(vmx->nested.current_vmcs12_page);
6670 nested_release_page(vmx->nested.current_vmcs12_page);
6671 vmx->nested.current_vmptr = -1ull;
6672 vmx->nested.current_vmcs12 = NULL;
6676 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6677 * just stops using VMX.
6679 static void free_nested(struct vcpu_vmx *vmx)
6681 if (!vmx->nested.vmxon)
6684 vmx->nested.vmxon = false;
6685 nested_release_vmcs12(vmx);
6686 if (enable_shadow_vmcs)
6687 free_vmcs(vmx->nested.current_shadow_vmcs);
6688 /* Unpin physical memory we referred to in current vmcs02 */
6689 if (vmx->nested.apic_access_page) {
6690 nested_release_page(vmx->nested.apic_access_page);
6691 vmx->nested.apic_access_page = NULL;
6693 if (vmx->nested.virtual_apic_page) {
6694 nested_release_page(vmx->nested.virtual_apic_page);
6695 vmx->nested.virtual_apic_page = NULL;
6697 if (vmx->nested.pi_desc_page) {
6698 kunmap(vmx->nested.pi_desc_page);
6699 nested_release_page(vmx->nested.pi_desc_page);
6700 vmx->nested.pi_desc_page = NULL;
6701 vmx->nested.pi_desc = NULL;
6704 nested_free_all_saved_vmcss(vmx);
6707 /* Emulate the VMXOFF instruction */
6708 static int handle_vmoff(struct kvm_vcpu *vcpu)
6710 if (!nested_vmx_check_permission(vcpu))
6712 free_nested(to_vmx(vcpu));
6713 skip_emulated_instruction(vcpu);
6714 nested_vmx_succeed(vcpu);
6718 /* Emulate the VMCLEAR instruction */
6719 static int handle_vmclear(struct kvm_vcpu *vcpu)
6721 struct vcpu_vmx *vmx = to_vmx(vcpu);
6723 struct vmcs12 *vmcs12;
6726 if (!nested_vmx_check_permission(vcpu))
6729 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6732 if (vmptr == vmx->nested.current_vmptr)
6733 nested_release_vmcs12(vmx);
6735 page = nested_get_page(vcpu, vmptr);
6738 * For accurate processor emulation, VMCLEAR beyond available
6739 * physical memory should do nothing at all. However, it is
6740 * possible that a nested vmx bug, not a guest hypervisor bug,
6741 * resulted in this case, so let's shut down before doing any
6744 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6747 vmcs12 = kmap(page);
6748 vmcs12->launch_state = 0;
6750 nested_release_page(page);
6752 nested_free_vmcs02(vmx, vmptr);
6754 skip_emulated_instruction(vcpu);
6755 nested_vmx_succeed(vcpu);
6759 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6761 /* Emulate the VMLAUNCH instruction */
6762 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6764 return nested_vmx_run(vcpu, true);
6767 /* Emulate the VMRESUME instruction */
6768 static int handle_vmresume(struct kvm_vcpu *vcpu)
6771 return nested_vmx_run(vcpu, false);
6774 enum vmcs_field_type {
6775 VMCS_FIELD_TYPE_U16 = 0,
6776 VMCS_FIELD_TYPE_U64 = 1,
6777 VMCS_FIELD_TYPE_U32 = 2,
6778 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6781 static inline int vmcs_field_type(unsigned long field)
6783 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6784 return VMCS_FIELD_TYPE_U32;
6785 return (field >> 13) & 0x3 ;
6788 static inline int vmcs_field_readonly(unsigned long field)
6790 return (((field >> 10) & 0x3) == 1);
6794 * Read a vmcs12 field. Since these can have varying lengths and we return
6795 * one type, we chose the biggest type (u64) and zero-extend the return value
6796 * to that size. Note that the caller, handle_vmread, might need to use only
6797 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6798 * 64-bit fields are to be returned).
6800 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6801 unsigned long field, u64 *ret)
6803 short offset = vmcs_field_to_offset(field);
6809 p = ((char *)(get_vmcs12(vcpu))) + offset;
6811 switch (vmcs_field_type(field)) {
6812 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6813 *ret = *((natural_width *)p);
6815 case VMCS_FIELD_TYPE_U16:
6818 case VMCS_FIELD_TYPE_U32:
6821 case VMCS_FIELD_TYPE_U64:
6831 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6832 unsigned long field, u64 field_value){
6833 short offset = vmcs_field_to_offset(field);
6834 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6838 switch (vmcs_field_type(field)) {
6839 case VMCS_FIELD_TYPE_U16:
6840 *(u16 *)p = field_value;
6842 case VMCS_FIELD_TYPE_U32:
6843 *(u32 *)p = field_value;
6845 case VMCS_FIELD_TYPE_U64:
6846 *(u64 *)p = field_value;
6848 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6849 *(natural_width *)p = field_value;
6858 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6861 unsigned long field;
6863 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6864 const unsigned long *fields = shadow_read_write_fields;
6865 const int num_fields = max_shadow_read_write_fields;
6869 vmcs_load(shadow_vmcs);
6871 for (i = 0; i < num_fields; i++) {
6873 switch (vmcs_field_type(field)) {
6874 case VMCS_FIELD_TYPE_U16:
6875 field_value = vmcs_read16(field);
6877 case VMCS_FIELD_TYPE_U32:
6878 field_value = vmcs_read32(field);
6880 case VMCS_FIELD_TYPE_U64:
6881 field_value = vmcs_read64(field);
6883 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6884 field_value = vmcs_readl(field);
6890 vmcs12_write_any(&vmx->vcpu, field, field_value);
6893 vmcs_clear(shadow_vmcs);
6894 vmcs_load(vmx->loaded_vmcs->vmcs);
6899 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6901 const unsigned long *fields[] = {
6902 shadow_read_write_fields,
6903 shadow_read_only_fields
6905 const int max_fields[] = {
6906 max_shadow_read_write_fields,
6907 max_shadow_read_only_fields
6910 unsigned long field;
6911 u64 field_value = 0;
6912 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6914 vmcs_load(shadow_vmcs);
6916 for (q = 0; q < ARRAY_SIZE(fields); q++) {
6917 for (i = 0; i < max_fields[q]; i++) {
6918 field = fields[q][i];
6919 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6921 switch (vmcs_field_type(field)) {
6922 case VMCS_FIELD_TYPE_U16:
6923 vmcs_write16(field, (u16)field_value);
6925 case VMCS_FIELD_TYPE_U32:
6926 vmcs_write32(field, (u32)field_value);
6928 case VMCS_FIELD_TYPE_U64:
6929 vmcs_write64(field, (u64)field_value);
6931 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6932 vmcs_writel(field, (long)field_value);
6941 vmcs_clear(shadow_vmcs);
6942 vmcs_load(vmx->loaded_vmcs->vmcs);
6946 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6947 * used before) all generate the same failure when it is missing.
6949 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6951 struct vcpu_vmx *vmx = to_vmx(vcpu);
6952 if (vmx->nested.current_vmptr == -1ull) {
6953 nested_vmx_failInvalid(vcpu);
6954 skip_emulated_instruction(vcpu);
6960 static int handle_vmread(struct kvm_vcpu *vcpu)
6962 unsigned long field;
6964 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6965 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6968 if (!nested_vmx_check_permission(vcpu) ||
6969 !nested_vmx_check_vmcs12(vcpu))
6972 /* Decode instruction info and find the field to read */
6973 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6974 /* Read the field, zero-extended to a u64 field_value */
6975 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6976 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6977 skip_emulated_instruction(vcpu);
6981 * Now copy part of this value to register or memory, as requested.
6982 * Note that the number of bits actually copied is 32 or 64 depending
6983 * on the guest's mode (32 or 64 bit), not on the given field's length.
6985 if (vmx_instruction_info & (1u << 10)) {
6986 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6989 if (get_vmx_mem_address(vcpu, exit_qualification,
6990 vmx_instruction_info, &gva))
6992 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6993 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6994 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6997 nested_vmx_succeed(vcpu);
6998 skip_emulated_instruction(vcpu);
7003 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7005 unsigned long field;
7007 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7008 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7009 /* The value to write might be 32 or 64 bits, depending on L1's long
7010 * mode, and eventually we need to write that into a field of several
7011 * possible lengths. The code below first zero-extends the value to 64
7012 * bit (field_value), and then copies only the approriate number of
7013 * bits into the vmcs12 field.
7015 u64 field_value = 0;
7016 struct x86_exception e;
7018 if (!nested_vmx_check_permission(vcpu) ||
7019 !nested_vmx_check_vmcs12(vcpu))
7022 if (vmx_instruction_info & (1u << 10))
7023 field_value = kvm_register_readl(vcpu,
7024 (((vmx_instruction_info) >> 3) & 0xf));
7026 if (get_vmx_mem_address(vcpu, exit_qualification,
7027 vmx_instruction_info, &gva))
7029 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7030 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7031 kvm_inject_page_fault(vcpu, &e);
7037 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7038 if (vmcs_field_readonly(field)) {
7039 nested_vmx_failValid(vcpu,
7040 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7041 skip_emulated_instruction(vcpu);
7045 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7046 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7047 skip_emulated_instruction(vcpu);
7051 nested_vmx_succeed(vcpu);
7052 skip_emulated_instruction(vcpu);
7056 /* Emulate the VMPTRLD instruction */
7057 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7059 struct vcpu_vmx *vmx = to_vmx(vcpu);
7063 if (!nested_vmx_check_permission(vcpu))
7066 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7069 if (vmx->nested.current_vmptr != vmptr) {
7070 struct vmcs12 *new_vmcs12;
7072 page = nested_get_page(vcpu, vmptr);
7074 nested_vmx_failInvalid(vcpu);
7075 skip_emulated_instruction(vcpu);
7078 new_vmcs12 = kmap(page);
7079 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7081 nested_release_page_clean(page);
7082 nested_vmx_failValid(vcpu,
7083 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7084 skip_emulated_instruction(vcpu);
7088 nested_release_vmcs12(vmx);
7089 vmx->nested.current_vmptr = vmptr;
7090 vmx->nested.current_vmcs12 = new_vmcs12;
7091 vmx->nested.current_vmcs12_page = page;
7092 if (enable_shadow_vmcs) {
7093 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7094 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7095 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7096 vmcs_write64(VMCS_LINK_POINTER,
7097 __pa(vmx->nested.current_shadow_vmcs));
7098 vmx->nested.sync_shadow_vmcs = true;
7102 nested_vmx_succeed(vcpu);
7103 skip_emulated_instruction(vcpu);
7107 /* Emulate the VMPTRST instruction */
7108 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7110 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7111 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7113 struct x86_exception e;
7115 if (!nested_vmx_check_permission(vcpu))
7118 if (get_vmx_mem_address(vcpu, exit_qualification,
7119 vmx_instruction_info, &vmcs_gva))
7121 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7122 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7123 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7125 kvm_inject_page_fault(vcpu, &e);
7128 nested_vmx_succeed(vcpu);
7129 skip_emulated_instruction(vcpu);
7133 /* Emulate the INVEPT instruction */
7134 static int handle_invept(struct kvm_vcpu *vcpu)
7136 struct vcpu_vmx *vmx = to_vmx(vcpu);
7137 u32 vmx_instruction_info, types;
7140 struct x86_exception e;
7145 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7146 SECONDARY_EXEC_ENABLE_EPT) ||
7147 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7148 kvm_queue_exception(vcpu, UD_VECTOR);
7152 if (!nested_vmx_check_permission(vcpu))
7155 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7156 kvm_queue_exception(vcpu, UD_VECTOR);
7160 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7161 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7163 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7165 if (!(types & (1UL << type))) {
7166 nested_vmx_failValid(vcpu,
7167 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7171 /* According to the Intel VMX instruction reference, the memory
7172 * operand is read even if it isn't needed (e.g., for type==global)
7174 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7175 vmx_instruction_info, &gva))
7177 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7178 sizeof(operand), &e)) {
7179 kvm_inject_page_fault(vcpu, &e);
7184 case VMX_EPT_EXTENT_GLOBAL:
7185 kvm_mmu_sync_roots(vcpu);
7186 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7187 nested_vmx_succeed(vcpu);
7190 /* Trap single context invalidation invept calls */
7195 skip_emulated_instruction(vcpu);
7199 static int handle_invvpid(struct kvm_vcpu *vcpu)
7201 kvm_queue_exception(vcpu, UD_VECTOR);
7205 static int handle_pml_full(struct kvm_vcpu *vcpu)
7207 unsigned long exit_qualification;
7209 trace_kvm_pml_full(vcpu->vcpu_id);
7211 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7214 * PML buffer FULL happened while executing iret from NMI,
7215 * "blocked by NMI" bit has to be set before next VM entry.
7217 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7218 cpu_has_virtual_nmis() &&
7219 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7220 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7221 GUEST_INTR_STATE_NMI);
7224 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7225 * here.., and there's no userspace involvement needed for PML.
7231 * The exit handlers return 1 if the exit was handled fully and guest execution
7232 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7233 * to be done to userspace and return 0.
7235 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7236 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7237 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7238 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7239 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7240 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7241 [EXIT_REASON_CR_ACCESS] = handle_cr,
7242 [EXIT_REASON_DR_ACCESS] = handle_dr,
7243 [EXIT_REASON_CPUID] = handle_cpuid,
7244 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7245 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7246 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7247 [EXIT_REASON_HLT] = handle_halt,
7248 [EXIT_REASON_INVD] = handle_invd,
7249 [EXIT_REASON_INVLPG] = handle_invlpg,
7250 [EXIT_REASON_RDPMC] = handle_rdpmc,
7251 [EXIT_REASON_VMCALL] = handle_vmcall,
7252 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7253 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7254 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7255 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7256 [EXIT_REASON_VMREAD] = handle_vmread,
7257 [EXIT_REASON_VMRESUME] = handle_vmresume,
7258 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7259 [EXIT_REASON_VMOFF] = handle_vmoff,
7260 [EXIT_REASON_VMON] = handle_vmon,
7261 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7262 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7263 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7264 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7265 [EXIT_REASON_WBINVD] = handle_wbinvd,
7266 [EXIT_REASON_XSETBV] = handle_xsetbv,
7267 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7268 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7269 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7270 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7271 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7272 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7273 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7274 [EXIT_REASON_INVEPT] = handle_invept,
7275 [EXIT_REASON_INVVPID] = handle_invvpid,
7276 [EXIT_REASON_XSAVES] = handle_xsaves,
7277 [EXIT_REASON_XRSTORS] = handle_xrstors,
7278 [EXIT_REASON_PML_FULL] = handle_pml_full,
7281 static const int kvm_vmx_max_exit_handlers =
7282 ARRAY_SIZE(kvm_vmx_exit_handlers);
7284 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7285 struct vmcs12 *vmcs12)
7287 unsigned long exit_qualification;
7288 gpa_t bitmap, last_bitmap;
7293 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7294 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7296 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7298 port = exit_qualification >> 16;
7299 size = (exit_qualification & 7) + 1;
7301 last_bitmap = (gpa_t)-1;
7306 bitmap = vmcs12->io_bitmap_a;
7307 else if (port < 0x10000)
7308 bitmap = vmcs12->io_bitmap_b;
7311 bitmap += (port & 0x7fff) / 8;
7313 if (last_bitmap != bitmap)
7314 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7316 if (b & (1 << (port & 7)))
7321 last_bitmap = bitmap;
7328 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7329 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7330 * disinterest in the current event (read or write a specific MSR) by using an
7331 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7333 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7334 struct vmcs12 *vmcs12, u32 exit_reason)
7336 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7339 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7343 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7344 * for the four combinations of read/write and low/high MSR numbers.
7345 * First we need to figure out which of the four to use:
7347 bitmap = vmcs12->msr_bitmap;
7348 if (exit_reason == EXIT_REASON_MSR_WRITE)
7350 if (msr_index >= 0xc0000000) {
7351 msr_index -= 0xc0000000;
7355 /* Then read the msr_index'th bit from this bitmap: */
7356 if (msr_index < 1024*8) {
7358 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7360 return 1 & (b >> (msr_index & 7));
7362 return 1; /* let L1 handle the wrong parameter */
7366 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7367 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7368 * intercept (via guest_host_mask etc.) the current event.
7370 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7371 struct vmcs12 *vmcs12)
7373 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7374 int cr = exit_qualification & 15;
7375 int reg = (exit_qualification >> 8) & 15;
7376 unsigned long val = kvm_register_readl(vcpu, reg);
7378 switch ((exit_qualification >> 4) & 3) {
7379 case 0: /* mov to cr */
7382 if (vmcs12->cr0_guest_host_mask &
7383 (val ^ vmcs12->cr0_read_shadow))
7387 if ((vmcs12->cr3_target_count >= 1 &&
7388 vmcs12->cr3_target_value0 == val) ||
7389 (vmcs12->cr3_target_count >= 2 &&
7390 vmcs12->cr3_target_value1 == val) ||
7391 (vmcs12->cr3_target_count >= 3 &&
7392 vmcs12->cr3_target_value2 == val) ||
7393 (vmcs12->cr3_target_count >= 4 &&
7394 vmcs12->cr3_target_value3 == val))
7396 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7400 if (vmcs12->cr4_guest_host_mask &
7401 (vmcs12->cr4_read_shadow ^ val))
7405 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7411 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7412 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7415 case 1: /* mov from cr */
7418 if (vmcs12->cpu_based_vm_exec_control &
7419 CPU_BASED_CR3_STORE_EXITING)
7423 if (vmcs12->cpu_based_vm_exec_control &
7424 CPU_BASED_CR8_STORE_EXITING)
7431 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7432 * cr0. Other attempted changes are ignored, with no exit.
7434 if (vmcs12->cr0_guest_host_mask & 0xe &
7435 (val ^ vmcs12->cr0_read_shadow))
7437 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7438 !(vmcs12->cr0_read_shadow & 0x1) &&
7447 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7448 * should handle it ourselves in L0 (and then continue L2). Only call this
7449 * when in is_guest_mode (L2).
7451 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7453 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7454 struct vcpu_vmx *vmx = to_vmx(vcpu);
7455 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7456 u32 exit_reason = vmx->exit_reason;
7458 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7459 vmcs_readl(EXIT_QUALIFICATION),
7460 vmx->idt_vectoring_info,
7462 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7465 if (vmx->nested.nested_run_pending)
7468 if (unlikely(vmx->fail)) {
7469 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7470 vmcs_read32(VM_INSTRUCTION_ERROR));
7474 switch (exit_reason) {
7475 case EXIT_REASON_EXCEPTION_NMI:
7476 if (!is_exception(intr_info))
7478 else if (is_page_fault(intr_info))
7480 else if (is_no_device(intr_info) &&
7481 !(vmcs12->guest_cr0 & X86_CR0_TS))
7483 return vmcs12->exception_bitmap &
7484 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7485 case EXIT_REASON_EXTERNAL_INTERRUPT:
7487 case EXIT_REASON_TRIPLE_FAULT:
7489 case EXIT_REASON_PENDING_INTERRUPT:
7490 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7491 case EXIT_REASON_NMI_WINDOW:
7492 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7493 case EXIT_REASON_TASK_SWITCH:
7495 case EXIT_REASON_CPUID:
7496 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7499 case EXIT_REASON_HLT:
7500 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7501 case EXIT_REASON_INVD:
7503 case EXIT_REASON_INVLPG:
7504 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7505 case EXIT_REASON_RDPMC:
7506 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7507 case EXIT_REASON_RDTSC:
7508 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7509 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7510 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7511 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7512 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7513 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7514 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7516 * VMX instructions trap unconditionally. This allows L1 to
7517 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7520 case EXIT_REASON_CR_ACCESS:
7521 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7522 case EXIT_REASON_DR_ACCESS:
7523 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7524 case EXIT_REASON_IO_INSTRUCTION:
7525 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7526 case EXIT_REASON_MSR_READ:
7527 case EXIT_REASON_MSR_WRITE:
7528 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7529 case EXIT_REASON_INVALID_STATE:
7531 case EXIT_REASON_MWAIT_INSTRUCTION:
7532 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7533 case EXIT_REASON_MONITOR_INSTRUCTION:
7534 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7535 case EXIT_REASON_PAUSE_INSTRUCTION:
7536 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7537 nested_cpu_has2(vmcs12,
7538 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7539 case EXIT_REASON_MCE_DURING_VMENTRY:
7541 case EXIT_REASON_TPR_BELOW_THRESHOLD:
7542 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7543 case EXIT_REASON_APIC_ACCESS:
7544 return nested_cpu_has2(vmcs12,
7545 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7546 case EXIT_REASON_APIC_WRITE:
7547 case EXIT_REASON_EOI_INDUCED:
7548 /* apic_write and eoi_induced should exit unconditionally. */
7550 case EXIT_REASON_EPT_VIOLATION:
7552 * L0 always deals with the EPT violation. If nested EPT is
7553 * used, and the nested mmu code discovers that the address is
7554 * missing in the guest EPT table (EPT12), the EPT violation
7555 * will be injected with nested_ept_inject_page_fault()
7558 case EXIT_REASON_EPT_MISCONFIG:
7560 * L2 never uses directly L1's EPT, but rather L0's own EPT
7561 * table (shadow on EPT) or a merged EPT table that L0 built
7562 * (EPT on EPT). So any problems with the structure of the
7563 * table is L0's fault.
7566 case EXIT_REASON_WBINVD:
7567 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7568 case EXIT_REASON_XSETBV:
7570 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7572 * This should never happen, since it is not possible to
7573 * set XSS to a non-zero value---neither in L1 nor in L2.
7574 * If if it were, XSS would have to be checked against
7575 * the XSS exit bitmap in vmcs12.
7577 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7583 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7585 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7586 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7589 static int vmx_enable_pml(struct vcpu_vmx *vmx)
7591 struct page *pml_pg;
7594 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7598 vmx->pml_pg = pml_pg;
7600 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7601 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7603 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7604 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7605 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7610 static void vmx_disable_pml(struct vcpu_vmx *vmx)
7614 ASSERT(vmx->pml_pg);
7615 __free_page(vmx->pml_pg);
7618 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7619 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7620 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7623 static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7625 struct kvm *kvm = vmx->vcpu.kvm;
7629 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7631 /* Do nothing if PML buffer is empty */
7632 if (pml_idx == (PML_ENTITY_NUM - 1))
7635 /* PML index always points to next available PML buffer entity */
7636 if (pml_idx >= PML_ENTITY_NUM)
7641 pml_buf = page_address(vmx->pml_pg);
7642 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7645 gpa = pml_buf[pml_idx];
7646 WARN_ON(gpa & (PAGE_SIZE - 1));
7647 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7650 /* reset PML index */
7651 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7655 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7656 * Called before reporting dirty_bitmap to userspace.
7658 static void kvm_flush_pml_buffers(struct kvm *kvm)
7661 struct kvm_vcpu *vcpu;
7663 * We only need to kick vcpu out of guest mode here, as PML buffer
7664 * is flushed at beginning of all VMEXITs, and it's obvious that only
7665 * vcpus running in guest are possible to have unflushed GPAs in PML
7668 kvm_for_each_vcpu(i, vcpu, kvm)
7669 kvm_vcpu_kick(vcpu);
7673 * The guest has exited. See if we can fix it or if we need userspace
7676 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7678 struct vcpu_vmx *vmx = to_vmx(vcpu);
7679 u32 exit_reason = vmx->exit_reason;
7680 u32 vectoring_info = vmx->idt_vectoring_info;
7683 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7684 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7685 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7686 * mode as if vcpus is in root mode, the PML buffer must has been
7690 vmx_flush_pml_buffer(vmx);
7692 /* If guest state is invalid, start emulating */
7693 if (vmx->emulation_required)
7694 return handle_invalid_guest_state(vcpu);
7696 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7697 nested_vmx_vmexit(vcpu, exit_reason,
7698 vmcs_read32(VM_EXIT_INTR_INFO),
7699 vmcs_readl(EXIT_QUALIFICATION));
7703 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7704 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7705 vcpu->run->fail_entry.hardware_entry_failure_reason
7710 if (unlikely(vmx->fail)) {
7711 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7712 vcpu->run->fail_entry.hardware_entry_failure_reason
7713 = vmcs_read32(VM_INSTRUCTION_ERROR);
7719 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7720 * delivery event since it indicates guest is accessing MMIO.
7721 * The vm-exit can be triggered again after return to guest that
7722 * will cause infinite loop.
7724 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7725 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7726 exit_reason != EXIT_REASON_EPT_VIOLATION &&
7727 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7728 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7729 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7730 vcpu->run->internal.ndata = 2;
7731 vcpu->run->internal.data[0] = vectoring_info;
7732 vcpu->run->internal.data[1] = exit_reason;
7736 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7737 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7738 get_vmcs12(vcpu))))) {
7739 if (vmx_interrupt_allowed(vcpu)) {
7740 vmx->soft_vnmi_blocked = 0;
7741 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7742 vcpu->arch.nmi_pending) {
7744 * This CPU don't support us in finding the end of an
7745 * NMI-blocked window if the guest runs with IRQs
7746 * disabled. So we pull the trigger after 1 s of
7747 * futile waiting, but inform the user about this.
7749 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7750 "state on VCPU %d after 1 s timeout\n",
7751 __func__, vcpu->vcpu_id);
7752 vmx->soft_vnmi_blocked = 0;
7756 if (exit_reason < kvm_vmx_max_exit_handlers
7757 && kvm_vmx_exit_handlers[exit_reason])
7758 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7760 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7761 kvm_queue_exception(vcpu, UD_VECTOR);
7766 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7768 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7770 if (is_guest_mode(vcpu) &&
7771 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7774 if (irr == -1 || tpr < irr) {
7775 vmcs_write32(TPR_THRESHOLD, 0);
7779 vmcs_write32(TPR_THRESHOLD, irr);
7782 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7784 u32 sec_exec_control;
7787 * There is not point to enable virtualize x2apic without enable
7790 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7791 !vmx_vm_has_apicv(vcpu->kvm))
7794 if (!vm_need_tpr_shadow(vcpu->kvm))
7797 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7800 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7801 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7803 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7804 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7806 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7808 vmx_set_msr_bitmap(vcpu);
7811 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7813 struct vcpu_vmx *vmx = to_vmx(vcpu);
7816 * Currently we do not handle the nested case where L2 has an
7817 * APIC access page of its own; that page is still pinned.
7818 * Hence, we skip the case where the VCPU is in guest mode _and_
7819 * L1 prepared an APIC access page for L2.
7821 * For the case where L1 and L2 share the same APIC access page
7822 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7823 * in the vmcs12), this function will only update either the vmcs01
7824 * or the vmcs02. If the former, the vmcs02 will be updated by
7825 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7826 * the next L2->L1 exit.
7828 if (!is_guest_mode(vcpu) ||
7829 !nested_cpu_has2(vmx->nested.current_vmcs12,
7830 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7831 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7834 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7842 status = vmcs_read16(GUEST_INTR_STATUS);
7847 vmcs_write16(GUEST_INTR_STATUS, status);
7851 static void vmx_set_rvi(int vector)
7859 status = vmcs_read16(GUEST_INTR_STATUS);
7860 old = (u8)status & 0xff;
7861 if ((u8)vector != old) {
7863 status |= (u8)vector;
7864 vmcs_write16(GUEST_INTR_STATUS, status);
7868 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7870 if (!is_guest_mode(vcpu)) {
7871 vmx_set_rvi(max_irr);
7879 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7882 if (nested_exit_on_intr(vcpu))
7886 * Else, fall back to pre-APICv interrupt injection since L2
7887 * is run without virtual interrupt delivery.
7889 if (!kvm_event_needs_reinjection(vcpu) &&
7890 vmx_interrupt_allowed(vcpu)) {
7891 kvm_queue_interrupt(vcpu, max_irr, false);
7892 vmx_inject_irq(vcpu);
7896 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7898 if (!vmx_vm_has_apicv(vcpu->kvm))
7901 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7902 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7903 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7904 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7907 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7911 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7912 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7915 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7916 exit_intr_info = vmx->exit_intr_info;
7918 /* Handle machine checks before interrupts are enabled */
7919 if (is_machine_check(exit_intr_info))
7920 kvm_machine_check();
7922 /* We need to handle NMIs before interrupts are enabled */
7923 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7924 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7925 kvm_before_handle_nmi(&vmx->vcpu);
7927 kvm_after_handle_nmi(&vmx->vcpu);
7931 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7933 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7936 * If external interrupt exists, IF bit is set in rflags/eflags on the
7937 * interrupt stack frame, and interrupt will be enabled on a return
7938 * from interrupt handler.
7940 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7941 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7942 unsigned int vector;
7943 unsigned long entry;
7945 struct vcpu_vmx *vmx = to_vmx(vcpu);
7946 #ifdef CONFIG_X86_64
7950 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7951 desc = (gate_desc *)vmx->host_idt_base + vector;
7952 entry = gate_offset(*desc);
7954 #ifdef CONFIG_X86_64
7955 "mov %%" _ASM_SP ", %[sp]\n\t"
7956 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7961 "orl $0x200, (%%" _ASM_SP ")\n\t"
7962 __ASM_SIZE(push) " $%c[cs]\n\t"
7963 "call *%[entry]\n\t"
7965 #ifdef CONFIG_X86_64
7970 [ss]"i"(__KERNEL_DS),
7971 [cs]"i"(__KERNEL_CS)
7977 static bool vmx_mpx_supported(void)
7979 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7980 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7983 static bool vmx_xsaves_supported(void)
7985 return vmcs_config.cpu_based_2nd_exec_ctrl &
7986 SECONDARY_EXEC_XSAVES;
7989 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7994 bool idtv_info_valid;
7996 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7998 if (cpu_has_virtual_nmis()) {
7999 if (vmx->nmi_known_unmasked)
8002 * Can't use vmx->exit_intr_info since we're not sure what
8003 * the exit reason is.
8005 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8006 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8007 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8009 * SDM 3: 27.7.1.2 (September 2008)
8010 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8011 * a guest IRET fault.
8012 * SDM 3: 23.2.2 (September 2008)
8013 * Bit 12 is undefined in any of the following cases:
8014 * If the VM exit sets the valid bit in the IDT-vectoring
8015 * information field.
8016 * If the VM exit is due to a double fault.
8018 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8019 vector != DF_VECTOR && !idtv_info_valid)
8020 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8021 GUEST_INTR_STATE_NMI);
8023 vmx->nmi_known_unmasked =
8024 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8025 & GUEST_INTR_STATE_NMI);
8026 } else if (unlikely(vmx->soft_vnmi_blocked))
8027 vmx->vnmi_blocked_time +=
8028 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8031 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8032 u32 idt_vectoring_info,
8033 int instr_len_field,
8034 int error_code_field)
8038 bool idtv_info_valid;
8040 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8042 vcpu->arch.nmi_injected = false;
8043 kvm_clear_exception_queue(vcpu);
8044 kvm_clear_interrupt_queue(vcpu);
8046 if (!idtv_info_valid)
8049 kvm_make_request(KVM_REQ_EVENT, vcpu);
8051 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8052 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8055 case INTR_TYPE_NMI_INTR:
8056 vcpu->arch.nmi_injected = true;
8058 * SDM 3: 27.7.1.2 (September 2008)
8059 * Clear bit "block by NMI" before VM entry if a NMI
8062 vmx_set_nmi_mask(vcpu, false);
8064 case INTR_TYPE_SOFT_EXCEPTION:
8065 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8067 case INTR_TYPE_HARD_EXCEPTION:
8068 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8069 u32 err = vmcs_read32(error_code_field);
8070 kvm_requeue_exception_e(vcpu, vector, err);
8072 kvm_requeue_exception(vcpu, vector);
8074 case INTR_TYPE_SOFT_INTR:
8075 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8077 case INTR_TYPE_EXT_INTR:
8078 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8085 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8087 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8088 VM_EXIT_INSTRUCTION_LEN,
8089 IDT_VECTORING_ERROR_CODE);
8092 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8094 __vmx_complete_interrupts(vcpu,
8095 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8096 VM_ENTRY_INSTRUCTION_LEN,
8097 VM_ENTRY_EXCEPTION_ERROR_CODE);
8099 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8102 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8105 struct perf_guest_switch_msr *msrs;
8107 msrs = perf_guest_get_msrs(&nr_msrs);
8112 for (i = 0; i < nr_msrs; i++)
8113 if (msrs[i].host == msrs[i].guest)
8114 clear_atomic_switch_msr(vmx, msrs[i].msr);
8116 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8120 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8122 struct vcpu_vmx *vmx = to_vmx(vcpu);
8123 unsigned long debugctlmsr, cr4;
8125 /* Record the guest's net vcpu time for enforced NMI injections. */
8126 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8127 vmx->entry_time = ktime_get();
8129 /* Don't enter VMX if guest state is invalid, let the exit handler
8130 start emulation until we arrive back to a valid state */
8131 if (vmx->emulation_required)
8134 if (vmx->ple_window_dirty) {
8135 vmx->ple_window_dirty = false;
8136 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8139 if (vmx->nested.sync_shadow_vmcs) {
8140 copy_vmcs12_to_shadow(vmx);
8141 vmx->nested.sync_shadow_vmcs = false;
8144 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8145 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8146 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8147 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8149 cr4 = cr4_read_shadow();
8150 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8151 vmcs_writel(HOST_CR4, cr4);
8152 vmx->host_state.vmcs_host_cr4 = cr4;
8155 /* When single-stepping over STI and MOV SS, we must clear the
8156 * corresponding interruptibility bits in the guest state. Otherwise
8157 * vmentry fails as it then expects bit 14 (BS) in pending debug
8158 * exceptions being set, but that's not correct for the guest debugging
8160 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8161 vmx_set_interrupt_shadow(vcpu, 0);
8163 atomic_switch_perf_msrs(vmx);
8164 debugctlmsr = get_debugctlmsr();
8166 vmx->__launched = vmx->loaded_vmcs->launched;
8168 /* Store host registers */
8169 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8170 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8171 "push %%" _ASM_CX " \n\t"
8172 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8174 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8175 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8177 /* Reload cr2 if changed */
8178 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8179 "mov %%cr2, %%" _ASM_DX " \n\t"
8180 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8182 "mov %%" _ASM_AX", %%cr2 \n\t"
8184 /* Check if vmlaunch of vmresume is needed */
8185 "cmpl $0, %c[launched](%0) \n\t"
8186 /* Load guest registers. Don't clobber flags. */
8187 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8188 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8189 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8190 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8191 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8192 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8193 #ifdef CONFIG_X86_64
8194 "mov %c[r8](%0), %%r8 \n\t"
8195 "mov %c[r9](%0), %%r9 \n\t"
8196 "mov %c[r10](%0), %%r10 \n\t"
8197 "mov %c[r11](%0), %%r11 \n\t"
8198 "mov %c[r12](%0), %%r12 \n\t"
8199 "mov %c[r13](%0), %%r13 \n\t"
8200 "mov %c[r14](%0), %%r14 \n\t"
8201 "mov %c[r15](%0), %%r15 \n\t"
8203 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8205 /* Enter guest mode */
8207 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8209 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8211 /* Save guest registers, load host registers, keep flags */
8212 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8214 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8215 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8216 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8217 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8218 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8219 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8220 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8221 #ifdef CONFIG_X86_64
8222 "mov %%r8, %c[r8](%0) \n\t"
8223 "mov %%r9, %c[r9](%0) \n\t"
8224 "mov %%r10, %c[r10](%0) \n\t"
8225 "mov %%r11, %c[r11](%0) \n\t"
8226 "mov %%r12, %c[r12](%0) \n\t"
8227 "mov %%r13, %c[r13](%0) \n\t"
8228 "mov %%r14, %c[r14](%0) \n\t"
8229 "mov %%r15, %c[r15](%0) \n\t"
8231 "mov %%cr2, %%" _ASM_AX " \n\t"
8232 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8234 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8235 "setbe %c[fail](%0) \n\t"
8236 ".pushsection .rodata \n\t"
8237 ".global vmx_return \n\t"
8238 "vmx_return: " _ASM_PTR " 2b \n\t"
8240 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8241 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8242 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8243 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8244 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8245 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8246 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8247 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8248 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8249 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8250 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8251 #ifdef CONFIG_X86_64
8252 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8253 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8254 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8255 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8256 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8257 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8258 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8259 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8261 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8262 [wordsize]"i"(sizeof(ulong))
8264 #ifdef CONFIG_X86_64
8265 , "rax", "rbx", "rdi", "rsi"
8266 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8268 , "eax", "ebx", "edi", "esi"
8272 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8274 update_debugctlmsr(debugctlmsr);
8276 #ifndef CONFIG_X86_64
8278 * The sysexit path does not restore ds/es, so we must set them to
8279 * a reasonable value ourselves.
8281 * We can't defer this to vmx_load_host_state() since that function
8282 * may be executed in interrupt context, which saves and restore segments
8283 * around it, nullifying its effect.
8285 loadsegment(ds, __USER_DS);
8286 loadsegment(es, __USER_DS);
8289 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8290 | (1 << VCPU_EXREG_RFLAGS)
8291 | (1 << VCPU_EXREG_PDPTR)
8292 | (1 << VCPU_EXREG_SEGMENTS)
8293 | (1 << VCPU_EXREG_CR3));
8294 vcpu->arch.regs_dirty = 0;
8296 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8298 vmx->loaded_vmcs->launched = 1;
8300 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8301 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8304 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8305 * we did not inject a still-pending event to L1 now because of
8306 * nested_run_pending, we need to re-enable this bit.
8308 if (vmx->nested.nested_run_pending)
8309 kvm_make_request(KVM_REQ_EVENT, vcpu);
8311 vmx->nested.nested_run_pending = 0;
8313 vmx_complete_atomic_exit(vmx);
8314 vmx_recover_nmi_blocking(vmx);
8315 vmx_complete_interrupts(vmx);
8318 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8320 struct vcpu_vmx *vmx = to_vmx(vcpu);
8323 if (vmx->loaded_vmcs == &vmx->vmcs01)
8327 vmx->loaded_vmcs = &vmx->vmcs01;
8329 vmx_vcpu_load(vcpu, cpu);
8334 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8336 struct vcpu_vmx *vmx = to_vmx(vcpu);
8339 vmx_disable_pml(vmx);
8341 leave_guest_mode(vcpu);
8342 vmx_load_vmcs01(vcpu);
8344 free_loaded_vmcs(vmx->loaded_vmcs);
8345 kfree(vmx->guest_msrs);
8346 kvm_vcpu_uninit(vcpu);
8347 kmem_cache_free(kvm_vcpu_cache, vmx);
8350 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8353 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8357 return ERR_PTR(-ENOMEM);
8361 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8365 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8366 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8370 if (!vmx->guest_msrs) {
8374 vmx->loaded_vmcs = &vmx->vmcs01;
8375 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8376 if (!vmx->loaded_vmcs->vmcs)
8379 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8380 loaded_vmcs_init(vmx->loaded_vmcs);
8385 vmx_vcpu_load(&vmx->vcpu, cpu);
8386 vmx->vcpu.cpu = cpu;
8387 err = vmx_vcpu_setup(vmx);
8388 vmx_vcpu_put(&vmx->vcpu);
8392 if (vm_need_virtualize_apic_accesses(kvm)) {
8393 err = alloc_apic_access_page(kvm);
8399 if (!kvm->arch.ept_identity_map_addr)
8400 kvm->arch.ept_identity_map_addr =
8401 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8402 err = init_rmode_identity_map(kvm);
8408 nested_vmx_setup_ctls_msrs(vmx);
8410 vmx->nested.posted_intr_nv = -1;
8411 vmx->nested.current_vmptr = -1ull;
8412 vmx->nested.current_vmcs12 = NULL;
8415 * If PML is turned on, failure on enabling PML just results in failure
8416 * of creating the vcpu, therefore we can simplify PML logic (by
8417 * avoiding dealing with cases, such as enabling PML partially on vcpus
8418 * for the guest, etc.
8421 err = vmx_enable_pml(vmx);
8429 free_loaded_vmcs(vmx->loaded_vmcs);
8431 kfree(vmx->guest_msrs);
8433 kvm_vcpu_uninit(&vmx->vcpu);
8436 kmem_cache_free(kvm_vcpu_cache, vmx);
8437 return ERR_PTR(err);
8440 static void __init vmx_check_processor_compat(void *rtn)
8442 struct vmcs_config vmcs_conf;
8445 if (setup_vmcs_config(&vmcs_conf) < 0)
8447 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8448 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8449 smp_processor_id());
8454 static int get_ept_level(void)
8456 return VMX_EPT_DEFAULT_GAW + 1;
8459 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8463 /* For VT-d and EPT combination
8464 * 1. MMIO: always map as UC
8466 * a. VT-d without snooping control feature: can't guarantee the
8467 * result, try to trust guest.
8468 * b. VT-d with snooping control feature: snooping control feature of
8469 * VT-d engine can guarantee the cache correctness. Just set it
8470 * to WB to keep consistent with host. So the same as item 3.
8471 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8472 * consistent with host MTRR
8475 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8476 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8477 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8478 VMX_EPT_MT_EPTE_SHIFT;
8480 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8486 static int vmx_get_lpage_level(void)
8488 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8489 return PT_DIRECTORY_LEVEL;
8491 /* For shadow and EPT supported 1GB page */
8492 return PT_PDPE_LEVEL;
8495 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8497 struct kvm_cpuid_entry2 *best;
8498 struct vcpu_vmx *vmx = to_vmx(vcpu);
8501 vmx->rdtscp_enabled = false;
8502 if (vmx_rdtscp_supported()) {
8503 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8504 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8505 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8506 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8507 vmx->rdtscp_enabled = true;
8509 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8510 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8516 /* Exposing INVPCID only when PCID is exposed */
8517 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8518 if (vmx_invpcid_supported() &&
8519 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8520 guest_cpuid_has_pcid(vcpu)) {
8521 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8522 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8523 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8526 if (cpu_has_secondary_exec_ctrls()) {
8527 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8528 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8529 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8533 best->ebx &= ~bit(X86_FEATURE_INVPCID);
8537 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8539 if (func == 1 && nested)
8540 entry->ecx |= bit(X86_FEATURE_VMX);
8543 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8544 struct x86_exception *fault)
8546 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8549 if (fault->error_code & PFERR_RSVD_MASK)
8550 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8552 exit_reason = EXIT_REASON_EPT_VIOLATION;
8553 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8554 vmcs12->guest_physical_address = fault->address;
8557 /* Callbacks for nested_ept_init_mmu_context: */
8559 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8561 /* return the page table to be shadowed - in our case, EPT12 */
8562 return get_vmcs12(vcpu)->ept_pointer;
8565 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8567 WARN_ON(mmu_is_nested(vcpu));
8568 kvm_init_shadow_ept_mmu(vcpu,
8569 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8570 VMX_EPT_EXECUTE_ONLY_BIT);
8571 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8572 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8573 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8575 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
8578 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8580 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8583 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8586 bool inequality, bit;
8588 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8590 (error_code & vmcs12->page_fault_error_code_mask) !=
8591 vmcs12->page_fault_error_code_match;
8592 return inequality ^ bit;
8595 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8596 struct x86_exception *fault)
8598 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8600 WARN_ON(!is_guest_mode(vcpu));
8602 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
8603 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8604 vmcs_read32(VM_EXIT_INTR_INFO),
8605 vmcs_readl(EXIT_QUALIFICATION));
8607 kvm_inject_page_fault(vcpu, fault);
8610 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8611 struct vmcs12 *vmcs12)
8613 struct vcpu_vmx *vmx = to_vmx(vcpu);
8615 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8616 /* TODO: Also verify bits beyond physical address width are 0 */
8617 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
8621 * Translate L1 physical address to host physical
8622 * address for vmcs02. Keep the page pinned, so this
8623 * physical address remains valid. We keep a reference
8624 * to it so we can release it later.
8626 if (vmx->nested.apic_access_page) /* shouldn't happen */
8627 nested_release_page(vmx->nested.apic_access_page);
8628 vmx->nested.apic_access_page =
8629 nested_get_page(vcpu, vmcs12->apic_access_addr);
8632 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8633 /* TODO: Also verify bits beyond physical address width are 0 */
8634 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8637 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8638 nested_release_page(vmx->nested.virtual_apic_page);
8639 vmx->nested.virtual_apic_page =
8640 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8643 * Failing the vm entry is _not_ what the processor does
8644 * but it's basically the only possibility we have.
8645 * We could still enter the guest if CR8 load exits are
8646 * enabled, CR8 store exits are enabled, and virtualize APIC
8647 * access is disabled; in this case the processor would never
8648 * use the TPR shadow and we could simply clear the bit from
8649 * the execution control. But such a configuration is useless,
8650 * so let's keep the code simple.
8652 if (!vmx->nested.virtual_apic_page)
8656 if (nested_cpu_has_posted_intr(vmcs12)) {
8657 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64))
8660 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8661 kunmap(vmx->nested.pi_desc_page);
8662 nested_release_page(vmx->nested.pi_desc_page);
8664 vmx->nested.pi_desc_page =
8665 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8666 if (!vmx->nested.pi_desc_page)
8669 vmx->nested.pi_desc =
8670 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8671 if (!vmx->nested.pi_desc) {
8672 nested_release_page_clean(vmx->nested.pi_desc_page);
8675 vmx->nested.pi_desc =
8676 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8677 (unsigned long)(vmcs12->posted_intr_desc_addr &
8684 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8686 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8687 struct vcpu_vmx *vmx = to_vmx(vcpu);
8689 if (vcpu->arch.virtual_tsc_khz == 0)
8692 /* Make sure short timeouts reliably trigger an immediate vmexit.
8693 * hrtimer_start does not guarantee this. */
8694 if (preemption_timeout <= 1) {
8695 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8699 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8700 preemption_timeout *= 1000000;
8701 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8702 hrtimer_start(&vmx->nested.preemption_timer,
8703 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8706 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8707 struct vmcs12 *vmcs12)
8712 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8715 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8719 maxphyaddr = cpuid_maxphyaddr(vcpu);
8721 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8722 ((addr + PAGE_SIZE) >> maxphyaddr))
8729 * Merge L0's and L1's MSR bitmap, return false to indicate that
8730 * we do not use the hardware.
8732 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8733 struct vmcs12 *vmcs12)
8737 unsigned long *msr_bitmap;
8739 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8742 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8747 msr_bitmap = (unsigned long *)kmap(page);
8749 nested_release_page_clean(page);
8754 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8755 if (nested_cpu_has_apic_reg_virt(vmcs12))
8756 for (msr = 0x800; msr <= 0x8ff; msr++)
8757 nested_vmx_disable_intercept_for_msr(
8759 vmx_msr_bitmap_nested,
8761 /* TPR is allowed */
8762 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8763 vmx_msr_bitmap_nested,
8764 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8765 MSR_TYPE_R | MSR_TYPE_W);
8766 if (nested_cpu_has_vid(vmcs12)) {
8767 /* EOI and self-IPI are allowed */
8768 nested_vmx_disable_intercept_for_msr(
8770 vmx_msr_bitmap_nested,
8771 APIC_BASE_MSR + (APIC_EOI >> 4),
8773 nested_vmx_disable_intercept_for_msr(
8775 vmx_msr_bitmap_nested,
8776 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8781 * Enable reading intercept of all the x2apic
8782 * MSRs. We should not rely on vmcs12 to do any
8783 * optimizations here, it may have been modified
8786 for (msr = 0x800; msr <= 0x8ff; msr++)
8787 __vmx_enable_intercept_for_msr(
8788 vmx_msr_bitmap_nested,
8792 __vmx_enable_intercept_for_msr(
8793 vmx_msr_bitmap_nested,
8794 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8796 __vmx_enable_intercept_for_msr(
8797 vmx_msr_bitmap_nested,
8798 APIC_BASE_MSR + (APIC_EOI >> 4),
8800 __vmx_enable_intercept_for_msr(
8801 vmx_msr_bitmap_nested,
8802 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8806 nested_release_page_clean(page);
8811 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8812 struct vmcs12 *vmcs12)
8814 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8815 !nested_cpu_has_apic_reg_virt(vmcs12) &&
8816 !nested_cpu_has_vid(vmcs12) &&
8817 !nested_cpu_has_posted_intr(vmcs12))
8821 * If virtualize x2apic mode is enabled,
8822 * virtualize apic access must be disabled.
8824 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8825 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8829 * If virtual interrupt delivery is enabled,
8830 * we must exit on external interrupts.
8832 if (nested_cpu_has_vid(vmcs12) &&
8833 !nested_exit_on_intr(vcpu))
8837 * bits 15:8 should be zero in posted_intr_nv,
8838 * the descriptor address has been already checked
8839 * in nested_get_vmcs12_pages.
8841 if (nested_cpu_has_posted_intr(vmcs12) &&
8842 (!nested_cpu_has_vid(vmcs12) ||
8843 !nested_exit_intr_ack_set(vcpu) ||
8844 vmcs12->posted_intr_nv & 0xff00))
8847 /* tpr shadow is needed by all apicv features. */
8848 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8854 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8855 unsigned long count_field,
8856 unsigned long addr_field,
8861 if (vmcs12_read_any(vcpu, count_field, &count) ||
8862 vmcs12_read_any(vcpu, addr_field, &addr)) {
8868 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8869 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8870 pr_warn_ratelimited(
8871 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8872 addr_field, maxphyaddr, count, addr);
8878 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8879 struct vmcs12 *vmcs12)
8883 if (vmcs12->vm_exit_msr_load_count == 0 &&
8884 vmcs12->vm_exit_msr_store_count == 0 &&
8885 vmcs12->vm_entry_msr_load_count == 0)
8886 return 0; /* Fast path */
8887 maxphyaddr = cpuid_maxphyaddr(vcpu);
8888 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8889 VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
8890 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8891 VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
8892 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8893 VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
8898 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8899 struct vmx_msr_entry *e)
8901 /* x2APIC MSR accesses are not allowed */
8902 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8904 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8905 e->index == MSR_IA32_UCODE_REV)
8907 if (e->reserved != 0)
8912 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8913 struct vmx_msr_entry *e)
8915 if (e->index == MSR_FS_BASE ||
8916 e->index == MSR_GS_BASE ||
8917 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8918 nested_vmx_msr_check_common(vcpu, e))
8923 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8924 struct vmx_msr_entry *e)
8926 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8927 nested_vmx_msr_check_common(vcpu, e))
8933 * Load guest's/host's msr at nested entry/exit.
8934 * return 0 for success, entry index for failure.
8936 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8939 struct vmx_msr_entry e;
8940 struct msr_data msr;
8942 msr.host_initiated = false;
8943 for (i = 0; i < count; i++) {
8944 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8946 pr_warn_ratelimited(
8947 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8948 __func__, i, gpa + i * sizeof(e));
8951 if (nested_vmx_load_msr_check(vcpu, &e)) {
8952 pr_warn_ratelimited(
8953 "%s check failed (%u, 0x%x, 0x%x)\n",
8954 __func__, i, e.index, e.reserved);
8957 msr.index = e.index;
8959 if (kvm_set_msr(vcpu, &msr)) {
8960 pr_warn_ratelimited(
8961 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8962 __func__, i, e.index, e.value);
8971 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8974 struct vmx_msr_entry e;
8976 for (i = 0; i < count; i++) {
8977 if (kvm_read_guest(vcpu->kvm,
8978 gpa + i * sizeof(e),
8979 &e, 2 * sizeof(u32))) {
8980 pr_warn_ratelimited(
8981 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8982 __func__, i, gpa + i * sizeof(e));
8985 if (nested_vmx_store_msr_check(vcpu, &e)) {
8986 pr_warn_ratelimited(
8987 "%s check failed (%u, 0x%x, 0x%x)\n",
8988 __func__, i, e.index, e.reserved);
8991 if (kvm_get_msr(vcpu, e.index, &e.value)) {
8992 pr_warn_ratelimited(
8993 "%s cannot read MSR (%u, 0x%x)\n",
8994 __func__, i, e.index);
8997 if (kvm_write_guest(vcpu->kvm,
8998 gpa + i * sizeof(e) +
8999 offsetof(struct vmx_msr_entry, value),
9000 &e.value, sizeof(e.value))) {
9001 pr_warn_ratelimited(
9002 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9003 __func__, i, e.index, e.value);
9011 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9012 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9013 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9014 * guest in a way that will both be appropriate to L1's requests, and our
9015 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9016 * function also has additional necessary side-effects, like setting various
9017 * vcpu->arch fields.
9019 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9021 struct vcpu_vmx *vmx = to_vmx(vcpu);
9024 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9025 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9026 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9027 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9028 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9029 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9030 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9031 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9032 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9033 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9034 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9035 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9036 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9037 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9038 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9039 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9040 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9041 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9042 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9043 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9044 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9045 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9046 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9047 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9048 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9049 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9050 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9051 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9052 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9053 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9054 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9055 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9056 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9057 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9058 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9059 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9061 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9062 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9063 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9065 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9066 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9068 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9069 vmcs12->vm_entry_intr_info_field);
9070 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9071 vmcs12->vm_entry_exception_error_code);
9072 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9073 vmcs12->vm_entry_instruction_len);
9074 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9075 vmcs12->guest_interruptibility_info);
9076 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9077 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9078 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9079 vmcs12->guest_pending_dbg_exceptions);
9080 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9081 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9083 if (nested_cpu_has_xsaves(vmcs12))
9084 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9085 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9087 exec_control = vmcs12->pin_based_vm_exec_control;
9088 exec_control |= vmcs_config.pin_based_exec_ctrl;
9089 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9091 if (nested_cpu_has_posted_intr(vmcs12)) {
9093 * Note that we use L0's vector here and in
9094 * vmx_deliver_nested_posted_interrupt.
9096 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9097 vmx->nested.pi_pending = false;
9098 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9099 vmcs_write64(POSTED_INTR_DESC_ADDR,
9100 page_to_phys(vmx->nested.pi_desc_page) +
9101 (unsigned long)(vmcs12->posted_intr_desc_addr &
9104 exec_control &= ~PIN_BASED_POSTED_INTR;
9106 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9108 vmx->nested.preemption_timer_expired = false;
9109 if (nested_cpu_has_preemption_timer(vmcs12))
9110 vmx_start_preemption_timer(vcpu);
9113 * Whether page-faults are trapped is determined by a combination of
9114 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9115 * If enable_ept, L0 doesn't care about page faults and we should
9116 * set all of these to L1's desires. However, if !enable_ept, L0 does
9117 * care about (at least some) page faults, and because it is not easy
9118 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9119 * to exit on each and every L2 page fault. This is done by setting
9120 * MASK=MATCH=0 and (see below) EB.PF=1.
9121 * Note that below we don't need special code to set EB.PF beyond the
9122 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9123 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9124 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9126 * A problem with this approach (when !enable_ept) is that L1 may be
9127 * injected with more page faults than it asked for. This could have
9128 * caused problems, but in practice existing hypervisors don't care.
9129 * To fix this, we will need to emulate the PFEC checking (on the L1
9130 * page tables), using walk_addr(), when injecting PFs to L1.
9132 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9133 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9134 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9135 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9137 if (cpu_has_secondary_exec_ctrls()) {
9138 exec_control = vmx_secondary_exec_control(vmx);
9139 if (!vmx->rdtscp_enabled)
9140 exec_control &= ~SECONDARY_EXEC_RDTSCP;
9141 /* Take the following fields only from vmcs12 */
9142 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9143 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9144 SECONDARY_EXEC_APIC_REGISTER_VIRT);
9145 if (nested_cpu_has(vmcs12,
9146 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9147 exec_control |= vmcs12->secondary_vm_exec_control;
9149 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9151 * If translation failed, no matter: This feature asks
9152 * to exit when accessing the given address, and if it
9153 * can never be accessed, this feature won't do
9156 if (!vmx->nested.apic_access_page)
9158 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9160 vmcs_write64(APIC_ACCESS_ADDR,
9161 page_to_phys(vmx->nested.apic_access_page));
9162 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9163 (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
9165 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9166 kvm_vcpu_reload_apic_access_page(vcpu);
9169 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9170 vmcs_write64(EOI_EXIT_BITMAP0,
9171 vmcs12->eoi_exit_bitmap0);
9172 vmcs_write64(EOI_EXIT_BITMAP1,
9173 vmcs12->eoi_exit_bitmap1);
9174 vmcs_write64(EOI_EXIT_BITMAP2,
9175 vmcs12->eoi_exit_bitmap2);
9176 vmcs_write64(EOI_EXIT_BITMAP3,
9177 vmcs12->eoi_exit_bitmap3);
9178 vmcs_write16(GUEST_INTR_STATUS,
9179 vmcs12->guest_intr_status);
9182 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9187 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9188 * Some constant fields are set here by vmx_set_constant_host_state().
9189 * Other fields are different per CPU, and will be set later when
9190 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9192 vmx_set_constant_host_state(vmx);
9195 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9196 * entry, but only if the current (host) sp changed from the value
9197 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9198 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9199 * here we just force the write to happen on entry.
9203 exec_control = vmx_exec_control(vmx); /* L0's desires */
9204 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9205 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9206 exec_control &= ~CPU_BASED_TPR_SHADOW;
9207 exec_control |= vmcs12->cpu_based_vm_exec_control;
9209 if (exec_control & CPU_BASED_TPR_SHADOW) {
9210 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9211 page_to_phys(vmx->nested.virtual_apic_page));
9212 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9215 if (cpu_has_vmx_msr_bitmap() &&
9216 exec_control & CPU_BASED_USE_MSR_BITMAPS &&
9217 nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) {
9218 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_nested));
9220 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9223 * Merging of IO bitmap not currently supported.
9224 * Rather, exit every time.
9226 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9227 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9229 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9231 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9232 * bitwise-or of what L1 wants to trap for L2, and what we want to
9233 * trap. Note that CR0.TS also needs updating - we do this later.
9235 update_exception_bitmap(vcpu);
9236 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9237 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9239 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9240 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9241 * bits are further modified by vmx_set_efer() below.
9243 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9245 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9246 * emulated by vmx_set_efer(), below.
9248 vm_entry_controls_init(vmx,
9249 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9250 ~VM_ENTRY_IA32E_MODE) |
9251 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9253 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9254 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9255 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9256 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9257 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9260 set_cr4_guest_host_mask(vmx);
9262 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9263 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9265 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9266 vmcs_write64(TSC_OFFSET,
9267 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9269 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9273 * Trivially support vpid by letting L2s share their parent
9274 * L1's vpid. TODO: move to a more elaborate solution, giving
9275 * each L2 its own vpid and exposing the vpid feature to L1.
9277 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9278 vmx_flush_tlb(vcpu);
9281 if (nested_cpu_has_ept(vmcs12)) {
9282 kvm_mmu_unload(vcpu);
9283 nested_ept_init_mmu_context(vcpu);
9286 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9287 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9288 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9289 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9291 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9292 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9293 vmx_set_efer(vcpu, vcpu->arch.efer);
9296 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9297 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9298 * The CR0_READ_SHADOW is what L2 should have expected to read given
9299 * the specifications by L1; It's not enough to take
9300 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9301 * have more bits than L1 expected.
9303 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9304 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9306 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9307 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9309 /* shadow page tables on either EPT or shadow page tables */
9310 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9311 kvm_mmu_reset_context(vcpu);
9314 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9317 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9320 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9321 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9322 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9323 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9326 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9327 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9331 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9332 * for running an L2 nested guest.
9334 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9336 struct vmcs12 *vmcs12;
9337 struct vcpu_vmx *vmx = to_vmx(vcpu);
9339 struct loaded_vmcs *vmcs02;
9343 if (!nested_vmx_check_permission(vcpu) ||
9344 !nested_vmx_check_vmcs12(vcpu))
9347 skip_emulated_instruction(vcpu);
9348 vmcs12 = get_vmcs12(vcpu);
9350 if (enable_shadow_vmcs)
9351 copy_shadow_to_vmcs12(vmx);
9354 * The nested entry process starts with enforcing various prerequisites
9355 * on vmcs12 as required by the Intel SDM, and act appropriately when
9356 * they fail: As the SDM explains, some conditions should cause the
9357 * instruction to fail, while others will cause the instruction to seem
9358 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9359 * To speed up the normal (success) code path, we should avoid checking
9360 * for misconfigurations which will anyway be caught by the processor
9361 * when using the merged vmcs02.
9363 if (vmcs12->launch_state == launch) {
9364 nested_vmx_failValid(vcpu,
9365 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9366 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9370 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9371 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9372 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9376 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9377 /*TODO: Also verify bits beyond physical address width are 0*/
9378 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9382 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9383 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9387 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9388 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9392 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9393 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9397 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9398 vmx->nested.nested_vmx_true_procbased_ctls_low,
9399 vmx->nested.nested_vmx_procbased_ctls_high) ||
9400 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9401 vmx->nested.nested_vmx_secondary_ctls_low,
9402 vmx->nested.nested_vmx_secondary_ctls_high) ||
9403 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9404 vmx->nested.nested_vmx_pinbased_ctls_low,
9405 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9406 !vmx_control_verify(vmcs12->vm_exit_controls,
9407 vmx->nested.nested_vmx_true_exit_ctls_low,
9408 vmx->nested.nested_vmx_exit_ctls_high) ||
9409 !vmx_control_verify(vmcs12->vm_entry_controls,
9410 vmx->nested.nested_vmx_true_entry_ctls_low,
9411 vmx->nested.nested_vmx_entry_ctls_high))
9413 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9417 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9418 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9419 nested_vmx_failValid(vcpu,
9420 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9424 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9425 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9426 nested_vmx_entry_failure(vcpu, vmcs12,
9427 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9430 if (vmcs12->vmcs_link_pointer != -1ull) {
9431 nested_vmx_entry_failure(vcpu, vmcs12,
9432 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9437 * If the load IA32_EFER VM-entry control is 1, the following checks
9438 * are performed on the field for the IA32_EFER MSR:
9439 * - Bits reserved in the IA32_EFER MSR must be 0.
9440 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9441 * the IA-32e mode guest VM-exit control. It must also be identical
9442 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9445 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9446 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9447 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9448 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9449 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9450 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9451 nested_vmx_entry_failure(vcpu, vmcs12,
9452 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9458 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9459 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9460 * the values of the LMA and LME bits in the field must each be that of
9461 * the host address-space size VM-exit control.
9463 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9464 ia32e = (vmcs12->vm_exit_controls &
9465 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9466 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9467 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9468 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9469 nested_vmx_entry_failure(vcpu, vmcs12,
9470 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9476 * We're finally done with prerequisite checking, and can start with
9480 vmcs02 = nested_get_current_vmcs02(vmx);
9484 enter_guest_mode(vcpu);
9486 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9488 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9489 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9492 vmx->loaded_vmcs = vmcs02;
9494 vmx_vcpu_load(vcpu, cpu);
9498 vmx_segment_cache_clear(vmx);
9500 prepare_vmcs02(vcpu, vmcs12);
9502 msr_entry_idx = nested_vmx_load_msr(vcpu,
9503 vmcs12->vm_entry_msr_load_addr,
9504 vmcs12->vm_entry_msr_load_count);
9505 if (msr_entry_idx) {
9506 leave_guest_mode(vcpu);
9507 vmx_load_vmcs01(vcpu);
9508 nested_vmx_entry_failure(vcpu, vmcs12,
9509 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9513 vmcs12->launch_state = 1;
9515 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9516 return kvm_emulate_halt(vcpu);
9518 vmx->nested.nested_run_pending = 1;
9521 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9522 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9523 * returned as far as L1 is concerned. It will only return (and set
9524 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9530 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9531 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9532 * This function returns the new value we should put in vmcs12.guest_cr0.
9533 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9534 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9535 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9536 * didn't trap the bit, because if L1 did, so would L0).
9537 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9538 * been modified by L2, and L1 knows it. So just leave the old value of
9539 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9540 * isn't relevant, because if L0 traps this bit it can set it to anything.
9541 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9542 * changed these bits, and therefore they need to be updated, but L0
9543 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9544 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9546 static inline unsigned long
9547 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9550 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9551 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9552 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9553 vcpu->arch.cr0_guest_owned_bits));
9556 static inline unsigned long
9557 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9560 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9561 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9562 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9563 vcpu->arch.cr4_guest_owned_bits));
9566 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9567 struct vmcs12 *vmcs12)
9572 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9573 nr = vcpu->arch.exception.nr;
9574 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9576 if (kvm_exception_is_soft(nr)) {
9577 vmcs12->vm_exit_instruction_len =
9578 vcpu->arch.event_exit_inst_len;
9579 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9581 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9583 if (vcpu->arch.exception.has_error_code) {
9584 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9585 vmcs12->idt_vectoring_error_code =
9586 vcpu->arch.exception.error_code;
9589 vmcs12->idt_vectoring_info_field = idt_vectoring;
9590 } else if (vcpu->arch.nmi_injected) {
9591 vmcs12->idt_vectoring_info_field =
9592 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9593 } else if (vcpu->arch.interrupt.pending) {
9594 nr = vcpu->arch.interrupt.nr;
9595 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9597 if (vcpu->arch.interrupt.soft) {
9598 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9599 vmcs12->vm_entry_instruction_len =
9600 vcpu->arch.event_exit_inst_len;
9602 idt_vectoring |= INTR_TYPE_EXT_INTR;
9604 vmcs12->idt_vectoring_info_field = idt_vectoring;
9608 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9610 struct vcpu_vmx *vmx = to_vmx(vcpu);
9612 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9613 vmx->nested.preemption_timer_expired) {
9614 if (vmx->nested.nested_run_pending)
9616 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9620 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
9621 if (vmx->nested.nested_run_pending ||
9622 vcpu->arch.interrupt.pending)
9624 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9625 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9626 INTR_INFO_VALID_MASK, 0);
9628 * The NMI-triggered VM exit counts as injection:
9629 * clear this one and block further NMIs.
9631 vcpu->arch.nmi_pending = 0;
9632 vmx_set_nmi_mask(vcpu, true);
9636 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9637 nested_exit_on_intr(vcpu)) {
9638 if (vmx->nested.nested_run_pending)
9640 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9644 return vmx_complete_nested_posted_interrupt(vcpu);
9647 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9650 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9653 if (ktime_to_ns(remaining) <= 0)
9656 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9657 do_div(value, 1000000);
9658 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9662 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9663 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9664 * and this function updates it to reflect the changes to the guest state while
9665 * L2 was running (and perhaps made some exits which were handled directly by L0
9666 * without going back to L1), and to reflect the exit reason.
9667 * Note that we do not have to copy here all VMCS fields, just those that
9668 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9669 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9670 * which already writes to vmcs12 directly.
9672 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9673 u32 exit_reason, u32 exit_intr_info,
9674 unsigned long exit_qualification)
9676 /* update guest state fields: */
9677 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9678 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9680 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9681 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9682 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9684 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9685 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9686 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9687 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9688 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9689 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9690 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9691 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9692 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9693 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9694 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9695 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9696 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9697 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9698 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9699 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9700 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9701 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9702 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9703 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9704 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9705 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9706 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9707 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9708 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9709 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9710 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9711 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9712 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9713 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9714 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9715 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9716 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9717 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9718 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9719 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9721 vmcs12->guest_interruptibility_info =
9722 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9723 vmcs12->guest_pending_dbg_exceptions =
9724 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
9725 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9726 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9728 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
9730 if (nested_cpu_has_preemption_timer(vmcs12)) {
9731 if (vmcs12->vm_exit_controls &
9732 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9733 vmcs12->vmx_preemption_timer_value =
9734 vmx_get_preemption_timer_value(vcpu);
9735 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9739 * In some cases (usually, nested EPT), L2 is allowed to change its
9740 * own CR3 without exiting. If it has changed it, we must keep it.
9741 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9742 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9744 * Additionally, restore L2's PDPTR to vmcs12.
9747 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9748 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9749 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9750 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9751 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9754 if (nested_cpu_has_vid(vmcs12))
9755 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9757 vmcs12->vm_entry_controls =
9758 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
9759 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
9761 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9762 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9763 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9766 /* TODO: These cannot have changed unless we have MSR bitmaps and
9767 * the relevant bit asks not to trap the change */
9768 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
9769 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
9770 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9771 vmcs12->guest_ia32_efer = vcpu->arch.efer;
9772 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9773 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9774 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
9775 if (vmx_mpx_supported())
9776 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
9777 if (nested_cpu_has_xsaves(vmcs12))
9778 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
9780 /* update exit information fields: */
9782 vmcs12->vm_exit_reason = exit_reason;
9783 vmcs12->exit_qualification = exit_qualification;
9785 vmcs12->vm_exit_intr_info = exit_intr_info;
9786 if ((vmcs12->vm_exit_intr_info &
9787 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9788 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9789 vmcs12->vm_exit_intr_error_code =
9790 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
9791 vmcs12->idt_vectoring_info_field = 0;
9792 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9793 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9795 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9796 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9797 * instead of reading the real value. */
9798 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
9801 * Transfer the event that L0 or L1 may wanted to inject into
9802 * L2 to IDT_VECTORING_INFO_FIELD.
9804 vmcs12_save_pending_event(vcpu, vmcs12);
9808 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9809 * preserved above and would only end up incorrectly in L1.
9811 vcpu->arch.nmi_injected = false;
9812 kvm_clear_exception_queue(vcpu);
9813 kvm_clear_interrupt_queue(vcpu);
9817 * A part of what we need to when the nested L2 guest exits and we want to
9818 * run its L1 parent, is to reset L1's guest state to the host state specified
9820 * This function is to be called not only on normal nested exit, but also on
9821 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9822 * Failures During or After Loading Guest State").
9823 * This function should be called when the active VMCS is L1's (vmcs01).
9825 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9826 struct vmcs12 *vmcs12)
9828 struct kvm_segment seg;
9830 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9831 vcpu->arch.efer = vmcs12->host_ia32_efer;
9832 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9833 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9835 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9836 vmx_set_efer(vcpu, vcpu->arch.efer);
9838 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9839 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
9840 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
9842 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9843 * actually changed, because it depends on the current state of
9844 * fpu_active (which may have changed).
9845 * Note that vmx_set_cr0 refers to efer set above.
9847 vmx_set_cr0(vcpu, vmcs12->host_cr0);
9849 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9850 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9851 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9853 update_exception_bitmap(vcpu);
9854 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9855 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9858 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9859 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9861 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9862 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9864 nested_ept_uninit_mmu_context(vcpu);
9866 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9867 kvm_mmu_reset_context(vcpu);
9870 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9874 * Trivially support vpid by letting L2s share their parent
9875 * L1's vpid. TODO: move to a more elaborate solution, giving
9876 * each L2 its own vpid and exposing the vpid feature to L1.
9878 vmx_flush_tlb(vcpu);
9882 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9883 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9884 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9885 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9886 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9888 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9889 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9890 vmcs_write64(GUEST_BNDCFGS, 0);
9892 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9893 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9894 vcpu->arch.pat = vmcs12->host_ia32_pat;
9896 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9897 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9898 vmcs12->host_ia32_perf_global_ctrl);
9900 /* Set L1 segment info according to Intel SDM
9901 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9902 seg = (struct kvm_segment) {
9904 .limit = 0xFFFFFFFF,
9905 .selector = vmcs12->host_cs_selector,
9911 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9915 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9916 seg = (struct kvm_segment) {
9918 .limit = 0xFFFFFFFF,
9925 seg.selector = vmcs12->host_ds_selector;
9926 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9927 seg.selector = vmcs12->host_es_selector;
9928 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9929 seg.selector = vmcs12->host_ss_selector;
9930 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9931 seg.selector = vmcs12->host_fs_selector;
9932 seg.base = vmcs12->host_fs_base;
9933 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9934 seg.selector = vmcs12->host_gs_selector;
9935 seg.base = vmcs12->host_gs_base;
9936 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9937 seg = (struct kvm_segment) {
9938 .base = vmcs12->host_tr_base,
9940 .selector = vmcs12->host_tr_selector,
9944 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9946 kvm_set_dr(vcpu, 7, 0x400);
9947 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9949 if (cpu_has_vmx_msr_bitmap())
9950 vmx_set_msr_bitmap(vcpu);
9952 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9953 vmcs12->vm_exit_msr_load_count))
9954 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
9958 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9959 * and modify vmcs12 to make it see what it would expect to see there if
9960 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9962 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9964 unsigned long exit_qualification)
9966 struct vcpu_vmx *vmx = to_vmx(vcpu);
9967 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9969 /* trying to cancel vmlaunch/vmresume is a bug */
9970 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9972 leave_guest_mode(vcpu);
9973 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9974 exit_qualification);
9976 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9977 vmcs12->vm_exit_msr_store_count))
9978 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9980 vmx_load_vmcs01(vcpu);
9982 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9983 && nested_exit_intr_ack_set(vcpu)) {
9984 int irq = kvm_cpu_get_interrupt(vcpu);
9986 vmcs12->vm_exit_intr_info = irq |
9987 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9990 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9991 vmcs12->exit_qualification,
9992 vmcs12->idt_vectoring_info_field,
9993 vmcs12->vm_exit_intr_info,
9994 vmcs12->vm_exit_intr_error_code,
9997 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9998 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
9999 vmx_segment_cache_clear(vmx);
10001 /* if no vmcs02 cache requested, remove the one we used */
10002 if (VMCS02_POOL_SIZE == 0)
10003 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10005 load_vmcs12_host_state(vcpu, vmcs12);
10007 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10008 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10010 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10013 /* Unpin physical memory we referred to in vmcs02 */
10014 if (vmx->nested.apic_access_page) {
10015 nested_release_page(vmx->nested.apic_access_page);
10016 vmx->nested.apic_access_page = NULL;
10018 if (vmx->nested.virtual_apic_page) {
10019 nested_release_page(vmx->nested.virtual_apic_page);
10020 vmx->nested.virtual_apic_page = NULL;
10022 if (vmx->nested.pi_desc_page) {
10023 kunmap(vmx->nested.pi_desc_page);
10024 nested_release_page(vmx->nested.pi_desc_page);
10025 vmx->nested.pi_desc_page = NULL;
10026 vmx->nested.pi_desc = NULL;
10030 * We are now running in L2, mmu_notifier will force to reload the
10031 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10033 kvm_vcpu_reload_apic_access_page(vcpu);
10036 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10037 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10038 * success or failure flag accordingly.
10040 if (unlikely(vmx->fail)) {
10042 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10044 nested_vmx_succeed(vcpu);
10045 if (enable_shadow_vmcs)
10046 vmx->nested.sync_shadow_vmcs = true;
10048 /* in case we halted in L2 */
10049 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10053 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10055 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10057 if (is_guest_mode(vcpu))
10058 nested_vmx_vmexit(vcpu, -1, 0, 0);
10059 free_nested(to_vmx(vcpu));
10063 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10064 * 23.7 "VM-entry failures during or after loading guest state" (this also
10065 * lists the acceptable exit-reason and exit-qualification parameters).
10066 * It should only be called before L2 actually succeeded to run, and when
10067 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10069 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10070 struct vmcs12 *vmcs12,
10071 u32 reason, unsigned long qualification)
10073 load_vmcs12_host_state(vcpu, vmcs12);
10074 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10075 vmcs12->exit_qualification = qualification;
10076 nested_vmx_succeed(vcpu);
10077 if (enable_shadow_vmcs)
10078 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10081 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10082 struct x86_instruction_info *info,
10083 enum x86_intercept_stage stage)
10085 return X86EMUL_CONTINUE;
10088 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10091 shrink_ple_window(vcpu);
10094 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10095 struct kvm_memory_slot *slot)
10097 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10098 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10101 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10102 struct kvm_memory_slot *slot)
10104 kvm_mmu_slot_set_dirty(kvm, slot);
10107 static void vmx_flush_log_dirty(struct kvm *kvm)
10109 kvm_flush_pml_buffers(kvm);
10112 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10113 struct kvm_memory_slot *memslot,
10114 gfn_t offset, unsigned long mask)
10116 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10119 static struct kvm_x86_ops vmx_x86_ops = {
10120 .cpu_has_kvm_support = cpu_has_kvm_support,
10121 .disabled_by_bios = vmx_disabled_by_bios,
10122 .hardware_setup = hardware_setup,
10123 .hardware_unsetup = hardware_unsetup,
10124 .check_processor_compatibility = vmx_check_processor_compat,
10125 .hardware_enable = hardware_enable,
10126 .hardware_disable = hardware_disable,
10127 .cpu_has_accelerated_tpr = report_flexpriority,
10129 .vcpu_create = vmx_create_vcpu,
10130 .vcpu_free = vmx_free_vcpu,
10131 .vcpu_reset = vmx_vcpu_reset,
10133 .prepare_guest_switch = vmx_save_host_state,
10134 .vcpu_load = vmx_vcpu_load,
10135 .vcpu_put = vmx_vcpu_put,
10137 .update_db_bp_intercept = update_exception_bitmap,
10138 .get_msr = vmx_get_msr,
10139 .set_msr = vmx_set_msr,
10140 .get_segment_base = vmx_get_segment_base,
10141 .get_segment = vmx_get_segment,
10142 .set_segment = vmx_set_segment,
10143 .get_cpl = vmx_get_cpl,
10144 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10145 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10146 .decache_cr3 = vmx_decache_cr3,
10147 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10148 .set_cr0 = vmx_set_cr0,
10149 .set_cr3 = vmx_set_cr3,
10150 .set_cr4 = vmx_set_cr4,
10151 .set_efer = vmx_set_efer,
10152 .get_idt = vmx_get_idt,
10153 .set_idt = vmx_set_idt,
10154 .get_gdt = vmx_get_gdt,
10155 .set_gdt = vmx_set_gdt,
10156 .get_dr6 = vmx_get_dr6,
10157 .set_dr6 = vmx_set_dr6,
10158 .set_dr7 = vmx_set_dr7,
10159 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10160 .cache_reg = vmx_cache_reg,
10161 .get_rflags = vmx_get_rflags,
10162 .set_rflags = vmx_set_rflags,
10163 .fpu_deactivate = vmx_fpu_deactivate,
10165 .tlb_flush = vmx_flush_tlb,
10167 .run = vmx_vcpu_run,
10168 .handle_exit = vmx_handle_exit,
10169 .skip_emulated_instruction = skip_emulated_instruction,
10170 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10171 .get_interrupt_shadow = vmx_get_interrupt_shadow,
10172 .patch_hypercall = vmx_patch_hypercall,
10173 .set_irq = vmx_inject_irq,
10174 .set_nmi = vmx_inject_nmi,
10175 .queue_exception = vmx_queue_exception,
10176 .cancel_injection = vmx_cancel_injection,
10177 .interrupt_allowed = vmx_interrupt_allowed,
10178 .nmi_allowed = vmx_nmi_allowed,
10179 .get_nmi_mask = vmx_get_nmi_mask,
10180 .set_nmi_mask = vmx_set_nmi_mask,
10181 .enable_nmi_window = enable_nmi_window,
10182 .enable_irq_window = enable_irq_window,
10183 .update_cr8_intercept = update_cr8_intercept,
10184 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10185 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10186 .vm_has_apicv = vmx_vm_has_apicv,
10187 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10188 .hwapic_irr_update = vmx_hwapic_irr_update,
10189 .hwapic_isr_update = vmx_hwapic_isr_update,
10190 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10191 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10193 .set_tss_addr = vmx_set_tss_addr,
10194 .get_tdp_level = get_ept_level,
10195 .get_mt_mask = vmx_get_mt_mask,
10197 .get_exit_info = vmx_get_exit_info,
10199 .get_lpage_level = vmx_get_lpage_level,
10201 .cpuid_update = vmx_cpuid_update,
10203 .rdtscp_supported = vmx_rdtscp_supported,
10204 .invpcid_supported = vmx_invpcid_supported,
10206 .set_supported_cpuid = vmx_set_supported_cpuid,
10208 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10210 .set_tsc_khz = vmx_set_tsc_khz,
10211 .read_tsc_offset = vmx_read_tsc_offset,
10212 .write_tsc_offset = vmx_write_tsc_offset,
10213 .adjust_tsc_offset = vmx_adjust_tsc_offset,
10214 .compute_tsc_offset = vmx_compute_tsc_offset,
10215 .read_l1_tsc = vmx_read_l1_tsc,
10217 .set_tdp_cr3 = vmx_set_cr3,
10219 .check_intercept = vmx_check_intercept,
10220 .handle_external_intr = vmx_handle_external_intr,
10221 .mpx_supported = vmx_mpx_supported,
10222 .xsaves_supported = vmx_xsaves_supported,
10224 .check_nested_events = vmx_check_nested_events,
10226 .sched_in = vmx_sched_in,
10228 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10229 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10230 .flush_log_dirty = vmx_flush_log_dirty,
10231 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10234 static int __init vmx_init(void)
10236 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10237 __alignof__(struct vcpu_vmx), THIS_MODULE);
10241 #ifdef CONFIG_KEXEC
10242 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10243 crash_vmclear_local_loaded_vmcss);
10249 static void __exit vmx_exit(void)
10251 #ifdef CONFIG_KEXEC
10252 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10259 module_init(vmx_init)
10260 module_exit(vmx_exit)