arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * ple_gap:    upper bound on the amount of time between two successive
 120  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 121  *             According to test, this time is usually smaller than 128 cycles.
 122  * ple_window: upper bound on the amount of time a guest is allowed to execute
 123  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 124  *             less than 2^12 cycles
 125  * Time is measured based on a counter that runs at the same rate as the TSC,
 126  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 127  */
 128 #define KVM_VMX_DEFAULT_PLE_GAP    128
 129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 130 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 131 module_param(ple_gap, int, S_IRUGO);
 132
 133 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 134 module_param(ple_window, int, S_IRUGO);
 135
 136 extern const ulong vmx_return;
 137
 138 #define NR_AUTOLOAD_MSRS 8
 139 #define VMCS02_POOL_SIZE 1
 140
 141 struct vmcs {
 142         u32 revision_id;
 143         u32 abort;
 144         char data[0];
 145 };
 146
 147 /*
 148  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 149  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 150  * loaded on this CPU (so we can clear them if the CPU goes down).
 151  */
 152 struct loaded_vmcs {
 153         struct vmcs *vmcs;
 154         int cpu;
 155         int launched;
 156         struct list_head loaded_vmcss_on_cpu_link;
 157 };
 158
 159 struct shared_msr_entry {
 160         unsigned index;
 161         u64 data;
 162         u64 mask;
 163 };
 164
 165 /*
 166  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 167  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 168  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 169  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 170  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 171  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 172  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 173  * underlying hardware which will be used to run L2.
 174  * This structure is packed to ensure that its layout is identical across
 175  * machines (necessary for live migration).
 176  * If there are changes in this struct, VMCS12_REVISION must be changed.
 177  */
 178 typedef u64 natural_width;
 179 struct __packed vmcs12 {
 180         /* According to the Intel spec, a VMCS region must start with the
 181          * following two fields. Then follow implementation-specific data.
 182          */
 183         u32 revision_id;
 184         u32 abort;
 185
 186         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 187         u32 padding[7]; /* room for future expansion */
 188
 189         u64 io_bitmap_a;
 190         u64 io_bitmap_b;
 191         u64 msr_bitmap;
 192         u64 vm_exit_msr_store_addr;
 193         u64 vm_exit_msr_load_addr;
 194         u64 vm_entry_msr_load_addr;
 195         u64 tsc_offset;
 196         u64 virtual_apic_page_addr;
 197         u64 apic_access_addr;
 198         u64 ept_pointer;
 199         u64 guest_physical_address;
 200         u64 vmcs_link_pointer;
 201         u64 guest_ia32_debugctl;
 202         u64 guest_ia32_pat;
 203         u64 guest_ia32_efer;
 204         u64 guest_ia32_perf_global_ctrl;
 205         u64 guest_pdptr0;
 206         u64 guest_pdptr1;
 207         u64 guest_pdptr2;
 208         u64 guest_pdptr3;
 209         u64 guest_bndcfgs;
 210         u64 host_ia32_pat;
 211         u64 host_ia32_efer;
 212         u64 host_ia32_perf_global_ctrl;
 213         u64 padding64[8]; /* room for future expansion */
 214         /*
 215          * To allow migration of L1 (complete with its L2 guests) between
 216          * machines of different natural widths (32 or 64 bit), we cannot have
 217          * unsigned long fields with no explict size. We use u64 (aliased
 218          * natural_width) instead. Luckily, x86 is little-endian.
 219          */
 220         natural_width cr0_guest_host_mask;
 221         natural_width cr4_guest_host_mask;
 222         natural_width cr0_read_shadow;
 223         natural_width cr4_read_shadow;
 224         natural_width cr3_target_value0;
 225         natural_width cr3_target_value1;
 226         natural_width cr3_target_value2;
 227         natural_width cr3_target_value3;
 228         natural_width exit_qualification;
 229         natural_width guest_linear_address;
 230         natural_width guest_cr0;
 231         natural_width guest_cr3;
 232         natural_width guest_cr4;
 233         natural_width guest_es_base;
 234         natural_width guest_cs_base;
 235         natural_width guest_ss_base;
 236         natural_width guest_ds_base;
 237         natural_width guest_fs_base;
 238         natural_width guest_gs_base;
 239         natural_width guest_ldtr_base;
 240         natural_width guest_tr_base;
 241         natural_width guest_gdtr_base;
 242         natural_width guest_idtr_base;
 243         natural_width guest_dr7;
 244         natural_width guest_rsp;
 245         natural_width guest_rip;
 246         natural_width guest_rflags;
 247         natural_width guest_pending_dbg_exceptions;
 248         natural_width guest_sysenter_esp;
 249         natural_width guest_sysenter_eip;
 250         natural_width host_cr0;
 251         natural_width host_cr3;
 252         natural_width host_cr4;
 253         natural_width host_fs_base;
 254         natural_width host_gs_base;
 255         natural_width host_tr_base;
 256         natural_width host_gdtr_base;
 257         natural_width host_idtr_base;
 258         natural_width host_ia32_sysenter_esp;
 259         natural_width host_ia32_sysenter_eip;
 260         natural_width host_rsp;
 261         natural_width host_rip;
 262         natural_width paddingl[8]; /* room for future expansion */
 263         u32 pin_based_vm_exec_control;
 264         u32 cpu_based_vm_exec_control;
 265         u32 exception_bitmap;
 266         u32 page_fault_error_code_mask;
 267         u32 page_fault_error_code_match;
 268         u32 cr3_target_count;
 269         u32 vm_exit_controls;
 270         u32 vm_exit_msr_store_count;
 271         u32 vm_exit_msr_load_count;
 272         u32 vm_entry_controls;
 273         u32 vm_entry_msr_load_count;
 274         u32 vm_entry_intr_info_field;
 275         u32 vm_entry_exception_error_code;
 276         u32 vm_entry_instruction_len;
 277         u32 tpr_threshold;
 278         u32 secondary_vm_exec_control;
 279         u32 vm_instruction_error;
 280         u32 vm_exit_reason;
 281         u32 vm_exit_intr_info;
 282         u32 vm_exit_intr_error_code;
 283         u32 idt_vectoring_info_field;
 284         u32 idt_vectoring_error_code;
 285         u32 vm_exit_instruction_len;
 286         u32 vmx_instruction_info;
 287         u32 guest_es_limit;
 288         u32 guest_cs_limit;
 289         u32 guest_ss_limit;
 290         u32 guest_ds_limit;
 291         u32 guest_fs_limit;
 292         u32 guest_gs_limit;
 293         u32 guest_ldtr_limit;
 294         u32 guest_tr_limit;
 295         u32 guest_gdtr_limit;
 296         u32 guest_idtr_limit;
 297         u32 guest_es_ar_bytes;
 298         u32 guest_cs_ar_bytes;
 299         u32 guest_ss_ar_bytes;
 300         u32 guest_ds_ar_bytes;
 301         u32 guest_fs_ar_bytes;
 302         u32 guest_gs_ar_bytes;
 303         u32 guest_ldtr_ar_bytes;
 304         u32 guest_tr_ar_bytes;
 305         u32 guest_interruptibility_info;
 306         u32 guest_activity_state;
 307         u32 guest_sysenter_cs;
 308         u32 host_ia32_sysenter_cs;
 309         u32 vmx_preemption_timer_value;
 310         u32 padding32[7]; /* room for future expansion */
 311         u16 virtual_processor_id;
 312         u16 guest_es_selector;
 313         u16 guest_cs_selector;
 314         u16 guest_ss_selector;
 315         u16 guest_ds_selector;
 316         u16 guest_fs_selector;
 317         u16 guest_gs_selector;
 318         u16 guest_ldtr_selector;
 319         u16 guest_tr_selector;
 320         u16 host_es_selector;
 321         u16 host_cs_selector;
 322         u16 host_ss_selector;
 323         u16 host_ds_selector;
 324         u16 host_fs_selector;
 325         u16 host_gs_selector;
 326         u16 host_tr_selector;
 327 };
 328
 329 /*
 330  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 331  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 332  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 333  */
 334 #define VMCS12_REVISION 0x11e57ed0
 335
 336 /*
 337  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 338  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 339  * current implementation, 4K are reserved to avoid future complications.
 340  */
 341 #define VMCS12_SIZE 0x1000
 342
 343 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 344 struct vmcs02_list {
 345         struct list_head list;
 346         gpa_t vmptr;
 347         struct loaded_vmcs vmcs02;
 348 };
 349
 350 /*
 351  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 352  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 353  */
 354 struct nested_vmx {
 355         /* Has the level1 guest done vmxon? */
 356         bool vmxon;
 357
 358         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 359         gpa_t current_vmptr;
 360         /* The host-usable pointer to the above */
 361         struct page *current_vmcs12_page;
 362         struct vmcs12 *current_vmcs12;
 363         struct vmcs *current_shadow_vmcs;
 364         /*
 365          * Indicates if the shadow vmcs must be updated with the
 366          * data hold by vmcs12
 367          */
 368         bool sync_shadow_vmcs;
 369
 370         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 371         struct list_head vmcs02_pool;
 372         int vmcs02_num;
 373         u64 vmcs01_tsc_offset;
 374         /* L2 must run next, and mustn't decide to exit to L1. */
 375         bool nested_run_pending;
 376         /*
 377          * Guest pages referred to in vmcs02 with host-physical pointers, so
 378          * we must keep them pinned while L2 runs.
 379          */
 380         struct page *apic_access_page;
 381         u64 msr_ia32_feature_control;
 382
 383         struct hrtimer preemption_timer;
 384         bool preemption_timer_expired;
 385 };
 386
 387 #define POSTED_INTR_ON  0
 388 /* Posted-Interrupt Descriptor */
 389 struct pi_desc {
 390         u32 pir[8];     /* Posted interrupt requested */
 391         u32 control;    /* bit 0 of control is outstanding notification bit */
 392         u32 rsvd[7];
 393 } __aligned(64);
 394
 395 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 396 {
 397         return test_and_set_bit(POSTED_INTR_ON,
 398                         (unsigned long *)&pi_desc->control);
 399 }
 400
 401 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 402 {
 403         return test_and_clear_bit(POSTED_INTR_ON,
 404                         (unsigned long *)&pi_desc->control);
 405 }
 406
 407 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 408 {
 409         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 410 }
 411
 412 struct vcpu_vmx {
 413         struct kvm_vcpu       vcpu;
 414         unsigned long         host_rsp;
 415         u8                    fail;
 416         u8                    cpl;
 417         bool                  nmi_known_unmasked;
 418         u32                   exit_intr_info;
 419         u32                   idt_vectoring_info;
 420         ulong                 rflags;
 421         struct shared_msr_entry *guest_msrs;
 422         int                   nmsrs;
 423         int                   save_nmsrs;
 424         unsigned long         host_idt_base;
 425 #ifdef CONFIG_X86_64
 426         u64                   msr_host_kernel_gs_base;
 427         u64                   msr_guest_kernel_gs_base;
 428 #endif
 429         u32 vm_entry_controls_shadow;
 430         u32 vm_exit_controls_shadow;
 431         /*
 432          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 433          * non-nested (L1) guest, it always points to vmcs01. For a nested
 434          * guest (L2), it points to a different VMCS.
 435          */
 436         struct loaded_vmcs    vmcs01;
 437         struct loaded_vmcs   *loaded_vmcs;
 438         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 439         struct msr_autoload {
 440                 unsigned nr;
 441                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 442                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 443         } msr_autoload;
 444         struct {
 445                 int           loaded;
 446                 u16           fs_sel, gs_sel, ldt_sel;
 447 #ifdef CONFIG_X86_64
 448                 u16           ds_sel, es_sel;
 449 #endif
 450                 int           gs_ldt_reload_needed;
 451                 int           fs_reload_needed;
 452                 u64           msr_host_bndcfgs;
 453         } host_state;
 454         struct {
 455                 int vm86_active;
 456                 ulong save_rflags;
 457                 struct kvm_segment segs[8];
 458         } rmode;
 459         struct {
 460                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 461                 struct kvm_save_segment {
 462                         u16 selector;
 463                         unsigned long base;
 464                         u32 limit;
 465                         u32 ar;
 466                 } seg[8];
 467         } segment_cache;
 468         int vpid;
 469         bool emulation_required;
 470
 471         /* Support for vnmi-less CPUs */
 472         int soft_vnmi_blocked;
 473         ktime_t entry_time;
 474         s64 vnmi_blocked_time;
 475         u32 exit_reason;
 476
 477         bool rdtscp_enabled;
 478
 479         /* Posted interrupt descriptor */
 480         struct pi_desc pi_desc;
 481
 482         /* Support for a guest hypervisor (nested VMX) */
 483         struct nested_vmx nested;
 484 };
 485
 486 enum segment_cache_field {
 487         SEG_FIELD_SEL = 0,
 488         SEG_FIELD_BASE = 1,
 489         SEG_FIELD_LIMIT = 2,
 490         SEG_FIELD_AR = 3,
 491
 492         SEG_FIELD_NR = 4
 493 };
 494
 495 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 496 {
 497         return container_of(vcpu, struct vcpu_vmx, vcpu);
 498 }
 499
 500 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 501 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 502 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 503                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 504
 505
 506 static const unsigned long shadow_read_only_fields[] = {
 507         /*
 508          * We do NOT shadow fields that are modified when L0
 509          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 510          * VMXON...) executed by L1.
 511          * For example, VM_INSTRUCTION_ERROR is read
 512          * by L1 if a vmx instruction fails (part of the error path).
 513          * Note the code assumes this logic. If for some reason
 514          * we start shadowing these fields then we need to
 515          * force a shadow sync when L0 emulates vmx instructions
 516          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 517          * by nested_vmx_failValid)
 518          */
 519         VM_EXIT_REASON,
 520         VM_EXIT_INTR_INFO,
 521         VM_EXIT_INSTRUCTION_LEN,
 522         IDT_VECTORING_INFO_FIELD,
 523         IDT_VECTORING_ERROR_CODE,
 524         VM_EXIT_INTR_ERROR_CODE,
 525         EXIT_QUALIFICATION,
 526         GUEST_LINEAR_ADDRESS,
 527         GUEST_PHYSICAL_ADDRESS
 528 };
 529 static const int max_shadow_read_only_fields =
 530         ARRAY_SIZE(shadow_read_only_fields);
 531
 532 static const unsigned long shadow_read_write_fields[] = {
 533         GUEST_RIP,
 534         GUEST_RSP,
 535         GUEST_CR0,
 536         GUEST_CR3,
 537         GUEST_CR4,
 538         GUEST_INTERRUPTIBILITY_INFO,
 539         GUEST_RFLAGS,
 540         GUEST_CS_SELECTOR,
 541         GUEST_CS_AR_BYTES,
 542         GUEST_CS_LIMIT,
 543         GUEST_CS_BASE,
 544         GUEST_ES_BASE,
 545         GUEST_BNDCFGS,
 546         CR0_GUEST_HOST_MASK,
 547         CR0_READ_SHADOW,
 548         CR4_READ_SHADOW,
 549         TSC_OFFSET,
 550         EXCEPTION_BITMAP,
 551         CPU_BASED_VM_EXEC_CONTROL,
 552         VM_ENTRY_EXCEPTION_ERROR_CODE,
 553         VM_ENTRY_INTR_INFO_FIELD,
 554         VM_ENTRY_INSTRUCTION_LEN,
 555         VM_ENTRY_EXCEPTION_ERROR_CODE,
 556         HOST_FS_BASE,
 557         HOST_GS_BASE,
 558         HOST_FS_SELECTOR,
 559         HOST_GS_SELECTOR
 560 };
 561 static const int max_shadow_read_write_fields =
 562         ARRAY_SIZE(shadow_read_write_fields);
 563
 564 static const unsigned short vmcs_field_to_offset_table[] = {
 565         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 566         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 567         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 568         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 569         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 570         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 571         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 572         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 573         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 574         FIELD(HOST_ES_SELECTOR, host_es_selector),
 575         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 576         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 577         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 578         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 579         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 580         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 581         FIELD64(IO_BITMAP_A, io_bitmap_a),
 582         FIELD64(IO_BITMAP_B, io_bitmap_b),
 583         FIELD64(MSR_BITMAP, msr_bitmap),
 584         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 585         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 586         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 587         FIELD64(TSC_OFFSET, tsc_offset),
 588         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 589         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 590         FIELD64(EPT_POINTER, ept_pointer),
 591         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 592         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 593         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 594         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 595         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 596         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 597         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 598         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 599         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 600         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 601         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 602         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 603         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 604         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 605         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 606         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 607         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 608         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 609         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 610         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 611         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 612         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 613         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 614         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 615         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 616         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 617         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 618         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 619         FIELD(TPR_THRESHOLD, tpr_threshold),
 620         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 621         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 622         FIELD(VM_EXIT_REASON, vm_exit_reason),
 623         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 624         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 625         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 626         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 627         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 628         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 629         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 630         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 631         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 632         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 633         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 634         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 635         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 636         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 637         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 638         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 639         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 640         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 641         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 642         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 643         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 644         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 645         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 646         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 647         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 648         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 649         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 650         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 651         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 652         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 653         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 654         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 655         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 656         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 657         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 658         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 659         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 660         FIELD(EXIT_QUALIFICATION, exit_qualification),
 661         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 662         FIELD(GUEST_CR0, guest_cr0),
 663         FIELD(GUEST_CR3, guest_cr3),
 664         FIELD(GUEST_CR4, guest_cr4),
 665         FIELD(GUEST_ES_BASE, guest_es_base),
 666         FIELD(GUEST_CS_BASE, guest_cs_base),
 667         FIELD(GUEST_SS_BASE, guest_ss_base),
 668         FIELD(GUEST_DS_BASE, guest_ds_base),
 669         FIELD(GUEST_FS_BASE, guest_fs_base),
 670         FIELD(GUEST_GS_BASE, guest_gs_base),
 671         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 672         FIELD(GUEST_TR_BASE, guest_tr_base),
 673         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 674         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 675         FIELD(GUEST_DR7, guest_dr7),
 676         FIELD(GUEST_RSP, guest_rsp),
 677         FIELD(GUEST_RIP, guest_rip),
 678         FIELD(GUEST_RFLAGS, guest_rflags),
 679         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 680         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 681         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 682         FIELD(HOST_CR0, host_cr0),
 683         FIELD(HOST_CR3, host_cr3),
 684         FIELD(HOST_CR4, host_cr4),
 685         FIELD(HOST_FS_BASE, host_fs_base),
 686         FIELD(HOST_GS_BASE, host_gs_base),
 687         FIELD(HOST_TR_BASE, host_tr_base),
 688         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 689         FIELD(HOST_IDTR_BASE, host_idtr_base),
 690         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 691         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 692         FIELD(HOST_RSP, host_rsp),
 693         FIELD(HOST_RIP, host_rip),
 694 };
 695 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 696
 697 static inline short vmcs_field_to_offset(unsigned long field)
 698 {
 699         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 700                 return -1;
 701         return vmcs_field_to_offset_table[field];
 702 }
 703
 704 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 705 {
 706         return to_vmx(vcpu)->nested.current_vmcs12;
 707 }
 708
 709 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 710 {
 711         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 712         if (is_error_page(page))
 713                 return NULL;
 714
 715         return page;
 716 }
 717
 718 static void nested_release_page(struct page *page)
 719 {
 720         kvm_release_page_dirty(page);
 721 }
 722
 723 static void nested_release_page_clean(struct page *page)
 724 {
 725         kvm_release_page_clean(page);
 726 }
 727
 728 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 729 static u64 construct_eptp(unsigned long root_hpa);
 730 static void kvm_cpu_vmxon(u64 addr);
 731 static void kvm_cpu_vmxoff(void);
 732 static bool vmx_mpx_supported(void);
 733 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 734 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 735                             struct kvm_segment *var, int seg);
 736 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 737                             struct kvm_segment *var, int seg);
 738 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 739 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 740 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 741 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 742 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 743 static bool vmx_mpx_supported(void);
 744
 745 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 746 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 747 /*
 748  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 749  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 750  */
 751 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 752 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 753
 754 static unsigned long *vmx_io_bitmap_a;
 755 static unsigned long *vmx_io_bitmap_b;
 756 static unsigned long *vmx_msr_bitmap_legacy;
 757 static unsigned long *vmx_msr_bitmap_longmode;
 758 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 759 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 760 static unsigned long *vmx_vmread_bitmap;
 761 static unsigned long *vmx_vmwrite_bitmap;
 762
 763 static bool cpu_has_load_ia32_efer;
 764 static bool cpu_has_load_perf_global_ctrl;
 765
 766 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 767 static DEFINE_SPINLOCK(vmx_vpid_lock);
 768
 769 static struct vmcs_config {
 770         int size;
 771         int order;
 772         u32 revision_id;
 773         u32 pin_based_exec_ctrl;
 774         u32 cpu_based_exec_ctrl;
 775         u32 cpu_based_2nd_exec_ctrl;
 776         u32 vmexit_ctrl;
 777         u32 vmentry_ctrl;
 778 } vmcs_config;
 779
 780 static struct vmx_capability {
 781         u32 ept;
 782         u32 vpid;
 783 } vmx_capability;
 784
 785 #define VMX_SEGMENT_FIELD(seg)                                  \
 786         [VCPU_SREG_##seg] = {                                   \
 787                 .selector = GUEST_##seg##_SELECTOR,             \
 788                 .base = GUEST_##seg##_BASE,                     \
 789                 .limit = GUEST_##seg##_LIMIT,                   \
 790                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 791         }
 792
 793 static const struct kvm_vmx_segment_field {
 794         unsigned selector;
 795         unsigned base;
 796         unsigned limit;
 797         unsigned ar_bytes;
 798 } kvm_vmx_segment_fields[] = {
 799         VMX_SEGMENT_FIELD(CS),
 800         VMX_SEGMENT_FIELD(DS),
 801         VMX_SEGMENT_FIELD(ES),
 802         VMX_SEGMENT_FIELD(FS),
 803         VMX_SEGMENT_FIELD(GS),
 804         VMX_SEGMENT_FIELD(SS),
 805         VMX_SEGMENT_FIELD(TR),
 806         VMX_SEGMENT_FIELD(LDTR),
 807 };
 808
 809 static u64 host_efer;
 810
 811 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 812
 813 /*
 814  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 815  * away by decrementing the array size.
 816  */
 817 static const u32 vmx_msr_index[] = {
 818 #ifdef CONFIG_X86_64
 819         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 820 #endif
 821         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 822 };
 823 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 824
 825 static inline bool is_page_fault(u32 intr_info)
 826 {
 827         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 828                              INTR_INFO_VALID_MASK)) ==
 829                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 830 }
 831
 832 static inline bool is_no_device(u32 intr_info)
 833 {
 834         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 835                              INTR_INFO_VALID_MASK)) ==
 836                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 837 }
 838
 839 static inline bool is_invalid_opcode(u32 intr_info)
 840 {
 841         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 842                              INTR_INFO_VALID_MASK)) ==
 843                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 844 }
 845
 846 static inline bool is_external_interrupt(u32 intr_info)
 847 {
 848         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 849                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 850 }
 851
 852 static inline bool is_machine_check(u32 intr_info)
 853 {
 854         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 855                              INTR_INFO_VALID_MASK)) ==
 856                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 857 }
 858
 859 static inline bool cpu_has_vmx_msr_bitmap(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 862 }
 863
 864 static inline bool cpu_has_vmx_tpr_shadow(void)
 865 {
 866         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 867 }
 868
 869 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 870 {
 871         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 872 }
 873
 874 static inline bool cpu_has_secondary_exec_ctrls(void)
 875 {
 876         return vmcs_config.cpu_based_exec_ctrl &
 877                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 878 }
 879
 880 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 881 {
 882         return vmcs_config.cpu_based_2nd_exec_ctrl &
 883                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 884 }
 885
 886 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 887 {
 888         return vmcs_config.cpu_based_2nd_exec_ctrl &
 889                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 890 }
 891
 892 static inline bool cpu_has_vmx_apic_register_virt(void)
 893 {
 894         return vmcs_config.cpu_based_2nd_exec_ctrl &
 895                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 896 }
 897
 898 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 899 {
 900         return vmcs_config.cpu_based_2nd_exec_ctrl &
 901                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 902 }
 903
 904 static inline bool cpu_has_vmx_posted_intr(void)
 905 {
 906         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 907 }
 908
 909 static inline bool cpu_has_vmx_apicv(void)
 910 {
 911         return cpu_has_vmx_apic_register_virt() &&
 912                 cpu_has_vmx_virtual_intr_delivery() &&
 913                 cpu_has_vmx_posted_intr();
 914 }
 915
 916 static inline bool cpu_has_vmx_flexpriority(void)
 917 {
 918         return cpu_has_vmx_tpr_shadow() &&
 919                 cpu_has_vmx_virtualize_apic_accesses();
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_execute_only(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 928 {
 929         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_eptp_writeback(void)
 933 {
 934         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_2m_page(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_ept_1g_page(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_ept_4levels(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_ept_ad_bits(void)
 953 {
 954         return vmx_capability.ept & VMX_EPT_AD_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invept_context(void)
 958 {
 959         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_invept_global(void)
 963 {
 964         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 965 }
 966
 967 static inline bool cpu_has_vmx_invvpid_single(void)
 968 {
 969         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 970 }
 971
 972 static inline bool cpu_has_vmx_invvpid_global(void)
 973 {
 974         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 975 }
 976
 977 static inline bool cpu_has_vmx_ept(void)
 978 {
 979         return vmcs_config.cpu_based_2nd_exec_ctrl &
 980                 SECONDARY_EXEC_ENABLE_EPT;
 981 }
 982
 983 static inline bool cpu_has_vmx_unrestricted_guest(void)
 984 {
 985         return vmcs_config.cpu_based_2nd_exec_ctrl &
 986                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 987 }
 988
 989 static inline bool cpu_has_vmx_ple(void)
 990 {
 991         return vmcs_config.cpu_based_2nd_exec_ctrl &
 992                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 993 }
 994
 995 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 996 {
 997         return flexpriority_enabled && irqchip_in_kernel(kvm);
 998 }
 999
1000 static inline bool cpu_has_vmx_vpid(void)
1001 {
1002         return vmcs_config.cpu_based_2nd_exec_ctrl &
1003                 SECONDARY_EXEC_ENABLE_VPID;
1004 }
1005
1006 static inline bool cpu_has_vmx_rdtscp(void)
1007 {
1008         return vmcs_config.cpu_based_2nd_exec_ctrl &
1009                 SECONDARY_EXEC_RDTSCP;
1010 }
1011
1012 static inline bool cpu_has_vmx_invpcid(void)
1013 {
1014         return vmcs_config.cpu_based_2nd_exec_ctrl &
1015                 SECONDARY_EXEC_ENABLE_INVPCID;
1016 }
1017
1018 static inline bool cpu_has_virtual_nmis(void)
1019 {
1020         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1021 }
1022
1023 static inline bool cpu_has_vmx_wbinvd_exit(void)
1024 {
1025         return vmcs_config.cpu_based_2nd_exec_ctrl &
1026                 SECONDARY_EXEC_WBINVD_EXITING;
1027 }
1028
1029 static inline bool cpu_has_vmx_shadow_vmcs(void)
1030 {
1031         u64 vmx_msr;
1032         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033         /* check if the cpu supports writing r/o exit information fields */
1034         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1035                 return false;
1036
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_SHADOW_VMCS;
1039 }
1040
1041 static inline bool report_flexpriority(void)
1042 {
1043         return flexpriority_enabled;
1044 }
1045
1046 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1047 {
1048         return vmcs12->cpu_based_vm_exec_control & bit;
1049 }
1050
1051 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1052 {
1053         return (vmcs12->cpu_based_vm_exec_control &
1054                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055                 (vmcs12->secondary_vm_exec_control & bit);
1056 }
1057
1058 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1059 {
1060         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1061 }
1062
1063 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1064 {
1065         return vmcs12->pin_based_vm_exec_control &
1066                 PIN_BASED_VMX_PREEMPTION_TIMER;
1067 }
1068
1069 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1070 {
1071         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1072 }
1073
1074 static inline bool is_exception(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1081                               u32 exit_intr_info,
1082                               unsigned long exit_qualification);
1083 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084                         struct vmcs12 *vmcs12,
1085                         u32 reason, unsigned long qualification);
1086
1087 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1088 {
1089         int i;
1090
1091         for (i = 0; i < vmx->nmsrs; ++i)
1092                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1093                         return i;
1094         return -1;
1095 }
1096
1097 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1098 {
1099     struct {
1100         u64 vpid : 16;
1101         u64 rsvd : 48;
1102         u64 gva;
1103     } operand = { vpid, 0, gva };
1104
1105     asm volatile (__ex(ASM_VMX_INVVPID)
1106                   /* CF==1 or ZF==1 --> rc = -1 */
1107                   "; ja 1f ; ud2 ; 1:"
1108                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1109 }
1110
1111 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1112 {
1113         struct {
1114                 u64 eptp, gpa;
1115         } operand = {eptp, gpa};
1116
1117         asm volatile (__ex(ASM_VMX_INVEPT)
1118                         /* CF==1 or ZF==1 --> rc = -1 */
1119                         "; ja 1f ; ud2 ; 1:\n"
1120                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1121 }
1122
1123 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1124 {
1125         int i;
1126
1127         i = __find_msr_index(vmx, msr);
1128         if (i >= 0)
1129                 return &vmx->guest_msrs[i];
1130         return NULL;
1131 }
1132
1133 static void vmcs_clear(struct vmcs *vmcs)
1134 {
1135         u64 phys_addr = __pa(vmcs);
1136         u8 error;
1137
1138         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1139                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1140                       : "cc", "memory");
1141         if (error)
1142                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1143                        vmcs, phys_addr);
1144 }
1145
1146 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1147 {
1148         vmcs_clear(loaded_vmcs->vmcs);
1149         loaded_vmcs->cpu = -1;
1150         loaded_vmcs->launched = 0;
1151 }
1152
1153 static void vmcs_load(struct vmcs *vmcs)
1154 {
1155         u64 phys_addr = __pa(vmcs);
1156         u8 error;
1157
1158         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1159                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1160                         : "cc", "memory");
1161         if (error)
1162                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1163                        vmcs, phys_addr);
1164 }
1165
1166 #ifdef CONFIG_KEXEC
1167 /*
1168  * This bitmap is used to indicate whether the vmclear
1169  * operation is enabled on all cpus. All disabled by
1170  * default.
1171  */
1172 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1173
1174 static inline void crash_enable_local_vmclear(int cpu)
1175 {
1176         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177 }
1178
1179 static inline void crash_disable_local_vmclear(int cpu)
1180 {
1181         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182 }
1183
1184 static inline int crash_local_vmclear_enabled(int cpu)
1185 {
1186         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187 }
1188
1189 static void crash_vmclear_local_loaded_vmcss(void)
1190 {
1191         int cpu = raw_smp_processor_id();
1192         struct loaded_vmcs *v;
1193
1194         if (!crash_local_vmclear_enabled(cpu))
1195                 return;
1196
1197         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198                             loaded_vmcss_on_cpu_link)
1199                 vmcs_clear(v->vmcs);
1200 }
1201 #else
1202 static inline void crash_enable_local_vmclear(int cpu) { }
1203 static inline void crash_disable_local_vmclear(int cpu) { }
1204 #endif /* CONFIG_KEXEC */
1205
1206 static void __loaded_vmcs_clear(void *arg)
1207 {
1208         struct loaded_vmcs *loaded_vmcs = arg;
1209         int cpu = raw_smp_processor_id();
1210
1211         if (loaded_vmcs->cpu != cpu)
1212                 return; /* vcpu migration can race with cpu offline */
1213         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1214                 per_cpu(current_vmcs, cpu) = NULL;
1215         crash_disable_local_vmclear(cpu);
1216         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1217
1218         /*
1219          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220          * is before setting loaded_vmcs->vcpu to -1 which is done in
1221          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222          * then adds the vmcs into percpu list before it is deleted.
1223          */
1224         smp_wmb();
1225
1226         loaded_vmcs_init(loaded_vmcs);
1227         crash_enable_local_vmclear(cpu);
1228 }
1229
1230 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1231 {
1232         int cpu = loaded_vmcs->cpu;
1233
1234         if (cpu != -1)
1235                 smp_call_function_single(cpu,
1236                          __loaded_vmcs_clear, loaded_vmcs, 1);
1237 }
1238
1239 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1240 {
1241         if (vmx->vpid == 0)
1242                 return;
1243
1244         if (cpu_has_vmx_invvpid_single())
1245                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1246 }
1247
1248 static inline void vpid_sync_vcpu_global(void)
1249 {
1250         if (cpu_has_vmx_invvpid_global())
1251                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1252 }
1253
1254 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1255 {
1256         if (cpu_has_vmx_invvpid_single())
1257                 vpid_sync_vcpu_single(vmx);
1258         else
1259                 vpid_sync_vcpu_global();
1260 }
1261
1262 static inline void ept_sync_global(void)
1263 {
1264         if (cpu_has_vmx_invept_global())
1265                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1266 }
1267
1268 static inline void ept_sync_context(u64 eptp)
1269 {
1270         if (enable_ept) {
1271                 if (cpu_has_vmx_invept_context())
1272                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1273                 else
1274                         ept_sync_global();
1275         }
1276 }
1277
1278 static __always_inline unsigned long vmcs_readl(unsigned long field)
1279 {
1280         unsigned long value;
1281
1282         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283                       : "=a"(value) : "d"(field) : "cc");
1284         return value;
1285 }
1286
1287 static __always_inline u16 vmcs_read16(unsigned long field)
1288 {
1289         return vmcs_readl(field);
1290 }
1291
1292 static __always_inline u32 vmcs_read32(unsigned long field)
1293 {
1294         return vmcs_readl(field);
1295 }
1296
1297 static __always_inline u64 vmcs_read64(unsigned long field)
1298 {
1299 #ifdef CONFIG_X86_64
1300         return vmcs_readl(field);
1301 #else
1302         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1303 #endif
1304 }
1305
1306 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1307 {
1308         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1310         dump_stack();
1311 }
1312
1313 static void vmcs_writel(unsigned long field, unsigned long value)
1314 {
1315         u8 error;
1316
1317         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1318                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1319         if (unlikely(error))
1320                 vmwrite_error(field, value);
1321 }
1322
1323 static void vmcs_write16(unsigned long field, u16 value)
1324 {
1325         vmcs_writel(field, value);
1326 }
1327
1328 static void vmcs_write32(unsigned long field, u32 value)
1329 {
1330         vmcs_writel(field, value);
1331 }
1332
1333 static void vmcs_write64(unsigned long field, u64 value)
1334 {
1335         vmcs_writel(field, value);
1336 #ifndef CONFIG_X86_64
1337         asm volatile ("");
1338         vmcs_writel(field+1, value >> 32);
1339 #endif
1340 }
1341
1342 static void vmcs_clear_bits(unsigned long field, u32 mask)
1343 {
1344         vmcs_writel(field, vmcs_readl(field) & ~mask);
1345 }
1346
1347 static void vmcs_set_bits(unsigned long field, u32 mask)
1348 {
1349         vmcs_writel(field, vmcs_readl(field) | mask);
1350 }
1351
1352 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1353 {
1354         vmcs_write32(VM_ENTRY_CONTROLS, val);
1355         vmx->vm_entry_controls_shadow = val;
1356 }
1357
1358 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1359 {
1360         if (vmx->vm_entry_controls_shadow != val)
1361                 vm_entry_controls_init(vmx, val);
1362 }
1363
1364 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1365 {
1366         return vmx->vm_entry_controls_shadow;
1367 }
1368
1369
1370 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1371 {
1372         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1373 }
1374
1375 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1376 {
1377         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1378 }
1379
1380 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1381 {
1382         vmcs_write32(VM_EXIT_CONTROLS, val);
1383         vmx->vm_exit_controls_shadow = val;
1384 }
1385
1386 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1387 {
1388         if (vmx->vm_exit_controls_shadow != val)
1389                 vm_exit_controls_init(vmx, val);
1390 }
1391
1392 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1393 {
1394         return vmx->vm_exit_controls_shadow;
1395 }
1396
1397
1398 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1399 {
1400         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1401 }
1402
1403 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1404 {
1405         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1406 }
1407
1408 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1409 {
1410         vmx->segment_cache.bitmask = 0;
1411 }
1412
1413 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1414                                        unsigned field)
1415 {
1416         bool ret;
1417         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1418
1419         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421                 vmx->segment_cache.bitmask = 0;
1422         }
1423         ret = vmx->segment_cache.bitmask & mask;
1424         vmx->segment_cache.bitmask |= mask;
1425         return ret;
1426 }
1427
1428 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1429 {
1430         u16 *p = &vmx->segment_cache.seg[seg].selector;
1431
1432         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1434         return *p;
1435 }
1436
1437 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1438 {
1439         ulong *p = &vmx->segment_cache.seg[seg].base;
1440
1441         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1443         return *p;
1444 }
1445
1446 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1447 {
1448         u32 *p = &vmx->segment_cache.seg[seg].limit;
1449
1450         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1452         return *p;
1453 }
1454
1455 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1456 {
1457         u32 *p = &vmx->segment_cache.seg[seg].ar;
1458
1459         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1461         return *p;
1462 }
1463
1464 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1465 {
1466         u32 eb;
1467
1468         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470         if ((vcpu->guest_debug &
1471              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473                 eb |= 1u << BP_VECTOR;
1474         if (to_vmx(vcpu)->rmode.vm86_active)
1475                 eb = ~0;
1476         if (enable_ept)
1477                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1478         if (vcpu->fpu_active)
1479                 eb &= ~(1u << NM_VECTOR);
1480
1481         /* When we are running a nested L2 guest and L1 specified for it a
1482          * certain exception bitmap, we must trap the same exceptions and pass
1483          * them to L1. When running L2, we will only handle the exceptions
1484          * specified above if L1 did not want them.
1485          */
1486         if (is_guest_mode(vcpu))
1487                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1488
1489         vmcs_write32(EXCEPTION_BITMAP, eb);
1490 }
1491
1492 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493                 unsigned long entry, unsigned long exit)
1494 {
1495         vm_entry_controls_clearbit(vmx, entry);
1496         vm_exit_controls_clearbit(vmx, exit);
1497 }
1498
1499 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1500 {
1501         unsigned i;
1502         struct msr_autoload *m = &vmx->msr_autoload;
1503
1504         switch (msr) {
1505         case MSR_EFER:
1506                 if (cpu_has_load_ia32_efer) {
1507                         clear_atomic_switch_msr_special(vmx,
1508                                         VM_ENTRY_LOAD_IA32_EFER,
1509                                         VM_EXIT_LOAD_IA32_EFER);
1510                         return;
1511                 }
1512                 break;
1513         case MSR_CORE_PERF_GLOBAL_CTRL:
1514                 if (cpu_has_load_perf_global_ctrl) {
1515                         clear_atomic_switch_msr_special(vmx,
1516                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1518                         return;
1519                 }
1520                 break;
1521         }
1522
1523         for (i = 0; i < m->nr; ++i)
1524                 if (m->guest[i].index == msr)
1525                         break;
1526
1527         if (i == m->nr)
1528                 return;
1529         --m->nr;
1530         m->guest[i] = m->guest[m->nr];
1531         m->host[i] = m->host[m->nr];
1532         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1534 }
1535
1536 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537                 unsigned long entry, unsigned long exit,
1538                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539                 u64 guest_val, u64 host_val)
1540 {
1541         vmcs_write64(guest_val_vmcs, guest_val);
1542         vmcs_write64(host_val_vmcs, host_val);
1543         vm_entry_controls_setbit(vmx, entry);
1544         vm_exit_controls_setbit(vmx, exit);
1545 }
1546
1547 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548                                   u64 guest_val, u64 host_val)
1549 {
1550         unsigned i;
1551         struct msr_autoload *m = &vmx->msr_autoload;
1552
1553         switch (msr) {
1554         case MSR_EFER:
1555                 if (cpu_has_load_ia32_efer) {
1556                         add_atomic_switch_msr_special(vmx,
1557                                         VM_ENTRY_LOAD_IA32_EFER,
1558                                         VM_EXIT_LOAD_IA32_EFER,
1559                                         GUEST_IA32_EFER,
1560                                         HOST_IA32_EFER,
1561                                         guest_val, host_val);
1562                         return;
1563                 }
1564                 break;
1565         case MSR_CORE_PERF_GLOBAL_CTRL:
1566                 if (cpu_has_load_perf_global_ctrl) {
1567                         add_atomic_switch_msr_special(vmx,
1568                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1571                                         HOST_IA32_PERF_GLOBAL_CTRL,
1572                                         guest_val, host_val);
1573                         return;
1574                 }
1575                 break;
1576         }
1577
1578         for (i = 0; i < m->nr; ++i)
1579                 if (m->guest[i].index == msr)
1580                         break;
1581
1582         if (i == NR_AUTOLOAD_MSRS) {
1583                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1584                                 "Can't add msr %x\n", msr);
1585                 return;
1586         } else if (i == m->nr) {
1587                 ++m->nr;
1588                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1590         }
1591
1592         m->guest[i].index = msr;
1593         m->guest[i].value = guest_val;
1594         m->host[i].index = msr;
1595         m->host[i].value = host_val;
1596 }
1597
1598 static void reload_tss(void)
1599 {
1600         /*
1601          * VT restores TR but not its size.  Useless.
1602          */
1603         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1604         struct desc_struct *descs;
1605
1606         descs = (void *)gdt->address;
1607         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1608         load_TR_desc();
1609 }
1610
1611 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1612 {
1613         u64 guest_efer;
1614         u64 ignore_bits;
1615
1616         guest_efer = vmx->vcpu.arch.efer;
1617
1618         /*
1619          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1620          * outside long mode
1621          */
1622         ignore_bits = EFER_NX | EFER_SCE;
1623 #ifdef CONFIG_X86_64
1624         ignore_bits |= EFER_LMA | EFER_LME;
1625         /* SCE is meaningful only in long mode on Intel */
1626         if (guest_efer & EFER_LMA)
1627                 ignore_bits &= ~(u64)EFER_SCE;
1628 #endif
1629         guest_efer &= ~ignore_bits;
1630         guest_efer |= host_efer & ignore_bits;
1631         vmx->guest_msrs[efer_offset].data = guest_efer;
1632         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1633
1634         clear_atomic_switch_msr(vmx, MSR_EFER);
1635         /* On ept, can't emulate nx, and must switch nx atomically */
1636         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637                 guest_efer = vmx->vcpu.arch.efer;
1638                 if (!(guest_efer & EFER_LMA))
1639                         guest_efer &= ~EFER_LME;
1640                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1641                 return false;
1642         }
1643
1644         return true;
1645 }
1646
1647 static unsigned long segment_base(u16 selector)
1648 {
1649         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1650         struct desc_struct *d;
1651         unsigned long table_base;
1652         unsigned long v;
1653
1654         if (!(selector & ~3))
1655                 return 0;
1656
1657         table_base = gdt->address;
1658
1659         if (selector & 4) {           /* from ldt */
1660                 u16 ldt_selector = kvm_read_ldt();
1661
1662                 if (!(ldt_selector & ~3))
1663                         return 0;
1664
1665                 table_base = segment_base(ldt_selector);
1666         }
1667         d = (struct desc_struct *)(table_base + (selector & ~7));
1668         v = get_desc_base(d);
1669 #ifdef CONFIG_X86_64
1670        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1672 #endif
1673         return v;
1674 }
1675
1676 static inline unsigned long kvm_read_tr_base(void)
1677 {
1678         u16 tr;
1679         asm("str %0" : "=g"(tr));
1680         return segment_base(tr);
1681 }
1682
1683 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1684 {
1685         struct vcpu_vmx *vmx = to_vmx(vcpu);
1686         int i;
1687
1688         if (vmx->host_state.loaded)
1689                 return;
1690
1691         vmx->host_state.loaded = 1;
1692         /*
1693          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1694          * allow segment selectors with cpl > 0 or ti == 1.
1695          */
1696         vmx->host_state.ldt_sel = kvm_read_ldt();
1697         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1698         savesegment(fs, vmx->host_state.fs_sel);
1699         if (!(vmx->host_state.fs_sel & 7)) {
1700                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1701                 vmx->host_state.fs_reload_needed = 0;
1702         } else {
1703                 vmcs_write16(HOST_FS_SELECTOR, 0);
1704                 vmx->host_state.fs_reload_needed = 1;
1705         }
1706         savesegment(gs, vmx->host_state.gs_sel);
1707         if (!(vmx->host_state.gs_sel & 7))
1708                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1709         else {
1710                 vmcs_write16(HOST_GS_SELECTOR, 0);
1711                 vmx->host_state.gs_ldt_reload_needed = 1;
1712         }
1713
1714 #ifdef CONFIG_X86_64
1715         savesegment(ds, vmx->host_state.ds_sel);
1716         savesegment(es, vmx->host_state.es_sel);
1717 #endif
1718
1719 #ifdef CONFIG_X86_64
1720         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1722 #else
1723         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1725 #endif
1726
1727 #ifdef CONFIG_X86_64
1728         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729         if (is_long_mode(&vmx->vcpu))
1730                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1731 #endif
1732         if (boot_cpu_has(X86_FEATURE_MPX))
1733                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1734         for (i = 0; i < vmx->save_nmsrs; ++i)
1735                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1736                                    vmx->guest_msrs[i].data,
1737                                    vmx->guest_msrs[i].mask);
1738 }
1739
1740 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1741 {
1742         if (!vmx->host_state.loaded)
1743                 return;
1744
1745         ++vmx->vcpu.stat.host_state_reload;
1746         vmx->host_state.loaded = 0;
1747 #ifdef CONFIG_X86_64
1748         if (is_long_mode(&vmx->vcpu))
1749                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1750 #endif
1751         if (vmx->host_state.gs_ldt_reload_needed) {
1752                 kvm_load_ldt(vmx->host_state.ldt_sel);
1753 #ifdef CONFIG_X86_64
1754                 load_gs_index(vmx->host_state.gs_sel);
1755 #else
1756                 loadsegment(gs, vmx->host_state.gs_sel);
1757 #endif
1758         }
1759         if (vmx->host_state.fs_reload_needed)
1760                 loadsegment(fs, vmx->host_state.fs_sel);
1761 #ifdef CONFIG_X86_64
1762         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763                 loadsegment(ds, vmx->host_state.ds_sel);
1764                 loadsegment(es, vmx->host_state.es_sel);
1765         }
1766 #endif
1767         reload_tss();
1768 #ifdef CONFIG_X86_64
1769         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1770 #endif
1771         if (vmx->host_state.msr_host_bndcfgs)
1772                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1773         /*
1774          * If the FPU is not active (through the host task or
1775          * the guest vcpu), then restore the cr0.TS bit.
1776          */
1777         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1778                 stts();
1779         load_gdt(&__get_cpu_var(host_gdt));
1780 }
1781
1782 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1783 {
1784         preempt_disable();
1785         __vmx_load_host_state(vmx);
1786         preempt_enable();
1787 }
1788
1789 /*
1790  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791  * vcpu mutex is already taken.
1792  */
1793 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1794 {
1795         struct vcpu_vmx *vmx = to_vmx(vcpu);
1796         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1797
1798         if (!vmm_exclusive)
1799                 kvm_cpu_vmxon(phys_addr);
1800         else if (vmx->loaded_vmcs->cpu != cpu)
1801                 loaded_vmcs_clear(vmx->loaded_vmcs);
1802
1803         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805                 vmcs_load(vmx->loaded_vmcs->vmcs);
1806         }
1807
1808         if (vmx->loaded_vmcs->cpu != cpu) {
1809                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1810                 unsigned long sysenter_esp;
1811
1812                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1813                 local_irq_disable();
1814                 crash_disable_local_vmclear(cpu);
1815
1816                 /*
1817                  * Read loaded_vmcs->cpu should be before fetching
1818                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819                  * See the comments in __loaded_vmcs_clear().
1820                  */
1821                 smp_rmb();
1822
1823                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1825                 crash_enable_local_vmclear(cpu);
1826                 local_irq_enable();
1827
1828                 /*
1829                  * Linux uses per-cpu TSS and GDT, so set these when switching
1830                  * processors.
1831                  */
1832                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1833                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1834
1835                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1837                 vmx->loaded_vmcs->cpu = cpu;
1838         }
1839 }
1840
1841 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1842 {
1843         __vmx_load_host_state(to_vmx(vcpu));
1844         if (!vmm_exclusive) {
1845                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1846                 vcpu->cpu = -1;
1847                 kvm_cpu_vmxoff();
1848         }
1849 }
1850
1851 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1852 {
1853         ulong cr0;
1854
1855         if (vcpu->fpu_active)
1856                 return;
1857         vcpu->fpu_active = 1;
1858         cr0 = vmcs_readl(GUEST_CR0);
1859         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861         vmcs_writel(GUEST_CR0, cr0);
1862         update_exception_bitmap(vcpu);
1863         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1864         if (is_guest_mode(vcpu))
1865                 vcpu->arch.cr0_guest_owned_bits &=
1866                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1867         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1868 }
1869
1870 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1871
1872 /*
1873  * Return the cr0 value that a nested guest would read. This is a combination
1874  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875  * its hypervisor (cr0_read_shadow).
1876  */
1877 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1878 {
1879         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1881 }
1882 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1883 {
1884         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1886 }
1887
1888 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1889 {
1890         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891          * set this *before* calling this function.
1892          */
1893         vmx_decache_cr0_guest_bits(vcpu);
1894         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1895         update_exception_bitmap(vcpu);
1896         vcpu->arch.cr0_guest_owned_bits = 0;
1897         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1898         if (is_guest_mode(vcpu)) {
1899                 /*
1900                  * L1's specified read shadow might not contain the TS bit,
1901                  * so now that we turned on shadowing of this bit, we need to
1902                  * set this bit of the shadow. Like in nested_vmx_run we need
1903                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904                  * up-to-date here because we just decached cr0.TS (and we'll
1905                  * only update vmcs12->guest_cr0 on nested exit).
1906                  */
1907                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909                         (vcpu->arch.cr0 & X86_CR0_TS);
1910                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1911         } else
1912                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1913 }
1914
1915 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1916 {
1917         unsigned long rflags, save_rflags;
1918
1919         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921                 rflags = vmcs_readl(GUEST_RFLAGS);
1922                 if (to_vmx(vcpu)->rmode.vm86_active) {
1923                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1926                 }
1927                 to_vmx(vcpu)->rflags = rflags;
1928         }
1929         return to_vmx(vcpu)->rflags;
1930 }
1931
1932 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1933 {
1934         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935         to_vmx(vcpu)->rflags = rflags;
1936         if (to_vmx(vcpu)->rmode.vm86_active) {
1937                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1938                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1939         }
1940         vmcs_writel(GUEST_RFLAGS, rflags);
1941 }
1942
1943 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1944 {
1945         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1946         int ret = 0;
1947
1948         if (interruptibility & GUEST_INTR_STATE_STI)
1949                 ret |= KVM_X86_SHADOW_INT_STI;
1950         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1951                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1952
1953         return ret & mask;
1954 }
1955
1956 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1957 {
1958         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959         u32 interruptibility = interruptibility_old;
1960
1961         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1962
1963         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1964                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1965         else if (mask & KVM_X86_SHADOW_INT_STI)
1966                 interruptibility |= GUEST_INTR_STATE_STI;
1967
1968         if ((interruptibility != interruptibility_old))
1969                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1970 }
1971
1972 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1973 {
1974         unsigned long rip;
1975
1976         rip = kvm_rip_read(vcpu);
1977         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1978         kvm_rip_write(vcpu, rip);
1979
1980         /* skipping an emulated instruction also counts */
1981         vmx_set_interrupt_shadow(vcpu, 0);
1982 }
1983
1984 /*
1985  * KVM wants to inject page-faults which it got to the guest. This function
1986  * checks whether in a nested guest, we need to inject them to L1 or L2.
1987  */
1988 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
1989 {
1990         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1991
1992         if (!(vmcs12->exception_bitmap & (1u << nr)))
1993                 return 0;
1994
1995         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996                           vmcs_read32(VM_EXIT_INTR_INFO),
1997                           vmcs_readl(EXIT_QUALIFICATION));
1998         return 1;
1999 }
2000
2001 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2002                                 bool has_error_code, u32 error_code,
2003                                 bool reinject)
2004 {
2005         struct vcpu_vmx *vmx = to_vmx(vcpu);
2006         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2007
2008         if (!reinject && is_guest_mode(vcpu) &&
2009             nested_vmx_check_exception(vcpu, nr))
2010                 return;
2011
2012         if (has_error_code) {
2013                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2014                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2015         }
2016
2017         if (vmx->rmode.vm86_active) {
2018                 int inc_eip = 0;
2019                 if (kvm_exception_is_soft(nr))
2020                         inc_eip = vcpu->arch.event_exit_inst_len;
2021                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2022                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2023                 return;
2024         }
2025
2026         if (kvm_exception_is_soft(nr)) {
2027                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028                              vmx->vcpu.arch.event_exit_inst_len);
2029                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2030         } else
2031                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2032
2033         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2034 }
2035
2036 static bool vmx_rdtscp_supported(void)
2037 {
2038         return cpu_has_vmx_rdtscp();
2039 }
2040
2041 static bool vmx_invpcid_supported(void)
2042 {
2043         return cpu_has_vmx_invpcid() && enable_ept;
2044 }
2045
2046 /*
2047  * Swap MSR entry in host/guest MSR entry array.
2048  */
2049 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2050 {
2051         struct shared_msr_entry tmp;
2052
2053         tmp = vmx->guest_msrs[to];
2054         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055         vmx->guest_msrs[from] = tmp;
2056 }
2057
2058 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2059 {
2060         unsigned long *msr_bitmap;
2061
2062         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063                 if (is_long_mode(vcpu))
2064                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2065                 else
2066                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2067         } else {
2068                 if (is_long_mode(vcpu))
2069                         msr_bitmap = vmx_msr_bitmap_longmode;
2070                 else
2071                         msr_bitmap = vmx_msr_bitmap_legacy;
2072         }
2073
2074         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2075 }
2076
2077 /*
2078  * Set up the vmcs to automatically save and restore system
2079  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2080  * mode, as fiddling with msrs is very expensive.
2081  */
2082 static void setup_msrs(struct vcpu_vmx *vmx)
2083 {
2084         int save_nmsrs, index;
2085
2086         save_nmsrs = 0;
2087 #ifdef CONFIG_X86_64
2088         if (is_long_mode(&vmx->vcpu)) {
2089                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2090                 if (index >= 0)
2091                         move_msr_up(vmx, index, save_nmsrs++);
2092                 index = __find_msr_index(vmx, MSR_LSTAR);
2093                 if (index >= 0)
2094                         move_msr_up(vmx, index, save_nmsrs++);
2095                 index = __find_msr_index(vmx, MSR_CSTAR);
2096                 if (index >= 0)
2097                         move_msr_up(vmx, index, save_nmsrs++);
2098                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099                 if (index >= 0 && vmx->rdtscp_enabled)
2100                         move_msr_up(vmx, index, save_nmsrs++);
2101                 /*
2102                  * MSR_STAR is only needed on long mode guests, and only
2103                  * if efer.sce is enabled.
2104                  */
2105                 index = __find_msr_index(vmx, MSR_STAR);
2106                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2107                         move_msr_up(vmx, index, save_nmsrs++);
2108         }
2109 #endif
2110         index = __find_msr_index(vmx, MSR_EFER);
2111         if (index >= 0 && update_transition_efer(vmx, index))
2112                 move_msr_up(vmx, index, save_nmsrs++);
2113
2114         vmx->save_nmsrs = save_nmsrs;
2115
2116         if (cpu_has_vmx_msr_bitmap())
2117                 vmx_set_msr_bitmap(&vmx->vcpu);
2118 }
2119
2120 /*
2121  * reads and returns guest's timestamp counter "register"
2122  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2123  */
2124 static u64 guest_read_tsc(void)
2125 {
2126         u64 host_tsc, tsc_offset;
2127
2128         rdtscll(host_tsc);
2129         tsc_offset = vmcs_read64(TSC_OFFSET);
2130         return host_tsc + tsc_offset;
2131 }
2132
2133 /*
2134  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135  * counter, even if a nested guest (L2) is currently running.
2136  */
2137 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2138 {
2139         u64 tsc_offset;
2140
2141         tsc_offset = is_guest_mode(vcpu) ?
2142                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143                 vmcs_read64(TSC_OFFSET);
2144         return host_tsc + tsc_offset;
2145 }
2146
2147 /*
2148  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2149  * software catchup for faster rates on slower CPUs.
2150  */
2151 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2152 {
2153         if (!scale)
2154                 return;
2155
2156         if (user_tsc_khz > tsc_khz) {
2157                 vcpu->arch.tsc_catchup = 1;
2158                 vcpu->arch.tsc_always_catchup = 1;
2159         } else
2160                 WARN(1, "user requested TSC rate below hardware speed\n");
2161 }
2162
2163 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2164 {
2165         return vmcs_read64(TSC_OFFSET);
2166 }
2167
2168 /*
2169  * writes 'offset' into guest's timestamp counter offset register
2170  */
2171 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2172 {
2173         if (is_guest_mode(vcpu)) {
2174                 /*
2175                  * We're here if L1 chose not to trap WRMSR to TSC. According
2176                  * to the spec, this should set L1's TSC; The offset that L1
2177                  * set for L2 remains unchanged, and still needs to be added
2178                  * to the newly set TSC to get L2's TSC.
2179                  */
2180                 struct vmcs12 *vmcs12;
2181                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182                 /* recalculate vmcs02.TSC_OFFSET: */
2183                 vmcs12 = get_vmcs12(vcpu);
2184                 vmcs_write64(TSC_OFFSET, offset +
2185                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186                          vmcs12->tsc_offset : 0));
2187         } else {
2188                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189                                            vmcs_read64(TSC_OFFSET), offset);
2190                 vmcs_write64(TSC_OFFSET, offset);
2191         }
2192 }
2193
2194 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2195 {
2196         u64 offset = vmcs_read64(TSC_OFFSET);
2197
2198         vmcs_write64(TSC_OFFSET, offset + adjustment);
2199         if (is_guest_mode(vcpu)) {
2200                 /* Even when running L2, the adjustment needs to apply to L1 */
2201                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2202         } else
2203                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204                                            offset + adjustment);
2205 }
2206
2207 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2208 {
2209         return target_tsc - native_read_tsc();
2210 }
2211
2212 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2213 {
2214         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2216 }
2217
2218 /*
2219  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221  * all guests if the "nested" module option is off, and can also be disabled
2222  * for a single guest by disabling its VMX cpuid bit.
2223  */
2224 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2225 {
2226         return nested && guest_cpuid_has_vmx(vcpu);
2227 }
2228
2229 /*
2230  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231  * returned for the various VMX controls MSRs when nested VMX is enabled.
2232  * The same values should also be used to verify that vmcs12 control fields are
2233  * valid during nested entry from L1 to L2.
2234  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236  * bit in the high half is on if the corresponding bit in the control field
2237  * may be on. See also vmx_control_verify().
2238  * TODO: allow these variables to be modified (downgraded) by module options
2239  * or other means.
2240  */
2241 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2242 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2243 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2244 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2245 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2246 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2247 static u32 nested_vmx_ept_caps;
2248 static __init void nested_vmx_setup_ctls_msrs(void)
2249 {
2250         /*
2251          * Note that as a general rule, the high half of the MSRs (bits in
2252          * the control fields which may be 1) should be initialized by the
2253          * intersection of the underlying hardware's MSR (i.e., features which
2254          * can be supported) and the list of features we want to expose -
2255          * because they are known to be properly supported in our code.
2256          * Also, usually, the low half of the MSRs (bits which must be 1) can
2257          * be set to 0, meaning that L1 may turn off any of these bits. The
2258          * reason is that if one of these bits is necessary, it will appear
2259          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2260          * fields of vmcs01 and vmcs02, will turn these bits off - and
2261          * nested_vmx_exit_handled() will not pass related exits to L1.
2262          * These rules have exceptions below.
2263          */
2264
2265         /* pin-based controls */
2266         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2267               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2268         /*
2269          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2270          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2271          */
2272         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2273         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2274                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2275         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2276                 PIN_BASED_VMX_PREEMPTION_TIMER;
2277
2278         /*
2279          * Exit controls
2280          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2281          * 17 must be 1.
2282          */
2283         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2284                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2285         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2286         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2287         nested_vmx_exit_ctls_high &=
2288 #ifdef CONFIG_X86_64
2289                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2290 #endif
2291                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2292         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2293                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2294                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2295         if (vmx_mpx_supported())
2296                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2297
2298         /* entry controls */
2299         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2300                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2301         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2302         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2303         nested_vmx_entry_ctls_high &=
2304 #ifdef CONFIG_X86_64
2305                 VM_ENTRY_IA32E_MODE |
2306 #endif
2307                 VM_ENTRY_LOAD_IA32_PAT;
2308         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2309                                        VM_ENTRY_LOAD_IA32_EFER);
2310         if (vmx_mpx_supported())
2311                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2312
2313         /* cpu-based controls */
2314         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2315                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2316         nested_vmx_procbased_ctls_low = 0;
2317         nested_vmx_procbased_ctls_high &=
2318                 CPU_BASED_VIRTUAL_INTR_PENDING |
2319                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2320                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2321                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2322                 CPU_BASED_CR3_STORE_EXITING |
2323 #ifdef CONFIG_X86_64
2324                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2325 #endif
2326                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2327                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2328                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2329                 CPU_BASED_PAUSE_EXITING |
2330                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2331         /*
2332          * We can allow some features even when not supported by the
2333          * hardware. For example, L1 can specify an MSR bitmap - and we
2334          * can use it to avoid exits to L1 - even when L0 runs L2
2335          * without MSR bitmaps.
2336          */
2337         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2338
2339         /* secondary cpu-based controls */
2340         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2341                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2342         nested_vmx_secondary_ctls_low = 0;
2343         nested_vmx_secondary_ctls_high &=
2344                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2345                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2346                 SECONDARY_EXEC_WBINVD_EXITING;
2347
2348         if (enable_ept) {
2349                 /* nested EPT: emulate EPT also to L1 */
2350                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2351                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2352                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2353                          VMX_EPT_INVEPT_BIT;
2354                 nested_vmx_ept_caps &= vmx_capability.ept;
2355                 /*
2356                  * For nested guests, we don't do anything specific
2357                  * for single context invalidation. Hence, only advertise
2358                  * support for global context invalidation.
2359                  */
2360                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2361         } else
2362                 nested_vmx_ept_caps = 0;
2363
2364         /* miscellaneous data */
2365         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2366         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2367         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2368                 VMX_MISC_ACTIVITY_HLT;
2369         nested_vmx_misc_high = 0;
2370 }
2371
2372 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2373 {
2374         /*
2375          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2376          */
2377         return ((control & high) | low) == control;
2378 }
2379
2380 static inline u64 vmx_control_msr(u32 low, u32 high)
2381 {
2382         return low | ((u64)high << 32);
2383 }
2384
2385 /* Returns 0 on success, non-0 otherwise. */
2386 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2387 {
2388         switch (msr_index) {
2389         case MSR_IA32_VMX_BASIC:
2390                 /*
2391                  * This MSR reports some information about VMX support. We
2392                  * should return information about the VMX we emulate for the
2393                  * guest, and the VMCS structure we give it - not about the
2394                  * VMX support of the underlying hardware.
2395                  */
2396                 *pdata = VMCS12_REVISION |
2397                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2398                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2399                 break;
2400         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2401         case MSR_IA32_VMX_PINBASED_CTLS:
2402                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2403                                         nested_vmx_pinbased_ctls_high);
2404                 break;
2405         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2406         case MSR_IA32_VMX_PROCBASED_CTLS:
2407                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2408                                         nested_vmx_procbased_ctls_high);
2409                 break;
2410         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2411         case MSR_IA32_VMX_EXIT_CTLS:
2412                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2413                                         nested_vmx_exit_ctls_high);
2414                 break;
2415         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2416         case MSR_IA32_VMX_ENTRY_CTLS:
2417                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2418                                         nested_vmx_entry_ctls_high);
2419                 break;
2420         case MSR_IA32_VMX_MISC:
2421                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2422                                          nested_vmx_misc_high);
2423                 break;
2424         /*
2425          * These MSRs specify bits which the guest must keep fixed (on or off)
2426          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2427          * We picked the standard core2 setting.
2428          */
2429 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2430 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2431         case MSR_IA32_VMX_CR0_FIXED0:
2432                 *pdata = VMXON_CR0_ALWAYSON;
2433                 break;
2434         case MSR_IA32_VMX_CR0_FIXED1:
2435                 *pdata = -1ULL;
2436                 break;
2437         case MSR_IA32_VMX_CR4_FIXED0:
2438                 *pdata = VMXON_CR4_ALWAYSON;
2439                 break;
2440         case MSR_IA32_VMX_CR4_FIXED1:
2441                 *pdata = -1ULL;
2442                 break;
2443         case MSR_IA32_VMX_VMCS_ENUM:
2444                 *pdata = 0x1f;
2445                 break;
2446         case MSR_IA32_VMX_PROCBASED_CTLS2:
2447                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2448                                         nested_vmx_secondary_ctls_high);
2449                 break;
2450         case MSR_IA32_VMX_EPT_VPID_CAP:
2451                 /* Currently, no nested vpid support */
2452                 *pdata = nested_vmx_ept_caps;
2453                 break;
2454         default:
2455                 return 1;
2456         }
2457
2458         return 0;
2459 }
2460
2461 /*
2462  * Reads an msr value (of 'msr_index') into 'pdata'.
2463  * Returns 0 on success, non-0 otherwise.
2464  * Assumes vcpu_load() was already called.
2465  */
2466 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2467 {
2468         u64 data;
2469         struct shared_msr_entry *msr;
2470
2471         if (!pdata) {
2472                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2473                 return -EINVAL;
2474         }
2475
2476         switch (msr_index) {
2477 #ifdef CONFIG_X86_64
2478         case MSR_FS_BASE:
2479                 data = vmcs_readl(GUEST_FS_BASE);
2480                 break;
2481         case MSR_GS_BASE:
2482                 data = vmcs_readl(GUEST_GS_BASE);
2483                 break;
2484         case MSR_KERNEL_GS_BASE:
2485                 vmx_load_host_state(to_vmx(vcpu));
2486                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2487                 break;
2488 #endif
2489         case MSR_EFER:
2490                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2491         case MSR_IA32_TSC:
2492                 data = guest_read_tsc();
2493                 break;
2494         case MSR_IA32_SYSENTER_CS:
2495                 data = vmcs_read32(GUEST_SYSENTER_CS);
2496                 break;
2497         case MSR_IA32_SYSENTER_EIP:
2498                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2499                 break;
2500         case MSR_IA32_SYSENTER_ESP:
2501                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2502                 break;
2503         case MSR_IA32_BNDCFGS:
2504                 if (!vmx_mpx_supported())
2505                         return 1;
2506                 data = vmcs_read64(GUEST_BNDCFGS);
2507                 break;
2508         case MSR_IA32_FEATURE_CONTROL:
2509                 if (!nested_vmx_allowed(vcpu))
2510                         return 1;
2511                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2512                 break;
2513         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2514                 if (!nested_vmx_allowed(vcpu))
2515                         return 1;
2516                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2517         case MSR_TSC_AUX:
2518                 if (!to_vmx(vcpu)->rdtscp_enabled)
2519                         return 1;
2520                 /* Otherwise falls through */
2521         default:
2522                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2523                 if (msr) {
2524                         data = msr->data;
2525                         break;
2526                 }
2527                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2528         }
2529
2530         *pdata = data;
2531         return 0;
2532 }
2533
2534 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2535
2536 /*
2537  * Writes msr value into into the appropriate "register".
2538  * Returns 0 on success, non-0 otherwise.
2539  * Assumes vcpu_load() was already called.
2540  */
2541 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2542 {
2543         struct vcpu_vmx *vmx = to_vmx(vcpu);
2544         struct shared_msr_entry *msr;
2545         int ret = 0;
2546         u32 msr_index = msr_info->index;
2547         u64 data = msr_info->data;
2548
2549         switch (msr_index) {
2550         case MSR_EFER:
2551                 ret = kvm_set_msr_common(vcpu, msr_info);
2552                 break;
2553 #ifdef CONFIG_X86_64
2554         case MSR_FS_BASE:
2555                 vmx_segment_cache_clear(vmx);
2556                 vmcs_writel(GUEST_FS_BASE, data);
2557                 break;
2558         case MSR_GS_BASE:
2559                 vmx_segment_cache_clear(vmx);
2560                 vmcs_writel(GUEST_GS_BASE, data);
2561                 break;
2562         case MSR_KERNEL_GS_BASE:
2563                 vmx_load_host_state(vmx);
2564                 vmx->msr_guest_kernel_gs_base = data;
2565                 break;
2566 #endif
2567         case MSR_IA32_SYSENTER_CS:
2568                 vmcs_write32(GUEST_SYSENTER_CS, data);
2569                 break;
2570         case MSR_IA32_SYSENTER_EIP:
2571                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2572                 break;
2573         case MSR_IA32_SYSENTER_ESP:
2574                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2575                 break;
2576         case MSR_IA32_BNDCFGS:
2577                 if (!vmx_mpx_supported())
2578                         return 1;
2579                 vmcs_write64(GUEST_BNDCFGS, data);
2580                 break;
2581         case MSR_IA32_TSC:
2582                 kvm_write_tsc(vcpu, msr_info);
2583                 break;
2584         case MSR_IA32_CR_PAT:
2585                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2586                         vmcs_write64(GUEST_IA32_PAT, data);
2587                         vcpu->arch.pat = data;
2588                         break;
2589                 }
2590                 ret = kvm_set_msr_common(vcpu, msr_info);
2591                 break;
2592         case MSR_IA32_TSC_ADJUST:
2593                 ret = kvm_set_msr_common(vcpu, msr_info);
2594                 break;
2595         case MSR_IA32_FEATURE_CONTROL:
2596                 if (!nested_vmx_allowed(vcpu) ||
2597                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2598                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2599                         return 1;
2600                 vmx->nested.msr_ia32_feature_control = data;
2601                 if (msr_info->host_initiated && data == 0)
2602                         vmx_leave_nested(vcpu);
2603                 break;
2604         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2605                 return 1; /* they are read-only */
2606         case MSR_TSC_AUX:
2607                 if (!vmx->rdtscp_enabled)
2608                         return 1;
2609                 /* Check reserved bit, higher 32 bits should be zero */
2610                 if ((data >> 32) != 0)
2611                         return 1;
2612                 /* Otherwise falls through */
2613         default:
2614                 msr = find_msr_entry(vmx, msr_index);
2615                 if (msr) {
2616                         msr->data = data;
2617                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2618                                 preempt_disable();
2619                                 kvm_set_shared_msr(msr->index, msr->data,
2620                                                    msr->mask);
2621                                 preempt_enable();
2622                         }
2623                         break;
2624                 }
2625                 ret = kvm_set_msr_common(vcpu, msr_info);
2626         }
2627
2628         return ret;
2629 }
2630
2631 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2632 {
2633         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2634         switch (reg) {
2635         case VCPU_REGS_RSP:
2636                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2637                 break;
2638         case VCPU_REGS_RIP:
2639                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2640                 break;
2641         case VCPU_EXREG_PDPTR:
2642                 if (enable_ept)
2643                         ept_save_pdptrs(vcpu);
2644                 break;
2645         default:
2646                 break;
2647         }
2648 }
2649
2650 static __init int cpu_has_kvm_support(void)
2651 {
2652         return cpu_has_vmx();
2653 }
2654
2655 static __init int vmx_disabled_by_bios(void)
2656 {
2657         u64 msr;
2658
2659         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2660         if (msr & FEATURE_CONTROL_LOCKED) {
2661                 /* launched w/ TXT and VMX disabled */
2662                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2663                         && tboot_enabled())
2664                         return 1;
2665                 /* launched w/o TXT and VMX only enabled w/ TXT */
2666                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2667                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2668                         && !tboot_enabled()) {
2669                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2670                                 "activate TXT before enabling KVM\n");
2671                         return 1;
2672                 }
2673                 /* launched w/o TXT and VMX disabled */
2674                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2675                         && !tboot_enabled())
2676                         return 1;
2677         }
2678
2679         return 0;
2680 }
2681
2682 static void kvm_cpu_vmxon(u64 addr)
2683 {
2684         asm volatile (ASM_VMX_VMXON_RAX
2685                         : : "a"(&addr), "m"(addr)
2686                         : "memory", "cc");
2687 }
2688
2689 static int hardware_enable(void *garbage)
2690 {
2691         int cpu = raw_smp_processor_id();
2692         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2693         u64 old, test_bits;
2694
2695         if (read_cr4() & X86_CR4_VMXE)
2696                 return -EBUSY;
2697
2698         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2699
2700         /*
2701          * Now we can enable the vmclear operation in kdump
2702          * since the loaded_vmcss_on_cpu list on this cpu
2703          * has been initialized.
2704          *
2705          * Though the cpu is not in VMX operation now, there
2706          * is no problem to enable the vmclear operation
2707          * for the loaded_vmcss_on_cpu list is empty!
2708          */
2709         crash_enable_local_vmclear(cpu);
2710
2711         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2712
2713         test_bits = FEATURE_CONTROL_LOCKED;
2714         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2715         if (tboot_enabled())
2716                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2717
2718         if ((old & test_bits) != test_bits) {
2719                 /* enable and lock */
2720                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2721         }
2722         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2723
2724         if (vmm_exclusive) {
2725                 kvm_cpu_vmxon(phys_addr);
2726                 ept_sync_global();
2727         }
2728
2729         native_store_gdt(&__get_cpu_var(host_gdt));
2730
2731         return 0;
2732 }
2733
2734 static void vmclear_local_loaded_vmcss(void)
2735 {
2736         int cpu = raw_smp_processor_id();
2737         struct loaded_vmcs *v, *n;
2738
2739         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2740                                  loaded_vmcss_on_cpu_link)
2741                 __loaded_vmcs_clear(v);
2742 }
2743
2744
2745 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2746  * tricks.
2747  */
2748 static void kvm_cpu_vmxoff(void)
2749 {
2750         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2751 }
2752
2753 static void hardware_disable(void *garbage)
2754 {
2755         if (vmm_exclusive) {
2756                 vmclear_local_loaded_vmcss();
2757                 kvm_cpu_vmxoff();
2758         }
2759         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2760 }
2761
2762 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2763                                       u32 msr, u32 *result)
2764 {
2765         u32 vmx_msr_low, vmx_msr_high;
2766         u32 ctl = ctl_min | ctl_opt;
2767
2768         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2769
2770         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2771         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2772
2773         /* Ensure minimum (required) set of control bits are supported. */
2774         if (ctl_min & ~ctl)
2775                 return -EIO;
2776
2777         *result = ctl;
2778         return 0;
2779 }
2780
2781 static __init bool allow_1_setting(u32 msr, u32 ctl)
2782 {
2783         u32 vmx_msr_low, vmx_msr_high;
2784
2785         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2786         return vmx_msr_high & ctl;
2787 }
2788
2789 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2790 {
2791         u32 vmx_msr_low, vmx_msr_high;
2792         u32 min, opt, min2, opt2;
2793         u32 _pin_based_exec_control = 0;
2794         u32 _cpu_based_exec_control = 0;
2795         u32 _cpu_based_2nd_exec_control = 0;
2796         u32 _vmexit_control = 0;
2797         u32 _vmentry_control = 0;
2798
2799         min = CPU_BASED_HLT_EXITING |
2800 #ifdef CONFIG_X86_64
2801               CPU_BASED_CR8_LOAD_EXITING |
2802               CPU_BASED_CR8_STORE_EXITING |
2803 #endif
2804               CPU_BASED_CR3_LOAD_EXITING |
2805               CPU_BASED_CR3_STORE_EXITING |
2806               CPU_BASED_USE_IO_BITMAPS |
2807               CPU_BASED_MOV_DR_EXITING |
2808               CPU_BASED_USE_TSC_OFFSETING |
2809               CPU_BASED_MWAIT_EXITING |
2810               CPU_BASED_MONITOR_EXITING |
2811               CPU_BASED_INVLPG_EXITING |
2812               CPU_BASED_RDPMC_EXITING;
2813
2814         opt = CPU_BASED_TPR_SHADOW |
2815               CPU_BASED_USE_MSR_BITMAPS |
2816               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2817         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2818                                 &_cpu_based_exec_control) < 0)
2819                 return -EIO;
2820 #ifdef CONFIG_X86_64
2821         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2822                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2823                                            ~CPU_BASED_CR8_STORE_EXITING;
2824 #endif
2825         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2826                 min2 = 0;
2827                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2828                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2829                         SECONDARY_EXEC_WBINVD_EXITING |
2830                         SECONDARY_EXEC_ENABLE_VPID |
2831                         SECONDARY_EXEC_ENABLE_EPT |
2832                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2833                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2834                         SECONDARY_EXEC_RDTSCP |
2835                         SECONDARY_EXEC_ENABLE_INVPCID |
2836                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2837                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2838                         SECONDARY_EXEC_SHADOW_VMCS;
2839                 if (adjust_vmx_controls(min2, opt2,
2840                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2841                                         &_cpu_based_2nd_exec_control) < 0)
2842                         return -EIO;
2843         }
2844 #ifndef CONFIG_X86_64
2845         if (!(_cpu_based_2nd_exec_control &
2846                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2847                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2848 #endif
2849
2850         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2851                 _cpu_based_2nd_exec_control &= ~(
2852                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2853                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2854                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2855
2856         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2857                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2858                    enabled */
2859                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2860                                              CPU_BASED_CR3_STORE_EXITING |
2861                                              CPU_BASED_INVLPG_EXITING);
2862                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2863                       vmx_capability.ept, vmx_capability.vpid);
2864         }
2865
2866         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2867 #ifdef CONFIG_X86_64
2868         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2869 #endif
2870         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2871                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2872         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2873                                 &_vmexit_control) < 0)
2874                 return -EIO;
2875
2876         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2877         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2878         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2879                                 &_pin_based_exec_control) < 0)
2880                 return -EIO;
2881
2882         if (!(_cpu_based_2nd_exec_control &
2883                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2884                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2885                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2886
2887         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2888         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2889         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2890                                 &_vmentry_control) < 0)
2891                 return -EIO;
2892
2893         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2894
2895         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2896         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2897                 return -EIO;
2898
2899 #ifdef CONFIG_X86_64
2900         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2901         if (vmx_msr_high & (1u<<16))
2902                 return -EIO;
2903 #endif
2904
2905         /* Require Write-Back (WB) memory type for VMCS accesses. */
2906         if (((vmx_msr_high >> 18) & 15) != 6)
2907                 return -EIO;
2908
2909         vmcs_conf->size = vmx_msr_high & 0x1fff;
2910         vmcs_conf->order = get_order(vmcs_config.size);
2911         vmcs_conf->revision_id = vmx_msr_low;
2912
2913         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2914         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2915         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2916         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2917         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2918
2919         cpu_has_load_ia32_efer =
2920                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2921                                 VM_ENTRY_LOAD_IA32_EFER)
2922                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2923                                    VM_EXIT_LOAD_IA32_EFER);
2924
2925         cpu_has_load_perf_global_ctrl =
2926                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2927                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2928                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2929                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2930
2931         /*
2932          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2933          * but due to arrata below it can't be used. Workaround is to use
2934          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2935          *
2936          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2937          *
2938          * AAK155             (model 26)
2939          * AAP115             (model 30)
2940          * AAT100             (model 37)
2941          * BC86,AAY89,BD102   (model 44)
2942          * BA97               (model 46)
2943          *
2944          */
2945         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2946                 switch (boot_cpu_data.x86_model) {
2947                 case 26:
2948                 case 30:
2949                 case 37:
2950                 case 44:
2951                 case 46:
2952                         cpu_has_load_perf_global_ctrl = false;
2953                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2954                                         "does not work properly. Using workaround\n");
2955                         break;
2956                 default:
2957                         break;
2958                 }
2959         }
2960
2961         return 0;
2962 }
2963
2964 static struct vmcs *alloc_vmcs_cpu(int cpu)
2965 {
2966         int node = cpu_to_node(cpu);
2967         struct page *pages;
2968         struct vmcs *vmcs;
2969
2970         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2971         if (!pages)
2972                 return NULL;
2973         vmcs = page_address(pages);
2974         memset(vmcs, 0, vmcs_config.size);
2975         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2976         return vmcs;
2977 }
2978
2979 static struct vmcs *alloc_vmcs(void)
2980 {
2981         return alloc_vmcs_cpu(raw_smp_processor_id());
2982 }
2983
2984 static void free_vmcs(struct vmcs *vmcs)
2985 {
2986         free_pages((unsigned long)vmcs, vmcs_config.order);
2987 }
2988
2989 /*
2990  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2991  */
2992 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2993 {
2994         if (!loaded_vmcs->vmcs)
2995                 return;
2996         loaded_vmcs_clear(loaded_vmcs);
2997         free_vmcs(loaded_vmcs->vmcs);
2998         loaded_vmcs->vmcs = NULL;
2999 }
3000
3001 static void free_kvm_area(void)
3002 {
3003         int cpu;
3004
3005         for_each_possible_cpu(cpu) {
3006                 free_vmcs(per_cpu(vmxarea, cpu));
3007                 per_cpu(vmxarea, cpu) = NULL;
3008         }
3009 }
3010
3011 static __init int alloc_kvm_area(void)
3012 {
3013         int cpu;
3014
3015         for_each_possible_cpu(cpu) {
3016                 struct vmcs *vmcs;
3017
3018                 vmcs = alloc_vmcs_cpu(cpu);
3019                 if (!vmcs) {
3020                         free_kvm_area();
3021                         return -ENOMEM;
3022                 }
3023
3024                 per_cpu(vmxarea, cpu) = vmcs;
3025         }
3026         return 0;
3027 }
3028
3029 static __init int hardware_setup(void)
3030 {
3031         if (setup_vmcs_config(&vmcs_config) < 0)
3032                 return -EIO;
3033
3034         if (boot_cpu_has(X86_FEATURE_NX))
3035                 kvm_enable_efer_bits(EFER_NX);
3036
3037         if (!cpu_has_vmx_vpid())
3038                 enable_vpid = 0;
3039         if (!cpu_has_vmx_shadow_vmcs())
3040                 enable_shadow_vmcs = 0;
3041
3042         if (!cpu_has_vmx_ept() ||
3043             !cpu_has_vmx_ept_4levels()) {
3044                 enable_ept = 0;
3045                 enable_unrestricted_guest = 0;
3046                 enable_ept_ad_bits = 0;
3047         }
3048
3049         if (!cpu_has_vmx_ept_ad_bits())
3050                 enable_ept_ad_bits = 0;
3051
3052         if (!cpu_has_vmx_unrestricted_guest())
3053                 enable_unrestricted_guest = 0;
3054
3055         if (!cpu_has_vmx_flexpriority())
3056                 flexpriority_enabled = 0;
3057
3058         if (!cpu_has_vmx_tpr_shadow())
3059                 kvm_x86_ops->update_cr8_intercept = NULL;
3060
3061         if (enable_ept && !cpu_has_vmx_ept_2m_page())
3062                 kvm_disable_largepages();
3063
3064         if (!cpu_has_vmx_ple())
3065                 ple_gap = 0;
3066
3067         if (!cpu_has_vmx_apicv())
3068                 enable_apicv = 0;
3069
3070         if (enable_apicv)
3071                 kvm_x86_ops->update_cr8_intercept = NULL;
3072         else {
3073                 kvm_x86_ops->hwapic_irr_update = NULL;
3074                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3075                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3076         }
3077
3078         if (nested)
3079                 nested_vmx_setup_ctls_msrs();
3080
3081         return alloc_kvm_area();
3082 }
3083
3084 static __exit void hardware_unsetup(void)
3085 {
3086         free_kvm_area();
3087 }
3088
3089 static bool emulation_required(struct kvm_vcpu *vcpu)
3090 {
3091         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3092 }
3093
3094 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3095                 struct kvm_segment *save)
3096 {
3097         if (!emulate_invalid_guest_state) {
3098                 /*
3099                  * CS and SS RPL should be equal during guest entry according
3100                  * to VMX spec, but in reality it is not always so. Since vcpu
3101                  * is in the middle of the transition from real mode to
3102                  * protected mode it is safe to assume that RPL 0 is a good
3103                  * default value.
3104                  */
3105                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3106                         save->selector &= ~SELECTOR_RPL_MASK;
3107                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3108                 save->s = 1;
3109         }
3110         vmx_set_segment(vcpu, save, seg);
3111 }
3112
3113 static void enter_pmode(struct kvm_vcpu *vcpu)
3114 {
3115         unsigned long flags;
3116         struct vcpu_vmx *vmx = to_vmx(vcpu);
3117
3118         /*
3119          * Update real mode segment cache. It may be not up-to-date if sement
3120          * register was written while vcpu was in a guest mode.
3121          */
3122         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3123         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3124         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3125         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3126         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3127         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3128
3129         vmx->rmode.vm86_active = 0;
3130
3131         vmx_segment_cache_clear(vmx);
3132
3133         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3134
3135         flags = vmcs_readl(GUEST_RFLAGS);
3136         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3137         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3138         vmcs_writel(GUEST_RFLAGS, flags);
3139
3140         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3141                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3142
3143         update_exception_bitmap(vcpu);
3144
3145         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3146         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3147         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3148         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3149         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3150         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3151
3152         /* CPL is always 0 when CPU enters protected mode */
3153         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3154         vmx->cpl = 0;
3155 }
3156
3157 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3158 {
3159         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3160         struct kvm_segment var = *save;
3161
3162         var.dpl = 0x3;
3163         if (seg == VCPU_SREG_CS)
3164                 var.type = 0x3;
3165
3166         if (!emulate_invalid_guest_state) {
3167                 var.selector = var.base >> 4;
3168                 var.base = var.base & 0xffff0;
3169                 var.limit = 0xffff;
3170                 var.g = 0;
3171                 var.db = 0;
3172                 var.present = 1;
3173                 var.s = 1;
3174                 var.l = 0;
3175                 var.unusable = 0;
3176                 var.type = 0x3;
3177                 var.avl = 0;
3178                 if (save->base & 0xf)
3179                         printk_once(KERN_WARNING "kvm: segment base is not "
3180                                         "paragraph aligned when entering "
3181                                         "protected mode (seg=%d)", seg);
3182         }
3183
3184         vmcs_write16(sf->selector, var.selector);
3185         vmcs_write32(sf->base, var.base);
3186         vmcs_write32(sf->limit, var.limit);
3187         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3188 }
3189
3190 static void enter_rmode(struct kvm_vcpu *vcpu)
3191 {
3192         unsigned long flags;
3193         struct vcpu_vmx *vmx = to_vmx(vcpu);
3194
3195         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3196         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3197         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3198         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3199         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3200         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3201         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3202
3203         vmx->rmode.vm86_active = 1;
3204
3205         /*
3206          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3207          * vcpu. Warn the user that an update is overdue.
3208          */
3209         if (!vcpu->kvm->arch.tss_addr)
3210                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3211                              "called before entering vcpu\n");
3212
3213         vmx_segment_cache_clear(vmx);
3214
3215         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3216         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3217         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3218
3219         flags = vmcs_readl(GUEST_RFLAGS);
3220         vmx->rmode.save_rflags = flags;
3221
3222         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3223
3224         vmcs_writel(GUEST_RFLAGS, flags);
3225         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3226         update_exception_bitmap(vcpu);
3227
3228         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3229         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3230         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3231         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3232         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3233         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3234
3235         kvm_mmu_reset_context(vcpu);
3236 }
3237
3238 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3239 {
3240         struct vcpu_vmx *vmx = to_vmx(vcpu);
3241         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3242
3243         if (!msr)
3244                 return;
3245
3246         /*
3247          * Force kernel_gs_base reloading before EFER changes, as control
3248          * of this msr depends on is_long_mode().
3249          */
3250         vmx_load_host_state(to_vmx(vcpu));
3251         vcpu->arch.efer = efer;
3252         if (efer & EFER_LMA) {
3253                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3254                 msr->data = efer;
3255         } else {
3256                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3257
3258                 msr->data = efer & ~EFER_LME;
3259         }
3260         setup_msrs(vmx);
3261 }
3262
3263 #ifdef CONFIG_X86_64
3264
3265 static void enter_lmode(struct kvm_vcpu *vcpu)
3266 {
3267         u32 guest_tr_ar;
3268
3269         vmx_segment_cache_clear(to_vmx(vcpu));
3270
3271         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3272         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3273                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3274                                      __func__);
3275                 vmcs_write32(GUEST_TR_AR_BYTES,
3276                              (guest_tr_ar & ~AR_TYPE_MASK)
3277                              | AR_TYPE_BUSY_64_TSS);
3278         }
3279         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3280 }
3281
3282 static void exit_lmode(struct kvm_vcpu *vcpu)
3283 {
3284         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3285         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3286 }
3287
3288 #endif
3289
3290 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3291 {
3292         vpid_sync_context(to_vmx(vcpu));
3293         if (enable_ept) {
3294                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3295                         return;
3296                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3297         }
3298 }
3299
3300 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3301 {
3302         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3303
3304         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3305         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3306 }
3307
3308 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3309 {
3310         if (enable_ept && is_paging(vcpu))
3311                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3312         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3313 }
3314
3315 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3316 {
3317         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3318
3319         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3320         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3321 }
3322
3323 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3324 {
3325         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3326
3327         if (!test_bit(VCPU_EXREG_PDPTR,
3328                       (unsigned long *)&vcpu->arch.regs_dirty))
3329                 return;
3330
3331         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3332                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3333                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3334                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3335                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3336         }
3337 }
3338
3339 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3340 {
3341         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3342
3343         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3344                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3345                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3346                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3347                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3348         }
3349
3350         __set_bit(VCPU_EXREG_PDPTR,
3351                   (unsigned long *)&vcpu->arch.regs_avail);
3352         __set_bit(VCPU_EXREG_PDPTR,
3353                   (unsigned long *)&vcpu->arch.regs_dirty);
3354 }
3355
3356 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3357
3358 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3359                                         unsigned long cr0,
3360                                         struct kvm_vcpu *vcpu)
3361 {
3362         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3363                 vmx_decache_cr3(vcpu);
3364         if (!(cr0 & X86_CR0_PG)) {
3365                 /* From paging/starting to nonpaging */
3366                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3367                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3368                              (CPU_BASED_CR3_LOAD_EXITING |
3369                               CPU_BASED_CR3_STORE_EXITING));
3370                 vcpu->arch.cr0 = cr0;
3371                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3372         } else if (!is_paging(vcpu)) {
3373                 /* From nonpaging to paging */
3374                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3375                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3376                              ~(CPU_BASED_CR3_LOAD_EXITING |
3377                                CPU_BASED_CR3_STORE_EXITING));
3378                 vcpu->arch.cr0 = cr0;
3379                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3380         }
3381
3382         if (!(cr0 & X86_CR0_WP))
3383                 *hw_cr0 &= ~X86_CR0_WP;
3384 }
3385
3386 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3387 {
3388         struct vcpu_vmx *vmx = to_vmx(vcpu);
3389         unsigned long hw_cr0;
3390
3391         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3392         if (enable_unrestricted_guest)
3393                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3394         else {
3395                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3396
3397                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3398                         enter_pmode(vcpu);
3399
3400                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3401                         enter_rmode(vcpu);
3402         }
3403
3404 #ifdef CONFIG_X86_64
3405         if (vcpu->arch.efer & EFER_LME) {
3406                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3407                         enter_lmode(vcpu);
3408                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3409                         exit_lmode(vcpu);
3410         }
3411 #endif
3412
3413         if (enable_ept)
3414                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3415
3416         if (!vcpu->fpu_active)
3417                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3418
3419         vmcs_writel(CR0_READ_SHADOW, cr0);
3420         vmcs_writel(GUEST_CR0, hw_cr0);
3421         vcpu->arch.cr0 = cr0;
3422
3423         /* depends on vcpu->arch.cr0 to be set to a new value */
3424         vmx->emulation_required = emulation_required(vcpu);
3425 }
3426
3427 static u64 construct_eptp(unsigned long root_hpa)
3428 {
3429         u64 eptp;
3430
3431         /* TODO write the value reading from MSR */
3432         eptp = VMX_EPT_DEFAULT_MT |
3433                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3434         if (enable_ept_ad_bits)
3435                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3436         eptp |= (root_hpa & PAGE_MASK);
3437
3438         return eptp;
3439 }
3440
3441 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3442 {
3443         unsigned long guest_cr3;
3444         u64 eptp;
3445
3446         guest_cr3 = cr3;
3447         if (enable_ept) {
3448                 eptp = construct_eptp(cr3);
3449                 vmcs_write64(EPT_POINTER, eptp);
3450                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3451                         guest_cr3 = kvm_read_cr3(vcpu);
3452                 else
3453                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3454                 ept_load_pdptrs(vcpu);
3455         }
3456
3457         vmx_flush_tlb(vcpu);
3458         vmcs_writel(GUEST_CR3, guest_cr3);
3459 }
3460
3461 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3462 {
3463         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3464                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3465
3466         if (cr4 & X86_CR4_VMXE) {
3467                 /*
3468                  * To use VMXON (and later other VMX instructions), a guest
3469                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3470                  * So basically the check on whether to allow nested VMX
3471                  * is here.
3472                  */
3473                 if (!nested_vmx_allowed(vcpu))
3474                         return 1;
3475         }
3476         if (to_vmx(vcpu)->nested.vmxon &&
3477             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3478                 return 1;
3479
3480         vcpu->arch.cr4 = cr4;
3481         if (enable_ept) {
3482                 if (!is_paging(vcpu)) {
3483                         hw_cr4 &= ~X86_CR4_PAE;
3484                         hw_cr4 |= X86_CR4_PSE;
3485                         /*
3486                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3487                          * in hardware. However KVM always uses paging mode to
3488                          * emulate guest non-paging mode with TDP.
3489                          * To emulate this behavior, SMEP/SMAP needs to be
3490                          * manually disabled when guest switches to non-paging
3491                          * mode.
3492                          */
3493                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3494                 } else if (!(cr4 & X86_CR4_PAE)) {
3495                         hw_cr4 &= ~X86_CR4_PAE;
3496                 }
3497         }
3498
3499         vmcs_writel(CR4_READ_SHADOW, cr4);
3500         vmcs_writel(GUEST_CR4, hw_cr4);
3501         return 0;
3502 }
3503
3504 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3505                             struct kvm_segment *var, int seg)
3506 {
3507         struct vcpu_vmx *vmx = to_vmx(vcpu);
3508         u32 ar;
3509
3510         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3511                 *var = vmx->rmode.segs[seg];
3512                 if (seg == VCPU_SREG_TR
3513                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3514                         return;
3515                 var->base = vmx_read_guest_seg_base(vmx, seg);
3516                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3517                 return;
3518         }
3519         var->base = vmx_read_guest_seg_base(vmx, seg);
3520         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3521         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3522         ar = vmx_read_guest_seg_ar(vmx, seg);
3523         var->unusable = (ar >> 16) & 1;
3524         var->type = ar & 15;
3525         var->s = (ar >> 4) & 1;
3526         var->dpl = (ar >> 5) & 3;
3527         /*
3528          * Some userspaces do not preserve unusable property. Since usable
3529          * segment has to be present according to VMX spec we can use present
3530          * property to amend userspace bug by making unusable segment always
3531          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3532          * segment as unusable.
3533          */
3534         var->present = !var->unusable;
3535         var->avl = (ar >> 12) & 1;
3536         var->l = (ar >> 13) & 1;
3537         var->db = (ar >> 14) & 1;
3538         var->g = (ar >> 15) & 1;
3539 }
3540
3541 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3542 {
3543         struct kvm_segment s;
3544
3545         if (to_vmx(vcpu)->rmode.vm86_active) {
3546                 vmx_get_segment(vcpu, &s, seg);
3547                 return s.base;
3548         }
3549         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3550 }
3551
3552 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3553 {
3554         struct vcpu_vmx *vmx = to_vmx(vcpu);
3555
3556         if (!is_protmode(vcpu))
3557                 return 0;
3558
3559         if (!is_long_mode(vcpu)
3560             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3561                 return 3;
3562
3563         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3564                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3565                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3566         }
3567
3568         return vmx->cpl;
3569 }
3570
3571
3572 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3573 {
3574         u32 ar;
3575
3576         if (var->unusable || !var->present)
3577                 ar = 1 << 16;
3578         else {
3579                 ar = var->type & 15;
3580                 ar |= (var->s & 1) << 4;
3581                 ar |= (var->dpl & 3) << 5;
3582                 ar |= (var->present & 1) << 7;
3583                 ar |= (var->avl & 1) << 12;
3584                 ar |= (var->l & 1) << 13;
3585                 ar |= (var->db & 1) << 14;
3586                 ar |= (var->g & 1) << 15;
3587         }
3588
3589         return ar;
3590 }
3591
3592 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3593                             struct kvm_segment *var, int seg)
3594 {
3595         struct vcpu_vmx *vmx = to_vmx(vcpu);
3596         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3597
3598         vmx_segment_cache_clear(vmx);
3599         if (seg == VCPU_SREG_CS)
3600                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3601
3602         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3603                 vmx->rmode.segs[seg] = *var;
3604                 if (seg == VCPU_SREG_TR)
3605                         vmcs_write16(sf->selector, var->selector);
3606                 else if (var->s)
3607                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3608                 goto out;
3609         }
3610
3611         vmcs_writel(sf->base, var->base);
3612         vmcs_write32(sf->limit, var->limit);
3613         vmcs_write16(sf->selector, var->selector);
3614
3615         /*
3616          *   Fix the "Accessed" bit in AR field of segment registers for older
3617          * qemu binaries.
3618          *   IA32 arch specifies that at the time of processor reset the
3619          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3620          * is setting it to 0 in the userland code. This causes invalid guest
3621          * state vmexit when "unrestricted guest" mode is turned on.
3622          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3623          * tree. Newer qemu binaries with that qemu fix would not need this
3624          * kvm hack.
3625          */
3626         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3627                 var->type |= 0x1; /* Accessed */
3628
3629         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3630
3631 out:
3632         vmx->emulation_required |= emulation_required(vcpu);
3633 }
3634
3635 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3636 {
3637         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3638
3639         *db = (ar >> 14) & 1;
3640         *l = (ar >> 13) & 1;
3641 }
3642
3643 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3644 {
3645         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3646         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3647 }
3648
3649 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3650 {
3651         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3652         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3653 }
3654
3655 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3656 {
3657         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3658         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3659 }
3660
3661 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3662 {
3663         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3664         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3665 }
3666
3667 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3668 {
3669         struct kvm_segment var;
3670         u32 ar;
3671
3672         vmx_get_segment(vcpu, &var, seg);
3673         var.dpl = 0x3;
3674         if (seg == VCPU_SREG_CS)
3675                 var.type = 0x3;
3676         ar = vmx_segment_access_rights(&var);
3677
3678         if (var.base != (var.selector << 4))
3679                 return false;
3680         if (var.limit != 0xffff)
3681                 return false;
3682         if (ar != 0xf3)
3683                 return false;
3684
3685         return true;
3686 }
3687
3688 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3689 {
3690         struct kvm_segment cs;
3691         unsigned int cs_rpl;
3692
3693         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3694         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3695
3696         if (cs.unusable)
3697                 return false;
3698         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3699                 return false;
3700         if (!cs.s)
3701                 return false;
3702         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3703                 if (cs.dpl > cs_rpl)
3704                         return false;
3705         } else {
3706                 if (cs.dpl != cs_rpl)
3707                         return false;
3708         }
3709         if (!cs.present)
3710                 return false;
3711
3712         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3713         return true;
3714 }
3715
3716 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3717 {
3718         struct kvm_segment ss;
3719         unsigned int ss_rpl;
3720
3721         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3722         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3723
3724         if (ss.unusable)
3725                 return true;
3726         if (ss.type != 3 && ss.type != 7)
3727                 return false;
3728         if (!ss.s)
3729                 return false;
3730         if (ss.dpl != ss_rpl) /* DPL != RPL */
3731                 return false;
3732         if (!ss.present)
3733                 return false;
3734
3735         return true;
3736 }
3737
3738 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3739 {
3740         struct kvm_segment var;
3741         unsigned int rpl;
3742
3743         vmx_get_segment(vcpu, &var, seg);
3744         rpl = var.selector & SELECTOR_RPL_MASK;
3745
3746         if (var.unusable)
3747                 return true;
3748         if (!var.s)
3749                 return false;
3750         if (!var.present)
3751                 return false;
3752         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3753                 if (var.dpl < rpl) /* DPL < RPL */
3754                         return false;
3755         }
3756
3757         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3758          * rights flags
3759          */
3760         return true;
3761 }
3762
3763 static bool tr_valid(struct kvm_vcpu *vcpu)
3764 {
3765         struct kvm_segment tr;
3766
3767         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3768
3769         if (tr.unusable)
3770                 return false;
3771         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3772                 return false;
3773         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3774                 return false;
3775         if (!tr.present)
3776                 return false;
3777
3778         return true;
3779 }
3780
3781 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3782 {
3783         struct kvm_segment ldtr;
3784
3785         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3786
3787         if (ldtr.unusable)
3788                 return true;
3789         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3790                 return false;
3791         if (ldtr.type != 2)
3792                 return false;
3793         if (!ldtr.present)
3794                 return false;
3795
3796         return true;
3797 }
3798
3799 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3800 {
3801         struct kvm_segment cs, ss;
3802
3803         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3804         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3805
3806         return ((cs.selector & SELECTOR_RPL_MASK) ==
3807                  (ss.selector & SELECTOR_RPL_MASK));
3808 }
3809
3810 /*
3811  * Check if guest state is valid. Returns true if valid, false if
3812  * not.
3813  * We assume that registers are always usable
3814  */
3815 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3816 {
3817         if (enable_unrestricted_guest)
3818                 return true;
3819
3820         /* real mode guest state checks */
3821         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3822                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3823                         return false;
3824                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3825                         return false;
3826                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3827                         return false;
3828                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3829                         return false;
3830                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3831                         return false;
3832                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3833                         return false;
3834         } else {
3835         /* protected mode guest state checks */
3836                 if (!cs_ss_rpl_check(vcpu))
3837                         return false;
3838                 if (!code_segment_valid(vcpu))
3839                         return false;
3840                 if (!stack_segment_valid(vcpu))
3841                         return false;
3842                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3843                         return false;
3844                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3845                         return false;
3846                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3847                         return false;
3848                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3849                         return false;
3850                 if (!tr_valid(vcpu))
3851                         return false;
3852                 if (!ldtr_valid(vcpu))
3853                         return false;
3854         }
3855         /* TODO:
3856          * - Add checks on RIP
3857          * - Add checks on RFLAGS
3858          */
3859
3860         return true;
3861 }
3862
3863 static int init_rmode_tss(struct kvm *kvm)
3864 {
3865         gfn_t fn;
3866         u16 data = 0;
3867         int r, idx, ret = 0;
3868
3869         idx = srcu_read_lock(&kvm->srcu);
3870         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3871         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3872         if (r < 0)
3873                 goto out;
3874         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3875         r = kvm_write_guest_page(kvm, fn++, &data,
3876                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3877         if (r < 0)
3878                 goto out;
3879         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3880         if (r < 0)
3881                 goto out;
3882         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3883         if (r < 0)
3884                 goto out;
3885         data = ~0;
3886         r = kvm_write_guest_page(kvm, fn, &data,
3887                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3888                                  sizeof(u8));
3889         if (r < 0)
3890                 goto out;
3891
3892         ret = 1;
3893 out:
3894         srcu_read_unlock(&kvm->srcu, idx);
3895         return ret;
3896 }
3897
3898 static int init_rmode_identity_map(struct kvm *kvm)
3899 {
3900         int i, idx, r, ret;
3901         pfn_t identity_map_pfn;
3902         u32 tmp;
3903
3904         if (!enable_ept)
3905                 return 1;
3906         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3907                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3908                         "haven't been allocated!\n");
3909                 return 0;
3910         }
3911         if (likely(kvm->arch.ept_identity_pagetable_done))
3912                 return 1;
3913         ret = 0;
3914         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3915         idx = srcu_read_lock(&kvm->srcu);
3916         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3917         if (r < 0)
3918                 goto out;
3919         /* Set up identity-mapping pagetable for EPT in real mode */
3920         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3921                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3922                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3923                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3924                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3925                 if (r < 0)
3926                         goto out;
3927         }
3928         kvm->arch.ept_identity_pagetable_done = true;
3929         ret = 1;
3930 out:
3931         srcu_read_unlock(&kvm->srcu, idx);
3932         return ret;
3933 }
3934
3935 static void seg_setup(int seg)
3936 {
3937         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3938         unsigned int ar;
3939
3940         vmcs_write16(sf->selector, 0);
3941         vmcs_writel(sf->base, 0);
3942         vmcs_write32(sf->limit, 0xffff);
3943         ar = 0x93;
3944         if (seg == VCPU_SREG_CS)
3945                 ar |= 0x08; /* code segment */
3946
3947         vmcs_write32(sf->ar_bytes, ar);
3948 }
3949
3950 static int alloc_apic_access_page(struct kvm *kvm)
3951 {
3952         struct page *page;
3953         struct kvm_userspace_memory_region kvm_userspace_mem;
3954         int r = 0;
3955
3956         mutex_lock(&kvm->slots_lock);
3957         if (kvm->arch.apic_access_page)
3958                 goto out;
3959         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3960         kvm_userspace_mem.flags = 0;
3961         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3962         kvm_userspace_mem.memory_size = PAGE_SIZE;
3963         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3964         if (r)
3965                 goto out;
3966
3967         page = gfn_to_page(kvm, 0xfee00);
3968         if (is_error_page(page)) {
3969                 r = -EFAULT;
3970                 goto out;
3971         }
3972
3973         kvm->arch.apic_access_page = page;
3974 out:
3975         mutex_unlock(&kvm->slots_lock);
3976         return r;
3977 }
3978
3979 static int alloc_identity_pagetable(struct kvm *kvm)
3980 {
3981         struct page *page;
3982         struct kvm_userspace_memory_region kvm_userspace_mem;
3983         int r = 0;
3984
3985         mutex_lock(&kvm->slots_lock);
3986         if (kvm->arch.ept_identity_pagetable)
3987                 goto out;
3988         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3989         kvm_userspace_mem.flags = 0;
3990         kvm_userspace_mem.guest_phys_addr =
3991                 kvm->arch.ept_identity_map_addr;
3992         kvm_userspace_mem.memory_size = PAGE_SIZE;
3993         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3994         if (r)
3995                 goto out;
3996
3997         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3998         if (is_error_page(page)) {
3999                 r = -EFAULT;
4000                 goto out;
4001         }
4002
4003         kvm->arch.ept_identity_pagetable = page;
4004 out:
4005         mutex_unlock(&kvm->slots_lock);
4006         return r;
4007 }
4008
4009 static void allocate_vpid(struct vcpu_vmx *vmx)
4010 {
4011         int vpid;
4012
4013         vmx->vpid = 0;
4014         if (!enable_vpid)
4015                 return;
4016         spin_lock(&vmx_vpid_lock);
4017         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4018         if (vpid < VMX_NR_VPIDS) {
4019                 vmx->vpid = vpid;
4020                 __set_bit(vpid, vmx_vpid_bitmap);
4021         }
4022         spin_unlock(&vmx_vpid_lock);
4023 }
4024
4025 static void free_vpid(struct vcpu_vmx *vmx)
4026 {
4027         if (!enable_vpid)
4028                 return;
4029         spin_lock(&vmx_vpid_lock);
4030         if (vmx->vpid != 0)
4031                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4032         spin_unlock(&vmx_vpid_lock);
4033 }
4034
4035 #define MSR_TYPE_R      1
4036 #define MSR_TYPE_W      2
4037 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4038                                                 u32 msr, int type)
4039 {
4040         int f = sizeof(unsigned long);
4041
4042         if (!cpu_has_vmx_msr_bitmap())
4043                 return;
4044
4045         /*
4046          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4047          * have the write-low and read-high bitmap offsets the wrong way round.
4048          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4049          */
4050         if (msr <= 0x1fff) {
4051                 if (type & MSR_TYPE_R)
4052                         /* read-low */
4053                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4054
4055                 if (type & MSR_TYPE_W)
4056                         /* write-low */
4057                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4058
4059         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4060                 msr &= 0x1fff;
4061                 if (type & MSR_TYPE_R)
4062                         /* read-high */
4063                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4064
4065                 if (type & MSR_TYPE_W)
4066                         /* write-high */
4067                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4068
4069         }
4070 }
4071
4072 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4073                                                 u32 msr, int type)
4074 {
4075         int f = sizeof(unsigned long);
4076
4077         if (!cpu_has_vmx_msr_bitmap())
4078                 return;
4079
4080         /*
4081          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4082          * have the write-low and read-high bitmap offsets the wrong way round.
4083          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4084          */
4085         if (msr <= 0x1fff) {
4086                 if (type & MSR_TYPE_R)
4087                         /* read-low */
4088                         __set_bit(msr, msr_bitmap + 0x000 / f);
4089
4090                 if (type & MSR_TYPE_W)
4091                         /* write-low */
4092                         __set_bit(msr, msr_bitmap + 0x800 / f);
4093
4094         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4095                 msr &= 0x1fff;
4096                 if (type & MSR_TYPE_R)
4097                         /* read-high */
4098                         __set_bit(msr, msr_bitmap + 0x400 / f);
4099
4100                 if (type & MSR_TYPE_W)
4101                         /* write-high */
4102                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4103
4104         }
4105 }
4106
4107 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4108 {
4109         if (!longmode_only)
4110                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4111                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4112         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4113                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4114 }
4115
4116 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4117 {
4118         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4119                         msr, MSR_TYPE_R);
4120         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4121                         msr, MSR_TYPE_R);
4122 }
4123
4124 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4125 {
4126         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4127                         msr, MSR_TYPE_R);
4128         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4129                         msr, MSR_TYPE_R);
4130 }
4131
4132 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4133 {
4134         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4135                         msr, MSR_TYPE_W);
4136         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4137                         msr, MSR_TYPE_W);
4138 }
4139
4140 static int vmx_vm_has_apicv(struct kvm *kvm)
4141 {
4142         return enable_apicv && irqchip_in_kernel(kvm);
4143 }
4144
4145 /*
4146  * Send interrupt to vcpu via posted interrupt way.
4147  * 1. If target vcpu is running(non-root mode), send posted interrupt
4148  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4149  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4150  * interrupt from PIR in next vmentry.
4151  */
4152 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4153 {
4154         struct vcpu_vmx *vmx = to_vmx(vcpu);
4155         int r;
4156
4157         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4158                 return;
4159
4160         r = pi_test_and_set_on(&vmx->pi_desc);
4161         kvm_make_request(KVM_REQ_EVENT, vcpu);
4162 #ifdef CONFIG_SMP
4163         if (!r && (vcpu->mode == IN_GUEST_MODE))
4164                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4165                                 POSTED_INTR_VECTOR);
4166         else
4167 #endif
4168                 kvm_vcpu_kick(vcpu);
4169 }
4170
4171 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4172 {
4173         struct vcpu_vmx *vmx = to_vmx(vcpu);
4174
4175         if (!pi_test_and_clear_on(&vmx->pi_desc))
4176                 return;
4177
4178         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4179 }
4180
4181 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4182 {
4183         return;
4184 }
4185
4186 /*
4187  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4188  * will not change in the lifetime of the guest.
4189  * Note that host-state that does change is set elsewhere. E.g., host-state
4190  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4191  */
4192 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4193 {
4194         u32 low32, high32;
4195         unsigned long tmpl;
4196         struct desc_ptr dt;
4197
4198         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4199         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4200         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4201
4202         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4203 #ifdef CONFIG_X86_64
4204         /*
4205          * Load null selectors, so we can avoid reloading them in
4206          * __vmx_load_host_state(), in case userspace uses the null selectors
4207          * too (the expected case).
4208          */
4209         vmcs_write16(HOST_DS_SELECTOR, 0);
4210         vmcs_write16(HOST_ES_SELECTOR, 0);
4211 #else
4212         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4213         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4214 #endif
4215         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4216         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4217
4218         native_store_idt(&dt);
4219         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4220         vmx->host_idt_base = dt.address;
4221
4222         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4223
4224         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4225         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4226         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4227         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4228
4229         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4230                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4231                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4232         }
4233 }
4234
4235 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4236 {
4237         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4238         if (enable_ept)
4239                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4240         if (is_guest_mode(&vmx->vcpu))
4241                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4242                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4243         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4244 }
4245
4246 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4247 {
4248         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4249
4250         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4251                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4252         return pin_based_exec_ctrl;
4253 }
4254
4255 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4256 {
4257         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4258
4259         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4260                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4261
4262         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4263                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4264 #ifdef CONFIG_X86_64
4265                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4266                                 CPU_BASED_CR8_LOAD_EXITING;
4267 #endif
4268         }
4269         if (!enable_ept)
4270                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4271                                 CPU_BASED_CR3_LOAD_EXITING  |
4272                                 CPU_BASED_INVLPG_EXITING;
4273         return exec_control;
4274 }
4275
4276 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4277 {
4278         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4279         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4280                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4281         if (vmx->vpid == 0)
4282                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4283         if (!enable_ept) {
4284                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4285                 enable_unrestricted_guest = 0;
4286                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4287                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4288         }
4289         if (!enable_unrestricted_guest)
4290                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4291         if (!ple_gap)
4292                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4293         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4294                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4295                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4296         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4297         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4298            (handle_vmptrld).
4299            We can NOT enable shadow_vmcs here because we don't have yet
4300            a current VMCS12
4301         */
4302         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4303         return exec_control;
4304 }
4305
4306 static void ept_set_mmio_spte_mask(void)
4307 {
4308         /*
4309          * EPT Misconfigurations can be generated if the value of bits 2:0
4310          * of an EPT paging-structure entry is 110b (write/execute).
4311          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4312          * spte.
4313          */
4314         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4315 }
4316
4317 /*
4318  * Sets up the vmcs for emulated real mode.
4319  */
4320 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4321 {
4322 #ifdef CONFIG_X86_64
4323         unsigned long a;
4324 #endif
4325         int i;
4326
4327         /* I/O */
4328         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4329         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4330
4331         if (enable_shadow_vmcs) {
4332                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4333                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4334         }
4335         if (cpu_has_vmx_msr_bitmap())
4336                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4337
4338         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4339
4340         /* Control */
4341         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4342
4343         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4344
4345         if (cpu_has_secondary_exec_ctrls()) {
4346                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4347                                 vmx_secondary_exec_control(vmx));
4348         }
4349
4350         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4351                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4352                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4353                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4354                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4355
4356                 vmcs_write16(GUEST_INTR_STATUS, 0);
4357
4358                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4359                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4360         }
4361
4362         if (ple_gap) {
4363                 vmcs_write32(PLE_GAP, ple_gap);
4364                 vmcs_write32(PLE_WINDOW, ple_window);
4365         }
4366
4367         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4368         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4369         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4370
4371         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4372         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4373         vmx_set_constant_host_state(vmx);
4374 #ifdef CONFIG_X86_64
4375         rdmsrl(MSR_FS_BASE, a);
4376         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4377         rdmsrl(MSR_GS_BASE, a);
4378         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4379 #else
4380         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4381         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4382 #endif
4383
4384         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4385         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4386         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4387         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4388         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4389
4390         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4391                 u32 msr_low, msr_high;
4392                 u64 host_pat;
4393                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4394                 host_pat = msr_low | ((u64) msr_high << 32);
4395                 /* Write the default value follow host pat */
4396                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4397                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4398                 vmx->vcpu.arch.pat = host_pat;
4399         }
4400
4401         for (i = 0; i < NR_VMX_MSR; ++i) {
4402                 u32 index = vmx_msr_index[i];
4403                 u32 data_low, data_high;
4404                 int j = vmx->nmsrs;
4405
4406                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4407                         continue;
4408                 if (wrmsr_safe(index, data_low, data_high) < 0)
4409                         continue;
4410                 vmx->guest_msrs[j].index = i;
4411                 vmx->guest_msrs[j].data = 0;
4412                 vmx->guest_msrs[j].mask = -1ull;
4413                 ++vmx->nmsrs;
4414         }
4415
4416
4417         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4418
4419         /* 22.2.1, 20.8.1 */
4420         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4421
4422         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4423         set_cr4_guest_host_mask(vmx);
4424
4425         return 0;
4426 }
4427
4428 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4429 {
4430         struct vcpu_vmx *vmx = to_vmx(vcpu);
4431         struct msr_data apic_base_msr;
4432
4433         vmx->rmode.vm86_active = 0;
4434
4435         vmx->soft_vnmi_blocked = 0;
4436
4437         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4438         kvm_set_cr8(&vmx->vcpu, 0);
4439         apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4440         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4441                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4442         apic_base_msr.host_initiated = true;
4443         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4444
4445         vmx_segment_cache_clear(vmx);
4446
4447         seg_setup(VCPU_SREG_CS);
4448         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4449         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4450
4451         seg_setup(VCPU_SREG_DS);
4452         seg_setup(VCPU_SREG_ES);
4453         seg_setup(VCPU_SREG_FS);
4454         seg_setup(VCPU_SREG_GS);
4455         seg_setup(VCPU_SREG_SS);
4456
4457         vmcs_write16(GUEST_TR_SELECTOR, 0);
4458         vmcs_writel(GUEST_TR_BASE, 0);
4459         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4460         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4461
4462         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4463         vmcs_writel(GUEST_LDTR_BASE, 0);
4464         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4465         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4466
4467         vmcs_write32(GUEST_SYSENTER_CS, 0);
4468         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4469         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4470
4471         vmcs_writel(GUEST_RFLAGS, 0x02);
4472         kvm_rip_write(vcpu, 0xfff0);
4473
4474         vmcs_writel(GUEST_GDTR_BASE, 0);
4475         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4476
4477         vmcs_writel(GUEST_IDTR_BASE, 0);
4478         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4479
4480         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4481         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4482         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4483
4484         /* Special registers */
4485         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4486
4487         setup_msrs(vmx);
4488
4489         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4490
4491         if (cpu_has_vmx_tpr_shadow()) {
4492                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4493                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4494                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4495                                      __pa(vmx->vcpu.arch.apic->regs));
4496                 vmcs_write32(TPR_THRESHOLD, 0);
4497         }
4498
4499         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4500                 vmcs_write64(APIC_ACCESS_ADDR,
4501                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4502
4503         if (vmx_vm_has_apicv(vcpu->kvm))
4504                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4505
4506         if (vmx->vpid != 0)
4507                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4508
4509         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4510         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4511         vmx_set_cr4(&vmx->vcpu, 0);
4512         vmx_set_efer(&vmx->vcpu, 0);
4513         vmx_fpu_activate(&vmx->vcpu);
4514         update_exception_bitmap(&vmx->vcpu);
4515
4516         vpid_sync_context(vmx);
4517 }
4518
4519 /*
4520  * In nested virtualization, check if L1 asked to exit on external interrupts.
4521  * For most existing hypervisors, this will always return true.
4522  */
4523 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4524 {
4525         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4526                 PIN_BASED_EXT_INTR_MASK;
4527 }
4528
4529 /*
4530  * In nested virtualization, check if L1 has set
4531  * VM_EXIT_ACK_INTR_ON_EXIT
4532  */
4533 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4534 {
4535         return get_vmcs12(vcpu)->vm_exit_controls &
4536                 VM_EXIT_ACK_INTR_ON_EXIT;
4537 }
4538
4539 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4540 {
4541         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4542                 PIN_BASED_NMI_EXITING;
4543 }
4544
4545 static void enable_irq_window(struct kvm_vcpu *vcpu)
4546 {
4547         u32 cpu_based_vm_exec_control;
4548
4549         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4550         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4551         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4552 }
4553
4554 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4555 {
4556         u32 cpu_based_vm_exec_control;
4557
4558         if (!cpu_has_virtual_nmis() ||
4559             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4560                 enable_irq_window(vcpu);
4561                 return;
4562         }
4563
4564         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4565         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4566         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4567 }
4568
4569 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4570 {
4571         struct vcpu_vmx *vmx = to_vmx(vcpu);
4572         uint32_t intr;
4573         int irq = vcpu->arch.interrupt.nr;
4574
4575         trace_kvm_inj_virq(irq);
4576
4577         ++vcpu->stat.irq_injections;
4578         if (vmx->rmode.vm86_active) {
4579                 int inc_eip = 0;
4580                 if (vcpu->arch.interrupt.soft)
4581                         inc_eip = vcpu->arch.event_exit_inst_len;
4582                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4583                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4584                 return;
4585         }
4586         intr = irq | INTR_INFO_VALID_MASK;
4587         if (vcpu->arch.interrupt.soft) {
4588                 intr |= INTR_TYPE_SOFT_INTR;
4589                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4590                              vmx->vcpu.arch.event_exit_inst_len);
4591         } else
4592                 intr |= INTR_TYPE_EXT_INTR;
4593         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4594 }
4595
4596 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4597 {
4598         struct vcpu_vmx *vmx = to_vmx(vcpu);
4599
4600         if (is_guest_mode(vcpu))
4601                 return;
4602
4603         if (!cpu_has_virtual_nmis()) {
4604                 /*
4605                  * Tracking the NMI-blocked state in software is built upon
4606                  * finding the next open IRQ window. This, in turn, depends on
4607                  * well-behaving guests: They have to keep IRQs disabled at
4608                  * least as long as the NMI handler runs. Otherwise we may
4609                  * cause NMI nesting, maybe breaking the guest. But as this is
4610                  * highly unlikely, we can live with the residual risk.
4611                  */
4612                 vmx->soft_vnmi_blocked = 1;
4613                 vmx->vnmi_blocked_time = 0;
4614         }
4615
4616         ++vcpu->stat.nmi_injections;
4617         vmx->nmi_known_unmasked = false;
4618         if (vmx->rmode.vm86_active) {
4619                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4620                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4621                 return;
4622         }
4623         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4624                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4625 }
4626
4627 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4628 {
4629         if (!cpu_has_virtual_nmis())
4630                 return to_vmx(vcpu)->soft_vnmi_blocked;
4631         if (to_vmx(vcpu)->nmi_known_unmasked)
4632                 return false;
4633         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4634 }
4635
4636 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4637 {
4638         struct vcpu_vmx *vmx = to_vmx(vcpu);
4639
4640         if (!cpu_has_virtual_nmis()) {
4641                 if (vmx->soft_vnmi_blocked != masked) {
4642                         vmx->soft_vnmi_blocked = masked;
4643                         vmx->vnmi_blocked_time = 0;
4644                 }
4645         } else {
4646                 vmx->nmi_known_unmasked = !masked;
4647                 if (masked)
4648                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4649                                       GUEST_INTR_STATE_NMI);
4650                 else
4651                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4652                                         GUEST_INTR_STATE_NMI);
4653         }
4654 }
4655
4656 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4657 {
4658         if (to_vmx(vcpu)->nested.nested_run_pending)
4659                 return 0;
4660
4661         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4662                 return 0;
4663
4664         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4665                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4666                    | GUEST_INTR_STATE_NMI));
4667 }
4668
4669 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4670 {
4671         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4672                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4673                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4674                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4675 }
4676
4677 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4678 {
4679         int ret;
4680         struct kvm_userspace_memory_region tss_mem = {
4681                 .slot = TSS_PRIVATE_MEMSLOT,
4682                 .guest_phys_addr = addr,
4683                 .memory_size = PAGE_SIZE * 3,
4684                 .flags = 0,
4685         };
4686
4687         ret = kvm_set_memory_region(kvm, &tss_mem);
4688         if (ret)
4689                 return ret;
4690         kvm->arch.tss_addr = addr;
4691         if (!init_rmode_tss(kvm))
4692                 return  -ENOMEM;
4693
4694         return 0;
4695 }
4696
4697 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4698 {
4699         switch (vec) {
4700         case BP_VECTOR:
4701                 /*
4702                  * Update instruction length as we may reinject the exception
4703                  * from user space while in guest debugging mode.
4704                  */
4705                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4706                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4707                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4708                         return false;
4709                 /* fall through */
4710         case DB_VECTOR:
4711                 if (vcpu->guest_debug &
4712                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4713                         return false;
4714                 /* fall through */
4715         case DE_VECTOR:
4716         case OF_VECTOR:
4717         case BR_VECTOR:
4718         case UD_VECTOR:
4719         case DF_VECTOR:
4720         case SS_VECTOR:
4721         case GP_VECTOR:
4722         case MF_VECTOR:
4723                 return true;
4724         break;
4725         }
4726         return false;
4727 }
4728
4729 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4730                                   int vec, u32 err_code)
4731 {
4732         /*
4733          * Instruction with address size override prefix opcode 0x67
4734          * Cause the #SS fault with 0 error code in VM86 mode.
4735          */
4736         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4737                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4738                         if (vcpu->arch.halt_request) {
4739                                 vcpu->arch.halt_request = 0;
4740                                 return kvm_emulate_halt(vcpu);
4741                         }
4742                         return 1;
4743                 }
4744                 return 0;
4745         }
4746
4747         /*
4748          * Forward all other exceptions that are valid in real mode.
4749          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4750          *        the required debugging infrastructure rework.
4751          */
4752         kvm_queue_exception(vcpu, vec);
4753         return 1;
4754 }
4755
4756 /*
4757  * Trigger machine check on the host. We assume all the MSRs are already set up
4758  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4759  * We pass a fake environment to the machine check handler because we want
4760  * the guest to be always treated like user space, no matter what context
4761  * it used internally.
4762  */
4763 static void kvm_machine_check(void)
4764 {
4765 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4766         struct pt_regs regs = {
4767                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4768                 .flags = X86_EFLAGS_IF,
4769         };
4770
4771         do_machine_check(&regs, 0);
4772 #endif
4773 }
4774
4775 static int handle_machine_check(struct kvm_vcpu *vcpu)
4776 {
4777         /* already handled by vcpu_run */
4778         return 1;
4779 }
4780
4781 static int handle_exception(struct kvm_vcpu *vcpu)
4782 {
4783         struct vcpu_vmx *vmx = to_vmx(vcpu);
4784         struct kvm_run *kvm_run = vcpu->run;
4785         u32 intr_info, ex_no, error_code;
4786         unsigned long cr2, rip, dr6;
4787         u32 vect_info;
4788         enum emulation_result er;
4789
4790         vect_info = vmx->idt_vectoring_info;
4791         intr_info = vmx->exit_intr_info;
4792
4793         if (is_machine_check(intr_info))
4794                 return handle_machine_check(vcpu);
4795
4796         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4797                 return 1;  /* already handled by vmx_vcpu_run() */
4798
4799         if (is_no_device(intr_info)) {
4800                 vmx_fpu_activate(vcpu);
4801                 return 1;
4802         }
4803
4804         if (is_invalid_opcode(intr_info)) {
4805                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4806                 if (er != EMULATE_DONE)
4807                         kvm_queue_exception(vcpu, UD_VECTOR);
4808                 return 1;
4809         }
4810
4811         error_code = 0;
4812         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4813                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4814
4815         /*
4816          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4817          * MMIO, it is better to report an internal error.
4818          * See the comments in vmx_handle_exit.
4819          */
4820         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4821             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4822                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4823                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4824                 vcpu->run->internal.ndata = 2;
4825                 vcpu->run->internal.data[0] = vect_info;
4826                 vcpu->run->internal.data[1] = intr_info;
4827                 return 0;
4828         }
4829
4830         if (is_page_fault(intr_info)) {
4831                 /* EPT won't cause page fault directly */
4832                 BUG_ON(enable_ept);
4833                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4834                 trace_kvm_page_fault(cr2, error_code);
4835
4836                 if (kvm_event_needs_reinjection(vcpu))
4837                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4838                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4839         }
4840
4841         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4842
4843         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4844                 return handle_rmode_exception(vcpu, ex_no, error_code);
4845
4846         switch (ex_no) {
4847         case DB_VECTOR:
4848                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4849                 if (!(vcpu->guest_debug &
4850                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4851                         vcpu->arch.dr6 &= ~15;
4852                         vcpu->arch.dr6 |= dr6;
4853                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4854                                 skip_emulated_instruction(vcpu);
4855
4856                         kvm_queue_exception(vcpu, DB_VECTOR);
4857                         return 1;
4858                 }
4859                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4860                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4861                 /* fall through */
4862         case BP_VECTOR:
4863                 /*
4864                  * Update instruction length as we may reinject #BP from
4865                  * user space while in guest debugging mode. Reading it for
4866                  * #DB as well causes no harm, it is not used in that case.
4867                  */
4868                 vmx->vcpu.arch.event_exit_inst_len =
4869                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4870                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4871                 rip = kvm_rip_read(vcpu);
4872                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4873                 kvm_run->debug.arch.exception = ex_no;
4874                 break;
4875         default:
4876                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4877                 kvm_run->ex.exception = ex_no;
4878                 kvm_run->ex.error_code = error_code;
4879                 break;
4880         }
4881         return 0;
4882 }
4883
4884 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4885 {
4886         ++vcpu->stat.irq_exits;
4887         return 1;
4888 }
4889
4890 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4891 {
4892         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4893         return 0;
4894 }
4895
4896 static int handle_io(struct kvm_vcpu *vcpu)
4897 {
4898         unsigned long exit_qualification;
4899         int size, in, string;
4900         unsigned port;
4901
4902         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4903         string = (exit_qualification & 16) != 0;
4904         in = (exit_qualification & 8) != 0;
4905
4906         ++vcpu->stat.io_exits;
4907
4908         if (string || in)
4909                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4910
4911         port = exit_qualification >> 16;
4912         size = (exit_qualification & 7) + 1;
4913         skip_emulated_instruction(vcpu);
4914
4915         return kvm_fast_pio_out(vcpu, size, port);
4916 }
4917
4918 static void
4919 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4920 {
4921         /*
4922          * Patch in the VMCALL instruction:
4923          */
4924         hypercall[0] = 0x0f;
4925         hypercall[1] = 0x01;
4926         hypercall[2] = 0xc1;
4927 }
4928
4929 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4930 {
4931         unsigned long always_on = VMXON_CR0_ALWAYSON;
4932
4933         if (nested_vmx_secondary_ctls_high &
4934                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4935             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4936                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4937         return (val & always_on) == always_on;
4938 }
4939
4940 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4941 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4942 {
4943         if (is_guest_mode(vcpu)) {
4944                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4945                 unsigned long orig_val = val;
4946
4947                 /*
4948                  * We get here when L2 changed cr0 in a way that did not change
4949                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4950                  * but did change L0 shadowed bits. So we first calculate the
4951                  * effective cr0 value that L1 would like to write into the
4952                  * hardware. It consists of the L2-owned bits from the new
4953                  * value combined with the L1-owned bits from L1's guest_cr0.
4954                  */
4955                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4956                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4957
4958                 if (!nested_cr0_valid(vmcs12, val))
4959                         return 1;
4960
4961                 if (kvm_set_cr0(vcpu, val))
4962                         return 1;
4963                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4964                 return 0;
4965         } else {
4966                 if (to_vmx(vcpu)->nested.vmxon &&
4967                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4968                         return 1;
4969                 return kvm_set_cr0(vcpu, val);
4970         }
4971 }
4972
4973 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4974 {
4975         if (is_guest_mode(vcpu)) {
4976                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4977                 unsigned long orig_val = val;
4978
4979                 /* analogously to handle_set_cr0 */
4980                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4981                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4982                 if (kvm_set_cr4(vcpu, val))
4983                         return 1;
4984                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4985                 return 0;
4986         } else
4987                 return kvm_set_cr4(vcpu, val);
4988 }
4989
4990 /* called to set cr0 as approriate for clts instruction exit. */
4991 static void handle_clts(struct kvm_vcpu *vcpu)
4992 {
4993         if (is_guest_mode(vcpu)) {
4994                 /*
4995                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4996                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4997                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4998                  */
4999                 vmcs_writel(CR0_READ_SHADOW,
5000                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5001                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5002         } else
5003                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5004 }
5005
5006 static int handle_cr(struct kvm_vcpu *vcpu)
5007 {
5008         unsigned long exit_qualification, val;
5009         int cr;
5010         int reg;
5011         int err;
5012
5013         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5014         cr = exit_qualification & 15;
5015         reg = (exit_qualification >> 8) & 15;
5016         switch ((exit_qualification >> 4) & 3) {
5017         case 0: /* mov to cr */
5018                 val = kvm_register_read(vcpu, reg);
5019                 trace_kvm_cr_write(cr, val);
5020                 switch (cr) {
5021                 case 0:
5022                         err = handle_set_cr0(vcpu, val);
5023                         kvm_complete_insn_gp(vcpu, err);
5024                         return 1;
5025                 case 3:
5026                         err = kvm_set_cr3(vcpu, val);
5027                         kvm_complete_insn_gp(vcpu, err);
5028                         return 1;
5029                 case 4:
5030                         err = handle_set_cr4(vcpu, val);
5031                         kvm_complete_insn_gp(vcpu, err);
5032                         return 1;
5033                 case 8: {
5034                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5035                                 u8 cr8 = kvm_register_read(vcpu, reg);
5036                                 err = kvm_set_cr8(vcpu, cr8);
5037                                 kvm_complete_insn_gp(vcpu, err);
5038                                 if (irqchip_in_kernel(vcpu->kvm))
5039                                         return 1;
5040                                 if (cr8_prev <= cr8)
5041                                         return 1;
5042                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5043                                 return 0;
5044                         }
5045                 }
5046                 break;
5047         case 2: /* clts */
5048                 handle_clts(vcpu);
5049                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5050                 skip_emulated_instruction(vcpu);
5051                 vmx_fpu_activate(vcpu);
5052                 return 1;
5053         case 1: /*mov from cr*/
5054                 switch (cr) {
5055                 case 3:
5056                         val = kvm_read_cr3(vcpu);
5057                         kvm_register_write(vcpu, reg, val);
5058                         trace_kvm_cr_read(cr, val);
5059                         skip_emulated_instruction(vcpu);
5060                         return 1;
5061                 case 8:
5062                         val = kvm_get_cr8(vcpu);
5063                         kvm_register_write(vcpu, reg, val);
5064                         trace_kvm_cr_read(cr, val);
5065                         skip_emulated_instruction(vcpu);
5066                         return 1;
5067                 }
5068                 break;
5069         case 3: /* lmsw */
5070                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5071                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5072                 kvm_lmsw(vcpu, val);
5073
5074                 skip_emulated_instruction(vcpu);
5075                 return 1;
5076         default:
5077                 break;
5078         }
5079         vcpu->run->exit_reason = 0;
5080         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5081                (int)(exit_qualification >> 4) & 3, cr);
5082         return 0;
5083 }
5084
5085 static int handle_dr(struct kvm_vcpu *vcpu)
5086 {
5087         unsigned long exit_qualification;
5088         int dr, reg;
5089
5090         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5091         if (!kvm_require_cpl(vcpu, 0))
5092                 return 1;
5093         dr = vmcs_readl(GUEST_DR7);
5094         if (dr & DR7_GD) {
5095                 /*
5096                  * As the vm-exit takes precedence over the debug trap, we
5097                  * need to emulate the latter, either for the host or the
5098                  * guest debugging itself.
5099                  */
5100                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5101                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5102                         vcpu->run->debug.arch.dr7 = dr;
5103                         vcpu->run->debug.arch.pc =
5104                                 vmcs_readl(GUEST_CS_BASE) +
5105                                 vmcs_readl(GUEST_RIP);
5106                         vcpu->run->debug.arch.exception = DB_VECTOR;
5107                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5108                         return 0;
5109                 } else {
5110                         vcpu->arch.dr7 &= ~DR7_GD;
5111                         vcpu->arch.dr6 |= DR6_BD;
5112                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5113                         kvm_queue_exception(vcpu, DB_VECTOR);
5114                         return 1;
5115                 }
5116         }
5117
5118         if (vcpu->guest_debug == 0) {
5119                 u32 cpu_based_vm_exec_control;
5120
5121                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5122                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5123                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5124
5125                 /*
5126                  * No more DR vmexits; force a reload of the debug registers
5127                  * and reenter on this instruction.  The next vmexit will
5128                  * retrieve the full state of the debug registers.
5129                  */
5130                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5131                 return 1;
5132         }
5133
5134         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5135         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5136         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5137         if (exit_qualification & TYPE_MOV_FROM_DR) {
5138                 unsigned long val;
5139
5140                 if (kvm_get_dr(vcpu, dr, &val))
5141                         return 1;
5142                 kvm_register_write(vcpu, reg, val);
5143         } else
5144                 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5145                         return 1;
5146
5147         skip_emulated_instruction(vcpu);
5148         return 1;
5149 }
5150
5151 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5152 {
5153         return vcpu->arch.dr6;
5154 }
5155
5156 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5157 {
5158 }
5159
5160 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5161 {
5162         u32 cpu_based_vm_exec_control;
5163
5164         get_debugreg(vcpu->arch.db[0], 0);
5165         get_debugreg(vcpu->arch.db[1], 1);
5166         get_debugreg(vcpu->arch.db[2], 2);
5167         get_debugreg(vcpu->arch.db[3], 3);
5168         get_debugreg(vcpu->arch.dr6, 6);
5169         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5170
5171         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5172
5173         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5174         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5175         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5176 }
5177
5178 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5179 {
5180         vmcs_writel(GUEST_DR7, val);
5181 }
5182
5183 static int handle_cpuid(struct kvm_vcpu *vcpu)
5184 {
5185         kvm_emulate_cpuid(vcpu);
5186         return 1;
5187 }
5188
5189 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5190 {
5191         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5192         u64 data;
5193
5194         if (vmx_get_msr(vcpu, ecx, &data)) {
5195                 trace_kvm_msr_read_ex(ecx);
5196                 kvm_inject_gp(vcpu, 0);
5197                 return 1;
5198         }
5199
5200         trace_kvm_msr_read(ecx, data);
5201
5202         /* FIXME: handling of bits 32:63 of rax, rdx */
5203         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5204         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5205         skip_emulated_instruction(vcpu);
5206         return 1;
5207 }
5208
5209 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5210 {
5211         struct msr_data msr;
5212         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5213         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5214                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5215
5216         msr.data = data;
5217         msr.index = ecx;
5218         msr.host_initiated = false;
5219         if (vmx_set_msr(vcpu, &msr) != 0) {
5220                 trace_kvm_msr_write_ex(ecx, data);
5221                 kvm_inject_gp(vcpu, 0);
5222                 return 1;
5223         }
5224
5225         trace_kvm_msr_write(ecx, data);
5226         skip_emulated_instruction(vcpu);
5227         return 1;
5228 }
5229
5230 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5231 {
5232         kvm_make_request(KVM_REQ_EVENT, vcpu);
5233         return 1;
5234 }
5235
5236 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5237 {
5238         u32 cpu_based_vm_exec_control;
5239
5240         /* clear pending irq */
5241         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5242         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5243         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5244
5245         kvm_make_request(KVM_REQ_EVENT, vcpu);
5246
5247         ++vcpu->stat.irq_window_exits;
5248
5249         /*
5250          * If the user space waits to inject interrupts, exit as soon as
5251          * possible
5252          */
5253         if (!irqchip_in_kernel(vcpu->kvm) &&
5254             vcpu->run->request_interrupt_window &&
5255             !kvm_cpu_has_interrupt(vcpu)) {
5256                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5257                 return 0;
5258         }
5259         return 1;
5260 }
5261
5262 static int handle_halt(struct kvm_vcpu *vcpu)
5263 {
5264         skip_emulated_instruction(vcpu);
5265         return kvm_emulate_halt(vcpu);
5266 }
5267
5268 static int handle_vmcall(struct kvm_vcpu *vcpu)
5269 {
5270         skip_emulated_instruction(vcpu);
5271         kvm_emulate_hypercall(vcpu);
5272         return 1;
5273 }
5274
5275 static int handle_invd(struct kvm_vcpu *vcpu)
5276 {
5277         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5278 }
5279
5280 static int handle_invlpg(struct kvm_vcpu *vcpu)
5281 {
5282         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5283
5284         kvm_mmu_invlpg(vcpu, exit_qualification);
5285         skip_emulated_instruction(vcpu);
5286         return 1;
5287 }
5288
5289 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5290 {
5291         int err;
5292
5293         err = kvm_rdpmc(vcpu);
5294         kvm_complete_insn_gp(vcpu, err);
5295
5296         return 1;
5297 }
5298
5299 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5300 {
5301         skip_emulated_instruction(vcpu);
5302         kvm_emulate_wbinvd(vcpu);
5303         return 1;
5304 }
5305
5306 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5307 {
5308         u64 new_bv = kvm_read_edx_eax(vcpu);
5309         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5310
5311         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5312                 skip_emulated_instruction(vcpu);
5313         return 1;
5314 }
5315
5316 static int handle_apic_access(struct kvm_vcpu *vcpu)
5317 {
5318         if (likely(fasteoi)) {
5319                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5320                 int access_type, offset;
5321
5322                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5323                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5324                 /*
5325                  * Sane guest uses MOV to write EOI, with written value
5326                  * not cared. So make a short-circuit here by avoiding
5327                  * heavy instruction emulation.
5328                  */
5329                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5330                     (offset == APIC_EOI)) {
5331                         kvm_lapic_set_eoi(vcpu);
5332                         skip_emulated_instruction(vcpu);
5333                         return 1;
5334                 }
5335         }
5336         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5337 }
5338
5339 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5340 {
5341         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5342         int vector = exit_qualification & 0xff;
5343
5344         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5345         kvm_apic_set_eoi_accelerated(vcpu, vector);
5346         return 1;
5347 }
5348
5349 static int handle_apic_write(struct kvm_vcpu *vcpu)
5350 {
5351         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5352         u32 offset = exit_qualification & 0xfff;
5353
5354         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5355         kvm_apic_write_nodecode(vcpu, offset);
5356         return 1;
5357 }
5358
5359 static int handle_task_switch(struct kvm_vcpu *vcpu)
5360 {
5361         struct vcpu_vmx *vmx = to_vmx(vcpu);
5362         unsigned long exit_qualification;
5363         bool has_error_code = false;
5364         u32 error_code = 0;
5365         u16 tss_selector;
5366         int reason, type, idt_v, idt_index;
5367
5368         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5369         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5370         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5371
5372         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5373
5374         reason = (u32)exit_qualification >> 30;
5375         if (reason == TASK_SWITCH_GATE && idt_v) {
5376                 switch (type) {
5377                 case INTR_TYPE_NMI_INTR:
5378                         vcpu->arch.nmi_injected = false;
5379                         vmx_set_nmi_mask(vcpu, true);
5380                         break;
5381                 case INTR_TYPE_EXT_INTR:
5382                 case INTR_TYPE_SOFT_INTR:
5383                         kvm_clear_interrupt_queue(vcpu);
5384                         break;
5385                 case INTR_TYPE_HARD_EXCEPTION:
5386                         if (vmx->idt_vectoring_info &
5387                             VECTORING_INFO_DELIVER_CODE_MASK) {
5388                                 has_error_code = true;
5389                                 error_code =
5390                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5391                         }
5392                         /* fall through */
5393                 case INTR_TYPE_SOFT_EXCEPTION:
5394                         kvm_clear_exception_queue(vcpu);
5395                         break;
5396                 default:
5397                         break;
5398                 }
5399         }
5400         tss_selector = exit_qualification;
5401
5402         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5403                        type != INTR_TYPE_EXT_INTR &&
5404                        type != INTR_TYPE_NMI_INTR))
5405                 skip_emulated_instruction(vcpu);
5406
5407         if (kvm_task_switch(vcpu, tss_selector,
5408                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5409                             has_error_code, error_code) == EMULATE_FAIL) {
5410                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5411                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5412                 vcpu->run->internal.ndata = 0;
5413                 return 0;
5414         }
5415
5416         /* clear all local breakpoint enable flags */
5417         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5418
5419         /*
5420          * TODO: What about debug traps on tss switch?
5421          *       Are we supposed to inject them and update dr6?
5422          */
5423
5424         return 1;
5425 }
5426
5427 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5428 {
5429         unsigned long exit_qualification;
5430         gpa_t gpa;
5431         u32 error_code;
5432         int gla_validity;
5433
5434         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5435
5436         gla_validity = (exit_qualification >> 7) & 0x3;
5437         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5438                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5439                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5440                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5441                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5442                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5443                         (long unsigned int)exit_qualification);
5444                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5445                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5446                 return 0;
5447         }
5448
5449         /*
5450          * EPT violation happened while executing iret from NMI,
5451          * "blocked by NMI" bit has to be set before next VM entry.
5452          * There are errata that may cause this bit to not be set:
5453          * AAK134, BY25.
5454          */
5455         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5456                         cpu_has_virtual_nmis() &&
5457                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5458                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5459
5460         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5461         trace_kvm_page_fault(gpa, exit_qualification);
5462
5463         /* It is a write fault? */
5464         error_code = exit_qualification & (1U << 1);
5465         /* It is a fetch fault? */
5466         error_code |= (exit_qualification & (1U << 2)) << 2;
5467         /* ept page table is present? */
5468         error_code |= (exit_qualification >> 3) & 0x1;
5469
5470         vcpu->arch.exit_qualification = exit_qualification;
5471
5472         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5473 }
5474
5475 static u64 ept_rsvd_mask(u64 spte, int level)
5476 {
5477         int i;
5478         u64 mask = 0;
5479
5480         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5481                 mask |= (1ULL << i);
5482
5483         if (level > 2)
5484                 /* bits 7:3 reserved */
5485                 mask |= 0xf8;
5486         else if (level == 2) {
5487                 if (spte & (1ULL << 7))
5488                         /* 2MB ref, bits 20:12 reserved */
5489                         mask |= 0x1ff000;
5490                 else
5491                         /* bits 6:3 reserved */
5492                         mask |= 0x78;
5493         }
5494
5495         return mask;
5496 }
5497
5498 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5499                                        int level)
5500 {
5501         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5502
5503         /* 010b (write-only) */
5504         WARN_ON((spte & 0x7) == 0x2);
5505
5506         /* 110b (write/execute) */
5507         WARN_ON((spte & 0x7) == 0x6);
5508
5509         /* 100b (execute-only) and value not supported by logical processor */
5510         if (!cpu_has_vmx_ept_execute_only())
5511                 WARN_ON((spte & 0x7) == 0x4);
5512
5513         /* not 000b */
5514         if ((spte & 0x7)) {
5515                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5516
5517                 if (rsvd_bits != 0) {
5518                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5519                                          __func__, rsvd_bits);
5520                         WARN_ON(1);
5521                 }
5522
5523                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5524                         u64 ept_mem_type = (spte & 0x38) >> 3;
5525
5526                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5527                             ept_mem_type == 7) {
5528                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5529                                                 __func__, ept_mem_type);
5530                                 WARN_ON(1);
5531                         }
5532                 }
5533         }
5534 }
5535
5536 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5537 {
5538         u64 sptes[4];
5539         int nr_sptes, i, ret;
5540         gpa_t gpa;
5541
5542         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5543         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5544                 skip_emulated_instruction(vcpu);
5545                 return 1;
5546         }
5547
5548         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5549         if (likely(ret == RET_MMIO_PF_EMULATE))
5550                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5551                                               EMULATE_DONE;
5552
5553         if (unlikely(ret == RET_MMIO_PF_INVALID))
5554                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5555
5556         if (unlikely(ret == RET_MMIO_PF_RETRY))
5557                 return 1;
5558
5559         /* It is the real ept misconfig */
5560         printk(KERN_ERR "EPT: Misconfiguration.\n");
5561         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5562
5563         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5564
5565         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5566                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5567
5568         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5569         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5570
5571         return 0;
5572 }
5573
5574 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5575 {
5576         u32 cpu_based_vm_exec_control;
5577
5578         /* clear pending NMI */
5579         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5580         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5581         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5582         ++vcpu->stat.nmi_window_exits;
5583         kvm_make_request(KVM_REQ_EVENT, vcpu);
5584
5585         return 1;
5586 }
5587
5588 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5589 {
5590         struct vcpu_vmx *vmx = to_vmx(vcpu);
5591         enum emulation_result err = EMULATE_DONE;
5592         int ret = 1;
5593         u32 cpu_exec_ctrl;
5594         bool intr_window_requested;
5595         unsigned count = 130;
5596
5597         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5598         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5599
5600         while (!guest_state_valid(vcpu) && count-- != 0) {
5601                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5602                         return handle_interrupt_window(&vmx->vcpu);
5603
5604                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5605                         return 1;
5606
5607                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5608
5609                 if (err == EMULATE_USER_EXIT) {
5610                         ++vcpu->stat.mmio_exits;
5611                         ret = 0;
5612                         goto out;
5613                 }
5614
5615                 if (err != EMULATE_DONE) {
5616                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5617                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5618                         vcpu->run->internal.ndata = 0;
5619                         return 0;
5620                 }
5621
5622                 if (vcpu->arch.halt_request) {
5623                         vcpu->arch.halt_request = 0;
5624                         ret = kvm_emulate_halt(vcpu);
5625                         goto out;
5626                 }
5627
5628                 if (signal_pending(current))
5629                         goto out;
5630                 if (need_resched())
5631                         schedule();
5632         }
5633
5634         vmx->emulation_required = emulation_required(vcpu);
5635 out:
5636         return ret;
5637 }
5638
5639 /*
5640  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5641  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5642  */
5643 static int handle_pause(struct kvm_vcpu *vcpu)
5644 {
5645         skip_emulated_instruction(vcpu);
5646         kvm_vcpu_on_spin(vcpu);
5647
5648         return 1;
5649 }
5650
5651 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5652 {
5653         kvm_queue_exception(vcpu, UD_VECTOR);
5654         return 1;
5655 }
5656
5657 /*
5658  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5659  * We could reuse a single VMCS for all the L2 guests, but we also want the
5660  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5661  * allows keeping them loaded on the processor, and in the future will allow
5662  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5663  * every entry if they never change.
5664  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5665  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5666  *
5667  * The following functions allocate and free a vmcs02 in this pool.
5668  */
5669
5670 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5671 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5672 {
5673         struct vmcs02_list *item;
5674         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5675                 if (item->vmptr == vmx->nested.current_vmptr) {
5676                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5677                         return &item->vmcs02;
5678                 }
5679
5680         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5681                 /* Recycle the least recently used VMCS. */
5682                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5683                         struct vmcs02_list, list);
5684                 item->vmptr = vmx->nested.current_vmptr;
5685                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5686                 return &item->vmcs02;
5687         }
5688
5689         /* Create a new VMCS */
5690         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5691         if (!item)
5692                 return NULL;
5693         item->vmcs02.vmcs = alloc_vmcs();
5694         if (!item->vmcs02.vmcs) {
5695                 kfree(item);
5696                 return NULL;
5697         }
5698         loaded_vmcs_init(&item->vmcs02);
5699         item->vmptr = vmx->nested.current_vmptr;
5700         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5701         vmx->nested.vmcs02_num++;
5702         return &item->vmcs02;
5703 }
5704
5705 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5706 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5707 {
5708         struct vmcs02_list *item;
5709         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5710                 if (item->vmptr == vmptr) {
5711                         free_loaded_vmcs(&item->vmcs02);
5712                         list_del(&item->list);
5713                         kfree(item);
5714                         vmx->nested.vmcs02_num--;
5715                         return;
5716                 }
5717 }
5718
5719 /*
5720  * Free all VMCSs saved for this vcpu, except the one pointed by
5721  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5722  * currently used, if running L2), and vmcs01 when running L2.
5723  */
5724 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5725 {
5726         struct vmcs02_list *item, *n;
5727         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5728                 if (vmx->loaded_vmcs != &item->vmcs02)
5729                         free_loaded_vmcs(&item->vmcs02);
5730                 list_del(&item->list);
5731                 kfree(item);
5732         }
5733         vmx->nested.vmcs02_num = 0;
5734
5735         if (vmx->loaded_vmcs != &vmx->vmcs01)
5736                 free_loaded_vmcs(&vmx->vmcs01);
5737 }
5738
5739 /*
5740  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5741  * set the success or error code of an emulated VMX instruction, as specified
5742  * by Vol 2B, VMX Instruction Reference, "Conventions".
5743  */
5744 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5745 {
5746         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5747                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5748                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5749 }
5750
5751 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5752 {
5753         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5754                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5755                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5756                         | X86_EFLAGS_CF);
5757 }
5758
5759 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5760                                         u32 vm_instruction_error)
5761 {
5762         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5763                 /*
5764                  * failValid writes the error number to the current VMCS, which
5765                  * can't be done there isn't a current VMCS.
5766                  */
5767                 nested_vmx_failInvalid(vcpu);
5768                 return;
5769         }
5770         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5771                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5772                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5773                         | X86_EFLAGS_ZF);
5774         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5775         /*
5776          * We don't need to force a shadow sync because
5777          * VM_INSTRUCTION_ERROR is not shadowed
5778          */
5779 }
5780
5781 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5782 {
5783         struct vcpu_vmx *vmx =
5784                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5785
5786         vmx->nested.preemption_timer_expired = true;
5787         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5788         kvm_vcpu_kick(&vmx->vcpu);
5789
5790         return HRTIMER_NORESTART;
5791 }
5792
5793 /*
5794  * Emulate the VMXON instruction.
5795  * Currently, we just remember that VMX is active, and do not save or even
5796  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5797  * do not currently need to store anything in that guest-allocated memory
5798  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5799  * argument is different from the VMXON pointer (which the spec says they do).
5800  */
5801 static int handle_vmon(struct kvm_vcpu *vcpu)
5802 {
5803         struct kvm_segment cs;
5804         struct vcpu_vmx *vmx = to_vmx(vcpu);
5805         struct vmcs *shadow_vmcs;
5806         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5807                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5808
5809         /* The Intel VMX Instruction Reference lists a bunch of bits that
5810          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5811          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5812          * Otherwise, we should fail with #UD. We test these now:
5813          */
5814         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5815             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5816             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5817                 kvm_queue_exception(vcpu, UD_VECTOR);
5818                 return 1;
5819         }
5820
5821         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5822         if (is_long_mode(vcpu) && !cs.l) {
5823                 kvm_queue_exception(vcpu, UD_VECTOR);
5824                 return 1;
5825         }
5826
5827         if (vmx_get_cpl(vcpu)) {
5828                 kvm_inject_gp(vcpu, 0);
5829                 return 1;
5830         }
5831         if (vmx->nested.vmxon) {
5832                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5833                 skip_emulated_instruction(vcpu);
5834                 return 1;
5835         }
5836
5837         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5838                         != VMXON_NEEDED_FEATURES) {
5839                 kvm_inject_gp(vcpu, 0);
5840                 return 1;
5841         }
5842
5843         if (enable_shadow_vmcs) {
5844                 shadow_vmcs = alloc_vmcs();
5845                 if (!shadow_vmcs)
5846                         return -ENOMEM;
5847                 /* mark vmcs as shadow */
5848                 shadow_vmcs->revision_id |= (1u << 31);
5849                 /* init shadow vmcs */
5850                 vmcs_clear(shadow_vmcs);
5851                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5852         }
5853
5854         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5855         vmx->nested.vmcs02_num = 0;
5856
5857         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5858                      HRTIMER_MODE_REL);
5859         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5860
5861         vmx->nested.vmxon = true;
5862
5863         skip_emulated_instruction(vcpu);
5864         nested_vmx_succeed(vcpu);
5865         return 1;
5866 }
5867
5868 /*
5869  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5870  * for running VMX instructions (except VMXON, whose prerequisites are
5871  * slightly different). It also specifies what exception to inject otherwise.
5872  */
5873 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5874 {
5875         struct kvm_segment cs;
5876         struct vcpu_vmx *vmx = to_vmx(vcpu);
5877
5878         if (!vmx->nested.vmxon) {
5879                 kvm_queue_exception(vcpu, UD_VECTOR);
5880                 return 0;
5881         }
5882
5883         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5884         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5885             (is_long_mode(vcpu) && !cs.l)) {
5886                 kvm_queue_exception(vcpu, UD_VECTOR);
5887                 return 0;
5888         }
5889
5890         if (vmx_get_cpl(vcpu)) {
5891                 kvm_inject_gp(vcpu, 0);
5892                 return 0;
5893         }
5894
5895         return 1;
5896 }
5897
5898 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5899 {
5900         u32 exec_control;
5901         if (enable_shadow_vmcs) {
5902                 if (vmx->nested.current_vmcs12 != NULL) {
5903                         /* copy to memory all shadowed fields in case
5904                            they were modified */
5905                         copy_shadow_to_vmcs12(vmx);
5906                         vmx->nested.sync_shadow_vmcs = false;
5907                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5908                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5909                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5910                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5911                 }
5912         }
5913         kunmap(vmx->nested.current_vmcs12_page);
5914         nested_release_page(vmx->nested.current_vmcs12_page);
5915 }
5916
5917 /*
5918  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5919  * just stops using VMX.
5920  */
5921 static void free_nested(struct vcpu_vmx *vmx)
5922 {
5923         if (!vmx->nested.vmxon)
5924                 return;
5925         vmx->nested.vmxon = false;
5926         if (vmx->nested.current_vmptr != -1ull) {
5927                 nested_release_vmcs12(vmx);
5928                 vmx->nested.current_vmptr = -1ull;
5929                 vmx->nested.current_vmcs12 = NULL;
5930         }
5931         if (enable_shadow_vmcs)
5932                 free_vmcs(vmx->nested.current_shadow_vmcs);
5933         /* Unpin physical memory we referred to in current vmcs02 */
5934         if (vmx->nested.apic_access_page) {
5935                 nested_release_page(vmx->nested.apic_access_page);
5936                 vmx->nested.apic_access_page = 0;
5937         }
5938
5939         nested_free_all_saved_vmcss(vmx);
5940 }
5941
5942 /* Emulate the VMXOFF instruction */
5943 static int handle_vmoff(struct kvm_vcpu *vcpu)
5944 {
5945         if (!nested_vmx_check_permission(vcpu))
5946                 return 1;
5947         free_nested(to_vmx(vcpu));
5948         skip_emulated_instruction(vcpu);
5949         nested_vmx_succeed(vcpu);
5950         return 1;
5951 }
5952
5953 /*
5954  * Decode the memory-address operand of a vmx instruction, as recorded on an
5955  * exit caused by such an instruction (run by a guest hypervisor).
5956  * On success, returns 0. When the operand is invalid, returns 1 and throws
5957  * #UD or #GP.
5958  */
5959 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5960                                  unsigned long exit_qualification,
5961                                  u32 vmx_instruction_info, gva_t *ret)
5962 {
5963         /*
5964          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5965          * Execution", on an exit, vmx_instruction_info holds most of the
5966          * addressing components of the operand. Only the displacement part
5967          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5968          * For how an actual address is calculated from all these components,
5969          * refer to Vol. 1, "Operand Addressing".
5970          */
5971         int  scaling = vmx_instruction_info & 3;
5972         int  addr_size = (vmx_instruction_info >> 7) & 7;
5973         bool is_reg = vmx_instruction_info & (1u << 10);
5974         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5975         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5976         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5977         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5978         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5979
5980         if (is_reg) {
5981                 kvm_queue_exception(vcpu, UD_VECTOR);
5982                 return 1;
5983         }
5984
5985         /* Addr = segment_base + offset */
5986         /* offset = base + [index * scale] + displacement */
5987         *ret = vmx_get_segment_base(vcpu, seg_reg);
5988         if (base_is_valid)
5989                 *ret += kvm_register_read(vcpu, base_reg);
5990         if (index_is_valid)
5991                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5992         *ret += exit_qualification; /* holds the displacement */
5993
5994         if (addr_size == 1) /* 32 bit */
5995                 *ret &= 0xffffffff;
5996
5997         /*
5998          * TODO: throw #GP (and return 1) in various cases that the VM*
5999          * instructions require it - e.g., offset beyond segment limit,
6000          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6001          * address, and so on. Currently these are not checked.
6002          */
6003         return 0;
6004 }
6005
6006 /* Emulate the VMCLEAR instruction */
6007 static int handle_vmclear(struct kvm_vcpu *vcpu)
6008 {
6009         struct vcpu_vmx *vmx = to_vmx(vcpu);
6010         gva_t gva;
6011         gpa_t vmptr;
6012         struct vmcs12 *vmcs12;
6013         struct page *page;
6014         struct x86_exception e;
6015
6016         if (!nested_vmx_check_permission(vcpu))
6017                 return 1;
6018
6019         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6020                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6021                 return 1;
6022
6023         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6024                                 sizeof(vmptr), &e)) {
6025                 kvm_inject_page_fault(vcpu, &e);
6026                 return 1;
6027         }
6028
6029         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6030                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
6031                 skip_emulated_instruction(vcpu);
6032                 return 1;
6033         }
6034
6035         if (vmptr == vmx->nested.current_vmptr) {
6036                 nested_release_vmcs12(vmx);
6037                 vmx->nested.current_vmptr = -1ull;
6038                 vmx->nested.current_vmcs12 = NULL;
6039         }
6040
6041         page = nested_get_page(vcpu, vmptr);
6042         if (page == NULL) {
6043                 /*
6044                  * For accurate processor emulation, VMCLEAR beyond available
6045                  * physical memory should do nothing at all. However, it is
6046                  * possible that a nested vmx bug, not a guest hypervisor bug,
6047                  * resulted in this case, so let's shut down before doing any
6048                  * more damage:
6049                  */
6050                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6051                 return 1;
6052         }
6053         vmcs12 = kmap(page);
6054         vmcs12->launch_state = 0;
6055         kunmap(page);
6056         nested_release_page(page);
6057
6058         nested_free_vmcs02(vmx, vmptr);
6059
6060         skip_emulated_instruction(vcpu);
6061         nested_vmx_succeed(vcpu);
6062         return 1;
6063 }
6064
6065 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6066
6067 /* Emulate the VMLAUNCH instruction */
6068 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6069 {
6070         return nested_vmx_run(vcpu, true);
6071 }
6072
6073 /* Emulate the VMRESUME instruction */
6074 static int handle_vmresume(struct kvm_vcpu *vcpu)
6075 {
6076
6077         return nested_vmx_run(vcpu, false);
6078 }
6079
6080 enum vmcs_field_type {
6081         VMCS_FIELD_TYPE_U16 = 0,
6082         VMCS_FIELD_TYPE_U64 = 1,
6083         VMCS_FIELD_TYPE_U32 = 2,
6084         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6085 };
6086
6087 static inline int vmcs_field_type(unsigned long field)
6088 {
6089         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6090                 return VMCS_FIELD_TYPE_U32;
6091         return (field >> 13) & 0x3 ;
6092 }
6093
6094 static inline int vmcs_field_readonly(unsigned long field)
6095 {
6096         return (((field >> 10) & 0x3) == 1);
6097 }
6098
6099 /*
6100  * Read a vmcs12 field. Since these can have varying lengths and we return
6101  * one type, we chose the biggest type (u64) and zero-extend the return value
6102  * to that size. Note that the caller, handle_vmread, might need to use only
6103  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6104  * 64-bit fields are to be returned).
6105  */
6106 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6107                                         unsigned long field, u64 *ret)
6108 {
6109         short offset = vmcs_field_to_offset(field);
6110         char *p;
6111
6112         if (offset < 0)
6113                 return 0;
6114
6115         p = ((char *)(get_vmcs12(vcpu))) + offset;
6116
6117         switch (vmcs_field_type(field)) {
6118         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6119                 *ret = *((natural_width *)p);
6120                 return 1;
6121         case VMCS_FIELD_TYPE_U16:
6122                 *ret = *((u16 *)p);
6123                 return 1;
6124         case VMCS_FIELD_TYPE_U32:
6125                 *ret = *((u32 *)p);
6126                 return 1;
6127         case VMCS_FIELD_TYPE_U64:
6128                 *ret = *((u64 *)p);
6129                 return 1;
6130         default:
6131                 return 0; /* can never happen. */
6132         }
6133 }
6134
6135
6136 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6137                                     unsigned long field, u64 field_value){
6138         short offset = vmcs_field_to_offset(field);
6139         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6140         if (offset < 0)
6141                 return false;
6142
6143         switch (vmcs_field_type(field)) {
6144         case VMCS_FIELD_TYPE_U16:
6145                 *(u16 *)p = field_value;
6146                 return true;
6147         case VMCS_FIELD_TYPE_U32:
6148                 *(u32 *)p = field_value;
6149                 return true;
6150         case VMCS_FIELD_TYPE_U64:
6151                 *(u64 *)p = field_value;
6152                 return true;
6153         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6154                 *(natural_width *)p = field_value;
6155                 return true;
6156         default:
6157                 return false; /* can never happen. */
6158         }
6159
6160 }
6161
6162 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6163 {
6164         int i;
6165         unsigned long field;
6166         u64 field_value;
6167         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6168         const unsigned long *fields = shadow_read_write_fields;
6169         const int num_fields = max_shadow_read_write_fields;
6170
6171         vmcs_load(shadow_vmcs);
6172
6173         for (i = 0; i < num_fields; i++) {
6174                 field = fields[i];
6175                 switch (vmcs_field_type(field)) {
6176                 case VMCS_FIELD_TYPE_U16:
6177                         field_value = vmcs_read16(field);
6178                         break;
6179                 case VMCS_FIELD_TYPE_U32:
6180                         field_value = vmcs_read32(field);
6181                         break;
6182                 case VMCS_FIELD_TYPE_U64:
6183                         field_value = vmcs_read64(field);
6184                         break;
6185                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6186                         field_value = vmcs_readl(field);
6187                         break;
6188                 }
6189                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6190         }
6191
6192         vmcs_clear(shadow_vmcs);
6193         vmcs_load(vmx->loaded_vmcs->vmcs);
6194 }
6195
6196 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6197 {
6198         const unsigned long *fields[] = {
6199                 shadow_read_write_fields,
6200                 shadow_read_only_fields
6201         };
6202         const int max_fields[] = {
6203                 max_shadow_read_write_fields,
6204                 max_shadow_read_only_fields
6205         };
6206         int i, q;
6207         unsigned long field;
6208         u64 field_value = 0;
6209         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6210
6211         vmcs_load(shadow_vmcs);
6212
6213         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6214                 for (i = 0; i < max_fields[q]; i++) {
6215                         field = fields[q][i];
6216                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6217
6218                         switch (vmcs_field_type(field)) {
6219                         case VMCS_FIELD_TYPE_U16:
6220                                 vmcs_write16(field, (u16)field_value);
6221                                 break;
6222                         case VMCS_FIELD_TYPE_U32:
6223                                 vmcs_write32(field, (u32)field_value);
6224                                 break;
6225                         case VMCS_FIELD_TYPE_U64:
6226                                 vmcs_write64(field, (u64)field_value);
6227                                 break;
6228                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6229                                 vmcs_writel(field, (long)field_value);
6230                                 break;
6231                         }
6232                 }
6233         }
6234
6235         vmcs_clear(shadow_vmcs);
6236         vmcs_load(vmx->loaded_vmcs->vmcs);
6237 }
6238
6239 /*
6240  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6241  * used before) all generate the same failure when it is missing.
6242  */
6243 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6244 {
6245         struct vcpu_vmx *vmx = to_vmx(vcpu);
6246         if (vmx->nested.current_vmptr == -1ull) {
6247                 nested_vmx_failInvalid(vcpu);
6248                 skip_emulated_instruction(vcpu);
6249                 return 0;
6250         }
6251         return 1;
6252 }
6253
6254 static int handle_vmread(struct kvm_vcpu *vcpu)
6255 {
6256         unsigned long field;
6257         u64 field_value;
6258         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6259         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6260         gva_t gva = 0;
6261
6262         if (!nested_vmx_check_permission(vcpu) ||
6263             !nested_vmx_check_vmcs12(vcpu))
6264                 return 1;
6265
6266         /* Decode instruction info and find the field to read */
6267         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6268         /* Read the field, zero-extended to a u64 field_value */
6269         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6270                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6271                 skip_emulated_instruction(vcpu);
6272                 return 1;
6273         }
6274         /*
6275          * Now copy part of this value to register or memory, as requested.
6276          * Note that the number of bits actually copied is 32 or 64 depending
6277          * on the guest's mode (32 or 64 bit), not on the given field's length.
6278          */
6279         if (vmx_instruction_info & (1u << 10)) {
6280                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6281                         field_value);
6282         } else {
6283                 if (get_vmx_mem_address(vcpu, exit_qualification,
6284                                 vmx_instruction_info, &gva))
6285                         return 1;
6286                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6287                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6288                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6289         }
6290
6291         nested_vmx_succeed(vcpu);
6292         skip_emulated_instruction(vcpu);
6293         return 1;
6294 }
6295
6296
6297 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6298 {
6299         unsigned long field;
6300         gva_t gva;
6301         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6302         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6303         /* The value to write might be 32 or 64 bits, depending on L1's long
6304          * mode, and eventually we need to write that into a field of several
6305          * possible lengths. The code below first zero-extends the value to 64
6306          * bit (field_value), and then copies only the approriate number of
6307          * bits into the vmcs12 field.
6308          */
6309         u64 field_value = 0;
6310         struct x86_exception e;
6311
6312         if (!nested_vmx_check_permission(vcpu) ||
6313             !nested_vmx_check_vmcs12(vcpu))
6314                 return 1;
6315
6316         if (vmx_instruction_info & (1u << 10))
6317                 field_value = kvm_register_read(vcpu,
6318                         (((vmx_instruction_info) >> 3) & 0xf));
6319         else {
6320                 if (get_vmx_mem_address(vcpu, exit_qualification,
6321                                 vmx_instruction_info, &gva))
6322                         return 1;
6323                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6324                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6325                         kvm_inject_page_fault(vcpu, &e);
6326                         return 1;
6327                 }
6328         }
6329
6330
6331         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6332         if (vmcs_field_readonly(field)) {
6333                 nested_vmx_failValid(vcpu,
6334                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6335                 skip_emulated_instruction(vcpu);
6336                 return 1;
6337         }
6338
6339         if (!vmcs12_write_any(vcpu, field, field_value)) {
6340                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6341                 skip_emulated_instruction(vcpu);
6342                 return 1;
6343         }
6344
6345         nested_vmx_succeed(vcpu);
6346         skip_emulated_instruction(vcpu);
6347         return 1;
6348 }
6349
6350 /* Emulate the VMPTRLD instruction */
6351 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6352 {
6353         struct vcpu_vmx *vmx = to_vmx(vcpu);
6354         gva_t gva;
6355         gpa_t vmptr;
6356         struct x86_exception e;
6357         u32 exec_control;
6358
6359         if (!nested_vmx_check_permission(vcpu))
6360                 return 1;
6361
6362         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6363                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6364                 return 1;
6365
6366         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6367                                 sizeof(vmptr), &e)) {
6368                 kvm_inject_page_fault(vcpu, &e);
6369                 return 1;
6370         }
6371
6372         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6373                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6374                 skip_emulated_instruction(vcpu);
6375                 return 1;
6376         }
6377
6378         if (vmx->nested.current_vmptr != vmptr) {
6379                 struct vmcs12 *new_vmcs12;
6380                 struct page *page;
6381                 page = nested_get_page(vcpu, vmptr);
6382                 if (page == NULL) {
6383                         nested_vmx_failInvalid(vcpu);
6384                         skip_emulated_instruction(vcpu);
6385                         return 1;
6386                 }
6387                 new_vmcs12 = kmap(page);
6388                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6389                         kunmap(page);
6390                         nested_release_page_clean(page);
6391                         nested_vmx_failValid(vcpu,
6392                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6393                         skip_emulated_instruction(vcpu);
6394                         return 1;
6395                 }
6396                 if (vmx->nested.current_vmptr != -1ull)
6397                         nested_release_vmcs12(vmx);
6398
6399                 vmx->nested.current_vmptr = vmptr;
6400                 vmx->nested.current_vmcs12 = new_vmcs12;
6401                 vmx->nested.current_vmcs12_page = page;
6402                 if (enable_shadow_vmcs) {
6403                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6404                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6405                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6406                         vmcs_write64(VMCS_LINK_POINTER,
6407                                      __pa(vmx->nested.current_shadow_vmcs));
6408                         vmx->nested.sync_shadow_vmcs = true;
6409                 }
6410         }
6411
6412         nested_vmx_succeed(vcpu);
6413         skip_emulated_instruction(vcpu);
6414         return 1;
6415 }
6416
6417 /* Emulate the VMPTRST instruction */
6418 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6419 {
6420         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6421         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6422         gva_t vmcs_gva;
6423         struct x86_exception e;
6424
6425         if (!nested_vmx_check_permission(vcpu))
6426                 return 1;
6427
6428         if (get_vmx_mem_address(vcpu, exit_qualification,
6429                         vmx_instruction_info, &vmcs_gva))
6430                 return 1;
6431         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6432         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6433                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6434                                  sizeof(u64), &e)) {
6435                 kvm_inject_page_fault(vcpu, &e);
6436                 return 1;
6437         }
6438         nested_vmx_succeed(vcpu);
6439         skip_emulated_instruction(vcpu);
6440         return 1;
6441 }
6442
6443 /* Emulate the INVEPT instruction */
6444 static int handle_invept(struct kvm_vcpu *vcpu)
6445 {
6446         u32 vmx_instruction_info, types;
6447         unsigned long type;
6448         gva_t gva;
6449         struct x86_exception e;
6450         struct {
6451                 u64 eptp, gpa;
6452         } operand;
6453
6454         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6455             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6456                 kvm_queue_exception(vcpu, UD_VECTOR);
6457                 return 1;
6458         }
6459
6460         if (!nested_vmx_check_permission(vcpu))
6461                 return 1;
6462
6463         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6464                 kvm_queue_exception(vcpu, UD_VECTOR);
6465                 return 1;
6466         }
6467
6468         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6469         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6470
6471         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6472
6473         if (!(types & (1UL << type))) {
6474                 nested_vmx_failValid(vcpu,
6475                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6476                 return 1;
6477         }
6478
6479         /* According to the Intel VMX instruction reference, the memory
6480          * operand is read even if it isn't needed (e.g., for type==global)
6481          */
6482         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6483                         vmx_instruction_info, &gva))
6484                 return 1;
6485         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6486                                 sizeof(operand), &e)) {
6487                 kvm_inject_page_fault(vcpu, &e);
6488                 return 1;
6489         }
6490
6491         switch (type) {
6492         case VMX_EPT_EXTENT_GLOBAL:
6493                 kvm_mmu_sync_roots(vcpu);
6494                 kvm_mmu_flush_tlb(vcpu);
6495                 nested_vmx_succeed(vcpu);
6496                 break;
6497         default:
6498                 /* Trap single context invalidation invept calls */
6499                 BUG_ON(1);
6500                 break;
6501         }
6502
6503         skip_emulated_instruction(vcpu);
6504         return 1;
6505 }
6506
6507 /*
6508  * The exit handlers return 1 if the exit was handled fully and guest execution
6509  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6510  * to be done to userspace and return 0.
6511  */
6512 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6513         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6514         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6515         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6516         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6517         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6518         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6519         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6520         [EXIT_REASON_CPUID]                   = handle_cpuid,
6521         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6522         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6523         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6524         [EXIT_REASON_HLT]                     = handle_halt,
6525         [EXIT_REASON_INVD]                    = handle_invd,
6526         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6527         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6528         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6529         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6530         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6531         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6532         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6533         [EXIT_REASON_VMREAD]                  = handle_vmread,
6534         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6535         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6536         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6537         [EXIT_REASON_VMON]                    = handle_vmon,
6538         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6539         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6540         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6541         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6542         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6543         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6544         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6545         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6546         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6547         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6548         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6549         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6550         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6551         [EXIT_REASON_INVEPT]                  = handle_invept,
6552 };
6553
6554 static const int kvm_vmx_max_exit_handlers =
6555         ARRAY_SIZE(kvm_vmx_exit_handlers);
6556
6557 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6558                                        struct vmcs12 *vmcs12)
6559 {
6560         unsigned long exit_qualification;
6561         gpa_t bitmap, last_bitmap;
6562         unsigned int port;
6563         int size;
6564         u8 b;
6565
6566         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6567                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6568
6569         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6570
6571         port = exit_qualification >> 16;
6572         size = (exit_qualification & 7) + 1;
6573
6574         last_bitmap = (gpa_t)-1;
6575         b = -1;
6576
6577         while (size > 0) {
6578                 if (port < 0x8000)
6579                         bitmap = vmcs12->io_bitmap_a;
6580                 else if (port < 0x10000)
6581                         bitmap = vmcs12->io_bitmap_b;
6582                 else
6583                         return 1;
6584                 bitmap += (port & 0x7fff) / 8;
6585
6586                 if (last_bitmap != bitmap)
6587                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6588                                 return 1;
6589                 if (b & (1 << (port & 7)))
6590                         return 1;
6591
6592                 port++;
6593                 size--;
6594                 last_bitmap = bitmap;
6595         }
6596
6597         return 0;
6598 }
6599
6600 /*
6601  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6602  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6603  * disinterest in the current event (read or write a specific MSR) by using an
6604  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6605  */
6606 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6607         struct vmcs12 *vmcs12, u32 exit_reason)
6608 {
6609         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6610         gpa_t bitmap;
6611
6612         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6613                 return 1;
6614
6615         /*
6616          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6617          * for the four combinations of read/write and low/high MSR numbers.
6618          * First we need to figure out which of the four to use:
6619          */
6620         bitmap = vmcs12->msr_bitmap;
6621         if (exit_reason == EXIT_REASON_MSR_WRITE)
6622                 bitmap += 2048;
6623         if (msr_index >= 0xc0000000) {
6624                 msr_index -= 0xc0000000;
6625                 bitmap += 1024;
6626         }
6627
6628         /* Then read the msr_index'th bit from this bitmap: */
6629         if (msr_index < 1024*8) {
6630                 unsigned char b;
6631                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6632                         return 1;
6633                 return 1 & (b >> (msr_index & 7));
6634         } else
6635                 return 1; /* let L1 handle the wrong parameter */
6636 }
6637
6638 /*
6639  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6640  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6641  * intercept (via guest_host_mask etc.) the current event.
6642  */
6643 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6644         struct vmcs12 *vmcs12)
6645 {
6646         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6647         int cr = exit_qualification & 15;
6648         int reg = (exit_qualification >> 8) & 15;
6649         unsigned long val = kvm_register_read(vcpu, reg);
6650
6651         switch ((exit_qualification >> 4) & 3) {
6652         case 0: /* mov to cr */
6653                 switch (cr) {
6654                 case 0:
6655                         if (vmcs12->cr0_guest_host_mask &
6656                             (val ^ vmcs12->cr0_read_shadow))
6657                                 return 1;
6658                         break;
6659                 case 3:
6660                         if ((vmcs12->cr3_target_count >= 1 &&
6661                                         vmcs12->cr3_target_value0 == val) ||
6662                                 (vmcs12->cr3_target_count >= 2 &&
6663                                         vmcs12->cr3_target_value1 == val) ||
6664                                 (vmcs12->cr3_target_count >= 3 &&
6665                                         vmcs12->cr3_target_value2 == val) ||
6666                                 (vmcs12->cr3_target_count >= 4 &&
6667                                         vmcs12->cr3_target_value3 == val))
6668                                 return 0;
6669                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6670                                 return 1;
6671                         break;
6672                 case 4:
6673                         if (vmcs12->cr4_guest_host_mask &
6674                             (vmcs12->cr4_read_shadow ^ val))
6675                                 return 1;
6676                         break;
6677                 case 8:
6678                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6679                                 return 1;
6680                         break;
6681                 }
6682                 break;
6683         case 2: /* clts */
6684                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6685                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6686                         return 1;
6687                 break;
6688         case 1: /* mov from cr */
6689                 switch (cr) {
6690                 case 3:
6691                         if (vmcs12->cpu_based_vm_exec_control &
6692                             CPU_BASED_CR3_STORE_EXITING)
6693                                 return 1;
6694                         break;
6695                 case 8:
6696                         if (vmcs12->cpu_based_vm_exec_control &
6697                             CPU_BASED_CR8_STORE_EXITING)
6698                                 return 1;
6699                         break;
6700                 }
6701                 break;
6702         case 3: /* lmsw */
6703                 /*
6704                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6705                  * cr0. Other attempted changes are ignored, with no exit.
6706                  */
6707                 if (vmcs12->cr0_guest_host_mask & 0xe &
6708                     (val ^ vmcs12->cr0_read_shadow))
6709                         return 1;
6710                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6711                     !(vmcs12->cr0_read_shadow & 0x1) &&
6712                     (val & 0x1))
6713                         return 1;
6714                 break;
6715         }
6716         return 0;
6717 }
6718
6719 /*
6720  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6721  * should handle it ourselves in L0 (and then continue L2). Only call this
6722  * when in is_guest_mode (L2).
6723  */
6724 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6725 {
6726         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6727         struct vcpu_vmx *vmx = to_vmx(vcpu);
6728         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6729         u32 exit_reason = vmx->exit_reason;
6730
6731         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6732                                 vmcs_readl(EXIT_QUALIFICATION),
6733                                 vmx->idt_vectoring_info,
6734                                 intr_info,
6735                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6736                                 KVM_ISA_VMX);
6737
6738         if (vmx->nested.nested_run_pending)
6739                 return 0;
6740
6741         if (unlikely(vmx->fail)) {
6742                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6743                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6744                 return 1;
6745         }
6746
6747         switch (exit_reason) {
6748         case EXIT_REASON_EXCEPTION_NMI:
6749                 if (!is_exception(intr_info))
6750                         return 0;
6751                 else if (is_page_fault(intr_info))
6752                         return enable_ept;
6753                 else if (is_no_device(intr_info) &&
6754                          !(vmcs12->guest_cr0 & X86_CR0_TS))
6755                         return 0;
6756                 return vmcs12->exception_bitmap &
6757                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6758         case EXIT_REASON_EXTERNAL_INTERRUPT:
6759                 return 0;
6760         case EXIT_REASON_TRIPLE_FAULT:
6761                 return 1;
6762         case EXIT_REASON_PENDING_INTERRUPT:
6763                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6764         case EXIT_REASON_NMI_WINDOW:
6765                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6766         case EXIT_REASON_TASK_SWITCH:
6767                 return 1;
6768         case EXIT_REASON_CPUID:
6769                 return 1;
6770         case EXIT_REASON_HLT:
6771                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6772         case EXIT_REASON_INVD:
6773                 return 1;
6774         case EXIT_REASON_INVLPG:
6775                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6776         case EXIT_REASON_RDPMC:
6777                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6778         case EXIT_REASON_RDTSC:
6779                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6780         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6781         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6782         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6783         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6784         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6785         case EXIT_REASON_INVEPT:
6786                 /*
6787                  * VMX instructions trap unconditionally. This allows L1 to
6788                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6789                  */
6790                 return 1;
6791         case EXIT_REASON_CR_ACCESS:
6792                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6793         case EXIT_REASON_DR_ACCESS:
6794                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6795         case EXIT_REASON_IO_INSTRUCTION:
6796                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6797         case EXIT_REASON_MSR_READ:
6798         case EXIT_REASON_MSR_WRITE:
6799                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6800         case EXIT_REASON_INVALID_STATE:
6801                 return 1;
6802         case EXIT_REASON_MWAIT_INSTRUCTION:
6803                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6804         case EXIT_REASON_MONITOR_INSTRUCTION:
6805                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6806         case EXIT_REASON_PAUSE_INSTRUCTION:
6807                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6808                         nested_cpu_has2(vmcs12,
6809                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6810         case EXIT_REASON_MCE_DURING_VMENTRY:
6811                 return 0;
6812         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6813                 return 1;
6814         case EXIT_REASON_APIC_ACCESS:
6815                 return nested_cpu_has2(vmcs12,
6816                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6817         case EXIT_REASON_EPT_VIOLATION:
6818                 /*
6819                  * L0 always deals with the EPT violation. If nested EPT is
6820                  * used, and the nested mmu code discovers that the address is
6821                  * missing in the guest EPT table (EPT12), the EPT violation
6822                  * will be injected with nested_ept_inject_page_fault()
6823                  */
6824                 return 0;
6825         case EXIT_REASON_EPT_MISCONFIG:
6826                 /*
6827                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6828                  * table (shadow on EPT) or a merged EPT table that L0 built
6829                  * (EPT on EPT). So any problems with the structure of the
6830                  * table is L0's fault.
6831                  */
6832                 return 0;
6833         case EXIT_REASON_WBINVD:
6834                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6835         case EXIT_REASON_XSETBV:
6836                 return 1;
6837         default:
6838                 return 1;
6839         }
6840 }
6841
6842 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6843 {
6844         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6845         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6846 }
6847
6848 /*
6849  * The guest has exited.  See if we can fix it or if we need userspace
6850  * assistance.
6851  */
6852 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6853 {
6854         struct vcpu_vmx *vmx = to_vmx(vcpu);
6855         u32 exit_reason = vmx->exit_reason;
6856         u32 vectoring_info = vmx->idt_vectoring_info;
6857
6858         /* If guest state is invalid, start emulating */
6859         if (vmx->emulation_required)
6860                 return handle_invalid_guest_state(vcpu);
6861
6862         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6863                 nested_vmx_vmexit(vcpu, exit_reason,
6864                                   vmcs_read32(VM_EXIT_INTR_INFO),
6865                                   vmcs_readl(EXIT_QUALIFICATION));
6866                 return 1;
6867         }
6868
6869         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6870                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6871                 vcpu->run->fail_entry.hardware_entry_failure_reason
6872                         = exit_reason;
6873                 return 0;
6874         }
6875
6876         if (unlikely(vmx->fail)) {
6877                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6878                 vcpu->run->fail_entry.hardware_entry_failure_reason
6879                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6880                 return 0;
6881         }
6882
6883         /*
6884          * Note:
6885          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6886          * delivery event since it indicates guest is accessing MMIO.
6887          * The vm-exit can be triggered again after return to guest that
6888          * will cause infinite loop.
6889          */
6890         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6891                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6892                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6893                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6894                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6895                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6896                 vcpu->run->internal.ndata = 2;
6897                 vcpu->run->internal.data[0] = vectoring_info;
6898                 vcpu->run->internal.data[1] = exit_reason;
6899                 return 0;
6900         }
6901
6902         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6903             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6904                                         get_vmcs12(vcpu))))) {
6905                 if (vmx_interrupt_allowed(vcpu)) {
6906                         vmx->soft_vnmi_blocked = 0;
6907                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6908                            vcpu->arch.nmi_pending) {
6909                         /*
6910                          * This CPU don't support us in finding the end of an
6911                          * NMI-blocked window if the guest runs with IRQs
6912                          * disabled. So we pull the trigger after 1 s of
6913                          * futile waiting, but inform the user about this.
6914                          */
6915                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6916                                "state on VCPU %d after 1 s timeout\n",
6917                                __func__, vcpu->vcpu_id);
6918                         vmx->soft_vnmi_blocked = 0;
6919                 }
6920         }
6921
6922         if (exit_reason < kvm_vmx_max_exit_handlers
6923             && kvm_vmx_exit_handlers[exit_reason])
6924                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6925         else {
6926                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6927                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6928         }
6929         return 0;
6930 }
6931
6932 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6933 {
6934         if (irr == -1 || tpr < irr) {
6935                 vmcs_write32(TPR_THRESHOLD, 0);
6936                 return;
6937         }
6938
6939         vmcs_write32(TPR_THRESHOLD, irr);
6940 }
6941
6942 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6943 {
6944         u32 sec_exec_control;
6945
6946         /*
6947          * There is not point to enable virtualize x2apic without enable
6948          * apicv
6949          */
6950         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6951                                 !vmx_vm_has_apicv(vcpu->kvm))
6952                 return;
6953
6954         if (!vm_need_tpr_shadow(vcpu->kvm))
6955                 return;
6956
6957         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6958
6959         if (set) {
6960                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6961                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6962         } else {
6963                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6964                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6965         }
6966         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6967
6968         vmx_set_msr_bitmap(vcpu);
6969 }
6970
6971 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6972 {
6973         u16 status;
6974         u8 old;
6975
6976         if (!vmx_vm_has_apicv(kvm))
6977                 return;
6978
6979         if (isr == -1)
6980                 isr = 0;
6981
6982         status = vmcs_read16(GUEST_INTR_STATUS);
6983         old = status >> 8;
6984         if (isr != old) {
6985                 status &= 0xff;
6986                 status |= isr << 8;
6987                 vmcs_write16(GUEST_INTR_STATUS, status);
6988         }
6989 }
6990
6991 static void vmx_set_rvi(int vector)
6992 {
6993         u16 status;
6994         u8 old;
6995
6996         status = vmcs_read16(GUEST_INTR_STATUS);
6997         old = (u8)status & 0xff;
6998         if ((u8)vector != old) {
6999                 status &= ~0xff;
7000                 status |= (u8)vector;
7001                 vmcs_write16(GUEST_INTR_STATUS, status);
7002         }
7003 }
7004
7005 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7006 {
7007         if (max_irr == -1)
7008                 return;
7009
7010         vmx_set_rvi(max_irr);
7011 }
7012
7013 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7014 {
7015         if (!vmx_vm_has_apicv(vcpu->kvm))
7016                 return;
7017
7018         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7019         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7020         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7021         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7022 }
7023
7024 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7025 {
7026         u32 exit_intr_info;
7027
7028         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7029               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7030                 return;
7031
7032         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7033         exit_intr_info = vmx->exit_intr_info;
7034
7035         /* Handle machine checks before interrupts are enabled */
7036         if (is_machine_check(exit_intr_info))
7037                 kvm_machine_check();
7038
7039         /* We need to handle NMIs before interrupts are enabled */
7040         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7041             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7042                 kvm_before_handle_nmi(&vmx->vcpu);
7043                 asm("int $2");
7044                 kvm_after_handle_nmi(&vmx->vcpu);
7045         }
7046 }
7047
7048 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7049 {
7050         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7051
7052         /*
7053          * If external interrupt exists, IF bit is set in rflags/eflags on the
7054          * interrupt stack frame, and interrupt will be enabled on a return
7055          * from interrupt handler.
7056          */
7057         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7058                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7059                 unsigned int vector;
7060                 unsigned long entry;
7061                 gate_desc *desc;
7062                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7063 #ifdef CONFIG_X86_64
7064                 unsigned long tmp;
7065 #endif
7066
7067                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7068                 desc = (gate_desc *)vmx->host_idt_base + vector;
7069                 entry = gate_offset(*desc);
7070                 asm volatile(
7071 #ifdef CONFIG_X86_64
7072                         "mov %%" _ASM_SP ", %[sp]\n\t"
7073                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7074                         "push $%c[ss]\n\t"
7075                         "push %[sp]\n\t"
7076 #endif
7077                         "pushf\n\t"
7078                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7079                         __ASM_SIZE(push) " $%c[cs]\n\t"
7080                         "call *%[entry]\n\t"
7081                         :
7082 #ifdef CONFIG_X86_64
7083                         [sp]"=&r"(tmp)
7084 #endif
7085                         :
7086                         [entry]"r"(entry),
7087                         [ss]"i"(__KERNEL_DS),
7088                         [cs]"i"(__KERNEL_CS)
7089                         );
7090         } else
7091                 local_irq_enable();
7092 }
7093
7094 static bool vmx_mpx_supported(void)
7095 {
7096         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7097                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7098 }
7099
7100 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7101 {
7102         u32 exit_intr_info;
7103         bool unblock_nmi;
7104         u8 vector;
7105         bool idtv_info_valid;
7106
7107         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7108
7109         if (cpu_has_virtual_nmis()) {
7110                 if (vmx->nmi_known_unmasked)
7111                         return;
7112                 /*
7113                  * Can't use vmx->exit_intr_info since we're not sure what
7114                  * the exit reason is.
7115                  */
7116                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7117                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7118                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7119                 /*
7120                  * SDM 3: 27.7.1.2 (September 2008)
7121                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7122                  * a guest IRET fault.
7123                  * SDM 3: 23.2.2 (September 2008)
7124                  * Bit 12 is undefined in any of the following cases:
7125                  *  If the VM exit sets the valid bit in the IDT-vectoring
7126                  *   information field.
7127                  *  If the VM exit is due to a double fault.
7128                  */
7129                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7130                     vector != DF_VECTOR && !idtv_info_valid)
7131                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7132                                       GUEST_INTR_STATE_NMI);
7133                 else
7134                         vmx->nmi_known_unmasked =
7135                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7136                                   & GUEST_INTR_STATE_NMI);
7137         } else if (unlikely(vmx->soft_vnmi_blocked))
7138                 vmx->vnmi_blocked_time +=
7139                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7140 }
7141
7142 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7143                                       u32 idt_vectoring_info,
7144                                       int instr_len_field,
7145                                       int error_code_field)
7146 {
7147         u8 vector;
7148         int type;
7149         bool idtv_info_valid;
7150
7151         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7152
7153         vcpu->arch.nmi_injected = false;
7154         kvm_clear_exception_queue(vcpu);
7155         kvm_clear_interrupt_queue(vcpu);
7156
7157         if (!idtv_info_valid)
7158                 return;
7159
7160         kvm_make_request(KVM_REQ_EVENT, vcpu);
7161
7162         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7163         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7164
7165         switch (type) {
7166         case INTR_TYPE_NMI_INTR:
7167                 vcpu->arch.nmi_injected = true;
7168                 /*
7169                  * SDM 3: 27.7.1.2 (September 2008)
7170                  * Clear bit "block by NMI" before VM entry if a NMI
7171                  * delivery faulted.
7172                  */
7173                 vmx_set_nmi_mask(vcpu, false);
7174                 break;
7175         case INTR_TYPE_SOFT_EXCEPTION:
7176                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7177                 /* fall through */
7178         case INTR_TYPE_HARD_EXCEPTION:
7179                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7180                         u32 err = vmcs_read32(error_code_field);
7181                         kvm_requeue_exception_e(vcpu, vector, err);
7182                 } else
7183                         kvm_requeue_exception(vcpu, vector);
7184                 break;
7185         case INTR_TYPE_SOFT_INTR:
7186                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7187                 /* fall through */
7188         case INTR_TYPE_EXT_INTR:
7189                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7190                 break;
7191         default:
7192                 break;
7193         }
7194 }
7195
7196 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7197 {
7198         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7199                                   VM_EXIT_INSTRUCTION_LEN,
7200                                   IDT_VECTORING_ERROR_CODE);
7201 }
7202
7203 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7204 {
7205         __vmx_complete_interrupts(vcpu,
7206                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7207                                   VM_ENTRY_INSTRUCTION_LEN,
7208                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7209
7210         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7211 }
7212
7213 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7214 {
7215         int i, nr_msrs;
7216         struct perf_guest_switch_msr *msrs;
7217
7218         msrs = perf_guest_get_msrs(&nr_msrs);
7219
7220         if (!msrs)
7221                 return;
7222
7223         for (i = 0; i < nr_msrs; i++)
7224                 if (msrs[i].host == msrs[i].guest)
7225                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7226                 else
7227                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7228                                         msrs[i].host);
7229 }
7230
7231 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7232 {
7233         struct vcpu_vmx *vmx = to_vmx(vcpu);
7234         unsigned long debugctlmsr;
7235
7236         /* Record the guest's net vcpu time for enforced NMI injections. */
7237         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7238                 vmx->entry_time = ktime_get();
7239
7240         /* Don't enter VMX if guest state is invalid, let the exit handler
7241            start emulation until we arrive back to a valid state */
7242         if (vmx->emulation_required)
7243                 return;
7244
7245         if (vmx->nested.sync_shadow_vmcs) {
7246                 copy_vmcs12_to_shadow(vmx);
7247                 vmx->nested.sync_shadow_vmcs = false;
7248         }
7249
7250         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7251                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7252         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7253                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7254
7255         /* When single-stepping over STI and MOV SS, we must clear the
7256          * corresponding interruptibility bits in the guest state. Otherwise
7257          * vmentry fails as it then expects bit 14 (BS) in pending debug
7258          * exceptions being set, but that's not correct for the guest debugging
7259          * case. */
7260         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7261                 vmx_set_interrupt_shadow(vcpu, 0);
7262
7263         atomic_switch_perf_msrs(vmx);
7264         debugctlmsr = get_debugctlmsr();
7265
7266         vmx->__launched = vmx->loaded_vmcs->launched;
7267         asm(
7268                 /* Store host registers */
7269                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7270                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7271                 "push %%" _ASM_CX " \n\t"
7272                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7273                 "je 1f \n\t"
7274                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7275                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7276                 "1: \n\t"
7277                 /* Reload cr2 if changed */
7278                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7279                 "mov %%cr2, %%" _ASM_DX " \n\t"
7280                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7281                 "je 2f \n\t"
7282                 "mov %%" _ASM_AX", %%cr2 \n\t"
7283                 "2: \n\t"
7284                 /* Check if vmlaunch of vmresume is needed */
7285                 "cmpl $0, %c[launched](%0) \n\t"
7286                 /* Load guest registers.  Don't clobber flags. */
7287                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7288                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7289                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7290                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7291                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7292                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7293 #ifdef CONFIG_X86_64
7294                 "mov %c[r8](%0),  %%r8  \n\t"
7295                 "mov %c[r9](%0),  %%r9  \n\t"
7296                 "mov %c[r10](%0), %%r10 \n\t"
7297                 "mov %c[r11](%0), %%r11 \n\t"
7298                 "mov %c[r12](%0), %%r12 \n\t"
7299                 "mov %c[r13](%0), %%r13 \n\t"
7300                 "mov %c[r14](%0), %%r14 \n\t"
7301                 "mov %c[r15](%0), %%r15 \n\t"
7302 #endif
7303                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7304
7305                 /* Enter guest mode */
7306                 "jne 1f \n\t"
7307                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7308                 "jmp 2f \n\t"
7309                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7310                 "2: "
7311                 /* Save guest registers, load host registers, keep flags */
7312                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7313                 "pop %0 \n\t"
7314                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7315                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7316                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7317                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7318                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7319                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7320                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7321 #ifdef CONFIG_X86_64
7322                 "mov %%r8,  %c[r8](%0) \n\t"
7323                 "mov %%r9,  %c[r9](%0) \n\t"
7324                 "mov %%r10, %c[r10](%0) \n\t"
7325                 "mov %%r11, %c[r11](%0) \n\t"
7326                 "mov %%r12, %c[r12](%0) \n\t"
7327                 "mov %%r13, %c[r13](%0) \n\t"
7328                 "mov %%r14, %c[r14](%0) \n\t"
7329                 "mov %%r15, %c[r15](%0) \n\t"
7330 #endif
7331                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7332                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7333
7334                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7335                 "setbe %c[fail](%0) \n\t"
7336                 ".pushsection .rodata \n\t"
7337                 ".global vmx_return \n\t"
7338                 "vmx_return: " _ASM_PTR " 2b \n\t"
7339                 ".popsection"
7340               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7341                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7342                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7343                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7344                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7345                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7346                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7347                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7348                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7349                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7350                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7351 #ifdef CONFIG_X86_64
7352                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7353                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7354                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7355                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7356                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7357                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7358                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7359                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7360 #endif
7361                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7362                 [wordsize]"i"(sizeof(ulong))
7363               : "cc", "memory"
7364 #ifdef CONFIG_X86_64
7365                 , "rax", "rbx", "rdi", "rsi"
7366                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7367 #else
7368                 , "eax", "ebx", "edi", "esi"
7369 #endif
7370               );
7371
7372         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7373         if (debugctlmsr)
7374                 update_debugctlmsr(debugctlmsr);
7375
7376 #ifndef CONFIG_X86_64
7377         /*
7378          * The sysexit path does not restore ds/es, so we must set them to
7379          * a reasonable value ourselves.
7380          *
7381          * We can't defer this to vmx_load_host_state() since that function
7382          * may be executed in interrupt context, which saves and restore segments
7383          * around it, nullifying its effect.
7384          */
7385         loadsegment(ds, __USER_DS);
7386         loadsegment(es, __USER_DS);
7387 #endif
7388
7389         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7390                                   | (1 << VCPU_EXREG_RFLAGS)
7391                                   | (1 << VCPU_EXREG_CPL)
7392                                   | (1 << VCPU_EXREG_PDPTR)
7393                                   | (1 << VCPU_EXREG_SEGMENTS)
7394                                   | (1 << VCPU_EXREG_CR3));
7395         vcpu->arch.regs_dirty = 0;
7396
7397         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7398
7399         vmx->loaded_vmcs->launched = 1;
7400
7401         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7402         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7403
7404         /*
7405          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7406          * we did not inject a still-pending event to L1 now because of
7407          * nested_run_pending, we need to re-enable this bit.
7408          */
7409         if (vmx->nested.nested_run_pending)
7410                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7411
7412         vmx->nested.nested_run_pending = 0;
7413
7414         vmx_complete_atomic_exit(vmx);
7415         vmx_recover_nmi_blocking(vmx);
7416         vmx_complete_interrupts(vmx);
7417 }
7418
7419 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7420 {
7421         struct vcpu_vmx *vmx = to_vmx(vcpu);
7422
7423         free_vpid(vmx);
7424         free_loaded_vmcs(vmx->loaded_vmcs);
7425         free_nested(vmx);
7426         kfree(vmx->guest_msrs);
7427         kvm_vcpu_uninit(vcpu);
7428         kmem_cache_free(kvm_vcpu_cache, vmx);
7429 }
7430
7431 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7432 {
7433         int err;
7434         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7435         int cpu;
7436
7437         if (!vmx)
7438                 return ERR_PTR(-ENOMEM);
7439
7440         allocate_vpid(vmx);
7441
7442         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7443         if (err)
7444                 goto free_vcpu;
7445
7446         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7447         err = -ENOMEM;
7448         if (!vmx->guest_msrs) {
7449                 goto uninit_vcpu;
7450         }
7451
7452         vmx->loaded_vmcs = &vmx->vmcs01;
7453         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7454         if (!vmx->loaded_vmcs->vmcs)
7455                 goto free_msrs;
7456         if (!vmm_exclusive)
7457                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7458         loaded_vmcs_init(vmx->loaded_vmcs);
7459         if (!vmm_exclusive)
7460                 kvm_cpu_vmxoff();
7461
7462         cpu = get_cpu();
7463         vmx_vcpu_load(&vmx->vcpu, cpu);
7464         vmx->vcpu.cpu = cpu;
7465         err = vmx_vcpu_setup(vmx);
7466         vmx_vcpu_put(&vmx->vcpu);
7467         put_cpu();
7468         if (err)
7469                 goto free_vmcs;
7470         if (vm_need_virtualize_apic_accesses(kvm)) {
7471                 err = alloc_apic_access_page(kvm);
7472                 if (err)
7473                         goto free_vmcs;
7474         }
7475
7476         if (enable_ept) {
7477                 if (!kvm->arch.ept_identity_map_addr)
7478                         kvm->arch.ept_identity_map_addr =
7479                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7480                 err = -ENOMEM;
7481                 if (alloc_identity_pagetable(kvm) != 0)
7482                         goto free_vmcs;
7483                 if (!init_rmode_identity_map(kvm))
7484                         goto free_vmcs;
7485         }
7486
7487         vmx->nested.current_vmptr = -1ull;
7488         vmx->nested.current_vmcs12 = NULL;
7489
7490         return &vmx->vcpu;
7491
7492 free_vmcs:
7493         free_loaded_vmcs(vmx->loaded_vmcs);
7494 free_msrs:
7495         kfree(vmx->guest_msrs);
7496 uninit_vcpu:
7497         kvm_vcpu_uninit(&vmx->vcpu);
7498 free_vcpu:
7499         free_vpid(vmx);
7500         kmem_cache_free(kvm_vcpu_cache, vmx);
7501         return ERR_PTR(err);
7502 }
7503
7504 static void __init vmx_check_processor_compat(void *rtn)
7505 {
7506         struct vmcs_config vmcs_conf;
7507
7508         *(int *)rtn = 0;
7509         if (setup_vmcs_config(&vmcs_conf) < 0)
7510                 *(int *)rtn = -EIO;
7511         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7512                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7513                                 smp_processor_id());
7514                 *(int *)rtn = -EIO;
7515         }
7516 }
7517
7518 static int get_ept_level(void)
7519 {
7520         return VMX_EPT_DEFAULT_GAW + 1;
7521 }
7522
7523 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7524 {
7525         u64 ret;
7526
7527         /* For VT-d and EPT combination
7528          * 1. MMIO: always map as UC
7529          * 2. EPT with VT-d:
7530          *   a. VT-d without snooping control feature: can't guarantee the
7531          *      result, try to trust guest.
7532          *   b. VT-d with snooping control feature: snooping control feature of
7533          *      VT-d engine can guarantee the cache correctness. Just set it
7534          *      to WB to keep consistent with host. So the same as item 3.
7535          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7536          *    consistent with host MTRR
7537          */
7538         if (is_mmio)
7539                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7540         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
7541                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7542                       VMX_EPT_MT_EPTE_SHIFT;
7543         else
7544                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7545                         | VMX_EPT_IPAT_BIT;
7546
7547         return ret;
7548 }
7549
7550 static int vmx_get_lpage_level(void)
7551 {
7552         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7553                 return PT_DIRECTORY_LEVEL;
7554         else
7555                 /* For shadow and EPT supported 1GB page */
7556                 return PT_PDPE_LEVEL;
7557 }
7558
7559 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7560 {
7561         struct kvm_cpuid_entry2 *best;
7562         struct vcpu_vmx *vmx = to_vmx(vcpu);
7563         u32 exec_control;
7564
7565         vmx->rdtscp_enabled = false;
7566         if (vmx_rdtscp_supported()) {
7567                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7568                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7569                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7570                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7571                                 vmx->rdtscp_enabled = true;
7572                         else {
7573                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7574                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7575                                                 exec_control);
7576                         }
7577                 }
7578         }
7579
7580         /* Exposing INVPCID only when PCID is exposed */
7581         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7582         if (vmx_invpcid_supported() &&
7583             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7584             guest_cpuid_has_pcid(vcpu)) {
7585                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7586                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7587                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7588                              exec_control);
7589         } else {
7590                 if (cpu_has_secondary_exec_ctrls()) {
7591                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7592                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7593                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7594                                      exec_control);
7595                 }
7596                 if (best)
7597                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7598         }
7599 }
7600
7601 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7602 {
7603         if (func == 1 && nested)
7604                 entry->ecx |= bit(X86_FEATURE_VMX);
7605 }
7606
7607 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7608                 struct x86_exception *fault)
7609 {
7610         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7611         u32 exit_reason;
7612
7613         if (fault->error_code & PFERR_RSVD_MASK)
7614                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
7615         else
7616                 exit_reason = EXIT_REASON_EPT_VIOLATION;
7617         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
7618         vmcs12->guest_physical_address = fault->address;
7619 }
7620
7621 /* Callbacks for nested_ept_init_mmu_context: */
7622
7623 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7624 {
7625         /* return the page table to be shadowed - in our case, EPT12 */
7626         return get_vmcs12(vcpu)->ept_pointer;
7627 }
7628
7629 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7630 {
7631         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7632                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7633
7634         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7635         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7636         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7637
7638         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7639 }
7640
7641 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7642 {
7643         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7644 }
7645
7646 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7647                 struct x86_exception *fault)
7648 {
7649         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7650
7651         WARN_ON(!is_guest_mode(vcpu));
7652
7653         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7654         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7655                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7656                                   vmcs_read32(VM_EXIT_INTR_INFO),
7657                                   vmcs_readl(EXIT_QUALIFICATION));
7658         else
7659                 kvm_inject_page_fault(vcpu, fault);
7660 }
7661
7662 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7663 {
7664         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7665         struct vcpu_vmx *vmx = to_vmx(vcpu);
7666
7667         if (vcpu->arch.virtual_tsc_khz == 0)
7668                 return;
7669
7670         /* Make sure short timeouts reliably trigger an immediate vmexit.
7671          * hrtimer_start does not guarantee this. */
7672         if (preemption_timeout <= 1) {
7673                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7674                 return;
7675         }
7676
7677         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7678         preemption_timeout *= 1000000;
7679         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7680         hrtimer_start(&vmx->nested.preemption_timer,
7681                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7682 }
7683
7684 /*
7685  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7686  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7687  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7688  * guest in a way that will both be appropriate to L1's requests, and our
7689  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7690  * function also has additional necessary side-effects, like setting various
7691  * vcpu->arch fields.
7692  */
7693 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7694 {
7695         struct vcpu_vmx *vmx = to_vmx(vcpu);
7696         u32 exec_control;
7697
7698         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7699         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7700         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7701         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7702         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7703         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7704         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7705         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7706         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7707         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7708         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7709         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7710         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7711         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7712         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7713         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7714         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7715         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7716         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7717         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7718         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7719         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7720         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7721         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7722         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7723         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7724         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7725         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7726         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7727         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7728         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7729         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7730         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7731         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7732         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7733         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7734
7735         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7736         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7737                 vmcs12->vm_entry_intr_info_field);
7738         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7739                 vmcs12->vm_entry_exception_error_code);
7740         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7741                 vmcs12->vm_entry_instruction_len);
7742         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7743                 vmcs12->guest_interruptibility_info);
7744         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7745         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7746         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7747         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7748                 vmcs12->guest_pending_dbg_exceptions);
7749         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7750         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7751
7752         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7753
7754         exec_control = vmcs12->pin_based_vm_exec_control;
7755         exec_control |= vmcs_config.pin_based_exec_ctrl;
7756         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7757         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
7758
7759         vmx->nested.preemption_timer_expired = false;
7760         if (nested_cpu_has_preemption_timer(vmcs12))
7761                 vmx_start_preemption_timer(vcpu);
7762
7763         /*
7764          * Whether page-faults are trapped is determined by a combination of
7765          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7766          * If enable_ept, L0 doesn't care about page faults and we should
7767          * set all of these to L1's desires. However, if !enable_ept, L0 does
7768          * care about (at least some) page faults, and because it is not easy
7769          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7770          * to exit on each and every L2 page fault. This is done by setting
7771          * MASK=MATCH=0 and (see below) EB.PF=1.
7772          * Note that below we don't need special code to set EB.PF beyond the
7773          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7774          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7775          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7776          *
7777          * A problem with this approach (when !enable_ept) is that L1 may be
7778          * injected with more page faults than it asked for. This could have
7779          * caused problems, but in practice existing hypervisors don't care.
7780          * To fix this, we will need to emulate the PFEC checking (on the L1
7781          * page tables), using walk_addr(), when injecting PFs to L1.
7782          */
7783         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7784                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7785         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7786                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7787
7788         if (cpu_has_secondary_exec_ctrls()) {
7789                 exec_control = vmx_secondary_exec_control(vmx);
7790                 if (!vmx->rdtscp_enabled)
7791                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7792                 /* Take the following fields only from vmcs12 */
7793                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7794                 if (nested_cpu_has(vmcs12,
7795                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7796                         exec_control |= vmcs12->secondary_vm_exec_control;
7797
7798                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7799                         /*
7800                          * Translate L1 physical address to host physical
7801                          * address for vmcs02. Keep the page pinned, so this
7802                          * physical address remains valid. We keep a reference
7803                          * to it so we can release it later.
7804                          */
7805                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7806                                 nested_release_page(vmx->nested.apic_access_page);
7807                         vmx->nested.apic_access_page =
7808                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7809                         /*
7810                          * If translation failed, no matter: This feature asks
7811                          * to exit when accessing the given address, and if it
7812                          * can never be accessed, this feature won't do
7813                          * anything anyway.
7814                          */
7815                         if (!vmx->nested.apic_access_page)
7816                                 exec_control &=
7817                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7818                         else
7819                                 vmcs_write64(APIC_ACCESS_ADDR,
7820                                   page_to_phys(vmx->nested.apic_access_page));
7821                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7822                         exec_control |=
7823                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7824                         vmcs_write64(APIC_ACCESS_ADDR,
7825                                 page_to_phys(vcpu->kvm->arch.apic_access_page));
7826                 }
7827
7828                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7829         }
7830
7831
7832         /*
7833          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7834          * Some constant fields are set here by vmx_set_constant_host_state().
7835          * Other fields are different per CPU, and will be set later when
7836          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7837          */
7838         vmx_set_constant_host_state(vmx);
7839
7840         /*
7841          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7842          * entry, but only if the current (host) sp changed from the value
7843          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7844          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7845          * here we just force the write to happen on entry.
7846          */
7847         vmx->host_rsp = 0;
7848
7849         exec_control = vmx_exec_control(vmx); /* L0's desires */
7850         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7851         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7852         exec_control &= ~CPU_BASED_TPR_SHADOW;
7853         exec_control |= vmcs12->cpu_based_vm_exec_control;
7854         /*
7855          * Merging of IO and MSR bitmaps not currently supported.
7856          * Rather, exit every time.
7857          */
7858         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7859         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7860         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7861
7862         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7863
7864         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7865          * bitwise-or of what L1 wants to trap for L2, and what we want to
7866          * trap. Note that CR0.TS also needs updating - we do this later.
7867          */
7868         update_exception_bitmap(vcpu);
7869         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7870         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7871
7872         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7873          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7874          * bits are further modified by vmx_set_efer() below.
7875          */
7876         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7877
7878         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7879          * emulated by vmx_set_efer(), below.
7880          */
7881         vm_entry_controls_init(vmx,
7882                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7883                         ~VM_ENTRY_IA32E_MODE) |
7884                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7885
7886         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7887                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7888                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7889         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7890                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7891
7892
7893         set_cr4_guest_host_mask(vmx);
7894
7895         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7896                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7897
7898         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7899                 vmcs_write64(TSC_OFFSET,
7900                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7901         else
7902                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7903
7904         if (enable_vpid) {
7905                 /*
7906                  * Trivially support vpid by letting L2s share their parent
7907                  * L1's vpid. TODO: move to a more elaborate solution, giving
7908                  * each L2 its own vpid and exposing the vpid feature to L1.
7909                  */
7910                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7911                 vmx_flush_tlb(vcpu);
7912         }
7913
7914         if (nested_cpu_has_ept(vmcs12)) {
7915                 kvm_mmu_unload(vcpu);
7916                 nested_ept_init_mmu_context(vcpu);
7917         }
7918
7919         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7920                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7921         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7922                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7923         else
7924                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7925         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7926         vmx_set_efer(vcpu, vcpu->arch.efer);
7927
7928         /*
7929          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7930          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7931          * The CR0_READ_SHADOW is what L2 should have expected to read given
7932          * the specifications by L1; It's not enough to take
7933          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7934          * have more bits than L1 expected.
7935          */
7936         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7937         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7938
7939         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7940         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7941
7942         /* shadow page tables on either EPT or shadow page tables */
7943         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7944         kvm_mmu_reset_context(vcpu);
7945
7946         if (!enable_ept)
7947                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7948
7949         /*
7950          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7951          */
7952         if (enable_ept) {
7953                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7954                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7955                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7956                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7957         }
7958
7959         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7960         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7961 }
7962
7963 /*
7964  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7965  * for running an L2 nested guest.
7966  */
7967 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7968 {
7969         struct vmcs12 *vmcs12;
7970         struct vcpu_vmx *vmx = to_vmx(vcpu);
7971         int cpu;
7972         struct loaded_vmcs *vmcs02;
7973         bool ia32e;
7974
7975         if (!nested_vmx_check_permission(vcpu) ||
7976             !nested_vmx_check_vmcs12(vcpu))
7977                 return 1;
7978
7979         skip_emulated_instruction(vcpu);
7980         vmcs12 = get_vmcs12(vcpu);
7981
7982         if (enable_shadow_vmcs)
7983                 copy_shadow_to_vmcs12(vmx);
7984
7985         /*
7986          * The nested entry process starts with enforcing various prerequisites
7987          * on vmcs12 as required by the Intel SDM, and act appropriately when
7988          * they fail: As the SDM explains, some conditions should cause the
7989          * instruction to fail, while others will cause the instruction to seem
7990          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7991          * To speed up the normal (success) code path, we should avoid checking
7992          * for misconfigurations which will anyway be caught by the processor
7993          * when using the merged vmcs02.
7994          */
7995         if (vmcs12->launch_state == launch) {
7996                 nested_vmx_failValid(vcpu,
7997                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7998                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7999                 return 1;
8000         }
8001
8002         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8003             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
8004                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8005                 return 1;
8006         }
8007
8008         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8009                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
8010                 /*TODO: Also verify bits beyond physical address width are 0*/
8011                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8012                 return 1;
8013         }
8014
8015         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8016                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
8017                 /*TODO: Also verify bits beyond physical address width are 0*/
8018                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8019                 return 1;
8020         }
8021
8022         if (vmcs12->vm_entry_msr_load_count > 0 ||
8023             vmcs12->vm_exit_msr_load_count > 0 ||
8024             vmcs12->vm_exit_msr_store_count > 0) {
8025                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8026                                     __func__);
8027                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8028                 return 1;
8029         }
8030
8031         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8032               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8033             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8034               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8035             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8036               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8037             !vmx_control_verify(vmcs12->vm_exit_controls,
8038               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8039             !vmx_control_verify(vmcs12->vm_entry_controls,
8040               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8041         {
8042                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8043                 return 1;
8044         }
8045
8046         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8047             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8048                 nested_vmx_failValid(vcpu,
8049                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8050                 return 1;
8051         }
8052
8053         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8054             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8055                 nested_vmx_entry_failure(vcpu, vmcs12,
8056                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8057                 return 1;
8058         }
8059         if (vmcs12->vmcs_link_pointer != -1ull) {
8060                 nested_vmx_entry_failure(vcpu, vmcs12,
8061                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8062                 return 1;
8063         }
8064
8065         /*
8066          * If the load IA32_EFER VM-entry control is 1, the following checks
8067          * are performed on the field for the IA32_EFER MSR:
8068          * - Bits reserved in the IA32_EFER MSR must be 0.
8069          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8070          *   the IA-32e mode guest VM-exit control. It must also be identical
8071          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8072          *   CR0.PG) is 1.
8073          */
8074         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8075                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8076                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8077                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8078                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8079                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8080                         nested_vmx_entry_failure(vcpu, vmcs12,
8081                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8082                         return 1;
8083                 }
8084         }
8085
8086         /*
8087          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8088          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8089          * the values of the LMA and LME bits in the field must each be that of
8090          * the host address-space size VM-exit control.
8091          */
8092         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8093                 ia32e = (vmcs12->vm_exit_controls &
8094                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8095                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8096                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8097                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8098                         nested_vmx_entry_failure(vcpu, vmcs12,
8099                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8100                         return 1;
8101                 }
8102         }
8103
8104         /*
8105          * We're finally done with prerequisite checking, and can start with
8106          * the nested entry.
8107          */
8108
8109         vmcs02 = nested_get_current_vmcs02(vmx);
8110         if (!vmcs02)
8111                 return -ENOMEM;
8112
8113         enter_guest_mode(vcpu);
8114
8115         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8116
8117         cpu = get_cpu();
8118         vmx->loaded_vmcs = vmcs02;
8119         vmx_vcpu_put(vcpu);
8120         vmx_vcpu_load(vcpu, cpu);
8121         vcpu->cpu = cpu;
8122         put_cpu();
8123
8124         vmx_segment_cache_clear(vmx);
8125
8126         vmcs12->launch_state = 1;
8127
8128         prepare_vmcs02(vcpu, vmcs12);
8129
8130         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8131                 return kvm_emulate_halt(vcpu);
8132
8133         vmx->nested.nested_run_pending = 1;
8134
8135         /*
8136          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8137          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8138          * returned as far as L1 is concerned. It will only return (and set
8139          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8140          */
8141         return 1;
8142 }
8143
8144 /*
8145  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8146  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8147  * This function returns the new value we should put in vmcs12.guest_cr0.
8148  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8149  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8150  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8151  *     didn't trap the bit, because if L1 did, so would L0).
8152  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8153  *     been modified by L2, and L1 knows it. So just leave the old value of
8154  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8155  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8156  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8157  *     changed these bits, and therefore they need to be updated, but L0
8158  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8159  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8160  */
8161 static inline unsigned long
8162 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8163 {
8164         return
8165         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8166         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8167         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8168                         vcpu->arch.cr0_guest_owned_bits));
8169 }
8170
8171 static inline unsigned long
8172 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8173 {
8174         return
8175         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8176         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8177         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8178                         vcpu->arch.cr4_guest_owned_bits));
8179 }
8180
8181 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8182                                        struct vmcs12 *vmcs12)
8183 {
8184         u32 idt_vectoring;
8185         unsigned int nr;
8186
8187         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8188                 nr = vcpu->arch.exception.nr;
8189                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8190
8191                 if (kvm_exception_is_soft(nr)) {
8192                         vmcs12->vm_exit_instruction_len =
8193                                 vcpu->arch.event_exit_inst_len;
8194                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8195                 } else
8196                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8197
8198                 if (vcpu->arch.exception.has_error_code) {
8199                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8200                         vmcs12->idt_vectoring_error_code =
8201                                 vcpu->arch.exception.error_code;
8202                 }
8203
8204                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8205         } else if (vcpu->arch.nmi_injected) {
8206                 vmcs12->idt_vectoring_info_field =
8207                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8208         } else if (vcpu->arch.interrupt.pending) {
8209                 nr = vcpu->arch.interrupt.nr;
8210                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8211
8212                 if (vcpu->arch.interrupt.soft) {
8213                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8214                         vmcs12->vm_entry_instruction_len =
8215                                 vcpu->arch.event_exit_inst_len;
8216                 } else
8217                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8218
8219                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8220         }
8221 }
8222
8223 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8224 {
8225         struct vcpu_vmx *vmx = to_vmx(vcpu);
8226
8227         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8228             vmx->nested.preemption_timer_expired) {
8229                 if (vmx->nested.nested_run_pending)
8230                         return -EBUSY;
8231                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8232                 return 0;
8233         }
8234
8235         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8236                 if (vmx->nested.nested_run_pending ||
8237                     vcpu->arch.interrupt.pending)
8238                         return -EBUSY;
8239                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8240                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8241                                   INTR_INFO_VALID_MASK, 0);
8242                 /*
8243                  * The NMI-triggered VM exit counts as injection:
8244                  * clear this one and block further NMIs.
8245                  */
8246                 vcpu->arch.nmi_pending = 0;
8247                 vmx_set_nmi_mask(vcpu, true);
8248                 return 0;
8249         }
8250
8251         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8252             nested_exit_on_intr(vcpu)) {
8253                 if (vmx->nested.nested_run_pending)
8254                         return -EBUSY;
8255                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8256         }
8257
8258         return 0;
8259 }
8260
8261 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8262 {
8263         ktime_t remaining =
8264                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8265         u64 value;
8266
8267         if (ktime_to_ns(remaining) <= 0)
8268                 return 0;
8269
8270         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8271         do_div(value, 1000000);
8272         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8273 }
8274
8275 /*
8276  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8277  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8278  * and this function updates it to reflect the changes to the guest state while
8279  * L2 was running (and perhaps made some exits which were handled directly by L0
8280  * without going back to L1), and to reflect the exit reason.
8281  * Note that we do not have to copy here all VMCS fields, just those that
8282  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8283  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8284  * which already writes to vmcs12 directly.
8285  */
8286 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8287                            u32 exit_reason, u32 exit_intr_info,
8288                            unsigned long exit_qualification)
8289 {
8290         /* update guest state fields: */
8291         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8292         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8293
8294         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8295         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8296         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8297         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8298
8299         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8300         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8301         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8302         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8303         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8304         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8305         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8306         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8307         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8308         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8309         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8310         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8311         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8312         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8313         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8314         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8315         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8316         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8317         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8318         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8319         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8320         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8321         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8322         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8323         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8324         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8325         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8326         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8327         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8328         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8329         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8330         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8331         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8332         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8333         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8334         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8335
8336         vmcs12->guest_interruptibility_info =
8337                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8338         vmcs12->guest_pending_dbg_exceptions =
8339                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8340         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8341                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8342         else
8343                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8344
8345         if (nested_cpu_has_preemption_timer(vmcs12)) {
8346                 if (vmcs12->vm_exit_controls &
8347                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8348                         vmcs12->vmx_preemption_timer_value =
8349                                 vmx_get_preemption_timer_value(vcpu);
8350                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8351         }
8352
8353         /*
8354          * In some cases (usually, nested EPT), L2 is allowed to change its
8355          * own CR3 without exiting. If it has changed it, we must keep it.
8356          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8357          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8358          *
8359          * Additionally, restore L2's PDPTR to vmcs12.
8360          */
8361         if (enable_ept) {
8362                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8363                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8364                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8365                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8366                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8367         }
8368
8369         vmcs12->vm_entry_controls =
8370                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8371                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8372
8373         /* TODO: These cannot have changed unless we have MSR bitmaps and
8374          * the relevant bit asks not to trap the change */
8375         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8376         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8377                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8378         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8379                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8380         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8381         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8382         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8383         if (vmx_mpx_supported())
8384                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8385
8386         /* update exit information fields: */
8387
8388         vmcs12->vm_exit_reason = exit_reason;
8389         vmcs12->exit_qualification = exit_qualification;
8390
8391         vmcs12->vm_exit_intr_info = exit_intr_info;
8392         if ((vmcs12->vm_exit_intr_info &
8393              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8394             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8395                 vmcs12->vm_exit_intr_error_code =
8396                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8397         vmcs12->idt_vectoring_info_field = 0;
8398         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8399         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8400
8401         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8402                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8403                  * instead of reading the real value. */
8404                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8405
8406                 /*
8407                  * Transfer the event that L0 or L1 may wanted to inject into
8408                  * L2 to IDT_VECTORING_INFO_FIELD.
8409                  */
8410                 vmcs12_save_pending_event(vcpu, vmcs12);
8411         }
8412
8413         /*
8414          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8415          * preserved above and would only end up incorrectly in L1.
8416          */
8417         vcpu->arch.nmi_injected = false;
8418         kvm_clear_exception_queue(vcpu);
8419         kvm_clear_interrupt_queue(vcpu);
8420 }
8421
8422 /*
8423  * A part of what we need to when the nested L2 guest exits and we want to
8424  * run its L1 parent, is to reset L1's guest state to the host state specified
8425  * in vmcs12.
8426  * This function is to be called not only on normal nested exit, but also on
8427  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8428  * Failures During or After Loading Guest State").
8429  * This function should be called when the active VMCS is L1's (vmcs01).
8430  */
8431 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8432                                    struct vmcs12 *vmcs12)
8433 {
8434         struct kvm_segment seg;
8435
8436         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8437                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8438         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8439                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8440         else
8441                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8442         vmx_set_efer(vcpu, vcpu->arch.efer);
8443
8444         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8445         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8446         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8447         /*
8448          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8449          * actually changed, because it depends on the current state of
8450          * fpu_active (which may have changed).
8451          * Note that vmx_set_cr0 refers to efer set above.
8452          */
8453         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8454         /*
8455          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8456          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8457          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8458          */
8459         update_exception_bitmap(vcpu);
8460         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8461         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8462
8463         /*
8464          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8465          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8466          */
8467         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8468         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8469
8470         nested_ept_uninit_mmu_context(vcpu);
8471
8472         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8473         kvm_mmu_reset_context(vcpu);
8474
8475         if (!enable_ept)
8476                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8477
8478         if (enable_vpid) {
8479                 /*
8480                  * Trivially support vpid by letting L2s share their parent
8481                  * L1's vpid. TODO: move to a more elaborate solution, giving
8482                  * each L2 its own vpid and exposing the vpid feature to L1.
8483                  */
8484                 vmx_flush_tlb(vcpu);
8485         }
8486
8487
8488         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8489         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8490         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8491         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8492         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8493
8494         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
8495         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8496                 vmcs_write64(GUEST_BNDCFGS, 0);
8497
8498         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8499                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8500                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8501         }
8502         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8503                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8504                         vmcs12->host_ia32_perf_global_ctrl);
8505
8506         /* Set L1 segment info according to Intel SDM
8507             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8508         seg = (struct kvm_segment) {
8509                 .base = 0,
8510                 .limit = 0xFFFFFFFF,
8511                 .selector = vmcs12->host_cs_selector,
8512                 .type = 11,
8513                 .present = 1,
8514                 .s = 1,
8515                 .g = 1
8516         };
8517         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8518                 seg.l = 1;
8519         else
8520                 seg.db = 1;
8521         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8522         seg = (struct kvm_segment) {
8523                 .base = 0,
8524                 .limit = 0xFFFFFFFF,
8525                 .type = 3,
8526                 .present = 1,
8527                 .s = 1,
8528                 .db = 1,
8529                 .g = 1
8530         };
8531         seg.selector = vmcs12->host_ds_selector;
8532         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8533         seg.selector = vmcs12->host_es_selector;
8534         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8535         seg.selector = vmcs12->host_ss_selector;
8536         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8537         seg.selector = vmcs12->host_fs_selector;
8538         seg.base = vmcs12->host_fs_base;
8539         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8540         seg.selector = vmcs12->host_gs_selector;
8541         seg.base = vmcs12->host_gs_base;
8542         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8543         seg = (struct kvm_segment) {
8544                 .base = vmcs12->host_tr_base,
8545                 .limit = 0x67,
8546                 .selector = vmcs12->host_tr_selector,
8547                 .type = 11,
8548                 .present = 1
8549         };
8550         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8551
8552         kvm_set_dr(vcpu, 7, 0x400);
8553         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8554 }
8555
8556 /*
8557  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8558  * and modify vmcs12 to make it see what it would expect to see there if
8559  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8560  */
8561 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8562                               u32 exit_intr_info,
8563                               unsigned long exit_qualification)
8564 {
8565         struct vcpu_vmx *vmx = to_vmx(vcpu);
8566         int cpu;
8567         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8568
8569         /* trying to cancel vmlaunch/vmresume is a bug */
8570         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8571
8572         leave_guest_mode(vcpu);
8573         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8574                        exit_qualification);
8575
8576         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8577             && nested_exit_intr_ack_set(vcpu)) {
8578                 int irq = kvm_cpu_get_interrupt(vcpu);
8579                 WARN_ON(irq < 0);
8580                 vmcs12->vm_exit_intr_info = irq |
8581                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8582         }
8583
8584         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8585                                        vmcs12->exit_qualification,
8586                                        vmcs12->idt_vectoring_info_field,
8587                                        vmcs12->vm_exit_intr_info,
8588                                        vmcs12->vm_exit_intr_error_code,
8589                                        KVM_ISA_VMX);
8590
8591         cpu = get_cpu();
8592         vmx->loaded_vmcs = &vmx->vmcs01;
8593         vmx_vcpu_put(vcpu);
8594         vmx_vcpu_load(vcpu, cpu);
8595         vcpu->cpu = cpu;
8596         put_cpu();
8597
8598         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8599         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
8600         vmx_segment_cache_clear(vmx);
8601
8602         /* if no vmcs02 cache requested, remove the one we used */
8603         if (VMCS02_POOL_SIZE == 0)
8604                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8605
8606         load_vmcs12_host_state(vcpu, vmcs12);
8607
8608         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8609         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8610
8611         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8612         vmx->host_rsp = 0;
8613
8614         /* Unpin physical memory we referred to in vmcs02 */
8615         if (vmx->nested.apic_access_page) {
8616                 nested_release_page(vmx->nested.apic_access_page);
8617                 vmx->nested.apic_access_page = 0;
8618         }
8619
8620         /*
8621          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8622          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8623          * success or failure flag accordingly.
8624          */
8625         if (unlikely(vmx->fail)) {
8626                 vmx->fail = 0;
8627                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8628         } else
8629                 nested_vmx_succeed(vcpu);
8630         if (enable_shadow_vmcs)
8631                 vmx->nested.sync_shadow_vmcs = true;
8632
8633         /* in case we halted in L2 */
8634         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8635 }
8636
8637 /*
8638  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8639  */
8640 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8641 {
8642         if (is_guest_mode(vcpu))
8643                 nested_vmx_vmexit(vcpu, -1, 0, 0);
8644         free_nested(to_vmx(vcpu));
8645 }
8646
8647 /*
8648  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8649  * 23.7 "VM-entry failures during or after loading guest state" (this also
8650  * lists the acceptable exit-reason and exit-qualification parameters).
8651  * It should only be called before L2 actually succeeded to run, and when
8652  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8653  */
8654 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8655                         struct vmcs12 *vmcs12,
8656                         u32 reason, unsigned long qualification)
8657 {
8658         load_vmcs12_host_state(vcpu, vmcs12);
8659         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8660         vmcs12->exit_qualification = qualification;
8661         nested_vmx_succeed(vcpu);
8662         if (enable_shadow_vmcs)
8663                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8664 }
8665
8666 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8667                                struct x86_instruction_info *info,
8668                                enum x86_intercept_stage stage)
8669 {
8670         return X86EMUL_CONTINUE;
8671 }
8672
8673 static struct kvm_x86_ops vmx_x86_ops = {
8674         .cpu_has_kvm_support = cpu_has_kvm_support,
8675         .disabled_by_bios = vmx_disabled_by_bios,
8676         .hardware_setup = hardware_setup,
8677         .hardware_unsetup = hardware_unsetup,
8678         .check_processor_compatibility = vmx_check_processor_compat,
8679         .hardware_enable = hardware_enable,
8680         .hardware_disable = hardware_disable,
8681         .cpu_has_accelerated_tpr = report_flexpriority,
8682
8683         .vcpu_create = vmx_create_vcpu,
8684         .vcpu_free = vmx_free_vcpu,
8685         .vcpu_reset = vmx_vcpu_reset,
8686
8687         .prepare_guest_switch = vmx_save_host_state,
8688         .vcpu_load = vmx_vcpu_load,
8689         .vcpu_put = vmx_vcpu_put,
8690
8691         .update_db_bp_intercept = update_exception_bitmap,
8692         .get_msr = vmx_get_msr,
8693         .set_msr = vmx_set_msr,
8694         .get_segment_base = vmx_get_segment_base,
8695         .get_segment = vmx_get_segment,
8696         .set_segment = vmx_set_segment,
8697         .get_cpl = vmx_get_cpl,
8698         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8699         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8700         .decache_cr3 = vmx_decache_cr3,
8701         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8702         .set_cr0 = vmx_set_cr0,
8703         .set_cr3 = vmx_set_cr3,
8704         .set_cr4 = vmx_set_cr4,
8705         .set_efer = vmx_set_efer,
8706         .get_idt = vmx_get_idt,
8707         .set_idt = vmx_set_idt,
8708         .get_gdt = vmx_get_gdt,
8709         .set_gdt = vmx_set_gdt,
8710         .get_dr6 = vmx_get_dr6,
8711         .set_dr6 = vmx_set_dr6,
8712         .set_dr7 = vmx_set_dr7,
8713         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
8714         .cache_reg = vmx_cache_reg,
8715         .get_rflags = vmx_get_rflags,
8716         .set_rflags = vmx_set_rflags,
8717         .fpu_activate = vmx_fpu_activate,
8718         .fpu_deactivate = vmx_fpu_deactivate,
8719
8720         .tlb_flush = vmx_flush_tlb,
8721
8722         .run = vmx_vcpu_run,
8723         .handle_exit = vmx_handle_exit,
8724         .skip_emulated_instruction = skip_emulated_instruction,
8725         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8726         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8727         .patch_hypercall = vmx_patch_hypercall,
8728         .set_irq = vmx_inject_irq,
8729         .set_nmi = vmx_inject_nmi,
8730         .queue_exception = vmx_queue_exception,
8731         .cancel_injection = vmx_cancel_injection,
8732         .interrupt_allowed = vmx_interrupt_allowed,
8733         .nmi_allowed = vmx_nmi_allowed,
8734         .get_nmi_mask = vmx_get_nmi_mask,
8735         .set_nmi_mask = vmx_set_nmi_mask,
8736         .enable_nmi_window = enable_nmi_window,
8737         .enable_irq_window = enable_irq_window,
8738         .update_cr8_intercept = update_cr8_intercept,
8739         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8740         .vm_has_apicv = vmx_vm_has_apicv,
8741         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8742         .hwapic_irr_update = vmx_hwapic_irr_update,
8743         .hwapic_isr_update = vmx_hwapic_isr_update,
8744         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8745         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8746
8747         .set_tss_addr = vmx_set_tss_addr,
8748         .get_tdp_level = get_ept_level,
8749         .get_mt_mask = vmx_get_mt_mask,
8750
8751         .get_exit_info = vmx_get_exit_info,
8752
8753         .get_lpage_level = vmx_get_lpage_level,
8754
8755         .cpuid_update = vmx_cpuid_update,
8756
8757         .rdtscp_supported = vmx_rdtscp_supported,
8758         .invpcid_supported = vmx_invpcid_supported,
8759
8760         .set_supported_cpuid = vmx_set_supported_cpuid,
8761
8762         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8763
8764         .set_tsc_khz = vmx_set_tsc_khz,
8765         .read_tsc_offset = vmx_read_tsc_offset,
8766         .write_tsc_offset = vmx_write_tsc_offset,
8767         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8768         .compute_tsc_offset = vmx_compute_tsc_offset,
8769         .read_l1_tsc = vmx_read_l1_tsc,
8770
8771         .set_tdp_cr3 = vmx_set_cr3,
8772
8773         .check_intercept = vmx_check_intercept,
8774         .handle_external_intr = vmx_handle_external_intr,
8775         .mpx_supported = vmx_mpx_supported,
8776
8777         .check_nested_events = vmx_check_nested_events,
8778 };
8779
8780 static int __init vmx_init(void)
8781 {
8782         int r, i, msr;
8783
8784         rdmsrl_safe(MSR_EFER, &host_efer);
8785
8786         for (i = 0; i < NR_VMX_MSR; ++i)
8787                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8788
8789         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8790         if (!vmx_io_bitmap_a)
8791                 return -ENOMEM;
8792
8793         r = -ENOMEM;
8794
8795         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8796         if (!vmx_io_bitmap_b)
8797                 goto out;
8798
8799         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8800         if (!vmx_msr_bitmap_legacy)
8801                 goto out1;
8802
8803         vmx_msr_bitmap_legacy_x2apic =
8804                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8805         if (!vmx_msr_bitmap_legacy_x2apic)
8806                 goto out2;
8807
8808         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8809         if (!vmx_msr_bitmap_longmode)
8810                 goto out3;
8811
8812         vmx_msr_bitmap_longmode_x2apic =
8813                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8814         if (!vmx_msr_bitmap_longmode_x2apic)
8815                 goto out4;
8816         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8817         if (!vmx_vmread_bitmap)
8818                 goto out5;
8819
8820         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8821         if (!vmx_vmwrite_bitmap)
8822                 goto out6;
8823
8824         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8825         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8826         /* shadowed read/write fields */
8827         for (i = 0; i < max_shadow_read_write_fields; i++) {
8828                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8829                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8830         }
8831         /* shadowed read only fields */
8832         for (i = 0; i < max_shadow_read_only_fields; i++)
8833                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8834
8835         /*
8836          * Allow direct access to the PC debug port (it is often used for I/O
8837          * delays, but the vmexits simply slow things down).
8838          */
8839         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8840         clear_bit(0x80, vmx_io_bitmap_a);
8841
8842         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8843
8844         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8845         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8846
8847         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8848
8849         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8850                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8851         if (r)
8852                 goto out7;
8853
8854 #ifdef CONFIG_KEXEC
8855         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8856                            crash_vmclear_local_loaded_vmcss);
8857 #endif
8858
8859         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8860         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8861         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8862         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8863         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8864         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8865         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8866
8867         memcpy(vmx_msr_bitmap_legacy_x2apic,
8868                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8869         memcpy(vmx_msr_bitmap_longmode_x2apic,
8870                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8871
8872         if (enable_apicv) {
8873                 for (msr = 0x800; msr <= 0x8ff; msr++)
8874                         vmx_disable_intercept_msr_read_x2apic(msr);
8875
8876                 /* According SDM, in x2apic mode, the whole id reg is used.
8877                  * But in KVM, it only use the highest eight bits. Need to
8878                  * intercept it */
8879                 vmx_enable_intercept_msr_read_x2apic(0x802);
8880                 /* TMCCT */
8881                 vmx_enable_intercept_msr_read_x2apic(0x839);
8882                 /* TPR */
8883                 vmx_disable_intercept_msr_write_x2apic(0x808);
8884                 /* EOI */
8885                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8886                 /* SELF-IPI */
8887                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8888         }
8889
8890         if (enable_ept) {
8891                 kvm_mmu_set_mask_ptes(0ull,
8892                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8893                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8894                         0ull, VMX_EPT_EXECUTABLE_MASK);
8895                 ept_set_mmio_spte_mask();
8896                 kvm_enable_tdp();
8897         } else
8898                 kvm_disable_tdp();
8899
8900         return 0;
8901
8902 out7:
8903         free_page((unsigned long)vmx_vmwrite_bitmap);
8904 out6:
8905         free_page((unsigned long)vmx_vmread_bitmap);
8906 out5:
8907         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8908 out4:
8909         free_page((unsigned long)vmx_msr_bitmap_longmode);
8910 out3:
8911         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8912 out2:
8913         free_page((unsigned long)vmx_msr_bitmap_legacy);
8914 out1:
8915         free_page((unsigned long)vmx_io_bitmap_b);
8916 out:
8917         free_page((unsigned long)vmx_io_bitmap_a);
8918         return r;
8919 }
8920
8921 static void __exit vmx_exit(void)
8922 {
8923         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8924         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8925         free_page((unsigned long)vmx_msr_bitmap_legacy);
8926         free_page((unsigned long)vmx_msr_bitmap_longmode);
8927         free_page((unsigned long)vmx_io_bitmap_b);
8928         free_page((unsigned long)vmx_io_bitmap_a);
8929         free_page((unsigned long)vmx_vmwrite_bitmap);
8930         free_page((unsigned long)vmx_vmread_bitmap);
8931
8932 #ifdef CONFIG_KEXEC
8933         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8934         synchronize_rcu();
8935 #endif
8936
8937         kvm_exit();
8938 }
8939
8940 module_init(vmx_init)
8941 module_exit(vmx_exit)