2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/trace_events.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
42 #include <asm/virtext.h>
44 #include <asm/fpu/internal.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
49 #include <asm/irq_remapping.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
55 #define __ex_clear(x, reg) \
56 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
58 MODULE_AUTHOR("Qumranet");
59 MODULE_LICENSE("GPL");
61 static const struct x86_cpu_id vmx_cpu_id[] = {
62 X86_FEATURE_MATCH(X86_FEATURE_VMX),
65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
67 static bool __read_mostly enable_vpid = 1;
68 module_param_named(vpid, enable_vpid, bool, 0444);
70 static bool __read_mostly flexpriority_enabled = 1;
71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
73 static bool __read_mostly enable_ept = 1;
74 module_param_named(ept, enable_ept, bool, S_IRUGO);
76 static bool __read_mostly enable_unrestricted_guest = 1;
77 module_param_named(unrestricted_guest,
78 enable_unrestricted_guest, bool, S_IRUGO);
80 static bool __read_mostly enable_ept_ad_bits = 1;
81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
83 static bool __read_mostly emulate_invalid_guest_state = true;
84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
86 static bool __read_mostly vmm_exclusive = 1;
87 module_param(vmm_exclusive, bool, S_IRUGO);
89 static bool __read_mostly fasteoi = 1;
90 module_param(fasteoi, bool, S_IRUGO);
92 static bool __read_mostly enable_apicv = 1;
93 module_param(enable_apicv, bool, S_IRUGO);
95 static bool __read_mostly enable_shadow_vmcs = 1;
96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested = 0;
103 module_param(nested, bool, S_IRUGO);
105 static u64 __read_mostly host_xss;
107 static bool __read_mostly enable_pml = 1;
108 module_param_named(pml, enable_pml, bool, S_IRUGO);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
114 #define KVM_VM_CR0_ALWAYS_ON \
115 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
116 #define KVM_CR4_GUEST_OWNED_BITS \
117 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
118 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
128 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
129 * ple_gap: upper bound on the amount of time between two successive
130 * executions of PAUSE in a loop. Also indicate if ple enabled.
131 * According to test, this time is usually smaller than 128 cycles.
132 * ple_window: upper bound on the amount of time a guest is allowed to execute
133 * in a PAUSE loop. Tests indicate that most spinlocks are held for
134 * less than 2^12 cycles
135 * Time is measured based on a counter that runs at the same rate as the TSC,
136 * refer SDM volume 3b section 21.6.13 & 22.1.3.
138 #define KVM_VMX_DEFAULT_PLE_GAP 128
139 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
143 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
146 module_param(ple_gap, int, S_IRUGO);
148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
149 module_param(ple_window, int, S_IRUGO);
151 /* Default doubles per-vcpu window every exit. */
152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
153 module_param(ple_window_grow, int, S_IRUGO);
155 /* Default resets per-vcpu window every exit to ple_window. */
156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
157 module_param(ple_window_shrink, int, S_IRUGO);
159 /* Default is to compute the maximum so we can never overflow. */
160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
161 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
162 module_param(ple_window_max, int, S_IRUGO);
164 extern const ulong vmx_return;
166 #define NR_AUTOLOAD_MSRS 8
167 #define VMCS02_POOL_SIZE 1
176 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
177 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
178 * loaded on this CPU (so we can clear them if the CPU goes down).
184 struct list_head loaded_vmcss_on_cpu_link;
187 struct shared_msr_entry {
194 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
195 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
196 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
197 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
198 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
199 * More than one of these structures may exist, if L1 runs multiple L2 guests.
200 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
201 * underlying hardware which will be used to run L2.
202 * This structure is packed to ensure that its layout is identical across
203 * machines (necessary for live migration).
204 * If there are changes in this struct, VMCS12_REVISION must be changed.
206 typedef u64 natural_width;
207 struct __packed vmcs12 {
208 /* According to the Intel spec, a VMCS region must start with the
209 * following two fields. Then follow implementation-specific data.
214 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
215 u32 padding[7]; /* room for future expansion */
220 u64 vm_exit_msr_store_addr;
221 u64 vm_exit_msr_load_addr;
222 u64 vm_entry_msr_load_addr;
224 u64 virtual_apic_page_addr;
225 u64 apic_access_addr;
226 u64 posted_intr_desc_addr;
228 u64 eoi_exit_bitmap0;
229 u64 eoi_exit_bitmap1;
230 u64 eoi_exit_bitmap2;
231 u64 eoi_exit_bitmap3;
233 u64 guest_physical_address;
234 u64 vmcs_link_pointer;
235 u64 guest_ia32_debugctl;
238 u64 guest_ia32_perf_global_ctrl;
246 u64 host_ia32_perf_global_ctrl;
247 u64 padding64[8]; /* room for future expansion */
249 * To allow migration of L1 (complete with its L2 guests) between
250 * machines of different natural widths (32 or 64 bit), we cannot have
251 * unsigned long fields with no explict size. We use u64 (aliased
252 * natural_width) instead. Luckily, x86 is little-endian.
254 natural_width cr0_guest_host_mask;
255 natural_width cr4_guest_host_mask;
256 natural_width cr0_read_shadow;
257 natural_width cr4_read_shadow;
258 natural_width cr3_target_value0;
259 natural_width cr3_target_value1;
260 natural_width cr3_target_value2;
261 natural_width cr3_target_value3;
262 natural_width exit_qualification;
263 natural_width guest_linear_address;
264 natural_width guest_cr0;
265 natural_width guest_cr3;
266 natural_width guest_cr4;
267 natural_width guest_es_base;
268 natural_width guest_cs_base;
269 natural_width guest_ss_base;
270 natural_width guest_ds_base;
271 natural_width guest_fs_base;
272 natural_width guest_gs_base;
273 natural_width guest_ldtr_base;
274 natural_width guest_tr_base;
275 natural_width guest_gdtr_base;
276 natural_width guest_idtr_base;
277 natural_width guest_dr7;
278 natural_width guest_rsp;
279 natural_width guest_rip;
280 natural_width guest_rflags;
281 natural_width guest_pending_dbg_exceptions;
282 natural_width guest_sysenter_esp;
283 natural_width guest_sysenter_eip;
284 natural_width host_cr0;
285 natural_width host_cr3;
286 natural_width host_cr4;
287 natural_width host_fs_base;
288 natural_width host_gs_base;
289 natural_width host_tr_base;
290 natural_width host_gdtr_base;
291 natural_width host_idtr_base;
292 natural_width host_ia32_sysenter_esp;
293 natural_width host_ia32_sysenter_eip;
294 natural_width host_rsp;
295 natural_width host_rip;
296 natural_width paddingl[8]; /* room for future expansion */
297 u32 pin_based_vm_exec_control;
298 u32 cpu_based_vm_exec_control;
299 u32 exception_bitmap;
300 u32 page_fault_error_code_mask;
301 u32 page_fault_error_code_match;
302 u32 cr3_target_count;
303 u32 vm_exit_controls;
304 u32 vm_exit_msr_store_count;
305 u32 vm_exit_msr_load_count;
306 u32 vm_entry_controls;
307 u32 vm_entry_msr_load_count;
308 u32 vm_entry_intr_info_field;
309 u32 vm_entry_exception_error_code;
310 u32 vm_entry_instruction_len;
312 u32 secondary_vm_exec_control;
313 u32 vm_instruction_error;
315 u32 vm_exit_intr_info;
316 u32 vm_exit_intr_error_code;
317 u32 idt_vectoring_info_field;
318 u32 idt_vectoring_error_code;
319 u32 vm_exit_instruction_len;
320 u32 vmx_instruction_info;
327 u32 guest_ldtr_limit;
329 u32 guest_gdtr_limit;
330 u32 guest_idtr_limit;
331 u32 guest_es_ar_bytes;
332 u32 guest_cs_ar_bytes;
333 u32 guest_ss_ar_bytes;
334 u32 guest_ds_ar_bytes;
335 u32 guest_fs_ar_bytes;
336 u32 guest_gs_ar_bytes;
337 u32 guest_ldtr_ar_bytes;
338 u32 guest_tr_ar_bytes;
339 u32 guest_interruptibility_info;
340 u32 guest_activity_state;
341 u32 guest_sysenter_cs;
342 u32 host_ia32_sysenter_cs;
343 u32 vmx_preemption_timer_value;
344 u32 padding32[7]; /* room for future expansion */
345 u16 virtual_processor_id;
347 u16 guest_es_selector;
348 u16 guest_cs_selector;
349 u16 guest_ss_selector;
350 u16 guest_ds_selector;
351 u16 guest_fs_selector;
352 u16 guest_gs_selector;
353 u16 guest_ldtr_selector;
354 u16 guest_tr_selector;
355 u16 guest_intr_status;
356 u16 host_es_selector;
357 u16 host_cs_selector;
358 u16 host_ss_selector;
359 u16 host_ds_selector;
360 u16 host_fs_selector;
361 u16 host_gs_selector;
362 u16 host_tr_selector;
366 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
367 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
368 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
370 #define VMCS12_REVISION 0x11e57ed0
373 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
374 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
375 * current implementation, 4K are reserved to avoid future complications.
377 #define VMCS12_SIZE 0x1000
379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
381 struct list_head list;
383 struct loaded_vmcs vmcs02;
387 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
388 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
391 /* Has the level1 guest done vmxon? */
395 /* The guest-physical address of the current VMCS L1 keeps for L2 */
397 /* The host-usable pointer to the above */
398 struct page *current_vmcs12_page;
399 struct vmcs12 *current_vmcs12;
400 struct vmcs *current_shadow_vmcs;
402 * Indicates if the shadow vmcs must be updated with the
403 * data hold by vmcs12
405 bool sync_shadow_vmcs;
407 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
408 struct list_head vmcs02_pool;
410 u64 vmcs01_tsc_offset;
411 bool change_vmcs01_virtual_x2apic_mode;
412 /* L2 must run next, and mustn't decide to exit to L1. */
413 bool nested_run_pending;
415 * Guest pages referred to in vmcs02 with host-physical pointers, so
416 * we must keep them pinned while L2 runs.
418 struct page *apic_access_page;
419 struct page *virtual_apic_page;
420 struct page *pi_desc_page;
421 struct pi_desc *pi_desc;
424 u64 msr_ia32_feature_control;
426 struct hrtimer preemption_timer;
427 bool preemption_timer_expired;
429 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
435 u32 nested_vmx_procbased_ctls_low;
436 u32 nested_vmx_procbased_ctls_high;
437 u32 nested_vmx_true_procbased_ctls_low;
438 u32 nested_vmx_secondary_ctls_low;
439 u32 nested_vmx_secondary_ctls_high;
440 u32 nested_vmx_pinbased_ctls_low;
441 u32 nested_vmx_pinbased_ctls_high;
442 u32 nested_vmx_exit_ctls_low;
443 u32 nested_vmx_exit_ctls_high;
444 u32 nested_vmx_true_exit_ctls_low;
445 u32 nested_vmx_entry_ctls_low;
446 u32 nested_vmx_entry_ctls_high;
447 u32 nested_vmx_true_entry_ctls_low;
448 u32 nested_vmx_misc_low;
449 u32 nested_vmx_misc_high;
450 u32 nested_vmx_ept_caps;
451 u32 nested_vmx_vpid_caps;
454 #define POSTED_INTR_ON 0
455 #define POSTED_INTR_SN 1
457 /* Posted-Interrupt Descriptor */
459 u32 pir[8]; /* Posted interrupt requested */
462 /* bit 256 - Outstanding Notification */
464 /* bit 257 - Suppress Notification */
466 /* bit 271:258 - Reserved */
468 /* bit 279:272 - Notification Vector */
470 /* bit 287:280 - Reserved */
472 /* bit 319:288 - Notification Destination */
480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
482 return test_and_set_bit(POSTED_INTR_ON,
483 (unsigned long *)&pi_desc->control);
486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
488 return test_and_clear_bit(POSTED_INTR_ON,
489 (unsigned long *)&pi_desc->control);
492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
494 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
499 return clear_bit(POSTED_INTR_SN,
500 (unsigned long *)&pi_desc->control);
503 static inline void pi_set_sn(struct pi_desc *pi_desc)
505 return set_bit(POSTED_INTR_SN,
506 (unsigned long *)&pi_desc->control);
509 static inline int pi_test_on(struct pi_desc *pi_desc)
511 return test_bit(POSTED_INTR_ON,
512 (unsigned long *)&pi_desc->control);
515 static inline int pi_test_sn(struct pi_desc *pi_desc)
517 return test_bit(POSTED_INTR_SN,
518 (unsigned long *)&pi_desc->control);
522 struct kvm_vcpu vcpu;
523 unsigned long host_rsp;
525 bool nmi_known_unmasked;
527 u32 idt_vectoring_info;
529 struct shared_msr_entry *guest_msrs;
532 unsigned long host_idt_base;
534 u64 msr_host_kernel_gs_base;
535 u64 msr_guest_kernel_gs_base;
537 u32 vm_entry_controls_shadow;
538 u32 vm_exit_controls_shadow;
540 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
541 * non-nested (L1) guest, it always points to vmcs01. For a nested
542 * guest (L2), it points to a different VMCS.
544 struct loaded_vmcs vmcs01;
545 struct loaded_vmcs *loaded_vmcs;
546 bool __launched; /* temporary, used in vmx_vcpu_run */
547 struct msr_autoload {
549 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
550 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
554 u16 fs_sel, gs_sel, ldt_sel;
558 int gs_ldt_reload_needed;
559 int fs_reload_needed;
560 u64 msr_host_bndcfgs;
561 unsigned long vmcs_host_cr4; /* May not match real cr4 */
566 struct kvm_segment segs[8];
569 u32 bitmask; /* 4 bits per segment (1 bit per field) */
570 struct kvm_save_segment {
578 bool emulation_required;
580 /* Support for vnmi-less CPUs */
581 int soft_vnmi_blocked;
583 s64 vnmi_blocked_time;
586 /* Posted interrupt descriptor */
587 struct pi_desc pi_desc;
589 /* Support for a guest hypervisor (nested VMX) */
590 struct nested_vmx nested;
592 /* Dynamic PLE window. */
594 bool ple_window_dirty;
596 /* Support for PML */
597 #define PML_ENTITY_NUM 512
600 u64 current_tsc_ratio;
603 enum segment_cache_field {
612 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
614 return container_of(vcpu, struct vcpu_vmx, vcpu);
617 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
619 return &(to_vmx(vcpu)->pi_desc);
622 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
623 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
624 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
625 [number##_HIGH] = VMCS12_OFFSET(name)+4
628 static unsigned long shadow_read_only_fields[] = {
630 * We do NOT shadow fields that are modified when L0
631 * traps and emulates any vmx instruction (e.g. VMPTRLD,
632 * VMXON...) executed by L1.
633 * For example, VM_INSTRUCTION_ERROR is read
634 * by L1 if a vmx instruction fails (part of the error path).
635 * Note the code assumes this logic. If for some reason
636 * we start shadowing these fields then we need to
637 * force a shadow sync when L0 emulates vmx instructions
638 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
639 * by nested_vmx_failValid)
643 VM_EXIT_INSTRUCTION_LEN,
644 IDT_VECTORING_INFO_FIELD,
645 IDT_VECTORING_ERROR_CODE,
646 VM_EXIT_INTR_ERROR_CODE,
648 GUEST_LINEAR_ADDRESS,
649 GUEST_PHYSICAL_ADDRESS
651 static int max_shadow_read_only_fields =
652 ARRAY_SIZE(shadow_read_only_fields);
654 static unsigned long shadow_read_write_fields[] = {
661 GUEST_INTERRUPTIBILITY_INFO,
674 CPU_BASED_VM_EXEC_CONTROL,
675 VM_ENTRY_EXCEPTION_ERROR_CODE,
676 VM_ENTRY_INTR_INFO_FIELD,
677 VM_ENTRY_INSTRUCTION_LEN,
678 VM_ENTRY_EXCEPTION_ERROR_CODE,
684 static int max_shadow_read_write_fields =
685 ARRAY_SIZE(shadow_read_write_fields);
687 static const unsigned short vmcs_field_to_offset_table[] = {
688 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
689 FIELD(POSTED_INTR_NV, posted_intr_nv),
690 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
691 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
692 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
693 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
694 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
695 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
696 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
697 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
698 FIELD(GUEST_INTR_STATUS, guest_intr_status),
699 FIELD(HOST_ES_SELECTOR, host_es_selector),
700 FIELD(HOST_CS_SELECTOR, host_cs_selector),
701 FIELD(HOST_SS_SELECTOR, host_ss_selector),
702 FIELD(HOST_DS_SELECTOR, host_ds_selector),
703 FIELD(HOST_FS_SELECTOR, host_fs_selector),
704 FIELD(HOST_GS_SELECTOR, host_gs_selector),
705 FIELD(HOST_TR_SELECTOR, host_tr_selector),
706 FIELD64(IO_BITMAP_A, io_bitmap_a),
707 FIELD64(IO_BITMAP_B, io_bitmap_b),
708 FIELD64(MSR_BITMAP, msr_bitmap),
709 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
710 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
711 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
712 FIELD64(TSC_OFFSET, tsc_offset),
713 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
714 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
715 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
716 FIELD64(EPT_POINTER, ept_pointer),
717 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
718 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
719 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
720 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
721 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
722 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
723 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
724 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
725 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
726 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
727 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
728 FIELD64(GUEST_PDPTR0, guest_pdptr0),
729 FIELD64(GUEST_PDPTR1, guest_pdptr1),
730 FIELD64(GUEST_PDPTR2, guest_pdptr2),
731 FIELD64(GUEST_PDPTR3, guest_pdptr3),
732 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
733 FIELD64(HOST_IA32_PAT, host_ia32_pat),
734 FIELD64(HOST_IA32_EFER, host_ia32_efer),
735 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
736 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
737 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
738 FIELD(EXCEPTION_BITMAP, exception_bitmap),
739 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
740 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
741 FIELD(CR3_TARGET_COUNT, cr3_target_count),
742 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
743 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
744 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
745 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
746 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
747 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
748 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
749 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
750 FIELD(TPR_THRESHOLD, tpr_threshold),
751 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
752 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
753 FIELD(VM_EXIT_REASON, vm_exit_reason),
754 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
755 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
756 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
757 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
758 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
759 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
760 FIELD(GUEST_ES_LIMIT, guest_es_limit),
761 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
762 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
763 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
764 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
765 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
766 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
767 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
768 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
769 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
770 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
771 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
772 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
773 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
774 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
775 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
776 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
777 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
778 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
779 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
780 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
781 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
782 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
783 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
784 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
785 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
786 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
787 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
788 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
789 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
790 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
791 FIELD(EXIT_QUALIFICATION, exit_qualification),
792 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
793 FIELD(GUEST_CR0, guest_cr0),
794 FIELD(GUEST_CR3, guest_cr3),
795 FIELD(GUEST_CR4, guest_cr4),
796 FIELD(GUEST_ES_BASE, guest_es_base),
797 FIELD(GUEST_CS_BASE, guest_cs_base),
798 FIELD(GUEST_SS_BASE, guest_ss_base),
799 FIELD(GUEST_DS_BASE, guest_ds_base),
800 FIELD(GUEST_FS_BASE, guest_fs_base),
801 FIELD(GUEST_GS_BASE, guest_gs_base),
802 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
803 FIELD(GUEST_TR_BASE, guest_tr_base),
804 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
805 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
806 FIELD(GUEST_DR7, guest_dr7),
807 FIELD(GUEST_RSP, guest_rsp),
808 FIELD(GUEST_RIP, guest_rip),
809 FIELD(GUEST_RFLAGS, guest_rflags),
810 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
811 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
812 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
813 FIELD(HOST_CR0, host_cr0),
814 FIELD(HOST_CR3, host_cr3),
815 FIELD(HOST_CR4, host_cr4),
816 FIELD(HOST_FS_BASE, host_fs_base),
817 FIELD(HOST_GS_BASE, host_gs_base),
818 FIELD(HOST_TR_BASE, host_tr_base),
819 FIELD(HOST_GDTR_BASE, host_gdtr_base),
820 FIELD(HOST_IDTR_BASE, host_idtr_base),
821 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
822 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
823 FIELD(HOST_RSP, host_rsp),
824 FIELD(HOST_RIP, host_rip),
827 static inline short vmcs_field_to_offset(unsigned long field)
829 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
831 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
832 vmcs_field_to_offset_table[field] == 0)
835 return vmcs_field_to_offset_table[field];
838 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
840 return to_vmx(vcpu)->nested.current_vmcs12;
843 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
845 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
846 if (is_error_page(page))
852 static void nested_release_page(struct page *page)
854 kvm_release_page_dirty(page);
857 static void nested_release_page_clean(struct page *page)
859 kvm_release_page_clean(page);
862 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
863 static u64 construct_eptp(unsigned long root_hpa);
864 static void kvm_cpu_vmxon(u64 addr);
865 static void kvm_cpu_vmxoff(void);
866 static bool vmx_mpx_supported(void);
867 static bool vmx_xsaves_supported(void);
868 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
869 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
870 static void vmx_set_segment(struct kvm_vcpu *vcpu,
871 struct kvm_segment *var, int seg);
872 static void vmx_get_segment(struct kvm_vcpu *vcpu,
873 struct kvm_segment *var, int seg);
874 static bool guest_state_valid(struct kvm_vcpu *vcpu);
875 static u32 vmx_segment_access_rights(struct kvm_segment *var);
876 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
877 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
878 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
879 static int alloc_identity_pagetable(struct kvm *kvm);
881 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
882 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
884 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
885 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
887 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
888 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
891 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
892 * can find which vCPU should be waken up.
894 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
895 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
897 static unsigned long *vmx_io_bitmap_a;
898 static unsigned long *vmx_io_bitmap_b;
899 static unsigned long *vmx_msr_bitmap_legacy;
900 static unsigned long *vmx_msr_bitmap_longmode;
901 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
902 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
903 static unsigned long *vmx_msr_bitmap_nested;
904 static unsigned long *vmx_vmread_bitmap;
905 static unsigned long *vmx_vmwrite_bitmap;
907 static bool cpu_has_load_ia32_efer;
908 static bool cpu_has_load_perf_global_ctrl;
910 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
911 static DEFINE_SPINLOCK(vmx_vpid_lock);
913 static struct vmcs_config {
917 u32 pin_based_exec_ctrl;
918 u32 cpu_based_exec_ctrl;
919 u32 cpu_based_2nd_exec_ctrl;
924 static struct vmx_capability {
929 #define VMX_SEGMENT_FIELD(seg) \
930 [VCPU_SREG_##seg] = { \
931 .selector = GUEST_##seg##_SELECTOR, \
932 .base = GUEST_##seg##_BASE, \
933 .limit = GUEST_##seg##_LIMIT, \
934 .ar_bytes = GUEST_##seg##_AR_BYTES, \
937 static const struct kvm_vmx_segment_field {
942 } kvm_vmx_segment_fields[] = {
943 VMX_SEGMENT_FIELD(CS),
944 VMX_SEGMENT_FIELD(DS),
945 VMX_SEGMENT_FIELD(ES),
946 VMX_SEGMENT_FIELD(FS),
947 VMX_SEGMENT_FIELD(GS),
948 VMX_SEGMENT_FIELD(SS),
949 VMX_SEGMENT_FIELD(TR),
950 VMX_SEGMENT_FIELD(LDTR),
953 static u64 host_efer;
955 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
958 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
959 * away by decrementing the array size.
961 static const u32 vmx_msr_index[] = {
963 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
965 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
968 static inline bool is_page_fault(u32 intr_info)
970 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
971 INTR_INFO_VALID_MASK)) ==
972 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
975 static inline bool is_no_device(u32 intr_info)
977 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
978 INTR_INFO_VALID_MASK)) ==
979 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
982 static inline bool is_invalid_opcode(u32 intr_info)
984 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
985 INTR_INFO_VALID_MASK)) ==
986 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
989 static inline bool is_external_interrupt(u32 intr_info)
991 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
992 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
995 static inline bool is_machine_check(u32 intr_info)
997 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
998 INTR_INFO_VALID_MASK)) ==
999 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1002 static inline bool cpu_has_vmx_msr_bitmap(void)
1004 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1007 static inline bool cpu_has_vmx_tpr_shadow(void)
1009 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1012 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1014 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1017 static inline bool cpu_has_secondary_exec_ctrls(void)
1019 return vmcs_config.cpu_based_exec_ctrl &
1020 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1023 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1025 return vmcs_config.cpu_based_2nd_exec_ctrl &
1026 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1029 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1031 return vmcs_config.cpu_based_2nd_exec_ctrl &
1032 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1035 static inline bool cpu_has_vmx_apic_register_virt(void)
1037 return vmcs_config.cpu_based_2nd_exec_ctrl &
1038 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1041 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1043 return vmcs_config.cpu_based_2nd_exec_ctrl &
1044 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1047 static inline bool cpu_has_vmx_posted_intr(void)
1049 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1050 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1053 static inline bool cpu_has_vmx_apicv(void)
1055 return cpu_has_vmx_apic_register_virt() &&
1056 cpu_has_vmx_virtual_intr_delivery() &&
1057 cpu_has_vmx_posted_intr();
1060 static inline bool cpu_has_vmx_flexpriority(void)
1062 return cpu_has_vmx_tpr_shadow() &&
1063 cpu_has_vmx_virtualize_apic_accesses();
1066 static inline bool cpu_has_vmx_ept_execute_only(void)
1068 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1071 static inline bool cpu_has_vmx_ept_2m_page(void)
1073 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1076 static inline bool cpu_has_vmx_ept_1g_page(void)
1078 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1081 static inline bool cpu_has_vmx_ept_4levels(void)
1083 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1086 static inline bool cpu_has_vmx_ept_ad_bits(void)
1088 return vmx_capability.ept & VMX_EPT_AD_BIT;
1091 static inline bool cpu_has_vmx_invept_context(void)
1093 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1096 static inline bool cpu_has_vmx_invept_global(void)
1098 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1101 static inline bool cpu_has_vmx_invvpid_single(void)
1103 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1106 static inline bool cpu_has_vmx_invvpid_global(void)
1108 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1111 static inline bool cpu_has_vmx_ept(void)
1113 return vmcs_config.cpu_based_2nd_exec_ctrl &
1114 SECONDARY_EXEC_ENABLE_EPT;
1117 static inline bool cpu_has_vmx_unrestricted_guest(void)
1119 return vmcs_config.cpu_based_2nd_exec_ctrl &
1120 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1123 static inline bool cpu_has_vmx_ple(void)
1125 return vmcs_config.cpu_based_2nd_exec_ctrl &
1126 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1129 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1131 return flexpriority_enabled && lapic_in_kernel(vcpu);
1134 static inline bool cpu_has_vmx_vpid(void)
1136 return vmcs_config.cpu_based_2nd_exec_ctrl &
1137 SECONDARY_EXEC_ENABLE_VPID;
1140 static inline bool cpu_has_vmx_rdtscp(void)
1142 return vmcs_config.cpu_based_2nd_exec_ctrl &
1143 SECONDARY_EXEC_RDTSCP;
1146 static inline bool cpu_has_vmx_invpcid(void)
1148 return vmcs_config.cpu_based_2nd_exec_ctrl &
1149 SECONDARY_EXEC_ENABLE_INVPCID;
1152 static inline bool cpu_has_virtual_nmis(void)
1154 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1157 static inline bool cpu_has_vmx_wbinvd_exit(void)
1159 return vmcs_config.cpu_based_2nd_exec_ctrl &
1160 SECONDARY_EXEC_WBINVD_EXITING;
1163 static inline bool cpu_has_vmx_shadow_vmcs(void)
1166 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1167 /* check if the cpu supports writing r/o exit information fields */
1168 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1171 return vmcs_config.cpu_based_2nd_exec_ctrl &
1172 SECONDARY_EXEC_SHADOW_VMCS;
1175 static inline bool cpu_has_vmx_pml(void)
1177 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1180 static inline bool cpu_has_vmx_tsc_scaling(void)
1182 return vmcs_config.cpu_based_2nd_exec_ctrl &
1183 SECONDARY_EXEC_TSC_SCALING;
1186 static inline bool report_flexpriority(void)
1188 return flexpriority_enabled;
1191 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1193 return vmcs12->cpu_based_vm_exec_control & bit;
1196 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1198 return (vmcs12->cpu_based_vm_exec_control &
1199 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1200 (vmcs12->secondary_vm_exec_control & bit);
1203 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1205 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1208 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1210 return vmcs12->pin_based_vm_exec_control &
1211 PIN_BASED_VMX_PREEMPTION_TIMER;
1214 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1216 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1219 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1221 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1222 vmx_xsaves_supported();
1225 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1227 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1230 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1232 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1235 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1237 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1240 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1242 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1245 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1247 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1250 static inline bool is_nmi(u32 intr_info)
1252 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1253 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1256 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1258 unsigned long exit_qualification);
1259 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1260 struct vmcs12 *vmcs12,
1261 u32 reason, unsigned long qualification);
1263 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1267 for (i = 0; i < vmx->nmsrs; ++i)
1268 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1273 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1279 } operand = { vpid, 0, gva };
1281 asm volatile (__ex(ASM_VMX_INVVPID)
1282 /* CF==1 or ZF==1 --> rc = -1 */
1283 "; ja 1f ; ud2 ; 1:"
1284 : : "a"(&operand), "c"(ext) : "cc", "memory");
1287 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1291 } operand = {eptp, gpa};
1293 asm volatile (__ex(ASM_VMX_INVEPT)
1294 /* CF==1 or ZF==1 --> rc = -1 */
1295 "; ja 1f ; ud2 ; 1:\n"
1296 : : "a" (&operand), "c" (ext) : "cc", "memory");
1299 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1303 i = __find_msr_index(vmx, msr);
1305 return &vmx->guest_msrs[i];
1309 static void vmcs_clear(struct vmcs *vmcs)
1311 u64 phys_addr = __pa(vmcs);
1314 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1315 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1318 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1322 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1324 vmcs_clear(loaded_vmcs->vmcs);
1325 loaded_vmcs->cpu = -1;
1326 loaded_vmcs->launched = 0;
1329 static void vmcs_load(struct vmcs *vmcs)
1331 u64 phys_addr = __pa(vmcs);
1334 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1335 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1338 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1342 #ifdef CONFIG_KEXEC_CORE
1344 * This bitmap is used to indicate whether the vmclear
1345 * operation is enabled on all cpus. All disabled by
1348 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1350 static inline void crash_enable_local_vmclear(int cpu)
1352 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1355 static inline void crash_disable_local_vmclear(int cpu)
1357 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1360 static inline int crash_local_vmclear_enabled(int cpu)
1362 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1365 static void crash_vmclear_local_loaded_vmcss(void)
1367 int cpu = raw_smp_processor_id();
1368 struct loaded_vmcs *v;
1370 if (!crash_local_vmclear_enabled(cpu))
1373 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1374 loaded_vmcss_on_cpu_link)
1375 vmcs_clear(v->vmcs);
1378 static inline void crash_enable_local_vmclear(int cpu) { }
1379 static inline void crash_disable_local_vmclear(int cpu) { }
1380 #endif /* CONFIG_KEXEC_CORE */
1382 static void __loaded_vmcs_clear(void *arg)
1384 struct loaded_vmcs *loaded_vmcs = arg;
1385 int cpu = raw_smp_processor_id();
1387 if (loaded_vmcs->cpu != cpu)
1388 return; /* vcpu migration can race with cpu offline */
1389 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1390 per_cpu(current_vmcs, cpu) = NULL;
1391 crash_disable_local_vmclear(cpu);
1392 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1395 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1396 * is before setting loaded_vmcs->vcpu to -1 which is done in
1397 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1398 * then adds the vmcs into percpu list before it is deleted.
1402 loaded_vmcs_init(loaded_vmcs);
1403 crash_enable_local_vmclear(cpu);
1406 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1408 int cpu = loaded_vmcs->cpu;
1411 smp_call_function_single(cpu,
1412 __loaded_vmcs_clear, loaded_vmcs, 1);
1415 static inline void vpid_sync_vcpu_single(int vpid)
1420 if (cpu_has_vmx_invvpid_single())
1421 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1424 static inline void vpid_sync_vcpu_global(void)
1426 if (cpu_has_vmx_invvpid_global())
1427 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1430 static inline void vpid_sync_context(int vpid)
1432 if (cpu_has_vmx_invvpid_single())
1433 vpid_sync_vcpu_single(vpid);
1435 vpid_sync_vcpu_global();
1438 static inline void ept_sync_global(void)
1440 if (cpu_has_vmx_invept_global())
1441 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1444 static inline void ept_sync_context(u64 eptp)
1447 if (cpu_has_vmx_invept_context())
1448 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1454 static __always_inline unsigned long vmcs_readl(unsigned long field)
1456 unsigned long value;
1458 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1459 : "=a"(value) : "d"(field) : "cc");
1463 static __always_inline u16 vmcs_read16(unsigned long field)
1465 return vmcs_readl(field);
1468 static __always_inline u32 vmcs_read32(unsigned long field)
1470 return vmcs_readl(field);
1473 static __always_inline u64 vmcs_read64(unsigned long field)
1475 #ifdef CONFIG_X86_64
1476 return vmcs_readl(field);
1478 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1482 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1484 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1485 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1489 static void vmcs_writel(unsigned long field, unsigned long value)
1493 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1494 : "=q"(error) : "a"(value), "d"(field) : "cc");
1495 if (unlikely(error))
1496 vmwrite_error(field, value);
1499 static void vmcs_write16(unsigned long field, u16 value)
1501 vmcs_writel(field, value);
1504 static void vmcs_write32(unsigned long field, u32 value)
1506 vmcs_writel(field, value);
1509 static void vmcs_write64(unsigned long field, u64 value)
1511 vmcs_writel(field, value);
1512 #ifndef CONFIG_X86_64
1514 vmcs_writel(field+1, value >> 32);
1518 static void vmcs_clear_bits(unsigned long field, u32 mask)
1520 vmcs_writel(field, vmcs_readl(field) & ~mask);
1523 static void vmcs_set_bits(unsigned long field, u32 mask)
1525 vmcs_writel(field, vmcs_readl(field) | mask);
1528 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1530 vmcs_write32(VM_ENTRY_CONTROLS, val);
1531 vmx->vm_entry_controls_shadow = val;
1534 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1536 if (vmx->vm_entry_controls_shadow != val)
1537 vm_entry_controls_init(vmx, val);
1540 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1542 return vmx->vm_entry_controls_shadow;
1546 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1548 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1551 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1553 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1556 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1558 vmcs_write32(VM_EXIT_CONTROLS, val);
1559 vmx->vm_exit_controls_shadow = val;
1562 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1564 if (vmx->vm_exit_controls_shadow != val)
1565 vm_exit_controls_init(vmx, val);
1568 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1570 return vmx->vm_exit_controls_shadow;
1574 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1576 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1579 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1581 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1584 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1586 vmx->segment_cache.bitmask = 0;
1589 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1593 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1595 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1596 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1597 vmx->segment_cache.bitmask = 0;
1599 ret = vmx->segment_cache.bitmask & mask;
1600 vmx->segment_cache.bitmask |= mask;
1604 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1606 u16 *p = &vmx->segment_cache.seg[seg].selector;
1608 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1609 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1613 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1615 ulong *p = &vmx->segment_cache.seg[seg].base;
1617 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1618 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1622 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1624 u32 *p = &vmx->segment_cache.seg[seg].limit;
1626 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1627 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1631 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1633 u32 *p = &vmx->segment_cache.seg[seg].ar;
1635 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1636 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1640 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1644 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1645 (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1646 if ((vcpu->guest_debug &
1647 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1648 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1649 eb |= 1u << BP_VECTOR;
1650 if (to_vmx(vcpu)->rmode.vm86_active)
1653 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1654 if (vcpu->fpu_active)
1655 eb &= ~(1u << NM_VECTOR);
1657 /* When we are running a nested L2 guest and L1 specified for it a
1658 * certain exception bitmap, we must trap the same exceptions and pass
1659 * them to L1. When running L2, we will only handle the exceptions
1660 * specified above if L1 did not want them.
1662 if (is_guest_mode(vcpu))
1663 eb |= get_vmcs12(vcpu)->exception_bitmap;
1665 vmcs_write32(EXCEPTION_BITMAP, eb);
1668 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1669 unsigned long entry, unsigned long exit)
1671 vm_entry_controls_clearbit(vmx, entry);
1672 vm_exit_controls_clearbit(vmx, exit);
1675 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1678 struct msr_autoload *m = &vmx->msr_autoload;
1682 if (cpu_has_load_ia32_efer) {
1683 clear_atomic_switch_msr_special(vmx,
1684 VM_ENTRY_LOAD_IA32_EFER,
1685 VM_EXIT_LOAD_IA32_EFER);
1689 case MSR_CORE_PERF_GLOBAL_CTRL:
1690 if (cpu_has_load_perf_global_ctrl) {
1691 clear_atomic_switch_msr_special(vmx,
1692 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1693 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1699 for (i = 0; i < m->nr; ++i)
1700 if (m->guest[i].index == msr)
1706 m->guest[i] = m->guest[m->nr];
1707 m->host[i] = m->host[m->nr];
1708 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1709 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1712 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1713 unsigned long entry, unsigned long exit,
1714 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1715 u64 guest_val, u64 host_val)
1717 vmcs_write64(guest_val_vmcs, guest_val);
1718 vmcs_write64(host_val_vmcs, host_val);
1719 vm_entry_controls_setbit(vmx, entry);
1720 vm_exit_controls_setbit(vmx, exit);
1723 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1724 u64 guest_val, u64 host_val)
1727 struct msr_autoload *m = &vmx->msr_autoload;
1731 if (cpu_has_load_ia32_efer) {
1732 add_atomic_switch_msr_special(vmx,
1733 VM_ENTRY_LOAD_IA32_EFER,
1734 VM_EXIT_LOAD_IA32_EFER,
1737 guest_val, host_val);
1741 case MSR_CORE_PERF_GLOBAL_CTRL:
1742 if (cpu_has_load_perf_global_ctrl) {
1743 add_atomic_switch_msr_special(vmx,
1744 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1745 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1746 GUEST_IA32_PERF_GLOBAL_CTRL,
1747 HOST_IA32_PERF_GLOBAL_CTRL,
1748 guest_val, host_val);
1752 case MSR_IA32_PEBS_ENABLE:
1753 /* PEBS needs a quiescent period after being disabled (to write
1754 * a record). Disabling PEBS through VMX MSR swapping doesn't
1755 * provide that period, so a CPU could write host's record into
1758 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1761 for (i = 0; i < m->nr; ++i)
1762 if (m->guest[i].index == msr)
1765 if (i == NR_AUTOLOAD_MSRS) {
1766 printk_once(KERN_WARNING "Not enough msr switch entries. "
1767 "Can't add msr %x\n", msr);
1769 } else if (i == m->nr) {
1771 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1772 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1775 m->guest[i].index = msr;
1776 m->guest[i].value = guest_val;
1777 m->host[i].index = msr;
1778 m->host[i].value = host_val;
1781 static void reload_tss(void)
1784 * VT restores TR but not its size. Useless.
1786 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1787 struct desc_struct *descs;
1789 descs = (void *)gdt->address;
1790 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1794 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1796 u64 guest_efer = vmx->vcpu.arch.efer;
1797 u64 ignore_bits = 0;
1801 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1802 * host CPUID is more efficient than testing guest CPUID
1803 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1805 if (boot_cpu_has(X86_FEATURE_SMEP))
1806 guest_efer |= EFER_NX;
1807 else if (!(guest_efer & EFER_NX))
1808 ignore_bits |= EFER_NX;
1812 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1814 ignore_bits |= EFER_SCE;
1815 #ifdef CONFIG_X86_64
1816 ignore_bits |= EFER_LMA | EFER_LME;
1817 /* SCE is meaningful only in long mode on Intel */
1818 if (guest_efer & EFER_LMA)
1819 ignore_bits &= ~(u64)EFER_SCE;
1822 clear_atomic_switch_msr(vmx, MSR_EFER);
1825 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1826 * On CPUs that support "load IA32_EFER", always switch EFER
1827 * atomically, since it's faster than switching it manually.
1829 if (cpu_has_load_ia32_efer ||
1830 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1831 if (!(guest_efer & EFER_LMA))
1832 guest_efer &= ~EFER_LME;
1833 if (guest_efer != host_efer)
1834 add_atomic_switch_msr(vmx, MSR_EFER,
1835 guest_efer, host_efer);
1838 guest_efer &= ~ignore_bits;
1839 guest_efer |= host_efer & ignore_bits;
1841 vmx->guest_msrs[efer_offset].data = guest_efer;
1842 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1848 static unsigned long segment_base(u16 selector)
1850 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1851 struct desc_struct *d;
1852 unsigned long table_base;
1855 if (!(selector & ~3))
1858 table_base = gdt->address;
1860 if (selector & 4) { /* from ldt */
1861 u16 ldt_selector = kvm_read_ldt();
1863 if (!(ldt_selector & ~3))
1866 table_base = segment_base(ldt_selector);
1868 d = (struct desc_struct *)(table_base + (selector & ~7));
1869 v = get_desc_base(d);
1870 #ifdef CONFIG_X86_64
1871 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1872 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1877 static inline unsigned long kvm_read_tr_base(void)
1880 asm("str %0" : "=g"(tr));
1881 return segment_base(tr);
1884 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1886 struct vcpu_vmx *vmx = to_vmx(vcpu);
1889 if (vmx->host_state.loaded)
1892 vmx->host_state.loaded = 1;
1894 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1895 * allow segment selectors with cpl > 0 or ti == 1.
1897 vmx->host_state.ldt_sel = kvm_read_ldt();
1898 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1899 savesegment(fs, vmx->host_state.fs_sel);
1900 if (!(vmx->host_state.fs_sel & 7)) {
1901 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1902 vmx->host_state.fs_reload_needed = 0;
1904 vmcs_write16(HOST_FS_SELECTOR, 0);
1905 vmx->host_state.fs_reload_needed = 1;
1907 savesegment(gs, vmx->host_state.gs_sel);
1908 if (!(vmx->host_state.gs_sel & 7))
1909 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1911 vmcs_write16(HOST_GS_SELECTOR, 0);
1912 vmx->host_state.gs_ldt_reload_needed = 1;
1915 #ifdef CONFIG_X86_64
1916 savesegment(ds, vmx->host_state.ds_sel);
1917 savesegment(es, vmx->host_state.es_sel);
1920 #ifdef CONFIG_X86_64
1921 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1922 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1924 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1925 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1928 #ifdef CONFIG_X86_64
1929 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1930 if (is_long_mode(&vmx->vcpu))
1931 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1933 if (boot_cpu_has(X86_FEATURE_MPX))
1934 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1935 for (i = 0; i < vmx->save_nmsrs; ++i)
1936 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1937 vmx->guest_msrs[i].data,
1938 vmx->guest_msrs[i].mask);
1941 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1943 if (!vmx->host_state.loaded)
1946 ++vmx->vcpu.stat.host_state_reload;
1947 vmx->host_state.loaded = 0;
1948 #ifdef CONFIG_X86_64
1949 if (is_long_mode(&vmx->vcpu))
1950 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1952 if (vmx->host_state.gs_ldt_reload_needed) {
1953 kvm_load_ldt(vmx->host_state.ldt_sel);
1954 #ifdef CONFIG_X86_64
1955 load_gs_index(vmx->host_state.gs_sel);
1957 loadsegment(gs, vmx->host_state.gs_sel);
1960 if (vmx->host_state.fs_reload_needed)
1961 loadsegment(fs, vmx->host_state.fs_sel);
1962 #ifdef CONFIG_X86_64
1963 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1964 loadsegment(ds, vmx->host_state.ds_sel);
1965 loadsegment(es, vmx->host_state.es_sel);
1969 #ifdef CONFIG_X86_64
1970 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1972 if (vmx->host_state.msr_host_bndcfgs)
1973 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1975 * If the FPU is not active (through the host task or
1976 * the guest vcpu), then restore the cr0.TS bit.
1978 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1980 load_gdt(this_cpu_ptr(&host_gdt));
1983 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1986 __vmx_load_host_state(vmx);
1990 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1992 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1993 struct pi_desc old, new;
1996 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1997 !irq_remapping_cap(IRQ_POSTING_CAP))
2001 old.control = new.control = pi_desc->control;
2004 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2005 * are two possible cases:
2006 * 1. After running 'pre_block', context switch
2007 * happened. For this case, 'sn' was set in
2008 * vmx_vcpu_put(), so we need to clear it here.
2009 * 2. After running 'pre_block', we were blocked,
2010 * and woken up by some other guy. For this case,
2011 * we don't need to do anything, 'pi_post_block'
2012 * will do everything for us. However, we cannot
2013 * check whether it is case #1 or case #2 here
2014 * (maybe, not needed), so we also clear sn here,
2015 * I think it is not a big deal.
2017 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2018 if (vcpu->cpu != cpu) {
2019 dest = cpu_physical_id(cpu);
2021 if (x2apic_enabled())
2024 new.ndst = (dest << 8) & 0xFF00;
2027 /* set 'NV' to 'notification vector' */
2028 new.nv = POSTED_INTR_VECTOR;
2031 /* Allow posting non-urgent interrupts */
2033 } while (cmpxchg(&pi_desc->control, old.control,
2034 new.control) != old.control);
2037 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2038 * vcpu mutex is already taken.
2040 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2042 struct vcpu_vmx *vmx = to_vmx(vcpu);
2043 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2046 kvm_cpu_vmxon(phys_addr);
2047 else if (vmx->loaded_vmcs->cpu != cpu)
2048 loaded_vmcs_clear(vmx->loaded_vmcs);
2050 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2051 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2052 vmcs_load(vmx->loaded_vmcs->vmcs);
2055 if (vmx->loaded_vmcs->cpu != cpu) {
2056 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2057 unsigned long sysenter_esp;
2059 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2060 local_irq_disable();
2061 crash_disable_local_vmclear(cpu);
2064 * Read loaded_vmcs->cpu should be before fetching
2065 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2066 * See the comments in __loaded_vmcs_clear().
2070 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2071 &per_cpu(loaded_vmcss_on_cpu, cpu));
2072 crash_enable_local_vmclear(cpu);
2076 * Linux uses per-cpu TSS and GDT, so set these when switching
2079 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2080 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
2082 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2083 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2085 vmx->loaded_vmcs->cpu = cpu;
2088 /* Setup TSC multiplier */
2089 if (kvm_has_tsc_control &&
2090 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2091 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2092 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2095 vmx_vcpu_pi_load(vcpu, cpu);
2098 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2100 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2102 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2103 !irq_remapping_cap(IRQ_POSTING_CAP))
2106 /* Set SN when the vCPU is preempted */
2107 if (vcpu->preempted)
2111 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2113 vmx_vcpu_pi_put(vcpu);
2115 __vmx_load_host_state(to_vmx(vcpu));
2116 if (!vmm_exclusive) {
2117 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2123 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2127 if (vcpu->fpu_active)
2129 vcpu->fpu_active = 1;
2130 cr0 = vmcs_readl(GUEST_CR0);
2131 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2132 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2133 vmcs_writel(GUEST_CR0, cr0);
2134 update_exception_bitmap(vcpu);
2135 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2136 if (is_guest_mode(vcpu))
2137 vcpu->arch.cr0_guest_owned_bits &=
2138 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2139 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2142 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2145 * Return the cr0 value that a nested guest would read. This is a combination
2146 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2147 * its hypervisor (cr0_read_shadow).
2149 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2151 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2152 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2154 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2156 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2157 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2160 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2162 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2163 * set this *before* calling this function.
2165 vmx_decache_cr0_guest_bits(vcpu);
2166 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2167 update_exception_bitmap(vcpu);
2168 vcpu->arch.cr0_guest_owned_bits = 0;
2169 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2170 if (is_guest_mode(vcpu)) {
2172 * L1's specified read shadow might not contain the TS bit,
2173 * so now that we turned on shadowing of this bit, we need to
2174 * set this bit of the shadow. Like in nested_vmx_run we need
2175 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2176 * up-to-date here because we just decached cr0.TS (and we'll
2177 * only update vmcs12->guest_cr0 on nested exit).
2179 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2180 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2181 (vcpu->arch.cr0 & X86_CR0_TS);
2182 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2184 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2187 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2189 unsigned long rflags, save_rflags;
2191 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2192 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2193 rflags = vmcs_readl(GUEST_RFLAGS);
2194 if (to_vmx(vcpu)->rmode.vm86_active) {
2195 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2196 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2197 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2199 to_vmx(vcpu)->rflags = rflags;
2201 return to_vmx(vcpu)->rflags;
2204 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2206 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2207 to_vmx(vcpu)->rflags = rflags;
2208 if (to_vmx(vcpu)->rmode.vm86_active) {
2209 to_vmx(vcpu)->rmode.save_rflags = rflags;
2210 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2212 vmcs_writel(GUEST_RFLAGS, rflags);
2215 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2217 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2220 if (interruptibility & GUEST_INTR_STATE_STI)
2221 ret |= KVM_X86_SHADOW_INT_STI;
2222 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2223 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2228 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2230 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2231 u32 interruptibility = interruptibility_old;
2233 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2235 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2236 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2237 else if (mask & KVM_X86_SHADOW_INT_STI)
2238 interruptibility |= GUEST_INTR_STATE_STI;
2240 if ((interruptibility != interruptibility_old))
2241 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2244 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2248 rip = kvm_rip_read(vcpu);
2249 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2250 kvm_rip_write(vcpu, rip);
2252 /* skipping an emulated instruction also counts */
2253 vmx_set_interrupt_shadow(vcpu, 0);
2257 * KVM wants to inject page-faults which it got to the guest. This function
2258 * checks whether in a nested guest, we need to inject them to L1 or L2.
2260 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2262 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2264 if (!(vmcs12->exception_bitmap & (1u << nr)))
2267 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2268 vmcs_read32(VM_EXIT_INTR_INFO),
2269 vmcs_readl(EXIT_QUALIFICATION));
2273 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2274 bool has_error_code, u32 error_code,
2277 struct vcpu_vmx *vmx = to_vmx(vcpu);
2278 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2280 if (!reinject && is_guest_mode(vcpu) &&
2281 nested_vmx_check_exception(vcpu, nr))
2284 if (has_error_code) {
2285 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2286 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2289 if (vmx->rmode.vm86_active) {
2291 if (kvm_exception_is_soft(nr))
2292 inc_eip = vcpu->arch.event_exit_inst_len;
2293 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2294 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2298 if (kvm_exception_is_soft(nr)) {
2299 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2300 vmx->vcpu.arch.event_exit_inst_len);
2301 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2303 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2305 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2308 static bool vmx_rdtscp_supported(void)
2310 return cpu_has_vmx_rdtscp();
2313 static bool vmx_invpcid_supported(void)
2315 return cpu_has_vmx_invpcid() && enable_ept;
2319 * Swap MSR entry in host/guest MSR entry array.
2321 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2323 struct shared_msr_entry tmp;
2325 tmp = vmx->guest_msrs[to];
2326 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2327 vmx->guest_msrs[from] = tmp;
2330 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2332 unsigned long *msr_bitmap;
2334 if (is_guest_mode(vcpu))
2335 msr_bitmap = vmx_msr_bitmap_nested;
2336 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2337 if (is_long_mode(vcpu))
2338 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2340 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2342 if (is_long_mode(vcpu))
2343 msr_bitmap = vmx_msr_bitmap_longmode;
2345 msr_bitmap = vmx_msr_bitmap_legacy;
2348 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2352 * Set up the vmcs to automatically save and restore system
2353 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2354 * mode, as fiddling with msrs is very expensive.
2356 static void setup_msrs(struct vcpu_vmx *vmx)
2358 int save_nmsrs, index;
2361 #ifdef CONFIG_X86_64
2362 if (is_long_mode(&vmx->vcpu)) {
2363 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2365 move_msr_up(vmx, index, save_nmsrs++);
2366 index = __find_msr_index(vmx, MSR_LSTAR);
2368 move_msr_up(vmx, index, save_nmsrs++);
2369 index = __find_msr_index(vmx, MSR_CSTAR);
2371 move_msr_up(vmx, index, save_nmsrs++);
2372 index = __find_msr_index(vmx, MSR_TSC_AUX);
2373 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2374 move_msr_up(vmx, index, save_nmsrs++);
2376 * MSR_STAR is only needed on long mode guests, and only
2377 * if efer.sce is enabled.
2379 index = __find_msr_index(vmx, MSR_STAR);
2380 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2381 move_msr_up(vmx, index, save_nmsrs++);
2384 index = __find_msr_index(vmx, MSR_EFER);
2385 if (index >= 0 && update_transition_efer(vmx, index))
2386 move_msr_up(vmx, index, save_nmsrs++);
2388 vmx->save_nmsrs = save_nmsrs;
2390 if (cpu_has_vmx_msr_bitmap())
2391 vmx_set_msr_bitmap(&vmx->vcpu);
2395 * reads and returns guest's timestamp counter "register"
2396 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2397 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2399 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2401 u64 host_tsc, tsc_offset;
2404 tsc_offset = vmcs_read64(TSC_OFFSET);
2405 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2409 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2410 * counter, even if a nested guest (L2) is currently running.
2412 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2416 tsc_offset = is_guest_mode(vcpu) ?
2417 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2418 vmcs_read64(TSC_OFFSET);
2419 return host_tsc + tsc_offset;
2422 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2424 return vmcs_read64(TSC_OFFSET);
2428 * writes 'offset' into guest's timestamp counter offset register
2430 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2432 if (is_guest_mode(vcpu)) {
2434 * We're here if L1 chose not to trap WRMSR to TSC. According
2435 * to the spec, this should set L1's TSC; The offset that L1
2436 * set for L2 remains unchanged, and still needs to be added
2437 * to the newly set TSC to get L2's TSC.
2439 struct vmcs12 *vmcs12;
2440 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2441 /* recalculate vmcs02.TSC_OFFSET: */
2442 vmcs12 = get_vmcs12(vcpu);
2443 vmcs_write64(TSC_OFFSET, offset +
2444 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2445 vmcs12->tsc_offset : 0));
2447 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2448 vmcs_read64(TSC_OFFSET), offset);
2449 vmcs_write64(TSC_OFFSET, offset);
2453 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2455 u64 offset = vmcs_read64(TSC_OFFSET);
2457 vmcs_write64(TSC_OFFSET, offset + adjustment);
2458 if (is_guest_mode(vcpu)) {
2459 /* Even when running L2, the adjustment needs to apply to L1 */
2460 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2462 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2463 offset + adjustment);
2466 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2468 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2469 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2473 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2474 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2475 * all guests if the "nested" module option is off, and can also be disabled
2476 * for a single guest by disabling its VMX cpuid bit.
2478 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2480 return nested && guest_cpuid_has_vmx(vcpu);
2484 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2485 * returned for the various VMX controls MSRs when nested VMX is enabled.
2486 * The same values should also be used to verify that vmcs12 control fields are
2487 * valid during nested entry from L1 to L2.
2488 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2489 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2490 * bit in the high half is on if the corresponding bit in the control field
2491 * may be on. See also vmx_control_verify().
2493 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2496 * Note that as a general rule, the high half of the MSRs (bits in
2497 * the control fields which may be 1) should be initialized by the
2498 * intersection of the underlying hardware's MSR (i.e., features which
2499 * can be supported) and the list of features we want to expose -
2500 * because they are known to be properly supported in our code.
2501 * Also, usually, the low half of the MSRs (bits which must be 1) can
2502 * be set to 0, meaning that L1 may turn off any of these bits. The
2503 * reason is that if one of these bits is necessary, it will appear
2504 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2505 * fields of vmcs01 and vmcs02, will turn these bits off - and
2506 * nested_vmx_exit_handled() will not pass related exits to L1.
2507 * These rules have exceptions below.
2510 /* pin-based controls */
2511 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2512 vmx->nested.nested_vmx_pinbased_ctls_low,
2513 vmx->nested.nested_vmx_pinbased_ctls_high);
2514 vmx->nested.nested_vmx_pinbased_ctls_low |=
2515 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2516 vmx->nested.nested_vmx_pinbased_ctls_high &=
2517 PIN_BASED_EXT_INTR_MASK |
2518 PIN_BASED_NMI_EXITING |
2519 PIN_BASED_VIRTUAL_NMIS;
2520 vmx->nested.nested_vmx_pinbased_ctls_high |=
2521 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2522 PIN_BASED_VMX_PREEMPTION_TIMER;
2523 if (vmx_cpu_uses_apicv(&vmx->vcpu))
2524 vmx->nested.nested_vmx_pinbased_ctls_high |=
2525 PIN_BASED_POSTED_INTR;
2528 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2529 vmx->nested.nested_vmx_exit_ctls_low,
2530 vmx->nested.nested_vmx_exit_ctls_high);
2531 vmx->nested.nested_vmx_exit_ctls_low =
2532 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2534 vmx->nested.nested_vmx_exit_ctls_high &=
2535 #ifdef CONFIG_X86_64
2536 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2538 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2539 vmx->nested.nested_vmx_exit_ctls_high |=
2540 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2541 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2542 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2544 if (vmx_mpx_supported())
2545 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2547 /* We support free control of debug control saving. */
2548 vmx->nested.nested_vmx_true_exit_ctls_low =
2549 vmx->nested.nested_vmx_exit_ctls_low &
2550 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2552 /* entry controls */
2553 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2554 vmx->nested.nested_vmx_entry_ctls_low,
2555 vmx->nested.nested_vmx_entry_ctls_high);
2556 vmx->nested.nested_vmx_entry_ctls_low =
2557 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2558 vmx->nested.nested_vmx_entry_ctls_high &=
2559 #ifdef CONFIG_X86_64
2560 VM_ENTRY_IA32E_MODE |
2562 VM_ENTRY_LOAD_IA32_PAT;
2563 vmx->nested.nested_vmx_entry_ctls_high |=
2564 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2565 if (vmx_mpx_supported())
2566 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2568 /* We support free control of debug control loading. */
2569 vmx->nested.nested_vmx_true_entry_ctls_low =
2570 vmx->nested.nested_vmx_entry_ctls_low &
2571 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2573 /* cpu-based controls */
2574 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2575 vmx->nested.nested_vmx_procbased_ctls_low,
2576 vmx->nested.nested_vmx_procbased_ctls_high);
2577 vmx->nested.nested_vmx_procbased_ctls_low =
2578 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2579 vmx->nested.nested_vmx_procbased_ctls_high &=
2580 CPU_BASED_VIRTUAL_INTR_PENDING |
2581 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2582 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2583 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2584 CPU_BASED_CR3_STORE_EXITING |
2585 #ifdef CONFIG_X86_64
2586 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2588 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2589 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2590 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2591 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2592 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2594 * We can allow some features even when not supported by the
2595 * hardware. For example, L1 can specify an MSR bitmap - and we
2596 * can use it to avoid exits to L1 - even when L0 runs L2
2597 * without MSR bitmaps.
2599 vmx->nested.nested_vmx_procbased_ctls_high |=
2600 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2601 CPU_BASED_USE_MSR_BITMAPS;
2603 /* We support free control of CR3 access interception. */
2604 vmx->nested.nested_vmx_true_procbased_ctls_low =
2605 vmx->nested.nested_vmx_procbased_ctls_low &
2606 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2608 /* secondary cpu-based controls */
2609 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2610 vmx->nested.nested_vmx_secondary_ctls_low,
2611 vmx->nested.nested_vmx_secondary_ctls_high);
2612 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2613 vmx->nested.nested_vmx_secondary_ctls_high &=
2614 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2615 SECONDARY_EXEC_RDTSCP |
2616 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2617 SECONDARY_EXEC_ENABLE_VPID |
2618 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2619 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2620 SECONDARY_EXEC_WBINVD_EXITING |
2621 SECONDARY_EXEC_XSAVES |
2622 SECONDARY_EXEC_PCOMMIT;
2625 /* nested EPT: emulate EPT also to L1 */
2626 vmx->nested.nested_vmx_secondary_ctls_high |=
2627 SECONDARY_EXEC_ENABLE_EPT;
2628 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2629 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2631 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2633 * For nested guests, we don't do anything specific
2634 * for single context invalidation. Hence, only advertise
2635 * support for global context invalidation.
2637 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2639 vmx->nested.nested_vmx_ept_caps = 0;
2642 * Old versions of KVM use the single-context version without
2643 * checking for support, so declare that it is supported even
2644 * though it is treated as global context. The alternative is
2645 * not failing the single-context invvpid, and it is worse.
2648 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2649 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2650 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2652 vmx->nested.nested_vmx_vpid_caps = 0;
2654 if (enable_unrestricted_guest)
2655 vmx->nested.nested_vmx_secondary_ctls_high |=
2656 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2658 /* miscellaneous data */
2659 rdmsr(MSR_IA32_VMX_MISC,
2660 vmx->nested.nested_vmx_misc_low,
2661 vmx->nested.nested_vmx_misc_high);
2662 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2663 vmx->nested.nested_vmx_misc_low |=
2664 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2665 VMX_MISC_ACTIVITY_HLT;
2666 vmx->nested.nested_vmx_misc_high = 0;
2669 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2672 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2674 return ((control & high) | low) == control;
2677 static inline u64 vmx_control_msr(u32 low, u32 high)
2679 return low | ((u64)high << 32);
2682 /* Returns 0 on success, non-0 otherwise. */
2683 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2685 struct vcpu_vmx *vmx = to_vmx(vcpu);
2687 switch (msr_index) {
2688 case MSR_IA32_VMX_BASIC:
2690 * This MSR reports some information about VMX support. We
2691 * should return information about the VMX we emulate for the
2692 * guest, and the VMCS structure we give it - not about the
2693 * VMX support of the underlying hardware.
2695 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2696 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2697 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2699 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2700 case MSR_IA32_VMX_PINBASED_CTLS:
2701 *pdata = vmx_control_msr(
2702 vmx->nested.nested_vmx_pinbased_ctls_low,
2703 vmx->nested.nested_vmx_pinbased_ctls_high);
2705 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2706 *pdata = vmx_control_msr(
2707 vmx->nested.nested_vmx_true_procbased_ctls_low,
2708 vmx->nested.nested_vmx_procbased_ctls_high);
2710 case MSR_IA32_VMX_PROCBASED_CTLS:
2711 *pdata = vmx_control_msr(
2712 vmx->nested.nested_vmx_procbased_ctls_low,
2713 vmx->nested.nested_vmx_procbased_ctls_high);
2715 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2716 *pdata = vmx_control_msr(
2717 vmx->nested.nested_vmx_true_exit_ctls_low,
2718 vmx->nested.nested_vmx_exit_ctls_high);
2720 case MSR_IA32_VMX_EXIT_CTLS:
2721 *pdata = vmx_control_msr(
2722 vmx->nested.nested_vmx_exit_ctls_low,
2723 vmx->nested.nested_vmx_exit_ctls_high);
2725 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2726 *pdata = vmx_control_msr(
2727 vmx->nested.nested_vmx_true_entry_ctls_low,
2728 vmx->nested.nested_vmx_entry_ctls_high);
2730 case MSR_IA32_VMX_ENTRY_CTLS:
2731 *pdata = vmx_control_msr(
2732 vmx->nested.nested_vmx_entry_ctls_low,
2733 vmx->nested.nested_vmx_entry_ctls_high);
2735 case MSR_IA32_VMX_MISC:
2736 *pdata = vmx_control_msr(
2737 vmx->nested.nested_vmx_misc_low,
2738 vmx->nested.nested_vmx_misc_high);
2741 * These MSRs specify bits which the guest must keep fixed (on or off)
2742 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2743 * We picked the standard core2 setting.
2745 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2746 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2747 case MSR_IA32_VMX_CR0_FIXED0:
2748 *pdata = VMXON_CR0_ALWAYSON;
2750 case MSR_IA32_VMX_CR0_FIXED1:
2753 case MSR_IA32_VMX_CR4_FIXED0:
2754 *pdata = VMXON_CR4_ALWAYSON;
2756 case MSR_IA32_VMX_CR4_FIXED1:
2759 case MSR_IA32_VMX_VMCS_ENUM:
2760 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2762 case MSR_IA32_VMX_PROCBASED_CTLS2:
2763 *pdata = vmx_control_msr(
2764 vmx->nested.nested_vmx_secondary_ctls_low,
2765 vmx->nested.nested_vmx_secondary_ctls_high);
2767 case MSR_IA32_VMX_EPT_VPID_CAP:
2768 /* Currently, no nested vpid support */
2769 *pdata = vmx->nested.nested_vmx_ept_caps |
2770 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2780 * Reads an msr value (of 'msr_index') into 'pdata'.
2781 * Returns 0 on success, non-0 otherwise.
2782 * Assumes vcpu_load() was already called.
2784 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2786 struct shared_msr_entry *msr;
2788 switch (msr_info->index) {
2789 #ifdef CONFIG_X86_64
2791 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2794 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2796 case MSR_KERNEL_GS_BASE:
2797 vmx_load_host_state(to_vmx(vcpu));
2798 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2802 return kvm_get_msr_common(vcpu, msr_info);
2804 msr_info->data = guest_read_tsc(vcpu);
2806 case MSR_IA32_SYSENTER_CS:
2807 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2809 case MSR_IA32_SYSENTER_EIP:
2810 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2812 case MSR_IA32_SYSENTER_ESP:
2813 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2815 case MSR_IA32_BNDCFGS:
2816 if (!vmx_mpx_supported())
2818 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2820 case MSR_IA32_FEATURE_CONTROL:
2821 if (!nested_vmx_allowed(vcpu))
2823 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2825 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2826 if (!nested_vmx_allowed(vcpu))
2828 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2830 if (!vmx_xsaves_supported())
2832 msr_info->data = vcpu->arch.ia32_xss;
2835 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2837 /* Otherwise falls through */
2839 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2841 msr_info->data = msr->data;
2844 return kvm_get_msr_common(vcpu, msr_info);
2850 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2853 * Writes msr value into into the appropriate "register".
2854 * Returns 0 on success, non-0 otherwise.
2855 * Assumes vcpu_load() was already called.
2857 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2859 struct vcpu_vmx *vmx = to_vmx(vcpu);
2860 struct shared_msr_entry *msr;
2862 u32 msr_index = msr_info->index;
2863 u64 data = msr_info->data;
2865 switch (msr_index) {
2867 ret = kvm_set_msr_common(vcpu, msr_info);
2869 #ifdef CONFIG_X86_64
2871 vmx_segment_cache_clear(vmx);
2872 vmcs_writel(GUEST_FS_BASE, data);
2875 vmx_segment_cache_clear(vmx);
2876 vmcs_writel(GUEST_GS_BASE, data);
2878 case MSR_KERNEL_GS_BASE:
2879 vmx_load_host_state(vmx);
2880 vmx->msr_guest_kernel_gs_base = data;
2883 case MSR_IA32_SYSENTER_CS:
2884 vmcs_write32(GUEST_SYSENTER_CS, data);
2886 case MSR_IA32_SYSENTER_EIP:
2887 vmcs_writel(GUEST_SYSENTER_EIP, data);
2889 case MSR_IA32_SYSENTER_ESP:
2890 vmcs_writel(GUEST_SYSENTER_ESP, data);
2892 case MSR_IA32_BNDCFGS:
2893 if (!vmx_mpx_supported())
2895 vmcs_write64(GUEST_BNDCFGS, data);
2898 kvm_write_tsc(vcpu, msr_info);
2900 case MSR_IA32_CR_PAT:
2901 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2902 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2904 vmcs_write64(GUEST_IA32_PAT, data);
2905 vcpu->arch.pat = data;
2908 ret = kvm_set_msr_common(vcpu, msr_info);
2910 case MSR_IA32_TSC_ADJUST:
2911 ret = kvm_set_msr_common(vcpu, msr_info);
2913 case MSR_IA32_FEATURE_CONTROL:
2914 if (!nested_vmx_allowed(vcpu) ||
2915 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2916 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2918 vmx->nested.msr_ia32_feature_control = data;
2919 if (msr_info->host_initiated && data == 0)
2920 vmx_leave_nested(vcpu);
2922 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2923 return 1; /* they are read-only */
2925 if (!vmx_xsaves_supported())
2928 * The only supported bit as of Skylake is bit 8, but
2929 * it is not supported on KVM.
2933 vcpu->arch.ia32_xss = data;
2934 if (vcpu->arch.ia32_xss != host_xss)
2935 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2936 vcpu->arch.ia32_xss, host_xss);
2938 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2941 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2943 /* Check reserved bit, higher 32 bits should be zero */
2944 if ((data >> 32) != 0)
2946 /* Otherwise falls through */
2948 msr = find_msr_entry(vmx, msr_index);
2950 u64 old_msr_data = msr->data;
2952 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2954 ret = kvm_set_shared_msr(msr->index, msr->data,
2958 msr->data = old_msr_data;
2962 ret = kvm_set_msr_common(vcpu, msr_info);
2968 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2970 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2973 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2976 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2978 case VCPU_EXREG_PDPTR:
2980 ept_save_pdptrs(vcpu);
2987 static __init int cpu_has_kvm_support(void)
2989 return cpu_has_vmx();
2992 static __init int vmx_disabled_by_bios(void)
2996 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2997 if (msr & FEATURE_CONTROL_LOCKED) {
2998 /* launched w/ TXT and VMX disabled */
2999 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3002 /* launched w/o TXT and VMX only enabled w/ TXT */
3003 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3004 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3005 && !tboot_enabled()) {
3006 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3007 "activate TXT before enabling KVM\n");
3010 /* launched w/o TXT and VMX disabled */
3011 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3012 && !tboot_enabled())
3019 static void kvm_cpu_vmxon(u64 addr)
3021 asm volatile (ASM_VMX_VMXON_RAX
3022 : : "a"(&addr), "m"(addr)
3026 static int hardware_enable(void)
3028 int cpu = raw_smp_processor_id();
3029 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3032 if (cr4_read_shadow() & X86_CR4_VMXE)
3035 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3036 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3037 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3040 * Now we can enable the vmclear operation in kdump
3041 * since the loaded_vmcss_on_cpu list on this cpu
3042 * has been initialized.
3044 * Though the cpu is not in VMX operation now, there
3045 * is no problem to enable the vmclear operation
3046 * for the loaded_vmcss_on_cpu list is empty!
3048 crash_enable_local_vmclear(cpu);
3050 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3052 test_bits = FEATURE_CONTROL_LOCKED;
3053 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3054 if (tboot_enabled())
3055 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3057 if ((old & test_bits) != test_bits) {
3058 /* enable and lock */
3059 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3061 cr4_set_bits(X86_CR4_VMXE);
3063 if (vmm_exclusive) {
3064 kvm_cpu_vmxon(phys_addr);
3068 native_store_gdt(this_cpu_ptr(&host_gdt));
3073 static void vmclear_local_loaded_vmcss(void)
3075 int cpu = raw_smp_processor_id();
3076 struct loaded_vmcs *v, *n;
3078 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3079 loaded_vmcss_on_cpu_link)
3080 __loaded_vmcs_clear(v);
3084 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3087 static void kvm_cpu_vmxoff(void)
3089 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3092 static void hardware_disable(void)
3094 if (vmm_exclusive) {
3095 vmclear_local_loaded_vmcss();
3098 cr4_clear_bits(X86_CR4_VMXE);
3101 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3102 u32 msr, u32 *result)
3104 u32 vmx_msr_low, vmx_msr_high;
3105 u32 ctl = ctl_min | ctl_opt;
3107 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3109 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3110 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3112 /* Ensure minimum (required) set of control bits are supported. */
3120 static __init bool allow_1_setting(u32 msr, u32 ctl)
3122 u32 vmx_msr_low, vmx_msr_high;
3124 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3125 return vmx_msr_high & ctl;
3128 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3130 u32 vmx_msr_low, vmx_msr_high;
3131 u32 min, opt, min2, opt2;
3132 u32 _pin_based_exec_control = 0;
3133 u32 _cpu_based_exec_control = 0;
3134 u32 _cpu_based_2nd_exec_control = 0;
3135 u32 _vmexit_control = 0;
3136 u32 _vmentry_control = 0;
3138 min = CPU_BASED_HLT_EXITING |
3139 #ifdef CONFIG_X86_64
3140 CPU_BASED_CR8_LOAD_EXITING |
3141 CPU_BASED_CR8_STORE_EXITING |
3143 CPU_BASED_CR3_LOAD_EXITING |
3144 CPU_BASED_CR3_STORE_EXITING |
3145 CPU_BASED_USE_IO_BITMAPS |
3146 CPU_BASED_MOV_DR_EXITING |
3147 CPU_BASED_USE_TSC_OFFSETING |
3148 CPU_BASED_MWAIT_EXITING |
3149 CPU_BASED_MONITOR_EXITING |
3150 CPU_BASED_INVLPG_EXITING |
3151 CPU_BASED_RDPMC_EXITING;
3153 opt = CPU_BASED_TPR_SHADOW |
3154 CPU_BASED_USE_MSR_BITMAPS |
3155 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3156 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3157 &_cpu_based_exec_control) < 0)
3159 #ifdef CONFIG_X86_64
3160 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3161 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3162 ~CPU_BASED_CR8_STORE_EXITING;
3164 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3166 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3167 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3168 SECONDARY_EXEC_WBINVD_EXITING |
3169 SECONDARY_EXEC_ENABLE_VPID |
3170 SECONDARY_EXEC_ENABLE_EPT |
3171 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3172 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3173 SECONDARY_EXEC_RDTSCP |
3174 SECONDARY_EXEC_ENABLE_INVPCID |
3175 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3176 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3177 SECONDARY_EXEC_SHADOW_VMCS |
3178 SECONDARY_EXEC_XSAVES |
3179 SECONDARY_EXEC_ENABLE_PML |
3180 SECONDARY_EXEC_PCOMMIT |
3181 SECONDARY_EXEC_TSC_SCALING;
3182 if (adjust_vmx_controls(min2, opt2,
3183 MSR_IA32_VMX_PROCBASED_CTLS2,
3184 &_cpu_based_2nd_exec_control) < 0)
3187 #ifndef CONFIG_X86_64
3188 if (!(_cpu_based_2nd_exec_control &
3189 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3190 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3193 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3194 _cpu_based_2nd_exec_control &= ~(
3195 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3196 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3197 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3199 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3200 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3202 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3203 CPU_BASED_CR3_STORE_EXITING |
3204 CPU_BASED_INVLPG_EXITING);
3205 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3206 vmx_capability.ept, vmx_capability.vpid);
3209 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3210 #ifdef CONFIG_X86_64
3211 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3213 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3214 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3215 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3216 &_vmexit_control) < 0)
3219 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3220 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3221 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3222 &_pin_based_exec_control) < 0)
3225 if (!(_cpu_based_2nd_exec_control &
3226 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3227 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3228 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3230 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3231 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3232 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3233 &_vmentry_control) < 0)
3236 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3238 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3239 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3242 #ifdef CONFIG_X86_64
3243 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3244 if (vmx_msr_high & (1u<<16))
3248 /* Require Write-Back (WB) memory type for VMCS accesses. */
3249 if (((vmx_msr_high >> 18) & 15) != 6)
3252 vmcs_conf->size = vmx_msr_high & 0x1fff;
3253 vmcs_conf->order = get_order(vmcs_config.size);
3254 vmcs_conf->revision_id = vmx_msr_low;
3256 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3257 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3258 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3259 vmcs_conf->vmexit_ctrl = _vmexit_control;
3260 vmcs_conf->vmentry_ctrl = _vmentry_control;
3262 cpu_has_load_ia32_efer =
3263 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3264 VM_ENTRY_LOAD_IA32_EFER)
3265 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3266 VM_EXIT_LOAD_IA32_EFER);
3268 cpu_has_load_perf_global_ctrl =
3269 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3270 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3271 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3272 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3275 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3276 * but due to arrata below it can't be used. Workaround is to use
3277 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3279 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3284 * BC86,AAY89,BD102 (model 44)
3288 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3289 switch (boot_cpu_data.x86_model) {
3295 cpu_has_load_perf_global_ctrl = false;
3296 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3297 "does not work properly. Using workaround\n");
3305 rdmsrl(MSR_IA32_XSS, host_xss);
3310 static struct vmcs *alloc_vmcs_cpu(int cpu)
3312 int node = cpu_to_node(cpu);
3316 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3319 vmcs = page_address(pages);
3320 memset(vmcs, 0, vmcs_config.size);
3321 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3325 static struct vmcs *alloc_vmcs(void)
3327 return alloc_vmcs_cpu(raw_smp_processor_id());
3330 static void free_vmcs(struct vmcs *vmcs)
3332 free_pages((unsigned long)vmcs, vmcs_config.order);
3336 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3338 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3340 if (!loaded_vmcs->vmcs)
3342 loaded_vmcs_clear(loaded_vmcs);
3343 free_vmcs(loaded_vmcs->vmcs);
3344 loaded_vmcs->vmcs = NULL;
3347 static void free_kvm_area(void)
3351 for_each_possible_cpu(cpu) {
3352 free_vmcs(per_cpu(vmxarea, cpu));
3353 per_cpu(vmxarea, cpu) = NULL;
3357 static void init_vmcs_shadow_fields(void)
3361 /* No checks for read only fields yet */
3363 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3364 switch (shadow_read_write_fields[i]) {
3366 if (!vmx_mpx_supported())
3374 shadow_read_write_fields[j] =
3375 shadow_read_write_fields[i];
3378 max_shadow_read_write_fields = j;
3380 /* shadowed fields guest access without vmexit */
3381 for (i = 0; i < max_shadow_read_write_fields; i++) {
3382 clear_bit(shadow_read_write_fields[i],
3383 vmx_vmwrite_bitmap);
3384 clear_bit(shadow_read_write_fields[i],
3387 for (i = 0; i < max_shadow_read_only_fields; i++)
3388 clear_bit(shadow_read_only_fields[i],
3392 static __init int alloc_kvm_area(void)
3396 for_each_possible_cpu(cpu) {
3399 vmcs = alloc_vmcs_cpu(cpu);
3405 per_cpu(vmxarea, cpu) = vmcs;
3410 static bool emulation_required(struct kvm_vcpu *vcpu)
3412 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3415 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3416 struct kvm_segment *save)
3418 if (!emulate_invalid_guest_state) {
3420 * CS and SS RPL should be equal during guest entry according
3421 * to VMX spec, but in reality it is not always so. Since vcpu
3422 * is in the middle of the transition from real mode to
3423 * protected mode it is safe to assume that RPL 0 is a good
3426 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3427 save->selector &= ~SEGMENT_RPL_MASK;
3428 save->dpl = save->selector & SEGMENT_RPL_MASK;
3431 vmx_set_segment(vcpu, save, seg);
3434 static void enter_pmode(struct kvm_vcpu *vcpu)
3436 unsigned long flags;
3437 struct vcpu_vmx *vmx = to_vmx(vcpu);
3440 * Update real mode segment cache. It may be not up-to-date if sement
3441 * register was written while vcpu was in a guest mode.
3443 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3444 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3445 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3446 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3447 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3448 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3450 vmx->rmode.vm86_active = 0;
3452 vmx_segment_cache_clear(vmx);
3454 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3456 flags = vmcs_readl(GUEST_RFLAGS);
3457 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3458 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3459 vmcs_writel(GUEST_RFLAGS, flags);
3461 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3462 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3464 update_exception_bitmap(vcpu);
3466 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3467 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3468 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3469 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3470 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3471 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3474 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3476 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3477 struct kvm_segment var = *save;
3480 if (seg == VCPU_SREG_CS)
3483 if (!emulate_invalid_guest_state) {
3484 var.selector = var.base >> 4;
3485 var.base = var.base & 0xffff0;
3495 if (save->base & 0xf)
3496 printk_once(KERN_WARNING "kvm: segment base is not "
3497 "paragraph aligned when entering "
3498 "protected mode (seg=%d)", seg);
3501 vmcs_write16(sf->selector, var.selector);
3502 vmcs_write32(sf->base, var.base);
3503 vmcs_write32(sf->limit, var.limit);
3504 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3507 static void enter_rmode(struct kvm_vcpu *vcpu)
3509 unsigned long flags;
3510 struct vcpu_vmx *vmx = to_vmx(vcpu);
3512 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3513 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3514 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3515 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3516 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3517 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3518 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3520 vmx->rmode.vm86_active = 1;
3523 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3524 * vcpu. Warn the user that an update is overdue.
3526 if (!vcpu->kvm->arch.tss_addr)
3527 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3528 "called before entering vcpu\n");
3530 vmx_segment_cache_clear(vmx);
3532 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3533 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3534 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3536 flags = vmcs_readl(GUEST_RFLAGS);
3537 vmx->rmode.save_rflags = flags;
3539 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3541 vmcs_writel(GUEST_RFLAGS, flags);
3542 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3543 update_exception_bitmap(vcpu);
3545 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3546 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3547 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3548 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3549 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3550 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3552 kvm_mmu_reset_context(vcpu);
3555 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3557 struct vcpu_vmx *vmx = to_vmx(vcpu);
3558 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3564 * Force kernel_gs_base reloading before EFER changes, as control
3565 * of this msr depends on is_long_mode().
3567 vmx_load_host_state(to_vmx(vcpu));
3568 vcpu->arch.efer = efer;
3569 if (efer & EFER_LMA) {
3570 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3573 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3575 msr->data = efer & ~EFER_LME;
3580 #ifdef CONFIG_X86_64
3582 static void enter_lmode(struct kvm_vcpu *vcpu)
3586 vmx_segment_cache_clear(to_vmx(vcpu));
3588 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3589 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3590 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3592 vmcs_write32(GUEST_TR_AR_BYTES,
3593 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3594 | VMX_AR_TYPE_BUSY_64_TSS);
3596 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3599 static void exit_lmode(struct kvm_vcpu *vcpu)
3601 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3602 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3607 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3609 vpid_sync_context(vpid);
3611 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3613 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3617 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3619 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3622 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3624 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3626 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3627 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3630 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3632 if (enable_ept && is_paging(vcpu))
3633 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3634 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3637 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3639 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3641 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3642 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3645 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3647 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3649 if (!test_bit(VCPU_EXREG_PDPTR,
3650 (unsigned long *)&vcpu->arch.regs_dirty))
3653 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3654 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3655 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3656 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3657 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3661 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3663 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3665 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3666 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3667 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3668 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3669 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3672 __set_bit(VCPU_EXREG_PDPTR,
3673 (unsigned long *)&vcpu->arch.regs_avail);
3674 __set_bit(VCPU_EXREG_PDPTR,
3675 (unsigned long *)&vcpu->arch.regs_dirty);
3678 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3680 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3682 struct kvm_vcpu *vcpu)
3684 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3685 vmx_decache_cr3(vcpu);
3686 if (!(cr0 & X86_CR0_PG)) {
3687 /* From paging/starting to nonpaging */
3688 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3689 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3690 (CPU_BASED_CR3_LOAD_EXITING |
3691 CPU_BASED_CR3_STORE_EXITING));
3692 vcpu->arch.cr0 = cr0;
3693 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3694 } else if (!is_paging(vcpu)) {
3695 /* From nonpaging to paging */
3696 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3697 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3698 ~(CPU_BASED_CR3_LOAD_EXITING |
3699 CPU_BASED_CR3_STORE_EXITING));
3700 vcpu->arch.cr0 = cr0;
3701 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3704 if (!(cr0 & X86_CR0_WP))
3705 *hw_cr0 &= ~X86_CR0_WP;
3708 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3710 struct vcpu_vmx *vmx = to_vmx(vcpu);
3711 unsigned long hw_cr0;
3713 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3714 if (enable_unrestricted_guest)
3715 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3717 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3719 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3722 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3726 #ifdef CONFIG_X86_64
3727 if (vcpu->arch.efer & EFER_LME) {
3728 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3730 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3736 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3738 if (!vcpu->fpu_active)
3739 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3741 vmcs_writel(CR0_READ_SHADOW, cr0);
3742 vmcs_writel(GUEST_CR0, hw_cr0);
3743 vcpu->arch.cr0 = cr0;
3745 /* depends on vcpu->arch.cr0 to be set to a new value */
3746 vmx->emulation_required = emulation_required(vcpu);
3749 static u64 construct_eptp(unsigned long root_hpa)
3753 /* TODO write the value reading from MSR */
3754 eptp = VMX_EPT_DEFAULT_MT |
3755 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3756 if (enable_ept_ad_bits)
3757 eptp |= VMX_EPT_AD_ENABLE_BIT;
3758 eptp |= (root_hpa & PAGE_MASK);
3763 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3765 unsigned long guest_cr3;
3770 eptp = construct_eptp(cr3);
3771 vmcs_write64(EPT_POINTER, eptp);
3772 if (is_paging(vcpu) || is_guest_mode(vcpu))
3773 guest_cr3 = kvm_read_cr3(vcpu);
3775 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3776 ept_load_pdptrs(vcpu);
3779 vmx_flush_tlb(vcpu);
3780 vmcs_writel(GUEST_CR3, guest_cr3);
3783 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3786 * Pass through host's Machine Check Enable value to hw_cr4, which
3787 * is in force while we are in guest mode. Do not let guests control
3788 * this bit, even if host CR4.MCE == 0.
3790 unsigned long hw_cr4 =
3791 (cr4_read_shadow() & X86_CR4_MCE) |
3792 (cr4 & ~X86_CR4_MCE) |
3793 (to_vmx(vcpu)->rmode.vm86_active ?
3794 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3796 if (cr4 & X86_CR4_VMXE) {
3798 * To use VMXON (and later other VMX instructions), a guest
3799 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3800 * So basically the check on whether to allow nested VMX
3803 if (!nested_vmx_allowed(vcpu))
3806 if (to_vmx(vcpu)->nested.vmxon &&
3807 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3810 vcpu->arch.cr4 = cr4;
3812 if (!is_paging(vcpu)) {
3813 hw_cr4 &= ~X86_CR4_PAE;
3814 hw_cr4 |= X86_CR4_PSE;
3815 } else if (!(cr4 & X86_CR4_PAE)) {
3816 hw_cr4 &= ~X86_CR4_PAE;
3820 if (!enable_unrestricted_guest && !is_paging(vcpu))
3822 * SMEP/SMAP is disabled if CPU is in non-paging mode in
3823 * hardware. However KVM always uses paging mode without
3824 * unrestricted guest.
3825 * To emulate this behavior, SMEP/SMAP needs to be manually
3826 * disabled when guest switches to non-paging mode.
3828 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3830 vmcs_writel(CR4_READ_SHADOW, cr4);
3831 vmcs_writel(GUEST_CR4, hw_cr4);
3835 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3836 struct kvm_segment *var, int seg)
3838 struct vcpu_vmx *vmx = to_vmx(vcpu);
3841 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3842 *var = vmx->rmode.segs[seg];
3843 if (seg == VCPU_SREG_TR
3844 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3846 var->base = vmx_read_guest_seg_base(vmx, seg);
3847 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3850 var->base = vmx_read_guest_seg_base(vmx, seg);
3851 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3852 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3853 ar = vmx_read_guest_seg_ar(vmx, seg);
3854 var->unusable = (ar >> 16) & 1;
3855 var->type = ar & 15;
3856 var->s = (ar >> 4) & 1;
3857 var->dpl = (ar >> 5) & 3;
3859 * Some userspaces do not preserve unusable property. Since usable
3860 * segment has to be present according to VMX spec we can use present
3861 * property to amend userspace bug by making unusable segment always
3862 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3863 * segment as unusable.
3865 var->present = !var->unusable;
3866 var->avl = (ar >> 12) & 1;
3867 var->l = (ar >> 13) & 1;
3868 var->db = (ar >> 14) & 1;
3869 var->g = (ar >> 15) & 1;
3872 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3874 struct kvm_segment s;
3876 if (to_vmx(vcpu)->rmode.vm86_active) {
3877 vmx_get_segment(vcpu, &s, seg);
3880 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3883 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3885 struct vcpu_vmx *vmx = to_vmx(vcpu);
3887 if (unlikely(vmx->rmode.vm86_active))
3890 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3891 return VMX_AR_DPL(ar);
3895 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3899 if (var->unusable || !var->present)
3902 ar = var->type & 15;
3903 ar |= (var->s & 1) << 4;
3904 ar |= (var->dpl & 3) << 5;
3905 ar |= (var->present & 1) << 7;
3906 ar |= (var->avl & 1) << 12;
3907 ar |= (var->l & 1) << 13;
3908 ar |= (var->db & 1) << 14;
3909 ar |= (var->g & 1) << 15;
3915 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3916 struct kvm_segment *var, int seg)
3918 struct vcpu_vmx *vmx = to_vmx(vcpu);
3919 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3921 vmx_segment_cache_clear(vmx);
3923 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3924 vmx->rmode.segs[seg] = *var;
3925 if (seg == VCPU_SREG_TR)
3926 vmcs_write16(sf->selector, var->selector);
3928 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3932 vmcs_writel(sf->base, var->base);
3933 vmcs_write32(sf->limit, var->limit);
3934 vmcs_write16(sf->selector, var->selector);
3937 * Fix the "Accessed" bit in AR field of segment registers for older
3939 * IA32 arch specifies that at the time of processor reset the
3940 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3941 * is setting it to 0 in the userland code. This causes invalid guest
3942 * state vmexit when "unrestricted guest" mode is turned on.
3943 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3944 * tree. Newer qemu binaries with that qemu fix would not need this
3947 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3948 var->type |= 0x1; /* Accessed */
3950 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3953 vmx->emulation_required = emulation_required(vcpu);
3956 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3958 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3960 *db = (ar >> 14) & 1;
3961 *l = (ar >> 13) & 1;
3964 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3966 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3967 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3970 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3972 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3973 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3976 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3978 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3979 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3982 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3984 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3985 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3988 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3990 struct kvm_segment var;
3993 vmx_get_segment(vcpu, &var, seg);
3995 if (seg == VCPU_SREG_CS)
3997 ar = vmx_segment_access_rights(&var);
3999 if (var.base != (var.selector << 4))
4001 if (var.limit != 0xffff)
4009 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4011 struct kvm_segment cs;
4012 unsigned int cs_rpl;
4014 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4015 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4019 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4023 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4024 if (cs.dpl > cs_rpl)
4027 if (cs.dpl != cs_rpl)
4033 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4037 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4039 struct kvm_segment ss;
4040 unsigned int ss_rpl;
4042 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4043 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4047 if (ss.type != 3 && ss.type != 7)
4051 if (ss.dpl != ss_rpl) /* DPL != RPL */
4059 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4061 struct kvm_segment var;
4064 vmx_get_segment(vcpu, &var, seg);
4065 rpl = var.selector & SEGMENT_RPL_MASK;
4073 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4074 if (var.dpl < rpl) /* DPL < RPL */
4078 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4084 static bool tr_valid(struct kvm_vcpu *vcpu)
4086 struct kvm_segment tr;
4088 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4092 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4094 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4102 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4104 struct kvm_segment ldtr;
4106 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4110 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4120 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4122 struct kvm_segment cs, ss;
4124 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4125 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4127 return ((cs.selector & SEGMENT_RPL_MASK) ==
4128 (ss.selector & SEGMENT_RPL_MASK));
4132 * Check if guest state is valid. Returns true if valid, false if
4134 * We assume that registers are always usable
4136 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4138 if (enable_unrestricted_guest)
4141 /* real mode guest state checks */
4142 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4143 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4145 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4147 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4149 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4151 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4153 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4156 /* protected mode guest state checks */
4157 if (!cs_ss_rpl_check(vcpu))
4159 if (!code_segment_valid(vcpu))
4161 if (!stack_segment_valid(vcpu))
4163 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4165 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4167 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4169 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4171 if (!tr_valid(vcpu))
4173 if (!ldtr_valid(vcpu))
4177 * - Add checks on RIP
4178 * - Add checks on RFLAGS
4184 static int init_rmode_tss(struct kvm *kvm)
4190 idx = srcu_read_lock(&kvm->srcu);
4191 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4192 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4195 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4196 r = kvm_write_guest_page(kvm, fn++, &data,
4197 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4200 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4203 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4207 r = kvm_write_guest_page(kvm, fn, &data,
4208 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4211 srcu_read_unlock(&kvm->srcu, idx);
4215 static int init_rmode_identity_map(struct kvm *kvm)
4218 pfn_t identity_map_pfn;
4224 /* Protect kvm->arch.ept_identity_pagetable_done. */
4225 mutex_lock(&kvm->slots_lock);
4227 if (likely(kvm->arch.ept_identity_pagetable_done))
4230 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4232 r = alloc_identity_pagetable(kvm);
4236 idx = srcu_read_lock(&kvm->srcu);
4237 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4240 /* Set up identity-mapping pagetable for EPT in real mode */
4241 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4242 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4243 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4244 r = kvm_write_guest_page(kvm, identity_map_pfn,
4245 &tmp, i * sizeof(tmp), sizeof(tmp));
4249 kvm->arch.ept_identity_pagetable_done = true;
4252 srcu_read_unlock(&kvm->srcu, idx);
4255 mutex_unlock(&kvm->slots_lock);
4259 static void seg_setup(int seg)
4261 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4264 vmcs_write16(sf->selector, 0);
4265 vmcs_writel(sf->base, 0);
4266 vmcs_write32(sf->limit, 0xffff);
4268 if (seg == VCPU_SREG_CS)
4269 ar |= 0x08; /* code segment */
4271 vmcs_write32(sf->ar_bytes, ar);
4274 static int alloc_apic_access_page(struct kvm *kvm)
4279 mutex_lock(&kvm->slots_lock);
4280 if (kvm->arch.apic_access_page_done)
4282 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4283 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4287 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4288 if (is_error_page(page)) {
4294 * Do not pin the page in memory, so that memory hot-unplug
4295 * is able to migrate it.
4298 kvm->arch.apic_access_page_done = true;
4300 mutex_unlock(&kvm->slots_lock);
4304 static int alloc_identity_pagetable(struct kvm *kvm)
4306 /* Called with kvm->slots_lock held. */
4310 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4312 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4313 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4318 static int allocate_vpid(void)
4324 spin_lock(&vmx_vpid_lock);
4325 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4326 if (vpid < VMX_NR_VPIDS)
4327 __set_bit(vpid, vmx_vpid_bitmap);
4330 spin_unlock(&vmx_vpid_lock);
4334 static void free_vpid(int vpid)
4336 if (!enable_vpid || vpid == 0)
4338 spin_lock(&vmx_vpid_lock);
4339 __clear_bit(vpid, vmx_vpid_bitmap);
4340 spin_unlock(&vmx_vpid_lock);
4343 #define MSR_TYPE_R 1
4344 #define MSR_TYPE_W 2
4345 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4348 int f = sizeof(unsigned long);
4350 if (!cpu_has_vmx_msr_bitmap())
4354 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4355 * have the write-low and read-high bitmap offsets the wrong way round.
4356 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4358 if (msr <= 0x1fff) {
4359 if (type & MSR_TYPE_R)
4361 __clear_bit(msr, msr_bitmap + 0x000 / f);
4363 if (type & MSR_TYPE_W)
4365 __clear_bit(msr, msr_bitmap + 0x800 / f);
4367 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4369 if (type & MSR_TYPE_R)
4371 __clear_bit(msr, msr_bitmap + 0x400 / f);
4373 if (type & MSR_TYPE_W)
4375 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4380 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4383 int f = sizeof(unsigned long);
4385 if (!cpu_has_vmx_msr_bitmap())
4389 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4390 * have the write-low and read-high bitmap offsets the wrong way round.
4391 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4393 if (msr <= 0x1fff) {
4394 if (type & MSR_TYPE_R)
4396 __set_bit(msr, msr_bitmap + 0x000 / f);
4398 if (type & MSR_TYPE_W)
4400 __set_bit(msr, msr_bitmap + 0x800 / f);
4402 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4404 if (type & MSR_TYPE_R)
4406 __set_bit(msr, msr_bitmap + 0x400 / f);
4408 if (type & MSR_TYPE_W)
4410 __set_bit(msr, msr_bitmap + 0xc00 / f);
4416 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4417 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4419 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4420 unsigned long *msr_bitmap_nested,
4423 int f = sizeof(unsigned long);
4425 if (!cpu_has_vmx_msr_bitmap()) {
4431 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4432 * have the write-low and read-high bitmap offsets the wrong way round.
4433 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4435 if (msr <= 0x1fff) {
4436 if (type & MSR_TYPE_R &&
4437 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4439 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4441 if (type & MSR_TYPE_W &&
4442 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4444 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4446 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4448 if (type & MSR_TYPE_R &&
4449 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4451 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4453 if (type & MSR_TYPE_W &&
4454 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4456 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4461 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4464 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4465 msr, MSR_TYPE_R | MSR_TYPE_W);
4466 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4467 msr, MSR_TYPE_R | MSR_TYPE_W);
4470 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4472 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4474 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4478 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4480 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4482 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4486 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4488 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4490 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4494 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4496 return enable_apicv && lapic_in_kernel(vcpu);
4499 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4501 struct vcpu_vmx *vmx = to_vmx(vcpu);
4506 if (vmx->nested.pi_desc &&
4507 vmx->nested.pi_pending) {
4508 vmx->nested.pi_pending = false;
4509 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4512 max_irr = find_last_bit(
4513 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4518 vapic_page = kmap(vmx->nested.virtual_apic_page);
4523 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4524 kunmap(vmx->nested.virtual_apic_page);
4526 status = vmcs_read16(GUEST_INTR_STATUS);
4527 if ((u8)max_irr > ((u8)status & 0xff)) {
4529 status |= (u8)max_irr;
4530 vmcs_write16(GUEST_INTR_STATUS, status);
4536 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4539 if (vcpu->mode == IN_GUEST_MODE) {
4540 struct vcpu_vmx *vmx = to_vmx(vcpu);
4543 * Currently, we don't support urgent interrupt,
4544 * all interrupts are recognized as non-urgent
4545 * interrupt, so we cannot post interrupts when
4548 * If the vcpu is in guest mode, it means it is
4549 * running instead of being scheduled out and
4550 * waiting in the run queue, and that's the only
4551 * case when 'SN' is set currently, warning if
4554 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4556 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4557 POSTED_INTR_VECTOR);
4564 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4567 struct vcpu_vmx *vmx = to_vmx(vcpu);
4569 if (is_guest_mode(vcpu) &&
4570 vector == vmx->nested.posted_intr_nv) {
4571 /* the PIR and ON have been set by L1. */
4572 kvm_vcpu_trigger_posted_interrupt(vcpu);
4574 * If a posted intr is not recognized by hardware,
4575 * we will accomplish it in the next vmentry.
4577 vmx->nested.pi_pending = true;
4578 kvm_make_request(KVM_REQ_EVENT, vcpu);
4584 * Send interrupt to vcpu via posted interrupt way.
4585 * 1. If target vcpu is running(non-root mode), send posted interrupt
4586 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4587 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4588 * interrupt from PIR in next vmentry.
4590 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4592 struct vcpu_vmx *vmx = to_vmx(vcpu);
4595 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4599 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4602 r = pi_test_and_set_on(&vmx->pi_desc);
4603 kvm_make_request(KVM_REQ_EVENT, vcpu);
4604 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4605 kvm_vcpu_kick(vcpu);
4608 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4610 struct vcpu_vmx *vmx = to_vmx(vcpu);
4612 if (!pi_test_and_clear_on(&vmx->pi_desc))
4615 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4618 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4624 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4625 * will not change in the lifetime of the guest.
4626 * Note that host-state that does change is set elsewhere. E.g., host-state
4627 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4629 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4636 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4637 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4639 /* Save the most likely value for this task's CR4 in the VMCS. */
4640 cr4 = cr4_read_shadow();
4641 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4642 vmx->host_state.vmcs_host_cr4 = cr4;
4644 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4645 #ifdef CONFIG_X86_64
4647 * Load null selectors, so we can avoid reloading them in
4648 * __vmx_load_host_state(), in case userspace uses the null selectors
4649 * too (the expected case).
4651 vmcs_write16(HOST_DS_SELECTOR, 0);
4652 vmcs_write16(HOST_ES_SELECTOR, 0);
4654 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4655 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4657 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4658 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4660 native_store_idt(&dt);
4661 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4662 vmx->host_idt_base = dt.address;
4664 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4666 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4667 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4668 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4669 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4671 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4672 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4673 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4677 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4679 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4681 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4682 if (is_guest_mode(&vmx->vcpu))
4683 vmx->vcpu.arch.cr4_guest_owned_bits &=
4684 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4685 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4688 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4690 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4692 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4693 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4694 return pin_based_exec_ctrl;
4697 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4699 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4701 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4702 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4704 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4705 exec_control &= ~CPU_BASED_TPR_SHADOW;
4706 #ifdef CONFIG_X86_64
4707 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4708 CPU_BASED_CR8_LOAD_EXITING;
4712 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4713 CPU_BASED_CR3_LOAD_EXITING |
4714 CPU_BASED_INVLPG_EXITING;
4715 return exec_control;
4718 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4720 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4721 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4722 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4724 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4726 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4727 enable_unrestricted_guest = 0;
4728 /* Enable INVPCID for non-ept guests may cause performance regression. */
4729 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4731 if (!enable_unrestricted_guest)
4732 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4734 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4735 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4736 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4737 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4738 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4739 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4741 We can NOT enable shadow_vmcs here because we don't have yet
4744 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4747 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4749 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4750 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4752 return exec_control;
4755 static void ept_set_mmio_spte_mask(void)
4758 * EPT Misconfigurations can be generated if the value of bits 2:0
4759 * of an EPT paging-structure entry is 110b (write/execute).
4760 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4763 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4766 #define VMX_XSS_EXIT_BITMAP 0
4768 * Sets up the vmcs for emulated real mode.
4770 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4772 #ifdef CONFIG_X86_64
4778 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4779 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4781 if (enable_shadow_vmcs) {
4782 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4783 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4785 if (cpu_has_vmx_msr_bitmap())
4786 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4788 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4791 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4793 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4795 if (cpu_has_secondary_exec_ctrls())
4796 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4797 vmx_secondary_exec_control(vmx));
4799 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4800 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4801 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4802 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4803 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4805 vmcs_write16(GUEST_INTR_STATUS, 0);
4807 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4808 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4812 vmcs_write32(PLE_GAP, ple_gap);
4813 vmx->ple_window = ple_window;
4814 vmx->ple_window_dirty = true;
4817 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4818 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4819 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4821 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4822 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4823 vmx_set_constant_host_state(vmx);
4824 #ifdef CONFIG_X86_64
4825 rdmsrl(MSR_FS_BASE, a);
4826 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4827 rdmsrl(MSR_GS_BASE, a);
4828 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4830 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4831 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4834 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4835 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4836 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4837 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4838 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4840 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4841 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4843 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4844 u32 index = vmx_msr_index[i];
4845 u32 data_low, data_high;
4848 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4850 if (wrmsr_safe(index, data_low, data_high) < 0)
4852 vmx->guest_msrs[j].index = i;
4853 vmx->guest_msrs[j].data = 0;
4854 vmx->guest_msrs[j].mask = -1ull;
4859 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4861 /* 22.2.1, 20.8.1 */
4862 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4864 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4865 set_cr4_guest_host_mask(vmx);
4867 if (vmx_xsaves_supported())
4868 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4871 ASSERT(vmx->pml_pg);
4872 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4873 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4879 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4881 struct vcpu_vmx *vmx = to_vmx(vcpu);
4882 struct msr_data apic_base_msr;
4885 vmx->rmode.vm86_active = 0;
4887 vmx->soft_vnmi_blocked = 0;
4889 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4890 kvm_set_cr8(vcpu, 0);
4893 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4894 MSR_IA32_APICBASE_ENABLE;
4895 if (kvm_vcpu_is_reset_bsp(vcpu))
4896 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4897 apic_base_msr.host_initiated = true;
4898 kvm_set_apic_base(vcpu, &apic_base_msr);
4901 vmx_segment_cache_clear(vmx);
4903 seg_setup(VCPU_SREG_CS);
4904 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4905 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4907 seg_setup(VCPU_SREG_DS);
4908 seg_setup(VCPU_SREG_ES);
4909 seg_setup(VCPU_SREG_FS);
4910 seg_setup(VCPU_SREG_GS);
4911 seg_setup(VCPU_SREG_SS);
4913 vmcs_write16(GUEST_TR_SELECTOR, 0);
4914 vmcs_writel(GUEST_TR_BASE, 0);
4915 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4916 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4918 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4919 vmcs_writel(GUEST_LDTR_BASE, 0);
4920 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4921 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4924 vmcs_write32(GUEST_SYSENTER_CS, 0);
4925 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4926 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4927 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4930 vmcs_writel(GUEST_RFLAGS, 0x02);
4931 kvm_rip_write(vcpu, 0xfff0);
4933 vmcs_writel(GUEST_GDTR_BASE, 0);
4934 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4936 vmcs_writel(GUEST_IDTR_BASE, 0);
4937 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4939 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4940 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4941 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4947 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4948 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4949 if (cpu_need_tpr_shadow(vcpu))
4950 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4951 __pa(vcpu->arch.apic->regs));
4952 vmcs_write32(TPR_THRESHOLD, 0);
4955 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4957 if (vmx_cpu_uses_apicv(vcpu))
4958 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4961 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4963 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4964 vmx->vcpu.arch.cr0 = cr0;
4965 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4966 vmx_set_cr4(vcpu, 0);
4967 vmx_set_efer(vcpu, 0);
4968 vmx_fpu_activate(vcpu);
4969 update_exception_bitmap(vcpu);
4971 vpid_sync_context(vmx->vpid);
4975 * In nested virtualization, check if L1 asked to exit on external interrupts.
4976 * For most existing hypervisors, this will always return true.
4978 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4980 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4981 PIN_BASED_EXT_INTR_MASK;
4985 * In nested virtualization, check if L1 has set
4986 * VM_EXIT_ACK_INTR_ON_EXIT
4988 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4990 return get_vmcs12(vcpu)->vm_exit_controls &
4991 VM_EXIT_ACK_INTR_ON_EXIT;
4994 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4996 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4997 PIN_BASED_NMI_EXITING;
5000 static void enable_irq_window(struct kvm_vcpu *vcpu)
5002 u32 cpu_based_vm_exec_control;
5004 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5005 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5006 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5009 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5011 u32 cpu_based_vm_exec_control;
5013 if (!cpu_has_virtual_nmis() ||
5014 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5015 enable_irq_window(vcpu);
5019 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5020 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5021 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5024 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5026 struct vcpu_vmx *vmx = to_vmx(vcpu);
5028 int irq = vcpu->arch.interrupt.nr;
5030 trace_kvm_inj_virq(irq);
5032 ++vcpu->stat.irq_injections;
5033 if (vmx->rmode.vm86_active) {
5035 if (vcpu->arch.interrupt.soft)
5036 inc_eip = vcpu->arch.event_exit_inst_len;
5037 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5038 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5041 intr = irq | INTR_INFO_VALID_MASK;
5042 if (vcpu->arch.interrupt.soft) {
5043 intr |= INTR_TYPE_SOFT_INTR;
5044 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5045 vmx->vcpu.arch.event_exit_inst_len);
5047 intr |= INTR_TYPE_EXT_INTR;
5048 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5051 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5053 struct vcpu_vmx *vmx = to_vmx(vcpu);
5055 if (is_guest_mode(vcpu))
5058 if (!cpu_has_virtual_nmis()) {
5060 * Tracking the NMI-blocked state in software is built upon
5061 * finding the next open IRQ window. This, in turn, depends on
5062 * well-behaving guests: They have to keep IRQs disabled at
5063 * least as long as the NMI handler runs. Otherwise we may
5064 * cause NMI nesting, maybe breaking the guest. But as this is
5065 * highly unlikely, we can live with the residual risk.
5067 vmx->soft_vnmi_blocked = 1;
5068 vmx->vnmi_blocked_time = 0;
5071 ++vcpu->stat.nmi_injections;
5072 vmx->nmi_known_unmasked = false;
5073 if (vmx->rmode.vm86_active) {
5074 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5075 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5078 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5079 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5082 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5084 if (!cpu_has_virtual_nmis())
5085 return to_vmx(vcpu)->soft_vnmi_blocked;
5086 if (to_vmx(vcpu)->nmi_known_unmasked)
5088 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5091 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5093 struct vcpu_vmx *vmx = to_vmx(vcpu);
5095 if (!cpu_has_virtual_nmis()) {
5096 if (vmx->soft_vnmi_blocked != masked) {
5097 vmx->soft_vnmi_blocked = masked;
5098 vmx->vnmi_blocked_time = 0;
5101 vmx->nmi_known_unmasked = !masked;
5103 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5104 GUEST_INTR_STATE_NMI);
5106 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5107 GUEST_INTR_STATE_NMI);
5111 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5113 if (to_vmx(vcpu)->nested.nested_run_pending)
5116 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5119 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5120 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5121 | GUEST_INTR_STATE_NMI));
5124 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5126 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5127 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5128 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5129 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5132 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5136 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5140 kvm->arch.tss_addr = addr;
5141 return init_rmode_tss(kvm);
5144 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5149 * Update instruction length as we may reinject the exception
5150 * from user space while in guest debugging mode.
5152 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5153 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5154 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5158 if (vcpu->guest_debug &
5159 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5176 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5177 int vec, u32 err_code)
5180 * Instruction with address size override prefix opcode 0x67
5181 * Cause the #SS fault with 0 error code in VM86 mode.
5183 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5184 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5185 if (vcpu->arch.halt_request) {
5186 vcpu->arch.halt_request = 0;
5187 return kvm_vcpu_halt(vcpu);
5195 * Forward all other exceptions that are valid in real mode.
5196 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5197 * the required debugging infrastructure rework.
5199 kvm_queue_exception(vcpu, vec);
5204 * Trigger machine check on the host. We assume all the MSRs are already set up
5205 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5206 * We pass a fake environment to the machine check handler because we want
5207 * the guest to be always treated like user space, no matter what context
5208 * it used internally.
5210 static void kvm_machine_check(void)
5212 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5213 struct pt_regs regs = {
5214 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5215 .flags = X86_EFLAGS_IF,
5218 do_machine_check(®s, 0);
5222 static int handle_machine_check(struct kvm_vcpu *vcpu)
5224 /* already handled by vcpu_run */
5228 static int handle_exception(struct kvm_vcpu *vcpu)
5230 struct vcpu_vmx *vmx = to_vmx(vcpu);
5231 struct kvm_run *kvm_run = vcpu->run;
5232 u32 intr_info, ex_no, error_code;
5233 unsigned long cr2, rip, dr6;
5235 enum emulation_result er;
5237 vect_info = vmx->idt_vectoring_info;
5238 intr_info = vmx->exit_intr_info;
5240 if (is_machine_check(intr_info))
5241 return handle_machine_check(vcpu);
5243 if (is_nmi(intr_info))
5244 return 1; /* already handled by vmx_vcpu_run() */
5246 if (is_no_device(intr_info)) {
5247 vmx_fpu_activate(vcpu);
5251 if (is_invalid_opcode(intr_info)) {
5252 if (is_guest_mode(vcpu)) {
5253 kvm_queue_exception(vcpu, UD_VECTOR);
5256 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5257 if (er != EMULATE_DONE)
5258 kvm_queue_exception(vcpu, UD_VECTOR);
5263 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5264 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5267 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5268 * MMIO, it is better to report an internal error.
5269 * See the comments in vmx_handle_exit.
5271 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5272 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5273 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5274 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5275 vcpu->run->internal.ndata = 3;
5276 vcpu->run->internal.data[0] = vect_info;
5277 vcpu->run->internal.data[1] = intr_info;
5278 vcpu->run->internal.data[2] = error_code;
5282 if (is_page_fault(intr_info)) {
5283 /* EPT won't cause page fault directly */
5285 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5286 trace_kvm_page_fault(cr2, error_code);
5288 if (kvm_event_needs_reinjection(vcpu))
5289 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5290 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5293 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5295 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5296 return handle_rmode_exception(vcpu, ex_no, error_code);
5300 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5303 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5304 if (!(vcpu->guest_debug &
5305 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5306 vcpu->arch.dr6 &= ~15;
5307 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5308 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5309 skip_emulated_instruction(vcpu);
5311 kvm_queue_exception(vcpu, DB_VECTOR);
5314 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5315 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5319 * Update instruction length as we may reinject #BP from
5320 * user space while in guest debugging mode. Reading it for
5321 * #DB as well causes no harm, it is not used in that case.
5323 vmx->vcpu.arch.event_exit_inst_len =
5324 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5325 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5326 rip = kvm_rip_read(vcpu);
5327 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5328 kvm_run->debug.arch.exception = ex_no;
5331 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5332 kvm_run->ex.exception = ex_no;
5333 kvm_run->ex.error_code = error_code;
5339 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5341 ++vcpu->stat.irq_exits;
5345 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5347 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5351 static int handle_io(struct kvm_vcpu *vcpu)
5353 unsigned long exit_qualification;
5354 int size, in, string;
5357 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5358 string = (exit_qualification & 16) != 0;
5359 in = (exit_qualification & 8) != 0;
5361 ++vcpu->stat.io_exits;
5364 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5366 port = exit_qualification >> 16;
5367 size = (exit_qualification & 7) + 1;
5368 skip_emulated_instruction(vcpu);
5370 return kvm_fast_pio_out(vcpu, size, port);
5374 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5377 * Patch in the VMCALL instruction:
5379 hypercall[0] = 0x0f;
5380 hypercall[1] = 0x01;
5381 hypercall[2] = 0xc1;
5384 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5386 unsigned long always_on = VMXON_CR0_ALWAYSON;
5387 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5389 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5390 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5391 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5392 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5393 return (val & always_on) == always_on;
5396 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5397 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5399 if (is_guest_mode(vcpu)) {
5400 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5401 unsigned long orig_val = val;
5404 * We get here when L2 changed cr0 in a way that did not change
5405 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5406 * but did change L0 shadowed bits. So we first calculate the
5407 * effective cr0 value that L1 would like to write into the
5408 * hardware. It consists of the L2-owned bits from the new
5409 * value combined with the L1-owned bits from L1's guest_cr0.
5411 val = (val & ~vmcs12->cr0_guest_host_mask) |
5412 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5414 if (!nested_cr0_valid(vcpu, val))
5417 if (kvm_set_cr0(vcpu, val))
5419 vmcs_writel(CR0_READ_SHADOW, orig_val);
5422 if (to_vmx(vcpu)->nested.vmxon &&
5423 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5425 return kvm_set_cr0(vcpu, val);
5429 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5431 if (is_guest_mode(vcpu)) {
5432 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5433 unsigned long orig_val = val;
5435 /* analogously to handle_set_cr0 */
5436 val = (val & ~vmcs12->cr4_guest_host_mask) |
5437 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5438 if (kvm_set_cr4(vcpu, val))
5440 vmcs_writel(CR4_READ_SHADOW, orig_val);
5443 return kvm_set_cr4(vcpu, val);
5446 /* called to set cr0 as approriate for clts instruction exit. */
5447 static void handle_clts(struct kvm_vcpu *vcpu)
5449 if (is_guest_mode(vcpu)) {
5451 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5452 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5453 * just pretend it's off (also in arch.cr0 for fpu_activate).
5455 vmcs_writel(CR0_READ_SHADOW,
5456 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5457 vcpu->arch.cr0 &= ~X86_CR0_TS;
5459 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5462 static int handle_cr(struct kvm_vcpu *vcpu)
5464 unsigned long exit_qualification, val;
5469 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5470 cr = exit_qualification & 15;
5471 reg = (exit_qualification >> 8) & 15;
5472 switch ((exit_qualification >> 4) & 3) {
5473 case 0: /* mov to cr */
5474 val = kvm_register_readl(vcpu, reg);
5475 trace_kvm_cr_write(cr, val);
5478 err = handle_set_cr0(vcpu, val);
5479 kvm_complete_insn_gp(vcpu, err);
5482 err = kvm_set_cr3(vcpu, val);
5483 kvm_complete_insn_gp(vcpu, err);
5486 err = handle_set_cr4(vcpu, val);
5487 kvm_complete_insn_gp(vcpu, err);
5490 u8 cr8_prev = kvm_get_cr8(vcpu);
5492 err = kvm_set_cr8(vcpu, cr8);
5493 kvm_complete_insn_gp(vcpu, err);
5494 if (lapic_in_kernel(vcpu))
5496 if (cr8_prev <= cr8)
5498 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5505 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5506 skip_emulated_instruction(vcpu);
5507 vmx_fpu_activate(vcpu);
5509 case 1: /*mov from cr*/
5512 val = kvm_read_cr3(vcpu);
5513 kvm_register_write(vcpu, reg, val);
5514 trace_kvm_cr_read(cr, val);
5515 skip_emulated_instruction(vcpu);
5518 val = kvm_get_cr8(vcpu);
5519 kvm_register_write(vcpu, reg, val);
5520 trace_kvm_cr_read(cr, val);
5521 skip_emulated_instruction(vcpu);
5526 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5527 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5528 kvm_lmsw(vcpu, val);
5530 skip_emulated_instruction(vcpu);
5535 vcpu->run->exit_reason = 0;
5536 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5537 (int)(exit_qualification >> 4) & 3, cr);
5541 static int handle_dr(struct kvm_vcpu *vcpu)
5543 unsigned long exit_qualification;
5546 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5547 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5549 /* First, if DR does not exist, trigger UD */
5550 if (!kvm_require_dr(vcpu, dr))
5553 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5554 if (!kvm_require_cpl(vcpu, 0))
5556 dr7 = vmcs_readl(GUEST_DR7);
5559 * As the vm-exit takes precedence over the debug trap, we
5560 * need to emulate the latter, either for the host or the
5561 * guest debugging itself.
5563 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5564 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5565 vcpu->run->debug.arch.dr7 = dr7;
5566 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5567 vcpu->run->debug.arch.exception = DB_VECTOR;
5568 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5571 vcpu->arch.dr6 &= ~15;
5572 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5573 kvm_queue_exception(vcpu, DB_VECTOR);
5578 if (vcpu->guest_debug == 0) {
5579 u32 cpu_based_vm_exec_control;
5581 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5582 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5583 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5586 * No more DR vmexits; force a reload of the debug registers
5587 * and reenter on this instruction. The next vmexit will
5588 * retrieve the full state of the debug registers.
5590 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5594 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5595 if (exit_qualification & TYPE_MOV_FROM_DR) {
5598 if (kvm_get_dr(vcpu, dr, &val))
5600 kvm_register_write(vcpu, reg, val);
5602 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5605 skip_emulated_instruction(vcpu);
5609 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5611 return vcpu->arch.dr6;
5614 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5618 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5620 u32 cpu_based_vm_exec_control;
5622 get_debugreg(vcpu->arch.db[0], 0);
5623 get_debugreg(vcpu->arch.db[1], 1);
5624 get_debugreg(vcpu->arch.db[2], 2);
5625 get_debugreg(vcpu->arch.db[3], 3);
5626 get_debugreg(vcpu->arch.dr6, 6);
5627 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5629 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5631 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5632 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5633 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5636 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5638 vmcs_writel(GUEST_DR7, val);
5641 static int handle_cpuid(struct kvm_vcpu *vcpu)
5643 kvm_emulate_cpuid(vcpu);
5647 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5649 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5650 struct msr_data msr_info;
5652 msr_info.index = ecx;
5653 msr_info.host_initiated = false;
5654 if (vmx_get_msr(vcpu, &msr_info)) {
5655 trace_kvm_msr_read_ex(ecx);
5656 kvm_inject_gp(vcpu, 0);
5660 trace_kvm_msr_read(ecx, msr_info.data);
5662 /* FIXME: handling of bits 32:63 of rax, rdx */
5663 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5664 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5665 skip_emulated_instruction(vcpu);
5669 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5671 struct msr_data msr;
5672 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5673 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5674 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5678 msr.host_initiated = false;
5679 if (kvm_set_msr(vcpu, &msr) != 0) {
5680 trace_kvm_msr_write_ex(ecx, data);
5681 kvm_inject_gp(vcpu, 0);
5685 trace_kvm_msr_write(ecx, data);
5686 skip_emulated_instruction(vcpu);
5690 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5692 kvm_make_request(KVM_REQ_EVENT, vcpu);
5696 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5698 u32 cpu_based_vm_exec_control;
5700 /* clear pending irq */
5701 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5702 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5703 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5705 kvm_make_request(KVM_REQ_EVENT, vcpu);
5707 ++vcpu->stat.irq_window_exits;
5711 static int handle_halt(struct kvm_vcpu *vcpu)
5713 return kvm_emulate_halt(vcpu);
5716 static int handle_vmcall(struct kvm_vcpu *vcpu)
5718 kvm_emulate_hypercall(vcpu);
5722 static int handle_invd(struct kvm_vcpu *vcpu)
5724 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5727 static int handle_invlpg(struct kvm_vcpu *vcpu)
5729 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5731 kvm_mmu_invlpg(vcpu, exit_qualification);
5732 skip_emulated_instruction(vcpu);
5736 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5740 err = kvm_rdpmc(vcpu);
5741 kvm_complete_insn_gp(vcpu, err);
5746 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5748 kvm_emulate_wbinvd(vcpu);
5752 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5754 u64 new_bv = kvm_read_edx_eax(vcpu);
5755 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5757 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5758 skip_emulated_instruction(vcpu);
5762 static int handle_xsaves(struct kvm_vcpu *vcpu)
5764 skip_emulated_instruction(vcpu);
5765 WARN(1, "this should never happen\n");
5769 static int handle_xrstors(struct kvm_vcpu *vcpu)
5771 skip_emulated_instruction(vcpu);
5772 WARN(1, "this should never happen\n");
5776 static int handle_apic_access(struct kvm_vcpu *vcpu)
5778 if (likely(fasteoi)) {
5779 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5780 int access_type, offset;
5782 access_type = exit_qualification & APIC_ACCESS_TYPE;
5783 offset = exit_qualification & APIC_ACCESS_OFFSET;
5785 * Sane guest uses MOV to write EOI, with written value
5786 * not cared. So make a short-circuit here by avoiding
5787 * heavy instruction emulation.
5789 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5790 (offset == APIC_EOI)) {
5791 kvm_lapic_set_eoi(vcpu);
5792 skip_emulated_instruction(vcpu);
5796 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5799 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5801 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5802 int vector = exit_qualification & 0xff;
5804 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5805 kvm_apic_set_eoi_accelerated(vcpu, vector);
5809 static int handle_apic_write(struct kvm_vcpu *vcpu)
5811 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5812 u32 offset = exit_qualification & 0xfff;
5814 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5815 kvm_apic_write_nodecode(vcpu, offset);
5819 static int handle_task_switch(struct kvm_vcpu *vcpu)
5821 struct vcpu_vmx *vmx = to_vmx(vcpu);
5822 unsigned long exit_qualification;
5823 bool has_error_code = false;
5826 int reason, type, idt_v, idt_index;
5828 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5829 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5830 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5832 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5834 reason = (u32)exit_qualification >> 30;
5835 if (reason == TASK_SWITCH_GATE && idt_v) {
5837 case INTR_TYPE_NMI_INTR:
5838 vcpu->arch.nmi_injected = false;
5839 vmx_set_nmi_mask(vcpu, true);
5841 case INTR_TYPE_EXT_INTR:
5842 case INTR_TYPE_SOFT_INTR:
5843 kvm_clear_interrupt_queue(vcpu);
5845 case INTR_TYPE_HARD_EXCEPTION:
5846 if (vmx->idt_vectoring_info &
5847 VECTORING_INFO_DELIVER_CODE_MASK) {
5848 has_error_code = true;
5850 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5853 case INTR_TYPE_SOFT_EXCEPTION:
5854 kvm_clear_exception_queue(vcpu);
5860 tss_selector = exit_qualification;
5862 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5863 type != INTR_TYPE_EXT_INTR &&
5864 type != INTR_TYPE_NMI_INTR))
5865 skip_emulated_instruction(vcpu);
5867 if (kvm_task_switch(vcpu, tss_selector,
5868 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5869 has_error_code, error_code) == EMULATE_FAIL) {
5870 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5871 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5872 vcpu->run->internal.ndata = 0;
5877 * TODO: What about debug traps on tss switch?
5878 * Are we supposed to inject them and update dr6?
5884 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5886 unsigned long exit_qualification;
5891 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5893 gla_validity = (exit_qualification >> 7) & 0x3;
5894 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5895 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5896 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5897 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5898 vmcs_readl(GUEST_LINEAR_ADDRESS));
5899 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5900 (long unsigned int)exit_qualification);
5901 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5902 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5907 * EPT violation happened while executing iret from NMI,
5908 * "blocked by NMI" bit has to be set before next VM entry.
5909 * There are errata that may cause this bit to not be set:
5912 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5913 cpu_has_virtual_nmis() &&
5914 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5915 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5917 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5918 trace_kvm_page_fault(gpa, exit_qualification);
5920 /* It is a write fault? */
5921 error_code = exit_qualification & PFERR_WRITE_MASK;
5922 /* It is a fetch fault? */
5923 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5924 /* ept page table is present? */
5925 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5927 vcpu->arch.exit_qualification = exit_qualification;
5929 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5932 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5937 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5938 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5939 skip_emulated_instruction(vcpu);
5940 trace_kvm_fast_mmio(gpa);
5944 ret = handle_mmio_page_fault(vcpu, gpa, true);
5945 if (likely(ret == RET_MMIO_PF_EMULATE))
5946 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5949 if (unlikely(ret == RET_MMIO_PF_INVALID))
5950 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5952 if (unlikely(ret == RET_MMIO_PF_RETRY))
5955 /* It is the real ept misconfig */
5958 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5959 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5964 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5966 u32 cpu_based_vm_exec_control;
5968 /* clear pending NMI */
5969 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5970 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5971 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5972 ++vcpu->stat.nmi_window_exits;
5973 kvm_make_request(KVM_REQ_EVENT, vcpu);
5978 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5980 struct vcpu_vmx *vmx = to_vmx(vcpu);
5981 enum emulation_result err = EMULATE_DONE;
5984 bool intr_window_requested;
5985 unsigned count = 130;
5987 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5988 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5990 while (vmx->emulation_required && count-- != 0) {
5991 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5992 return handle_interrupt_window(&vmx->vcpu);
5994 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5997 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5999 if (err == EMULATE_USER_EXIT) {
6000 ++vcpu->stat.mmio_exits;
6005 if (err != EMULATE_DONE) {
6006 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6007 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6008 vcpu->run->internal.ndata = 0;
6012 if (vcpu->arch.halt_request) {
6013 vcpu->arch.halt_request = 0;
6014 ret = kvm_vcpu_halt(vcpu);
6018 if (signal_pending(current))
6028 static int __grow_ple_window(int val)
6030 if (ple_window_grow < 1)
6033 val = min(val, ple_window_actual_max);
6035 if (ple_window_grow < ple_window)
6036 val *= ple_window_grow;
6038 val += ple_window_grow;
6043 static int __shrink_ple_window(int val, int modifier, int minimum)
6048 if (modifier < ple_window)
6053 return max(val, minimum);
6056 static void grow_ple_window(struct kvm_vcpu *vcpu)
6058 struct vcpu_vmx *vmx = to_vmx(vcpu);
6059 int old = vmx->ple_window;
6061 vmx->ple_window = __grow_ple_window(old);
6063 if (vmx->ple_window != old)
6064 vmx->ple_window_dirty = true;
6066 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6069 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6071 struct vcpu_vmx *vmx = to_vmx(vcpu);
6072 int old = vmx->ple_window;
6074 vmx->ple_window = __shrink_ple_window(old,
6075 ple_window_shrink, ple_window);
6077 if (vmx->ple_window != old)
6078 vmx->ple_window_dirty = true;
6080 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6084 * ple_window_actual_max is computed to be one grow_ple_window() below
6085 * ple_window_max. (See __grow_ple_window for the reason.)
6086 * This prevents overflows, because ple_window_max is int.
6087 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6089 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6091 static void update_ple_window_actual_max(void)
6093 ple_window_actual_max =
6094 __shrink_ple_window(max(ple_window_max, ple_window),
6095 ple_window_grow, INT_MIN);
6099 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6101 static void wakeup_handler(void)
6103 struct kvm_vcpu *vcpu;
6104 int cpu = smp_processor_id();
6106 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6107 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6108 blocked_vcpu_list) {
6109 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6111 if (pi_test_on(pi_desc) == 1)
6112 kvm_vcpu_kick(vcpu);
6114 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6117 static __init int hardware_setup(void)
6119 int r = -ENOMEM, i, msr;
6121 rdmsrl_safe(MSR_EFER, &host_efer);
6123 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6124 kvm_define_shared_msr(i, vmx_msr_index[i]);
6126 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6127 if (!vmx_io_bitmap_a)
6130 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6131 if (!vmx_io_bitmap_b)
6134 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6135 if (!vmx_msr_bitmap_legacy)
6138 vmx_msr_bitmap_legacy_x2apic =
6139 (unsigned long *)__get_free_page(GFP_KERNEL);
6140 if (!vmx_msr_bitmap_legacy_x2apic)
6143 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6144 if (!vmx_msr_bitmap_longmode)
6147 vmx_msr_bitmap_longmode_x2apic =
6148 (unsigned long *)__get_free_page(GFP_KERNEL);
6149 if (!vmx_msr_bitmap_longmode_x2apic)
6153 vmx_msr_bitmap_nested =
6154 (unsigned long *)__get_free_page(GFP_KERNEL);
6155 if (!vmx_msr_bitmap_nested)
6159 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6160 if (!vmx_vmread_bitmap)
6163 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6164 if (!vmx_vmwrite_bitmap)
6167 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6168 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6171 * Allow direct access to the PC debug port (it is often used for I/O
6172 * delays, but the vmexits simply slow things down).
6174 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6175 clear_bit(0x80, vmx_io_bitmap_a);
6177 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6179 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6180 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6182 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6184 if (setup_vmcs_config(&vmcs_config) < 0) {
6189 if (boot_cpu_has(X86_FEATURE_NX))
6190 kvm_enable_efer_bits(EFER_NX);
6192 if (!cpu_has_vmx_vpid())
6194 if (!cpu_has_vmx_shadow_vmcs())
6195 enable_shadow_vmcs = 0;
6196 if (enable_shadow_vmcs)
6197 init_vmcs_shadow_fields();
6199 if (!cpu_has_vmx_ept() ||
6200 !cpu_has_vmx_ept_4levels()) {
6202 enable_unrestricted_guest = 0;
6203 enable_ept_ad_bits = 0;
6206 if (!cpu_has_vmx_ept_ad_bits())
6207 enable_ept_ad_bits = 0;
6209 if (!cpu_has_vmx_unrestricted_guest())
6210 enable_unrestricted_guest = 0;
6212 if (!cpu_has_vmx_flexpriority())
6213 flexpriority_enabled = 0;
6216 * set_apic_access_page_addr() is used to reload apic access
6217 * page upon invalidation. No need to do anything if not
6218 * using the APIC_ACCESS_ADDR VMCS field.
6220 if (!flexpriority_enabled)
6221 kvm_x86_ops->set_apic_access_page_addr = NULL;
6223 if (!cpu_has_vmx_tpr_shadow())
6224 kvm_x86_ops->update_cr8_intercept = NULL;
6226 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6227 kvm_disable_largepages();
6229 if (!cpu_has_vmx_ple())
6232 if (!cpu_has_vmx_apicv())
6235 if (cpu_has_vmx_tsc_scaling()) {
6236 kvm_has_tsc_control = true;
6237 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6238 kvm_tsc_scaling_ratio_frac_bits = 48;
6242 kvm_x86_ops->update_cr8_intercept = NULL;
6244 kvm_x86_ops->hwapic_irr_update = NULL;
6245 kvm_x86_ops->hwapic_isr_update = NULL;
6246 kvm_x86_ops->deliver_posted_interrupt = NULL;
6247 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6250 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6251 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6252 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6253 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6254 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6255 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6256 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6258 memcpy(vmx_msr_bitmap_legacy_x2apic,
6259 vmx_msr_bitmap_legacy, PAGE_SIZE);
6260 memcpy(vmx_msr_bitmap_longmode_x2apic,
6261 vmx_msr_bitmap_longmode, PAGE_SIZE);
6263 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6266 for (msr = 0x800; msr <= 0x8ff; msr++)
6267 vmx_disable_intercept_msr_read_x2apic(msr);
6269 /* According SDM, in x2apic mode, the whole id reg is used.
6270 * But in KVM, it only use the highest eight bits. Need to
6272 vmx_enable_intercept_msr_read_x2apic(0x802);
6274 vmx_enable_intercept_msr_read_x2apic(0x839);
6276 vmx_disable_intercept_msr_write_x2apic(0x808);
6278 vmx_disable_intercept_msr_write_x2apic(0x80b);
6280 vmx_disable_intercept_msr_write_x2apic(0x83f);
6284 kvm_mmu_set_mask_ptes(0ull,
6285 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6286 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6287 0ull, VMX_EPT_EXECUTABLE_MASK);
6288 ept_set_mmio_spte_mask();
6293 update_ple_window_actual_max();
6296 * Only enable PML when hardware supports PML feature, and both EPT
6297 * and EPT A/D bit features are enabled -- PML depends on them to work.
6299 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6303 kvm_x86_ops->slot_enable_log_dirty = NULL;
6304 kvm_x86_ops->slot_disable_log_dirty = NULL;
6305 kvm_x86_ops->flush_log_dirty = NULL;
6306 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6309 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6311 return alloc_kvm_area();
6314 free_page((unsigned long)vmx_vmwrite_bitmap);
6316 free_page((unsigned long)vmx_vmread_bitmap);
6319 free_page((unsigned long)vmx_msr_bitmap_nested);
6321 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6323 free_page((unsigned long)vmx_msr_bitmap_longmode);
6325 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6327 free_page((unsigned long)vmx_msr_bitmap_legacy);
6329 free_page((unsigned long)vmx_io_bitmap_b);
6331 free_page((unsigned long)vmx_io_bitmap_a);
6336 static __exit void hardware_unsetup(void)
6338 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6339 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6340 free_page((unsigned long)vmx_msr_bitmap_legacy);
6341 free_page((unsigned long)vmx_msr_bitmap_longmode);
6342 free_page((unsigned long)vmx_io_bitmap_b);
6343 free_page((unsigned long)vmx_io_bitmap_a);
6344 free_page((unsigned long)vmx_vmwrite_bitmap);
6345 free_page((unsigned long)vmx_vmread_bitmap);
6347 free_page((unsigned long)vmx_msr_bitmap_nested);
6353 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6354 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6356 static int handle_pause(struct kvm_vcpu *vcpu)
6359 grow_ple_window(vcpu);
6361 skip_emulated_instruction(vcpu);
6362 kvm_vcpu_on_spin(vcpu);
6367 static int handle_nop(struct kvm_vcpu *vcpu)
6369 skip_emulated_instruction(vcpu);
6373 static int handle_mwait(struct kvm_vcpu *vcpu)
6375 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6376 return handle_nop(vcpu);
6379 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6384 static int handle_monitor(struct kvm_vcpu *vcpu)
6386 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6387 return handle_nop(vcpu);
6391 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6392 * We could reuse a single VMCS for all the L2 guests, but we also want the
6393 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6394 * allows keeping them loaded on the processor, and in the future will allow
6395 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6396 * every entry if they never change.
6397 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6398 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6400 * The following functions allocate and free a vmcs02 in this pool.
6403 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6404 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6406 struct vmcs02_list *item;
6407 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6408 if (item->vmptr == vmx->nested.current_vmptr) {
6409 list_move(&item->list, &vmx->nested.vmcs02_pool);
6410 return &item->vmcs02;
6413 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6414 /* Recycle the least recently used VMCS. */
6415 item = list_entry(vmx->nested.vmcs02_pool.prev,
6416 struct vmcs02_list, list);
6417 item->vmptr = vmx->nested.current_vmptr;
6418 list_move(&item->list, &vmx->nested.vmcs02_pool);
6419 return &item->vmcs02;
6422 /* Create a new VMCS */
6423 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6426 item->vmcs02.vmcs = alloc_vmcs();
6427 if (!item->vmcs02.vmcs) {
6431 loaded_vmcs_init(&item->vmcs02);
6432 item->vmptr = vmx->nested.current_vmptr;
6433 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6434 vmx->nested.vmcs02_num++;
6435 return &item->vmcs02;
6438 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6439 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6441 struct vmcs02_list *item;
6442 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6443 if (item->vmptr == vmptr) {
6444 free_loaded_vmcs(&item->vmcs02);
6445 list_del(&item->list);
6447 vmx->nested.vmcs02_num--;
6453 * Free all VMCSs saved for this vcpu, except the one pointed by
6454 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6455 * must be &vmx->vmcs01.
6457 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6459 struct vmcs02_list *item, *n;
6461 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6462 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6464 * Something will leak if the above WARN triggers. Better than
6467 if (vmx->loaded_vmcs == &item->vmcs02)
6470 free_loaded_vmcs(&item->vmcs02);
6471 list_del(&item->list);
6473 vmx->nested.vmcs02_num--;
6478 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6479 * set the success or error code of an emulated VMX instruction, as specified
6480 * by Vol 2B, VMX Instruction Reference, "Conventions".
6482 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6484 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6485 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6486 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6489 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6491 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6492 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6493 X86_EFLAGS_SF | X86_EFLAGS_OF))
6497 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6498 u32 vm_instruction_error)
6500 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6502 * failValid writes the error number to the current VMCS, which
6503 * can't be done there isn't a current VMCS.
6505 nested_vmx_failInvalid(vcpu);
6508 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6509 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6510 X86_EFLAGS_SF | X86_EFLAGS_OF))
6512 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6514 * We don't need to force a shadow sync because
6515 * VM_INSTRUCTION_ERROR is not shadowed
6519 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6521 /* TODO: not to reset guest simply here. */
6522 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6523 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6526 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6528 struct vcpu_vmx *vmx =
6529 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6531 vmx->nested.preemption_timer_expired = true;
6532 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6533 kvm_vcpu_kick(&vmx->vcpu);
6535 return HRTIMER_NORESTART;
6539 * Decode the memory-address operand of a vmx instruction, as recorded on an
6540 * exit caused by such an instruction (run by a guest hypervisor).
6541 * On success, returns 0. When the operand is invalid, returns 1 and throws
6544 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6545 unsigned long exit_qualification,
6546 u32 vmx_instruction_info, bool wr, gva_t *ret)
6550 struct kvm_segment s;
6553 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6554 * Execution", on an exit, vmx_instruction_info holds most of the
6555 * addressing components of the operand. Only the displacement part
6556 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6557 * For how an actual address is calculated from all these components,
6558 * refer to Vol. 1, "Operand Addressing".
6560 int scaling = vmx_instruction_info & 3;
6561 int addr_size = (vmx_instruction_info >> 7) & 7;
6562 bool is_reg = vmx_instruction_info & (1u << 10);
6563 int seg_reg = (vmx_instruction_info >> 15) & 7;
6564 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6565 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6566 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6567 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6570 kvm_queue_exception(vcpu, UD_VECTOR);
6574 /* Addr = segment_base + offset */
6575 /* offset = base + [index * scale] + displacement */
6576 off = exit_qualification; /* holds the displacement */
6578 off += kvm_register_read(vcpu, base_reg);
6580 off += kvm_register_read(vcpu, index_reg)<<scaling;
6581 vmx_get_segment(vcpu, &s, seg_reg);
6582 *ret = s.base + off;
6584 if (addr_size == 1) /* 32 bit */
6587 /* Checks for #GP/#SS exceptions. */
6589 if (is_long_mode(vcpu)) {
6590 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6591 * non-canonical form. This is the only check on the memory
6592 * destination for long mode!
6594 exn = is_noncanonical_address(*ret);
6595 } else if (is_protmode(vcpu)) {
6596 /* Protected mode: apply checks for segment validity in the
6598 * - segment type check (#GP(0) may be thrown)
6599 * - usability check (#GP(0)/#SS(0))
6600 * - limit check (#GP(0)/#SS(0))
6603 /* #GP(0) if the destination operand is located in a
6604 * read-only data segment or any code segment.
6606 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6608 /* #GP(0) if the source operand is located in an
6609 * execute-only code segment
6611 exn = ((s.type & 0xa) == 8);
6613 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6616 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6618 exn = (s.unusable != 0);
6619 /* Protected mode: #GP(0)/#SS(0) if the memory
6620 * operand is outside the segment limit.
6622 exn = exn || (off + sizeof(u64) > s.limit);
6625 kvm_queue_exception_e(vcpu,
6626 seg_reg == VCPU_SREG_SS ?
6627 SS_VECTOR : GP_VECTOR,
6636 * This function performs the various checks including
6637 * - if it's 4KB aligned
6638 * - No bits beyond the physical address width are set
6639 * - Returns 0 on success or else 1
6640 * (Intel SDM Section 30.3)
6642 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6647 struct x86_exception e;
6649 struct vcpu_vmx *vmx = to_vmx(vcpu);
6650 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6652 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6653 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6656 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6657 sizeof(vmptr), &e)) {
6658 kvm_inject_page_fault(vcpu, &e);
6662 switch (exit_reason) {
6663 case EXIT_REASON_VMON:
6666 * The first 4 bytes of VMXON region contain the supported
6667 * VMCS revision identifier
6669 * Note - IA32_VMX_BASIC[48] will never be 1
6670 * for the nested case;
6671 * which replaces physical address width with 32
6674 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6675 nested_vmx_failInvalid(vcpu);
6676 skip_emulated_instruction(vcpu);
6680 page = nested_get_page(vcpu, vmptr);
6682 *(u32 *)kmap(page) != VMCS12_REVISION) {
6683 nested_vmx_failInvalid(vcpu);
6685 skip_emulated_instruction(vcpu);
6689 vmx->nested.vmxon_ptr = vmptr;
6691 case EXIT_REASON_VMCLEAR:
6692 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6693 nested_vmx_failValid(vcpu,
6694 VMXERR_VMCLEAR_INVALID_ADDRESS);
6695 skip_emulated_instruction(vcpu);
6699 if (vmptr == vmx->nested.vmxon_ptr) {
6700 nested_vmx_failValid(vcpu,
6701 VMXERR_VMCLEAR_VMXON_POINTER);
6702 skip_emulated_instruction(vcpu);
6706 case EXIT_REASON_VMPTRLD:
6707 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6708 nested_vmx_failValid(vcpu,
6709 VMXERR_VMPTRLD_INVALID_ADDRESS);
6710 skip_emulated_instruction(vcpu);
6714 if (vmptr == vmx->nested.vmxon_ptr) {
6715 nested_vmx_failValid(vcpu,
6716 VMXERR_VMCLEAR_VMXON_POINTER);
6717 skip_emulated_instruction(vcpu);
6722 return 1; /* shouldn't happen */
6731 * Emulate the VMXON instruction.
6732 * Currently, we just remember that VMX is active, and do not save or even
6733 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6734 * do not currently need to store anything in that guest-allocated memory
6735 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6736 * argument is different from the VMXON pointer (which the spec says they do).
6738 static int handle_vmon(struct kvm_vcpu *vcpu)
6740 struct kvm_segment cs;
6741 struct vcpu_vmx *vmx = to_vmx(vcpu);
6742 struct vmcs *shadow_vmcs;
6743 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6744 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6746 /* The Intel VMX Instruction Reference lists a bunch of bits that
6747 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6748 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6749 * Otherwise, we should fail with #UD. We test these now:
6751 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6752 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6753 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6754 kvm_queue_exception(vcpu, UD_VECTOR);
6758 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6759 if (is_long_mode(vcpu) && !cs.l) {
6760 kvm_queue_exception(vcpu, UD_VECTOR);
6764 if (vmx_get_cpl(vcpu)) {
6765 kvm_inject_gp(vcpu, 0);
6769 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6772 if (vmx->nested.vmxon) {
6773 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6774 skip_emulated_instruction(vcpu);
6778 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6779 != VMXON_NEEDED_FEATURES) {
6780 kvm_inject_gp(vcpu, 0);
6784 if (enable_shadow_vmcs) {
6785 shadow_vmcs = alloc_vmcs();
6788 /* mark vmcs as shadow */
6789 shadow_vmcs->revision_id |= (1u << 31);
6790 /* init shadow vmcs */
6791 vmcs_clear(shadow_vmcs);
6792 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6795 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6796 vmx->nested.vmcs02_num = 0;
6798 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6800 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6802 vmx->nested.vmxon = true;
6804 skip_emulated_instruction(vcpu);
6805 nested_vmx_succeed(vcpu);
6810 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6811 * for running VMX instructions (except VMXON, whose prerequisites are
6812 * slightly different). It also specifies what exception to inject otherwise.
6814 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6816 struct kvm_segment cs;
6817 struct vcpu_vmx *vmx = to_vmx(vcpu);
6819 if (!vmx->nested.vmxon) {
6820 kvm_queue_exception(vcpu, UD_VECTOR);
6824 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6825 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6826 (is_long_mode(vcpu) && !cs.l)) {
6827 kvm_queue_exception(vcpu, UD_VECTOR);
6831 if (vmx_get_cpl(vcpu)) {
6832 kvm_inject_gp(vcpu, 0);
6839 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6841 if (vmx->nested.current_vmptr == -1ull)
6844 /* current_vmptr and current_vmcs12 are always set/reset together */
6845 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6848 if (enable_shadow_vmcs) {
6849 /* copy to memory all shadowed fields in case
6850 they were modified */
6851 copy_shadow_to_vmcs12(vmx);
6852 vmx->nested.sync_shadow_vmcs = false;
6853 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6854 SECONDARY_EXEC_SHADOW_VMCS);
6855 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6857 vmx->nested.posted_intr_nv = -1;
6858 kunmap(vmx->nested.current_vmcs12_page);
6859 nested_release_page(vmx->nested.current_vmcs12_page);
6860 vmx->nested.current_vmptr = -1ull;
6861 vmx->nested.current_vmcs12 = NULL;
6865 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6866 * just stops using VMX.
6868 static void free_nested(struct vcpu_vmx *vmx)
6870 if (!vmx->nested.vmxon)
6873 vmx->nested.vmxon = false;
6874 free_vpid(vmx->nested.vpid02);
6875 nested_release_vmcs12(vmx);
6876 if (enable_shadow_vmcs)
6877 free_vmcs(vmx->nested.current_shadow_vmcs);
6878 /* Unpin physical memory we referred to in current vmcs02 */
6879 if (vmx->nested.apic_access_page) {
6880 nested_release_page(vmx->nested.apic_access_page);
6881 vmx->nested.apic_access_page = NULL;
6883 if (vmx->nested.virtual_apic_page) {
6884 nested_release_page(vmx->nested.virtual_apic_page);
6885 vmx->nested.virtual_apic_page = NULL;
6887 if (vmx->nested.pi_desc_page) {
6888 kunmap(vmx->nested.pi_desc_page);
6889 nested_release_page(vmx->nested.pi_desc_page);
6890 vmx->nested.pi_desc_page = NULL;
6891 vmx->nested.pi_desc = NULL;
6894 nested_free_all_saved_vmcss(vmx);
6897 /* Emulate the VMXOFF instruction */
6898 static int handle_vmoff(struct kvm_vcpu *vcpu)
6900 if (!nested_vmx_check_permission(vcpu))
6902 free_nested(to_vmx(vcpu));
6903 skip_emulated_instruction(vcpu);
6904 nested_vmx_succeed(vcpu);
6908 /* Emulate the VMCLEAR instruction */
6909 static int handle_vmclear(struct kvm_vcpu *vcpu)
6911 struct vcpu_vmx *vmx = to_vmx(vcpu);
6913 struct vmcs12 *vmcs12;
6916 if (!nested_vmx_check_permission(vcpu))
6919 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6922 if (vmptr == vmx->nested.current_vmptr)
6923 nested_release_vmcs12(vmx);
6925 page = nested_get_page(vcpu, vmptr);
6928 * For accurate processor emulation, VMCLEAR beyond available
6929 * physical memory should do nothing at all. However, it is
6930 * possible that a nested vmx bug, not a guest hypervisor bug,
6931 * resulted in this case, so let's shut down before doing any
6934 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6937 vmcs12 = kmap(page);
6938 vmcs12->launch_state = 0;
6940 nested_release_page(page);
6942 nested_free_vmcs02(vmx, vmptr);
6944 skip_emulated_instruction(vcpu);
6945 nested_vmx_succeed(vcpu);
6949 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6951 /* Emulate the VMLAUNCH instruction */
6952 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6954 return nested_vmx_run(vcpu, true);
6957 /* Emulate the VMRESUME instruction */
6958 static int handle_vmresume(struct kvm_vcpu *vcpu)
6961 return nested_vmx_run(vcpu, false);
6964 enum vmcs_field_type {
6965 VMCS_FIELD_TYPE_U16 = 0,
6966 VMCS_FIELD_TYPE_U64 = 1,
6967 VMCS_FIELD_TYPE_U32 = 2,
6968 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6971 static inline int vmcs_field_type(unsigned long field)
6973 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6974 return VMCS_FIELD_TYPE_U32;
6975 return (field >> 13) & 0x3 ;
6978 static inline int vmcs_field_readonly(unsigned long field)
6980 return (((field >> 10) & 0x3) == 1);
6984 * Read a vmcs12 field. Since these can have varying lengths and we return
6985 * one type, we chose the biggest type (u64) and zero-extend the return value
6986 * to that size. Note that the caller, handle_vmread, might need to use only
6987 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6988 * 64-bit fields are to be returned).
6990 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6991 unsigned long field, u64 *ret)
6993 short offset = vmcs_field_to_offset(field);
6999 p = ((char *)(get_vmcs12(vcpu))) + offset;
7001 switch (vmcs_field_type(field)) {
7002 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7003 *ret = *((natural_width *)p);
7005 case VMCS_FIELD_TYPE_U16:
7008 case VMCS_FIELD_TYPE_U32:
7011 case VMCS_FIELD_TYPE_U64:
7021 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7022 unsigned long field, u64 field_value){
7023 short offset = vmcs_field_to_offset(field);
7024 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7028 switch (vmcs_field_type(field)) {
7029 case VMCS_FIELD_TYPE_U16:
7030 *(u16 *)p = field_value;
7032 case VMCS_FIELD_TYPE_U32:
7033 *(u32 *)p = field_value;
7035 case VMCS_FIELD_TYPE_U64:
7036 *(u64 *)p = field_value;
7038 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7039 *(natural_width *)p = field_value;
7048 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7051 unsigned long field;
7053 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7054 const unsigned long *fields = shadow_read_write_fields;
7055 const int num_fields = max_shadow_read_write_fields;
7059 vmcs_load(shadow_vmcs);
7061 for (i = 0; i < num_fields; i++) {
7063 switch (vmcs_field_type(field)) {
7064 case VMCS_FIELD_TYPE_U16:
7065 field_value = vmcs_read16(field);
7067 case VMCS_FIELD_TYPE_U32:
7068 field_value = vmcs_read32(field);
7070 case VMCS_FIELD_TYPE_U64:
7071 field_value = vmcs_read64(field);
7073 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7074 field_value = vmcs_readl(field);
7080 vmcs12_write_any(&vmx->vcpu, field, field_value);
7083 vmcs_clear(shadow_vmcs);
7084 vmcs_load(vmx->loaded_vmcs->vmcs);
7089 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7091 const unsigned long *fields[] = {
7092 shadow_read_write_fields,
7093 shadow_read_only_fields
7095 const int max_fields[] = {
7096 max_shadow_read_write_fields,
7097 max_shadow_read_only_fields
7100 unsigned long field;
7101 u64 field_value = 0;
7102 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7104 vmcs_load(shadow_vmcs);
7106 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7107 for (i = 0; i < max_fields[q]; i++) {
7108 field = fields[q][i];
7109 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7111 switch (vmcs_field_type(field)) {
7112 case VMCS_FIELD_TYPE_U16:
7113 vmcs_write16(field, (u16)field_value);
7115 case VMCS_FIELD_TYPE_U32:
7116 vmcs_write32(field, (u32)field_value);
7118 case VMCS_FIELD_TYPE_U64:
7119 vmcs_write64(field, (u64)field_value);
7121 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7122 vmcs_writel(field, (long)field_value);
7131 vmcs_clear(shadow_vmcs);
7132 vmcs_load(vmx->loaded_vmcs->vmcs);
7136 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7137 * used before) all generate the same failure when it is missing.
7139 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7141 struct vcpu_vmx *vmx = to_vmx(vcpu);
7142 if (vmx->nested.current_vmptr == -1ull) {
7143 nested_vmx_failInvalid(vcpu);
7144 skip_emulated_instruction(vcpu);
7150 static int handle_vmread(struct kvm_vcpu *vcpu)
7152 unsigned long field;
7154 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7155 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7158 if (!nested_vmx_check_permission(vcpu) ||
7159 !nested_vmx_check_vmcs12(vcpu))
7162 /* Decode instruction info and find the field to read */
7163 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7164 /* Read the field, zero-extended to a u64 field_value */
7165 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7166 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7167 skip_emulated_instruction(vcpu);
7171 * Now copy part of this value to register or memory, as requested.
7172 * Note that the number of bits actually copied is 32 or 64 depending
7173 * on the guest's mode (32 or 64 bit), not on the given field's length.
7175 if (vmx_instruction_info & (1u << 10)) {
7176 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7179 if (get_vmx_mem_address(vcpu, exit_qualification,
7180 vmx_instruction_info, true, &gva))
7182 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7183 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7184 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7187 nested_vmx_succeed(vcpu);
7188 skip_emulated_instruction(vcpu);
7193 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7195 unsigned long field;
7197 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7198 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7199 /* The value to write might be 32 or 64 bits, depending on L1's long
7200 * mode, and eventually we need to write that into a field of several
7201 * possible lengths. The code below first zero-extends the value to 64
7202 * bit (field_value), and then copies only the approriate number of
7203 * bits into the vmcs12 field.
7205 u64 field_value = 0;
7206 struct x86_exception e;
7208 if (!nested_vmx_check_permission(vcpu) ||
7209 !nested_vmx_check_vmcs12(vcpu))
7212 if (vmx_instruction_info & (1u << 10))
7213 field_value = kvm_register_readl(vcpu,
7214 (((vmx_instruction_info) >> 3) & 0xf));
7216 if (get_vmx_mem_address(vcpu, exit_qualification,
7217 vmx_instruction_info, false, &gva))
7219 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7220 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7221 kvm_inject_page_fault(vcpu, &e);
7227 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7228 if (vmcs_field_readonly(field)) {
7229 nested_vmx_failValid(vcpu,
7230 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7231 skip_emulated_instruction(vcpu);
7235 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7236 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7237 skip_emulated_instruction(vcpu);
7241 nested_vmx_succeed(vcpu);
7242 skip_emulated_instruction(vcpu);
7246 /* Emulate the VMPTRLD instruction */
7247 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7249 struct vcpu_vmx *vmx = to_vmx(vcpu);
7252 if (!nested_vmx_check_permission(vcpu))
7255 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7258 if (vmx->nested.current_vmptr != vmptr) {
7259 struct vmcs12 *new_vmcs12;
7261 page = nested_get_page(vcpu, vmptr);
7263 nested_vmx_failInvalid(vcpu);
7264 skip_emulated_instruction(vcpu);
7267 new_vmcs12 = kmap(page);
7268 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7270 nested_release_page_clean(page);
7271 nested_vmx_failValid(vcpu,
7272 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7273 skip_emulated_instruction(vcpu);
7277 nested_release_vmcs12(vmx);
7278 vmx->nested.current_vmptr = vmptr;
7279 vmx->nested.current_vmcs12 = new_vmcs12;
7280 vmx->nested.current_vmcs12_page = page;
7281 if (enable_shadow_vmcs) {
7282 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7283 SECONDARY_EXEC_SHADOW_VMCS);
7284 vmcs_write64(VMCS_LINK_POINTER,
7285 __pa(vmx->nested.current_shadow_vmcs));
7286 vmx->nested.sync_shadow_vmcs = true;
7290 nested_vmx_succeed(vcpu);
7291 skip_emulated_instruction(vcpu);
7295 /* Emulate the VMPTRST instruction */
7296 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7298 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7299 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7301 struct x86_exception e;
7303 if (!nested_vmx_check_permission(vcpu))
7306 if (get_vmx_mem_address(vcpu, exit_qualification,
7307 vmx_instruction_info, true, &vmcs_gva))
7309 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7310 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7311 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7313 kvm_inject_page_fault(vcpu, &e);
7316 nested_vmx_succeed(vcpu);
7317 skip_emulated_instruction(vcpu);
7321 /* Emulate the INVEPT instruction */
7322 static int handle_invept(struct kvm_vcpu *vcpu)
7324 struct vcpu_vmx *vmx = to_vmx(vcpu);
7325 u32 vmx_instruction_info, types;
7328 struct x86_exception e;
7333 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7334 SECONDARY_EXEC_ENABLE_EPT) ||
7335 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7336 kvm_queue_exception(vcpu, UD_VECTOR);
7340 if (!nested_vmx_check_permission(vcpu))
7343 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7344 kvm_queue_exception(vcpu, UD_VECTOR);
7348 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7349 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7351 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7353 if (!(types & (1UL << type))) {
7354 nested_vmx_failValid(vcpu,
7355 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7356 skip_emulated_instruction(vcpu);
7360 /* According to the Intel VMX instruction reference, the memory
7361 * operand is read even if it isn't needed (e.g., for type==global)
7363 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7364 vmx_instruction_info, false, &gva))
7366 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7367 sizeof(operand), &e)) {
7368 kvm_inject_page_fault(vcpu, &e);
7373 case VMX_EPT_EXTENT_GLOBAL:
7374 kvm_mmu_sync_roots(vcpu);
7375 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7376 nested_vmx_succeed(vcpu);
7379 /* Trap single context invalidation invept calls */
7384 skip_emulated_instruction(vcpu);
7388 static int handle_invvpid(struct kvm_vcpu *vcpu)
7390 struct vcpu_vmx *vmx = to_vmx(vcpu);
7391 u32 vmx_instruction_info;
7392 unsigned long type, types;
7394 struct x86_exception e;
7397 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7398 SECONDARY_EXEC_ENABLE_VPID) ||
7399 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7400 kvm_queue_exception(vcpu, UD_VECTOR);
7404 if (!nested_vmx_check_permission(vcpu))
7407 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7408 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7410 types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7412 if (!(types & (1UL << type))) {
7413 nested_vmx_failValid(vcpu,
7414 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7415 skip_emulated_instruction(vcpu);
7419 /* according to the intel vmx instruction reference, the memory
7420 * operand is read even if it isn't needed (e.g., for type==global)
7422 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7423 vmx_instruction_info, false, &gva))
7425 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7427 kvm_inject_page_fault(vcpu, &e);
7432 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7434 * Old versions of KVM use the single-context version so we
7435 * have to support it; just treat it the same as all-context.
7437 case VMX_VPID_EXTENT_ALL_CONTEXT:
7438 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7439 nested_vmx_succeed(vcpu);
7442 /* Trap individual address invalidation invvpid calls */
7447 skip_emulated_instruction(vcpu);
7451 static int handle_pml_full(struct kvm_vcpu *vcpu)
7453 unsigned long exit_qualification;
7455 trace_kvm_pml_full(vcpu->vcpu_id);
7457 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7460 * PML buffer FULL happened while executing iret from NMI,
7461 * "blocked by NMI" bit has to be set before next VM entry.
7463 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7464 cpu_has_virtual_nmis() &&
7465 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7466 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7467 GUEST_INTR_STATE_NMI);
7470 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7471 * here.., and there's no userspace involvement needed for PML.
7476 static int handle_pcommit(struct kvm_vcpu *vcpu)
7478 /* we never catch pcommit instruct for L1 guest. */
7484 * The exit handlers return 1 if the exit was handled fully and guest execution
7485 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7486 * to be done to userspace and return 0.
7488 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7489 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7490 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7491 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7492 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7493 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7494 [EXIT_REASON_CR_ACCESS] = handle_cr,
7495 [EXIT_REASON_DR_ACCESS] = handle_dr,
7496 [EXIT_REASON_CPUID] = handle_cpuid,
7497 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7498 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7499 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7500 [EXIT_REASON_HLT] = handle_halt,
7501 [EXIT_REASON_INVD] = handle_invd,
7502 [EXIT_REASON_INVLPG] = handle_invlpg,
7503 [EXIT_REASON_RDPMC] = handle_rdpmc,
7504 [EXIT_REASON_VMCALL] = handle_vmcall,
7505 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7506 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7507 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7508 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7509 [EXIT_REASON_VMREAD] = handle_vmread,
7510 [EXIT_REASON_VMRESUME] = handle_vmresume,
7511 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7512 [EXIT_REASON_VMOFF] = handle_vmoff,
7513 [EXIT_REASON_VMON] = handle_vmon,
7514 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7515 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7516 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7517 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7518 [EXIT_REASON_WBINVD] = handle_wbinvd,
7519 [EXIT_REASON_XSETBV] = handle_xsetbv,
7520 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7521 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7522 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7523 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7524 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7525 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7526 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7527 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7528 [EXIT_REASON_INVEPT] = handle_invept,
7529 [EXIT_REASON_INVVPID] = handle_invvpid,
7530 [EXIT_REASON_XSAVES] = handle_xsaves,
7531 [EXIT_REASON_XRSTORS] = handle_xrstors,
7532 [EXIT_REASON_PML_FULL] = handle_pml_full,
7533 [EXIT_REASON_PCOMMIT] = handle_pcommit,
7536 static const int kvm_vmx_max_exit_handlers =
7537 ARRAY_SIZE(kvm_vmx_exit_handlers);
7539 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7540 struct vmcs12 *vmcs12)
7542 unsigned long exit_qualification;
7543 gpa_t bitmap, last_bitmap;
7548 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7549 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7551 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7553 port = exit_qualification >> 16;
7554 size = (exit_qualification & 7) + 1;
7556 last_bitmap = (gpa_t)-1;
7561 bitmap = vmcs12->io_bitmap_a;
7562 else if (port < 0x10000)
7563 bitmap = vmcs12->io_bitmap_b;
7566 bitmap += (port & 0x7fff) / 8;
7568 if (last_bitmap != bitmap)
7569 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7571 if (b & (1 << (port & 7)))
7576 last_bitmap = bitmap;
7583 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7584 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7585 * disinterest in the current event (read or write a specific MSR) by using an
7586 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7588 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7589 struct vmcs12 *vmcs12, u32 exit_reason)
7591 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7594 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7598 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7599 * for the four combinations of read/write and low/high MSR numbers.
7600 * First we need to figure out which of the four to use:
7602 bitmap = vmcs12->msr_bitmap;
7603 if (exit_reason == EXIT_REASON_MSR_WRITE)
7605 if (msr_index >= 0xc0000000) {
7606 msr_index -= 0xc0000000;
7610 /* Then read the msr_index'th bit from this bitmap: */
7611 if (msr_index < 1024*8) {
7613 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7615 return 1 & (b >> (msr_index & 7));
7617 return true; /* let L1 handle the wrong parameter */
7621 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7622 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7623 * intercept (via guest_host_mask etc.) the current event.
7625 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7626 struct vmcs12 *vmcs12)
7628 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7629 int cr = exit_qualification & 15;
7630 int reg = (exit_qualification >> 8) & 15;
7631 unsigned long val = kvm_register_readl(vcpu, reg);
7633 switch ((exit_qualification >> 4) & 3) {
7634 case 0: /* mov to cr */
7637 if (vmcs12->cr0_guest_host_mask &
7638 (val ^ vmcs12->cr0_read_shadow))
7642 if ((vmcs12->cr3_target_count >= 1 &&
7643 vmcs12->cr3_target_value0 == val) ||
7644 (vmcs12->cr3_target_count >= 2 &&
7645 vmcs12->cr3_target_value1 == val) ||
7646 (vmcs12->cr3_target_count >= 3 &&
7647 vmcs12->cr3_target_value2 == val) ||
7648 (vmcs12->cr3_target_count >= 4 &&
7649 vmcs12->cr3_target_value3 == val))
7651 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7655 if (vmcs12->cr4_guest_host_mask &
7656 (vmcs12->cr4_read_shadow ^ val))
7660 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7666 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7667 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7670 case 1: /* mov from cr */
7673 if (vmcs12->cpu_based_vm_exec_control &
7674 CPU_BASED_CR3_STORE_EXITING)
7678 if (vmcs12->cpu_based_vm_exec_control &
7679 CPU_BASED_CR8_STORE_EXITING)
7686 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7687 * cr0. Other attempted changes are ignored, with no exit.
7689 if (vmcs12->cr0_guest_host_mask & 0xe &
7690 (val ^ vmcs12->cr0_read_shadow))
7692 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7693 !(vmcs12->cr0_read_shadow & 0x1) &&
7702 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7703 * should handle it ourselves in L0 (and then continue L2). Only call this
7704 * when in is_guest_mode (L2).
7706 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7708 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7709 struct vcpu_vmx *vmx = to_vmx(vcpu);
7710 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7711 u32 exit_reason = vmx->exit_reason;
7713 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7714 vmcs_readl(EXIT_QUALIFICATION),
7715 vmx->idt_vectoring_info,
7717 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7720 if (vmx->nested.nested_run_pending)
7723 if (unlikely(vmx->fail)) {
7724 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7725 vmcs_read32(VM_INSTRUCTION_ERROR));
7729 switch (exit_reason) {
7730 case EXIT_REASON_EXCEPTION_NMI:
7731 if (is_nmi(intr_info))
7733 else if (is_page_fault(intr_info))
7735 else if (is_no_device(intr_info) &&
7736 !(vmcs12->guest_cr0 & X86_CR0_TS))
7738 return vmcs12->exception_bitmap &
7739 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7740 case EXIT_REASON_EXTERNAL_INTERRUPT:
7742 case EXIT_REASON_TRIPLE_FAULT:
7744 case EXIT_REASON_PENDING_INTERRUPT:
7745 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7746 case EXIT_REASON_NMI_WINDOW:
7747 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7748 case EXIT_REASON_TASK_SWITCH:
7750 case EXIT_REASON_CPUID:
7751 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7754 case EXIT_REASON_HLT:
7755 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7756 case EXIT_REASON_INVD:
7758 case EXIT_REASON_INVLPG:
7759 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7760 case EXIT_REASON_RDPMC:
7761 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7762 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7763 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7764 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7765 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7766 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7767 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7768 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7769 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7771 * VMX instructions trap unconditionally. This allows L1 to
7772 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7775 case EXIT_REASON_CR_ACCESS:
7776 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7777 case EXIT_REASON_DR_ACCESS:
7778 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7779 case EXIT_REASON_IO_INSTRUCTION:
7780 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7781 case EXIT_REASON_MSR_READ:
7782 case EXIT_REASON_MSR_WRITE:
7783 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7784 case EXIT_REASON_INVALID_STATE:
7786 case EXIT_REASON_MWAIT_INSTRUCTION:
7787 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7788 case EXIT_REASON_MONITOR_TRAP_FLAG:
7789 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7790 case EXIT_REASON_MONITOR_INSTRUCTION:
7791 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7792 case EXIT_REASON_PAUSE_INSTRUCTION:
7793 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7794 nested_cpu_has2(vmcs12,
7795 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7796 case EXIT_REASON_MCE_DURING_VMENTRY:
7798 case EXIT_REASON_TPR_BELOW_THRESHOLD:
7799 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7800 case EXIT_REASON_APIC_ACCESS:
7801 return nested_cpu_has2(vmcs12,
7802 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7803 case EXIT_REASON_APIC_WRITE:
7804 case EXIT_REASON_EOI_INDUCED:
7805 /* apic_write and eoi_induced should exit unconditionally. */
7807 case EXIT_REASON_EPT_VIOLATION:
7809 * L0 always deals with the EPT violation. If nested EPT is
7810 * used, and the nested mmu code discovers that the address is
7811 * missing in the guest EPT table (EPT12), the EPT violation
7812 * will be injected with nested_ept_inject_page_fault()
7815 case EXIT_REASON_EPT_MISCONFIG:
7817 * L2 never uses directly L1's EPT, but rather L0's own EPT
7818 * table (shadow on EPT) or a merged EPT table that L0 built
7819 * (EPT on EPT). So any problems with the structure of the
7820 * table is L0's fault.
7823 case EXIT_REASON_WBINVD:
7824 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7825 case EXIT_REASON_XSETBV:
7827 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7829 * This should never happen, since it is not possible to
7830 * set XSS to a non-zero value---neither in L1 nor in L2.
7831 * If if it were, XSS would have to be checked against
7832 * the XSS exit bitmap in vmcs12.
7834 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7835 case EXIT_REASON_PCOMMIT:
7836 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7842 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7844 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7845 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7848 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7851 __free_page(vmx->pml_pg);
7856 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7858 struct vcpu_vmx *vmx = to_vmx(vcpu);
7862 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7864 /* Do nothing if PML buffer is empty */
7865 if (pml_idx == (PML_ENTITY_NUM - 1))
7868 /* PML index always points to next available PML buffer entity */
7869 if (pml_idx >= PML_ENTITY_NUM)
7874 pml_buf = page_address(vmx->pml_pg);
7875 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7878 gpa = pml_buf[pml_idx];
7879 WARN_ON(gpa & (PAGE_SIZE - 1));
7880 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7883 /* reset PML index */
7884 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7888 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7889 * Called before reporting dirty_bitmap to userspace.
7891 static void kvm_flush_pml_buffers(struct kvm *kvm)
7894 struct kvm_vcpu *vcpu;
7896 * We only need to kick vcpu out of guest mode here, as PML buffer
7897 * is flushed at beginning of all VMEXITs, and it's obvious that only
7898 * vcpus running in guest are possible to have unflushed GPAs in PML
7901 kvm_for_each_vcpu(i, vcpu, kvm)
7902 kvm_vcpu_kick(vcpu);
7905 static void vmx_dump_sel(char *name, uint32_t sel)
7907 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7908 name, vmcs_read32(sel),
7909 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7910 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7911 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7914 static void vmx_dump_dtsel(char *name, uint32_t limit)
7916 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7917 name, vmcs_read32(limit),
7918 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7921 static void dump_vmcs(void)
7923 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7924 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7925 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7926 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7927 u32 secondary_exec_control = 0;
7928 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7929 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7932 if (cpu_has_secondary_exec_ctrls())
7933 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7935 pr_err("*** Guest State ***\n");
7936 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7937 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7938 vmcs_readl(CR0_GUEST_HOST_MASK));
7939 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7940 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7941 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7942 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7943 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7945 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7946 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7947 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7948 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7950 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7951 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7952 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7953 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7954 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7955 vmcs_readl(GUEST_SYSENTER_ESP),
7956 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7957 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7958 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7959 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7960 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7961 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7962 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7963 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7964 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7965 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7966 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7967 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7968 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7969 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7970 efer, vmcs_readl(GUEST_IA32_PAT));
7971 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7972 vmcs_readl(GUEST_IA32_DEBUGCTL),
7973 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7974 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7975 pr_err("PerfGlobCtl = 0x%016lx\n",
7976 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7977 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7978 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7979 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7980 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7981 vmcs_read32(GUEST_ACTIVITY_STATE));
7982 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7983 pr_err("InterruptStatus = %04x\n",
7984 vmcs_read16(GUEST_INTR_STATUS));
7986 pr_err("*** Host State ***\n");
7987 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7988 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7989 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7990 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7991 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7992 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7993 vmcs_read16(HOST_TR_SELECTOR));
7994 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7995 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7996 vmcs_readl(HOST_TR_BASE));
7997 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7998 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7999 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8000 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8001 vmcs_readl(HOST_CR4));
8002 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8003 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8004 vmcs_read32(HOST_IA32_SYSENTER_CS),
8005 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8006 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8007 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
8008 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
8009 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8010 pr_err("PerfGlobCtl = 0x%016lx\n",
8011 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
8013 pr_err("*** Control State ***\n");
8014 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8015 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8016 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8017 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8018 vmcs_read32(EXCEPTION_BITMAP),
8019 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8020 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8021 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8022 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8023 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8024 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8025 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8026 vmcs_read32(VM_EXIT_INTR_INFO),
8027 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8028 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8029 pr_err(" reason=%08x qualification=%016lx\n",
8030 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8031 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8032 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8033 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8034 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8035 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8036 pr_err("TSC Multiplier = 0x%016lx\n",
8037 vmcs_readl(TSC_MULTIPLIER));
8038 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8039 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8040 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8041 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8042 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8043 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8044 n = vmcs_read32(CR3_TARGET_COUNT);
8045 for (i = 0; i + 1 < n; i += 4)
8046 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8047 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8048 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8050 pr_err("CR3 target%u=%016lx\n",
8051 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8052 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8053 pr_err("PLE Gap=%08x Window=%08x\n",
8054 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8055 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8056 pr_err("Virtual processor ID = 0x%04x\n",
8057 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8061 * The guest has exited. See if we can fix it or if we need userspace
8064 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8066 struct vcpu_vmx *vmx = to_vmx(vcpu);
8067 u32 exit_reason = vmx->exit_reason;
8068 u32 vectoring_info = vmx->idt_vectoring_info;
8070 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8073 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8074 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8075 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8076 * mode as if vcpus is in root mode, the PML buffer must has been
8080 vmx_flush_pml_buffer(vcpu);
8082 /* If guest state is invalid, start emulating */
8083 if (vmx->emulation_required)
8084 return handle_invalid_guest_state(vcpu);
8086 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8087 nested_vmx_vmexit(vcpu, exit_reason,
8088 vmcs_read32(VM_EXIT_INTR_INFO),
8089 vmcs_readl(EXIT_QUALIFICATION));
8093 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8095 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8096 vcpu->run->fail_entry.hardware_entry_failure_reason
8101 if (unlikely(vmx->fail)) {
8102 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8103 vcpu->run->fail_entry.hardware_entry_failure_reason
8104 = vmcs_read32(VM_INSTRUCTION_ERROR);
8110 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8111 * delivery event since it indicates guest is accessing MMIO.
8112 * The vm-exit can be triggered again after return to guest that
8113 * will cause infinite loop.
8115 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8116 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8117 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8118 exit_reason != EXIT_REASON_PML_FULL &&
8119 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8120 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8121 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8122 vcpu->run->internal.ndata = 2;
8123 vcpu->run->internal.data[0] = vectoring_info;
8124 vcpu->run->internal.data[1] = exit_reason;
8128 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8129 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8130 get_vmcs12(vcpu))))) {
8131 if (vmx_interrupt_allowed(vcpu)) {
8132 vmx->soft_vnmi_blocked = 0;
8133 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8134 vcpu->arch.nmi_pending) {
8136 * This CPU don't support us in finding the end of an
8137 * NMI-blocked window if the guest runs with IRQs
8138 * disabled. So we pull the trigger after 1 s of
8139 * futile waiting, but inform the user about this.
8141 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8142 "state on VCPU %d after 1 s timeout\n",
8143 __func__, vcpu->vcpu_id);
8144 vmx->soft_vnmi_blocked = 0;
8148 if (exit_reason < kvm_vmx_max_exit_handlers
8149 && kvm_vmx_exit_handlers[exit_reason])
8150 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8152 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8153 kvm_queue_exception(vcpu, UD_VECTOR);
8158 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8160 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8162 if (is_guest_mode(vcpu) &&
8163 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8166 if (irr == -1 || tpr < irr) {
8167 vmcs_write32(TPR_THRESHOLD, 0);
8171 vmcs_write32(TPR_THRESHOLD, irr);
8174 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8176 u32 sec_exec_control;
8178 /* Postpone execution until vmcs01 is the current VMCS. */
8179 if (is_guest_mode(vcpu)) {
8180 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8185 * There is not point to enable virtualize x2apic without enable
8188 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8189 !vmx_cpu_uses_apicv(vcpu))
8192 if (!cpu_need_tpr_shadow(vcpu))
8195 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8198 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8199 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8201 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8202 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8204 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8206 vmx_set_msr_bitmap(vcpu);
8209 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8211 struct vcpu_vmx *vmx = to_vmx(vcpu);
8214 * Currently we do not handle the nested case where L2 has an
8215 * APIC access page of its own; that page is still pinned.
8216 * Hence, we skip the case where the VCPU is in guest mode _and_
8217 * L1 prepared an APIC access page for L2.
8219 * For the case where L1 and L2 share the same APIC access page
8220 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8221 * in the vmcs12), this function will only update either the vmcs01
8222 * or the vmcs02. If the former, the vmcs02 will be updated by
8223 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8224 * the next L2->L1 exit.
8226 if (!is_guest_mode(vcpu) ||
8227 !nested_cpu_has2(vmx->nested.current_vmcs12,
8228 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8229 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8232 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8240 status = vmcs_read16(GUEST_INTR_STATUS);
8245 vmcs_write16(GUEST_INTR_STATUS, status);
8249 static void vmx_set_rvi(int vector)
8257 status = vmcs_read16(GUEST_INTR_STATUS);
8258 old = (u8)status & 0xff;
8259 if ((u8)vector != old) {
8261 status |= (u8)vector;
8262 vmcs_write16(GUEST_INTR_STATUS, status);
8266 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8268 if (!is_guest_mode(vcpu)) {
8269 vmx_set_rvi(max_irr);
8277 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8280 if (nested_exit_on_intr(vcpu))
8284 * Else, fall back to pre-APICv interrupt injection since L2
8285 * is run without virtual interrupt delivery.
8287 if (!kvm_event_needs_reinjection(vcpu) &&
8288 vmx_interrupt_allowed(vcpu)) {
8289 kvm_queue_interrupt(vcpu, max_irr, false);
8290 vmx_inject_irq(vcpu);
8294 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8296 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8297 if (!vmx_cpu_uses_apicv(vcpu))
8300 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8301 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8302 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8303 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8306 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8310 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8311 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8314 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8315 exit_intr_info = vmx->exit_intr_info;
8317 /* Handle machine checks before interrupts are enabled */
8318 if (is_machine_check(exit_intr_info))
8319 kvm_machine_check();
8321 /* We need to handle NMIs before interrupts are enabled */
8322 if (is_nmi(exit_intr_info)) {
8323 kvm_before_handle_nmi(&vmx->vcpu);
8325 kvm_after_handle_nmi(&vmx->vcpu);
8329 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8331 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8334 * If external interrupt exists, IF bit is set in rflags/eflags on the
8335 * interrupt stack frame, and interrupt will be enabled on a return
8336 * from interrupt handler.
8338 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8339 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8340 unsigned int vector;
8341 unsigned long entry;
8343 struct vcpu_vmx *vmx = to_vmx(vcpu);
8344 #ifdef CONFIG_X86_64
8348 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8349 desc = (gate_desc *)vmx->host_idt_base + vector;
8350 entry = gate_offset(*desc);
8352 #ifdef CONFIG_X86_64
8353 "mov %%" _ASM_SP ", %[sp]\n\t"
8354 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8359 "orl $0x200, (%%" _ASM_SP ")\n\t"
8360 __ASM_SIZE(push) " $%c[cs]\n\t"
8361 "call *%[entry]\n\t"
8363 #ifdef CONFIG_X86_64
8368 [ss]"i"(__KERNEL_DS),
8369 [cs]"i"(__KERNEL_CS)
8375 static bool vmx_has_high_real_mode_segbase(void)
8377 return enable_unrestricted_guest || emulate_invalid_guest_state;
8380 static bool vmx_mpx_supported(void)
8382 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8383 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8386 static bool vmx_xsaves_supported(void)
8388 return vmcs_config.cpu_based_2nd_exec_ctrl &
8389 SECONDARY_EXEC_XSAVES;
8392 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8397 bool idtv_info_valid;
8399 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8401 if (cpu_has_virtual_nmis()) {
8402 if (vmx->nmi_known_unmasked)
8405 * Can't use vmx->exit_intr_info since we're not sure what
8406 * the exit reason is.
8408 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8409 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8410 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8412 * SDM 3: 27.7.1.2 (September 2008)
8413 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8414 * a guest IRET fault.
8415 * SDM 3: 23.2.2 (September 2008)
8416 * Bit 12 is undefined in any of the following cases:
8417 * If the VM exit sets the valid bit in the IDT-vectoring
8418 * information field.
8419 * If the VM exit is due to a double fault.
8421 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8422 vector != DF_VECTOR && !idtv_info_valid)
8423 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8424 GUEST_INTR_STATE_NMI);
8426 vmx->nmi_known_unmasked =
8427 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8428 & GUEST_INTR_STATE_NMI);
8429 } else if (unlikely(vmx->soft_vnmi_blocked))
8430 vmx->vnmi_blocked_time +=
8431 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8434 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8435 u32 idt_vectoring_info,
8436 int instr_len_field,
8437 int error_code_field)
8441 bool idtv_info_valid;
8443 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8445 vcpu->arch.nmi_injected = false;
8446 kvm_clear_exception_queue(vcpu);
8447 kvm_clear_interrupt_queue(vcpu);
8449 if (!idtv_info_valid)
8452 kvm_make_request(KVM_REQ_EVENT, vcpu);
8454 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8455 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8458 case INTR_TYPE_NMI_INTR:
8459 vcpu->arch.nmi_injected = true;
8461 * SDM 3: 27.7.1.2 (September 2008)
8462 * Clear bit "block by NMI" before VM entry if a NMI
8465 vmx_set_nmi_mask(vcpu, false);
8467 case INTR_TYPE_SOFT_EXCEPTION:
8468 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8470 case INTR_TYPE_HARD_EXCEPTION:
8471 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8472 u32 err = vmcs_read32(error_code_field);
8473 kvm_requeue_exception_e(vcpu, vector, err);
8475 kvm_requeue_exception(vcpu, vector);
8477 case INTR_TYPE_SOFT_INTR:
8478 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8480 case INTR_TYPE_EXT_INTR:
8481 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8488 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8490 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8491 VM_EXIT_INSTRUCTION_LEN,
8492 IDT_VECTORING_ERROR_CODE);
8495 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8497 __vmx_complete_interrupts(vcpu,
8498 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8499 VM_ENTRY_INSTRUCTION_LEN,
8500 VM_ENTRY_EXCEPTION_ERROR_CODE);
8502 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8505 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8508 struct perf_guest_switch_msr *msrs;
8510 msrs = perf_guest_get_msrs(&nr_msrs);
8515 for (i = 0; i < nr_msrs; i++)
8516 if (msrs[i].host == msrs[i].guest)
8517 clear_atomic_switch_msr(vmx, msrs[i].msr);
8519 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8523 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8525 struct vcpu_vmx *vmx = to_vmx(vcpu);
8526 unsigned long debugctlmsr, cr4;
8528 /* Record the guest's net vcpu time for enforced NMI injections. */
8529 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8530 vmx->entry_time = ktime_get();
8532 /* Don't enter VMX if guest state is invalid, let the exit handler
8533 start emulation until we arrive back to a valid state */
8534 if (vmx->emulation_required)
8537 if (vmx->ple_window_dirty) {
8538 vmx->ple_window_dirty = false;
8539 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8542 if (vmx->nested.sync_shadow_vmcs) {
8543 copy_vmcs12_to_shadow(vmx);
8544 vmx->nested.sync_shadow_vmcs = false;
8547 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8548 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8549 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8550 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8552 cr4 = cr4_read_shadow();
8553 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8554 vmcs_writel(HOST_CR4, cr4);
8555 vmx->host_state.vmcs_host_cr4 = cr4;
8558 /* When single-stepping over STI and MOV SS, we must clear the
8559 * corresponding interruptibility bits in the guest state. Otherwise
8560 * vmentry fails as it then expects bit 14 (BS) in pending debug
8561 * exceptions being set, but that's not correct for the guest debugging
8563 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8564 vmx_set_interrupt_shadow(vcpu, 0);
8566 atomic_switch_perf_msrs(vmx);
8567 debugctlmsr = get_debugctlmsr();
8569 vmx->__launched = vmx->loaded_vmcs->launched;
8571 /* Store host registers */
8572 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8573 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8574 "push %%" _ASM_CX " \n\t"
8575 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8577 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8578 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8580 /* Reload cr2 if changed */
8581 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8582 "mov %%cr2, %%" _ASM_DX " \n\t"
8583 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8585 "mov %%" _ASM_AX", %%cr2 \n\t"
8587 /* Check if vmlaunch of vmresume is needed */
8588 "cmpl $0, %c[launched](%0) \n\t"
8589 /* Load guest registers. Don't clobber flags. */
8590 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8591 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8592 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8593 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8594 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8595 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8596 #ifdef CONFIG_X86_64
8597 "mov %c[r8](%0), %%r8 \n\t"
8598 "mov %c[r9](%0), %%r9 \n\t"
8599 "mov %c[r10](%0), %%r10 \n\t"
8600 "mov %c[r11](%0), %%r11 \n\t"
8601 "mov %c[r12](%0), %%r12 \n\t"
8602 "mov %c[r13](%0), %%r13 \n\t"
8603 "mov %c[r14](%0), %%r14 \n\t"
8604 "mov %c[r15](%0), %%r15 \n\t"
8606 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8608 /* Enter guest mode */
8610 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8612 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8614 /* Save guest registers, load host registers, keep flags */
8615 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8617 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8618 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8619 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8620 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8621 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8622 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8623 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8624 #ifdef CONFIG_X86_64
8625 "mov %%r8, %c[r8](%0) \n\t"
8626 "mov %%r9, %c[r9](%0) \n\t"
8627 "mov %%r10, %c[r10](%0) \n\t"
8628 "mov %%r11, %c[r11](%0) \n\t"
8629 "mov %%r12, %c[r12](%0) \n\t"
8630 "mov %%r13, %c[r13](%0) \n\t"
8631 "mov %%r14, %c[r14](%0) \n\t"
8632 "mov %%r15, %c[r15](%0) \n\t"
8634 "mov %%cr2, %%" _ASM_AX " \n\t"
8635 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8637 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8638 "setbe %c[fail](%0) \n\t"
8639 ".pushsection .rodata \n\t"
8640 ".global vmx_return \n\t"
8641 "vmx_return: " _ASM_PTR " 2b \n\t"
8643 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8644 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8645 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8646 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8647 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8648 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8649 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8650 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8651 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8652 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8653 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8654 #ifdef CONFIG_X86_64
8655 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8656 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8657 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8658 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8659 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8660 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8661 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8662 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8664 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8665 [wordsize]"i"(sizeof(ulong))
8667 #ifdef CONFIG_X86_64
8668 , "rax", "rbx", "rdi", "rsi"
8669 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8671 , "eax", "ebx", "edi", "esi"
8675 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8677 update_debugctlmsr(debugctlmsr);
8679 #ifndef CONFIG_X86_64
8681 * The sysexit path does not restore ds/es, so we must set them to
8682 * a reasonable value ourselves.
8684 * We can't defer this to vmx_load_host_state() since that function
8685 * may be executed in interrupt context, which saves and restore segments
8686 * around it, nullifying its effect.
8688 loadsegment(ds, __USER_DS);
8689 loadsegment(es, __USER_DS);
8692 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8693 | (1 << VCPU_EXREG_RFLAGS)
8694 | (1 << VCPU_EXREG_PDPTR)
8695 | (1 << VCPU_EXREG_SEGMENTS)
8696 | (1 << VCPU_EXREG_CR3));
8697 vcpu->arch.regs_dirty = 0;
8699 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8701 vmx->loaded_vmcs->launched = 1;
8703 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8706 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8707 * we did not inject a still-pending event to L1 now because of
8708 * nested_run_pending, we need to re-enable this bit.
8710 if (vmx->nested.nested_run_pending)
8711 kvm_make_request(KVM_REQ_EVENT, vcpu);
8713 vmx->nested.nested_run_pending = 0;
8715 vmx_complete_atomic_exit(vmx);
8716 vmx_recover_nmi_blocking(vmx);
8717 vmx_complete_interrupts(vmx);
8720 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8722 struct vcpu_vmx *vmx = to_vmx(vcpu);
8725 if (vmx->loaded_vmcs == &vmx->vmcs01)
8729 vmx->loaded_vmcs = &vmx->vmcs01;
8731 vmx_vcpu_load(vcpu, cpu);
8737 * Ensure that the current vmcs of the logical processor is the
8738 * vmcs01 of the vcpu before calling free_nested().
8740 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
8742 struct vcpu_vmx *vmx = to_vmx(vcpu);
8745 r = vcpu_load(vcpu);
8747 vmx_load_vmcs01(vcpu);
8752 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8754 struct vcpu_vmx *vmx = to_vmx(vcpu);
8757 vmx_destroy_pml_buffer(vmx);
8758 free_vpid(vmx->vpid);
8759 leave_guest_mode(vcpu);
8760 vmx_free_vcpu_nested(vcpu);
8761 free_loaded_vmcs(vmx->loaded_vmcs);
8762 kfree(vmx->guest_msrs);
8763 kvm_vcpu_uninit(vcpu);
8764 kmem_cache_free(kvm_vcpu_cache, vmx);
8767 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8770 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8774 return ERR_PTR(-ENOMEM);
8776 vmx->vpid = allocate_vpid();
8778 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8785 * If PML is turned on, failure on enabling PML just results in failure
8786 * of creating the vcpu, therefore we can simplify PML logic (by
8787 * avoiding dealing with cases, such as enabling PML partially on vcpus
8788 * for the guest, etc.
8791 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
8796 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8797 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8800 if (!vmx->guest_msrs)
8803 vmx->loaded_vmcs = &vmx->vmcs01;
8804 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8805 if (!vmx->loaded_vmcs->vmcs)
8808 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8809 loaded_vmcs_init(vmx->loaded_vmcs);
8814 vmx_vcpu_load(&vmx->vcpu, cpu);
8815 vmx->vcpu.cpu = cpu;
8816 err = vmx_vcpu_setup(vmx);
8817 vmx_vcpu_put(&vmx->vcpu);
8821 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8822 err = alloc_apic_access_page(kvm);
8828 if (!kvm->arch.ept_identity_map_addr)
8829 kvm->arch.ept_identity_map_addr =
8830 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8831 err = init_rmode_identity_map(kvm);
8837 nested_vmx_setup_ctls_msrs(vmx);
8838 vmx->nested.vpid02 = allocate_vpid();
8841 vmx->nested.posted_intr_nv = -1;
8842 vmx->nested.current_vmptr = -1ull;
8843 vmx->nested.current_vmcs12 = NULL;
8848 free_vpid(vmx->nested.vpid02);
8849 free_loaded_vmcs(vmx->loaded_vmcs);
8851 kfree(vmx->guest_msrs);
8853 vmx_destroy_pml_buffer(vmx);
8855 kvm_vcpu_uninit(&vmx->vcpu);
8857 free_vpid(vmx->vpid);
8858 kmem_cache_free(kvm_vcpu_cache, vmx);
8859 return ERR_PTR(err);
8862 static void __init vmx_check_processor_compat(void *rtn)
8864 struct vmcs_config vmcs_conf;
8867 if (setup_vmcs_config(&vmcs_conf) < 0)
8869 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8870 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8871 smp_processor_id());
8876 static int get_ept_level(void)
8878 return VMX_EPT_DEFAULT_GAW + 1;
8881 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8886 /* For VT-d and EPT combination
8887 * 1. MMIO: always map as UC
8889 * a. VT-d without snooping control feature: can't guarantee the
8890 * result, try to trust guest.
8891 * b. VT-d with snooping control feature: snooping control feature of
8892 * VT-d engine can guarantee the cache correctness. Just set it
8893 * to WB to keep consistent with host. So the same as item 3.
8894 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8895 * consistent with host MTRR
8898 cache = MTRR_TYPE_UNCACHABLE;
8902 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8903 ipat = VMX_EPT_IPAT_BIT;
8904 cache = MTRR_TYPE_WRBACK;
8908 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8909 ipat = VMX_EPT_IPAT_BIT;
8910 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8911 cache = MTRR_TYPE_WRBACK;
8913 cache = MTRR_TYPE_UNCACHABLE;
8917 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8920 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8923 static int vmx_get_lpage_level(void)
8925 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8926 return PT_DIRECTORY_LEVEL;
8928 /* For shadow and EPT supported 1GB page */
8929 return PT_PDPE_LEVEL;
8932 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8935 * These bits in the secondary execution controls field
8936 * are dynamic, the others are mostly based on the hypervisor
8937 * architecture and the guest's CPUID. Do not touch the
8941 SECONDARY_EXEC_SHADOW_VMCS |
8942 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8943 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8945 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8947 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8948 (new_ctl & ~mask) | (cur_ctl & mask));
8951 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8953 struct kvm_cpuid_entry2 *best;
8954 struct vcpu_vmx *vmx = to_vmx(vcpu);
8955 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8957 if (vmx_rdtscp_supported()) {
8958 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8959 if (!rdtscp_enabled)
8960 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8964 vmx->nested.nested_vmx_secondary_ctls_high |=
8965 SECONDARY_EXEC_RDTSCP;
8967 vmx->nested.nested_vmx_secondary_ctls_high &=
8968 ~SECONDARY_EXEC_RDTSCP;
8972 /* Exposing INVPCID only when PCID is exposed */
8973 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8974 if (vmx_invpcid_supported() &&
8975 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8976 !guest_cpuid_has_pcid(vcpu))) {
8977 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8980 best->ebx &= ~bit(X86_FEATURE_INVPCID);
8983 if (cpu_has_secondary_exec_ctrls())
8984 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8986 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8987 if (guest_cpuid_has_pcommit(vcpu))
8988 vmx->nested.nested_vmx_secondary_ctls_high |=
8989 SECONDARY_EXEC_PCOMMIT;
8991 vmx->nested.nested_vmx_secondary_ctls_high &=
8992 ~SECONDARY_EXEC_PCOMMIT;
8996 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8998 if (func == 1 && nested)
8999 entry->ecx |= bit(X86_FEATURE_VMX);
9002 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9003 struct x86_exception *fault)
9005 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9008 if (fault->error_code & PFERR_RSVD_MASK)
9009 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9011 exit_reason = EXIT_REASON_EPT_VIOLATION;
9012 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9013 vmcs12->guest_physical_address = fault->address;
9016 /* Callbacks for nested_ept_init_mmu_context: */
9018 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9020 /* return the page table to be shadowed - in our case, EPT12 */
9021 return get_vmcs12(vcpu)->ept_pointer;
9024 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9026 WARN_ON(mmu_is_nested(vcpu));
9027 kvm_init_shadow_ept_mmu(vcpu,
9028 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9029 VMX_EPT_EXECUTE_ONLY_BIT);
9030 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9031 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9032 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9034 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9037 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9039 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9042 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9045 bool inequality, bit;
9047 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9049 (error_code & vmcs12->page_fault_error_code_mask) !=
9050 vmcs12->page_fault_error_code_match;
9051 return inequality ^ bit;
9054 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9055 struct x86_exception *fault)
9057 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9059 WARN_ON(!is_guest_mode(vcpu));
9061 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9062 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9063 vmcs_read32(VM_EXIT_INTR_INFO),
9064 vmcs_readl(EXIT_QUALIFICATION));
9066 kvm_inject_page_fault(vcpu, fault);
9069 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9070 struct vmcs12 *vmcs12)
9072 struct vcpu_vmx *vmx = to_vmx(vcpu);
9073 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9075 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9076 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9077 vmcs12->apic_access_addr >> maxphyaddr)
9081 * Translate L1 physical address to host physical
9082 * address for vmcs02. Keep the page pinned, so this
9083 * physical address remains valid. We keep a reference
9084 * to it so we can release it later.
9086 if (vmx->nested.apic_access_page) /* shouldn't happen */
9087 nested_release_page(vmx->nested.apic_access_page);
9088 vmx->nested.apic_access_page =
9089 nested_get_page(vcpu, vmcs12->apic_access_addr);
9092 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9093 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9094 vmcs12->virtual_apic_page_addr >> maxphyaddr)
9097 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9098 nested_release_page(vmx->nested.virtual_apic_page);
9099 vmx->nested.virtual_apic_page =
9100 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9103 * Failing the vm entry is _not_ what the processor does
9104 * but it's basically the only possibility we have.
9105 * We could still enter the guest if CR8 load exits are
9106 * enabled, CR8 store exits are enabled, and virtualize APIC
9107 * access is disabled; in this case the processor would never
9108 * use the TPR shadow and we could simply clear the bit from
9109 * the execution control. But such a configuration is useless,
9110 * so let's keep the code simple.
9112 if (!vmx->nested.virtual_apic_page)
9116 if (nested_cpu_has_posted_intr(vmcs12)) {
9117 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9118 vmcs12->posted_intr_desc_addr >> maxphyaddr)
9121 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9122 kunmap(vmx->nested.pi_desc_page);
9123 nested_release_page(vmx->nested.pi_desc_page);
9125 vmx->nested.pi_desc_page =
9126 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9127 if (!vmx->nested.pi_desc_page)
9130 vmx->nested.pi_desc =
9131 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9132 if (!vmx->nested.pi_desc) {
9133 nested_release_page_clean(vmx->nested.pi_desc_page);
9136 vmx->nested.pi_desc =
9137 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9138 (unsigned long)(vmcs12->posted_intr_desc_addr &
9145 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9147 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9148 struct vcpu_vmx *vmx = to_vmx(vcpu);
9150 if (vcpu->arch.virtual_tsc_khz == 0)
9153 /* Make sure short timeouts reliably trigger an immediate vmexit.
9154 * hrtimer_start does not guarantee this. */
9155 if (preemption_timeout <= 1) {
9156 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9160 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9161 preemption_timeout *= 1000000;
9162 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9163 hrtimer_start(&vmx->nested.preemption_timer,
9164 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9167 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9168 struct vmcs12 *vmcs12)
9173 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9176 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9180 maxphyaddr = cpuid_maxphyaddr(vcpu);
9182 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9183 ((addr + PAGE_SIZE) >> maxphyaddr))
9190 * Merge L0's and L1's MSR bitmap, return false to indicate that
9191 * we do not use the hardware.
9193 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9194 struct vmcs12 *vmcs12)
9198 unsigned long *msr_bitmap;
9200 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9203 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9208 msr_bitmap = (unsigned long *)kmap(page);
9210 nested_release_page_clean(page);
9215 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9216 if (nested_cpu_has_apic_reg_virt(vmcs12))
9217 for (msr = 0x800; msr <= 0x8ff; msr++)
9218 nested_vmx_disable_intercept_for_msr(
9220 vmx_msr_bitmap_nested,
9222 /* TPR is allowed */
9223 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9224 vmx_msr_bitmap_nested,
9225 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9226 MSR_TYPE_R | MSR_TYPE_W);
9227 if (nested_cpu_has_vid(vmcs12)) {
9228 /* EOI and self-IPI are allowed */
9229 nested_vmx_disable_intercept_for_msr(
9231 vmx_msr_bitmap_nested,
9232 APIC_BASE_MSR + (APIC_EOI >> 4),
9234 nested_vmx_disable_intercept_for_msr(
9236 vmx_msr_bitmap_nested,
9237 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9242 * Enable reading intercept of all the x2apic
9243 * MSRs. We should not rely on vmcs12 to do any
9244 * optimizations here, it may have been modified
9247 for (msr = 0x800; msr <= 0x8ff; msr++)
9248 __vmx_enable_intercept_for_msr(
9249 vmx_msr_bitmap_nested,
9253 __vmx_enable_intercept_for_msr(
9254 vmx_msr_bitmap_nested,
9255 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9257 __vmx_enable_intercept_for_msr(
9258 vmx_msr_bitmap_nested,
9259 APIC_BASE_MSR + (APIC_EOI >> 4),
9261 __vmx_enable_intercept_for_msr(
9262 vmx_msr_bitmap_nested,
9263 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9267 nested_release_page_clean(page);
9272 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9273 struct vmcs12 *vmcs12)
9275 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9276 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9277 !nested_cpu_has_vid(vmcs12) &&
9278 !nested_cpu_has_posted_intr(vmcs12))
9282 * If virtualize x2apic mode is enabled,
9283 * virtualize apic access must be disabled.
9285 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9286 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9290 * If virtual interrupt delivery is enabled,
9291 * we must exit on external interrupts.
9293 if (nested_cpu_has_vid(vmcs12) &&
9294 !nested_exit_on_intr(vcpu))
9298 * bits 15:8 should be zero in posted_intr_nv,
9299 * the descriptor address has been already checked
9300 * in nested_get_vmcs12_pages.
9302 if (nested_cpu_has_posted_intr(vmcs12) &&
9303 (!nested_cpu_has_vid(vmcs12) ||
9304 !nested_exit_intr_ack_set(vcpu) ||
9305 vmcs12->posted_intr_nv & 0xff00))
9308 /* tpr shadow is needed by all apicv features. */
9309 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9315 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9316 unsigned long count_field,
9317 unsigned long addr_field)
9322 if (vmcs12_read_any(vcpu, count_field, &count) ||
9323 vmcs12_read_any(vcpu, addr_field, &addr)) {
9329 maxphyaddr = cpuid_maxphyaddr(vcpu);
9330 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9331 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9332 pr_warn_ratelimited(
9333 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9334 addr_field, maxphyaddr, count, addr);
9340 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9341 struct vmcs12 *vmcs12)
9343 if (vmcs12->vm_exit_msr_load_count == 0 &&
9344 vmcs12->vm_exit_msr_store_count == 0 &&
9345 vmcs12->vm_entry_msr_load_count == 0)
9346 return 0; /* Fast path */
9347 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9348 VM_EXIT_MSR_LOAD_ADDR) ||
9349 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9350 VM_EXIT_MSR_STORE_ADDR) ||
9351 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9352 VM_ENTRY_MSR_LOAD_ADDR))
9357 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9358 struct vmx_msr_entry *e)
9360 /* x2APIC MSR accesses are not allowed */
9361 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9363 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9364 e->index == MSR_IA32_UCODE_REV)
9366 if (e->reserved != 0)
9371 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9372 struct vmx_msr_entry *e)
9374 if (e->index == MSR_FS_BASE ||
9375 e->index == MSR_GS_BASE ||
9376 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9377 nested_vmx_msr_check_common(vcpu, e))
9382 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9383 struct vmx_msr_entry *e)
9385 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9386 nested_vmx_msr_check_common(vcpu, e))
9392 * Load guest's/host's msr at nested entry/exit.
9393 * return 0 for success, entry index for failure.
9395 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9398 struct vmx_msr_entry e;
9399 struct msr_data msr;
9401 msr.host_initiated = false;
9402 for (i = 0; i < count; i++) {
9403 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9405 pr_warn_ratelimited(
9406 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9407 __func__, i, gpa + i * sizeof(e));
9410 if (nested_vmx_load_msr_check(vcpu, &e)) {
9411 pr_warn_ratelimited(
9412 "%s check failed (%u, 0x%x, 0x%x)\n",
9413 __func__, i, e.index, e.reserved);
9416 msr.index = e.index;
9418 if (kvm_set_msr(vcpu, &msr)) {
9419 pr_warn_ratelimited(
9420 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9421 __func__, i, e.index, e.value);
9430 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9433 struct vmx_msr_entry e;
9435 for (i = 0; i < count; i++) {
9436 struct msr_data msr_info;
9437 if (kvm_vcpu_read_guest(vcpu,
9438 gpa + i * sizeof(e),
9439 &e, 2 * sizeof(u32))) {
9440 pr_warn_ratelimited(
9441 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9442 __func__, i, gpa + i * sizeof(e));
9445 if (nested_vmx_store_msr_check(vcpu, &e)) {
9446 pr_warn_ratelimited(
9447 "%s check failed (%u, 0x%x, 0x%x)\n",
9448 __func__, i, e.index, e.reserved);
9451 msr_info.host_initiated = false;
9452 msr_info.index = e.index;
9453 if (kvm_get_msr(vcpu, &msr_info)) {
9454 pr_warn_ratelimited(
9455 "%s cannot read MSR (%u, 0x%x)\n",
9456 __func__, i, e.index);
9459 if (kvm_vcpu_write_guest(vcpu,
9460 gpa + i * sizeof(e) +
9461 offsetof(struct vmx_msr_entry, value),
9462 &msr_info.data, sizeof(msr_info.data))) {
9463 pr_warn_ratelimited(
9464 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9465 __func__, i, e.index, msr_info.data);
9473 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9474 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9475 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9476 * guest in a way that will both be appropriate to L1's requests, and our
9477 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9478 * function also has additional necessary side-effects, like setting various
9479 * vcpu->arch fields.
9481 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9483 struct vcpu_vmx *vmx = to_vmx(vcpu);
9486 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9487 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9488 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9489 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9490 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9491 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9492 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9493 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9494 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9495 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9496 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9497 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9498 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9499 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9500 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9501 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9502 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9503 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9504 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9505 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9506 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9507 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9508 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9509 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9510 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9511 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9512 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9513 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9514 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9515 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9516 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9517 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9518 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9519 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9520 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9521 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9523 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9524 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9525 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9527 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9528 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9530 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9531 vmcs12->vm_entry_intr_info_field);
9532 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9533 vmcs12->vm_entry_exception_error_code);
9534 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9535 vmcs12->vm_entry_instruction_len);
9536 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9537 vmcs12->guest_interruptibility_info);
9538 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9539 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9540 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9541 vmcs12->guest_pending_dbg_exceptions);
9542 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9543 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9545 if (nested_cpu_has_xsaves(vmcs12))
9546 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9547 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9549 exec_control = vmcs12->pin_based_vm_exec_control;
9550 exec_control |= vmcs_config.pin_based_exec_ctrl;
9551 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9553 if (nested_cpu_has_posted_intr(vmcs12)) {
9555 * Note that we use L0's vector here and in
9556 * vmx_deliver_nested_posted_interrupt.
9558 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9559 vmx->nested.pi_pending = false;
9560 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9561 vmcs_write64(POSTED_INTR_DESC_ADDR,
9562 page_to_phys(vmx->nested.pi_desc_page) +
9563 (unsigned long)(vmcs12->posted_intr_desc_addr &
9566 exec_control &= ~PIN_BASED_POSTED_INTR;
9568 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9570 vmx->nested.preemption_timer_expired = false;
9571 if (nested_cpu_has_preemption_timer(vmcs12))
9572 vmx_start_preemption_timer(vcpu);
9575 * Whether page-faults are trapped is determined by a combination of
9576 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9577 * If enable_ept, L0 doesn't care about page faults and we should
9578 * set all of these to L1's desires. However, if !enable_ept, L0 does
9579 * care about (at least some) page faults, and because it is not easy
9580 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9581 * to exit on each and every L2 page fault. This is done by setting
9582 * MASK=MATCH=0 and (see below) EB.PF=1.
9583 * Note that below we don't need special code to set EB.PF beyond the
9584 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9585 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9586 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9588 * A problem with this approach (when !enable_ept) is that L1 may be
9589 * injected with more page faults than it asked for. This could have
9590 * caused problems, but in practice existing hypervisors don't care.
9591 * To fix this, we will need to emulate the PFEC checking (on the L1
9592 * page tables), using walk_addr(), when injecting PFs to L1.
9594 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9595 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9596 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9597 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9599 if (cpu_has_secondary_exec_ctrls()) {
9600 exec_control = vmx_secondary_exec_control(vmx);
9602 /* Take the following fields only from vmcs12 */
9603 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9604 SECONDARY_EXEC_RDTSCP |
9605 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9606 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9607 SECONDARY_EXEC_PCOMMIT);
9608 if (nested_cpu_has(vmcs12,
9609 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9610 exec_control |= vmcs12->secondary_vm_exec_control;
9612 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9614 * If translation failed, no matter: This feature asks
9615 * to exit when accessing the given address, and if it
9616 * can never be accessed, this feature won't do
9619 if (!vmx->nested.apic_access_page)
9621 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9623 vmcs_write64(APIC_ACCESS_ADDR,
9624 page_to_phys(vmx->nested.apic_access_page));
9625 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9626 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9628 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9629 kvm_vcpu_reload_apic_access_page(vcpu);
9632 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9633 vmcs_write64(EOI_EXIT_BITMAP0,
9634 vmcs12->eoi_exit_bitmap0);
9635 vmcs_write64(EOI_EXIT_BITMAP1,
9636 vmcs12->eoi_exit_bitmap1);
9637 vmcs_write64(EOI_EXIT_BITMAP2,
9638 vmcs12->eoi_exit_bitmap2);
9639 vmcs_write64(EOI_EXIT_BITMAP3,
9640 vmcs12->eoi_exit_bitmap3);
9641 vmcs_write16(GUEST_INTR_STATUS,
9642 vmcs12->guest_intr_status);
9645 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9650 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9651 * Some constant fields are set here by vmx_set_constant_host_state().
9652 * Other fields are different per CPU, and will be set later when
9653 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9655 vmx_set_constant_host_state(vmx);
9658 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9659 * entry, but only if the current (host) sp changed from the value
9660 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9661 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9662 * here we just force the write to happen on entry.
9666 exec_control = vmx_exec_control(vmx); /* L0's desires */
9667 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9668 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9669 exec_control &= ~CPU_BASED_TPR_SHADOW;
9670 exec_control |= vmcs12->cpu_based_vm_exec_control;
9672 if (exec_control & CPU_BASED_TPR_SHADOW) {
9673 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9674 page_to_phys(vmx->nested.virtual_apic_page));
9675 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9678 if (cpu_has_vmx_msr_bitmap() &&
9679 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9680 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9681 /* MSR_BITMAP will be set by following vmx_set_efer. */
9683 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9686 * Merging of IO bitmap not currently supported.
9687 * Rather, exit every time.
9689 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9690 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9692 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9694 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9695 * bitwise-or of what L1 wants to trap for L2, and what we want to
9696 * trap. Note that CR0.TS also needs updating - we do this later.
9698 update_exception_bitmap(vcpu);
9699 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9700 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9702 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9703 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9704 * bits are further modified by vmx_set_efer() below.
9706 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9708 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9709 * emulated by vmx_set_efer(), below.
9711 vm_entry_controls_init(vmx,
9712 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9713 ~VM_ENTRY_IA32E_MODE) |
9714 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9716 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9717 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9718 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9719 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9720 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9723 set_cr4_guest_host_mask(vmx);
9725 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9726 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9728 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9729 vmcs_write64(TSC_OFFSET,
9730 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9732 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9736 * There is no direct mapping between vpid02 and vpid12, the
9737 * vpid02 is per-vCPU for L0 and reused while the value of
9738 * vpid12 is changed w/ one invvpid during nested vmentry.
9739 * The vpid12 is allocated by L1 for L2, so it will not
9740 * influence global bitmap(for vpid01 and vpid02 allocation)
9741 * even if spawn a lot of nested vCPUs.
9743 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9744 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9745 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9746 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9747 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9750 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9751 vmx_flush_tlb(vcpu);
9756 if (nested_cpu_has_ept(vmcs12)) {
9757 kvm_mmu_unload(vcpu);
9758 nested_ept_init_mmu_context(vcpu);
9761 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9762 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9763 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9764 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9766 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9767 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9768 vmx_set_efer(vcpu, vcpu->arch.efer);
9771 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9772 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9773 * The CR0_READ_SHADOW is what L2 should have expected to read given
9774 * the specifications by L1; It's not enough to take
9775 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9776 * have more bits than L1 expected.
9778 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9779 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9781 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9782 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9784 /* shadow page tables on either EPT or shadow page tables */
9785 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9786 kvm_mmu_reset_context(vcpu);
9789 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9792 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9795 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9796 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9797 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9798 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9801 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9802 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9806 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9807 * for running an L2 nested guest.
9809 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9811 struct vmcs12 *vmcs12;
9812 struct vcpu_vmx *vmx = to_vmx(vcpu);
9814 struct loaded_vmcs *vmcs02;
9818 if (!nested_vmx_check_permission(vcpu) ||
9819 !nested_vmx_check_vmcs12(vcpu))
9822 skip_emulated_instruction(vcpu);
9823 vmcs12 = get_vmcs12(vcpu);
9825 if (enable_shadow_vmcs)
9826 copy_shadow_to_vmcs12(vmx);
9829 * The nested entry process starts with enforcing various prerequisites
9830 * on vmcs12 as required by the Intel SDM, and act appropriately when
9831 * they fail: As the SDM explains, some conditions should cause the
9832 * instruction to fail, while others will cause the instruction to seem
9833 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9834 * To speed up the normal (success) code path, we should avoid checking
9835 * for misconfigurations which will anyway be caught by the processor
9836 * when using the merged vmcs02.
9838 if (vmcs12->launch_state == launch) {
9839 nested_vmx_failValid(vcpu,
9840 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9841 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9845 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9846 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9847 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9851 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9852 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9856 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9857 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9861 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9862 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9866 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9867 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9871 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9872 vmx->nested.nested_vmx_true_procbased_ctls_low,
9873 vmx->nested.nested_vmx_procbased_ctls_high) ||
9874 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9875 vmx->nested.nested_vmx_secondary_ctls_low,
9876 vmx->nested.nested_vmx_secondary_ctls_high) ||
9877 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9878 vmx->nested.nested_vmx_pinbased_ctls_low,
9879 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9880 !vmx_control_verify(vmcs12->vm_exit_controls,
9881 vmx->nested.nested_vmx_true_exit_ctls_low,
9882 vmx->nested.nested_vmx_exit_ctls_high) ||
9883 !vmx_control_verify(vmcs12->vm_entry_controls,
9884 vmx->nested.nested_vmx_true_entry_ctls_low,
9885 vmx->nested.nested_vmx_entry_ctls_high))
9887 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9891 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9892 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9893 nested_vmx_failValid(vcpu,
9894 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9898 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9899 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9900 nested_vmx_entry_failure(vcpu, vmcs12,
9901 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9904 if (vmcs12->vmcs_link_pointer != -1ull) {
9905 nested_vmx_entry_failure(vcpu, vmcs12,
9906 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9911 * If the load IA32_EFER VM-entry control is 1, the following checks
9912 * are performed on the field for the IA32_EFER MSR:
9913 * - Bits reserved in the IA32_EFER MSR must be 0.
9914 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9915 * the IA-32e mode guest VM-exit control. It must also be identical
9916 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9919 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9920 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9921 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9922 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9923 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9924 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9925 nested_vmx_entry_failure(vcpu, vmcs12,
9926 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9932 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9933 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9934 * the values of the LMA and LME bits in the field must each be that of
9935 * the host address-space size VM-exit control.
9937 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9938 ia32e = (vmcs12->vm_exit_controls &
9939 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9940 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9941 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9942 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9943 nested_vmx_entry_failure(vcpu, vmcs12,
9944 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9950 * We're finally done with prerequisite checking, and can start with
9954 vmcs02 = nested_get_current_vmcs02(vmx);
9958 enter_guest_mode(vcpu);
9960 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9962 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9963 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9966 vmx->loaded_vmcs = vmcs02;
9968 vmx_vcpu_load(vcpu, cpu);
9972 vmx_segment_cache_clear(vmx);
9974 prepare_vmcs02(vcpu, vmcs12);
9976 msr_entry_idx = nested_vmx_load_msr(vcpu,
9977 vmcs12->vm_entry_msr_load_addr,
9978 vmcs12->vm_entry_msr_load_count);
9979 if (msr_entry_idx) {
9980 leave_guest_mode(vcpu);
9981 vmx_load_vmcs01(vcpu);
9982 nested_vmx_entry_failure(vcpu, vmcs12,
9983 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9987 vmcs12->launch_state = 1;
9989 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9990 return kvm_vcpu_halt(vcpu);
9992 vmx->nested.nested_run_pending = 1;
9995 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9996 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9997 * returned as far as L1 is concerned. It will only return (and set
9998 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10004 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10005 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10006 * This function returns the new value we should put in vmcs12.guest_cr0.
10007 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10008 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10009 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10010 * didn't trap the bit, because if L1 did, so would L0).
10011 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10012 * been modified by L2, and L1 knows it. So just leave the old value of
10013 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10014 * isn't relevant, because if L0 traps this bit it can set it to anything.
10015 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10016 * changed these bits, and therefore they need to be updated, but L0
10017 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10018 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10020 static inline unsigned long
10021 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10024 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10025 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10026 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10027 vcpu->arch.cr0_guest_owned_bits));
10030 static inline unsigned long
10031 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10034 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10035 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10036 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10037 vcpu->arch.cr4_guest_owned_bits));
10040 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10041 struct vmcs12 *vmcs12)
10046 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10047 nr = vcpu->arch.exception.nr;
10048 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10050 if (kvm_exception_is_soft(nr)) {
10051 vmcs12->vm_exit_instruction_len =
10052 vcpu->arch.event_exit_inst_len;
10053 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10055 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10057 if (vcpu->arch.exception.has_error_code) {
10058 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10059 vmcs12->idt_vectoring_error_code =
10060 vcpu->arch.exception.error_code;
10063 vmcs12->idt_vectoring_info_field = idt_vectoring;
10064 } else if (vcpu->arch.nmi_injected) {
10065 vmcs12->idt_vectoring_info_field =
10066 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10067 } else if (vcpu->arch.interrupt.pending) {
10068 nr = vcpu->arch.interrupt.nr;
10069 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10071 if (vcpu->arch.interrupt.soft) {
10072 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10073 vmcs12->vm_entry_instruction_len =
10074 vcpu->arch.event_exit_inst_len;
10076 idt_vectoring |= INTR_TYPE_EXT_INTR;
10078 vmcs12->idt_vectoring_info_field = idt_vectoring;
10082 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10084 struct vcpu_vmx *vmx = to_vmx(vcpu);
10086 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10087 vmx->nested.preemption_timer_expired) {
10088 if (vmx->nested.nested_run_pending)
10090 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10094 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10095 if (vmx->nested.nested_run_pending ||
10096 vcpu->arch.interrupt.pending)
10098 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10099 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10100 INTR_INFO_VALID_MASK, 0);
10102 * The NMI-triggered VM exit counts as injection:
10103 * clear this one and block further NMIs.
10105 vcpu->arch.nmi_pending = 0;
10106 vmx_set_nmi_mask(vcpu, true);
10110 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10111 nested_exit_on_intr(vcpu)) {
10112 if (vmx->nested.nested_run_pending)
10114 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10118 return vmx_complete_nested_posted_interrupt(vcpu);
10121 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10123 ktime_t remaining =
10124 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10127 if (ktime_to_ns(remaining) <= 0)
10130 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10131 do_div(value, 1000000);
10132 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10136 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10137 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10138 * and this function updates it to reflect the changes to the guest state while
10139 * L2 was running (and perhaps made some exits which were handled directly by L0
10140 * without going back to L1), and to reflect the exit reason.
10141 * Note that we do not have to copy here all VMCS fields, just those that
10142 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10143 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10144 * which already writes to vmcs12 directly.
10146 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10147 u32 exit_reason, u32 exit_intr_info,
10148 unsigned long exit_qualification)
10150 /* update guest state fields: */
10151 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10152 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10154 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10155 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10156 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10158 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10159 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10160 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10161 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10162 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10163 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10164 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10165 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10166 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10167 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10168 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10169 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10170 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10171 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10172 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10173 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10174 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10175 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10176 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10177 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10178 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10179 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10180 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10181 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10182 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10183 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10184 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10185 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10186 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10187 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10188 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10189 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10190 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10191 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10192 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10193 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10195 vmcs12->guest_interruptibility_info =
10196 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10197 vmcs12->guest_pending_dbg_exceptions =
10198 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10199 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10200 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10202 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10204 if (nested_cpu_has_preemption_timer(vmcs12)) {
10205 if (vmcs12->vm_exit_controls &
10206 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10207 vmcs12->vmx_preemption_timer_value =
10208 vmx_get_preemption_timer_value(vcpu);
10209 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10213 * In some cases (usually, nested EPT), L2 is allowed to change its
10214 * own CR3 without exiting. If it has changed it, we must keep it.
10215 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10216 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10218 * Additionally, restore L2's PDPTR to vmcs12.
10221 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10222 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10223 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10224 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10225 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10228 if (nested_cpu_has_vid(vmcs12))
10229 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10231 vmcs12->vm_entry_controls =
10232 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10233 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10235 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10236 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10237 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10240 /* TODO: These cannot have changed unless we have MSR bitmaps and
10241 * the relevant bit asks not to trap the change */
10242 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10243 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10244 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10245 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10246 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10247 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10248 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10249 if (vmx_mpx_supported())
10250 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10251 if (nested_cpu_has_xsaves(vmcs12))
10252 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10254 /* update exit information fields: */
10256 vmcs12->vm_exit_reason = exit_reason;
10257 vmcs12->exit_qualification = exit_qualification;
10259 vmcs12->vm_exit_intr_info = exit_intr_info;
10260 if ((vmcs12->vm_exit_intr_info &
10261 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10262 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10263 vmcs12->vm_exit_intr_error_code =
10264 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10265 vmcs12->idt_vectoring_info_field = 0;
10266 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10267 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10269 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10270 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10271 * instead of reading the real value. */
10272 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10275 * Transfer the event that L0 or L1 may wanted to inject into
10276 * L2 to IDT_VECTORING_INFO_FIELD.
10278 vmcs12_save_pending_event(vcpu, vmcs12);
10282 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10283 * preserved above and would only end up incorrectly in L1.
10285 vcpu->arch.nmi_injected = false;
10286 kvm_clear_exception_queue(vcpu);
10287 kvm_clear_interrupt_queue(vcpu);
10291 * A part of what we need to when the nested L2 guest exits and we want to
10292 * run its L1 parent, is to reset L1's guest state to the host state specified
10294 * This function is to be called not only on normal nested exit, but also on
10295 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10296 * Failures During or After Loading Guest State").
10297 * This function should be called when the active VMCS is L1's (vmcs01).
10299 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10300 struct vmcs12 *vmcs12)
10302 struct kvm_segment seg;
10304 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10305 vcpu->arch.efer = vmcs12->host_ia32_efer;
10306 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10307 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10309 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10310 vmx_set_efer(vcpu, vcpu->arch.efer);
10312 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10313 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10314 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10316 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10317 * actually changed, because it depends on the current state of
10318 * fpu_active (which may have changed).
10319 * Note that vmx_set_cr0 refers to efer set above.
10321 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10323 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10324 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10325 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10327 update_exception_bitmap(vcpu);
10328 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10329 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10332 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10333 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10335 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10336 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10338 nested_ept_uninit_mmu_context(vcpu);
10340 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10341 kvm_mmu_reset_context(vcpu);
10344 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10348 * Trivially support vpid by letting L2s share their parent
10349 * L1's vpid. TODO: move to a more elaborate solution, giving
10350 * each L2 its own vpid and exposing the vpid feature to L1.
10352 vmx_flush_tlb(vcpu);
10356 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10357 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10358 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10359 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10360 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10362 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10363 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10364 vmcs_write64(GUEST_BNDCFGS, 0);
10366 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10367 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10368 vcpu->arch.pat = vmcs12->host_ia32_pat;
10370 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10371 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10372 vmcs12->host_ia32_perf_global_ctrl);
10374 /* Set L1 segment info according to Intel SDM
10375 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10376 seg = (struct kvm_segment) {
10378 .limit = 0xFFFFFFFF,
10379 .selector = vmcs12->host_cs_selector,
10385 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10389 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10390 seg = (struct kvm_segment) {
10392 .limit = 0xFFFFFFFF,
10399 seg.selector = vmcs12->host_ds_selector;
10400 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10401 seg.selector = vmcs12->host_es_selector;
10402 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10403 seg.selector = vmcs12->host_ss_selector;
10404 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10405 seg.selector = vmcs12->host_fs_selector;
10406 seg.base = vmcs12->host_fs_base;
10407 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10408 seg.selector = vmcs12->host_gs_selector;
10409 seg.base = vmcs12->host_gs_base;
10410 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10411 seg = (struct kvm_segment) {
10412 .base = vmcs12->host_tr_base,
10414 .selector = vmcs12->host_tr_selector,
10418 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10420 kvm_set_dr(vcpu, 7, 0x400);
10421 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10423 if (cpu_has_vmx_msr_bitmap())
10424 vmx_set_msr_bitmap(vcpu);
10426 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10427 vmcs12->vm_exit_msr_load_count))
10428 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10432 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10433 * and modify vmcs12 to make it see what it would expect to see there if
10434 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10436 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10437 u32 exit_intr_info,
10438 unsigned long exit_qualification)
10440 struct vcpu_vmx *vmx = to_vmx(vcpu);
10441 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10443 /* trying to cancel vmlaunch/vmresume is a bug */
10444 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10446 leave_guest_mode(vcpu);
10447 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10448 exit_qualification);
10450 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10451 vmcs12->vm_exit_msr_store_count))
10452 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10454 vmx_load_vmcs01(vcpu);
10456 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10457 && nested_exit_intr_ack_set(vcpu)) {
10458 int irq = kvm_cpu_get_interrupt(vcpu);
10460 vmcs12->vm_exit_intr_info = irq |
10461 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10464 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10465 vmcs12->exit_qualification,
10466 vmcs12->idt_vectoring_info_field,
10467 vmcs12->vm_exit_intr_info,
10468 vmcs12->vm_exit_intr_error_code,
10471 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10472 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10473 vmx_segment_cache_clear(vmx);
10475 /* if no vmcs02 cache requested, remove the one we used */
10476 if (VMCS02_POOL_SIZE == 0)
10477 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10479 load_vmcs12_host_state(vcpu, vmcs12);
10481 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10482 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10484 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10485 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
10486 vmx_set_virtual_x2apic_mode(vcpu,
10487 vcpu->arch.apic_base & X2APIC_ENABLE);
10490 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10493 /* Unpin physical memory we referred to in vmcs02 */
10494 if (vmx->nested.apic_access_page) {
10495 nested_release_page(vmx->nested.apic_access_page);
10496 vmx->nested.apic_access_page = NULL;
10498 if (vmx->nested.virtual_apic_page) {
10499 nested_release_page(vmx->nested.virtual_apic_page);
10500 vmx->nested.virtual_apic_page = NULL;
10502 if (vmx->nested.pi_desc_page) {
10503 kunmap(vmx->nested.pi_desc_page);
10504 nested_release_page(vmx->nested.pi_desc_page);
10505 vmx->nested.pi_desc_page = NULL;
10506 vmx->nested.pi_desc = NULL;
10510 * We are now running in L2, mmu_notifier will force to reload the
10511 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10513 kvm_vcpu_reload_apic_access_page(vcpu);
10516 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10517 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10518 * success or failure flag accordingly.
10520 if (unlikely(vmx->fail)) {
10522 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10524 nested_vmx_succeed(vcpu);
10525 if (enable_shadow_vmcs)
10526 vmx->nested.sync_shadow_vmcs = true;
10528 /* in case we halted in L2 */
10529 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10533 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10535 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10537 if (is_guest_mode(vcpu))
10538 nested_vmx_vmexit(vcpu, -1, 0, 0);
10539 free_nested(to_vmx(vcpu));
10543 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10544 * 23.7 "VM-entry failures during or after loading guest state" (this also
10545 * lists the acceptable exit-reason and exit-qualification parameters).
10546 * It should only be called before L2 actually succeeded to run, and when
10547 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10549 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10550 struct vmcs12 *vmcs12,
10551 u32 reason, unsigned long qualification)
10553 load_vmcs12_host_state(vcpu, vmcs12);
10554 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10555 vmcs12->exit_qualification = qualification;
10556 nested_vmx_succeed(vcpu);
10557 if (enable_shadow_vmcs)
10558 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10561 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10562 struct x86_instruction_info *info,
10563 enum x86_intercept_stage stage)
10565 return X86EMUL_CONTINUE;
10568 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10571 shrink_ple_window(vcpu);
10574 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10575 struct kvm_memory_slot *slot)
10577 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10578 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10581 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10582 struct kvm_memory_slot *slot)
10584 kvm_mmu_slot_set_dirty(kvm, slot);
10587 static void vmx_flush_log_dirty(struct kvm *kvm)
10589 kvm_flush_pml_buffers(kvm);
10592 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10593 struct kvm_memory_slot *memslot,
10594 gfn_t offset, unsigned long mask)
10596 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10600 * This routine does the following things for vCPU which is going
10601 * to be blocked if VT-d PI is enabled.
10602 * - Store the vCPU to the wakeup list, so when interrupts happen
10603 * we can find the right vCPU to wake up.
10604 * - Change the Posted-interrupt descriptor as below:
10605 * 'NDST' <-- vcpu->pre_pcpu
10606 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10607 * - If 'ON' is set during this process, which means at least one
10608 * interrupt is posted for this vCPU, we cannot block it, in
10609 * this case, return 1, otherwise, return 0.
10612 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10614 unsigned long flags;
10616 struct pi_desc old, new;
10617 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10619 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10620 !irq_remapping_cap(IRQ_POSTING_CAP))
10623 vcpu->pre_pcpu = vcpu->cpu;
10624 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10625 vcpu->pre_pcpu), flags);
10626 list_add_tail(&vcpu->blocked_vcpu_list,
10627 &per_cpu(blocked_vcpu_on_cpu,
10629 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10630 vcpu->pre_pcpu), flags);
10633 old.control = new.control = pi_desc->control;
10636 * We should not block the vCPU if
10637 * an interrupt is posted for it.
10639 if (pi_test_on(pi_desc) == 1) {
10640 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10641 vcpu->pre_pcpu), flags);
10642 list_del(&vcpu->blocked_vcpu_list);
10643 spin_unlock_irqrestore(
10644 &per_cpu(blocked_vcpu_on_cpu_lock,
10645 vcpu->pre_pcpu), flags);
10646 vcpu->pre_pcpu = -1;
10651 WARN((pi_desc->sn == 1),
10652 "Warning: SN field of posted-interrupts "
10653 "is set before blocking\n");
10656 * Since vCPU can be preempted during this process,
10657 * vcpu->cpu could be different with pre_pcpu, we
10658 * need to set pre_pcpu as the destination of wakeup
10659 * notification event, then we can find the right vCPU
10660 * to wakeup in wakeup handler if interrupts happen
10661 * when the vCPU is in blocked state.
10663 dest = cpu_physical_id(vcpu->pre_pcpu);
10665 if (x2apic_enabled())
10668 new.ndst = (dest << 8) & 0xFF00;
10670 /* set 'NV' to 'wakeup vector' */
10671 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10672 } while (cmpxchg(&pi_desc->control, old.control,
10673 new.control) != old.control);
10678 static void vmx_post_block(struct kvm_vcpu *vcpu)
10680 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10681 struct pi_desc old, new;
10683 unsigned long flags;
10685 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10686 !irq_remapping_cap(IRQ_POSTING_CAP))
10690 old.control = new.control = pi_desc->control;
10692 dest = cpu_physical_id(vcpu->cpu);
10694 if (x2apic_enabled())
10697 new.ndst = (dest << 8) & 0xFF00;
10699 /* Allow posting non-urgent interrupts */
10702 /* set 'NV' to 'notification vector' */
10703 new.nv = POSTED_INTR_VECTOR;
10704 } while (cmpxchg(&pi_desc->control, old.control,
10705 new.control) != old.control);
10707 if(vcpu->pre_pcpu != -1) {
10709 &per_cpu(blocked_vcpu_on_cpu_lock,
10710 vcpu->pre_pcpu), flags);
10711 list_del(&vcpu->blocked_vcpu_list);
10712 spin_unlock_irqrestore(
10713 &per_cpu(blocked_vcpu_on_cpu_lock,
10714 vcpu->pre_pcpu), flags);
10715 vcpu->pre_pcpu = -1;
10720 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10723 * @host_irq: host irq of the interrupt
10724 * @guest_irq: gsi of the interrupt
10725 * @set: set or unset PI
10726 * returns 0 on success, < 0 on failure
10728 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10729 uint32_t guest_irq, bool set)
10731 struct kvm_kernel_irq_routing_entry *e;
10732 struct kvm_irq_routing_table *irq_rt;
10733 struct kvm_lapic_irq irq;
10734 struct kvm_vcpu *vcpu;
10735 struct vcpu_data vcpu_info;
10736 int idx, ret = -EINVAL;
10738 if (!kvm_arch_has_assigned_device(kvm) ||
10739 !irq_remapping_cap(IRQ_POSTING_CAP))
10742 idx = srcu_read_lock(&kvm->irq_srcu);
10743 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10744 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10746 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10747 if (e->type != KVM_IRQ_ROUTING_MSI)
10750 * VT-d PI cannot support posting multicast/broadcast
10751 * interrupts to a vCPU, we still use interrupt remapping
10752 * for these kind of interrupts.
10754 * For lowest-priority interrupts, we only support
10755 * those with single CPU as the destination, e.g. user
10756 * configures the interrupts via /proc/irq or uses
10757 * irqbalance to make the interrupts single-CPU.
10759 * We will support full lowest-priority interrupt later.
10762 kvm_set_msi_irq(e, &irq);
10763 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10766 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10767 vcpu_info.vector = irq.vector;
10769 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10770 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10773 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10775 /* suppress notification event before unposting */
10776 pi_set_sn(vcpu_to_pi_desc(vcpu));
10777 ret = irq_set_vcpu_affinity(host_irq, NULL);
10778 pi_clear_sn(vcpu_to_pi_desc(vcpu));
10782 printk(KERN_INFO "%s: failed to update PI IRTE\n",
10790 srcu_read_unlock(&kvm->irq_srcu, idx);
10794 static struct kvm_x86_ops vmx_x86_ops = {
10795 .cpu_has_kvm_support = cpu_has_kvm_support,
10796 .disabled_by_bios = vmx_disabled_by_bios,
10797 .hardware_setup = hardware_setup,
10798 .hardware_unsetup = hardware_unsetup,
10799 .check_processor_compatibility = vmx_check_processor_compat,
10800 .hardware_enable = hardware_enable,
10801 .hardware_disable = hardware_disable,
10802 .cpu_has_accelerated_tpr = report_flexpriority,
10803 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10805 .vcpu_create = vmx_create_vcpu,
10806 .vcpu_free = vmx_free_vcpu,
10807 .vcpu_reset = vmx_vcpu_reset,
10809 .prepare_guest_switch = vmx_save_host_state,
10810 .vcpu_load = vmx_vcpu_load,
10811 .vcpu_put = vmx_vcpu_put,
10813 .update_bp_intercept = update_exception_bitmap,
10814 .get_msr = vmx_get_msr,
10815 .set_msr = vmx_set_msr,
10816 .get_segment_base = vmx_get_segment_base,
10817 .get_segment = vmx_get_segment,
10818 .set_segment = vmx_set_segment,
10819 .get_cpl = vmx_get_cpl,
10820 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10821 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10822 .decache_cr3 = vmx_decache_cr3,
10823 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10824 .set_cr0 = vmx_set_cr0,
10825 .set_cr3 = vmx_set_cr3,
10826 .set_cr4 = vmx_set_cr4,
10827 .set_efer = vmx_set_efer,
10828 .get_idt = vmx_get_idt,
10829 .set_idt = vmx_set_idt,
10830 .get_gdt = vmx_get_gdt,
10831 .set_gdt = vmx_set_gdt,
10832 .get_dr6 = vmx_get_dr6,
10833 .set_dr6 = vmx_set_dr6,
10834 .set_dr7 = vmx_set_dr7,
10835 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10836 .cache_reg = vmx_cache_reg,
10837 .get_rflags = vmx_get_rflags,
10838 .set_rflags = vmx_set_rflags,
10839 .fpu_activate = vmx_fpu_activate,
10840 .fpu_deactivate = vmx_fpu_deactivate,
10842 .tlb_flush = vmx_flush_tlb,
10844 .run = vmx_vcpu_run,
10845 .handle_exit = vmx_handle_exit,
10846 .skip_emulated_instruction = skip_emulated_instruction,
10847 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10848 .get_interrupt_shadow = vmx_get_interrupt_shadow,
10849 .patch_hypercall = vmx_patch_hypercall,
10850 .set_irq = vmx_inject_irq,
10851 .set_nmi = vmx_inject_nmi,
10852 .queue_exception = vmx_queue_exception,
10853 .cancel_injection = vmx_cancel_injection,
10854 .interrupt_allowed = vmx_interrupt_allowed,
10855 .nmi_allowed = vmx_nmi_allowed,
10856 .get_nmi_mask = vmx_get_nmi_mask,
10857 .set_nmi_mask = vmx_set_nmi_mask,
10858 .enable_nmi_window = enable_nmi_window,
10859 .enable_irq_window = enable_irq_window,
10860 .update_cr8_intercept = update_cr8_intercept,
10861 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10862 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10863 .cpu_uses_apicv = vmx_cpu_uses_apicv,
10864 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10865 .hwapic_irr_update = vmx_hwapic_irr_update,
10866 .hwapic_isr_update = vmx_hwapic_isr_update,
10867 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10868 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10870 .set_tss_addr = vmx_set_tss_addr,
10871 .get_tdp_level = get_ept_level,
10872 .get_mt_mask = vmx_get_mt_mask,
10874 .get_exit_info = vmx_get_exit_info,
10876 .get_lpage_level = vmx_get_lpage_level,
10878 .cpuid_update = vmx_cpuid_update,
10880 .rdtscp_supported = vmx_rdtscp_supported,
10881 .invpcid_supported = vmx_invpcid_supported,
10883 .set_supported_cpuid = vmx_set_supported_cpuid,
10885 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10887 .read_tsc_offset = vmx_read_tsc_offset,
10888 .write_tsc_offset = vmx_write_tsc_offset,
10889 .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10890 .read_l1_tsc = vmx_read_l1_tsc,
10892 .set_tdp_cr3 = vmx_set_cr3,
10894 .check_intercept = vmx_check_intercept,
10895 .handle_external_intr = vmx_handle_external_intr,
10896 .mpx_supported = vmx_mpx_supported,
10897 .xsaves_supported = vmx_xsaves_supported,
10899 .check_nested_events = vmx_check_nested_events,
10901 .sched_in = vmx_sched_in,
10903 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10904 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10905 .flush_log_dirty = vmx_flush_log_dirty,
10906 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10908 .pre_block = vmx_pre_block,
10909 .post_block = vmx_post_block,
10911 .pmu_ops = &intel_pmu_ops,
10913 .update_pi_irte = vmx_update_pi_irte,
10916 static int __init vmx_init(void)
10918 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10919 __alignof__(struct vcpu_vmx), THIS_MODULE);
10923 #ifdef CONFIG_KEXEC_CORE
10924 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10925 crash_vmclear_local_loaded_vmcss);
10931 static void __exit vmx_exit(void)
10933 #ifdef CONFIG_KEXEC_CORE
10934 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10941 module_init(vmx_init)
10942 module_exit(vmx_exit)