arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * ple_gap:    upper bound on the amount of time between two successive
 120  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 121  *             According to test, this time is usually smaller than 128 cycles.
 122  * ple_window: upper bound on the amount of time a guest is allowed to execute
 123  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 124  *             less than 2^12 cycles
 125  * Time is measured based on a counter that runs at the same rate as the TSC,
 126  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 127  */
 128 #define KVM_VMX_DEFAULT_PLE_GAP    128
 129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 130 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 131 module_param(ple_gap, int, S_IRUGO);
 132
 133 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 134 module_param(ple_window, int, S_IRUGO);
 135
 136 extern const ulong vmx_return;
 137
 138 #define NR_AUTOLOAD_MSRS 8
 139 #define VMCS02_POOL_SIZE 1
 140
 141 struct vmcs {
 142         u32 revision_id;
 143         u32 abort;
 144         char data[0];
 145 };
 146
 147 /*
 148  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 149  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 150  * loaded on this CPU (so we can clear them if the CPU goes down).
 151  */
 152 struct loaded_vmcs {
 153         struct vmcs *vmcs;
 154         int cpu;
 155         int launched;
 156         struct list_head loaded_vmcss_on_cpu_link;
 157 };
 158
 159 struct shared_msr_entry {
 160         unsigned index;
 161         u64 data;
 162         u64 mask;
 163 };
 164
 165 /*
 166  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 167  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 168  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 169  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 170  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 171  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 172  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 173  * underlying hardware which will be used to run L2.
 174  * This structure is packed to ensure that its layout is identical across
 175  * machines (necessary for live migration).
 176  * If there are changes in this struct, VMCS12_REVISION must be changed.
 177  */
 178 typedef u64 natural_width;
 179 struct __packed vmcs12 {
 180         /* According to the Intel spec, a VMCS region must start with the
 181          * following two fields. Then follow implementation-specific data.
 182          */
 183         u32 revision_id;
 184         u32 abort;
 185
 186         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 187         u32 padding[7]; /* room for future expansion */
 188
 189         u64 io_bitmap_a;
 190         u64 io_bitmap_b;
 191         u64 msr_bitmap;
 192         u64 vm_exit_msr_store_addr;
 193         u64 vm_exit_msr_load_addr;
 194         u64 vm_entry_msr_load_addr;
 195         u64 tsc_offset;
 196         u64 virtual_apic_page_addr;
 197         u64 apic_access_addr;
 198         u64 ept_pointer;
 199         u64 guest_physical_address;
 200         u64 vmcs_link_pointer;
 201         u64 guest_ia32_debugctl;
 202         u64 guest_ia32_pat;
 203         u64 guest_ia32_efer;
 204         u64 guest_ia32_perf_global_ctrl;
 205         u64 guest_pdptr0;
 206         u64 guest_pdptr1;
 207         u64 guest_pdptr2;
 208         u64 guest_pdptr3;
 209         u64 guest_bndcfgs;
 210         u64 host_ia32_pat;
 211         u64 host_ia32_efer;
 212         u64 host_ia32_perf_global_ctrl;
 213         u64 padding64[8]; /* room for future expansion */
 214         /*
 215          * To allow migration of L1 (complete with its L2 guests) between
 216          * machines of different natural widths (32 or 64 bit), we cannot have
 217          * unsigned long fields with no explict size. We use u64 (aliased
 218          * natural_width) instead. Luckily, x86 is little-endian.
 219          */
 220         natural_width cr0_guest_host_mask;
 221         natural_width cr4_guest_host_mask;
 222         natural_width cr0_read_shadow;
 223         natural_width cr4_read_shadow;
 224         natural_width cr3_target_value0;
 225         natural_width cr3_target_value1;
 226         natural_width cr3_target_value2;
 227         natural_width cr3_target_value3;
 228         natural_width exit_qualification;
 229         natural_width guest_linear_address;
 230         natural_width guest_cr0;
 231         natural_width guest_cr3;
 232         natural_width guest_cr4;
 233         natural_width guest_es_base;
 234         natural_width guest_cs_base;
 235         natural_width guest_ss_base;
 236         natural_width guest_ds_base;
 237         natural_width guest_fs_base;
 238         natural_width guest_gs_base;
 239         natural_width guest_ldtr_base;
 240         natural_width guest_tr_base;
 241         natural_width guest_gdtr_base;
 242         natural_width guest_idtr_base;
 243         natural_width guest_dr7;
 244         natural_width guest_rsp;
 245         natural_width guest_rip;
 246         natural_width guest_rflags;
 247         natural_width guest_pending_dbg_exceptions;
 248         natural_width guest_sysenter_esp;
 249         natural_width guest_sysenter_eip;
 250         natural_width host_cr0;
 251         natural_width host_cr3;
 252         natural_width host_cr4;
 253         natural_width host_fs_base;
 254         natural_width host_gs_base;
 255         natural_width host_tr_base;
 256         natural_width host_gdtr_base;
 257         natural_width host_idtr_base;
 258         natural_width host_ia32_sysenter_esp;
 259         natural_width host_ia32_sysenter_eip;
 260         natural_width host_rsp;
 261         natural_width host_rip;
 262         natural_width paddingl[8]; /* room for future expansion */
 263         u32 pin_based_vm_exec_control;
 264         u32 cpu_based_vm_exec_control;
 265         u32 exception_bitmap;
 266         u32 page_fault_error_code_mask;
 267         u32 page_fault_error_code_match;
 268         u32 cr3_target_count;
 269         u32 vm_exit_controls;
 270         u32 vm_exit_msr_store_count;
 271         u32 vm_exit_msr_load_count;
 272         u32 vm_entry_controls;
 273         u32 vm_entry_msr_load_count;
 274         u32 vm_entry_intr_info_field;
 275         u32 vm_entry_exception_error_code;
 276         u32 vm_entry_instruction_len;
 277         u32 tpr_threshold;
 278         u32 secondary_vm_exec_control;
 279         u32 vm_instruction_error;
 280         u32 vm_exit_reason;
 281         u32 vm_exit_intr_info;
 282         u32 vm_exit_intr_error_code;
 283         u32 idt_vectoring_info_field;
 284         u32 idt_vectoring_error_code;
 285         u32 vm_exit_instruction_len;
 286         u32 vmx_instruction_info;
 287         u32 guest_es_limit;
 288         u32 guest_cs_limit;
 289         u32 guest_ss_limit;
 290         u32 guest_ds_limit;
 291         u32 guest_fs_limit;
 292         u32 guest_gs_limit;
 293         u32 guest_ldtr_limit;
 294         u32 guest_tr_limit;
 295         u32 guest_gdtr_limit;
 296         u32 guest_idtr_limit;
 297         u32 guest_es_ar_bytes;
 298         u32 guest_cs_ar_bytes;
 299         u32 guest_ss_ar_bytes;
 300         u32 guest_ds_ar_bytes;
 301         u32 guest_fs_ar_bytes;
 302         u32 guest_gs_ar_bytes;
 303         u32 guest_ldtr_ar_bytes;
 304         u32 guest_tr_ar_bytes;
 305         u32 guest_interruptibility_info;
 306         u32 guest_activity_state;
 307         u32 guest_sysenter_cs;
 308         u32 host_ia32_sysenter_cs;
 309         u32 vmx_preemption_timer_value;
 310         u32 padding32[7]; /* room for future expansion */
 311         u16 virtual_processor_id;
 312         u16 guest_es_selector;
 313         u16 guest_cs_selector;
 314         u16 guest_ss_selector;
 315         u16 guest_ds_selector;
 316         u16 guest_fs_selector;
 317         u16 guest_gs_selector;
 318         u16 guest_ldtr_selector;
 319         u16 guest_tr_selector;
 320         u16 host_es_selector;
 321         u16 host_cs_selector;
 322         u16 host_ss_selector;
 323         u16 host_ds_selector;
 324         u16 host_fs_selector;
 325         u16 host_gs_selector;
 326         u16 host_tr_selector;
 327 };
 328
 329 /*
 330  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 331  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 332  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 333  */
 334 #define VMCS12_REVISION 0x11e57ed0
 335
 336 /*
 337  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 338  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 339  * current implementation, 4K are reserved to avoid future complications.
 340  */
 341 #define VMCS12_SIZE 0x1000
 342
 343 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 344 struct vmcs02_list {
 345         struct list_head list;
 346         gpa_t vmptr;
 347         struct loaded_vmcs vmcs02;
 348 };
 349
 350 /*
 351  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 352  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 353  */
 354 struct nested_vmx {
 355         /* Has the level1 guest done vmxon? */
 356         bool vmxon;
 357
 358         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 359         gpa_t current_vmptr;
 360         /* The host-usable pointer to the above */
 361         struct page *current_vmcs12_page;
 362         struct vmcs12 *current_vmcs12;
 363         struct vmcs *current_shadow_vmcs;
 364         /*
 365          * Indicates if the shadow vmcs must be updated with the
 366          * data hold by vmcs12
 367          */
 368         bool sync_shadow_vmcs;
 369
 370         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 371         struct list_head vmcs02_pool;
 372         int vmcs02_num;
 373         u64 vmcs01_tsc_offset;
 374         /* L2 must run next, and mustn't decide to exit to L1. */
 375         bool nested_run_pending;
 376         /*
 377          * Guest pages referred to in vmcs02 with host-physical pointers, so
 378          * we must keep them pinned while L2 runs.
 379          */
 380         struct page *apic_access_page;
 381         u64 msr_ia32_feature_control;
 382
 383         struct hrtimer preemption_timer;
 384         bool preemption_timer_expired;
 385 };
 386
 387 #define POSTED_INTR_ON  0
 388 /* Posted-Interrupt Descriptor */
 389 struct pi_desc {
 390         u32 pir[8];     /* Posted interrupt requested */
 391         u32 control;    /* bit 0 of control is outstanding notification bit */
 392         u32 rsvd[7];
 393 } __aligned(64);
 394
 395 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 396 {
 397         return test_and_set_bit(POSTED_INTR_ON,
 398                         (unsigned long *)&pi_desc->control);
 399 }
 400
 401 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 402 {
 403         return test_and_clear_bit(POSTED_INTR_ON,
 404                         (unsigned long *)&pi_desc->control);
 405 }
 406
 407 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 408 {
 409         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 410 }
 411
 412 struct vcpu_vmx {
 413         struct kvm_vcpu       vcpu;
 414         unsigned long         host_rsp;
 415         u8                    fail;
 416         u8                    cpl;
 417         bool                  nmi_known_unmasked;
 418         u32                   exit_intr_info;
 419         u32                   idt_vectoring_info;
 420         ulong                 rflags;
 421         struct shared_msr_entry *guest_msrs;
 422         int                   nmsrs;
 423         int                   save_nmsrs;
 424         unsigned long         host_idt_base;
 425 #ifdef CONFIG_X86_64
 426         u64                   msr_host_kernel_gs_base;
 427         u64                   msr_guest_kernel_gs_base;
 428 #endif
 429         u32 vm_entry_controls_shadow;
 430         u32 vm_exit_controls_shadow;
 431         /*
 432          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 433          * non-nested (L1) guest, it always points to vmcs01. For a nested
 434          * guest (L2), it points to a different VMCS.
 435          */
 436         struct loaded_vmcs    vmcs01;
 437         struct loaded_vmcs   *loaded_vmcs;
 438         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 439         struct msr_autoload {
 440                 unsigned nr;
 441                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 442                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 443         } msr_autoload;
 444         struct {
 445                 int           loaded;
 446                 u16           fs_sel, gs_sel, ldt_sel;
 447 #ifdef CONFIG_X86_64
 448                 u16           ds_sel, es_sel;
 449 #endif
 450                 int           gs_ldt_reload_needed;
 451                 int           fs_reload_needed;
 452                 u64           msr_host_bndcfgs;
 453         } host_state;
 454         struct {
 455                 int vm86_active;
 456                 ulong save_rflags;
 457                 struct kvm_segment segs[8];
 458         } rmode;
 459         struct {
 460                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 461                 struct kvm_save_segment {
 462                         u16 selector;
 463                         unsigned long base;
 464                         u32 limit;
 465                         u32 ar;
 466                 } seg[8];
 467         } segment_cache;
 468         int vpid;
 469         bool emulation_required;
 470
 471         /* Support for vnmi-less CPUs */
 472         int soft_vnmi_blocked;
 473         ktime_t entry_time;
 474         s64 vnmi_blocked_time;
 475         u32 exit_reason;
 476
 477         bool rdtscp_enabled;
 478
 479         /* Posted interrupt descriptor */
 480         struct pi_desc pi_desc;
 481
 482         /* Support for a guest hypervisor (nested VMX) */
 483         struct nested_vmx nested;
 484 };
 485
 486 enum segment_cache_field {
 487         SEG_FIELD_SEL = 0,
 488         SEG_FIELD_BASE = 1,
 489         SEG_FIELD_LIMIT = 2,
 490         SEG_FIELD_AR = 3,
 491
 492         SEG_FIELD_NR = 4
 493 };
 494
 495 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 496 {
 497         return container_of(vcpu, struct vcpu_vmx, vcpu);
 498 }
 499
 500 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 501 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 502 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 503                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 504
 505
 506 static const unsigned long shadow_read_only_fields[] = {
 507         /*
 508          * We do NOT shadow fields that are modified when L0
 509          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 510          * VMXON...) executed by L1.
 511          * For example, VM_INSTRUCTION_ERROR is read
 512          * by L1 if a vmx instruction fails (part of the error path).
 513          * Note the code assumes this logic. If for some reason
 514          * we start shadowing these fields then we need to
 515          * force a shadow sync when L0 emulates vmx instructions
 516          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 517          * by nested_vmx_failValid)
 518          */
 519         VM_EXIT_REASON,
 520         VM_EXIT_INTR_INFO,
 521         VM_EXIT_INSTRUCTION_LEN,
 522         IDT_VECTORING_INFO_FIELD,
 523         IDT_VECTORING_ERROR_CODE,
 524         VM_EXIT_INTR_ERROR_CODE,
 525         EXIT_QUALIFICATION,
 526         GUEST_LINEAR_ADDRESS,
 527         GUEST_PHYSICAL_ADDRESS
 528 };
 529 static const int max_shadow_read_only_fields =
 530         ARRAY_SIZE(shadow_read_only_fields);
 531
 532 static const unsigned long shadow_read_write_fields[] = {
 533         GUEST_RIP,
 534         GUEST_RSP,
 535         GUEST_CR0,
 536         GUEST_CR3,
 537         GUEST_CR4,
 538         GUEST_INTERRUPTIBILITY_INFO,
 539         GUEST_RFLAGS,
 540         GUEST_CS_SELECTOR,
 541         GUEST_CS_AR_BYTES,
 542         GUEST_CS_LIMIT,
 543         GUEST_CS_BASE,
 544         GUEST_ES_BASE,
 545         GUEST_BNDCFGS,
 546         CR0_GUEST_HOST_MASK,
 547         CR0_READ_SHADOW,
 548         CR4_READ_SHADOW,
 549         TSC_OFFSET,
 550         EXCEPTION_BITMAP,
 551         CPU_BASED_VM_EXEC_CONTROL,
 552         VM_ENTRY_EXCEPTION_ERROR_CODE,
 553         VM_ENTRY_INTR_INFO_FIELD,
 554         VM_ENTRY_INSTRUCTION_LEN,
 555         VM_ENTRY_EXCEPTION_ERROR_CODE,
 556         HOST_FS_BASE,
 557         HOST_GS_BASE,
 558         HOST_FS_SELECTOR,
 559         HOST_GS_SELECTOR
 560 };
 561 static const int max_shadow_read_write_fields =
 562         ARRAY_SIZE(shadow_read_write_fields);
 563
 564 static const unsigned short vmcs_field_to_offset_table[] = {
 565         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 566         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 567         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 568         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 569         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 570         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 571         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 572         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 573         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 574         FIELD(HOST_ES_SELECTOR, host_es_selector),
 575         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 576         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 577         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 578         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 579         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 580         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 581         FIELD64(IO_BITMAP_A, io_bitmap_a),
 582         FIELD64(IO_BITMAP_B, io_bitmap_b),
 583         FIELD64(MSR_BITMAP, msr_bitmap),
 584         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 585         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 586         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 587         FIELD64(TSC_OFFSET, tsc_offset),
 588         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 589         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 590         FIELD64(EPT_POINTER, ept_pointer),
 591         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 592         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 593         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 594         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 595         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 596         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 597         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 598         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 599         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 600         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 601         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 602         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 603         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 604         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 605         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 606         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 607         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 608         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 609         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 610         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 611         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 612         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 613         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 614         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 615         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 616         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 617         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 618         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 619         FIELD(TPR_THRESHOLD, tpr_threshold),
 620         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 621         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 622         FIELD(VM_EXIT_REASON, vm_exit_reason),
 623         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 624         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 625         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 626         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 627         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 628         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 629         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 630         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 631         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 632         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 633         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 634         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 635         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 636         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 637         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 638         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 639         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 640         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 641         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 642         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 643         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 644         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 645         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 646         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 647         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 648         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 649         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 650         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 651         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 652         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 653         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 654         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 655         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 656         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 657         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 658         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 659         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 660         FIELD(EXIT_QUALIFICATION, exit_qualification),
 661         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 662         FIELD(GUEST_CR0, guest_cr0),
 663         FIELD(GUEST_CR3, guest_cr3),
 664         FIELD(GUEST_CR4, guest_cr4),
 665         FIELD(GUEST_ES_BASE, guest_es_base),
 666         FIELD(GUEST_CS_BASE, guest_cs_base),
 667         FIELD(GUEST_SS_BASE, guest_ss_base),
 668         FIELD(GUEST_DS_BASE, guest_ds_base),
 669         FIELD(GUEST_FS_BASE, guest_fs_base),
 670         FIELD(GUEST_GS_BASE, guest_gs_base),
 671         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 672         FIELD(GUEST_TR_BASE, guest_tr_base),
 673         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 674         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 675         FIELD(GUEST_DR7, guest_dr7),
 676         FIELD(GUEST_RSP, guest_rsp),
 677         FIELD(GUEST_RIP, guest_rip),
 678         FIELD(GUEST_RFLAGS, guest_rflags),
 679         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 680         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 681         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 682         FIELD(HOST_CR0, host_cr0),
 683         FIELD(HOST_CR3, host_cr3),
 684         FIELD(HOST_CR4, host_cr4),
 685         FIELD(HOST_FS_BASE, host_fs_base),
 686         FIELD(HOST_GS_BASE, host_gs_base),
 687         FIELD(HOST_TR_BASE, host_tr_base),
 688         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 689         FIELD(HOST_IDTR_BASE, host_idtr_base),
 690         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 691         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 692         FIELD(HOST_RSP, host_rsp),
 693         FIELD(HOST_RIP, host_rip),
 694 };
 695 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 696
 697 static inline short vmcs_field_to_offset(unsigned long field)
 698 {
 699         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 700                 return -1;
 701         return vmcs_field_to_offset_table[field];
 702 }
 703
 704 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 705 {
 706         return to_vmx(vcpu)->nested.current_vmcs12;
 707 }
 708
 709 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 710 {
 711         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 712         if (is_error_page(page))
 713                 return NULL;
 714
 715         return page;
 716 }
 717
 718 static void nested_release_page(struct page *page)
 719 {
 720         kvm_release_page_dirty(page);
 721 }
 722
 723 static void nested_release_page_clean(struct page *page)
 724 {
 725         kvm_release_page_clean(page);
 726 }
 727
 728 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 729 static u64 construct_eptp(unsigned long root_hpa);
 730 static void kvm_cpu_vmxon(u64 addr);
 731 static void kvm_cpu_vmxoff(void);
 732 static bool vmx_mpx_supported(void);
 733 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 734 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 735                             struct kvm_segment *var, int seg);
 736 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 737                             struct kvm_segment *var, int seg);
 738 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 739 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 740 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 741 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 742 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 743 static bool vmx_mpx_supported(void);
 744
 745 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 746 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 747 /*
 748  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 749  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 750  */
 751 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 752 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 753
 754 static unsigned long *vmx_io_bitmap_a;
 755 static unsigned long *vmx_io_bitmap_b;
 756 static unsigned long *vmx_msr_bitmap_legacy;
 757 static unsigned long *vmx_msr_bitmap_longmode;
 758 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 759 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 760 static unsigned long *vmx_vmread_bitmap;
 761 static unsigned long *vmx_vmwrite_bitmap;
 762
 763 static bool cpu_has_load_ia32_efer;
 764 static bool cpu_has_load_perf_global_ctrl;
 765
 766 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 767 static DEFINE_SPINLOCK(vmx_vpid_lock);
 768
 769 static struct vmcs_config {
 770         int size;
 771         int order;
 772         u32 revision_id;
 773         u32 pin_based_exec_ctrl;
 774         u32 cpu_based_exec_ctrl;
 775         u32 cpu_based_2nd_exec_ctrl;
 776         u32 vmexit_ctrl;
 777         u32 vmentry_ctrl;
 778 } vmcs_config;
 779
 780 static struct vmx_capability {
 781         u32 ept;
 782         u32 vpid;
 783 } vmx_capability;
 784
 785 #define VMX_SEGMENT_FIELD(seg)                                  \
 786         [VCPU_SREG_##seg] = {                                   \
 787                 .selector = GUEST_##seg##_SELECTOR,             \
 788                 .base = GUEST_##seg##_BASE,                     \
 789                 .limit = GUEST_##seg##_LIMIT,                   \
 790                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 791         }
 792
 793 static const struct kvm_vmx_segment_field {
 794         unsigned selector;
 795         unsigned base;
 796         unsigned limit;
 797         unsigned ar_bytes;
 798 } kvm_vmx_segment_fields[] = {
 799         VMX_SEGMENT_FIELD(CS),
 800         VMX_SEGMENT_FIELD(DS),
 801         VMX_SEGMENT_FIELD(ES),
 802         VMX_SEGMENT_FIELD(FS),
 803         VMX_SEGMENT_FIELD(GS),
 804         VMX_SEGMENT_FIELD(SS),
 805         VMX_SEGMENT_FIELD(TR),
 806         VMX_SEGMENT_FIELD(LDTR),
 807 };
 808
 809 static u64 host_efer;
 810
 811 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 812
 813 /*
 814  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 815  * away by decrementing the array size.
 816  */
 817 static const u32 vmx_msr_index[] = {
 818 #ifdef CONFIG_X86_64
 819         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 820 #endif
 821         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 822 };
 823 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 824
 825 static inline bool is_page_fault(u32 intr_info)
 826 {
 827         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 828                              INTR_INFO_VALID_MASK)) ==
 829                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 830 }
 831
 832 static inline bool is_no_device(u32 intr_info)
 833 {
 834         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 835                              INTR_INFO_VALID_MASK)) ==
 836                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 837 }
 838
 839 static inline bool is_invalid_opcode(u32 intr_info)
 840 {
 841         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 842                              INTR_INFO_VALID_MASK)) ==
 843                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 844 }
 845
 846 static inline bool is_external_interrupt(u32 intr_info)
 847 {
 848         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 849                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 850 }
 851
 852 static inline bool is_machine_check(u32 intr_info)
 853 {
 854         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 855                              INTR_INFO_VALID_MASK)) ==
 856                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 857 }
 858
 859 static inline bool cpu_has_vmx_msr_bitmap(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 862 }
 863
 864 static inline bool cpu_has_vmx_tpr_shadow(void)
 865 {
 866         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 867 }
 868
 869 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 870 {
 871         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 872 }
 873
 874 static inline bool cpu_has_secondary_exec_ctrls(void)
 875 {
 876         return vmcs_config.cpu_based_exec_ctrl &
 877                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 878 }
 879
 880 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 881 {
 882         return vmcs_config.cpu_based_2nd_exec_ctrl &
 883                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 884 }
 885
 886 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 887 {
 888         return vmcs_config.cpu_based_2nd_exec_ctrl &
 889                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 890 }
 891
 892 static inline bool cpu_has_vmx_apic_register_virt(void)
 893 {
 894         return vmcs_config.cpu_based_2nd_exec_ctrl &
 895                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 896 }
 897
 898 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 899 {
 900         return vmcs_config.cpu_based_2nd_exec_ctrl &
 901                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 902 }
 903
 904 static inline bool cpu_has_vmx_posted_intr(void)
 905 {
 906         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 907 }
 908
 909 static inline bool cpu_has_vmx_apicv(void)
 910 {
 911         return cpu_has_vmx_apic_register_virt() &&
 912                 cpu_has_vmx_virtual_intr_delivery() &&
 913                 cpu_has_vmx_posted_intr();
 914 }
 915
 916 static inline bool cpu_has_vmx_flexpriority(void)
 917 {
 918         return cpu_has_vmx_tpr_shadow() &&
 919                 cpu_has_vmx_virtualize_apic_accesses();
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_execute_only(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 928 {
 929         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_eptp_writeback(void)
 933 {
 934         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_2m_page(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_ept_1g_page(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_ept_4levels(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_ept_ad_bits(void)
 953 {
 954         return vmx_capability.ept & VMX_EPT_AD_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invept_context(void)
 958 {
 959         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_invept_global(void)
 963 {
 964         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 965 }
 966
 967 static inline bool cpu_has_vmx_invvpid_single(void)
 968 {
 969         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 970 }
 971
 972 static inline bool cpu_has_vmx_invvpid_global(void)
 973 {
 974         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 975 }
 976
 977 static inline bool cpu_has_vmx_ept(void)
 978 {
 979         return vmcs_config.cpu_based_2nd_exec_ctrl &
 980                 SECONDARY_EXEC_ENABLE_EPT;
 981 }
 982
 983 static inline bool cpu_has_vmx_unrestricted_guest(void)
 984 {
 985         return vmcs_config.cpu_based_2nd_exec_ctrl &
 986                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 987 }
 988
 989 static inline bool cpu_has_vmx_ple(void)
 990 {
 991         return vmcs_config.cpu_based_2nd_exec_ctrl &
 992                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 993 }
 994
 995 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 996 {
 997         return flexpriority_enabled && irqchip_in_kernel(kvm);
 998 }
 999
1000 static inline bool cpu_has_vmx_vpid(void)
1001 {
1002         return vmcs_config.cpu_based_2nd_exec_ctrl &
1003                 SECONDARY_EXEC_ENABLE_VPID;
1004 }
1005
1006 static inline bool cpu_has_vmx_rdtscp(void)
1007 {
1008         return vmcs_config.cpu_based_2nd_exec_ctrl &
1009                 SECONDARY_EXEC_RDTSCP;
1010 }
1011
1012 static inline bool cpu_has_vmx_invpcid(void)
1013 {
1014         return vmcs_config.cpu_based_2nd_exec_ctrl &
1015                 SECONDARY_EXEC_ENABLE_INVPCID;
1016 }
1017
1018 static inline bool cpu_has_virtual_nmis(void)
1019 {
1020         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1021 }
1022
1023 static inline bool cpu_has_vmx_wbinvd_exit(void)
1024 {
1025         return vmcs_config.cpu_based_2nd_exec_ctrl &
1026                 SECONDARY_EXEC_WBINVD_EXITING;
1027 }
1028
1029 static inline bool cpu_has_vmx_shadow_vmcs(void)
1030 {
1031         u64 vmx_msr;
1032         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033         /* check if the cpu supports writing r/o exit information fields */
1034         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1035                 return false;
1036
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_SHADOW_VMCS;
1039 }
1040
1041 static inline bool report_flexpriority(void)
1042 {
1043         return flexpriority_enabled;
1044 }
1045
1046 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1047 {
1048         return vmcs12->cpu_based_vm_exec_control & bit;
1049 }
1050
1051 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1052 {
1053         return (vmcs12->cpu_based_vm_exec_control &
1054                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055                 (vmcs12->secondary_vm_exec_control & bit);
1056 }
1057
1058 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1059 {
1060         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1061 }
1062
1063 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1064 {
1065         return vmcs12->pin_based_vm_exec_control &
1066                 PIN_BASED_VMX_PREEMPTION_TIMER;
1067 }
1068
1069 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1070 {
1071         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1072 }
1073
1074 static inline bool is_exception(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1081                               u32 exit_intr_info,
1082                               unsigned long exit_qualification);
1083 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084                         struct vmcs12 *vmcs12,
1085                         u32 reason, unsigned long qualification);
1086
1087 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1088 {
1089         int i;
1090
1091         for (i = 0; i < vmx->nmsrs; ++i)
1092                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1093                         return i;
1094         return -1;
1095 }
1096
1097 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1098 {
1099     struct {
1100         u64 vpid : 16;
1101         u64 rsvd : 48;
1102         u64 gva;
1103     } operand = { vpid, 0, gva };
1104
1105     asm volatile (__ex(ASM_VMX_INVVPID)
1106                   /* CF==1 or ZF==1 --> rc = -1 */
1107                   "; ja 1f ; ud2 ; 1:"
1108                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1109 }
1110
1111 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1112 {
1113         struct {
1114                 u64 eptp, gpa;
1115         } operand = {eptp, gpa};
1116
1117         asm volatile (__ex(ASM_VMX_INVEPT)
1118                         /* CF==1 or ZF==1 --> rc = -1 */
1119                         "; ja 1f ; ud2 ; 1:\n"
1120                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1121 }
1122
1123 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1124 {
1125         int i;
1126
1127         i = __find_msr_index(vmx, msr);
1128         if (i >= 0)
1129                 return &vmx->guest_msrs[i];
1130         return NULL;
1131 }
1132
1133 static void vmcs_clear(struct vmcs *vmcs)
1134 {
1135         u64 phys_addr = __pa(vmcs);
1136         u8 error;
1137
1138         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1139                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1140                       : "cc", "memory");
1141         if (error)
1142                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1143                        vmcs, phys_addr);
1144 }
1145
1146 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1147 {
1148         vmcs_clear(loaded_vmcs->vmcs);
1149         loaded_vmcs->cpu = -1;
1150         loaded_vmcs->launched = 0;
1151 }
1152
1153 static void vmcs_load(struct vmcs *vmcs)
1154 {
1155         u64 phys_addr = __pa(vmcs);
1156         u8 error;
1157
1158         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1159                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1160                         : "cc", "memory");
1161         if (error)
1162                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1163                        vmcs, phys_addr);
1164 }
1165
1166 #ifdef CONFIG_KEXEC
1167 /*
1168  * This bitmap is used to indicate whether the vmclear
1169  * operation is enabled on all cpus. All disabled by
1170  * default.
1171  */
1172 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1173
1174 static inline void crash_enable_local_vmclear(int cpu)
1175 {
1176         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177 }
1178
1179 static inline void crash_disable_local_vmclear(int cpu)
1180 {
1181         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182 }
1183
1184 static inline int crash_local_vmclear_enabled(int cpu)
1185 {
1186         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187 }
1188
1189 static void crash_vmclear_local_loaded_vmcss(void)
1190 {
1191         int cpu = raw_smp_processor_id();
1192         struct loaded_vmcs *v;
1193
1194         if (!crash_local_vmclear_enabled(cpu))
1195                 return;
1196
1197         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198                             loaded_vmcss_on_cpu_link)
1199                 vmcs_clear(v->vmcs);
1200 }
1201 #else
1202 static inline void crash_enable_local_vmclear(int cpu) { }
1203 static inline void crash_disable_local_vmclear(int cpu) { }
1204 #endif /* CONFIG_KEXEC */
1205
1206 static void __loaded_vmcs_clear(void *arg)
1207 {
1208         struct loaded_vmcs *loaded_vmcs = arg;
1209         int cpu = raw_smp_processor_id();
1210
1211         if (loaded_vmcs->cpu != cpu)
1212                 return; /* vcpu migration can race with cpu offline */
1213         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1214                 per_cpu(current_vmcs, cpu) = NULL;
1215         crash_disable_local_vmclear(cpu);
1216         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1217
1218         /*
1219          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220          * is before setting loaded_vmcs->vcpu to -1 which is done in
1221          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222          * then adds the vmcs into percpu list before it is deleted.
1223          */
1224         smp_wmb();
1225
1226         loaded_vmcs_init(loaded_vmcs);
1227         crash_enable_local_vmclear(cpu);
1228 }
1229
1230 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1231 {
1232         int cpu = loaded_vmcs->cpu;
1233
1234         if (cpu != -1)
1235                 smp_call_function_single(cpu,
1236                          __loaded_vmcs_clear, loaded_vmcs, 1);
1237 }
1238
1239 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1240 {
1241         if (vmx->vpid == 0)
1242                 return;
1243
1244         if (cpu_has_vmx_invvpid_single())
1245                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1246 }
1247
1248 static inline void vpid_sync_vcpu_global(void)
1249 {
1250         if (cpu_has_vmx_invvpid_global())
1251                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1252 }
1253
1254 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1255 {
1256         if (cpu_has_vmx_invvpid_single())
1257                 vpid_sync_vcpu_single(vmx);
1258         else
1259                 vpid_sync_vcpu_global();
1260 }
1261
1262 static inline void ept_sync_global(void)
1263 {
1264         if (cpu_has_vmx_invept_global())
1265                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1266 }
1267
1268 static inline void ept_sync_context(u64 eptp)
1269 {
1270         if (enable_ept) {
1271                 if (cpu_has_vmx_invept_context())
1272                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1273                 else
1274                         ept_sync_global();
1275         }
1276 }
1277
1278 static __always_inline unsigned long vmcs_readl(unsigned long field)
1279 {
1280         unsigned long value;
1281
1282         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283                       : "=a"(value) : "d"(field) : "cc");
1284         return value;
1285 }
1286
1287 static __always_inline u16 vmcs_read16(unsigned long field)
1288 {
1289         return vmcs_readl(field);
1290 }
1291
1292 static __always_inline u32 vmcs_read32(unsigned long field)
1293 {
1294         return vmcs_readl(field);
1295 }
1296
1297 static __always_inline u64 vmcs_read64(unsigned long field)
1298 {
1299 #ifdef CONFIG_X86_64
1300         return vmcs_readl(field);
1301 #else
1302         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1303 #endif
1304 }
1305
1306 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1307 {
1308         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1310         dump_stack();
1311 }
1312
1313 static void vmcs_writel(unsigned long field, unsigned long value)
1314 {
1315         u8 error;
1316
1317         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1318                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1319         if (unlikely(error))
1320                 vmwrite_error(field, value);
1321 }
1322
1323 static void vmcs_write16(unsigned long field, u16 value)
1324 {
1325         vmcs_writel(field, value);
1326 }
1327
1328 static void vmcs_write32(unsigned long field, u32 value)
1329 {
1330         vmcs_writel(field, value);
1331 }
1332
1333 static void vmcs_write64(unsigned long field, u64 value)
1334 {
1335         vmcs_writel(field, value);
1336 #ifndef CONFIG_X86_64
1337         asm volatile ("");
1338         vmcs_writel(field+1, value >> 32);
1339 #endif
1340 }
1341
1342 static void vmcs_clear_bits(unsigned long field, u32 mask)
1343 {
1344         vmcs_writel(field, vmcs_readl(field) & ~mask);
1345 }
1346
1347 static void vmcs_set_bits(unsigned long field, u32 mask)
1348 {
1349         vmcs_writel(field, vmcs_readl(field) | mask);
1350 }
1351
1352 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1353 {
1354         vmcs_write32(VM_ENTRY_CONTROLS, val);
1355         vmx->vm_entry_controls_shadow = val;
1356 }
1357
1358 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1359 {
1360         if (vmx->vm_entry_controls_shadow != val)
1361                 vm_entry_controls_init(vmx, val);
1362 }
1363
1364 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1365 {
1366         return vmx->vm_entry_controls_shadow;
1367 }
1368
1369
1370 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1371 {
1372         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1373 }
1374
1375 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1376 {
1377         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1378 }
1379
1380 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1381 {
1382         vmcs_write32(VM_EXIT_CONTROLS, val);
1383         vmx->vm_exit_controls_shadow = val;
1384 }
1385
1386 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1387 {
1388         if (vmx->vm_exit_controls_shadow != val)
1389                 vm_exit_controls_init(vmx, val);
1390 }
1391
1392 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1393 {
1394         return vmx->vm_exit_controls_shadow;
1395 }
1396
1397
1398 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1399 {
1400         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1401 }
1402
1403 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1404 {
1405         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1406 }
1407
1408 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1409 {
1410         vmx->segment_cache.bitmask = 0;
1411 }
1412
1413 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1414                                        unsigned field)
1415 {
1416         bool ret;
1417         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1418
1419         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421                 vmx->segment_cache.bitmask = 0;
1422         }
1423         ret = vmx->segment_cache.bitmask & mask;
1424         vmx->segment_cache.bitmask |= mask;
1425         return ret;
1426 }
1427
1428 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1429 {
1430         u16 *p = &vmx->segment_cache.seg[seg].selector;
1431
1432         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1434         return *p;
1435 }
1436
1437 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1438 {
1439         ulong *p = &vmx->segment_cache.seg[seg].base;
1440
1441         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1443         return *p;
1444 }
1445
1446 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1447 {
1448         u32 *p = &vmx->segment_cache.seg[seg].limit;
1449
1450         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1452         return *p;
1453 }
1454
1455 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1456 {
1457         u32 *p = &vmx->segment_cache.seg[seg].ar;
1458
1459         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1461         return *p;
1462 }
1463
1464 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1465 {
1466         u32 eb;
1467
1468         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470         if ((vcpu->guest_debug &
1471              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473                 eb |= 1u << BP_VECTOR;
1474         if (to_vmx(vcpu)->rmode.vm86_active)
1475                 eb = ~0;
1476         if (enable_ept)
1477                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1478         if (vcpu->fpu_active)
1479                 eb &= ~(1u << NM_VECTOR);
1480
1481         /* When we are running a nested L2 guest and L1 specified for it a
1482          * certain exception bitmap, we must trap the same exceptions and pass
1483          * them to L1. When running L2, we will only handle the exceptions
1484          * specified above if L1 did not want them.
1485          */
1486         if (is_guest_mode(vcpu))
1487                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1488
1489         vmcs_write32(EXCEPTION_BITMAP, eb);
1490 }
1491
1492 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493                 unsigned long entry, unsigned long exit)
1494 {
1495         vm_entry_controls_clearbit(vmx, entry);
1496         vm_exit_controls_clearbit(vmx, exit);
1497 }
1498
1499 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1500 {
1501         unsigned i;
1502         struct msr_autoload *m = &vmx->msr_autoload;
1503
1504         switch (msr) {
1505         case MSR_EFER:
1506                 if (cpu_has_load_ia32_efer) {
1507                         clear_atomic_switch_msr_special(vmx,
1508                                         VM_ENTRY_LOAD_IA32_EFER,
1509                                         VM_EXIT_LOAD_IA32_EFER);
1510                         return;
1511                 }
1512                 break;
1513         case MSR_CORE_PERF_GLOBAL_CTRL:
1514                 if (cpu_has_load_perf_global_ctrl) {
1515                         clear_atomic_switch_msr_special(vmx,
1516                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1518                         return;
1519                 }
1520                 break;
1521         }
1522
1523         for (i = 0; i < m->nr; ++i)
1524                 if (m->guest[i].index == msr)
1525                         break;
1526
1527         if (i == m->nr)
1528                 return;
1529         --m->nr;
1530         m->guest[i] = m->guest[m->nr];
1531         m->host[i] = m->host[m->nr];
1532         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1534 }
1535
1536 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537                 unsigned long entry, unsigned long exit,
1538                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539                 u64 guest_val, u64 host_val)
1540 {
1541         vmcs_write64(guest_val_vmcs, guest_val);
1542         vmcs_write64(host_val_vmcs, host_val);
1543         vm_entry_controls_setbit(vmx, entry);
1544         vm_exit_controls_setbit(vmx, exit);
1545 }
1546
1547 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548                                   u64 guest_val, u64 host_val)
1549 {
1550         unsigned i;
1551         struct msr_autoload *m = &vmx->msr_autoload;
1552
1553         switch (msr) {
1554         case MSR_EFER:
1555                 if (cpu_has_load_ia32_efer) {
1556                         add_atomic_switch_msr_special(vmx,
1557                                         VM_ENTRY_LOAD_IA32_EFER,
1558                                         VM_EXIT_LOAD_IA32_EFER,
1559                                         GUEST_IA32_EFER,
1560                                         HOST_IA32_EFER,
1561                                         guest_val, host_val);
1562                         return;
1563                 }
1564                 break;
1565         case MSR_CORE_PERF_GLOBAL_CTRL:
1566                 if (cpu_has_load_perf_global_ctrl) {
1567                         add_atomic_switch_msr_special(vmx,
1568                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1571                                         HOST_IA32_PERF_GLOBAL_CTRL,
1572                                         guest_val, host_val);
1573                         return;
1574                 }
1575                 break;
1576         }
1577
1578         for (i = 0; i < m->nr; ++i)
1579                 if (m->guest[i].index == msr)
1580                         break;
1581
1582         if (i == NR_AUTOLOAD_MSRS) {
1583                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1584                                 "Can't add msr %x\n", msr);
1585                 return;
1586         } else if (i == m->nr) {
1587                 ++m->nr;
1588                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1590         }
1591
1592         m->guest[i].index = msr;
1593         m->guest[i].value = guest_val;
1594         m->host[i].index = msr;
1595         m->host[i].value = host_val;
1596 }
1597
1598 static void reload_tss(void)
1599 {
1600         /*
1601          * VT restores TR but not its size.  Useless.
1602          */
1603         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1604         struct desc_struct *descs;
1605
1606         descs = (void *)gdt->address;
1607         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1608         load_TR_desc();
1609 }
1610
1611 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1612 {
1613         u64 guest_efer;
1614         u64 ignore_bits;
1615
1616         guest_efer = vmx->vcpu.arch.efer;
1617
1618         /*
1619          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1620          * outside long mode
1621          */
1622         ignore_bits = EFER_NX | EFER_SCE;
1623 #ifdef CONFIG_X86_64
1624         ignore_bits |= EFER_LMA | EFER_LME;
1625         /* SCE is meaningful only in long mode on Intel */
1626         if (guest_efer & EFER_LMA)
1627                 ignore_bits &= ~(u64)EFER_SCE;
1628 #endif
1629         guest_efer &= ~ignore_bits;
1630         guest_efer |= host_efer & ignore_bits;
1631         vmx->guest_msrs[efer_offset].data = guest_efer;
1632         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1633
1634         clear_atomic_switch_msr(vmx, MSR_EFER);
1635         /* On ept, can't emulate nx, and must switch nx atomically */
1636         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637                 guest_efer = vmx->vcpu.arch.efer;
1638                 if (!(guest_efer & EFER_LMA))
1639                         guest_efer &= ~EFER_LME;
1640                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1641                 return false;
1642         }
1643
1644         return true;
1645 }
1646
1647 static unsigned long segment_base(u16 selector)
1648 {
1649         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1650         struct desc_struct *d;
1651         unsigned long table_base;
1652         unsigned long v;
1653
1654         if (!(selector & ~3))
1655                 return 0;
1656
1657         table_base = gdt->address;
1658
1659         if (selector & 4) {           /* from ldt */
1660                 u16 ldt_selector = kvm_read_ldt();
1661
1662                 if (!(ldt_selector & ~3))
1663                         return 0;
1664
1665                 table_base = segment_base(ldt_selector);
1666         }
1667         d = (struct desc_struct *)(table_base + (selector & ~7));
1668         v = get_desc_base(d);
1669 #ifdef CONFIG_X86_64
1670        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1672 #endif
1673         return v;
1674 }
1675
1676 static inline unsigned long kvm_read_tr_base(void)
1677 {
1678         u16 tr;
1679         asm("str %0" : "=g"(tr));
1680         return segment_base(tr);
1681 }
1682
1683 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1684 {
1685         struct vcpu_vmx *vmx = to_vmx(vcpu);
1686         int i;
1687
1688         if (vmx->host_state.loaded)
1689                 return;
1690
1691         vmx->host_state.loaded = 1;
1692         /*
1693          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1694          * allow segment selectors with cpl > 0 or ti == 1.
1695          */
1696         vmx->host_state.ldt_sel = kvm_read_ldt();
1697         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1698         savesegment(fs, vmx->host_state.fs_sel);
1699         if (!(vmx->host_state.fs_sel & 7)) {
1700                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1701                 vmx->host_state.fs_reload_needed = 0;
1702         } else {
1703                 vmcs_write16(HOST_FS_SELECTOR, 0);
1704                 vmx->host_state.fs_reload_needed = 1;
1705         }
1706         savesegment(gs, vmx->host_state.gs_sel);
1707         if (!(vmx->host_state.gs_sel & 7))
1708                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1709         else {
1710                 vmcs_write16(HOST_GS_SELECTOR, 0);
1711                 vmx->host_state.gs_ldt_reload_needed = 1;
1712         }
1713
1714 #ifdef CONFIG_X86_64
1715         savesegment(ds, vmx->host_state.ds_sel);
1716         savesegment(es, vmx->host_state.es_sel);
1717 #endif
1718
1719 #ifdef CONFIG_X86_64
1720         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1722 #else
1723         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1725 #endif
1726
1727 #ifdef CONFIG_X86_64
1728         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729         if (is_long_mode(&vmx->vcpu))
1730                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1731 #endif
1732         if (boot_cpu_has(X86_FEATURE_MPX))
1733                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1734         for (i = 0; i < vmx->save_nmsrs; ++i)
1735                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1736                                    vmx->guest_msrs[i].data,
1737                                    vmx->guest_msrs[i].mask);
1738 }
1739
1740 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1741 {
1742         if (!vmx->host_state.loaded)
1743                 return;
1744
1745         ++vmx->vcpu.stat.host_state_reload;
1746         vmx->host_state.loaded = 0;
1747 #ifdef CONFIG_X86_64
1748         if (is_long_mode(&vmx->vcpu))
1749                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1750 #endif
1751         if (vmx->host_state.gs_ldt_reload_needed) {
1752                 kvm_load_ldt(vmx->host_state.ldt_sel);
1753 #ifdef CONFIG_X86_64
1754                 load_gs_index(vmx->host_state.gs_sel);
1755 #else
1756                 loadsegment(gs, vmx->host_state.gs_sel);
1757 #endif
1758         }
1759         if (vmx->host_state.fs_reload_needed)
1760                 loadsegment(fs, vmx->host_state.fs_sel);
1761 #ifdef CONFIG_X86_64
1762         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763                 loadsegment(ds, vmx->host_state.ds_sel);
1764                 loadsegment(es, vmx->host_state.es_sel);
1765         }
1766 #endif
1767         reload_tss();
1768 #ifdef CONFIG_X86_64
1769         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1770 #endif
1771         if (vmx->host_state.msr_host_bndcfgs)
1772                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1773         /*
1774          * If the FPU is not active (through the host task or
1775          * the guest vcpu), then restore the cr0.TS bit.
1776          */
1777         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1778                 stts();
1779         load_gdt(&__get_cpu_var(host_gdt));
1780 }
1781
1782 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1783 {
1784         preempt_disable();
1785         __vmx_load_host_state(vmx);
1786         preempt_enable();
1787 }
1788
1789 /*
1790  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791  * vcpu mutex is already taken.
1792  */
1793 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1794 {
1795         struct vcpu_vmx *vmx = to_vmx(vcpu);
1796         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1797
1798         if (!vmm_exclusive)
1799                 kvm_cpu_vmxon(phys_addr);
1800         else if (vmx->loaded_vmcs->cpu != cpu)
1801                 loaded_vmcs_clear(vmx->loaded_vmcs);
1802
1803         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805                 vmcs_load(vmx->loaded_vmcs->vmcs);
1806         }
1807
1808         if (vmx->loaded_vmcs->cpu != cpu) {
1809                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1810                 unsigned long sysenter_esp;
1811
1812                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1813                 local_irq_disable();
1814                 crash_disable_local_vmclear(cpu);
1815
1816                 /*
1817                  * Read loaded_vmcs->cpu should be before fetching
1818                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819                  * See the comments in __loaded_vmcs_clear().
1820                  */
1821                 smp_rmb();
1822
1823                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1825                 crash_enable_local_vmclear(cpu);
1826                 local_irq_enable();
1827
1828                 /*
1829                  * Linux uses per-cpu TSS and GDT, so set these when switching
1830                  * processors.
1831                  */
1832                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1833                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1834
1835                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1837                 vmx->loaded_vmcs->cpu = cpu;
1838         }
1839 }
1840
1841 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1842 {
1843         __vmx_load_host_state(to_vmx(vcpu));
1844         if (!vmm_exclusive) {
1845                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1846                 vcpu->cpu = -1;
1847                 kvm_cpu_vmxoff();
1848         }
1849 }
1850
1851 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1852 {
1853         ulong cr0;
1854
1855         if (vcpu->fpu_active)
1856                 return;
1857         vcpu->fpu_active = 1;
1858         cr0 = vmcs_readl(GUEST_CR0);
1859         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861         vmcs_writel(GUEST_CR0, cr0);
1862         update_exception_bitmap(vcpu);
1863         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1864         if (is_guest_mode(vcpu))
1865                 vcpu->arch.cr0_guest_owned_bits &=
1866                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1867         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1868 }
1869
1870 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1871
1872 /*
1873  * Return the cr0 value that a nested guest would read. This is a combination
1874  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875  * its hypervisor (cr0_read_shadow).
1876  */
1877 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1878 {
1879         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1881 }
1882 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1883 {
1884         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1886 }
1887
1888 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1889 {
1890         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891          * set this *before* calling this function.
1892          */
1893         vmx_decache_cr0_guest_bits(vcpu);
1894         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1895         update_exception_bitmap(vcpu);
1896         vcpu->arch.cr0_guest_owned_bits = 0;
1897         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1898         if (is_guest_mode(vcpu)) {
1899                 /*
1900                  * L1's specified read shadow might not contain the TS bit,
1901                  * so now that we turned on shadowing of this bit, we need to
1902                  * set this bit of the shadow. Like in nested_vmx_run we need
1903                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904                  * up-to-date here because we just decached cr0.TS (and we'll
1905                  * only update vmcs12->guest_cr0 on nested exit).
1906                  */
1907                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909                         (vcpu->arch.cr0 & X86_CR0_TS);
1910                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1911         } else
1912                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1913 }
1914
1915 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1916 {
1917         unsigned long rflags, save_rflags;
1918
1919         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921                 rflags = vmcs_readl(GUEST_RFLAGS);
1922                 if (to_vmx(vcpu)->rmode.vm86_active) {
1923                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1926                 }
1927                 to_vmx(vcpu)->rflags = rflags;
1928         }
1929         return to_vmx(vcpu)->rflags;
1930 }
1931
1932 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1933 {
1934         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935         to_vmx(vcpu)->rflags = rflags;
1936         if (to_vmx(vcpu)->rmode.vm86_active) {
1937                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1938                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1939         }
1940         vmcs_writel(GUEST_RFLAGS, rflags);
1941 }
1942
1943 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1944 {
1945         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1946         int ret = 0;
1947
1948         if (interruptibility & GUEST_INTR_STATE_STI)
1949                 ret |= KVM_X86_SHADOW_INT_STI;
1950         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1951                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1952
1953         return ret & mask;
1954 }
1955
1956 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1957 {
1958         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959         u32 interruptibility = interruptibility_old;
1960
1961         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1962
1963         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1964                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1965         else if (mask & KVM_X86_SHADOW_INT_STI)
1966                 interruptibility |= GUEST_INTR_STATE_STI;
1967
1968         if ((interruptibility != interruptibility_old))
1969                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1970 }
1971
1972 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1973 {
1974         unsigned long rip;
1975
1976         rip = kvm_rip_read(vcpu);
1977         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1978         kvm_rip_write(vcpu, rip);
1979
1980         /* skipping an emulated instruction also counts */
1981         vmx_set_interrupt_shadow(vcpu, 0);
1982 }
1983
1984 /*
1985  * KVM wants to inject page-faults which it got to the guest. This function
1986  * checks whether in a nested guest, we need to inject them to L1 or L2.
1987  */
1988 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
1989 {
1990         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1991
1992         if (!(vmcs12->exception_bitmap & (1u << nr)))
1993                 return 0;
1994
1995         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996                           vmcs_read32(VM_EXIT_INTR_INFO),
1997                           vmcs_readl(EXIT_QUALIFICATION));
1998         return 1;
1999 }
2000
2001 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2002                                 bool has_error_code, u32 error_code,
2003                                 bool reinject)
2004 {
2005         struct vcpu_vmx *vmx = to_vmx(vcpu);
2006         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2007
2008         if (!reinject && is_guest_mode(vcpu) &&
2009             nested_vmx_check_exception(vcpu, nr))
2010                 return;
2011
2012         if (has_error_code) {
2013                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2014                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2015         }
2016
2017         if (vmx->rmode.vm86_active) {
2018                 int inc_eip = 0;
2019                 if (kvm_exception_is_soft(nr))
2020                         inc_eip = vcpu->arch.event_exit_inst_len;
2021                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2022                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2023                 return;
2024         }
2025
2026         if (kvm_exception_is_soft(nr)) {
2027                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028                              vmx->vcpu.arch.event_exit_inst_len);
2029                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2030         } else
2031                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2032
2033         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2034 }
2035
2036 static bool vmx_rdtscp_supported(void)
2037 {
2038         return cpu_has_vmx_rdtscp();
2039 }
2040
2041 static bool vmx_invpcid_supported(void)
2042 {
2043         return cpu_has_vmx_invpcid() && enable_ept;
2044 }
2045
2046 /*
2047  * Swap MSR entry in host/guest MSR entry array.
2048  */
2049 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2050 {
2051         struct shared_msr_entry tmp;
2052
2053         tmp = vmx->guest_msrs[to];
2054         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055         vmx->guest_msrs[from] = tmp;
2056 }
2057
2058 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2059 {
2060         unsigned long *msr_bitmap;
2061
2062         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063                 if (is_long_mode(vcpu))
2064                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2065                 else
2066                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2067         } else {
2068                 if (is_long_mode(vcpu))
2069                         msr_bitmap = vmx_msr_bitmap_longmode;
2070                 else
2071                         msr_bitmap = vmx_msr_bitmap_legacy;
2072         }
2073
2074         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2075 }
2076
2077 /*
2078  * Set up the vmcs to automatically save and restore system
2079  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2080  * mode, as fiddling with msrs is very expensive.
2081  */
2082 static void setup_msrs(struct vcpu_vmx *vmx)
2083 {
2084         int save_nmsrs, index;
2085
2086         save_nmsrs = 0;
2087 #ifdef CONFIG_X86_64
2088         if (is_long_mode(&vmx->vcpu)) {
2089                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2090                 if (index >= 0)
2091                         move_msr_up(vmx, index, save_nmsrs++);
2092                 index = __find_msr_index(vmx, MSR_LSTAR);
2093                 if (index >= 0)
2094                         move_msr_up(vmx, index, save_nmsrs++);
2095                 index = __find_msr_index(vmx, MSR_CSTAR);
2096                 if (index >= 0)
2097                         move_msr_up(vmx, index, save_nmsrs++);
2098                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099                 if (index >= 0 && vmx->rdtscp_enabled)
2100                         move_msr_up(vmx, index, save_nmsrs++);
2101                 /*
2102                  * MSR_STAR is only needed on long mode guests, and only
2103                  * if efer.sce is enabled.
2104                  */
2105                 index = __find_msr_index(vmx, MSR_STAR);
2106                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2107                         move_msr_up(vmx, index, save_nmsrs++);
2108         }
2109 #endif
2110         index = __find_msr_index(vmx, MSR_EFER);
2111         if (index >= 0 && update_transition_efer(vmx, index))
2112                 move_msr_up(vmx, index, save_nmsrs++);
2113
2114         vmx->save_nmsrs = save_nmsrs;
2115
2116         if (cpu_has_vmx_msr_bitmap())
2117                 vmx_set_msr_bitmap(&vmx->vcpu);
2118 }
2119
2120 /*
2121  * reads and returns guest's timestamp counter "register"
2122  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2123  */
2124 static u64 guest_read_tsc(void)
2125 {
2126         u64 host_tsc, tsc_offset;
2127
2128         rdtscll(host_tsc);
2129         tsc_offset = vmcs_read64(TSC_OFFSET);
2130         return host_tsc + tsc_offset;
2131 }
2132
2133 /*
2134  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135  * counter, even if a nested guest (L2) is currently running.
2136  */
2137 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2138 {
2139         u64 tsc_offset;
2140
2141         tsc_offset = is_guest_mode(vcpu) ?
2142                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143                 vmcs_read64(TSC_OFFSET);
2144         return host_tsc + tsc_offset;
2145 }
2146
2147 /*
2148  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2149  * software catchup for faster rates on slower CPUs.
2150  */
2151 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2152 {
2153         if (!scale)
2154                 return;
2155
2156         if (user_tsc_khz > tsc_khz) {
2157                 vcpu->arch.tsc_catchup = 1;
2158                 vcpu->arch.tsc_always_catchup = 1;
2159         } else
2160                 WARN(1, "user requested TSC rate below hardware speed\n");
2161 }
2162
2163 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2164 {
2165         return vmcs_read64(TSC_OFFSET);
2166 }
2167
2168 /*
2169  * writes 'offset' into guest's timestamp counter offset register
2170  */
2171 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2172 {
2173         if (is_guest_mode(vcpu)) {
2174                 /*
2175                  * We're here if L1 chose not to trap WRMSR to TSC. According
2176                  * to the spec, this should set L1's TSC; The offset that L1
2177                  * set for L2 remains unchanged, and still needs to be added
2178                  * to the newly set TSC to get L2's TSC.
2179                  */
2180                 struct vmcs12 *vmcs12;
2181                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182                 /* recalculate vmcs02.TSC_OFFSET: */
2183                 vmcs12 = get_vmcs12(vcpu);
2184                 vmcs_write64(TSC_OFFSET, offset +
2185                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186                          vmcs12->tsc_offset : 0));
2187         } else {
2188                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189                                            vmcs_read64(TSC_OFFSET), offset);
2190                 vmcs_write64(TSC_OFFSET, offset);
2191         }
2192 }
2193
2194 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2195 {
2196         u64 offset = vmcs_read64(TSC_OFFSET);
2197
2198         vmcs_write64(TSC_OFFSET, offset + adjustment);
2199         if (is_guest_mode(vcpu)) {
2200                 /* Even when running L2, the adjustment needs to apply to L1 */
2201                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2202         } else
2203                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204                                            offset + adjustment);
2205 }
2206
2207 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2208 {
2209         return target_tsc - native_read_tsc();
2210 }
2211
2212 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2213 {
2214         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2216 }
2217
2218 /*
2219  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221  * all guests if the "nested" module option is off, and can also be disabled
2222  * for a single guest by disabling its VMX cpuid bit.
2223  */
2224 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2225 {
2226         return nested && guest_cpuid_has_vmx(vcpu);
2227 }
2228
2229 /*
2230  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231  * returned for the various VMX controls MSRs when nested VMX is enabled.
2232  * The same values should also be used to verify that vmcs12 control fields are
2233  * valid during nested entry from L1 to L2.
2234  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236  * bit in the high half is on if the corresponding bit in the control field
2237  * may be on. See also vmx_control_verify().
2238  * TODO: allow these variables to be modified (downgraded) by module options
2239  * or other means.
2240  */
2241 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2242 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2243 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2244 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2245 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2246 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2247 static u32 nested_vmx_ept_caps;
2248 static __init void nested_vmx_setup_ctls_msrs(void)
2249 {
2250         /*
2251          * Note that as a general rule, the high half of the MSRs (bits in
2252          * the control fields which may be 1) should be initialized by the
2253          * intersection of the underlying hardware's MSR (i.e., features which
2254          * can be supported) and the list of features we want to expose -
2255          * because they are known to be properly supported in our code.
2256          * Also, usually, the low half of the MSRs (bits which must be 1) can
2257          * be set to 0, meaning that L1 may turn off any of these bits. The
2258          * reason is that if one of these bits is necessary, it will appear
2259          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2260          * fields of vmcs01 and vmcs02, will turn these bits off - and
2261          * nested_vmx_exit_handled() will not pass related exits to L1.
2262          * These rules have exceptions below.
2263          */
2264
2265         /* pin-based controls */
2266         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2267               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2268         /*
2269          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2270          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2271          */
2272         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2273         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2274                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2275         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2276                 PIN_BASED_VMX_PREEMPTION_TIMER;
2277
2278         /*
2279          * Exit controls
2280          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2281          * 17 must be 1.
2282          */
2283         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2284                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2285         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2286
2287         nested_vmx_exit_ctls_high &=
2288 #ifdef CONFIG_X86_64
2289                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2290 #endif
2291                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2292         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2293                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2294                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2295
2296         if (vmx_mpx_supported())
2297                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2298
2299         /* entry controls */
2300         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2301                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2302         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2303         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2304         nested_vmx_entry_ctls_high &=
2305 #ifdef CONFIG_X86_64
2306                 VM_ENTRY_IA32E_MODE |
2307 #endif
2308                 VM_ENTRY_LOAD_IA32_PAT;
2309         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2310                                        VM_ENTRY_LOAD_IA32_EFER);
2311         if (vmx_mpx_supported())
2312                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2313
2314         /* cpu-based controls */
2315         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2316                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2317         nested_vmx_procbased_ctls_low = 0;
2318         nested_vmx_procbased_ctls_high &=
2319                 CPU_BASED_VIRTUAL_INTR_PENDING |
2320                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2321                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2322                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2323                 CPU_BASED_CR3_STORE_EXITING |
2324 #ifdef CONFIG_X86_64
2325                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2326 #endif
2327                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2328                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2329                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2330                 CPU_BASED_PAUSE_EXITING |
2331                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2332         /*
2333          * We can allow some features even when not supported by the
2334          * hardware. For example, L1 can specify an MSR bitmap - and we
2335          * can use it to avoid exits to L1 - even when L0 runs L2
2336          * without MSR bitmaps.
2337          */
2338         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2339
2340         /* secondary cpu-based controls */
2341         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2342                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2343         nested_vmx_secondary_ctls_low = 0;
2344         nested_vmx_secondary_ctls_high &=
2345                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2346                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2347                 SECONDARY_EXEC_WBINVD_EXITING;
2348
2349         if (enable_ept) {
2350                 /* nested EPT: emulate EPT also to L1 */
2351                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2352                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2353                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2354                          VMX_EPT_INVEPT_BIT;
2355                 nested_vmx_ept_caps &= vmx_capability.ept;
2356                 /*
2357                  * For nested guests, we don't do anything specific
2358                  * for single context invalidation. Hence, only advertise
2359                  * support for global context invalidation.
2360                  */
2361                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2362         } else
2363                 nested_vmx_ept_caps = 0;
2364
2365         /* miscellaneous data */
2366         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2367         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2368         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2369                 VMX_MISC_ACTIVITY_HLT;
2370         nested_vmx_misc_high = 0;
2371 }
2372
2373 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2374 {
2375         /*
2376          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2377          */
2378         return ((control & high) | low) == control;
2379 }
2380
2381 static inline u64 vmx_control_msr(u32 low, u32 high)
2382 {
2383         return low | ((u64)high << 32);
2384 }
2385
2386 /* Returns 0 on success, non-0 otherwise. */
2387 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2388 {
2389         switch (msr_index) {
2390         case MSR_IA32_VMX_BASIC:
2391                 /*
2392                  * This MSR reports some information about VMX support. We
2393                  * should return information about the VMX we emulate for the
2394                  * guest, and the VMCS structure we give it - not about the
2395                  * VMX support of the underlying hardware.
2396                  */
2397                 *pdata = VMCS12_REVISION |
2398                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2399                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2400                 break;
2401         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2402         case MSR_IA32_VMX_PINBASED_CTLS:
2403                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2404                                         nested_vmx_pinbased_ctls_high);
2405                 break;
2406         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2407         case MSR_IA32_VMX_PROCBASED_CTLS:
2408                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2409                                         nested_vmx_procbased_ctls_high);
2410                 break;
2411         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2412         case MSR_IA32_VMX_EXIT_CTLS:
2413                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2414                                         nested_vmx_exit_ctls_high);
2415                 break;
2416         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2417         case MSR_IA32_VMX_ENTRY_CTLS:
2418                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2419                                         nested_vmx_entry_ctls_high);
2420                 break;
2421         case MSR_IA32_VMX_MISC:
2422                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2423                                          nested_vmx_misc_high);
2424                 break;
2425         /*
2426          * These MSRs specify bits which the guest must keep fixed (on or off)
2427          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2428          * We picked the standard core2 setting.
2429          */
2430 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2431 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2432         case MSR_IA32_VMX_CR0_FIXED0:
2433                 *pdata = VMXON_CR0_ALWAYSON;
2434                 break;
2435         case MSR_IA32_VMX_CR0_FIXED1:
2436                 *pdata = -1ULL;
2437                 break;
2438         case MSR_IA32_VMX_CR4_FIXED0:
2439                 *pdata = VMXON_CR4_ALWAYSON;
2440                 break;
2441         case MSR_IA32_VMX_CR4_FIXED1:
2442                 *pdata = -1ULL;
2443                 break;
2444         case MSR_IA32_VMX_VMCS_ENUM:
2445                 *pdata = 0x1f;
2446                 break;
2447         case MSR_IA32_VMX_PROCBASED_CTLS2:
2448                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2449                                         nested_vmx_secondary_ctls_high);
2450                 break;
2451         case MSR_IA32_VMX_EPT_VPID_CAP:
2452                 /* Currently, no nested vpid support */
2453                 *pdata = nested_vmx_ept_caps;
2454                 break;
2455         default:
2456                 return 1;
2457         }
2458
2459         return 0;
2460 }
2461
2462 /*
2463  * Reads an msr value (of 'msr_index') into 'pdata'.
2464  * Returns 0 on success, non-0 otherwise.
2465  * Assumes vcpu_load() was already called.
2466  */
2467 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2468 {
2469         u64 data;
2470         struct shared_msr_entry *msr;
2471
2472         if (!pdata) {
2473                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2474                 return -EINVAL;
2475         }
2476
2477         switch (msr_index) {
2478 #ifdef CONFIG_X86_64
2479         case MSR_FS_BASE:
2480                 data = vmcs_readl(GUEST_FS_BASE);
2481                 break;
2482         case MSR_GS_BASE:
2483                 data = vmcs_readl(GUEST_GS_BASE);
2484                 break;
2485         case MSR_KERNEL_GS_BASE:
2486                 vmx_load_host_state(to_vmx(vcpu));
2487                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2488                 break;
2489 #endif
2490         case MSR_EFER:
2491                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2492         case MSR_IA32_TSC:
2493                 data = guest_read_tsc();
2494                 break;
2495         case MSR_IA32_SYSENTER_CS:
2496                 data = vmcs_read32(GUEST_SYSENTER_CS);
2497                 break;
2498         case MSR_IA32_SYSENTER_EIP:
2499                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2500                 break;
2501         case MSR_IA32_SYSENTER_ESP:
2502                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2503                 break;
2504         case MSR_IA32_BNDCFGS:
2505                 if (!vmx_mpx_supported())
2506                         return 1;
2507                 data = vmcs_read64(GUEST_BNDCFGS);
2508                 break;
2509         case MSR_IA32_FEATURE_CONTROL:
2510                 if (!nested_vmx_allowed(vcpu))
2511                         return 1;
2512                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2513                 break;
2514         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2515                 if (!nested_vmx_allowed(vcpu))
2516                         return 1;
2517                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2518         case MSR_TSC_AUX:
2519                 if (!to_vmx(vcpu)->rdtscp_enabled)
2520                         return 1;
2521                 /* Otherwise falls through */
2522         default:
2523                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2524                 if (msr) {
2525                         data = msr->data;
2526                         break;
2527                 }
2528                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2529         }
2530
2531         *pdata = data;
2532         return 0;
2533 }
2534
2535 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2536
2537 /*
2538  * Writes msr value into into the appropriate "register".
2539  * Returns 0 on success, non-0 otherwise.
2540  * Assumes vcpu_load() was already called.
2541  */
2542 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2543 {
2544         struct vcpu_vmx *vmx = to_vmx(vcpu);
2545         struct shared_msr_entry *msr;
2546         int ret = 0;
2547         u32 msr_index = msr_info->index;
2548         u64 data = msr_info->data;
2549
2550         switch (msr_index) {
2551         case MSR_EFER:
2552                 ret = kvm_set_msr_common(vcpu, msr_info);
2553                 break;
2554 #ifdef CONFIG_X86_64
2555         case MSR_FS_BASE:
2556                 vmx_segment_cache_clear(vmx);
2557                 vmcs_writel(GUEST_FS_BASE, data);
2558                 break;
2559         case MSR_GS_BASE:
2560                 vmx_segment_cache_clear(vmx);
2561                 vmcs_writel(GUEST_GS_BASE, data);
2562                 break;
2563         case MSR_KERNEL_GS_BASE:
2564                 vmx_load_host_state(vmx);
2565                 vmx->msr_guest_kernel_gs_base = data;
2566                 break;
2567 #endif
2568         case MSR_IA32_SYSENTER_CS:
2569                 vmcs_write32(GUEST_SYSENTER_CS, data);
2570                 break;
2571         case MSR_IA32_SYSENTER_EIP:
2572                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2573                 break;
2574         case MSR_IA32_SYSENTER_ESP:
2575                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2576                 break;
2577         case MSR_IA32_BNDCFGS:
2578                 if (!vmx_mpx_supported())
2579                         return 1;
2580                 vmcs_write64(GUEST_BNDCFGS, data);
2581                 break;
2582         case MSR_IA32_TSC:
2583                 kvm_write_tsc(vcpu, msr_info);
2584                 break;
2585         case MSR_IA32_CR_PAT:
2586                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2587                         vmcs_write64(GUEST_IA32_PAT, data);
2588                         vcpu->arch.pat = data;
2589                         break;
2590                 }
2591                 ret = kvm_set_msr_common(vcpu, msr_info);
2592                 break;
2593         case MSR_IA32_TSC_ADJUST:
2594                 ret = kvm_set_msr_common(vcpu, msr_info);
2595                 break;
2596         case MSR_IA32_FEATURE_CONTROL:
2597                 if (!nested_vmx_allowed(vcpu) ||
2598                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2599                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2600                         return 1;
2601                 vmx->nested.msr_ia32_feature_control = data;
2602                 if (msr_info->host_initiated && data == 0)
2603                         vmx_leave_nested(vcpu);
2604                 break;
2605         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2606                 return 1; /* they are read-only */
2607         case MSR_TSC_AUX:
2608                 if (!vmx->rdtscp_enabled)
2609                         return 1;
2610                 /* Check reserved bit, higher 32 bits should be zero */
2611                 if ((data >> 32) != 0)
2612                         return 1;
2613                 /* Otherwise falls through */
2614         default:
2615                 msr = find_msr_entry(vmx, msr_index);
2616                 if (msr) {
2617                         msr->data = data;
2618                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2619                                 preempt_disable();
2620                                 kvm_set_shared_msr(msr->index, msr->data,
2621                                                    msr->mask);
2622                                 preempt_enable();
2623                         }
2624                         break;
2625                 }
2626                 ret = kvm_set_msr_common(vcpu, msr_info);
2627         }
2628
2629         return ret;
2630 }
2631
2632 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2633 {
2634         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2635         switch (reg) {
2636         case VCPU_REGS_RSP:
2637                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2638                 break;
2639         case VCPU_REGS_RIP:
2640                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2641                 break;
2642         case VCPU_EXREG_PDPTR:
2643                 if (enable_ept)
2644                         ept_save_pdptrs(vcpu);
2645                 break;
2646         default:
2647                 break;
2648         }
2649 }
2650
2651 static __init int cpu_has_kvm_support(void)
2652 {
2653         return cpu_has_vmx();
2654 }
2655
2656 static __init int vmx_disabled_by_bios(void)
2657 {
2658         u64 msr;
2659
2660         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2661         if (msr & FEATURE_CONTROL_LOCKED) {
2662                 /* launched w/ TXT and VMX disabled */
2663                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2664                         && tboot_enabled())
2665                         return 1;
2666                 /* launched w/o TXT and VMX only enabled w/ TXT */
2667                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2668                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2669                         && !tboot_enabled()) {
2670                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2671                                 "activate TXT before enabling KVM\n");
2672                         return 1;
2673                 }
2674                 /* launched w/o TXT and VMX disabled */
2675                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2676                         && !tboot_enabled())
2677                         return 1;
2678         }
2679
2680         return 0;
2681 }
2682
2683 static void kvm_cpu_vmxon(u64 addr)
2684 {
2685         asm volatile (ASM_VMX_VMXON_RAX
2686                         : : "a"(&addr), "m"(addr)
2687                         : "memory", "cc");
2688 }
2689
2690 static int hardware_enable(void *garbage)
2691 {
2692         int cpu = raw_smp_processor_id();
2693         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2694         u64 old, test_bits;
2695
2696         if (read_cr4() & X86_CR4_VMXE)
2697                 return -EBUSY;
2698
2699         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2700
2701         /*
2702          * Now we can enable the vmclear operation in kdump
2703          * since the loaded_vmcss_on_cpu list on this cpu
2704          * has been initialized.
2705          *
2706          * Though the cpu is not in VMX operation now, there
2707          * is no problem to enable the vmclear operation
2708          * for the loaded_vmcss_on_cpu list is empty!
2709          */
2710         crash_enable_local_vmclear(cpu);
2711
2712         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2713
2714         test_bits = FEATURE_CONTROL_LOCKED;
2715         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2716         if (tboot_enabled())
2717                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2718
2719         if ((old & test_bits) != test_bits) {
2720                 /* enable and lock */
2721                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2722         }
2723         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2724
2725         if (vmm_exclusive) {
2726                 kvm_cpu_vmxon(phys_addr);
2727                 ept_sync_global();
2728         }
2729
2730         native_store_gdt(&__get_cpu_var(host_gdt));
2731
2732         return 0;
2733 }
2734
2735 static void vmclear_local_loaded_vmcss(void)
2736 {
2737         int cpu = raw_smp_processor_id();
2738         struct loaded_vmcs *v, *n;
2739
2740         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2741                                  loaded_vmcss_on_cpu_link)
2742                 __loaded_vmcs_clear(v);
2743 }
2744
2745
2746 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2747  * tricks.
2748  */
2749 static void kvm_cpu_vmxoff(void)
2750 {
2751         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2752 }
2753
2754 static void hardware_disable(void *garbage)
2755 {
2756         if (vmm_exclusive) {
2757                 vmclear_local_loaded_vmcss();
2758                 kvm_cpu_vmxoff();
2759         }
2760         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2761 }
2762
2763 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2764                                       u32 msr, u32 *result)
2765 {
2766         u32 vmx_msr_low, vmx_msr_high;
2767         u32 ctl = ctl_min | ctl_opt;
2768
2769         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2770
2771         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2772         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2773
2774         /* Ensure minimum (required) set of control bits are supported. */
2775         if (ctl_min & ~ctl)
2776                 return -EIO;
2777
2778         *result = ctl;
2779         return 0;
2780 }
2781
2782 static __init bool allow_1_setting(u32 msr, u32 ctl)
2783 {
2784         u32 vmx_msr_low, vmx_msr_high;
2785
2786         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2787         return vmx_msr_high & ctl;
2788 }
2789
2790 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2791 {
2792         u32 vmx_msr_low, vmx_msr_high;
2793         u32 min, opt, min2, opt2;
2794         u32 _pin_based_exec_control = 0;
2795         u32 _cpu_based_exec_control = 0;
2796         u32 _cpu_based_2nd_exec_control = 0;
2797         u32 _vmexit_control = 0;
2798         u32 _vmentry_control = 0;
2799
2800         min = CPU_BASED_HLT_EXITING |
2801 #ifdef CONFIG_X86_64
2802               CPU_BASED_CR8_LOAD_EXITING |
2803               CPU_BASED_CR8_STORE_EXITING |
2804 #endif
2805               CPU_BASED_CR3_LOAD_EXITING |
2806               CPU_BASED_CR3_STORE_EXITING |
2807               CPU_BASED_USE_IO_BITMAPS |
2808               CPU_BASED_MOV_DR_EXITING |
2809               CPU_BASED_USE_TSC_OFFSETING |
2810               CPU_BASED_MWAIT_EXITING |
2811               CPU_BASED_MONITOR_EXITING |
2812               CPU_BASED_INVLPG_EXITING |
2813               CPU_BASED_RDPMC_EXITING;
2814
2815         opt = CPU_BASED_TPR_SHADOW |
2816               CPU_BASED_USE_MSR_BITMAPS |
2817               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2818         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2819                                 &_cpu_based_exec_control) < 0)
2820                 return -EIO;
2821 #ifdef CONFIG_X86_64
2822         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2823                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2824                                            ~CPU_BASED_CR8_STORE_EXITING;
2825 #endif
2826         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2827                 min2 = 0;
2828                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2829                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2830                         SECONDARY_EXEC_WBINVD_EXITING |
2831                         SECONDARY_EXEC_ENABLE_VPID |
2832                         SECONDARY_EXEC_ENABLE_EPT |
2833                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2834                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2835                         SECONDARY_EXEC_RDTSCP |
2836                         SECONDARY_EXEC_ENABLE_INVPCID |
2837                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2838                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2839                         SECONDARY_EXEC_SHADOW_VMCS;
2840                 if (adjust_vmx_controls(min2, opt2,
2841                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2842                                         &_cpu_based_2nd_exec_control) < 0)
2843                         return -EIO;
2844         }
2845 #ifndef CONFIG_X86_64
2846         if (!(_cpu_based_2nd_exec_control &
2847                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2848                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2849 #endif
2850
2851         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2852                 _cpu_based_2nd_exec_control &= ~(
2853                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2854                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2855                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2856
2857         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2858                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2859                    enabled */
2860                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2861                                              CPU_BASED_CR3_STORE_EXITING |
2862                                              CPU_BASED_INVLPG_EXITING);
2863                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2864                       vmx_capability.ept, vmx_capability.vpid);
2865         }
2866
2867         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2868 #ifdef CONFIG_X86_64
2869         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2870 #endif
2871         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2872                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2873         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2874                                 &_vmexit_control) < 0)
2875                 return -EIO;
2876
2877         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2878         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2879         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2880                                 &_pin_based_exec_control) < 0)
2881                 return -EIO;
2882
2883         if (!(_cpu_based_2nd_exec_control &
2884                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2885                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2886                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2887
2888         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2889         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2890         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2891                                 &_vmentry_control) < 0)
2892                 return -EIO;
2893
2894         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2895
2896         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2897         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2898                 return -EIO;
2899
2900 #ifdef CONFIG_X86_64
2901         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2902         if (vmx_msr_high & (1u<<16))
2903                 return -EIO;
2904 #endif
2905
2906         /* Require Write-Back (WB) memory type for VMCS accesses. */
2907         if (((vmx_msr_high >> 18) & 15) != 6)
2908                 return -EIO;
2909
2910         vmcs_conf->size = vmx_msr_high & 0x1fff;
2911         vmcs_conf->order = get_order(vmcs_config.size);
2912         vmcs_conf->revision_id = vmx_msr_low;
2913
2914         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2915         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2916         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2917         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2918         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2919
2920         cpu_has_load_ia32_efer =
2921                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2922                                 VM_ENTRY_LOAD_IA32_EFER)
2923                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2924                                    VM_EXIT_LOAD_IA32_EFER);
2925
2926         cpu_has_load_perf_global_ctrl =
2927                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2928                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2929                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2930                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2931
2932         /*
2933          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2934          * but due to arrata below it can't be used. Workaround is to use
2935          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2936          *
2937          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2938          *
2939          * AAK155             (model 26)
2940          * AAP115             (model 30)
2941          * AAT100             (model 37)
2942          * BC86,AAY89,BD102   (model 44)
2943          * BA97               (model 46)
2944          *
2945          */
2946         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2947                 switch (boot_cpu_data.x86_model) {
2948                 case 26:
2949                 case 30:
2950                 case 37:
2951                 case 44:
2952                 case 46:
2953                         cpu_has_load_perf_global_ctrl = false;
2954                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2955                                         "does not work properly. Using workaround\n");
2956                         break;
2957                 default:
2958                         break;
2959                 }
2960         }
2961
2962         return 0;
2963 }
2964
2965 static struct vmcs *alloc_vmcs_cpu(int cpu)
2966 {
2967         int node = cpu_to_node(cpu);
2968         struct page *pages;
2969         struct vmcs *vmcs;
2970
2971         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2972         if (!pages)
2973                 return NULL;
2974         vmcs = page_address(pages);
2975         memset(vmcs, 0, vmcs_config.size);
2976         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2977         return vmcs;
2978 }
2979
2980 static struct vmcs *alloc_vmcs(void)
2981 {
2982         return alloc_vmcs_cpu(raw_smp_processor_id());
2983 }
2984
2985 static void free_vmcs(struct vmcs *vmcs)
2986 {
2987         free_pages((unsigned long)vmcs, vmcs_config.order);
2988 }
2989
2990 /*
2991  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2992  */
2993 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2994 {
2995         if (!loaded_vmcs->vmcs)
2996                 return;
2997         loaded_vmcs_clear(loaded_vmcs);
2998         free_vmcs(loaded_vmcs->vmcs);
2999         loaded_vmcs->vmcs = NULL;
3000 }
3001
3002 static void free_kvm_area(void)
3003 {
3004         int cpu;
3005
3006         for_each_possible_cpu(cpu) {
3007                 free_vmcs(per_cpu(vmxarea, cpu));
3008                 per_cpu(vmxarea, cpu) = NULL;
3009         }
3010 }
3011
3012 static __init int alloc_kvm_area(void)
3013 {
3014         int cpu;
3015
3016         for_each_possible_cpu(cpu) {
3017                 struct vmcs *vmcs;
3018
3019                 vmcs = alloc_vmcs_cpu(cpu);
3020                 if (!vmcs) {
3021                         free_kvm_area();
3022                         return -ENOMEM;
3023                 }
3024
3025                 per_cpu(vmxarea, cpu) = vmcs;
3026         }
3027         return 0;
3028 }
3029
3030 static __init int hardware_setup(void)
3031 {
3032         if (setup_vmcs_config(&vmcs_config) < 0)
3033                 return -EIO;
3034
3035         if (boot_cpu_has(X86_FEATURE_NX))
3036                 kvm_enable_efer_bits(EFER_NX);
3037
3038         if (!cpu_has_vmx_vpid())
3039                 enable_vpid = 0;
3040         if (!cpu_has_vmx_shadow_vmcs())
3041                 enable_shadow_vmcs = 0;
3042
3043         if (!cpu_has_vmx_ept() ||
3044             !cpu_has_vmx_ept_4levels()) {
3045                 enable_ept = 0;
3046                 enable_unrestricted_guest = 0;
3047                 enable_ept_ad_bits = 0;
3048         }
3049
3050         if (!cpu_has_vmx_ept_ad_bits())
3051                 enable_ept_ad_bits = 0;
3052
3053         if (!cpu_has_vmx_unrestricted_guest())
3054                 enable_unrestricted_guest = 0;
3055
3056         if (!cpu_has_vmx_flexpriority())
3057                 flexpriority_enabled = 0;
3058
3059         if (!cpu_has_vmx_tpr_shadow())
3060                 kvm_x86_ops->update_cr8_intercept = NULL;
3061
3062         if (enable_ept && !cpu_has_vmx_ept_2m_page())
3063                 kvm_disable_largepages();
3064
3065         if (!cpu_has_vmx_ple())
3066                 ple_gap = 0;
3067
3068         if (!cpu_has_vmx_apicv())
3069                 enable_apicv = 0;
3070
3071         if (enable_apicv)
3072                 kvm_x86_ops->update_cr8_intercept = NULL;
3073         else {
3074                 kvm_x86_ops->hwapic_irr_update = NULL;
3075                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3076                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3077         }
3078
3079         if (nested)
3080                 nested_vmx_setup_ctls_msrs();
3081
3082         return alloc_kvm_area();
3083 }
3084
3085 static __exit void hardware_unsetup(void)
3086 {
3087         free_kvm_area();
3088 }
3089
3090 static bool emulation_required(struct kvm_vcpu *vcpu)
3091 {
3092         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3093 }
3094
3095 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3096                 struct kvm_segment *save)
3097 {
3098         if (!emulate_invalid_guest_state) {
3099                 /*
3100                  * CS and SS RPL should be equal during guest entry according
3101                  * to VMX spec, but in reality it is not always so. Since vcpu
3102                  * is in the middle of the transition from real mode to
3103                  * protected mode it is safe to assume that RPL 0 is a good
3104                  * default value.
3105                  */
3106                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3107                         save->selector &= ~SELECTOR_RPL_MASK;
3108                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3109                 save->s = 1;
3110         }
3111         vmx_set_segment(vcpu, save, seg);
3112 }
3113
3114 static void enter_pmode(struct kvm_vcpu *vcpu)
3115 {
3116         unsigned long flags;
3117         struct vcpu_vmx *vmx = to_vmx(vcpu);
3118
3119         /*
3120          * Update real mode segment cache. It may be not up-to-date if sement
3121          * register was written while vcpu was in a guest mode.
3122          */
3123         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3124         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3125         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3126         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3127         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3128         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3129
3130         vmx->rmode.vm86_active = 0;
3131
3132         vmx_segment_cache_clear(vmx);
3133
3134         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3135
3136         flags = vmcs_readl(GUEST_RFLAGS);
3137         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3138         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3139         vmcs_writel(GUEST_RFLAGS, flags);
3140
3141         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3142                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3143
3144         update_exception_bitmap(vcpu);
3145
3146         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3147         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3148         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3149         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3150         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3151         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3152
3153         /* CPL is always 0 when CPU enters protected mode */
3154         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3155         vmx->cpl = 0;
3156 }
3157
3158 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3159 {
3160         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3161         struct kvm_segment var = *save;
3162
3163         var.dpl = 0x3;
3164         if (seg == VCPU_SREG_CS)
3165                 var.type = 0x3;
3166
3167         if (!emulate_invalid_guest_state) {
3168                 var.selector = var.base >> 4;
3169                 var.base = var.base & 0xffff0;
3170                 var.limit = 0xffff;
3171                 var.g = 0;
3172                 var.db = 0;
3173                 var.present = 1;
3174                 var.s = 1;
3175                 var.l = 0;
3176                 var.unusable = 0;
3177                 var.type = 0x3;
3178                 var.avl = 0;
3179                 if (save->base & 0xf)
3180                         printk_once(KERN_WARNING "kvm: segment base is not "
3181                                         "paragraph aligned when entering "
3182                                         "protected mode (seg=%d)", seg);
3183         }
3184
3185         vmcs_write16(sf->selector, var.selector);
3186         vmcs_write32(sf->base, var.base);
3187         vmcs_write32(sf->limit, var.limit);
3188         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3189 }
3190
3191 static void enter_rmode(struct kvm_vcpu *vcpu)
3192 {
3193         unsigned long flags;
3194         struct vcpu_vmx *vmx = to_vmx(vcpu);
3195
3196         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3197         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3198         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3199         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3200         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3201         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3202         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3203
3204         vmx->rmode.vm86_active = 1;
3205
3206         /*
3207          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3208          * vcpu. Warn the user that an update is overdue.
3209          */
3210         if (!vcpu->kvm->arch.tss_addr)
3211                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3212                              "called before entering vcpu\n");
3213
3214         vmx_segment_cache_clear(vmx);
3215
3216         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3217         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3218         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3219
3220         flags = vmcs_readl(GUEST_RFLAGS);
3221         vmx->rmode.save_rflags = flags;
3222
3223         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3224
3225         vmcs_writel(GUEST_RFLAGS, flags);
3226         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3227         update_exception_bitmap(vcpu);
3228
3229         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3230         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3231         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3232         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3233         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3234         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3235
3236         kvm_mmu_reset_context(vcpu);
3237 }
3238
3239 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3240 {
3241         struct vcpu_vmx *vmx = to_vmx(vcpu);
3242         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3243
3244         if (!msr)
3245                 return;
3246
3247         /*
3248          * Force kernel_gs_base reloading before EFER changes, as control
3249          * of this msr depends on is_long_mode().
3250          */
3251         vmx_load_host_state(to_vmx(vcpu));
3252         vcpu->arch.efer = efer;
3253         if (efer & EFER_LMA) {
3254                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3255                 msr->data = efer;
3256         } else {
3257                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3258
3259                 msr->data = efer & ~EFER_LME;
3260         }
3261         setup_msrs(vmx);
3262 }
3263
3264 #ifdef CONFIG_X86_64
3265
3266 static void enter_lmode(struct kvm_vcpu *vcpu)
3267 {
3268         u32 guest_tr_ar;
3269
3270         vmx_segment_cache_clear(to_vmx(vcpu));
3271
3272         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3273         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3274                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3275                                      __func__);
3276                 vmcs_write32(GUEST_TR_AR_BYTES,
3277                              (guest_tr_ar & ~AR_TYPE_MASK)
3278                              | AR_TYPE_BUSY_64_TSS);
3279         }
3280         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3281 }
3282
3283 static void exit_lmode(struct kvm_vcpu *vcpu)
3284 {
3285         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3286         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3287 }
3288
3289 #endif
3290
3291 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3292 {
3293         vpid_sync_context(to_vmx(vcpu));
3294         if (enable_ept) {
3295                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3296                         return;
3297                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3298         }
3299 }
3300
3301 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3302 {
3303         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3304
3305         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3306         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3307 }
3308
3309 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3310 {
3311         if (enable_ept && is_paging(vcpu))
3312                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3313         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3314 }
3315
3316 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3317 {
3318         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3319
3320         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3321         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3322 }
3323
3324 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3325 {
3326         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3327
3328         if (!test_bit(VCPU_EXREG_PDPTR,
3329                       (unsigned long *)&vcpu->arch.regs_dirty))
3330                 return;
3331
3332         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3333                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3334                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3335                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3336                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3337         }
3338 }
3339
3340 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3341 {
3342         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3343
3344         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3345                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3346                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3347                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3348                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3349         }
3350
3351         __set_bit(VCPU_EXREG_PDPTR,
3352                   (unsigned long *)&vcpu->arch.regs_avail);
3353         __set_bit(VCPU_EXREG_PDPTR,
3354                   (unsigned long *)&vcpu->arch.regs_dirty);
3355 }
3356
3357 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3358
3359 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3360                                         unsigned long cr0,
3361                                         struct kvm_vcpu *vcpu)
3362 {
3363         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3364                 vmx_decache_cr3(vcpu);
3365         if (!(cr0 & X86_CR0_PG)) {
3366                 /* From paging/starting to nonpaging */
3367                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3368                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3369                              (CPU_BASED_CR3_LOAD_EXITING |
3370                               CPU_BASED_CR3_STORE_EXITING));
3371                 vcpu->arch.cr0 = cr0;
3372                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3373         } else if (!is_paging(vcpu)) {
3374                 /* From nonpaging to paging */
3375                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3376                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3377                              ~(CPU_BASED_CR3_LOAD_EXITING |
3378                                CPU_BASED_CR3_STORE_EXITING));
3379                 vcpu->arch.cr0 = cr0;
3380                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3381         }
3382
3383         if (!(cr0 & X86_CR0_WP))
3384                 *hw_cr0 &= ~X86_CR0_WP;
3385 }
3386
3387 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3388 {
3389         struct vcpu_vmx *vmx = to_vmx(vcpu);
3390         unsigned long hw_cr0;
3391
3392         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3393         if (enable_unrestricted_guest)
3394                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3395         else {
3396                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3397
3398                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3399                         enter_pmode(vcpu);
3400
3401                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3402                         enter_rmode(vcpu);
3403         }
3404
3405 #ifdef CONFIG_X86_64
3406         if (vcpu->arch.efer & EFER_LME) {
3407                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3408                         enter_lmode(vcpu);
3409                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3410                         exit_lmode(vcpu);
3411         }
3412 #endif
3413
3414         if (enable_ept)
3415                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3416
3417         if (!vcpu->fpu_active)
3418                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3419
3420         vmcs_writel(CR0_READ_SHADOW, cr0);
3421         vmcs_writel(GUEST_CR0, hw_cr0);
3422         vcpu->arch.cr0 = cr0;
3423
3424         /* depends on vcpu->arch.cr0 to be set to a new value */
3425         vmx->emulation_required = emulation_required(vcpu);
3426 }
3427
3428 static u64 construct_eptp(unsigned long root_hpa)
3429 {
3430         u64 eptp;
3431
3432         /* TODO write the value reading from MSR */
3433         eptp = VMX_EPT_DEFAULT_MT |
3434                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3435         if (enable_ept_ad_bits)
3436                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3437         eptp |= (root_hpa & PAGE_MASK);
3438
3439         return eptp;
3440 }
3441
3442 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3443 {
3444         unsigned long guest_cr3;
3445         u64 eptp;
3446
3447         guest_cr3 = cr3;
3448         if (enable_ept) {
3449                 eptp = construct_eptp(cr3);
3450                 vmcs_write64(EPT_POINTER, eptp);
3451                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3452                         guest_cr3 = kvm_read_cr3(vcpu);
3453                 else
3454                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3455                 ept_load_pdptrs(vcpu);
3456         }
3457
3458         vmx_flush_tlb(vcpu);
3459         vmcs_writel(GUEST_CR3, guest_cr3);
3460 }
3461
3462 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3463 {
3464         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3465                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3466
3467         if (cr4 & X86_CR4_VMXE) {
3468                 /*
3469                  * To use VMXON (and later other VMX instructions), a guest
3470                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3471                  * So basically the check on whether to allow nested VMX
3472                  * is here.
3473                  */
3474                 if (!nested_vmx_allowed(vcpu))
3475                         return 1;
3476         }
3477         if (to_vmx(vcpu)->nested.vmxon &&
3478             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3479                 return 1;
3480
3481         vcpu->arch.cr4 = cr4;
3482         if (enable_ept) {
3483                 if (!is_paging(vcpu)) {
3484                         hw_cr4 &= ~X86_CR4_PAE;
3485                         hw_cr4 |= X86_CR4_PSE;
3486                         /*
3487                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3488                          * in hardware. However KVM always uses paging mode to
3489                          * emulate guest non-paging mode with TDP.
3490                          * To emulate this behavior, SMEP/SMAP needs to be
3491                          * manually disabled when guest switches to non-paging
3492                          * mode.
3493                          */
3494                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3495                 } else if (!(cr4 & X86_CR4_PAE)) {
3496                         hw_cr4 &= ~X86_CR4_PAE;
3497                 }
3498         }
3499
3500         vmcs_writel(CR4_READ_SHADOW, cr4);
3501         vmcs_writel(GUEST_CR4, hw_cr4);
3502         return 0;
3503 }
3504
3505 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3506                             struct kvm_segment *var, int seg)
3507 {
3508         struct vcpu_vmx *vmx = to_vmx(vcpu);
3509         u32 ar;
3510
3511         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3512                 *var = vmx->rmode.segs[seg];
3513                 if (seg == VCPU_SREG_TR
3514                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3515                         return;
3516                 var->base = vmx_read_guest_seg_base(vmx, seg);
3517                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3518                 return;
3519         }
3520         var->base = vmx_read_guest_seg_base(vmx, seg);
3521         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3522         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3523         ar = vmx_read_guest_seg_ar(vmx, seg);
3524         var->unusable = (ar >> 16) & 1;
3525         var->type = ar & 15;
3526         var->s = (ar >> 4) & 1;
3527         var->dpl = (ar >> 5) & 3;
3528         /*
3529          * Some userspaces do not preserve unusable property. Since usable
3530          * segment has to be present according to VMX spec we can use present
3531          * property to amend userspace bug by making unusable segment always
3532          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3533          * segment as unusable.
3534          */
3535         var->present = !var->unusable;
3536         var->avl = (ar >> 12) & 1;
3537         var->l = (ar >> 13) & 1;
3538         var->db = (ar >> 14) & 1;
3539         var->g = (ar >> 15) & 1;
3540 }
3541
3542 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3543 {
3544         struct kvm_segment s;
3545
3546         if (to_vmx(vcpu)->rmode.vm86_active) {
3547                 vmx_get_segment(vcpu, &s, seg);
3548                 return s.base;
3549         }
3550         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3551 }
3552
3553 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3554 {
3555         struct vcpu_vmx *vmx = to_vmx(vcpu);
3556
3557         if (!is_protmode(vcpu))
3558                 return 0;
3559
3560         if (!is_long_mode(vcpu)
3561             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3562                 return 3;
3563
3564         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3565                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3566                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3567         }
3568
3569         return vmx->cpl;
3570 }
3571
3572
3573 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3574 {
3575         u32 ar;
3576
3577         if (var->unusable || !var->present)
3578                 ar = 1 << 16;
3579         else {
3580                 ar = var->type & 15;
3581                 ar |= (var->s & 1) << 4;
3582                 ar |= (var->dpl & 3) << 5;
3583                 ar |= (var->present & 1) << 7;
3584                 ar |= (var->avl & 1) << 12;
3585                 ar |= (var->l & 1) << 13;
3586                 ar |= (var->db & 1) << 14;
3587                 ar |= (var->g & 1) << 15;
3588         }
3589
3590         return ar;
3591 }
3592
3593 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3594                             struct kvm_segment *var, int seg)
3595 {
3596         struct vcpu_vmx *vmx = to_vmx(vcpu);
3597         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3598
3599         vmx_segment_cache_clear(vmx);
3600         if (seg == VCPU_SREG_CS)
3601                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3602
3603         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3604                 vmx->rmode.segs[seg] = *var;
3605                 if (seg == VCPU_SREG_TR)
3606                         vmcs_write16(sf->selector, var->selector);
3607                 else if (var->s)
3608                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3609                 goto out;
3610         }
3611
3612         vmcs_writel(sf->base, var->base);
3613         vmcs_write32(sf->limit, var->limit);
3614         vmcs_write16(sf->selector, var->selector);
3615
3616         /*
3617          *   Fix the "Accessed" bit in AR field of segment registers for older
3618          * qemu binaries.
3619          *   IA32 arch specifies that at the time of processor reset the
3620          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3621          * is setting it to 0 in the userland code. This causes invalid guest
3622          * state vmexit when "unrestricted guest" mode is turned on.
3623          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3624          * tree. Newer qemu binaries with that qemu fix would not need this
3625          * kvm hack.
3626          */
3627         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3628                 var->type |= 0x1; /* Accessed */
3629
3630         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3631
3632 out:
3633         vmx->emulation_required |= emulation_required(vcpu);
3634 }
3635
3636 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3637 {
3638         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3639
3640         *db = (ar >> 14) & 1;
3641         *l = (ar >> 13) & 1;
3642 }
3643
3644 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3645 {
3646         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3647         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3648 }
3649
3650 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3651 {
3652         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3653         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3654 }
3655
3656 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3657 {
3658         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3659         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3660 }
3661
3662 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3663 {
3664         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3665         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3666 }
3667
3668 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3669 {
3670         struct kvm_segment var;
3671         u32 ar;
3672
3673         vmx_get_segment(vcpu, &var, seg);
3674         var.dpl = 0x3;
3675         if (seg == VCPU_SREG_CS)
3676                 var.type = 0x3;
3677         ar = vmx_segment_access_rights(&var);
3678
3679         if (var.base != (var.selector << 4))
3680                 return false;
3681         if (var.limit != 0xffff)
3682                 return false;
3683         if (ar != 0xf3)
3684                 return false;
3685
3686         return true;
3687 }
3688
3689 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3690 {
3691         struct kvm_segment cs;
3692         unsigned int cs_rpl;
3693
3694         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3695         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3696
3697         if (cs.unusable)
3698                 return false;
3699         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3700                 return false;
3701         if (!cs.s)
3702                 return false;
3703         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3704                 if (cs.dpl > cs_rpl)
3705                         return false;
3706         } else {
3707                 if (cs.dpl != cs_rpl)
3708                         return false;
3709         }
3710         if (!cs.present)
3711                 return false;
3712
3713         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3714         return true;
3715 }
3716
3717 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3718 {
3719         struct kvm_segment ss;
3720         unsigned int ss_rpl;
3721
3722         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3723         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3724
3725         if (ss.unusable)
3726                 return true;
3727         if (ss.type != 3 && ss.type != 7)
3728                 return false;
3729         if (!ss.s)
3730                 return false;
3731         if (ss.dpl != ss_rpl) /* DPL != RPL */
3732                 return false;
3733         if (!ss.present)
3734                 return false;
3735
3736         return true;
3737 }
3738
3739 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3740 {
3741         struct kvm_segment var;
3742         unsigned int rpl;
3743
3744         vmx_get_segment(vcpu, &var, seg);
3745         rpl = var.selector & SELECTOR_RPL_MASK;
3746
3747         if (var.unusable)
3748                 return true;
3749         if (!var.s)
3750                 return false;
3751         if (!var.present)
3752                 return false;
3753         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3754                 if (var.dpl < rpl) /* DPL < RPL */
3755                         return false;
3756         }
3757
3758         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3759          * rights flags
3760          */
3761         return true;
3762 }
3763
3764 static bool tr_valid(struct kvm_vcpu *vcpu)
3765 {
3766         struct kvm_segment tr;
3767
3768         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3769
3770         if (tr.unusable)
3771                 return false;
3772         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3773                 return false;
3774         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3775                 return false;
3776         if (!tr.present)
3777                 return false;
3778
3779         return true;
3780 }
3781
3782 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3783 {
3784         struct kvm_segment ldtr;
3785
3786         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3787
3788         if (ldtr.unusable)
3789                 return true;
3790         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3791                 return false;
3792         if (ldtr.type != 2)
3793                 return false;
3794         if (!ldtr.present)
3795                 return false;
3796
3797         return true;
3798 }
3799
3800 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3801 {
3802         struct kvm_segment cs, ss;
3803
3804         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3805         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3806
3807         return ((cs.selector & SELECTOR_RPL_MASK) ==
3808                  (ss.selector & SELECTOR_RPL_MASK));
3809 }
3810
3811 /*
3812  * Check if guest state is valid. Returns true if valid, false if
3813  * not.
3814  * We assume that registers are always usable
3815  */
3816 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3817 {
3818         if (enable_unrestricted_guest)
3819                 return true;
3820
3821         /* real mode guest state checks */
3822         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3823                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3824                         return false;
3825                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3826                         return false;
3827                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3828                         return false;
3829                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3830                         return false;
3831                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3832                         return false;
3833                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3834                         return false;
3835         } else {
3836         /* protected mode guest state checks */
3837                 if (!cs_ss_rpl_check(vcpu))
3838                         return false;
3839                 if (!code_segment_valid(vcpu))
3840                         return false;
3841                 if (!stack_segment_valid(vcpu))
3842                         return false;
3843                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3844                         return false;
3845                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3846                         return false;
3847                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3848                         return false;
3849                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3850                         return false;
3851                 if (!tr_valid(vcpu))
3852                         return false;
3853                 if (!ldtr_valid(vcpu))
3854                         return false;
3855         }
3856         /* TODO:
3857          * - Add checks on RIP
3858          * - Add checks on RFLAGS
3859          */
3860
3861         return true;
3862 }
3863
3864 static int init_rmode_tss(struct kvm *kvm)
3865 {
3866         gfn_t fn;
3867         u16 data = 0;
3868         int r, idx, ret = 0;
3869
3870         idx = srcu_read_lock(&kvm->srcu);
3871         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3872         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3873         if (r < 0)
3874                 goto out;
3875         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3876         r = kvm_write_guest_page(kvm, fn++, &data,
3877                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3878         if (r < 0)
3879                 goto out;
3880         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3881         if (r < 0)
3882                 goto out;
3883         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3884         if (r < 0)
3885                 goto out;
3886         data = ~0;
3887         r = kvm_write_guest_page(kvm, fn, &data,
3888                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3889                                  sizeof(u8));
3890         if (r < 0)
3891                 goto out;
3892
3893         ret = 1;
3894 out:
3895         srcu_read_unlock(&kvm->srcu, idx);
3896         return ret;
3897 }
3898
3899 static int init_rmode_identity_map(struct kvm *kvm)
3900 {
3901         int i, idx, r, ret;
3902         pfn_t identity_map_pfn;
3903         u32 tmp;
3904
3905         if (!enable_ept)
3906                 return 1;
3907         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3908                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3909                         "haven't been allocated!\n");
3910                 return 0;
3911         }
3912         if (likely(kvm->arch.ept_identity_pagetable_done))
3913                 return 1;
3914         ret = 0;
3915         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3916         idx = srcu_read_lock(&kvm->srcu);
3917         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3918         if (r < 0)
3919                 goto out;
3920         /* Set up identity-mapping pagetable for EPT in real mode */
3921         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3922                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3923                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3924                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3925                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3926                 if (r < 0)
3927                         goto out;
3928         }
3929         kvm->arch.ept_identity_pagetable_done = true;
3930         ret = 1;
3931 out:
3932         srcu_read_unlock(&kvm->srcu, idx);
3933         return ret;
3934 }
3935
3936 static void seg_setup(int seg)
3937 {
3938         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3939         unsigned int ar;
3940
3941         vmcs_write16(sf->selector, 0);
3942         vmcs_writel(sf->base, 0);
3943         vmcs_write32(sf->limit, 0xffff);
3944         ar = 0x93;
3945         if (seg == VCPU_SREG_CS)
3946                 ar |= 0x08; /* code segment */
3947
3948         vmcs_write32(sf->ar_bytes, ar);
3949 }
3950
3951 static int alloc_apic_access_page(struct kvm *kvm)
3952 {
3953         struct page *page;
3954         struct kvm_userspace_memory_region kvm_userspace_mem;
3955         int r = 0;
3956
3957         mutex_lock(&kvm->slots_lock);
3958         if (kvm->arch.apic_access_page)
3959                 goto out;
3960         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3961         kvm_userspace_mem.flags = 0;
3962         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3963         kvm_userspace_mem.memory_size = PAGE_SIZE;
3964         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3965         if (r)
3966                 goto out;
3967
3968         page = gfn_to_page(kvm, 0xfee00);
3969         if (is_error_page(page)) {
3970                 r = -EFAULT;
3971                 goto out;
3972         }
3973
3974         kvm->arch.apic_access_page = page;
3975 out:
3976         mutex_unlock(&kvm->slots_lock);
3977         return r;
3978 }
3979
3980 static int alloc_identity_pagetable(struct kvm *kvm)
3981 {
3982         struct page *page;
3983         struct kvm_userspace_memory_region kvm_userspace_mem;
3984         int r = 0;
3985
3986         mutex_lock(&kvm->slots_lock);
3987         if (kvm->arch.ept_identity_pagetable)
3988                 goto out;
3989         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3990         kvm_userspace_mem.flags = 0;
3991         kvm_userspace_mem.guest_phys_addr =
3992                 kvm->arch.ept_identity_map_addr;
3993         kvm_userspace_mem.memory_size = PAGE_SIZE;
3994         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3995         if (r)
3996                 goto out;
3997
3998         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3999         if (is_error_page(page)) {
4000                 r = -EFAULT;
4001                 goto out;
4002         }
4003
4004         kvm->arch.ept_identity_pagetable = page;
4005 out:
4006         mutex_unlock(&kvm->slots_lock);
4007         return r;
4008 }
4009
4010 static void allocate_vpid(struct vcpu_vmx *vmx)
4011 {
4012         int vpid;
4013
4014         vmx->vpid = 0;
4015         if (!enable_vpid)
4016                 return;
4017         spin_lock(&vmx_vpid_lock);
4018         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4019         if (vpid < VMX_NR_VPIDS) {
4020                 vmx->vpid = vpid;
4021                 __set_bit(vpid, vmx_vpid_bitmap);
4022         }
4023         spin_unlock(&vmx_vpid_lock);
4024 }
4025
4026 static void free_vpid(struct vcpu_vmx *vmx)
4027 {
4028         if (!enable_vpid)
4029                 return;
4030         spin_lock(&vmx_vpid_lock);
4031         if (vmx->vpid != 0)
4032                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4033         spin_unlock(&vmx_vpid_lock);
4034 }
4035
4036 #define MSR_TYPE_R      1
4037 #define MSR_TYPE_W      2
4038 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4039                                                 u32 msr, int type)
4040 {
4041         int f = sizeof(unsigned long);
4042
4043         if (!cpu_has_vmx_msr_bitmap())
4044                 return;
4045
4046         /*
4047          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4048          * have the write-low and read-high bitmap offsets the wrong way round.
4049          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4050          */
4051         if (msr <= 0x1fff) {
4052                 if (type & MSR_TYPE_R)
4053                         /* read-low */
4054                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4055
4056                 if (type & MSR_TYPE_W)
4057                         /* write-low */
4058                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4059
4060         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4061                 msr &= 0x1fff;
4062                 if (type & MSR_TYPE_R)
4063                         /* read-high */
4064                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4065
4066                 if (type & MSR_TYPE_W)
4067                         /* write-high */
4068                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4069
4070         }
4071 }
4072
4073 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4074                                                 u32 msr, int type)
4075 {
4076         int f = sizeof(unsigned long);
4077
4078         if (!cpu_has_vmx_msr_bitmap())
4079                 return;
4080
4081         /*
4082          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4083          * have the write-low and read-high bitmap offsets the wrong way round.
4084          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4085          */
4086         if (msr <= 0x1fff) {
4087                 if (type & MSR_TYPE_R)
4088                         /* read-low */
4089                         __set_bit(msr, msr_bitmap + 0x000 / f);
4090
4091                 if (type & MSR_TYPE_W)
4092                         /* write-low */
4093                         __set_bit(msr, msr_bitmap + 0x800 / f);
4094
4095         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4096                 msr &= 0x1fff;
4097                 if (type & MSR_TYPE_R)
4098                         /* read-high */
4099                         __set_bit(msr, msr_bitmap + 0x400 / f);
4100
4101                 if (type & MSR_TYPE_W)
4102                         /* write-high */
4103                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4104
4105         }
4106 }
4107
4108 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4109 {
4110         if (!longmode_only)
4111                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4112                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4113         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4114                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4115 }
4116
4117 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4118 {
4119         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4120                         msr, MSR_TYPE_R);
4121         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4122                         msr, MSR_TYPE_R);
4123 }
4124
4125 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4126 {
4127         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4128                         msr, MSR_TYPE_R);
4129         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4130                         msr, MSR_TYPE_R);
4131 }
4132
4133 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4134 {
4135         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4136                         msr, MSR_TYPE_W);
4137         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4138                         msr, MSR_TYPE_W);
4139 }
4140
4141 static int vmx_vm_has_apicv(struct kvm *kvm)
4142 {
4143         return enable_apicv && irqchip_in_kernel(kvm);
4144 }
4145
4146 /*
4147  * Send interrupt to vcpu via posted interrupt way.
4148  * 1. If target vcpu is running(non-root mode), send posted interrupt
4149  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4150  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4151  * interrupt from PIR in next vmentry.
4152  */
4153 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4154 {
4155         struct vcpu_vmx *vmx = to_vmx(vcpu);
4156         int r;
4157
4158         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4159                 return;
4160
4161         r = pi_test_and_set_on(&vmx->pi_desc);
4162         kvm_make_request(KVM_REQ_EVENT, vcpu);
4163 #ifdef CONFIG_SMP
4164         if (!r && (vcpu->mode == IN_GUEST_MODE))
4165                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4166                                 POSTED_INTR_VECTOR);
4167         else
4168 #endif
4169                 kvm_vcpu_kick(vcpu);
4170 }
4171
4172 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4173 {
4174         struct vcpu_vmx *vmx = to_vmx(vcpu);
4175
4176         if (!pi_test_and_clear_on(&vmx->pi_desc))
4177                 return;
4178
4179         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4180 }
4181
4182 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4183 {
4184         return;
4185 }
4186
4187 /*
4188  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4189  * will not change in the lifetime of the guest.
4190  * Note that host-state that does change is set elsewhere. E.g., host-state
4191  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4192  */
4193 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4194 {
4195         u32 low32, high32;
4196         unsigned long tmpl;
4197         struct desc_ptr dt;
4198
4199         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4200         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4201         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4202
4203         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4204 #ifdef CONFIG_X86_64
4205         /*
4206          * Load null selectors, so we can avoid reloading them in
4207          * __vmx_load_host_state(), in case userspace uses the null selectors
4208          * too (the expected case).
4209          */
4210         vmcs_write16(HOST_DS_SELECTOR, 0);
4211         vmcs_write16(HOST_ES_SELECTOR, 0);
4212 #else
4213         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4214         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4215 #endif
4216         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4217         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4218
4219         native_store_idt(&dt);
4220         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4221         vmx->host_idt_base = dt.address;
4222
4223         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4224
4225         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4226         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4227         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4228         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4229
4230         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4231                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4232                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4233         }
4234 }
4235
4236 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4237 {
4238         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4239         if (enable_ept)
4240                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4241         if (is_guest_mode(&vmx->vcpu))
4242                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4243                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4244         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4245 }
4246
4247 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4248 {
4249         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4250
4251         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4252                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4253         return pin_based_exec_ctrl;
4254 }
4255
4256 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4257 {
4258         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4259
4260         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4261                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4262
4263         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4264                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4265 #ifdef CONFIG_X86_64
4266                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4267                                 CPU_BASED_CR8_LOAD_EXITING;
4268 #endif
4269         }
4270         if (!enable_ept)
4271                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4272                                 CPU_BASED_CR3_LOAD_EXITING  |
4273                                 CPU_BASED_INVLPG_EXITING;
4274         return exec_control;
4275 }
4276
4277 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4278 {
4279         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4280         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4281                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4282         if (vmx->vpid == 0)
4283                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4284         if (!enable_ept) {
4285                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4286                 enable_unrestricted_guest = 0;
4287                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4288                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4289         }
4290         if (!enable_unrestricted_guest)
4291                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4292         if (!ple_gap)
4293                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4294         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4295                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4296                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4297         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4298         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4299            (handle_vmptrld).
4300            We can NOT enable shadow_vmcs here because we don't have yet
4301            a current VMCS12
4302         */
4303         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4304         return exec_control;
4305 }
4306
4307 static void ept_set_mmio_spte_mask(void)
4308 {
4309         /*
4310          * EPT Misconfigurations can be generated if the value of bits 2:0
4311          * of an EPT paging-structure entry is 110b (write/execute).
4312          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4313          * spte.
4314          */
4315         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4316 }
4317
4318 /*
4319  * Sets up the vmcs for emulated real mode.
4320  */
4321 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4322 {
4323 #ifdef CONFIG_X86_64
4324         unsigned long a;
4325 #endif
4326         int i;
4327
4328         /* I/O */
4329         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4330         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4331
4332         if (enable_shadow_vmcs) {
4333                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4334                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4335         }
4336         if (cpu_has_vmx_msr_bitmap())
4337                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4338
4339         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4340
4341         /* Control */
4342         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4343
4344         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4345
4346         if (cpu_has_secondary_exec_ctrls()) {
4347                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4348                                 vmx_secondary_exec_control(vmx));
4349         }
4350
4351         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4352                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4353                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4354                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4355                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4356
4357                 vmcs_write16(GUEST_INTR_STATUS, 0);
4358
4359                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4360                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4361         }
4362
4363         if (ple_gap) {
4364                 vmcs_write32(PLE_GAP, ple_gap);
4365                 vmcs_write32(PLE_WINDOW, ple_window);
4366         }
4367
4368         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4369         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4370         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4371
4372         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4373         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4374         vmx_set_constant_host_state(vmx);
4375 #ifdef CONFIG_X86_64
4376         rdmsrl(MSR_FS_BASE, a);
4377         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4378         rdmsrl(MSR_GS_BASE, a);
4379         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4380 #else
4381         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4382         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4383 #endif
4384
4385         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4386         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4387         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4388         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4389         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4390
4391         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4392                 u32 msr_low, msr_high;
4393                 u64 host_pat;
4394                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4395                 host_pat = msr_low | ((u64) msr_high << 32);
4396                 /* Write the default value follow host pat */
4397                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4398                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4399                 vmx->vcpu.arch.pat = host_pat;
4400         }
4401
4402         for (i = 0; i < NR_VMX_MSR; ++i) {
4403                 u32 index = vmx_msr_index[i];
4404                 u32 data_low, data_high;
4405                 int j = vmx->nmsrs;
4406
4407                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4408                         continue;
4409                 if (wrmsr_safe(index, data_low, data_high) < 0)
4410                         continue;
4411                 vmx->guest_msrs[j].index = i;
4412                 vmx->guest_msrs[j].data = 0;
4413                 vmx->guest_msrs[j].mask = -1ull;
4414                 ++vmx->nmsrs;
4415         }
4416
4417
4418         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4419
4420         /* 22.2.1, 20.8.1 */
4421         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4422
4423         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4424         set_cr4_guest_host_mask(vmx);
4425
4426         return 0;
4427 }
4428
4429 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4430 {
4431         struct vcpu_vmx *vmx = to_vmx(vcpu);
4432         struct msr_data apic_base_msr;
4433
4434         vmx->rmode.vm86_active = 0;
4435
4436         vmx->soft_vnmi_blocked = 0;
4437
4438         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4439         kvm_set_cr8(&vmx->vcpu, 0);
4440         apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4441         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4442                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4443         apic_base_msr.host_initiated = true;
4444         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4445
4446         vmx_segment_cache_clear(vmx);
4447
4448         seg_setup(VCPU_SREG_CS);
4449         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4450         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4451
4452         seg_setup(VCPU_SREG_DS);
4453         seg_setup(VCPU_SREG_ES);
4454         seg_setup(VCPU_SREG_FS);
4455         seg_setup(VCPU_SREG_GS);
4456         seg_setup(VCPU_SREG_SS);
4457
4458         vmcs_write16(GUEST_TR_SELECTOR, 0);
4459         vmcs_writel(GUEST_TR_BASE, 0);
4460         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4461         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4462
4463         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4464         vmcs_writel(GUEST_LDTR_BASE, 0);
4465         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4466         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4467
4468         vmcs_write32(GUEST_SYSENTER_CS, 0);
4469         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4470         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4471
4472         vmcs_writel(GUEST_RFLAGS, 0x02);
4473         kvm_rip_write(vcpu, 0xfff0);
4474
4475         vmcs_writel(GUEST_GDTR_BASE, 0);
4476         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4477
4478         vmcs_writel(GUEST_IDTR_BASE, 0);
4479         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4480
4481         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4482         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4483         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4484
4485         /* Special registers */
4486         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4487
4488         setup_msrs(vmx);
4489
4490         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4491
4492         if (cpu_has_vmx_tpr_shadow()) {
4493                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4494                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4495                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4496                                      __pa(vmx->vcpu.arch.apic->regs));
4497                 vmcs_write32(TPR_THRESHOLD, 0);
4498         }
4499
4500         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4501                 vmcs_write64(APIC_ACCESS_ADDR,
4502                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4503
4504         if (vmx_vm_has_apicv(vcpu->kvm))
4505                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4506
4507         if (vmx->vpid != 0)
4508                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4509
4510         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4511         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4512         vmx_set_cr4(&vmx->vcpu, 0);
4513         vmx_set_efer(&vmx->vcpu, 0);
4514         vmx_fpu_activate(&vmx->vcpu);
4515         update_exception_bitmap(&vmx->vcpu);
4516
4517         vpid_sync_context(vmx);
4518 }
4519
4520 /*
4521  * In nested virtualization, check if L1 asked to exit on external interrupts.
4522  * For most existing hypervisors, this will always return true.
4523  */
4524 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4525 {
4526         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4527                 PIN_BASED_EXT_INTR_MASK;
4528 }
4529
4530 /*
4531  * In nested virtualization, check if L1 has set
4532  * VM_EXIT_ACK_INTR_ON_EXIT
4533  */
4534 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4535 {
4536         return get_vmcs12(vcpu)->vm_exit_controls &
4537                 VM_EXIT_ACK_INTR_ON_EXIT;
4538 }
4539
4540 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4541 {
4542         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4543                 PIN_BASED_NMI_EXITING;
4544 }
4545
4546 static void enable_irq_window(struct kvm_vcpu *vcpu)
4547 {
4548         u32 cpu_based_vm_exec_control;
4549
4550         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4551         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4552         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4553 }
4554
4555 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4556 {
4557         u32 cpu_based_vm_exec_control;
4558
4559         if (!cpu_has_virtual_nmis() ||
4560             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4561                 enable_irq_window(vcpu);
4562                 return;
4563         }
4564
4565         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4566         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4567         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4568 }
4569
4570 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4571 {
4572         struct vcpu_vmx *vmx = to_vmx(vcpu);
4573         uint32_t intr;
4574         int irq = vcpu->arch.interrupt.nr;
4575
4576         trace_kvm_inj_virq(irq);
4577
4578         ++vcpu->stat.irq_injections;
4579         if (vmx->rmode.vm86_active) {
4580                 int inc_eip = 0;
4581                 if (vcpu->arch.interrupt.soft)
4582                         inc_eip = vcpu->arch.event_exit_inst_len;
4583                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4584                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4585                 return;
4586         }
4587         intr = irq | INTR_INFO_VALID_MASK;
4588         if (vcpu->arch.interrupt.soft) {
4589                 intr |= INTR_TYPE_SOFT_INTR;
4590                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4591                              vmx->vcpu.arch.event_exit_inst_len);
4592         } else
4593                 intr |= INTR_TYPE_EXT_INTR;
4594         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4595 }
4596
4597 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4598 {
4599         struct vcpu_vmx *vmx = to_vmx(vcpu);
4600
4601         if (is_guest_mode(vcpu))
4602                 return;
4603
4604         if (!cpu_has_virtual_nmis()) {
4605                 /*
4606                  * Tracking the NMI-blocked state in software is built upon
4607                  * finding the next open IRQ window. This, in turn, depends on
4608                  * well-behaving guests: They have to keep IRQs disabled at
4609                  * least as long as the NMI handler runs. Otherwise we may
4610                  * cause NMI nesting, maybe breaking the guest. But as this is
4611                  * highly unlikely, we can live with the residual risk.
4612                  */
4613                 vmx->soft_vnmi_blocked = 1;
4614                 vmx->vnmi_blocked_time = 0;
4615         }
4616
4617         ++vcpu->stat.nmi_injections;
4618         vmx->nmi_known_unmasked = false;
4619         if (vmx->rmode.vm86_active) {
4620                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4621                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4622                 return;
4623         }
4624         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4625                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4626 }
4627
4628 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4629 {
4630         if (!cpu_has_virtual_nmis())
4631                 return to_vmx(vcpu)->soft_vnmi_blocked;
4632         if (to_vmx(vcpu)->nmi_known_unmasked)
4633                 return false;
4634         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4635 }
4636
4637 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4638 {
4639         struct vcpu_vmx *vmx = to_vmx(vcpu);
4640
4641         if (!cpu_has_virtual_nmis()) {
4642                 if (vmx->soft_vnmi_blocked != masked) {
4643                         vmx->soft_vnmi_blocked = masked;
4644                         vmx->vnmi_blocked_time = 0;
4645                 }
4646         } else {
4647                 vmx->nmi_known_unmasked = !masked;
4648                 if (masked)
4649                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4650                                       GUEST_INTR_STATE_NMI);
4651                 else
4652                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4653                                         GUEST_INTR_STATE_NMI);
4654         }
4655 }
4656
4657 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4658 {
4659         if (to_vmx(vcpu)->nested.nested_run_pending)
4660                 return 0;
4661
4662         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4663                 return 0;
4664
4665         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4666                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4667                    | GUEST_INTR_STATE_NMI));
4668 }
4669
4670 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4671 {
4672         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4673                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4674                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4675                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4676 }
4677
4678 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4679 {
4680         int ret;
4681         struct kvm_userspace_memory_region tss_mem = {
4682                 .slot = TSS_PRIVATE_MEMSLOT,
4683                 .guest_phys_addr = addr,
4684                 .memory_size = PAGE_SIZE * 3,
4685                 .flags = 0,
4686         };
4687
4688         ret = kvm_set_memory_region(kvm, &tss_mem);
4689         if (ret)
4690                 return ret;
4691         kvm->arch.tss_addr = addr;
4692         if (!init_rmode_tss(kvm))
4693                 return  -ENOMEM;
4694
4695         return 0;
4696 }
4697
4698 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4699 {
4700         switch (vec) {
4701         case BP_VECTOR:
4702                 /*
4703                  * Update instruction length as we may reinject the exception
4704                  * from user space while in guest debugging mode.
4705                  */
4706                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4707                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4708                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4709                         return false;
4710                 /* fall through */
4711         case DB_VECTOR:
4712                 if (vcpu->guest_debug &
4713                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4714                         return false;
4715                 /* fall through */
4716         case DE_VECTOR:
4717         case OF_VECTOR:
4718         case BR_VECTOR:
4719         case UD_VECTOR:
4720         case DF_VECTOR:
4721         case SS_VECTOR:
4722         case GP_VECTOR:
4723         case MF_VECTOR:
4724                 return true;
4725         break;
4726         }
4727         return false;
4728 }
4729
4730 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4731                                   int vec, u32 err_code)
4732 {
4733         /*
4734          * Instruction with address size override prefix opcode 0x67
4735          * Cause the #SS fault with 0 error code in VM86 mode.
4736          */
4737         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4738                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4739                         if (vcpu->arch.halt_request) {
4740                                 vcpu->arch.halt_request = 0;
4741                                 return kvm_emulate_halt(vcpu);
4742                         }
4743                         return 1;
4744                 }
4745                 return 0;
4746         }
4747
4748         /*
4749          * Forward all other exceptions that are valid in real mode.
4750          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4751          *        the required debugging infrastructure rework.
4752          */
4753         kvm_queue_exception(vcpu, vec);
4754         return 1;
4755 }
4756
4757 /*
4758  * Trigger machine check on the host. We assume all the MSRs are already set up
4759  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4760  * We pass a fake environment to the machine check handler because we want
4761  * the guest to be always treated like user space, no matter what context
4762  * it used internally.
4763  */
4764 static void kvm_machine_check(void)
4765 {
4766 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4767         struct pt_regs regs = {
4768                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4769                 .flags = X86_EFLAGS_IF,
4770         };
4771
4772         do_machine_check(&regs, 0);
4773 #endif
4774 }
4775
4776 static int handle_machine_check(struct kvm_vcpu *vcpu)
4777 {
4778         /* already handled by vcpu_run */
4779         return 1;
4780 }
4781
4782 static int handle_exception(struct kvm_vcpu *vcpu)
4783 {
4784         struct vcpu_vmx *vmx = to_vmx(vcpu);
4785         struct kvm_run *kvm_run = vcpu->run;
4786         u32 intr_info, ex_no, error_code;
4787         unsigned long cr2, rip, dr6;
4788         u32 vect_info;
4789         enum emulation_result er;
4790
4791         vect_info = vmx->idt_vectoring_info;
4792         intr_info = vmx->exit_intr_info;
4793
4794         if (is_machine_check(intr_info))
4795                 return handle_machine_check(vcpu);
4796
4797         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4798                 return 1;  /* already handled by vmx_vcpu_run() */
4799
4800         if (is_no_device(intr_info)) {
4801                 vmx_fpu_activate(vcpu);
4802                 return 1;
4803         }
4804
4805         if (is_invalid_opcode(intr_info)) {
4806                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4807                 if (er != EMULATE_DONE)
4808                         kvm_queue_exception(vcpu, UD_VECTOR);
4809                 return 1;
4810         }
4811
4812         error_code = 0;
4813         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4814                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4815
4816         /*
4817          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4818          * MMIO, it is better to report an internal error.
4819          * See the comments in vmx_handle_exit.
4820          */
4821         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4822             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4823                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4824                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4825                 vcpu->run->internal.ndata = 2;
4826                 vcpu->run->internal.data[0] = vect_info;
4827                 vcpu->run->internal.data[1] = intr_info;
4828                 return 0;
4829         }
4830
4831         if (is_page_fault(intr_info)) {
4832                 /* EPT won't cause page fault directly */
4833                 BUG_ON(enable_ept);
4834                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4835                 trace_kvm_page_fault(cr2, error_code);
4836
4837                 if (kvm_event_needs_reinjection(vcpu))
4838                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4839                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4840         }
4841
4842         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4843
4844         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4845                 return handle_rmode_exception(vcpu, ex_no, error_code);
4846
4847         switch (ex_no) {
4848         case DB_VECTOR:
4849                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4850                 if (!(vcpu->guest_debug &
4851                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4852                         vcpu->arch.dr6 &= ~15;
4853                         vcpu->arch.dr6 |= dr6;
4854                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4855                                 skip_emulated_instruction(vcpu);
4856
4857                         kvm_queue_exception(vcpu, DB_VECTOR);
4858                         return 1;
4859                 }
4860                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4861                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4862                 /* fall through */
4863         case BP_VECTOR:
4864                 /*
4865                  * Update instruction length as we may reinject #BP from
4866                  * user space while in guest debugging mode. Reading it for
4867                  * #DB as well causes no harm, it is not used in that case.
4868                  */
4869                 vmx->vcpu.arch.event_exit_inst_len =
4870                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4871                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4872                 rip = kvm_rip_read(vcpu);
4873                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4874                 kvm_run->debug.arch.exception = ex_no;
4875                 break;
4876         default:
4877                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4878                 kvm_run->ex.exception = ex_no;
4879                 kvm_run->ex.error_code = error_code;
4880                 break;
4881         }
4882         return 0;
4883 }
4884
4885 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4886 {
4887         ++vcpu->stat.irq_exits;
4888         return 1;
4889 }
4890
4891 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4892 {
4893         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4894         return 0;
4895 }
4896
4897 static int handle_io(struct kvm_vcpu *vcpu)
4898 {
4899         unsigned long exit_qualification;
4900         int size, in, string;
4901         unsigned port;
4902
4903         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4904         string = (exit_qualification & 16) != 0;
4905         in = (exit_qualification & 8) != 0;
4906
4907         ++vcpu->stat.io_exits;
4908
4909         if (string || in)
4910                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4911
4912         port = exit_qualification >> 16;
4913         size = (exit_qualification & 7) + 1;
4914         skip_emulated_instruction(vcpu);
4915
4916         return kvm_fast_pio_out(vcpu, size, port);
4917 }
4918
4919 static void
4920 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4921 {
4922         /*
4923          * Patch in the VMCALL instruction:
4924          */
4925         hypercall[0] = 0x0f;
4926         hypercall[1] = 0x01;
4927         hypercall[2] = 0xc1;
4928 }
4929
4930 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4931 {
4932         unsigned long always_on = VMXON_CR0_ALWAYSON;
4933
4934         if (nested_vmx_secondary_ctls_high &
4935                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4936             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4937                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4938         return (val & always_on) == always_on;
4939 }
4940
4941 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4942 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4943 {
4944         if (is_guest_mode(vcpu)) {
4945                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4946                 unsigned long orig_val = val;
4947
4948                 /*
4949                  * We get here when L2 changed cr0 in a way that did not change
4950                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4951                  * but did change L0 shadowed bits. So we first calculate the
4952                  * effective cr0 value that L1 would like to write into the
4953                  * hardware. It consists of the L2-owned bits from the new
4954                  * value combined with the L1-owned bits from L1's guest_cr0.
4955                  */
4956                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4957                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4958
4959                 if (!nested_cr0_valid(vmcs12, val))
4960                         return 1;
4961
4962                 if (kvm_set_cr0(vcpu, val))
4963                         return 1;
4964                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4965                 return 0;
4966         } else {
4967                 if (to_vmx(vcpu)->nested.vmxon &&
4968                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4969                         return 1;
4970                 return kvm_set_cr0(vcpu, val);
4971         }
4972 }
4973
4974 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4975 {
4976         if (is_guest_mode(vcpu)) {
4977                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4978                 unsigned long orig_val = val;
4979
4980                 /* analogously to handle_set_cr0 */
4981                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4982                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4983                 if (kvm_set_cr4(vcpu, val))
4984                         return 1;
4985                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4986                 return 0;
4987         } else
4988                 return kvm_set_cr4(vcpu, val);
4989 }
4990
4991 /* called to set cr0 as approriate for clts instruction exit. */
4992 static void handle_clts(struct kvm_vcpu *vcpu)
4993 {
4994         if (is_guest_mode(vcpu)) {
4995                 /*
4996                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4997                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4998                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4999                  */
5000                 vmcs_writel(CR0_READ_SHADOW,
5001                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5002                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5003         } else
5004                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5005 }
5006
5007 static int handle_cr(struct kvm_vcpu *vcpu)
5008 {
5009         unsigned long exit_qualification, val;
5010         int cr;
5011         int reg;
5012         int err;
5013
5014         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5015         cr = exit_qualification & 15;
5016         reg = (exit_qualification >> 8) & 15;
5017         switch ((exit_qualification >> 4) & 3) {
5018         case 0: /* mov to cr */
5019                 val = kvm_register_read(vcpu, reg);
5020                 trace_kvm_cr_write(cr, val);
5021                 switch (cr) {
5022                 case 0:
5023                         err = handle_set_cr0(vcpu, val);
5024                         kvm_complete_insn_gp(vcpu, err);
5025                         return 1;
5026                 case 3:
5027                         err = kvm_set_cr3(vcpu, val);
5028                         kvm_complete_insn_gp(vcpu, err);
5029                         return 1;
5030                 case 4:
5031                         err = handle_set_cr4(vcpu, val);
5032                         kvm_complete_insn_gp(vcpu, err);
5033                         return 1;
5034                 case 8: {
5035                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5036                                 u8 cr8 = kvm_register_read(vcpu, reg);
5037                                 err = kvm_set_cr8(vcpu, cr8);
5038                                 kvm_complete_insn_gp(vcpu, err);
5039                                 if (irqchip_in_kernel(vcpu->kvm))
5040                                         return 1;
5041                                 if (cr8_prev <= cr8)
5042                                         return 1;
5043                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5044                                 return 0;
5045                         }
5046                 }
5047                 break;
5048         case 2: /* clts */
5049                 handle_clts(vcpu);
5050                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5051                 skip_emulated_instruction(vcpu);
5052                 vmx_fpu_activate(vcpu);
5053                 return 1;
5054         case 1: /*mov from cr*/
5055                 switch (cr) {
5056                 case 3:
5057                         val = kvm_read_cr3(vcpu);
5058                         kvm_register_write(vcpu, reg, val);
5059                         trace_kvm_cr_read(cr, val);
5060                         skip_emulated_instruction(vcpu);
5061                         return 1;
5062                 case 8:
5063                         val = kvm_get_cr8(vcpu);
5064                         kvm_register_write(vcpu, reg, val);
5065                         trace_kvm_cr_read(cr, val);
5066                         skip_emulated_instruction(vcpu);
5067                         return 1;
5068                 }
5069                 break;
5070         case 3: /* lmsw */
5071                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5072                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5073                 kvm_lmsw(vcpu, val);
5074
5075                 skip_emulated_instruction(vcpu);
5076                 return 1;
5077         default:
5078                 break;
5079         }
5080         vcpu->run->exit_reason = 0;
5081         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5082                (int)(exit_qualification >> 4) & 3, cr);
5083         return 0;
5084 }
5085
5086 static int handle_dr(struct kvm_vcpu *vcpu)
5087 {
5088         unsigned long exit_qualification;
5089         int dr, reg;
5090
5091         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5092         if (!kvm_require_cpl(vcpu, 0))
5093                 return 1;
5094         dr = vmcs_readl(GUEST_DR7);
5095         if (dr & DR7_GD) {
5096                 /*
5097                  * As the vm-exit takes precedence over the debug trap, we
5098                  * need to emulate the latter, either for the host or the
5099                  * guest debugging itself.
5100                  */
5101                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5102                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5103                         vcpu->run->debug.arch.dr7 = dr;
5104                         vcpu->run->debug.arch.pc =
5105                                 vmcs_readl(GUEST_CS_BASE) +
5106                                 vmcs_readl(GUEST_RIP);
5107                         vcpu->run->debug.arch.exception = DB_VECTOR;
5108                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5109                         return 0;
5110                 } else {
5111                         vcpu->arch.dr7 &= ~DR7_GD;
5112                         vcpu->arch.dr6 |= DR6_BD;
5113                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5114                         kvm_queue_exception(vcpu, DB_VECTOR);
5115                         return 1;
5116                 }
5117         }
5118
5119         if (vcpu->guest_debug == 0) {
5120                 u32 cpu_based_vm_exec_control;
5121
5122                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5123                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5124                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5125
5126                 /*
5127                  * No more DR vmexits; force a reload of the debug registers
5128                  * and reenter on this instruction.  The next vmexit will
5129                  * retrieve the full state of the debug registers.
5130                  */
5131                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5132                 return 1;
5133         }
5134
5135         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5136         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5137         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5138         if (exit_qualification & TYPE_MOV_FROM_DR) {
5139                 unsigned long val;
5140
5141                 if (kvm_get_dr(vcpu, dr, &val))
5142                         return 1;
5143                 kvm_register_write(vcpu, reg, val);
5144         } else
5145                 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5146                         return 1;
5147
5148         skip_emulated_instruction(vcpu);
5149         return 1;
5150 }
5151
5152 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5153 {
5154         return vcpu->arch.dr6;
5155 }
5156
5157 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5158 {
5159 }
5160
5161 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5162 {
5163         u32 cpu_based_vm_exec_control;
5164
5165         get_debugreg(vcpu->arch.db[0], 0);
5166         get_debugreg(vcpu->arch.db[1], 1);
5167         get_debugreg(vcpu->arch.db[2], 2);
5168         get_debugreg(vcpu->arch.db[3], 3);
5169         get_debugreg(vcpu->arch.dr6, 6);
5170         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5171
5172         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5173
5174         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5175         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5176         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5177 }
5178
5179 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5180 {
5181         vmcs_writel(GUEST_DR7, val);
5182 }
5183
5184 static int handle_cpuid(struct kvm_vcpu *vcpu)
5185 {
5186         kvm_emulate_cpuid(vcpu);
5187         return 1;
5188 }
5189
5190 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5191 {
5192         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5193         u64 data;
5194
5195         if (vmx_get_msr(vcpu, ecx, &data)) {
5196                 trace_kvm_msr_read_ex(ecx);
5197                 kvm_inject_gp(vcpu, 0);
5198                 return 1;
5199         }
5200
5201         trace_kvm_msr_read(ecx, data);
5202
5203         /* FIXME: handling of bits 32:63 of rax, rdx */
5204         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5205         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5206         skip_emulated_instruction(vcpu);
5207         return 1;
5208 }
5209
5210 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5211 {
5212         struct msr_data msr;
5213         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5214         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5215                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5216
5217         msr.data = data;
5218         msr.index = ecx;
5219         msr.host_initiated = false;
5220         if (vmx_set_msr(vcpu, &msr) != 0) {
5221                 trace_kvm_msr_write_ex(ecx, data);
5222                 kvm_inject_gp(vcpu, 0);
5223                 return 1;
5224         }
5225
5226         trace_kvm_msr_write(ecx, data);
5227         skip_emulated_instruction(vcpu);
5228         return 1;
5229 }
5230
5231 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5232 {
5233         kvm_make_request(KVM_REQ_EVENT, vcpu);
5234         return 1;
5235 }
5236
5237 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5238 {
5239         u32 cpu_based_vm_exec_control;
5240
5241         /* clear pending irq */
5242         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5243         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5244         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5245
5246         kvm_make_request(KVM_REQ_EVENT, vcpu);
5247
5248         ++vcpu->stat.irq_window_exits;
5249
5250         /*
5251          * If the user space waits to inject interrupts, exit as soon as
5252          * possible
5253          */
5254         if (!irqchip_in_kernel(vcpu->kvm) &&
5255             vcpu->run->request_interrupt_window &&
5256             !kvm_cpu_has_interrupt(vcpu)) {
5257                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5258                 return 0;
5259         }
5260         return 1;
5261 }
5262
5263 static int handle_halt(struct kvm_vcpu *vcpu)
5264 {
5265         skip_emulated_instruction(vcpu);
5266         return kvm_emulate_halt(vcpu);
5267 }
5268
5269 static int handle_vmcall(struct kvm_vcpu *vcpu)
5270 {
5271         skip_emulated_instruction(vcpu);
5272         kvm_emulate_hypercall(vcpu);
5273         return 1;
5274 }
5275
5276 static int handle_invd(struct kvm_vcpu *vcpu)
5277 {
5278         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5279 }
5280
5281 static int handle_invlpg(struct kvm_vcpu *vcpu)
5282 {
5283         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5284
5285         kvm_mmu_invlpg(vcpu, exit_qualification);
5286         skip_emulated_instruction(vcpu);
5287         return 1;
5288 }
5289
5290 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5291 {
5292         int err;
5293
5294         err = kvm_rdpmc(vcpu);
5295         kvm_complete_insn_gp(vcpu, err);
5296
5297         return 1;
5298 }
5299
5300 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5301 {
5302         skip_emulated_instruction(vcpu);
5303         kvm_emulate_wbinvd(vcpu);
5304         return 1;
5305 }
5306
5307 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5308 {
5309         u64 new_bv = kvm_read_edx_eax(vcpu);
5310         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5311
5312         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5313                 skip_emulated_instruction(vcpu);
5314         return 1;
5315 }
5316
5317 static int handle_apic_access(struct kvm_vcpu *vcpu)
5318 {
5319         if (likely(fasteoi)) {
5320                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5321                 int access_type, offset;
5322
5323                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5324                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5325                 /*
5326                  * Sane guest uses MOV to write EOI, with written value
5327                  * not cared. So make a short-circuit here by avoiding
5328                  * heavy instruction emulation.
5329                  */
5330                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5331                     (offset == APIC_EOI)) {
5332                         kvm_lapic_set_eoi(vcpu);
5333                         skip_emulated_instruction(vcpu);
5334                         return 1;
5335                 }
5336         }
5337         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5338 }
5339
5340 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5341 {
5342         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5343         int vector = exit_qualification & 0xff;
5344
5345         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5346         kvm_apic_set_eoi_accelerated(vcpu, vector);
5347         return 1;
5348 }
5349
5350 static int handle_apic_write(struct kvm_vcpu *vcpu)
5351 {
5352         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5353         u32 offset = exit_qualification & 0xfff;
5354
5355         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5356         kvm_apic_write_nodecode(vcpu, offset);
5357         return 1;
5358 }
5359
5360 static int handle_task_switch(struct kvm_vcpu *vcpu)
5361 {
5362         struct vcpu_vmx *vmx = to_vmx(vcpu);
5363         unsigned long exit_qualification;
5364         bool has_error_code = false;
5365         u32 error_code = 0;
5366         u16 tss_selector;
5367         int reason, type, idt_v, idt_index;
5368
5369         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5370         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5371         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5372
5373         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5374
5375         reason = (u32)exit_qualification >> 30;
5376         if (reason == TASK_SWITCH_GATE && idt_v) {
5377                 switch (type) {
5378                 case INTR_TYPE_NMI_INTR:
5379                         vcpu->arch.nmi_injected = false;
5380                         vmx_set_nmi_mask(vcpu, true);
5381                         break;
5382                 case INTR_TYPE_EXT_INTR:
5383                 case INTR_TYPE_SOFT_INTR:
5384                         kvm_clear_interrupt_queue(vcpu);
5385                         break;
5386                 case INTR_TYPE_HARD_EXCEPTION:
5387                         if (vmx->idt_vectoring_info &
5388                             VECTORING_INFO_DELIVER_CODE_MASK) {
5389                                 has_error_code = true;
5390                                 error_code =
5391                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5392                         }
5393                         /* fall through */
5394                 case INTR_TYPE_SOFT_EXCEPTION:
5395                         kvm_clear_exception_queue(vcpu);
5396                         break;
5397                 default:
5398                         break;
5399                 }
5400         }
5401         tss_selector = exit_qualification;
5402
5403         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5404                        type != INTR_TYPE_EXT_INTR &&
5405                        type != INTR_TYPE_NMI_INTR))
5406                 skip_emulated_instruction(vcpu);
5407
5408         if (kvm_task_switch(vcpu, tss_selector,
5409                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5410                             has_error_code, error_code) == EMULATE_FAIL) {
5411                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5412                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5413                 vcpu->run->internal.ndata = 0;
5414                 return 0;
5415         }
5416
5417         /* clear all local breakpoint enable flags */
5418         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5419
5420         /*
5421          * TODO: What about debug traps on tss switch?
5422          *       Are we supposed to inject them and update dr6?
5423          */
5424
5425         return 1;
5426 }
5427
5428 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5429 {
5430         unsigned long exit_qualification;
5431         gpa_t gpa;
5432         u32 error_code;
5433         int gla_validity;
5434
5435         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5436
5437         gla_validity = (exit_qualification >> 7) & 0x3;
5438         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5439                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5440                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5441                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5442                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5443                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5444                         (long unsigned int)exit_qualification);
5445                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5446                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5447                 return 0;
5448         }
5449
5450         /*
5451          * EPT violation happened while executing iret from NMI,
5452          * "blocked by NMI" bit has to be set before next VM entry.
5453          * There are errata that may cause this bit to not be set:
5454          * AAK134, BY25.
5455          */
5456         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5457                         cpu_has_virtual_nmis() &&
5458                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5459                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5460
5461         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5462         trace_kvm_page_fault(gpa, exit_qualification);
5463
5464         /* It is a write fault? */
5465         error_code = exit_qualification & (1U << 1);
5466         /* It is a fetch fault? */
5467         error_code |= (exit_qualification & (1U << 2)) << 2;
5468         /* ept page table is present? */
5469         error_code |= (exit_qualification >> 3) & 0x1;
5470
5471         vcpu->arch.exit_qualification = exit_qualification;
5472
5473         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5474 }
5475
5476 static u64 ept_rsvd_mask(u64 spte, int level)
5477 {
5478         int i;
5479         u64 mask = 0;
5480
5481         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5482                 mask |= (1ULL << i);
5483
5484         if (level > 2)
5485                 /* bits 7:3 reserved */
5486                 mask |= 0xf8;
5487         else if (level == 2) {
5488                 if (spte & (1ULL << 7))
5489                         /* 2MB ref, bits 20:12 reserved */
5490                         mask |= 0x1ff000;
5491                 else
5492                         /* bits 6:3 reserved */
5493                         mask |= 0x78;
5494         }
5495
5496         return mask;
5497 }
5498
5499 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5500                                        int level)
5501 {
5502         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5503
5504         /* 010b (write-only) */
5505         WARN_ON((spte & 0x7) == 0x2);
5506
5507         /* 110b (write/execute) */
5508         WARN_ON((spte & 0x7) == 0x6);
5509
5510         /* 100b (execute-only) and value not supported by logical processor */
5511         if (!cpu_has_vmx_ept_execute_only())
5512                 WARN_ON((spte & 0x7) == 0x4);
5513
5514         /* not 000b */
5515         if ((spte & 0x7)) {
5516                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5517
5518                 if (rsvd_bits != 0) {
5519                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5520                                          __func__, rsvd_bits);
5521                         WARN_ON(1);
5522                 }
5523
5524                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5525                         u64 ept_mem_type = (spte & 0x38) >> 3;
5526
5527                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5528                             ept_mem_type == 7) {
5529                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5530                                                 __func__, ept_mem_type);
5531                                 WARN_ON(1);
5532                         }
5533                 }
5534         }
5535 }
5536
5537 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5538 {
5539         u64 sptes[4];
5540         int nr_sptes, i, ret;
5541         gpa_t gpa;
5542
5543         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5544         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5545                 skip_emulated_instruction(vcpu);
5546                 return 1;
5547         }
5548
5549         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5550         if (likely(ret == RET_MMIO_PF_EMULATE))
5551                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5552                                               EMULATE_DONE;
5553
5554         if (unlikely(ret == RET_MMIO_PF_INVALID))
5555                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5556
5557         if (unlikely(ret == RET_MMIO_PF_RETRY))
5558                 return 1;
5559
5560         /* It is the real ept misconfig */
5561         printk(KERN_ERR "EPT: Misconfiguration.\n");
5562         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5563
5564         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5565
5566         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5567                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5568
5569         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5570         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5571
5572         return 0;
5573 }
5574
5575 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5576 {
5577         u32 cpu_based_vm_exec_control;
5578
5579         /* clear pending NMI */
5580         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5581         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5582         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5583         ++vcpu->stat.nmi_window_exits;
5584         kvm_make_request(KVM_REQ_EVENT, vcpu);
5585
5586         return 1;
5587 }
5588
5589 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5590 {
5591         struct vcpu_vmx *vmx = to_vmx(vcpu);
5592         enum emulation_result err = EMULATE_DONE;
5593         int ret = 1;
5594         u32 cpu_exec_ctrl;
5595         bool intr_window_requested;
5596         unsigned count = 130;
5597
5598         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5599         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5600
5601         while (!guest_state_valid(vcpu) && count-- != 0) {
5602                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5603                         return handle_interrupt_window(&vmx->vcpu);
5604
5605                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5606                         return 1;
5607
5608                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5609
5610                 if (err == EMULATE_USER_EXIT) {
5611                         ++vcpu->stat.mmio_exits;
5612                         ret = 0;
5613                         goto out;
5614                 }
5615
5616                 if (err != EMULATE_DONE) {
5617                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5618                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5619                         vcpu->run->internal.ndata = 0;
5620                         return 0;
5621                 }
5622
5623                 if (vcpu->arch.halt_request) {
5624                         vcpu->arch.halt_request = 0;
5625                         ret = kvm_emulate_halt(vcpu);
5626                         goto out;
5627                 }
5628
5629                 if (signal_pending(current))
5630                         goto out;
5631                 if (need_resched())
5632                         schedule();
5633         }
5634
5635         vmx->emulation_required = emulation_required(vcpu);
5636 out:
5637         return ret;
5638 }
5639
5640 /*
5641  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5642  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5643  */
5644 static int handle_pause(struct kvm_vcpu *vcpu)
5645 {
5646         skip_emulated_instruction(vcpu);
5647         kvm_vcpu_on_spin(vcpu);
5648
5649         return 1;
5650 }
5651
5652 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5653 {
5654         kvm_queue_exception(vcpu, UD_VECTOR);
5655         return 1;
5656 }
5657
5658 /*
5659  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5660  * We could reuse a single VMCS for all the L2 guests, but we also want the
5661  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5662  * allows keeping them loaded on the processor, and in the future will allow
5663  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5664  * every entry if they never change.
5665  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5666  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5667  *
5668  * The following functions allocate and free a vmcs02 in this pool.
5669  */
5670
5671 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5672 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5673 {
5674         struct vmcs02_list *item;
5675         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5676                 if (item->vmptr == vmx->nested.current_vmptr) {
5677                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5678                         return &item->vmcs02;
5679                 }
5680
5681         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5682                 /* Recycle the least recently used VMCS. */
5683                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5684                         struct vmcs02_list, list);
5685                 item->vmptr = vmx->nested.current_vmptr;
5686                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5687                 return &item->vmcs02;
5688         }
5689
5690         /* Create a new VMCS */
5691         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5692         if (!item)
5693                 return NULL;
5694         item->vmcs02.vmcs = alloc_vmcs();
5695         if (!item->vmcs02.vmcs) {
5696                 kfree(item);
5697                 return NULL;
5698         }
5699         loaded_vmcs_init(&item->vmcs02);
5700         item->vmptr = vmx->nested.current_vmptr;
5701         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5702         vmx->nested.vmcs02_num++;
5703         return &item->vmcs02;
5704 }
5705
5706 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5707 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5708 {
5709         struct vmcs02_list *item;
5710         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5711                 if (item->vmptr == vmptr) {
5712                         free_loaded_vmcs(&item->vmcs02);
5713                         list_del(&item->list);
5714                         kfree(item);
5715                         vmx->nested.vmcs02_num--;
5716                         return;
5717                 }
5718 }
5719
5720 /*
5721  * Free all VMCSs saved for this vcpu, except the one pointed by
5722  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5723  * currently used, if running L2), and vmcs01 when running L2.
5724  */
5725 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5726 {
5727         struct vmcs02_list *item, *n;
5728         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5729                 if (vmx->loaded_vmcs != &item->vmcs02)
5730                         free_loaded_vmcs(&item->vmcs02);
5731                 list_del(&item->list);
5732                 kfree(item);
5733         }
5734         vmx->nested.vmcs02_num = 0;
5735
5736         if (vmx->loaded_vmcs != &vmx->vmcs01)
5737                 free_loaded_vmcs(&vmx->vmcs01);
5738 }
5739
5740 /*
5741  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5742  * set the success or error code of an emulated VMX instruction, as specified
5743  * by Vol 2B, VMX Instruction Reference, "Conventions".
5744  */
5745 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5746 {
5747         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5748                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5749                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5750 }
5751
5752 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5753 {
5754         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5755                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5756                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5757                         | X86_EFLAGS_CF);
5758 }
5759
5760 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5761                                         u32 vm_instruction_error)
5762 {
5763         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5764                 /*
5765                  * failValid writes the error number to the current VMCS, which
5766                  * can't be done there isn't a current VMCS.
5767                  */
5768                 nested_vmx_failInvalid(vcpu);
5769                 return;
5770         }
5771         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5772                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5773                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5774                         | X86_EFLAGS_ZF);
5775         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5776         /*
5777          * We don't need to force a shadow sync because
5778          * VM_INSTRUCTION_ERROR is not shadowed
5779          */
5780 }
5781
5782 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5783 {
5784         struct vcpu_vmx *vmx =
5785                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5786
5787         vmx->nested.preemption_timer_expired = true;
5788         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5789         kvm_vcpu_kick(&vmx->vcpu);
5790
5791         return HRTIMER_NORESTART;
5792 }
5793
5794 /*
5795  * Emulate the VMXON instruction.
5796  * Currently, we just remember that VMX is active, and do not save or even
5797  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5798  * do not currently need to store anything in that guest-allocated memory
5799  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5800  * argument is different from the VMXON pointer (which the spec says they do).
5801  */
5802 static int handle_vmon(struct kvm_vcpu *vcpu)
5803 {
5804         struct kvm_segment cs;
5805         struct vcpu_vmx *vmx = to_vmx(vcpu);
5806         struct vmcs *shadow_vmcs;
5807         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5808                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5809
5810         /* The Intel VMX Instruction Reference lists a bunch of bits that
5811          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5812          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5813          * Otherwise, we should fail with #UD. We test these now:
5814          */
5815         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5816             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5817             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5818                 kvm_queue_exception(vcpu, UD_VECTOR);
5819                 return 1;
5820         }
5821
5822         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5823         if (is_long_mode(vcpu) && !cs.l) {
5824                 kvm_queue_exception(vcpu, UD_VECTOR);
5825                 return 1;
5826         }
5827
5828         if (vmx_get_cpl(vcpu)) {
5829                 kvm_inject_gp(vcpu, 0);
5830                 return 1;
5831         }
5832         if (vmx->nested.vmxon) {
5833                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5834                 skip_emulated_instruction(vcpu);
5835                 return 1;
5836         }
5837
5838         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5839                         != VMXON_NEEDED_FEATURES) {
5840                 kvm_inject_gp(vcpu, 0);
5841                 return 1;
5842         }
5843
5844         if (enable_shadow_vmcs) {
5845                 shadow_vmcs = alloc_vmcs();
5846                 if (!shadow_vmcs)
5847                         return -ENOMEM;
5848                 /* mark vmcs as shadow */
5849                 shadow_vmcs->revision_id |= (1u << 31);
5850                 /* init shadow vmcs */
5851                 vmcs_clear(shadow_vmcs);
5852                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5853         }
5854
5855         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5856         vmx->nested.vmcs02_num = 0;
5857
5858         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5859                      HRTIMER_MODE_REL);
5860         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5861
5862         vmx->nested.vmxon = true;
5863
5864         skip_emulated_instruction(vcpu);
5865         nested_vmx_succeed(vcpu);
5866         return 1;
5867 }
5868
5869 /*
5870  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5871  * for running VMX instructions (except VMXON, whose prerequisites are
5872  * slightly different). It also specifies what exception to inject otherwise.
5873  */
5874 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5875 {
5876         struct kvm_segment cs;
5877         struct vcpu_vmx *vmx = to_vmx(vcpu);
5878
5879         if (!vmx->nested.vmxon) {
5880                 kvm_queue_exception(vcpu, UD_VECTOR);
5881                 return 0;
5882         }
5883
5884         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5885         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5886             (is_long_mode(vcpu) && !cs.l)) {
5887                 kvm_queue_exception(vcpu, UD_VECTOR);
5888                 return 0;
5889         }
5890
5891         if (vmx_get_cpl(vcpu)) {
5892                 kvm_inject_gp(vcpu, 0);
5893                 return 0;
5894         }
5895
5896         return 1;
5897 }
5898
5899 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5900 {
5901         u32 exec_control;
5902         if (enable_shadow_vmcs) {
5903                 if (vmx->nested.current_vmcs12 != NULL) {
5904                         /* copy to memory all shadowed fields in case
5905                            they were modified */
5906                         copy_shadow_to_vmcs12(vmx);
5907                         vmx->nested.sync_shadow_vmcs = false;
5908                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5909                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5910                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5911                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5912                 }
5913         }
5914         kunmap(vmx->nested.current_vmcs12_page);
5915         nested_release_page(vmx->nested.current_vmcs12_page);
5916 }
5917
5918 /*
5919  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5920  * just stops using VMX.
5921  */
5922 static void free_nested(struct vcpu_vmx *vmx)
5923 {
5924         if (!vmx->nested.vmxon)
5925                 return;
5926         vmx->nested.vmxon = false;
5927         if (vmx->nested.current_vmptr != -1ull) {
5928                 nested_release_vmcs12(vmx);
5929                 vmx->nested.current_vmptr = -1ull;
5930                 vmx->nested.current_vmcs12 = NULL;
5931         }
5932         if (enable_shadow_vmcs)
5933                 free_vmcs(vmx->nested.current_shadow_vmcs);
5934         /* Unpin physical memory we referred to in current vmcs02 */
5935         if (vmx->nested.apic_access_page) {
5936                 nested_release_page(vmx->nested.apic_access_page);
5937                 vmx->nested.apic_access_page = 0;
5938         }
5939
5940         nested_free_all_saved_vmcss(vmx);
5941 }
5942
5943 /* Emulate the VMXOFF instruction */
5944 static int handle_vmoff(struct kvm_vcpu *vcpu)
5945 {
5946         if (!nested_vmx_check_permission(vcpu))
5947                 return 1;
5948         free_nested(to_vmx(vcpu));
5949         skip_emulated_instruction(vcpu);
5950         nested_vmx_succeed(vcpu);
5951         return 1;
5952 }
5953
5954 /*
5955  * Decode the memory-address operand of a vmx instruction, as recorded on an
5956  * exit caused by such an instruction (run by a guest hypervisor).
5957  * On success, returns 0. When the operand is invalid, returns 1 and throws
5958  * #UD or #GP.
5959  */
5960 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5961                                  unsigned long exit_qualification,
5962                                  u32 vmx_instruction_info, gva_t *ret)
5963 {
5964         /*
5965          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5966          * Execution", on an exit, vmx_instruction_info holds most of the
5967          * addressing components of the operand. Only the displacement part
5968          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5969          * For how an actual address is calculated from all these components,
5970          * refer to Vol. 1, "Operand Addressing".
5971          */
5972         int  scaling = vmx_instruction_info & 3;
5973         int  addr_size = (vmx_instruction_info >> 7) & 7;
5974         bool is_reg = vmx_instruction_info & (1u << 10);
5975         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5976         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5977         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5978         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5979         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5980
5981         if (is_reg) {
5982                 kvm_queue_exception(vcpu, UD_VECTOR);
5983                 return 1;
5984         }
5985
5986         /* Addr = segment_base + offset */
5987         /* offset = base + [index * scale] + displacement */
5988         *ret = vmx_get_segment_base(vcpu, seg_reg);
5989         if (base_is_valid)
5990                 *ret += kvm_register_read(vcpu, base_reg);
5991         if (index_is_valid)
5992                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5993         *ret += exit_qualification; /* holds the displacement */
5994
5995         if (addr_size == 1) /* 32 bit */
5996                 *ret &= 0xffffffff;
5997
5998         /*
5999          * TODO: throw #GP (and return 1) in various cases that the VM*
6000          * instructions require it - e.g., offset beyond segment limit,
6001          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6002          * address, and so on. Currently these are not checked.
6003          */
6004         return 0;
6005 }
6006
6007 /* Emulate the VMCLEAR instruction */
6008 static int handle_vmclear(struct kvm_vcpu *vcpu)
6009 {
6010         struct vcpu_vmx *vmx = to_vmx(vcpu);
6011         gva_t gva;
6012         gpa_t vmptr;
6013         struct vmcs12 *vmcs12;
6014         struct page *page;
6015         struct x86_exception e;
6016
6017         if (!nested_vmx_check_permission(vcpu))
6018                 return 1;
6019
6020         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6021                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6022                 return 1;
6023
6024         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6025                                 sizeof(vmptr), &e)) {
6026                 kvm_inject_page_fault(vcpu, &e);
6027                 return 1;
6028         }
6029
6030         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6031                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
6032                 skip_emulated_instruction(vcpu);
6033                 return 1;
6034         }
6035
6036         if (vmptr == vmx->nested.current_vmptr) {
6037                 nested_release_vmcs12(vmx);
6038                 vmx->nested.current_vmptr = -1ull;
6039                 vmx->nested.current_vmcs12 = NULL;
6040         }
6041
6042         page = nested_get_page(vcpu, vmptr);
6043         if (page == NULL) {
6044                 /*
6045                  * For accurate processor emulation, VMCLEAR beyond available
6046                  * physical memory should do nothing at all. However, it is
6047                  * possible that a nested vmx bug, not a guest hypervisor bug,
6048                  * resulted in this case, so let's shut down before doing any
6049                  * more damage:
6050                  */
6051                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6052                 return 1;
6053         }
6054         vmcs12 = kmap(page);
6055         vmcs12->launch_state = 0;
6056         kunmap(page);
6057         nested_release_page(page);
6058
6059         nested_free_vmcs02(vmx, vmptr);
6060
6061         skip_emulated_instruction(vcpu);
6062         nested_vmx_succeed(vcpu);
6063         return 1;
6064 }
6065
6066 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6067
6068 /* Emulate the VMLAUNCH instruction */
6069 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6070 {
6071         return nested_vmx_run(vcpu, true);
6072 }
6073
6074 /* Emulate the VMRESUME instruction */
6075 static int handle_vmresume(struct kvm_vcpu *vcpu)
6076 {
6077
6078         return nested_vmx_run(vcpu, false);
6079 }
6080
6081 enum vmcs_field_type {
6082         VMCS_FIELD_TYPE_U16 = 0,
6083         VMCS_FIELD_TYPE_U64 = 1,
6084         VMCS_FIELD_TYPE_U32 = 2,
6085         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6086 };
6087
6088 static inline int vmcs_field_type(unsigned long field)
6089 {
6090         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6091                 return VMCS_FIELD_TYPE_U32;
6092         return (field >> 13) & 0x3 ;
6093 }
6094
6095 static inline int vmcs_field_readonly(unsigned long field)
6096 {
6097         return (((field >> 10) & 0x3) == 1);
6098 }
6099
6100 /*
6101  * Read a vmcs12 field. Since these can have varying lengths and we return
6102  * one type, we chose the biggest type (u64) and zero-extend the return value
6103  * to that size. Note that the caller, handle_vmread, might need to use only
6104  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6105  * 64-bit fields are to be returned).
6106  */
6107 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6108                                         unsigned long field, u64 *ret)
6109 {
6110         short offset = vmcs_field_to_offset(field);
6111         char *p;
6112
6113         if (offset < 0)
6114                 return 0;
6115
6116         p = ((char *)(get_vmcs12(vcpu))) + offset;
6117
6118         switch (vmcs_field_type(field)) {
6119         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6120                 *ret = *((natural_width *)p);
6121                 return 1;
6122         case VMCS_FIELD_TYPE_U16:
6123                 *ret = *((u16 *)p);
6124                 return 1;
6125         case VMCS_FIELD_TYPE_U32:
6126                 *ret = *((u32 *)p);
6127                 return 1;
6128         case VMCS_FIELD_TYPE_U64:
6129                 *ret = *((u64 *)p);
6130                 return 1;
6131         default:
6132                 return 0; /* can never happen. */
6133         }
6134 }
6135
6136
6137 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6138                                     unsigned long field, u64 field_value){
6139         short offset = vmcs_field_to_offset(field);
6140         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6141         if (offset < 0)
6142                 return false;
6143
6144         switch (vmcs_field_type(field)) {
6145         case VMCS_FIELD_TYPE_U16:
6146                 *(u16 *)p = field_value;
6147                 return true;
6148         case VMCS_FIELD_TYPE_U32:
6149                 *(u32 *)p = field_value;
6150                 return true;
6151         case VMCS_FIELD_TYPE_U64:
6152                 *(u64 *)p = field_value;
6153                 return true;
6154         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6155                 *(natural_width *)p = field_value;
6156                 return true;
6157         default:
6158                 return false; /* can never happen. */
6159         }
6160
6161 }
6162
6163 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6164 {
6165         int i;
6166         unsigned long field;
6167         u64 field_value;
6168         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6169         const unsigned long *fields = shadow_read_write_fields;
6170         const int num_fields = max_shadow_read_write_fields;
6171
6172         vmcs_load(shadow_vmcs);
6173
6174         for (i = 0; i < num_fields; i++) {
6175                 field = fields[i];
6176                 switch (vmcs_field_type(field)) {
6177                 case VMCS_FIELD_TYPE_U16:
6178                         field_value = vmcs_read16(field);
6179                         break;
6180                 case VMCS_FIELD_TYPE_U32:
6181                         field_value = vmcs_read32(field);
6182                         break;
6183                 case VMCS_FIELD_TYPE_U64:
6184                         field_value = vmcs_read64(field);
6185                         break;
6186                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6187                         field_value = vmcs_readl(field);
6188                         break;
6189                 }
6190                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6191         }
6192
6193         vmcs_clear(shadow_vmcs);
6194         vmcs_load(vmx->loaded_vmcs->vmcs);
6195 }
6196
6197 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6198 {
6199         const unsigned long *fields[] = {
6200                 shadow_read_write_fields,
6201                 shadow_read_only_fields
6202         };
6203         const int max_fields[] = {
6204                 max_shadow_read_write_fields,
6205                 max_shadow_read_only_fields
6206         };
6207         int i, q;
6208         unsigned long field;
6209         u64 field_value = 0;
6210         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6211
6212         vmcs_load(shadow_vmcs);
6213
6214         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6215                 for (i = 0; i < max_fields[q]; i++) {
6216                         field = fields[q][i];
6217                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6218
6219                         switch (vmcs_field_type(field)) {
6220                         case VMCS_FIELD_TYPE_U16:
6221                                 vmcs_write16(field, (u16)field_value);
6222                                 break;
6223                         case VMCS_FIELD_TYPE_U32:
6224                                 vmcs_write32(field, (u32)field_value);
6225                                 break;
6226                         case VMCS_FIELD_TYPE_U64:
6227                                 vmcs_write64(field, (u64)field_value);
6228                                 break;
6229                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6230                                 vmcs_writel(field, (long)field_value);
6231                                 break;
6232                         }
6233                 }
6234         }
6235
6236         vmcs_clear(shadow_vmcs);
6237         vmcs_load(vmx->loaded_vmcs->vmcs);
6238 }
6239
6240 /*
6241  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6242  * used before) all generate the same failure when it is missing.
6243  */
6244 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6245 {
6246         struct vcpu_vmx *vmx = to_vmx(vcpu);
6247         if (vmx->nested.current_vmptr == -1ull) {
6248                 nested_vmx_failInvalid(vcpu);
6249                 skip_emulated_instruction(vcpu);
6250                 return 0;
6251         }
6252         return 1;
6253 }
6254
6255 static int handle_vmread(struct kvm_vcpu *vcpu)
6256 {
6257         unsigned long field;
6258         u64 field_value;
6259         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6260         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6261         gva_t gva = 0;
6262
6263         if (!nested_vmx_check_permission(vcpu) ||
6264             !nested_vmx_check_vmcs12(vcpu))
6265                 return 1;
6266
6267         /* Decode instruction info and find the field to read */
6268         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6269         /* Read the field, zero-extended to a u64 field_value */
6270         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6271                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6272                 skip_emulated_instruction(vcpu);
6273                 return 1;
6274         }
6275         /*
6276          * Now copy part of this value to register or memory, as requested.
6277          * Note that the number of bits actually copied is 32 or 64 depending
6278          * on the guest's mode (32 or 64 bit), not on the given field's length.
6279          */
6280         if (vmx_instruction_info & (1u << 10)) {
6281                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6282                         field_value);
6283         } else {
6284                 if (get_vmx_mem_address(vcpu, exit_qualification,
6285                                 vmx_instruction_info, &gva))
6286                         return 1;
6287                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6288                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6289                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6290         }
6291
6292         nested_vmx_succeed(vcpu);
6293         skip_emulated_instruction(vcpu);
6294         return 1;
6295 }
6296
6297
6298 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6299 {
6300         unsigned long field;
6301         gva_t gva;
6302         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6303         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6304         /* The value to write might be 32 or 64 bits, depending on L1's long
6305          * mode, and eventually we need to write that into a field of several
6306          * possible lengths. The code below first zero-extends the value to 64
6307          * bit (field_value), and then copies only the approriate number of
6308          * bits into the vmcs12 field.
6309          */
6310         u64 field_value = 0;
6311         struct x86_exception e;
6312
6313         if (!nested_vmx_check_permission(vcpu) ||
6314             !nested_vmx_check_vmcs12(vcpu))
6315                 return 1;
6316
6317         if (vmx_instruction_info & (1u << 10))
6318                 field_value = kvm_register_read(vcpu,
6319                         (((vmx_instruction_info) >> 3) & 0xf));
6320         else {
6321                 if (get_vmx_mem_address(vcpu, exit_qualification,
6322                                 vmx_instruction_info, &gva))
6323                         return 1;
6324                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6325                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6326                         kvm_inject_page_fault(vcpu, &e);
6327                         return 1;
6328                 }
6329         }
6330
6331
6332         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6333         if (vmcs_field_readonly(field)) {
6334                 nested_vmx_failValid(vcpu,
6335                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6336                 skip_emulated_instruction(vcpu);
6337                 return 1;
6338         }
6339
6340         if (!vmcs12_write_any(vcpu, field, field_value)) {
6341                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6342                 skip_emulated_instruction(vcpu);
6343                 return 1;
6344         }
6345
6346         nested_vmx_succeed(vcpu);
6347         skip_emulated_instruction(vcpu);
6348         return 1;
6349 }
6350
6351 /* Emulate the VMPTRLD instruction */
6352 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6353 {
6354         struct vcpu_vmx *vmx = to_vmx(vcpu);
6355         gva_t gva;
6356         gpa_t vmptr;
6357         struct x86_exception e;
6358         u32 exec_control;
6359
6360         if (!nested_vmx_check_permission(vcpu))
6361                 return 1;
6362
6363         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6364                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6365                 return 1;
6366
6367         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6368                                 sizeof(vmptr), &e)) {
6369                 kvm_inject_page_fault(vcpu, &e);
6370                 return 1;
6371         }
6372
6373         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6374                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6375                 skip_emulated_instruction(vcpu);
6376                 return 1;
6377         }
6378
6379         if (vmx->nested.current_vmptr != vmptr) {
6380                 struct vmcs12 *new_vmcs12;
6381                 struct page *page;
6382                 page = nested_get_page(vcpu, vmptr);
6383                 if (page == NULL) {
6384                         nested_vmx_failInvalid(vcpu);
6385                         skip_emulated_instruction(vcpu);
6386                         return 1;
6387                 }
6388                 new_vmcs12 = kmap(page);
6389                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6390                         kunmap(page);
6391                         nested_release_page_clean(page);
6392                         nested_vmx_failValid(vcpu,
6393                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6394                         skip_emulated_instruction(vcpu);
6395                         return 1;
6396                 }
6397                 if (vmx->nested.current_vmptr != -1ull)
6398                         nested_release_vmcs12(vmx);
6399
6400                 vmx->nested.current_vmptr = vmptr;
6401                 vmx->nested.current_vmcs12 = new_vmcs12;
6402                 vmx->nested.current_vmcs12_page = page;
6403                 if (enable_shadow_vmcs) {
6404                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6405                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6406                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6407                         vmcs_write64(VMCS_LINK_POINTER,
6408                                      __pa(vmx->nested.current_shadow_vmcs));
6409                         vmx->nested.sync_shadow_vmcs = true;
6410                 }
6411         }
6412
6413         nested_vmx_succeed(vcpu);
6414         skip_emulated_instruction(vcpu);
6415         return 1;
6416 }
6417
6418 /* Emulate the VMPTRST instruction */
6419 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6420 {
6421         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6422         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6423         gva_t vmcs_gva;
6424         struct x86_exception e;
6425
6426         if (!nested_vmx_check_permission(vcpu))
6427                 return 1;
6428
6429         if (get_vmx_mem_address(vcpu, exit_qualification,
6430                         vmx_instruction_info, &vmcs_gva))
6431                 return 1;
6432         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6433         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6434                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6435                                  sizeof(u64), &e)) {
6436                 kvm_inject_page_fault(vcpu, &e);
6437                 return 1;
6438         }
6439         nested_vmx_succeed(vcpu);
6440         skip_emulated_instruction(vcpu);
6441         return 1;
6442 }
6443
6444 /* Emulate the INVEPT instruction */
6445 static int handle_invept(struct kvm_vcpu *vcpu)
6446 {
6447         u32 vmx_instruction_info, types;
6448         unsigned long type;
6449         gva_t gva;
6450         struct x86_exception e;
6451         struct {
6452                 u64 eptp, gpa;
6453         } operand;
6454
6455         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6456             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6457                 kvm_queue_exception(vcpu, UD_VECTOR);
6458                 return 1;
6459         }
6460
6461         if (!nested_vmx_check_permission(vcpu))
6462                 return 1;
6463
6464         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6465                 kvm_queue_exception(vcpu, UD_VECTOR);
6466                 return 1;
6467         }
6468
6469         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6470         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6471
6472         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6473
6474         if (!(types & (1UL << type))) {
6475                 nested_vmx_failValid(vcpu,
6476                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6477                 return 1;
6478         }
6479
6480         /* According to the Intel VMX instruction reference, the memory
6481          * operand is read even if it isn't needed (e.g., for type==global)
6482          */
6483         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6484                         vmx_instruction_info, &gva))
6485                 return 1;
6486         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6487                                 sizeof(operand), &e)) {
6488                 kvm_inject_page_fault(vcpu, &e);
6489                 return 1;
6490         }
6491
6492         switch (type) {
6493         case VMX_EPT_EXTENT_GLOBAL:
6494                 kvm_mmu_sync_roots(vcpu);
6495                 kvm_mmu_flush_tlb(vcpu);
6496                 nested_vmx_succeed(vcpu);
6497                 break;
6498         default:
6499                 /* Trap single context invalidation invept calls */
6500                 BUG_ON(1);
6501                 break;
6502         }
6503
6504         skip_emulated_instruction(vcpu);
6505         return 1;
6506 }
6507
6508 /*
6509  * The exit handlers return 1 if the exit was handled fully and guest execution
6510  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6511  * to be done to userspace and return 0.
6512  */
6513 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6514         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6515         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6516         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6517         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6518         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6519         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6520         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6521         [EXIT_REASON_CPUID]                   = handle_cpuid,
6522         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6523         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6524         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6525         [EXIT_REASON_HLT]                     = handle_halt,
6526         [EXIT_REASON_INVD]                    = handle_invd,
6527         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6528         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6529         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6530         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6531         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6532         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6533         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6534         [EXIT_REASON_VMREAD]                  = handle_vmread,
6535         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6536         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6537         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6538         [EXIT_REASON_VMON]                    = handle_vmon,
6539         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6540         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6541         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6542         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6543         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6544         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6545         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6546         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6547         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6548         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6549         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6550         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6551         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6552         [EXIT_REASON_INVEPT]                  = handle_invept,
6553 };
6554
6555 static const int kvm_vmx_max_exit_handlers =
6556         ARRAY_SIZE(kvm_vmx_exit_handlers);
6557
6558 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6559                                        struct vmcs12 *vmcs12)
6560 {
6561         unsigned long exit_qualification;
6562         gpa_t bitmap, last_bitmap;
6563         unsigned int port;
6564         int size;
6565         u8 b;
6566
6567         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6568                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6569
6570         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6571
6572         port = exit_qualification >> 16;
6573         size = (exit_qualification & 7) + 1;
6574
6575         last_bitmap = (gpa_t)-1;
6576         b = -1;
6577
6578         while (size > 0) {
6579                 if (port < 0x8000)
6580                         bitmap = vmcs12->io_bitmap_a;
6581                 else if (port < 0x10000)
6582                         bitmap = vmcs12->io_bitmap_b;
6583                 else
6584                         return 1;
6585                 bitmap += (port & 0x7fff) / 8;
6586
6587                 if (last_bitmap != bitmap)
6588                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6589                                 return 1;
6590                 if (b & (1 << (port & 7)))
6591                         return 1;
6592
6593                 port++;
6594                 size--;
6595                 last_bitmap = bitmap;
6596         }
6597
6598         return 0;
6599 }
6600
6601 /*
6602  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6603  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6604  * disinterest in the current event (read or write a specific MSR) by using an
6605  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6606  */
6607 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6608         struct vmcs12 *vmcs12, u32 exit_reason)
6609 {
6610         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6611         gpa_t bitmap;
6612
6613         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6614                 return 1;
6615
6616         /*
6617          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6618          * for the four combinations of read/write and low/high MSR numbers.
6619          * First we need to figure out which of the four to use:
6620          */
6621         bitmap = vmcs12->msr_bitmap;
6622         if (exit_reason == EXIT_REASON_MSR_WRITE)
6623                 bitmap += 2048;
6624         if (msr_index >= 0xc0000000) {
6625                 msr_index -= 0xc0000000;
6626                 bitmap += 1024;
6627         }
6628
6629         /* Then read the msr_index'th bit from this bitmap: */
6630         if (msr_index < 1024*8) {
6631                 unsigned char b;
6632                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6633                         return 1;
6634                 return 1 & (b >> (msr_index & 7));
6635         } else
6636                 return 1; /* let L1 handle the wrong parameter */
6637 }
6638
6639 /*
6640  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6641  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6642  * intercept (via guest_host_mask etc.) the current event.
6643  */
6644 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6645         struct vmcs12 *vmcs12)
6646 {
6647         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6648         int cr = exit_qualification & 15;
6649         int reg = (exit_qualification >> 8) & 15;
6650         unsigned long val = kvm_register_read(vcpu, reg);
6651
6652         switch ((exit_qualification >> 4) & 3) {
6653         case 0: /* mov to cr */
6654                 switch (cr) {
6655                 case 0:
6656                         if (vmcs12->cr0_guest_host_mask &
6657                             (val ^ vmcs12->cr0_read_shadow))
6658                                 return 1;
6659                         break;
6660                 case 3:
6661                         if ((vmcs12->cr3_target_count >= 1 &&
6662                                         vmcs12->cr3_target_value0 == val) ||
6663                                 (vmcs12->cr3_target_count >= 2 &&
6664                                         vmcs12->cr3_target_value1 == val) ||
6665                                 (vmcs12->cr3_target_count >= 3 &&
6666                                         vmcs12->cr3_target_value2 == val) ||
6667                                 (vmcs12->cr3_target_count >= 4 &&
6668                                         vmcs12->cr3_target_value3 == val))
6669                                 return 0;
6670                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6671                                 return 1;
6672                         break;
6673                 case 4:
6674                         if (vmcs12->cr4_guest_host_mask &
6675                             (vmcs12->cr4_read_shadow ^ val))
6676                                 return 1;
6677                         break;
6678                 case 8:
6679                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6680                                 return 1;
6681                         break;
6682                 }
6683                 break;
6684         case 2: /* clts */
6685                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6686                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6687                         return 1;
6688                 break;
6689         case 1: /* mov from cr */
6690                 switch (cr) {
6691                 case 3:
6692                         if (vmcs12->cpu_based_vm_exec_control &
6693                             CPU_BASED_CR3_STORE_EXITING)
6694                                 return 1;
6695                         break;
6696                 case 8:
6697                         if (vmcs12->cpu_based_vm_exec_control &
6698                             CPU_BASED_CR8_STORE_EXITING)
6699                                 return 1;
6700                         break;
6701                 }
6702                 break;
6703         case 3: /* lmsw */
6704                 /*
6705                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6706                  * cr0. Other attempted changes are ignored, with no exit.
6707                  */
6708                 if (vmcs12->cr0_guest_host_mask & 0xe &
6709                     (val ^ vmcs12->cr0_read_shadow))
6710                         return 1;
6711                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6712                     !(vmcs12->cr0_read_shadow & 0x1) &&
6713                     (val & 0x1))
6714                         return 1;
6715                 break;
6716         }
6717         return 0;
6718 }
6719
6720 /*
6721  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6722  * should handle it ourselves in L0 (and then continue L2). Only call this
6723  * when in is_guest_mode (L2).
6724  */
6725 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6726 {
6727         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6728         struct vcpu_vmx *vmx = to_vmx(vcpu);
6729         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6730         u32 exit_reason = vmx->exit_reason;
6731
6732         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6733                                 vmcs_readl(EXIT_QUALIFICATION),
6734                                 vmx->idt_vectoring_info,
6735                                 intr_info,
6736                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6737                                 KVM_ISA_VMX);
6738
6739         if (vmx->nested.nested_run_pending)
6740                 return 0;
6741
6742         if (unlikely(vmx->fail)) {
6743                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6744                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6745                 return 1;
6746         }
6747
6748         switch (exit_reason) {
6749         case EXIT_REASON_EXCEPTION_NMI:
6750                 if (!is_exception(intr_info))
6751                         return 0;
6752                 else if (is_page_fault(intr_info))
6753                         return enable_ept;
6754                 else if (is_no_device(intr_info) &&
6755                          !(vmcs12->guest_cr0 & X86_CR0_TS))
6756                         return 0;
6757                 return vmcs12->exception_bitmap &
6758                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6759         case EXIT_REASON_EXTERNAL_INTERRUPT:
6760                 return 0;
6761         case EXIT_REASON_TRIPLE_FAULT:
6762                 return 1;
6763         case EXIT_REASON_PENDING_INTERRUPT:
6764                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6765         case EXIT_REASON_NMI_WINDOW:
6766                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6767         case EXIT_REASON_TASK_SWITCH:
6768                 return 1;
6769         case EXIT_REASON_CPUID:
6770                 return 1;
6771         case EXIT_REASON_HLT:
6772                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6773         case EXIT_REASON_INVD:
6774                 return 1;
6775         case EXIT_REASON_INVLPG:
6776                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6777         case EXIT_REASON_RDPMC:
6778                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6779         case EXIT_REASON_RDTSC:
6780                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6781         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6782         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6783         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6784         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6785         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6786         case EXIT_REASON_INVEPT:
6787                 /*
6788                  * VMX instructions trap unconditionally. This allows L1 to
6789                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6790                  */
6791                 return 1;
6792         case EXIT_REASON_CR_ACCESS:
6793                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6794         case EXIT_REASON_DR_ACCESS:
6795                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6796         case EXIT_REASON_IO_INSTRUCTION:
6797                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6798         case EXIT_REASON_MSR_READ:
6799         case EXIT_REASON_MSR_WRITE:
6800                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6801         case EXIT_REASON_INVALID_STATE:
6802                 return 1;
6803         case EXIT_REASON_MWAIT_INSTRUCTION:
6804                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6805         case EXIT_REASON_MONITOR_INSTRUCTION:
6806                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6807         case EXIT_REASON_PAUSE_INSTRUCTION:
6808                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6809                         nested_cpu_has2(vmcs12,
6810                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6811         case EXIT_REASON_MCE_DURING_VMENTRY:
6812                 return 0;
6813         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6814                 return 1;
6815         case EXIT_REASON_APIC_ACCESS:
6816                 return nested_cpu_has2(vmcs12,
6817                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6818         case EXIT_REASON_EPT_VIOLATION:
6819                 /*
6820                  * L0 always deals with the EPT violation. If nested EPT is
6821                  * used, and the nested mmu code discovers that the address is
6822                  * missing in the guest EPT table (EPT12), the EPT violation
6823                  * will be injected with nested_ept_inject_page_fault()
6824                  */
6825                 return 0;
6826         case EXIT_REASON_EPT_MISCONFIG:
6827                 /*
6828                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6829                  * table (shadow on EPT) or a merged EPT table that L0 built
6830                  * (EPT on EPT). So any problems with the structure of the
6831                  * table is L0's fault.
6832                  */
6833                 return 0;
6834         case EXIT_REASON_WBINVD:
6835                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6836         case EXIT_REASON_XSETBV:
6837                 return 1;
6838         default:
6839                 return 1;
6840         }
6841 }
6842
6843 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6844 {
6845         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6846         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6847 }
6848
6849 /*
6850  * The guest has exited.  See if we can fix it or if we need userspace
6851  * assistance.
6852  */
6853 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6854 {
6855         struct vcpu_vmx *vmx = to_vmx(vcpu);
6856         u32 exit_reason = vmx->exit_reason;
6857         u32 vectoring_info = vmx->idt_vectoring_info;
6858
6859         /* If guest state is invalid, start emulating */
6860         if (vmx->emulation_required)
6861                 return handle_invalid_guest_state(vcpu);
6862
6863         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6864                 nested_vmx_vmexit(vcpu, exit_reason,
6865                                   vmcs_read32(VM_EXIT_INTR_INFO),
6866                                   vmcs_readl(EXIT_QUALIFICATION));
6867                 return 1;
6868         }
6869
6870         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6871                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6872                 vcpu->run->fail_entry.hardware_entry_failure_reason
6873                         = exit_reason;
6874                 return 0;
6875         }
6876
6877         if (unlikely(vmx->fail)) {
6878                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6879                 vcpu->run->fail_entry.hardware_entry_failure_reason
6880                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6881                 return 0;
6882         }
6883
6884         /*
6885          * Note:
6886          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6887          * delivery event since it indicates guest is accessing MMIO.
6888          * The vm-exit can be triggered again after return to guest that
6889          * will cause infinite loop.
6890          */
6891         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6892                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6893                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6894                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6895                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6896                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6897                 vcpu->run->internal.ndata = 2;
6898                 vcpu->run->internal.data[0] = vectoring_info;
6899                 vcpu->run->internal.data[1] = exit_reason;
6900                 return 0;
6901         }
6902
6903         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6904             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6905                                         get_vmcs12(vcpu))))) {
6906                 if (vmx_interrupt_allowed(vcpu)) {
6907                         vmx->soft_vnmi_blocked = 0;
6908                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6909                            vcpu->arch.nmi_pending) {
6910                         /*
6911                          * This CPU don't support us in finding the end of an
6912                          * NMI-blocked window if the guest runs with IRQs
6913                          * disabled. So we pull the trigger after 1 s of
6914                          * futile waiting, but inform the user about this.
6915                          */
6916                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6917                                "state on VCPU %d after 1 s timeout\n",
6918                                __func__, vcpu->vcpu_id);
6919                         vmx->soft_vnmi_blocked = 0;
6920                 }
6921         }
6922
6923         if (exit_reason < kvm_vmx_max_exit_handlers
6924             && kvm_vmx_exit_handlers[exit_reason])
6925                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6926         else {
6927                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6928                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6929         }
6930         return 0;
6931 }
6932
6933 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6934 {
6935         if (irr == -1 || tpr < irr) {
6936                 vmcs_write32(TPR_THRESHOLD, 0);
6937                 return;
6938         }
6939
6940         vmcs_write32(TPR_THRESHOLD, irr);
6941 }
6942
6943 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6944 {
6945         u32 sec_exec_control;
6946
6947         /*
6948          * There is not point to enable virtualize x2apic without enable
6949          * apicv
6950          */
6951         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6952                                 !vmx_vm_has_apicv(vcpu->kvm))
6953                 return;
6954
6955         if (!vm_need_tpr_shadow(vcpu->kvm))
6956                 return;
6957
6958         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6959
6960         if (set) {
6961                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6962                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6963         } else {
6964                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6965                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6966         }
6967         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6968
6969         vmx_set_msr_bitmap(vcpu);
6970 }
6971
6972 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6973 {
6974         u16 status;
6975         u8 old;
6976
6977         if (!vmx_vm_has_apicv(kvm))
6978                 return;
6979
6980         if (isr == -1)
6981                 isr = 0;
6982
6983         status = vmcs_read16(GUEST_INTR_STATUS);
6984         old = status >> 8;
6985         if (isr != old) {
6986                 status &= 0xff;
6987                 status |= isr << 8;
6988                 vmcs_write16(GUEST_INTR_STATUS, status);
6989         }
6990 }
6991
6992 static void vmx_set_rvi(int vector)
6993 {
6994         u16 status;
6995         u8 old;
6996
6997         status = vmcs_read16(GUEST_INTR_STATUS);
6998         old = (u8)status & 0xff;
6999         if ((u8)vector != old) {
7000                 status &= ~0xff;
7001                 status |= (u8)vector;
7002                 vmcs_write16(GUEST_INTR_STATUS, status);
7003         }
7004 }
7005
7006 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7007 {
7008         if (max_irr == -1)
7009                 return;
7010
7011         vmx_set_rvi(max_irr);
7012 }
7013
7014 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7015 {
7016         if (!vmx_vm_has_apicv(vcpu->kvm))
7017                 return;
7018
7019         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7020         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7021         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7022         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7023 }
7024
7025 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7026 {
7027         u32 exit_intr_info;
7028
7029         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7030               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7031                 return;
7032
7033         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7034         exit_intr_info = vmx->exit_intr_info;
7035
7036         /* Handle machine checks before interrupts are enabled */
7037         if (is_machine_check(exit_intr_info))
7038                 kvm_machine_check();
7039
7040         /* We need to handle NMIs before interrupts are enabled */
7041         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7042             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7043                 kvm_before_handle_nmi(&vmx->vcpu);
7044                 asm("int $2");
7045                 kvm_after_handle_nmi(&vmx->vcpu);
7046         }
7047 }
7048
7049 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7050 {
7051         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7052
7053         /*
7054          * If external interrupt exists, IF bit is set in rflags/eflags on the
7055          * interrupt stack frame, and interrupt will be enabled on a return
7056          * from interrupt handler.
7057          */
7058         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7059                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7060                 unsigned int vector;
7061                 unsigned long entry;
7062                 gate_desc *desc;
7063                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7064 #ifdef CONFIG_X86_64
7065                 unsigned long tmp;
7066 #endif
7067
7068                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7069                 desc = (gate_desc *)vmx->host_idt_base + vector;
7070                 entry = gate_offset(*desc);
7071                 asm volatile(
7072 #ifdef CONFIG_X86_64
7073                         "mov %%" _ASM_SP ", %[sp]\n\t"
7074                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7075                         "push $%c[ss]\n\t"
7076                         "push %[sp]\n\t"
7077 #endif
7078                         "pushf\n\t"
7079                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7080                         __ASM_SIZE(push) " $%c[cs]\n\t"
7081                         "call *%[entry]\n\t"
7082                         :
7083 #ifdef CONFIG_X86_64
7084                         [sp]"=&r"(tmp)
7085 #endif
7086                         :
7087                         [entry]"r"(entry),
7088                         [ss]"i"(__KERNEL_DS),
7089                         [cs]"i"(__KERNEL_CS)
7090                         );
7091         } else
7092                 local_irq_enable();
7093 }
7094
7095 static bool vmx_mpx_supported(void)
7096 {
7097         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7098                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7099 }
7100
7101 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7102 {
7103         u32 exit_intr_info;
7104         bool unblock_nmi;
7105         u8 vector;
7106         bool idtv_info_valid;
7107
7108         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7109
7110         if (cpu_has_virtual_nmis()) {
7111                 if (vmx->nmi_known_unmasked)
7112                         return;
7113                 /*
7114                  * Can't use vmx->exit_intr_info since we're not sure what
7115                  * the exit reason is.
7116                  */
7117                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7118                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7119                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7120                 /*
7121                  * SDM 3: 27.7.1.2 (September 2008)
7122                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7123                  * a guest IRET fault.
7124                  * SDM 3: 23.2.2 (September 2008)
7125                  * Bit 12 is undefined in any of the following cases:
7126                  *  If the VM exit sets the valid bit in the IDT-vectoring
7127                  *   information field.
7128                  *  If the VM exit is due to a double fault.
7129                  */
7130                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7131                     vector != DF_VECTOR && !idtv_info_valid)
7132                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7133                                       GUEST_INTR_STATE_NMI);
7134                 else
7135                         vmx->nmi_known_unmasked =
7136                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7137                                   & GUEST_INTR_STATE_NMI);
7138         } else if (unlikely(vmx->soft_vnmi_blocked))
7139                 vmx->vnmi_blocked_time +=
7140                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7141 }
7142
7143 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7144                                       u32 idt_vectoring_info,
7145                                       int instr_len_field,
7146                                       int error_code_field)
7147 {
7148         u8 vector;
7149         int type;
7150         bool idtv_info_valid;
7151
7152         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7153
7154         vcpu->arch.nmi_injected = false;
7155         kvm_clear_exception_queue(vcpu);
7156         kvm_clear_interrupt_queue(vcpu);
7157
7158         if (!idtv_info_valid)
7159                 return;
7160
7161         kvm_make_request(KVM_REQ_EVENT, vcpu);
7162
7163         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7164         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7165
7166         switch (type) {
7167         case INTR_TYPE_NMI_INTR:
7168                 vcpu->arch.nmi_injected = true;
7169                 /*
7170                  * SDM 3: 27.7.1.2 (September 2008)
7171                  * Clear bit "block by NMI" before VM entry if a NMI
7172                  * delivery faulted.
7173                  */
7174                 vmx_set_nmi_mask(vcpu, false);
7175                 break;
7176         case INTR_TYPE_SOFT_EXCEPTION:
7177                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7178                 /* fall through */
7179         case INTR_TYPE_HARD_EXCEPTION:
7180                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7181                         u32 err = vmcs_read32(error_code_field);
7182                         kvm_requeue_exception_e(vcpu, vector, err);
7183                 } else
7184                         kvm_requeue_exception(vcpu, vector);
7185                 break;
7186         case INTR_TYPE_SOFT_INTR:
7187                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7188                 /* fall through */
7189         case INTR_TYPE_EXT_INTR:
7190                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7191                 break;
7192         default:
7193                 break;
7194         }
7195 }
7196
7197 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7198 {
7199         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7200                                   VM_EXIT_INSTRUCTION_LEN,
7201                                   IDT_VECTORING_ERROR_CODE);
7202 }
7203
7204 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7205 {
7206         __vmx_complete_interrupts(vcpu,
7207                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7208                                   VM_ENTRY_INSTRUCTION_LEN,
7209                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7210
7211         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7212 }
7213
7214 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7215 {
7216         int i, nr_msrs;
7217         struct perf_guest_switch_msr *msrs;
7218
7219         msrs = perf_guest_get_msrs(&nr_msrs);
7220
7221         if (!msrs)
7222                 return;
7223
7224         for (i = 0; i < nr_msrs; i++)
7225                 if (msrs[i].host == msrs[i].guest)
7226                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7227                 else
7228                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7229                                         msrs[i].host);
7230 }
7231
7232 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7233 {
7234         struct vcpu_vmx *vmx = to_vmx(vcpu);
7235         unsigned long debugctlmsr;
7236
7237         /* Record the guest's net vcpu time for enforced NMI injections. */
7238         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7239                 vmx->entry_time = ktime_get();
7240
7241         /* Don't enter VMX if guest state is invalid, let the exit handler
7242            start emulation until we arrive back to a valid state */
7243         if (vmx->emulation_required)
7244                 return;
7245
7246         if (vmx->nested.sync_shadow_vmcs) {
7247                 copy_vmcs12_to_shadow(vmx);
7248                 vmx->nested.sync_shadow_vmcs = false;
7249         }
7250
7251         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7252                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7253         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7254                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7255
7256         /* When single-stepping over STI and MOV SS, we must clear the
7257          * corresponding interruptibility bits in the guest state. Otherwise
7258          * vmentry fails as it then expects bit 14 (BS) in pending debug
7259          * exceptions being set, but that's not correct for the guest debugging
7260          * case. */
7261         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7262                 vmx_set_interrupt_shadow(vcpu, 0);
7263
7264         atomic_switch_perf_msrs(vmx);
7265         debugctlmsr = get_debugctlmsr();
7266
7267         vmx->__launched = vmx->loaded_vmcs->launched;
7268         asm(
7269                 /* Store host registers */
7270                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7271                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7272                 "push %%" _ASM_CX " \n\t"
7273                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7274                 "je 1f \n\t"
7275                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7276                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7277                 "1: \n\t"
7278                 /* Reload cr2 if changed */
7279                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7280                 "mov %%cr2, %%" _ASM_DX " \n\t"
7281                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7282                 "je 2f \n\t"
7283                 "mov %%" _ASM_AX", %%cr2 \n\t"
7284                 "2: \n\t"
7285                 /* Check if vmlaunch of vmresume is needed */
7286                 "cmpl $0, %c[launched](%0) \n\t"
7287                 /* Load guest registers.  Don't clobber flags. */
7288                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7289                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7290                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7291                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7292                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7293                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7294 #ifdef CONFIG_X86_64
7295                 "mov %c[r8](%0),  %%r8  \n\t"
7296                 "mov %c[r9](%0),  %%r9  \n\t"
7297                 "mov %c[r10](%0), %%r10 \n\t"
7298                 "mov %c[r11](%0), %%r11 \n\t"
7299                 "mov %c[r12](%0), %%r12 \n\t"
7300                 "mov %c[r13](%0), %%r13 \n\t"
7301                 "mov %c[r14](%0), %%r14 \n\t"
7302                 "mov %c[r15](%0), %%r15 \n\t"
7303 #endif
7304                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7305
7306                 /* Enter guest mode */
7307                 "jne 1f \n\t"
7308                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7309                 "jmp 2f \n\t"
7310                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7311                 "2: "
7312                 /* Save guest registers, load host registers, keep flags */
7313                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7314                 "pop %0 \n\t"
7315                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7316                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7317                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7318                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7319                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7320                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7321                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7322 #ifdef CONFIG_X86_64
7323                 "mov %%r8,  %c[r8](%0) \n\t"
7324                 "mov %%r9,  %c[r9](%0) \n\t"
7325                 "mov %%r10, %c[r10](%0) \n\t"
7326                 "mov %%r11, %c[r11](%0) \n\t"
7327                 "mov %%r12, %c[r12](%0) \n\t"
7328                 "mov %%r13, %c[r13](%0) \n\t"
7329                 "mov %%r14, %c[r14](%0) \n\t"
7330                 "mov %%r15, %c[r15](%0) \n\t"
7331 #endif
7332                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7333                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7334
7335                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7336                 "setbe %c[fail](%0) \n\t"
7337                 ".pushsection .rodata \n\t"
7338                 ".global vmx_return \n\t"
7339                 "vmx_return: " _ASM_PTR " 2b \n\t"
7340                 ".popsection"
7341               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7342                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7343                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7344                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7345                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7346                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7347                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7348                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7349                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7350                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7351                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7352 #ifdef CONFIG_X86_64
7353                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7354                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7355                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7356                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7357                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7358                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7359                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7360                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7361 #endif
7362                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7363                 [wordsize]"i"(sizeof(ulong))
7364               : "cc", "memory"
7365 #ifdef CONFIG_X86_64
7366                 , "rax", "rbx", "rdi", "rsi"
7367                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7368 #else
7369                 , "eax", "ebx", "edi", "esi"
7370 #endif
7371               );
7372
7373         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7374         if (debugctlmsr)
7375                 update_debugctlmsr(debugctlmsr);
7376
7377 #ifndef CONFIG_X86_64
7378         /*
7379          * The sysexit path does not restore ds/es, so we must set them to
7380          * a reasonable value ourselves.
7381          *
7382          * We can't defer this to vmx_load_host_state() since that function
7383          * may be executed in interrupt context, which saves and restore segments
7384          * around it, nullifying its effect.
7385          */
7386         loadsegment(ds, __USER_DS);
7387         loadsegment(es, __USER_DS);
7388 #endif
7389
7390         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7391                                   | (1 << VCPU_EXREG_RFLAGS)
7392                                   | (1 << VCPU_EXREG_CPL)
7393                                   | (1 << VCPU_EXREG_PDPTR)
7394                                   | (1 << VCPU_EXREG_SEGMENTS)
7395                                   | (1 << VCPU_EXREG_CR3));
7396         vcpu->arch.regs_dirty = 0;
7397
7398         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7399
7400         vmx->loaded_vmcs->launched = 1;
7401
7402         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7403         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7404
7405         /*
7406          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7407          * we did not inject a still-pending event to L1 now because of
7408          * nested_run_pending, we need to re-enable this bit.
7409          */
7410         if (vmx->nested.nested_run_pending)
7411                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7412
7413         vmx->nested.nested_run_pending = 0;
7414
7415         vmx_complete_atomic_exit(vmx);
7416         vmx_recover_nmi_blocking(vmx);
7417         vmx_complete_interrupts(vmx);
7418 }
7419
7420 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7421 {
7422         struct vcpu_vmx *vmx = to_vmx(vcpu);
7423
7424         free_vpid(vmx);
7425         free_loaded_vmcs(vmx->loaded_vmcs);
7426         free_nested(vmx);
7427         kfree(vmx->guest_msrs);
7428         kvm_vcpu_uninit(vcpu);
7429         kmem_cache_free(kvm_vcpu_cache, vmx);
7430 }
7431
7432 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7433 {
7434         int err;
7435         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7436         int cpu;
7437
7438         if (!vmx)
7439                 return ERR_PTR(-ENOMEM);
7440
7441         allocate_vpid(vmx);
7442
7443         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7444         if (err)
7445                 goto free_vcpu;
7446
7447         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7448         err = -ENOMEM;
7449         if (!vmx->guest_msrs) {
7450                 goto uninit_vcpu;
7451         }
7452
7453         vmx->loaded_vmcs = &vmx->vmcs01;
7454         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7455         if (!vmx->loaded_vmcs->vmcs)
7456                 goto free_msrs;
7457         if (!vmm_exclusive)
7458                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7459         loaded_vmcs_init(vmx->loaded_vmcs);
7460         if (!vmm_exclusive)
7461                 kvm_cpu_vmxoff();
7462
7463         cpu = get_cpu();
7464         vmx_vcpu_load(&vmx->vcpu, cpu);
7465         vmx->vcpu.cpu = cpu;
7466         err = vmx_vcpu_setup(vmx);
7467         vmx_vcpu_put(&vmx->vcpu);
7468         put_cpu();
7469         if (err)
7470                 goto free_vmcs;
7471         if (vm_need_virtualize_apic_accesses(kvm)) {
7472                 err = alloc_apic_access_page(kvm);
7473                 if (err)
7474                         goto free_vmcs;
7475         }
7476
7477         if (enable_ept) {
7478                 if (!kvm->arch.ept_identity_map_addr)
7479                         kvm->arch.ept_identity_map_addr =
7480                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7481                 err = -ENOMEM;
7482                 if (alloc_identity_pagetable(kvm) != 0)
7483                         goto free_vmcs;
7484                 if (!init_rmode_identity_map(kvm))
7485                         goto free_vmcs;
7486         }
7487
7488         vmx->nested.current_vmptr = -1ull;
7489         vmx->nested.current_vmcs12 = NULL;
7490
7491         return &vmx->vcpu;
7492
7493 free_vmcs:
7494         free_loaded_vmcs(vmx->loaded_vmcs);
7495 free_msrs:
7496         kfree(vmx->guest_msrs);
7497 uninit_vcpu:
7498         kvm_vcpu_uninit(&vmx->vcpu);
7499 free_vcpu:
7500         free_vpid(vmx);
7501         kmem_cache_free(kvm_vcpu_cache, vmx);
7502         return ERR_PTR(err);
7503 }
7504
7505 static void __init vmx_check_processor_compat(void *rtn)
7506 {
7507         struct vmcs_config vmcs_conf;
7508
7509         *(int *)rtn = 0;
7510         if (setup_vmcs_config(&vmcs_conf) < 0)
7511                 *(int *)rtn = -EIO;
7512         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7513                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7514                                 smp_processor_id());
7515                 *(int *)rtn = -EIO;
7516         }
7517 }
7518
7519 static int get_ept_level(void)
7520 {
7521         return VMX_EPT_DEFAULT_GAW + 1;
7522 }
7523
7524 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7525 {
7526         u64 ret;
7527
7528         /* For VT-d and EPT combination
7529          * 1. MMIO: always map as UC
7530          * 2. EPT with VT-d:
7531          *   a. VT-d without snooping control feature: can't guarantee the
7532          *      result, try to trust guest.
7533          *   b. VT-d with snooping control feature: snooping control feature of
7534          *      VT-d engine can guarantee the cache correctness. Just set it
7535          *      to WB to keep consistent with host. So the same as item 3.
7536          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7537          *    consistent with host MTRR
7538          */
7539         if (is_mmio)
7540                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7541         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
7542                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7543                       VMX_EPT_MT_EPTE_SHIFT;
7544         else
7545                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7546                         | VMX_EPT_IPAT_BIT;
7547
7548         return ret;
7549 }
7550
7551 static int vmx_get_lpage_level(void)
7552 {
7553         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7554                 return PT_DIRECTORY_LEVEL;
7555         else
7556                 /* For shadow and EPT supported 1GB page */
7557                 return PT_PDPE_LEVEL;
7558 }
7559
7560 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7561 {
7562         struct kvm_cpuid_entry2 *best;
7563         struct vcpu_vmx *vmx = to_vmx(vcpu);
7564         u32 exec_control;
7565
7566         vmx->rdtscp_enabled = false;
7567         if (vmx_rdtscp_supported()) {
7568                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7569                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7570                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7571                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7572                                 vmx->rdtscp_enabled = true;
7573                         else {
7574                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7575                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7576                                                 exec_control);
7577                         }
7578                 }
7579         }
7580
7581         /* Exposing INVPCID only when PCID is exposed */
7582         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7583         if (vmx_invpcid_supported() &&
7584             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7585             guest_cpuid_has_pcid(vcpu)) {
7586                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7587                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7588                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7589                              exec_control);
7590         } else {
7591                 if (cpu_has_secondary_exec_ctrls()) {
7592                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7593                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7594                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7595                                      exec_control);
7596                 }
7597                 if (best)
7598                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7599         }
7600 }
7601
7602 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7603 {
7604         if (func == 1 && nested)
7605                 entry->ecx |= bit(X86_FEATURE_VMX);
7606 }
7607
7608 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7609                 struct x86_exception *fault)
7610 {
7611         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7612         u32 exit_reason;
7613
7614         if (fault->error_code & PFERR_RSVD_MASK)
7615                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
7616         else
7617                 exit_reason = EXIT_REASON_EPT_VIOLATION;
7618         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
7619         vmcs12->guest_physical_address = fault->address;
7620 }
7621
7622 /* Callbacks for nested_ept_init_mmu_context: */
7623
7624 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7625 {
7626         /* return the page table to be shadowed - in our case, EPT12 */
7627         return get_vmcs12(vcpu)->ept_pointer;
7628 }
7629
7630 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7631 {
7632         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7633                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7634
7635         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7636         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7637         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7638
7639         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7640 }
7641
7642 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7643 {
7644         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7645 }
7646
7647 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7648                 struct x86_exception *fault)
7649 {
7650         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7651
7652         WARN_ON(!is_guest_mode(vcpu));
7653
7654         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7655         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7656                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7657                                   vmcs_read32(VM_EXIT_INTR_INFO),
7658                                   vmcs_readl(EXIT_QUALIFICATION));
7659         else
7660                 kvm_inject_page_fault(vcpu, fault);
7661 }
7662
7663 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7664 {
7665         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7666         struct vcpu_vmx *vmx = to_vmx(vcpu);
7667
7668         if (vcpu->arch.virtual_tsc_khz == 0)
7669                 return;
7670
7671         /* Make sure short timeouts reliably trigger an immediate vmexit.
7672          * hrtimer_start does not guarantee this. */
7673         if (preemption_timeout <= 1) {
7674                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7675                 return;
7676         }
7677
7678         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7679         preemption_timeout *= 1000000;
7680         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7681         hrtimer_start(&vmx->nested.preemption_timer,
7682                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7683 }
7684
7685 /*
7686  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7687  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7688  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7689  * guest in a way that will both be appropriate to L1's requests, and our
7690  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7691  * function also has additional necessary side-effects, like setting various
7692  * vcpu->arch fields.
7693  */
7694 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7695 {
7696         struct vcpu_vmx *vmx = to_vmx(vcpu);
7697         u32 exec_control;
7698
7699         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7700         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7701         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7702         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7703         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7704         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7705         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7706         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7707         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7708         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7709         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7710         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7711         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7712         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7713         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7714         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7715         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7716         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7717         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7718         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7719         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7720         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7721         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7722         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7723         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7724         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7725         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7726         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7727         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7728         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7729         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7730         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7731         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7732         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7733         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7734         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7735
7736         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7737         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7738                 vmcs12->vm_entry_intr_info_field);
7739         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7740                 vmcs12->vm_entry_exception_error_code);
7741         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7742                 vmcs12->vm_entry_instruction_len);
7743         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7744                 vmcs12->guest_interruptibility_info);
7745         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7746         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7747         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7748         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7749                 vmcs12->guest_pending_dbg_exceptions);
7750         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7751         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7752
7753         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7754
7755         exec_control = vmcs12->pin_based_vm_exec_control;
7756         exec_control |= vmcs_config.pin_based_exec_ctrl;
7757         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7758         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
7759
7760         vmx->nested.preemption_timer_expired = false;
7761         if (nested_cpu_has_preemption_timer(vmcs12))
7762                 vmx_start_preemption_timer(vcpu);
7763
7764         /*
7765          * Whether page-faults are trapped is determined by a combination of
7766          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7767          * If enable_ept, L0 doesn't care about page faults and we should
7768          * set all of these to L1's desires. However, if !enable_ept, L0 does
7769          * care about (at least some) page faults, and because it is not easy
7770          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7771          * to exit on each and every L2 page fault. This is done by setting
7772          * MASK=MATCH=0 and (see below) EB.PF=1.
7773          * Note that below we don't need special code to set EB.PF beyond the
7774          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7775          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7776          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7777          *
7778          * A problem with this approach (when !enable_ept) is that L1 may be
7779          * injected with more page faults than it asked for. This could have
7780          * caused problems, but in practice existing hypervisors don't care.
7781          * To fix this, we will need to emulate the PFEC checking (on the L1
7782          * page tables), using walk_addr(), when injecting PFs to L1.
7783          */
7784         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7785                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7786         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7787                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7788
7789         if (cpu_has_secondary_exec_ctrls()) {
7790                 exec_control = vmx_secondary_exec_control(vmx);
7791                 if (!vmx->rdtscp_enabled)
7792                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7793                 /* Take the following fields only from vmcs12 */
7794                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7795                 if (nested_cpu_has(vmcs12,
7796                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7797                         exec_control |= vmcs12->secondary_vm_exec_control;
7798
7799                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7800                         /*
7801                          * Translate L1 physical address to host physical
7802                          * address for vmcs02. Keep the page pinned, so this
7803                          * physical address remains valid. We keep a reference
7804                          * to it so we can release it later.
7805                          */
7806                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7807                                 nested_release_page(vmx->nested.apic_access_page);
7808                         vmx->nested.apic_access_page =
7809                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7810                         /*
7811                          * If translation failed, no matter: This feature asks
7812                          * to exit when accessing the given address, and if it
7813                          * can never be accessed, this feature won't do
7814                          * anything anyway.
7815                          */
7816                         if (!vmx->nested.apic_access_page)
7817                                 exec_control &=
7818                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7819                         else
7820                                 vmcs_write64(APIC_ACCESS_ADDR,
7821                                   page_to_phys(vmx->nested.apic_access_page));
7822                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7823                         exec_control |=
7824                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7825                         vmcs_write64(APIC_ACCESS_ADDR,
7826                                 page_to_phys(vcpu->kvm->arch.apic_access_page));
7827                 }
7828
7829                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7830         }
7831
7832
7833         /*
7834          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7835          * Some constant fields are set here by vmx_set_constant_host_state().
7836          * Other fields are different per CPU, and will be set later when
7837          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7838          */
7839         vmx_set_constant_host_state(vmx);
7840
7841         /*
7842          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7843          * entry, but only if the current (host) sp changed from the value
7844          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7845          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7846          * here we just force the write to happen on entry.
7847          */
7848         vmx->host_rsp = 0;
7849
7850         exec_control = vmx_exec_control(vmx); /* L0's desires */
7851         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7852         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7853         exec_control &= ~CPU_BASED_TPR_SHADOW;
7854         exec_control |= vmcs12->cpu_based_vm_exec_control;
7855         /*
7856          * Merging of IO and MSR bitmaps not currently supported.
7857          * Rather, exit every time.
7858          */
7859         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7860         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7861         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7862
7863         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7864
7865         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7866          * bitwise-or of what L1 wants to trap for L2, and what we want to
7867          * trap. Note that CR0.TS also needs updating - we do this later.
7868          */
7869         update_exception_bitmap(vcpu);
7870         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7871         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7872
7873         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7874          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7875          * bits are further modified by vmx_set_efer() below.
7876          */
7877         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7878
7879         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7880          * emulated by vmx_set_efer(), below.
7881          */
7882         vm_entry_controls_init(vmx,
7883                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7884                         ~VM_ENTRY_IA32E_MODE) |
7885                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7886
7887         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7888                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7889                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7890         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7891                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7892
7893
7894         set_cr4_guest_host_mask(vmx);
7895
7896         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7897                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7898
7899         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7900                 vmcs_write64(TSC_OFFSET,
7901                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7902         else
7903                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7904
7905         if (enable_vpid) {
7906                 /*
7907                  * Trivially support vpid by letting L2s share their parent
7908                  * L1's vpid. TODO: move to a more elaborate solution, giving
7909                  * each L2 its own vpid and exposing the vpid feature to L1.
7910                  */
7911                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7912                 vmx_flush_tlb(vcpu);
7913         }
7914
7915         if (nested_cpu_has_ept(vmcs12)) {
7916                 kvm_mmu_unload(vcpu);
7917                 nested_ept_init_mmu_context(vcpu);
7918         }
7919
7920         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7921                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7922         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7923                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7924         else
7925                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7926         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7927         vmx_set_efer(vcpu, vcpu->arch.efer);
7928
7929         /*
7930          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7931          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7932          * The CR0_READ_SHADOW is what L2 should have expected to read given
7933          * the specifications by L1; It's not enough to take
7934          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7935          * have more bits than L1 expected.
7936          */
7937         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7938         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7939
7940         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7941         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7942
7943         /* shadow page tables on either EPT or shadow page tables */
7944         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7945         kvm_mmu_reset_context(vcpu);
7946
7947         if (!enable_ept)
7948                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7949
7950         /*
7951          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7952          */
7953         if (enable_ept) {
7954                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7955                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7956                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7957                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7958         }
7959
7960         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7961         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7962 }
7963
7964 /*
7965  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7966  * for running an L2 nested guest.
7967  */
7968 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7969 {
7970         struct vmcs12 *vmcs12;
7971         struct vcpu_vmx *vmx = to_vmx(vcpu);
7972         int cpu;
7973         struct loaded_vmcs *vmcs02;
7974         bool ia32e;
7975
7976         if (!nested_vmx_check_permission(vcpu) ||
7977             !nested_vmx_check_vmcs12(vcpu))
7978                 return 1;
7979
7980         skip_emulated_instruction(vcpu);
7981         vmcs12 = get_vmcs12(vcpu);
7982
7983         if (enable_shadow_vmcs)
7984                 copy_shadow_to_vmcs12(vmx);
7985
7986         /*
7987          * The nested entry process starts with enforcing various prerequisites
7988          * on vmcs12 as required by the Intel SDM, and act appropriately when
7989          * they fail: As the SDM explains, some conditions should cause the
7990          * instruction to fail, while others will cause the instruction to seem
7991          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7992          * To speed up the normal (success) code path, we should avoid checking
7993          * for misconfigurations which will anyway be caught by the processor
7994          * when using the merged vmcs02.
7995          */
7996         if (vmcs12->launch_state == launch) {
7997                 nested_vmx_failValid(vcpu,
7998                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7999                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8000                 return 1;
8001         }
8002
8003         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8004             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
8005                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8006                 return 1;
8007         }
8008
8009         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8010                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
8011                 /*TODO: Also verify bits beyond physical address width are 0*/
8012                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8013                 return 1;
8014         }
8015
8016         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8017                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
8018                 /*TODO: Also verify bits beyond physical address width are 0*/
8019                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8020                 return 1;
8021         }
8022
8023         if (vmcs12->vm_entry_msr_load_count > 0 ||
8024             vmcs12->vm_exit_msr_load_count > 0 ||
8025             vmcs12->vm_exit_msr_store_count > 0) {
8026                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8027                                     __func__);
8028                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8029                 return 1;
8030         }
8031
8032         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8033               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8034             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8035               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8036             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8037               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8038             !vmx_control_verify(vmcs12->vm_exit_controls,
8039               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8040             !vmx_control_verify(vmcs12->vm_entry_controls,
8041               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8042         {
8043                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8044                 return 1;
8045         }
8046
8047         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8048             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8049                 nested_vmx_failValid(vcpu,
8050                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8051                 return 1;
8052         }
8053
8054         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8055             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8056                 nested_vmx_entry_failure(vcpu, vmcs12,
8057                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8058                 return 1;
8059         }
8060         if (vmcs12->vmcs_link_pointer != -1ull) {
8061                 nested_vmx_entry_failure(vcpu, vmcs12,
8062                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8063                 return 1;
8064         }
8065
8066         /*
8067          * If the load IA32_EFER VM-entry control is 1, the following checks
8068          * are performed on the field for the IA32_EFER MSR:
8069          * - Bits reserved in the IA32_EFER MSR must be 0.
8070          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8071          *   the IA-32e mode guest VM-exit control. It must also be identical
8072          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8073          *   CR0.PG) is 1.
8074          */
8075         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8076                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8077                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8078                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8079                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8080                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8081                         nested_vmx_entry_failure(vcpu, vmcs12,
8082                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8083                         return 1;
8084                 }
8085         }
8086
8087         /*
8088          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8089          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8090          * the values of the LMA and LME bits in the field must each be that of
8091          * the host address-space size VM-exit control.
8092          */
8093         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8094                 ia32e = (vmcs12->vm_exit_controls &
8095                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8096                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8097                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8098                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8099                         nested_vmx_entry_failure(vcpu, vmcs12,
8100                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8101                         return 1;
8102                 }
8103         }
8104
8105         /*
8106          * We're finally done with prerequisite checking, and can start with
8107          * the nested entry.
8108          */
8109
8110         vmcs02 = nested_get_current_vmcs02(vmx);
8111         if (!vmcs02)
8112                 return -ENOMEM;
8113
8114         enter_guest_mode(vcpu);
8115
8116         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8117
8118         cpu = get_cpu();
8119         vmx->loaded_vmcs = vmcs02;
8120         vmx_vcpu_put(vcpu);
8121         vmx_vcpu_load(vcpu, cpu);
8122         vcpu->cpu = cpu;
8123         put_cpu();
8124
8125         vmx_segment_cache_clear(vmx);
8126
8127         vmcs12->launch_state = 1;
8128
8129         prepare_vmcs02(vcpu, vmcs12);
8130
8131         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8132                 return kvm_emulate_halt(vcpu);
8133
8134         vmx->nested.nested_run_pending = 1;
8135
8136         /*
8137          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8138          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8139          * returned as far as L1 is concerned. It will only return (and set
8140          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8141          */
8142         return 1;
8143 }
8144
8145 /*
8146  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8147  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8148  * This function returns the new value we should put in vmcs12.guest_cr0.
8149  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8150  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8151  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8152  *     didn't trap the bit, because if L1 did, so would L0).
8153  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8154  *     been modified by L2, and L1 knows it. So just leave the old value of
8155  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8156  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8157  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8158  *     changed these bits, and therefore they need to be updated, but L0
8159  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8160  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8161  */
8162 static inline unsigned long
8163 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8164 {
8165         return
8166         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8167         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8168         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8169                         vcpu->arch.cr0_guest_owned_bits));
8170 }
8171
8172 static inline unsigned long
8173 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8174 {
8175         return
8176         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8177         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8178         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8179                         vcpu->arch.cr4_guest_owned_bits));
8180 }
8181
8182 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8183                                        struct vmcs12 *vmcs12)
8184 {
8185         u32 idt_vectoring;
8186         unsigned int nr;
8187
8188         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8189                 nr = vcpu->arch.exception.nr;
8190                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8191
8192                 if (kvm_exception_is_soft(nr)) {
8193                         vmcs12->vm_exit_instruction_len =
8194                                 vcpu->arch.event_exit_inst_len;
8195                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8196                 } else
8197                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8198
8199                 if (vcpu->arch.exception.has_error_code) {
8200                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8201                         vmcs12->idt_vectoring_error_code =
8202                                 vcpu->arch.exception.error_code;
8203                 }
8204
8205                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8206         } else if (vcpu->arch.nmi_injected) {
8207                 vmcs12->idt_vectoring_info_field =
8208                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8209         } else if (vcpu->arch.interrupt.pending) {
8210                 nr = vcpu->arch.interrupt.nr;
8211                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8212
8213                 if (vcpu->arch.interrupt.soft) {
8214                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8215                         vmcs12->vm_entry_instruction_len =
8216                                 vcpu->arch.event_exit_inst_len;
8217                 } else
8218                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8219
8220                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8221         }
8222 }
8223
8224 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8225 {
8226         struct vcpu_vmx *vmx = to_vmx(vcpu);
8227
8228         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8229             vmx->nested.preemption_timer_expired) {
8230                 if (vmx->nested.nested_run_pending)
8231                         return -EBUSY;
8232                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8233                 return 0;
8234         }
8235
8236         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8237                 if (vmx->nested.nested_run_pending ||
8238                     vcpu->arch.interrupt.pending)
8239                         return -EBUSY;
8240                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8241                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8242                                   INTR_INFO_VALID_MASK, 0);
8243                 /*
8244                  * The NMI-triggered VM exit counts as injection:
8245                  * clear this one and block further NMIs.
8246                  */
8247                 vcpu->arch.nmi_pending = 0;
8248                 vmx_set_nmi_mask(vcpu, true);
8249                 return 0;
8250         }
8251
8252         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8253             nested_exit_on_intr(vcpu)) {
8254                 if (vmx->nested.nested_run_pending)
8255                         return -EBUSY;
8256                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8257         }
8258
8259         return 0;
8260 }
8261
8262 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8263 {
8264         ktime_t remaining =
8265                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8266         u64 value;
8267
8268         if (ktime_to_ns(remaining) <= 0)
8269                 return 0;
8270
8271         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8272         do_div(value, 1000000);
8273         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8274 }
8275
8276 /*
8277  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8278  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8279  * and this function updates it to reflect the changes to the guest state while
8280  * L2 was running (and perhaps made some exits which were handled directly by L0
8281  * without going back to L1), and to reflect the exit reason.
8282  * Note that we do not have to copy here all VMCS fields, just those that
8283  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8284  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8285  * which already writes to vmcs12 directly.
8286  */
8287 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8288                            u32 exit_reason, u32 exit_intr_info,
8289                            unsigned long exit_qualification)
8290 {
8291         /* update guest state fields: */
8292         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8293         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8294
8295         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8296         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8297         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8298         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8299
8300         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8301         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8302         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8303         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8304         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8305         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8306         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8307         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8308         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8309         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8310         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8311         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8312         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8313         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8314         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8315         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8316         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8317         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8318         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8319         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8320         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8321         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8322         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8323         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8324         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8325         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8326         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8327         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8328         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8329         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8330         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8331         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8332         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8333         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8334         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8335         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8336
8337         vmcs12->guest_interruptibility_info =
8338                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8339         vmcs12->guest_pending_dbg_exceptions =
8340                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8341         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8342                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8343         else
8344                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8345
8346         if (nested_cpu_has_preemption_timer(vmcs12)) {
8347                 if (vmcs12->vm_exit_controls &
8348                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8349                         vmcs12->vmx_preemption_timer_value =
8350                                 vmx_get_preemption_timer_value(vcpu);
8351                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8352         }
8353
8354         /*
8355          * In some cases (usually, nested EPT), L2 is allowed to change its
8356          * own CR3 without exiting. If it has changed it, we must keep it.
8357          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8358          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8359          *
8360          * Additionally, restore L2's PDPTR to vmcs12.
8361          */
8362         if (enable_ept) {
8363                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8364                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8365                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8366                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8367                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8368         }
8369
8370         vmcs12->vm_entry_controls =
8371                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8372                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8373
8374         /* TODO: These cannot have changed unless we have MSR bitmaps and
8375          * the relevant bit asks not to trap the change */
8376         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8377         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8378                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8379         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8380                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8381         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8382         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8383         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8384         if (vmx_mpx_supported())
8385                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8386
8387         /* update exit information fields: */
8388
8389         vmcs12->vm_exit_reason = exit_reason;
8390         vmcs12->exit_qualification = exit_qualification;
8391
8392         vmcs12->vm_exit_intr_info = exit_intr_info;
8393         if ((vmcs12->vm_exit_intr_info &
8394              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8395             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8396                 vmcs12->vm_exit_intr_error_code =
8397                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8398         vmcs12->idt_vectoring_info_field = 0;
8399         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8400         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8401
8402         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8403                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8404                  * instead of reading the real value. */
8405                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8406
8407                 /*
8408                  * Transfer the event that L0 or L1 may wanted to inject into
8409                  * L2 to IDT_VECTORING_INFO_FIELD.
8410                  */
8411                 vmcs12_save_pending_event(vcpu, vmcs12);
8412         }
8413
8414         /*
8415          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8416          * preserved above and would only end up incorrectly in L1.
8417          */
8418         vcpu->arch.nmi_injected = false;
8419         kvm_clear_exception_queue(vcpu);
8420         kvm_clear_interrupt_queue(vcpu);
8421 }
8422
8423 /*
8424  * A part of what we need to when the nested L2 guest exits and we want to
8425  * run its L1 parent, is to reset L1's guest state to the host state specified
8426  * in vmcs12.
8427  * This function is to be called not only on normal nested exit, but also on
8428  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8429  * Failures During or After Loading Guest State").
8430  * This function should be called when the active VMCS is L1's (vmcs01).
8431  */
8432 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8433                                    struct vmcs12 *vmcs12)
8434 {
8435         struct kvm_segment seg;
8436
8437         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8438                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8439         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8440                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8441         else
8442                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8443         vmx_set_efer(vcpu, vcpu->arch.efer);
8444
8445         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8446         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8447         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8448         /*
8449          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8450          * actually changed, because it depends on the current state of
8451          * fpu_active (which may have changed).
8452          * Note that vmx_set_cr0 refers to efer set above.
8453          */
8454         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8455         /*
8456          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8457          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8458          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8459          */
8460         update_exception_bitmap(vcpu);
8461         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8462         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8463
8464         /*
8465          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8466          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8467          */
8468         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8469         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8470
8471         nested_ept_uninit_mmu_context(vcpu);
8472
8473         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8474         kvm_mmu_reset_context(vcpu);
8475
8476         if (!enable_ept)
8477                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8478
8479         if (enable_vpid) {
8480                 /*
8481                  * Trivially support vpid by letting L2s share their parent
8482                  * L1's vpid. TODO: move to a more elaborate solution, giving
8483                  * each L2 its own vpid and exposing the vpid feature to L1.
8484                  */
8485                 vmx_flush_tlb(vcpu);
8486         }
8487
8488
8489         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8490         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8491         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8492         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8493         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8494
8495         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
8496         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8497                 vmcs_write64(GUEST_BNDCFGS, 0);
8498
8499         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8500                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8501                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8502         }
8503         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8504                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8505                         vmcs12->host_ia32_perf_global_ctrl);
8506
8507         /* Set L1 segment info according to Intel SDM
8508             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8509         seg = (struct kvm_segment) {
8510                 .base = 0,
8511                 .limit = 0xFFFFFFFF,
8512                 .selector = vmcs12->host_cs_selector,
8513                 .type = 11,
8514                 .present = 1,
8515                 .s = 1,
8516                 .g = 1
8517         };
8518         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8519                 seg.l = 1;
8520         else
8521                 seg.db = 1;
8522         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8523         seg = (struct kvm_segment) {
8524                 .base = 0,
8525                 .limit = 0xFFFFFFFF,
8526                 .type = 3,
8527                 .present = 1,
8528                 .s = 1,
8529                 .db = 1,
8530                 .g = 1
8531         };
8532         seg.selector = vmcs12->host_ds_selector;
8533         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8534         seg.selector = vmcs12->host_es_selector;
8535         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8536         seg.selector = vmcs12->host_ss_selector;
8537         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8538         seg.selector = vmcs12->host_fs_selector;
8539         seg.base = vmcs12->host_fs_base;
8540         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8541         seg.selector = vmcs12->host_gs_selector;
8542         seg.base = vmcs12->host_gs_base;
8543         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8544         seg = (struct kvm_segment) {
8545                 .base = vmcs12->host_tr_base,
8546                 .limit = 0x67,
8547                 .selector = vmcs12->host_tr_selector,
8548                 .type = 11,
8549                 .present = 1
8550         };
8551         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8552
8553         kvm_set_dr(vcpu, 7, 0x400);
8554         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8555 }
8556
8557 /*
8558  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8559  * and modify vmcs12 to make it see what it would expect to see there if
8560  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8561  */
8562 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8563                               u32 exit_intr_info,
8564                               unsigned long exit_qualification)
8565 {
8566         struct vcpu_vmx *vmx = to_vmx(vcpu);
8567         int cpu;
8568         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8569
8570         /* trying to cancel vmlaunch/vmresume is a bug */
8571         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8572
8573         leave_guest_mode(vcpu);
8574         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8575                        exit_qualification);
8576
8577         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8578             && nested_exit_intr_ack_set(vcpu)) {
8579                 int irq = kvm_cpu_get_interrupt(vcpu);
8580                 WARN_ON(irq < 0);
8581                 vmcs12->vm_exit_intr_info = irq |
8582                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8583         }
8584
8585         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8586                                        vmcs12->exit_qualification,
8587                                        vmcs12->idt_vectoring_info_field,
8588                                        vmcs12->vm_exit_intr_info,
8589                                        vmcs12->vm_exit_intr_error_code,
8590                                        KVM_ISA_VMX);
8591
8592         cpu = get_cpu();
8593         vmx->loaded_vmcs = &vmx->vmcs01;
8594         vmx_vcpu_put(vcpu);
8595         vmx_vcpu_load(vcpu, cpu);
8596         vcpu->cpu = cpu;
8597         put_cpu();
8598
8599         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8600         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
8601         vmx_segment_cache_clear(vmx);
8602
8603         /* if no vmcs02 cache requested, remove the one we used */
8604         if (VMCS02_POOL_SIZE == 0)
8605                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8606
8607         load_vmcs12_host_state(vcpu, vmcs12);
8608
8609         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8610         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8611
8612         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8613         vmx->host_rsp = 0;
8614
8615         /* Unpin physical memory we referred to in vmcs02 */
8616         if (vmx->nested.apic_access_page) {
8617                 nested_release_page(vmx->nested.apic_access_page);
8618                 vmx->nested.apic_access_page = 0;
8619         }
8620
8621         /*
8622          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8623          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8624          * success or failure flag accordingly.
8625          */
8626         if (unlikely(vmx->fail)) {
8627                 vmx->fail = 0;
8628                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8629         } else
8630                 nested_vmx_succeed(vcpu);
8631         if (enable_shadow_vmcs)
8632                 vmx->nested.sync_shadow_vmcs = true;
8633
8634         /* in case we halted in L2 */
8635         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8636 }
8637
8638 /*
8639  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8640  */
8641 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8642 {
8643         if (is_guest_mode(vcpu))
8644                 nested_vmx_vmexit(vcpu, -1, 0, 0);
8645         free_nested(to_vmx(vcpu));
8646 }
8647
8648 /*
8649  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8650  * 23.7 "VM-entry failures during or after loading guest state" (this also
8651  * lists the acceptable exit-reason and exit-qualification parameters).
8652  * It should only be called before L2 actually succeeded to run, and when
8653  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8654  */
8655 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8656                         struct vmcs12 *vmcs12,
8657                         u32 reason, unsigned long qualification)
8658 {
8659         load_vmcs12_host_state(vcpu, vmcs12);
8660         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8661         vmcs12->exit_qualification = qualification;
8662         nested_vmx_succeed(vcpu);
8663         if (enable_shadow_vmcs)
8664                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8665 }
8666
8667 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8668                                struct x86_instruction_info *info,
8669                                enum x86_intercept_stage stage)
8670 {
8671         return X86EMUL_CONTINUE;
8672 }
8673
8674 static struct kvm_x86_ops vmx_x86_ops = {
8675         .cpu_has_kvm_support = cpu_has_kvm_support,
8676         .disabled_by_bios = vmx_disabled_by_bios,
8677         .hardware_setup = hardware_setup,
8678         .hardware_unsetup = hardware_unsetup,
8679         .check_processor_compatibility = vmx_check_processor_compat,
8680         .hardware_enable = hardware_enable,
8681         .hardware_disable = hardware_disable,
8682         .cpu_has_accelerated_tpr = report_flexpriority,
8683
8684         .vcpu_create = vmx_create_vcpu,
8685         .vcpu_free = vmx_free_vcpu,
8686         .vcpu_reset = vmx_vcpu_reset,
8687
8688         .prepare_guest_switch = vmx_save_host_state,
8689         .vcpu_load = vmx_vcpu_load,
8690         .vcpu_put = vmx_vcpu_put,
8691
8692         .update_db_bp_intercept = update_exception_bitmap,
8693         .get_msr = vmx_get_msr,
8694         .set_msr = vmx_set_msr,
8695         .get_segment_base = vmx_get_segment_base,
8696         .get_segment = vmx_get_segment,
8697         .set_segment = vmx_set_segment,
8698         .get_cpl = vmx_get_cpl,
8699         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8700         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8701         .decache_cr3 = vmx_decache_cr3,
8702         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8703         .set_cr0 = vmx_set_cr0,
8704         .set_cr3 = vmx_set_cr3,
8705         .set_cr4 = vmx_set_cr4,
8706         .set_efer = vmx_set_efer,
8707         .get_idt = vmx_get_idt,
8708         .set_idt = vmx_set_idt,
8709         .get_gdt = vmx_get_gdt,
8710         .set_gdt = vmx_set_gdt,
8711         .get_dr6 = vmx_get_dr6,
8712         .set_dr6 = vmx_set_dr6,
8713         .set_dr7 = vmx_set_dr7,
8714         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
8715         .cache_reg = vmx_cache_reg,
8716         .get_rflags = vmx_get_rflags,
8717         .set_rflags = vmx_set_rflags,
8718         .fpu_activate = vmx_fpu_activate,
8719         .fpu_deactivate = vmx_fpu_deactivate,
8720
8721         .tlb_flush = vmx_flush_tlb,
8722
8723         .run = vmx_vcpu_run,
8724         .handle_exit = vmx_handle_exit,
8725         .skip_emulated_instruction = skip_emulated_instruction,
8726         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8727         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8728         .patch_hypercall = vmx_patch_hypercall,
8729         .set_irq = vmx_inject_irq,
8730         .set_nmi = vmx_inject_nmi,
8731         .queue_exception = vmx_queue_exception,
8732         .cancel_injection = vmx_cancel_injection,
8733         .interrupt_allowed = vmx_interrupt_allowed,
8734         .nmi_allowed = vmx_nmi_allowed,
8735         .get_nmi_mask = vmx_get_nmi_mask,
8736         .set_nmi_mask = vmx_set_nmi_mask,
8737         .enable_nmi_window = enable_nmi_window,
8738         .enable_irq_window = enable_irq_window,
8739         .update_cr8_intercept = update_cr8_intercept,
8740         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8741         .vm_has_apicv = vmx_vm_has_apicv,
8742         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8743         .hwapic_irr_update = vmx_hwapic_irr_update,
8744         .hwapic_isr_update = vmx_hwapic_isr_update,
8745         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8746         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8747
8748         .set_tss_addr = vmx_set_tss_addr,
8749         .get_tdp_level = get_ept_level,
8750         .get_mt_mask = vmx_get_mt_mask,
8751
8752         .get_exit_info = vmx_get_exit_info,
8753
8754         .get_lpage_level = vmx_get_lpage_level,
8755
8756         .cpuid_update = vmx_cpuid_update,
8757
8758         .rdtscp_supported = vmx_rdtscp_supported,
8759         .invpcid_supported = vmx_invpcid_supported,
8760
8761         .set_supported_cpuid = vmx_set_supported_cpuid,
8762
8763         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8764
8765         .set_tsc_khz = vmx_set_tsc_khz,
8766         .read_tsc_offset = vmx_read_tsc_offset,
8767         .write_tsc_offset = vmx_write_tsc_offset,
8768         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8769         .compute_tsc_offset = vmx_compute_tsc_offset,
8770         .read_l1_tsc = vmx_read_l1_tsc,
8771
8772         .set_tdp_cr3 = vmx_set_cr3,
8773
8774         .check_intercept = vmx_check_intercept,
8775         .handle_external_intr = vmx_handle_external_intr,
8776         .mpx_supported = vmx_mpx_supported,
8777
8778         .check_nested_events = vmx_check_nested_events,
8779 };
8780
8781 static int __init vmx_init(void)
8782 {
8783         int r, i, msr;
8784
8785         rdmsrl_safe(MSR_EFER, &host_efer);
8786
8787         for (i = 0; i < NR_VMX_MSR; ++i)
8788                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8789
8790         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8791         if (!vmx_io_bitmap_a)
8792                 return -ENOMEM;
8793
8794         r = -ENOMEM;
8795
8796         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8797         if (!vmx_io_bitmap_b)
8798                 goto out;
8799
8800         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8801         if (!vmx_msr_bitmap_legacy)
8802                 goto out1;
8803
8804         vmx_msr_bitmap_legacy_x2apic =
8805                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8806         if (!vmx_msr_bitmap_legacy_x2apic)
8807                 goto out2;
8808
8809         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8810         if (!vmx_msr_bitmap_longmode)
8811                 goto out3;
8812
8813         vmx_msr_bitmap_longmode_x2apic =
8814                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8815         if (!vmx_msr_bitmap_longmode_x2apic)
8816                 goto out4;
8817         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8818         if (!vmx_vmread_bitmap)
8819                 goto out5;
8820
8821         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8822         if (!vmx_vmwrite_bitmap)
8823                 goto out6;
8824
8825         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8826         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8827         /* shadowed read/write fields */
8828         for (i = 0; i < max_shadow_read_write_fields; i++) {
8829                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8830                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8831         }
8832         /* shadowed read only fields */
8833         for (i = 0; i < max_shadow_read_only_fields; i++)
8834                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8835
8836         /*
8837          * Allow direct access to the PC debug port (it is often used for I/O
8838          * delays, but the vmexits simply slow things down).
8839          */
8840         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8841         clear_bit(0x80, vmx_io_bitmap_a);
8842
8843         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8844
8845         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8846         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8847
8848         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8849
8850         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8851                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8852         if (r)
8853                 goto out7;
8854
8855 #ifdef CONFIG_KEXEC
8856         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8857                            crash_vmclear_local_loaded_vmcss);
8858 #endif
8859
8860         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8861         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8862         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8863         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8864         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8865         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8866         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8867
8868         memcpy(vmx_msr_bitmap_legacy_x2apic,
8869                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8870         memcpy(vmx_msr_bitmap_longmode_x2apic,
8871                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8872
8873         if (enable_apicv) {
8874                 for (msr = 0x800; msr <= 0x8ff; msr++)
8875                         vmx_disable_intercept_msr_read_x2apic(msr);
8876
8877                 /* According SDM, in x2apic mode, the whole id reg is used.
8878                  * But in KVM, it only use the highest eight bits. Need to
8879                  * intercept it */
8880                 vmx_enable_intercept_msr_read_x2apic(0x802);
8881                 /* TMCCT */
8882                 vmx_enable_intercept_msr_read_x2apic(0x839);
8883                 /* TPR */
8884                 vmx_disable_intercept_msr_write_x2apic(0x808);
8885                 /* EOI */
8886                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8887                 /* SELF-IPI */
8888                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8889         }
8890
8891         if (enable_ept) {
8892                 kvm_mmu_set_mask_ptes(0ull,
8893                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8894                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8895                         0ull, VMX_EPT_EXECUTABLE_MASK);
8896                 ept_set_mmio_spte_mask();
8897                 kvm_enable_tdp();
8898         } else
8899                 kvm_disable_tdp();
8900
8901         return 0;
8902
8903 out7:
8904         free_page((unsigned long)vmx_vmwrite_bitmap);
8905 out6:
8906         free_page((unsigned long)vmx_vmread_bitmap);
8907 out5:
8908         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8909 out4:
8910         free_page((unsigned long)vmx_msr_bitmap_longmode);
8911 out3:
8912         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8913 out2:
8914         free_page((unsigned long)vmx_msr_bitmap_legacy);
8915 out1:
8916         free_page((unsigned long)vmx_io_bitmap_b);
8917 out:
8918         free_page((unsigned long)vmx_io_bitmap_a);
8919         return r;
8920 }
8921
8922 static void __exit vmx_exit(void)
8923 {
8924         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8925         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8926         free_page((unsigned long)vmx_msr_bitmap_legacy);
8927         free_page((unsigned long)vmx_msr_bitmap_longmode);
8928         free_page((unsigned long)vmx_io_bitmap_b);
8929         free_page((unsigned long)vmx_io_bitmap_a);
8930         free_page((unsigned long)vmx_vmwrite_bitmap);
8931         free_page((unsigned long)vmx_vmread_bitmap);
8932
8933 #ifdef CONFIG_KEXEC
8934         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8935         synchronize_rcu();
8936 #endif
8937
8938         kvm_exit();
8939 }
8940
8941 module_init(vmx_init)
8942 module_exit(vmx_exit)