arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46 #define __ex_clear(x, reg) \
  47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  48
  49 MODULE_AUTHOR("Qumranet");
  50 MODULE_LICENSE("GPL");
  51
  52 static int __read_mostly bypass_guest_pf = 1;
  53 module_param(bypass_guest_pf, bool, S_IRUGO);
  54
  55 static int __read_mostly enable_vpid = 1;
  56 module_param_named(vpid, enable_vpid, bool, 0444);
  57
  58 static int __read_mostly flexpriority_enabled = 1;
  59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  60
  61 static int __read_mostly enable_ept = 1;
  62 module_param_named(ept, enable_ept, bool, S_IRUGO);
  63
  64 static int __read_mostly enable_unrestricted_guest = 1;
  65 module_param_named(unrestricted_guest,
  66                         enable_unrestricted_guest, bool, S_IRUGO);
  67
  68 static int __read_mostly emulate_invalid_guest_state = 0;
  69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  70
  71 static int __read_mostly vmm_exclusive = 1;
  72 module_param(vmm_exclusive, bool, S_IRUGO);
  73
  74 static int __read_mostly yield_on_hlt = 1;
  75 module_param(yield_on_hlt, bool, S_IRUGO);
  76
  77 /*
  78  * If nested=1, nested virtualization is supported, i.e., guests may use
  79  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  80  * use VMX instructions.
  81  */
  82 static int __read_mostly nested = 0;
  83 module_param(nested, bool, S_IRUGO);
  84
  85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  86         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  87 #define KVM_GUEST_CR0_MASK                                              \
  88         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  90         (X86_CR0_WP | X86_CR0_NE)
  91 #define KVM_VM_CR0_ALWAYS_ON                                            \
  92         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  93 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  94         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  95          | X86_CR4_OSXMMEXCPT)
  96
  97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  99
 100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 101
 102 /*
 103  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 104  * ple_gap:    upper bound on the amount of time between two successive
 105  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 106  *             According to test, this time is usually smaller than 128 cycles.
 107  * ple_window: upper bound on the amount of time a guest is allowed to execute
 108  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 109  *             less than 2^12 cycles
 110  * Time is measured based on a counter that runs at the same rate as the TSC,
 111  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 112  */
 113 #define KVM_VMX_DEFAULT_PLE_GAP    128
 114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 116 module_param(ple_gap, int, S_IRUGO);
 117
 118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 119 module_param(ple_window, int, S_IRUGO);
 120
 121 #define NR_AUTOLOAD_MSRS 1
 122 #define VMCS02_POOL_SIZE 1
 123
 124 struct vmcs {
 125         u32 revision_id;
 126         u32 abort;
 127         char data[0];
 128 };
 129
 130 /*
 131  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 132  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 133  * loaded on this CPU (so we can clear them if the CPU goes down).
 134  */
 135 struct loaded_vmcs {
 136         struct vmcs *vmcs;
 137         int cpu;
 138         int launched;
 139         struct list_head loaded_vmcss_on_cpu_link;
 140 };
 141
 142 struct shared_msr_entry {
 143         unsigned index;
 144         u64 data;
 145         u64 mask;
 146 };
 147
 148 /*
 149  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 150  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 151  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 152  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 153  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 154  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 155  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 156  * underlying hardware which will be used to run L2.
 157  * This structure is packed to ensure that its layout is identical across
 158  * machines (necessary for live migration).
 159  * If there are changes in this struct, VMCS12_REVISION must be changed.
 160  */
 161 typedef u64 natural_width;
 162 struct __packed vmcs12 {
 163         /* According to the Intel spec, a VMCS region must start with the
 164          * following two fields. Then follow implementation-specific data.
 165          */
 166         u32 revision_id;
 167         u32 abort;
 168
 169         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 170         u32 padding[7]; /* room for future expansion */
 171
 172         u64 io_bitmap_a;
 173         u64 io_bitmap_b;
 174         u64 msr_bitmap;
 175         u64 vm_exit_msr_store_addr;
 176         u64 vm_exit_msr_load_addr;
 177         u64 vm_entry_msr_load_addr;
 178         u64 tsc_offset;
 179         u64 virtual_apic_page_addr;
 180         u64 apic_access_addr;
 181         u64 ept_pointer;
 182         u64 guest_physical_address;
 183         u64 vmcs_link_pointer;
 184         u64 guest_ia32_debugctl;
 185         u64 guest_ia32_pat;
 186         u64 guest_ia32_efer;
 187         u64 guest_ia32_perf_global_ctrl;
 188         u64 guest_pdptr0;
 189         u64 guest_pdptr1;
 190         u64 guest_pdptr2;
 191         u64 guest_pdptr3;
 192         u64 host_ia32_pat;
 193         u64 host_ia32_efer;
 194         u64 host_ia32_perf_global_ctrl;
 195         u64 padding64[8]; /* room for future expansion */
 196         /*
 197          * To allow migration of L1 (complete with its L2 guests) between
 198          * machines of different natural widths (32 or 64 bit), we cannot have
 199          * unsigned long fields with no explict size. We use u64 (aliased
 200          * natural_width) instead. Luckily, x86 is little-endian.
 201          */
 202         natural_width cr0_guest_host_mask;
 203         natural_width cr4_guest_host_mask;
 204         natural_width cr0_read_shadow;
 205         natural_width cr4_read_shadow;
 206         natural_width cr3_target_value0;
 207         natural_width cr3_target_value1;
 208         natural_width cr3_target_value2;
 209         natural_width cr3_target_value3;
 210         natural_width exit_qualification;
 211         natural_width guest_linear_address;
 212         natural_width guest_cr0;
 213         natural_width guest_cr3;
 214         natural_width guest_cr4;
 215         natural_width guest_es_base;
 216         natural_width guest_cs_base;
 217         natural_width guest_ss_base;
 218         natural_width guest_ds_base;
 219         natural_width guest_fs_base;
 220         natural_width guest_gs_base;
 221         natural_width guest_ldtr_base;
 222         natural_width guest_tr_base;
 223         natural_width guest_gdtr_base;
 224         natural_width guest_idtr_base;
 225         natural_width guest_dr7;
 226         natural_width guest_rsp;
 227         natural_width guest_rip;
 228         natural_width guest_rflags;
 229         natural_width guest_pending_dbg_exceptions;
 230         natural_width guest_sysenter_esp;
 231         natural_width guest_sysenter_eip;
 232         natural_width host_cr0;
 233         natural_width host_cr3;
 234         natural_width host_cr4;
 235         natural_width host_fs_base;
 236         natural_width host_gs_base;
 237         natural_width host_tr_base;
 238         natural_width host_gdtr_base;
 239         natural_width host_idtr_base;
 240         natural_width host_ia32_sysenter_esp;
 241         natural_width host_ia32_sysenter_eip;
 242         natural_width host_rsp;
 243         natural_width host_rip;
 244         natural_width paddingl[8]; /* room for future expansion */
 245         u32 pin_based_vm_exec_control;
 246         u32 cpu_based_vm_exec_control;
 247         u32 exception_bitmap;
 248         u32 page_fault_error_code_mask;
 249         u32 page_fault_error_code_match;
 250         u32 cr3_target_count;
 251         u32 vm_exit_controls;
 252         u32 vm_exit_msr_store_count;
 253         u32 vm_exit_msr_load_count;
 254         u32 vm_entry_controls;
 255         u32 vm_entry_msr_load_count;
 256         u32 vm_entry_intr_info_field;
 257         u32 vm_entry_exception_error_code;
 258         u32 vm_entry_instruction_len;
 259         u32 tpr_threshold;
 260         u32 secondary_vm_exec_control;
 261         u32 vm_instruction_error;
 262         u32 vm_exit_reason;
 263         u32 vm_exit_intr_info;
 264         u32 vm_exit_intr_error_code;
 265         u32 idt_vectoring_info_field;
 266         u32 idt_vectoring_error_code;
 267         u32 vm_exit_instruction_len;
 268         u32 vmx_instruction_info;
 269         u32 guest_es_limit;
 270         u32 guest_cs_limit;
 271         u32 guest_ss_limit;
 272         u32 guest_ds_limit;
 273         u32 guest_fs_limit;
 274         u32 guest_gs_limit;
 275         u32 guest_ldtr_limit;
 276         u32 guest_tr_limit;
 277         u32 guest_gdtr_limit;
 278         u32 guest_idtr_limit;
 279         u32 guest_es_ar_bytes;
 280         u32 guest_cs_ar_bytes;
 281         u32 guest_ss_ar_bytes;
 282         u32 guest_ds_ar_bytes;
 283         u32 guest_fs_ar_bytes;
 284         u32 guest_gs_ar_bytes;
 285         u32 guest_ldtr_ar_bytes;
 286         u32 guest_tr_ar_bytes;
 287         u32 guest_interruptibility_info;
 288         u32 guest_activity_state;
 289         u32 guest_sysenter_cs;
 290         u32 host_ia32_sysenter_cs;
 291         u32 padding32[8]; /* room for future expansion */
 292         u16 virtual_processor_id;
 293         u16 guest_es_selector;
 294         u16 guest_cs_selector;
 295         u16 guest_ss_selector;
 296         u16 guest_ds_selector;
 297         u16 guest_fs_selector;
 298         u16 guest_gs_selector;
 299         u16 guest_ldtr_selector;
 300         u16 guest_tr_selector;
 301         u16 host_es_selector;
 302         u16 host_cs_selector;
 303         u16 host_ss_selector;
 304         u16 host_ds_selector;
 305         u16 host_fs_selector;
 306         u16 host_gs_selector;
 307         u16 host_tr_selector;
 308 };
 309
 310 /*
 311  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 312  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 313  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 314  */
 315 #define VMCS12_REVISION 0x11e57ed0
 316
 317 /*
 318  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 319  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 320  * current implementation, 4K are reserved to avoid future complications.
 321  */
 322 #define VMCS12_SIZE 0x1000
 323
 324 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 325 struct vmcs02_list {
 326         struct list_head list;
 327         gpa_t vmptr;
 328         struct loaded_vmcs vmcs02;
 329 };
 330
 331 /*
 332  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 333  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 334  */
 335 struct nested_vmx {
 336         /* Has the level1 guest done vmxon? */
 337         bool vmxon;
 338
 339         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 340         gpa_t current_vmptr;
 341         /* The host-usable pointer to the above */
 342         struct page *current_vmcs12_page;
 343         struct vmcs12 *current_vmcs12;
 344
 345         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 346         struct list_head vmcs02_pool;
 347         int vmcs02_num;
 348         u64 vmcs01_tsc_offset;
 349         /*
 350          * Guest pages referred to in vmcs02 with host-physical pointers, so
 351          * we must keep them pinned while L2 runs.
 352          */
 353         struct page *apic_access_page;
 354 };
 355
 356 struct vcpu_vmx {
 357         struct kvm_vcpu       vcpu;
 358         unsigned long         host_rsp;
 359         u8                    fail;
 360         u8                    cpl;
 361         bool                  nmi_known_unmasked;
 362         u32                   exit_intr_info;
 363         u32                   idt_vectoring_info;
 364         ulong                 rflags;
 365         struct shared_msr_entry *guest_msrs;
 366         int                   nmsrs;
 367         int                   save_nmsrs;
 368 #ifdef CONFIG_X86_64
 369         u64                   msr_host_kernel_gs_base;
 370         u64                   msr_guest_kernel_gs_base;
 371 #endif
 372         /*
 373          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 374          * non-nested (L1) guest, it always points to vmcs01. For a nested
 375          * guest (L2), it points to a different VMCS.
 376          */
 377         struct loaded_vmcs    vmcs01;
 378         struct loaded_vmcs   *loaded_vmcs;
 379         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 380         struct msr_autoload {
 381                 unsigned nr;
 382                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 383                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 384         } msr_autoload;
 385         struct {
 386                 int           loaded;
 387                 u16           fs_sel, gs_sel, ldt_sel;
 388                 int           gs_ldt_reload_needed;
 389                 int           fs_reload_needed;
 390         } host_state;
 391         struct {
 392                 int vm86_active;
 393                 ulong save_rflags;
 394                 struct kvm_save_segment {
 395                         u16 selector;
 396                         unsigned long base;
 397                         u32 limit;
 398                         u32 ar;
 399                 } tr, es, ds, fs, gs;
 400         } rmode;
 401         struct {
 402                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 403                 struct kvm_save_segment seg[8];
 404         } segment_cache;
 405         int vpid;
 406         bool emulation_required;
 407
 408         /* Support for vnmi-less CPUs */
 409         int soft_vnmi_blocked;
 410         ktime_t entry_time;
 411         s64 vnmi_blocked_time;
 412         u32 exit_reason;
 413
 414         bool rdtscp_enabled;
 415
 416         /* Support for a guest hypervisor (nested VMX) */
 417         struct nested_vmx nested;
 418 };
 419
 420 enum segment_cache_field {
 421         SEG_FIELD_SEL = 0,
 422         SEG_FIELD_BASE = 1,
 423         SEG_FIELD_LIMIT = 2,
 424         SEG_FIELD_AR = 3,
 425
 426         SEG_FIELD_NR = 4
 427 };
 428
 429 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 430 {
 431         return container_of(vcpu, struct vcpu_vmx, vcpu);
 432 }
 433
 434 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 435 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 436 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 437                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 438
 439 static unsigned short vmcs_field_to_offset_table[] = {
 440         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 441         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 442         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 443         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 444         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 445         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 446         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 447         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 448         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 449         FIELD(HOST_ES_SELECTOR, host_es_selector),
 450         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 451         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 452         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 453         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 454         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 455         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 456         FIELD64(IO_BITMAP_A, io_bitmap_a),
 457         FIELD64(IO_BITMAP_B, io_bitmap_b),
 458         FIELD64(MSR_BITMAP, msr_bitmap),
 459         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 460         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 461         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 462         FIELD64(TSC_OFFSET, tsc_offset),
 463         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 464         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 465         FIELD64(EPT_POINTER, ept_pointer),
 466         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 467         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 468         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 469         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 470         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 471         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 472         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 473         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 474         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 475         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 476         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 477         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 478         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 479         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 480         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 481         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 482         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 483         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 484         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 485         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 486         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 487         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 488         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 489         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 490         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 491         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 492         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 493         FIELD(TPR_THRESHOLD, tpr_threshold),
 494         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 495         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 496         FIELD(VM_EXIT_REASON, vm_exit_reason),
 497         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 498         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 499         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 500         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 501         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 502         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 503         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 504         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 505         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 506         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 507         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 508         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 509         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 510         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 511         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 512         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 513         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 514         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 515         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 516         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 517         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 518         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 519         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 520         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 521         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 522         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 523         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 524         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 525         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 526         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 527         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 528         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 529         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 530         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 531         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 532         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 533         FIELD(EXIT_QUALIFICATION, exit_qualification),
 534         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 535         FIELD(GUEST_CR0, guest_cr0),
 536         FIELD(GUEST_CR3, guest_cr3),
 537         FIELD(GUEST_CR4, guest_cr4),
 538         FIELD(GUEST_ES_BASE, guest_es_base),
 539         FIELD(GUEST_CS_BASE, guest_cs_base),
 540         FIELD(GUEST_SS_BASE, guest_ss_base),
 541         FIELD(GUEST_DS_BASE, guest_ds_base),
 542         FIELD(GUEST_FS_BASE, guest_fs_base),
 543         FIELD(GUEST_GS_BASE, guest_gs_base),
 544         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 545         FIELD(GUEST_TR_BASE, guest_tr_base),
 546         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 547         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 548         FIELD(GUEST_DR7, guest_dr7),
 549         FIELD(GUEST_RSP, guest_rsp),
 550         FIELD(GUEST_RIP, guest_rip),
 551         FIELD(GUEST_RFLAGS, guest_rflags),
 552         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 553         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 554         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 555         FIELD(HOST_CR0, host_cr0),
 556         FIELD(HOST_CR3, host_cr3),
 557         FIELD(HOST_CR4, host_cr4),
 558         FIELD(HOST_FS_BASE, host_fs_base),
 559         FIELD(HOST_GS_BASE, host_gs_base),
 560         FIELD(HOST_TR_BASE, host_tr_base),
 561         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 562         FIELD(HOST_IDTR_BASE, host_idtr_base),
 563         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 564         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 565         FIELD(HOST_RSP, host_rsp),
 566         FIELD(HOST_RIP, host_rip),
 567 };
 568 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 569
 570 static inline short vmcs_field_to_offset(unsigned long field)
 571 {
 572         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 573                 return -1;
 574         return vmcs_field_to_offset_table[field];
 575 }
 576
 577 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 578 {
 579         return to_vmx(vcpu)->nested.current_vmcs12;
 580 }
 581
 582 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 583 {
 584         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 585         if (is_error_page(page)) {
 586                 kvm_release_page_clean(page);
 587                 return NULL;
 588         }
 589         return page;
 590 }
 591
 592 static void nested_release_page(struct page *page)
 593 {
 594         kvm_release_page_dirty(page);
 595 }
 596
 597 static void nested_release_page_clean(struct page *page)
 598 {
 599         kvm_release_page_clean(page);
 600 }
 601
 602 static u64 construct_eptp(unsigned long root_hpa);
 603 static void kvm_cpu_vmxon(u64 addr);
 604 static void kvm_cpu_vmxoff(void);
 605 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 606 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 607
 608 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 609 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 610 /*
 611  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 612  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 613  */
 614 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 615 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 616
 617 static unsigned long *vmx_io_bitmap_a;
 618 static unsigned long *vmx_io_bitmap_b;
 619 static unsigned long *vmx_msr_bitmap_legacy;
 620 static unsigned long *vmx_msr_bitmap_longmode;
 621
 622 static bool cpu_has_load_ia32_efer;
 623
 624 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 625 static DEFINE_SPINLOCK(vmx_vpid_lock);
 626
 627 static struct vmcs_config {
 628         int size;
 629         int order;
 630         u32 revision_id;
 631         u32 pin_based_exec_ctrl;
 632         u32 cpu_based_exec_ctrl;
 633         u32 cpu_based_2nd_exec_ctrl;
 634         u32 vmexit_ctrl;
 635         u32 vmentry_ctrl;
 636 } vmcs_config;
 637
 638 static struct vmx_capability {
 639         u32 ept;
 640         u32 vpid;
 641 } vmx_capability;
 642
 643 #define VMX_SEGMENT_FIELD(seg)                                  \
 644         [VCPU_SREG_##seg] = {                                   \
 645                 .selector = GUEST_##seg##_SELECTOR,             \
 646                 .base = GUEST_##seg##_BASE,                     \
 647                 .limit = GUEST_##seg##_LIMIT,                   \
 648                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 649         }
 650
 651 static struct kvm_vmx_segment_field {
 652         unsigned selector;
 653         unsigned base;
 654         unsigned limit;
 655         unsigned ar_bytes;
 656 } kvm_vmx_segment_fields[] = {
 657         VMX_SEGMENT_FIELD(CS),
 658         VMX_SEGMENT_FIELD(DS),
 659         VMX_SEGMENT_FIELD(ES),
 660         VMX_SEGMENT_FIELD(FS),
 661         VMX_SEGMENT_FIELD(GS),
 662         VMX_SEGMENT_FIELD(SS),
 663         VMX_SEGMENT_FIELD(TR),
 664         VMX_SEGMENT_FIELD(LDTR),
 665 };
 666
 667 static u64 host_efer;
 668
 669 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 670
 671 /*
 672  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 673  * away by decrementing the array size.
 674  */
 675 static const u32 vmx_msr_index[] = {
 676 #ifdef CONFIG_X86_64
 677         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 678 #endif
 679         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 680 };
 681 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 682
 683 static inline bool is_page_fault(u32 intr_info)
 684 {
 685         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 686                              INTR_INFO_VALID_MASK)) ==
 687                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 688 }
 689
 690 static inline bool is_no_device(u32 intr_info)
 691 {
 692         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 693                              INTR_INFO_VALID_MASK)) ==
 694                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 695 }
 696
 697 static inline bool is_invalid_opcode(u32 intr_info)
 698 {
 699         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 700                              INTR_INFO_VALID_MASK)) ==
 701                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 702 }
 703
 704 static inline bool is_external_interrupt(u32 intr_info)
 705 {
 706         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 707                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 708 }
 709
 710 static inline bool is_machine_check(u32 intr_info)
 711 {
 712         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 713                              INTR_INFO_VALID_MASK)) ==
 714                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 715 }
 716
 717 static inline bool cpu_has_vmx_msr_bitmap(void)
 718 {
 719         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 720 }
 721
 722 static inline bool cpu_has_vmx_tpr_shadow(void)
 723 {
 724         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 725 }
 726
 727 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 728 {
 729         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 730 }
 731
 732 static inline bool cpu_has_secondary_exec_ctrls(void)
 733 {
 734         return vmcs_config.cpu_based_exec_ctrl &
 735                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 736 }
 737
 738 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 739 {
 740         return vmcs_config.cpu_based_2nd_exec_ctrl &
 741                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 742 }
 743
 744 static inline bool cpu_has_vmx_flexpriority(void)
 745 {
 746         return cpu_has_vmx_tpr_shadow() &&
 747                 cpu_has_vmx_virtualize_apic_accesses();
 748 }
 749
 750 static inline bool cpu_has_vmx_ept_execute_only(void)
 751 {
 752         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 753 }
 754
 755 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 756 {
 757         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 758 }
 759
 760 static inline bool cpu_has_vmx_eptp_writeback(void)
 761 {
 762         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 763 }
 764
 765 static inline bool cpu_has_vmx_ept_2m_page(void)
 766 {
 767         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 768 }
 769
 770 static inline bool cpu_has_vmx_ept_1g_page(void)
 771 {
 772         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 773 }
 774
 775 static inline bool cpu_has_vmx_ept_4levels(void)
 776 {
 777         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 778 }
 779
 780 static inline bool cpu_has_vmx_invept_individual_addr(void)
 781 {
 782         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 783 }
 784
 785 static inline bool cpu_has_vmx_invept_context(void)
 786 {
 787         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 788 }
 789
 790 static inline bool cpu_has_vmx_invept_global(void)
 791 {
 792         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 793 }
 794
 795 static inline bool cpu_has_vmx_invvpid_single(void)
 796 {
 797         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 798 }
 799
 800 static inline bool cpu_has_vmx_invvpid_global(void)
 801 {
 802         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 803 }
 804
 805 static inline bool cpu_has_vmx_ept(void)
 806 {
 807         return vmcs_config.cpu_based_2nd_exec_ctrl &
 808                 SECONDARY_EXEC_ENABLE_EPT;
 809 }
 810
 811 static inline bool cpu_has_vmx_unrestricted_guest(void)
 812 {
 813         return vmcs_config.cpu_based_2nd_exec_ctrl &
 814                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 815 }
 816
 817 static inline bool cpu_has_vmx_ple(void)
 818 {
 819         return vmcs_config.cpu_based_2nd_exec_ctrl &
 820                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 821 }
 822
 823 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 824 {
 825         return flexpriority_enabled && irqchip_in_kernel(kvm);
 826 }
 827
 828 static inline bool cpu_has_vmx_vpid(void)
 829 {
 830         return vmcs_config.cpu_based_2nd_exec_ctrl &
 831                 SECONDARY_EXEC_ENABLE_VPID;
 832 }
 833
 834 static inline bool cpu_has_vmx_rdtscp(void)
 835 {
 836         return vmcs_config.cpu_based_2nd_exec_ctrl &
 837                 SECONDARY_EXEC_RDTSCP;
 838 }
 839
 840 static inline bool cpu_has_virtual_nmis(void)
 841 {
 842         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 843 }
 844
 845 static inline bool cpu_has_vmx_wbinvd_exit(void)
 846 {
 847         return vmcs_config.cpu_based_2nd_exec_ctrl &
 848                 SECONDARY_EXEC_WBINVD_EXITING;
 849 }
 850
 851 static inline bool report_flexpriority(void)
 852 {
 853         return flexpriority_enabled;
 854 }
 855
 856 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 857 {
 858         return vmcs12->cpu_based_vm_exec_control & bit;
 859 }
 860
 861 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 862 {
 863         return (vmcs12->cpu_based_vm_exec_control &
 864                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 865                 (vmcs12->secondary_vm_exec_control & bit);
 866 }
 867
 868 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 869                         struct vmcs12 *vmcs12,
 870                         u32 reason, unsigned long qualification);
 871
 872 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 873 {
 874         int i;
 875
 876         for (i = 0; i < vmx->nmsrs; ++i)
 877                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 878                         return i;
 879         return -1;
 880 }
 881
 882 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 883 {
 884     struct {
 885         u64 vpid : 16;
 886         u64 rsvd : 48;
 887         u64 gva;
 888     } operand = { vpid, 0, gva };
 889
 890     asm volatile (__ex(ASM_VMX_INVVPID)
 891                   /* CF==1 or ZF==1 --> rc = -1 */
 892                   "; ja 1f ; ud2 ; 1:"
 893                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 894 }
 895
 896 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 897 {
 898         struct {
 899                 u64 eptp, gpa;
 900         } operand = {eptp, gpa};
 901
 902         asm volatile (__ex(ASM_VMX_INVEPT)
 903                         /* CF==1 or ZF==1 --> rc = -1 */
 904                         "; ja 1f ; ud2 ; 1:\n"
 905                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 906 }
 907
 908 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 909 {
 910         int i;
 911
 912         i = __find_msr_index(vmx, msr);
 913         if (i >= 0)
 914                 return &vmx->guest_msrs[i];
 915         return NULL;
 916 }
 917
 918 static void vmcs_clear(struct vmcs *vmcs)
 919 {
 920         u64 phys_addr = __pa(vmcs);
 921         u8 error;
 922
 923         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 924                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 925                       : "cc", "memory");
 926         if (error)
 927                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 928                        vmcs, phys_addr);
 929 }
 930
 931 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 932 {
 933         vmcs_clear(loaded_vmcs->vmcs);
 934         loaded_vmcs->cpu = -1;
 935         loaded_vmcs->launched = 0;
 936 }
 937
 938 static void vmcs_load(struct vmcs *vmcs)
 939 {
 940         u64 phys_addr = __pa(vmcs);
 941         u8 error;
 942
 943         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 944                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 945                         : "cc", "memory");
 946         if (error)
 947                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 948                        vmcs, phys_addr);
 949 }
 950
 951 static void __loaded_vmcs_clear(void *arg)
 952 {
 953         struct loaded_vmcs *loaded_vmcs = arg;
 954         int cpu = raw_smp_processor_id();
 955
 956         if (loaded_vmcs->cpu != cpu)
 957                 return; /* vcpu migration can race with cpu offline */
 958         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 959                 per_cpu(current_vmcs, cpu) = NULL;
 960         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 961         loaded_vmcs_init(loaded_vmcs);
 962 }
 963
 964 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 965 {
 966         if (loaded_vmcs->cpu != -1)
 967                 smp_call_function_single(
 968                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 969 }
 970
 971 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 972 {
 973         if (vmx->vpid == 0)
 974                 return;
 975
 976         if (cpu_has_vmx_invvpid_single())
 977                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 978 }
 979
 980 static inline void vpid_sync_vcpu_global(void)
 981 {
 982         if (cpu_has_vmx_invvpid_global())
 983                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 984 }
 985
 986 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 987 {
 988         if (cpu_has_vmx_invvpid_single())
 989                 vpid_sync_vcpu_single(vmx);
 990         else
 991                 vpid_sync_vcpu_global();
 992 }
 993
 994 static inline void ept_sync_global(void)
 995 {
 996         if (cpu_has_vmx_invept_global())
 997                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 998 }
 999
1000 static inline void ept_sync_context(u64 eptp)
1001 {
1002         if (enable_ept) {
1003                 if (cpu_has_vmx_invept_context())
1004                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1005                 else
1006                         ept_sync_global();
1007         }
1008 }
1009
1010 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1011 {
1012         if (enable_ept) {
1013                 if (cpu_has_vmx_invept_individual_addr())
1014                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1015                                         eptp, gpa);
1016                 else
1017                         ept_sync_context(eptp);
1018         }
1019 }
1020
1021 static __always_inline unsigned long vmcs_readl(unsigned long field)
1022 {
1023         unsigned long value;
1024
1025         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1026                       : "=a"(value) : "d"(field) : "cc");
1027         return value;
1028 }
1029
1030 static __always_inline u16 vmcs_read16(unsigned long field)
1031 {
1032         return vmcs_readl(field);
1033 }
1034
1035 static __always_inline u32 vmcs_read32(unsigned long field)
1036 {
1037         return vmcs_readl(field);
1038 }
1039
1040 static __always_inline u64 vmcs_read64(unsigned long field)
1041 {
1042 #ifdef CONFIG_X86_64
1043         return vmcs_readl(field);
1044 #else
1045         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1046 #endif
1047 }
1048
1049 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1050 {
1051         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1052                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1053         dump_stack();
1054 }
1055
1056 static void vmcs_writel(unsigned long field, unsigned long value)
1057 {
1058         u8 error;
1059
1060         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1061                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1062         if (unlikely(error))
1063                 vmwrite_error(field, value);
1064 }
1065
1066 static void vmcs_write16(unsigned long field, u16 value)
1067 {
1068         vmcs_writel(field, value);
1069 }
1070
1071 static void vmcs_write32(unsigned long field, u32 value)
1072 {
1073         vmcs_writel(field, value);
1074 }
1075
1076 static void vmcs_write64(unsigned long field, u64 value)
1077 {
1078         vmcs_writel(field, value);
1079 #ifndef CONFIG_X86_64
1080         asm volatile ("");
1081         vmcs_writel(field+1, value >> 32);
1082 #endif
1083 }
1084
1085 static void vmcs_clear_bits(unsigned long field, u32 mask)
1086 {
1087         vmcs_writel(field, vmcs_readl(field) & ~mask);
1088 }
1089
1090 static void vmcs_set_bits(unsigned long field, u32 mask)
1091 {
1092         vmcs_writel(field, vmcs_readl(field) | mask);
1093 }
1094
1095 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1096 {
1097         vmx->segment_cache.bitmask = 0;
1098 }
1099
1100 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1101                                        unsigned field)
1102 {
1103         bool ret;
1104         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1105
1106         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1107                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1108                 vmx->segment_cache.bitmask = 0;
1109         }
1110         ret = vmx->segment_cache.bitmask & mask;
1111         vmx->segment_cache.bitmask |= mask;
1112         return ret;
1113 }
1114
1115 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1116 {
1117         u16 *p = &vmx->segment_cache.seg[seg].selector;
1118
1119         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1120                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1121         return *p;
1122 }
1123
1124 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1125 {
1126         ulong *p = &vmx->segment_cache.seg[seg].base;
1127
1128         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1129                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1130         return *p;
1131 }
1132
1133 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1134 {
1135         u32 *p = &vmx->segment_cache.seg[seg].limit;
1136
1137         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1138                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1139         return *p;
1140 }
1141
1142 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1143 {
1144         u32 *p = &vmx->segment_cache.seg[seg].ar;
1145
1146         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1147                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1148         return *p;
1149 }
1150
1151 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1152 {
1153         u32 eb;
1154
1155         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1156              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1157         if ((vcpu->guest_debug &
1158              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1159             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1160                 eb |= 1u << BP_VECTOR;
1161         if (to_vmx(vcpu)->rmode.vm86_active)
1162                 eb = ~0;
1163         if (enable_ept)
1164                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1165         if (vcpu->fpu_active)
1166                 eb &= ~(1u << NM_VECTOR);
1167         vmcs_write32(EXCEPTION_BITMAP, eb);
1168 }
1169
1170 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1171 {
1172         unsigned i;
1173         struct msr_autoload *m = &vmx->msr_autoload;
1174
1175         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1176                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1177                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1178                 return;
1179         }
1180
1181         for (i = 0; i < m->nr; ++i)
1182                 if (m->guest[i].index == msr)
1183                         break;
1184
1185         if (i == m->nr)
1186                 return;
1187         --m->nr;
1188         m->guest[i] = m->guest[m->nr];
1189         m->host[i] = m->host[m->nr];
1190         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1191         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1192 }
1193
1194 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1195                                   u64 guest_val, u64 host_val)
1196 {
1197         unsigned i;
1198         struct msr_autoload *m = &vmx->msr_autoload;
1199
1200         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1201                 vmcs_write64(GUEST_IA32_EFER, guest_val);
1202                 vmcs_write64(HOST_IA32_EFER, host_val);
1203                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1204                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1205                 return;
1206         }
1207
1208         for (i = 0; i < m->nr; ++i)
1209                 if (m->guest[i].index == msr)
1210                         break;
1211
1212         if (i == m->nr) {
1213                 ++m->nr;
1214                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1215                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1216         }
1217
1218         m->guest[i].index = msr;
1219         m->guest[i].value = guest_val;
1220         m->host[i].index = msr;
1221         m->host[i].value = host_val;
1222 }
1223
1224 static void reload_tss(void)
1225 {
1226         /*
1227          * VT restores TR but not its size.  Useless.
1228          */
1229         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1230         struct desc_struct *descs;
1231
1232         descs = (void *)gdt->address;
1233         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1234         load_TR_desc();
1235 }
1236
1237 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1238 {
1239         u64 guest_efer;
1240         u64 ignore_bits;
1241
1242         guest_efer = vmx->vcpu.arch.efer;
1243
1244         /*
1245          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1246          * outside long mode
1247          */
1248         ignore_bits = EFER_NX | EFER_SCE;
1249 #ifdef CONFIG_X86_64
1250         ignore_bits |= EFER_LMA | EFER_LME;
1251         /* SCE is meaningful only in long mode on Intel */
1252         if (guest_efer & EFER_LMA)
1253                 ignore_bits &= ~(u64)EFER_SCE;
1254 #endif
1255         guest_efer &= ~ignore_bits;
1256         guest_efer |= host_efer & ignore_bits;
1257         vmx->guest_msrs[efer_offset].data = guest_efer;
1258         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1259
1260         clear_atomic_switch_msr(vmx, MSR_EFER);
1261         /* On ept, can't emulate nx, and must switch nx atomically */
1262         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1263                 guest_efer = vmx->vcpu.arch.efer;
1264                 if (!(guest_efer & EFER_LMA))
1265                         guest_efer &= ~EFER_LME;
1266                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1267                 return false;
1268         }
1269
1270         return true;
1271 }
1272
1273 static unsigned long segment_base(u16 selector)
1274 {
1275         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1276         struct desc_struct *d;
1277         unsigned long table_base;
1278         unsigned long v;
1279
1280         if (!(selector & ~3))
1281                 return 0;
1282
1283         table_base = gdt->address;
1284
1285         if (selector & 4) {           /* from ldt */
1286                 u16 ldt_selector = kvm_read_ldt();
1287
1288                 if (!(ldt_selector & ~3))
1289                         return 0;
1290
1291                 table_base = segment_base(ldt_selector);
1292         }
1293         d = (struct desc_struct *)(table_base + (selector & ~7));
1294         v = get_desc_base(d);
1295 #ifdef CONFIG_X86_64
1296        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1297                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1298 #endif
1299         return v;
1300 }
1301
1302 static inline unsigned long kvm_read_tr_base(void)
1303 {
1304         u16 tr;
1305         asm("str %0" : "=g"(tr));
1306         return segment_base(tr);
1307 }
1308
1309 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1310 {
1311         struct vcpu_vmx *vmx = to_vmx(vcpu);
1312         int i;
1313
1314         if (vmx->host_state.loaded)
1315                 return;
1316
1317         vmx->host_state.loaded = 1;
1318         /*
1319          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1320          * allow segment selectors with cpl > 0 or ti == 1.
1321          */
1322         vmx->host_state.ldt_sel = kvm_read_ldt();
1323         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1324         savesegment(fs, vmx->host_state.fs_sel);
1325         if (!(vmx->host_state.fs_sel & 7)) {
1326                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1327                 vmx->host_state.fs_reload_needed = 0;
1328         } else {
1329                 vmcs_write16(HOST_FS_SELECTOR, 0);
1330                 vmx->host_state.fs_reload_needed = 1;
1331         }
1332         savesegment(gs, vmx->host_state.gs_sel);
1333         if (!(vmx->host_state.gs_sel & 7))
1334                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1335         else {
1336                 vmcs_write16(HOST_GS_SELECTOR, 0);
1337                 vmx->host_state.gs_ldt_reload_needed = 1;
1338         }
1339
1340 #ifdef CONFIG_X86_64
1341         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1342         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1343 #else
1344         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1345         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1346 #endif
1347
1348 #ifdef CONFIG_X86_64
1349         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1350         if (is_long_mode(&vmx->vcpu))
1351                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1352 #endif
1353         for (i = 0; i < vmx->save_nmsrs; ++i)
1354                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1355                                    vmx->guest_msrs[i].data,
1356                                    vmx->guest_msrs[i].mask);
1357 }
1358
1359 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1360 {
1361         if (!vmx->host_state.loaded)
1362                 return;
1363
1364         ++vmx->vcpu.stat.host_state_reload;
1365         vmx->host_state.loaded = 0;
1366 #ifdef CONFIG_X86_64
1367         if (is_long_mode(&vmx->vcpu))
1368                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1369 #endif
1370         if (vmx->host_state.gs_ldt_reload_needed) {
1371                 kvm_load_ldt(vmx->host_state.ldt_sel);
1372 #ifdef CONFIG_X86_64
1373                 load_gs_index(vmx->host_state.gs_sel);
1374 #else
1375                 loadsegment(gs, vmx->host_state.gs_sel);
1376 #endif
1377         }
1378         if (vmx->host_state.fs_reload_needed)
1379                 loadsegment(fs, vmx->host_state.fs_sel);
1380         reload_tss();
1381 #ifdef CONFIG_X86_64
1382         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1383 #endif
1384         if (current_thread_info()->status & TS_USEDFPU)
1385                 clts();
1386         load_gdt(&__get_cpu_var(host_gdt));
1387 }
1388
1389 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1390 {
1391         preempt_disable();
1392         __vmx_load_host_state(vmx);
1393         preempt_enable();
1394 }
1395
1396 /*
1397  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1398  * vcpu mutex is already taken.
1399  */
1400 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1401 {
1402         struct vcpu_vmx *vmx = to_vmx(vcpu);
1403         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1404
1405         if (!vmm_exclusive)
1406                 kvm_cpu_vmxon(phys_addr);
1407         else if (vmx->loaded_vmcs->cpu != cpu)
1408                 loaded_vmcs_clear(vmx->loaded_vmcs);
1409
1410         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1411                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1412                 vmcs_load(vmx->loaded_vmcs->vmcs);
1413         }
1414
1415         if (vmx->loaded_vmcs->cpu != cpu) {
1416                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1417                 unsigned long sysenter_esp;
1418
1419                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1420                 local_irq_disable();
1421                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1422                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1423                 local_irq_enable();
1424
1425                 /*
1426                  * Linux uses per-cpu TSS and GDT, so set these when switching
1427                  * processors.
1428                  */
1429                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1430                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1431
1432                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1433                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1434                 vmx->loaded_vmcs->cpu = cpu;
1435         }
1436 }
1437
1438 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1439 {
1440         __vmx_load_host_state(to_vmx(vcpu));
1441         if (!vmm_exclusive) {
1442                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1443                 vcpu->cpu = -1;
1444                 kvm_cpu_vmxoff();
1445         }
1446 }
1447
1448 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1449 {
1450         ulong cr0;
1451
1452         if (vcpu->fpu_active)
1453                 return;
1454         vcpu->fpu_active = 1;
1455         cr0 = vmcs_readl(GUEST_CR0);
1456         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1457         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1458         vmcs_writel(GUEST_CR0, cr0);
1459         update_exception_bitmap(vcpu);
1460         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1461         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1462 }
1463
1464 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1465
1466 /*
1467  * Return the cr0 value that a nested guest would read. This is a combination
1468  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1469  * its hypervisor (cr0_read_shadow).
1470  */
1471 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1472 {
1473         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1474                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1475 }
1476 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1477 {
1478         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1479                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1480 }
1481
1482 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1483 {
1484         vmx_decache_cr0_guest_bits(vcpu);
1485         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1486         update_exception_bitmap(vcpu);
1487         vcpu->arch.cr0_guest_owned_bits = 0;
1488         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1489         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1490 }
1491
1492 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1493 {
1494         unsigned long rflags, save_rflags;
1495
1496         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1497                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1498                 rflags = vmcs_readl(GUEST_RFLAGS);
1499                 if (to_vmx(vcpu)->rmode.vm86_active) {
1500                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1501                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1502                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1503                 }
1504                 to_vmx(vcpu)->rflags = rflags;
1505         }
1506         return to_vmx(vcpu)->rflags;
1507 }
1508
1509 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1510 {
1511         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1512         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1513         to_vmx(vcpu)->rflags = rflags;
1514         if (to_vmx(vcpu)->rmode.vm86_active) {
1515                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1516                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1517         }
1518         vmcs_writel(GUEST_RFLAGS, rflags);
1519 }
1520
1521 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1522 {
1523         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1524         int ret = 0;
1525
1526         if (interruptibility & GUEST_INTR_STATE_STI)
1527                 ret |= KVM_X86_SHADOW_INT_STI;
1528         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1529                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1530
1531         return ret & mask;
1532 }
1533
1534 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1535 {
1536         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1537         u32 interruptibility = interruptibility_old;
1538
1539         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1540
1541         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1542                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1543         else if (mask & KVM_X86_SHADOW_INT_STI)
1544                 interruptibility |= GUEST_INTR_STATE_STI;
1545
1546         if ((interruptibility != interruptibility_old))
1547                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1548 }
1549
1550 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1551 {
1552         unsigned long rip;
1553
1554         rip = kvm_rip_read(vcpu);
1555         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1556         kvm_rip_write(vcpu, rip);
1557
1558         /* skipping an emulated instruction also counts */
1559         vmx_set_interrupt_shadow(vcpu, 0);
1560 }
1561
1562 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1563 {
1564         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1565          * explicitly skip the instruction because if the HLT state is set, then
1566          * the instruction is already executing and RIP has already been
1567          * advanced. */
1568         if (!yield_on_hlt &&
1569             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1570                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1571 }
1572
1573 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1574                                 bool has_error_code, u32 error_code,
1575                                 bool reinject)
1576 {
1577         struct vcpu_vmx *vmx = to_vmx(vcpu);
1578         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1579
1580         if (has_error_code) {
1581                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1582                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1583         }
1584
1585         if (vmx->rmode.vm86_active) {
1586                 int inc_eip = 0;
1587                 if (kvm_exception_is_soft(nr))
1588                         inc_eip = vcpu->arch.event_exit_inst_len;
1589                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1590                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1591                 return;
1592         }
1593
1594         if (kvm_exception_is_soft(nr)) {
1595                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1596                              vmx->vcpu.arch.event_exit_inst_len);
1597                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1598         } else
1599                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1600
1601         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1602         vmx_clear_hlt(vcpu);
1603 }
1604
1605 static bool vmx_rdtscp_supported(void)
1606 {
1607         return cpu_has_vmx_rdtscp();
1608 }
1609
1610 /*
1611  * Swap MSR entry in host/guest MSR entry array.
1612  */
1613 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1614 {
1615         struct shared_msr_entry tmp;
1616
1617         tmp = vmx->guest_msrs[to];
1618         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1619         vmx->guest_msrs[from] = tmp;
1620 }
1621
1622 /*
1623  * Set up the vmcs to automatically save and restore system
1624  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1625  * mode, as fiddling with msrs is very expensive.
1626  */
1627 static void setup_msrs(struct vcpu_vmx *vmx)
1628 {
1629         int save_nmsrs, index;
1630         unsigned long *msr_bitmap;
1631
1632         vmx_load_host_state(vmx);
1633         save_nmsrs = 0;
1634 #ifdef CONFIG_X86_64
1635         if (is_long_mode(&vmx->vcpu)) {
1636                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1637                 if (index >= 0)
1638                         move_msr_up(vmx, index, save_nmsrs++);
1639                 index = __find_msr_index(vmx, MSR_LSTAR);
1640                 if (index >= 0)
1641                         move_msr_up(vmx, index, save_nmsrs++);
1642                 index = __find_msr_index(vmx, MSR_CSTAR);
1643                 if (index >= 0)
1644                         move_msr_up(vmx, index, save_nmsrs++);
1645                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1646                 if (index >= 0 && vmx->rdtscp_enabled)
1647                         move_msr_up(vmx, index, save_nmsrs++);
1648                 /*
1649                  * MSR_STAR is only needed on long mode guests, and only
1650                  * if efer.sce is enabled.
1651                  */
1652                 index = __find_msr_index(vmx, MSR_STAR);
1653                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1654                         move_msr_up(vmx, index, save_nmsrs++);
1655         }
1656 #endif
1657         index = __find_msr_index(vmx, MSR_EFER);
1658         if (index >= 0 && update_transition_efer(vmx, index))
1659                 move_msr_up(vmx, index, save_nmsrs++);
1660
1661         vmx->save_nmsrs = save_nmsrs;
1662
1663         if (cpu_has_vmx_msr_bitmap()) {
1664                 if (is_long_mode(&vmx->vcpu))
1665                         msr_bitmap = vmx_msr_bitmap_longmode;
1666                 else
1667                         msr_bitmap = vmx_msr_bitmap_legacy;
1668
1669                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1670         }
1671 }
1672
1673 /*
1674  * reads and returns guest's timestamp counter "register"
1675  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1676  */
1677 static u64 guest_read_tsc(void)
1678 {
1679         u64 host_tsc, tsc_offset;
1680
1681         rdtscll(host_tsc);
1682         tsc_offset = vmcs_read64(TSC_OFFSET);
1683         return host_tsc + tsc_offset;
1684 }
1685
1686 /*
1687  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1688  * ioctl. In this case the call-back should update internal vmx state to make
1689  * the changes effective.
1690  */
1691 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1692 {
1693         /* Nothing to do here */
1694 }
1695
1696 /*
1697  * writes 'offset' into guest's timestamp counter offset register
1698  */
1699 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1700 {
1701         vmcs_write64(TSC_OFFSET, offset);
1702 }
1703
1704 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1705 {
1706         u64 offset = vmcs_read64(TSC_OFFSET);
1707         vmcs_write64(TSC_OFFSET, offset + adjustment);
1708 }
1709
1710 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1711 {
1712         return target_tsc - native_read_tsc();
1713 }
1714
1715 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1716 {
1717         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1718         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1719 }
1720
1721 /*
1722  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1723  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1724  * all guests if the "nested" module option is off, and can also be disabled
1725  * for a single guest by disabling its VMX cpuid bit.
1726  */
1727 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1728 {
1729         return nested && guest_cpuid_has_vmx(vcpu);
1730 }
1731
1732 /*
1733  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1734  * returned for the various VMX controls MSRs when nested VMX is enabled.
1735  * The same values should also be used to verify that vmcs12 control fields are
1736  * valid during nested entry from L1 to L2.
1737  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1738  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1739  * bit in the high half is on if the corresponding bit in the control field
1740  * may be on. See also vmx_control_verify().
1741  * TODO: allow these variables to be modified (downgraded) by module options
1742  * or other means.
1743  */
1744 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1745 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1746 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1747 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1748 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1749 static __init void nested_vmx_setup_ctls_msrs(void)
1750 {
1751         /*
1752          * Note that as a general rule, the high half of the MSRs (bits in
1753          * the control fields which may be 1) should be initialized by the
1754          * intersection of the underlying hardware's MSR (i.e., features which
1755          * can be supported) and the list of features we want to expose -
1756          * because they are known to be properly supported in our code.
1757          * Also, usually, the low half of the MSRs (bits which must be 1) can
1758          * be set to 0, meaning that L1 may turn off any of these bits. The
1759          * reason is that if one of these bits is necessary, it will appear
1760          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1761          * fields of vmcs01 and vmcs02, will turn these bits off - and
1762          * nested_vmx_exit_handled() will not pass related exits to L1.
1763          * These rules have exceptions below.
1764          */
1765
1766         /* pin-based controls */
1767         /*
1768          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1769          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1770          */
1771         nested_vmx_pinbased_ctls_low = 0x16 ;
1772         nested_vmx_pinbased_ctls_high = 0x16 |
1773                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1774                 PIN_BASED_VIRTUAL_NMIS;
1775
1776         /* exit controls */
1777         nested_vmx_exit_ctls_low = 0;
1778 #ifdef CONFIG_X86_64
1779         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1780 #else
1781         nested_vmx_exit_ctls_high = 0;
1782 #endif
1783
1784         /* entry controls */
1785         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1786                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1787         nested_vmx_entry_ctls_low = 0;
1788         nested_vmx_entry_ctls_high &=
1789                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1790
1791         /* cpu-based controls */
1792         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1793                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1794         nested_vmx_procbased_ctls_low = 0;
1795         nested_vmx_procbased_ctls_high &=
1796                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1797                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1798                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1799                 CPU_BASED_CR3_STORE_EXITING |
1800 #ifdef CONFIG_X86_64
1801                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1802 #endif
1803                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1804                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1805                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1806         /*
1807          * We can allow some features even when not supported by the
1808          * hardware. For example, L1 can specify an MSR bitmap - and we
1809          * can use it to avoid exits to L1 - even when L0 runs L2
1810          * without MSR bitmaps.
1811          */
1812         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1813
1814         /* secondary cpu-based controls */
1815         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1816                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1817         nested_vmx_secondary_ctls_low = 0;
1818         nested_vmx_secondary_ctls_high &=
1819                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1820 }
1821
1822 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1823 {
1824         /*
1825          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1826          */
1827         return ((control & high) | low) == control;
1828 }
1829
1830 static inline u64 vmx_control_msr(u32 low, u32 high)
1831 {
1832         return low | ((u64)high << 32);
1833 }
1834
1835 /*
1836  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1837  * also let it use VMX-specific MSRs.
1838  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1839  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1840  * like all other MSRs).
1841  */
1842 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1843 {
1844         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1845                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1846                 /*
1847                  * According to the spec, processors which do not support VMX
1848                  * should throw a #GP(0) when VMX capability MSRs are read.
1849                  */
1850                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1851                 return 1;
1852         }
1853
1854         switch (msr_index) {
1855         case MSR_IA32_FEATURE_CONTROL:
1856                 *pdata = 0;
1857                 break;
1858         case MSR_IA32_VMX_BASIC:
1859                 /*
1860                  * This MSR reports some information about VMX support. We
1861                  * should return information about the VMX we emulate for the
1862                  * guest, and the VMCS structure we give it - not about the
1863                  * VMX support of the underlying hardware.
1864                  */
1865                 *pdata = VMCS12_REVISION |
1866                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1867                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1868                 break;
1869         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1870         case MSR_IA32_VMX_PINBASED_CTLS:
1871                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1872                                         nested_vmx_pinbased_ctls_high);
1873                 break;
1874         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1875         case MSR_IA32_VMX_PROCBASED_CTLS:
1876                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1877                                         nested_vmx_procbased_ctls_high);
1878                 break;
1879         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1880         case MSR_IA32_VMX_EXIT_CTLS:
1881                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1882                                         nested_vmx_exit_ctls_high);
1883                 break;
1884         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1885         case MSR_IA32_VMX_ENTRY_CTLS:
1886                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1887                                         nested_vmx_entry_ctls_high);
1888                 break;
1889         case MSR_IA32_VMX_MISC:
1890                 *pdata = 0;
1891                 break;
1892         /*
1893          * These MSRs specify bits which the guest must keep fixed (on or off)
1894          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1895          * We picked the standard core2 setting.
1896          */
1897 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1898 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
1899         case MSR_IA32_VMX_CR0_FIXED0:
1900                 *pdata = VMXON_CR0_ALWAYSON;
1901                 break;
1902         case MSR_IA32_VMX_CR0_FIXED1:
1903                 *pdata = -1ULL;
1904                 break;
1905         case MSR_IA32_VMX_CR4_FIXED0:
1906                 *pdata = VMXON_CR4_ALWAYSON;
1907                 break;
1908         case MSR_IA32_VMX_CR4_FIXED1:
1909                 *pdata = -1ULL;
1910                 break;
1911         case MSR_IA32_VMX_VMCS_ENUM:
1912                 *pdata = 0x1f;
1913                 break;
1914         case MSR_IA32_VMX_PROCBASED_CTLS2:
1915                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1916                                         nested_vmx_secondary_ctls_high);
1917                 break;
1918         case MSR_IA32_VMX_EPT_VPID_CAP:
1919                 /* Currently, no nested ept or nested vpid */
1920                 *pdata = 0;
1921                 break;
1922         default:
1923                 return 0;
1924         }
1925
1926         return 1;
1927 }
1928
1929 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1930 {
1931         if (!nested_vmx_allowed(vcpu))
1932                 return 0;
1933
1934         if (msr_index == MSR_IA32_FEATURE_CONTROL)
1935                 /* TODO: the right thing. */
1936                 return 1;
1937         /*
1938          * No need to treat VMX capability MSRs specially: If we don't handle
1939          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1940          */
1941         return 0;
1942 }
1943
1944 /*
1945  * Reads an msr value (of 'msr_index') into 'pdata'.
1946  * Returns 0 on success, non-0 otherwise.
1947  * Assumes vcpu_load() was already called.
1948  */
1949 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1950 {
1951         u64 data;
1952         struct shared_msr_entry *msr;
1953
1954         if (!pdata) {
1955                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1956                 return -EINVAL;
1957         }
1958
1959         switch (msr_index) {
1960 #ifdef CONFIG_X86_64
1961         case MSR_FS_BASE:
1962                 data = vmcs_readl(GUEST_FS_BASE);
1963                 break;
1964         case MSR_GS_BASE:
1965                 data = vmcs_readl(GUEST_GS_BASE);
1966                 break;
1967         case MSR_KERNEL_GS_BASE:
1968                 vmx_load_host_state(to_vmx(vcpu));
1969                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1970                 break;
1971 #endif
1972         case MSR_EFER:
1973                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1974         case MSR_IA32_TSC:
1975                 data = guest_read_tsc();
1976                 break;
1977         case MSR_IA32_SYSENTER_CS:
1978                 data = vmcs_read32(GUEST_SYSENTER_CS);
1979                 break;
1980         case MSR_IA32_SYSENTER_EIP:
1981                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1982                 break;
1983         case MSR_IA32_SYSENTER_ESP:
1984                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1985                 break;
1986         case MSR_TSC_AUX:
1987                 if (!to_vmx(vcpu)->rdtscp_enabled)
1988                         return 1;
1989                 /* Otherwise falls through */
1990         default:
1991                 vmx_load_host_state(to_vmx(vcpu));
1992                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
1993                         return 0;
1994                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1995                 if (msr) {
1996                         vmx_load_host_state(to_vmx(vcpu));
1997                         data = msr->data;
1998                         break;
1999                 }
2000                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2001         }
2002
2003         *pdata = data;
2004         return 0;
2005 }
2006
2007 /*
2008  * Writes msr value into into the appropriate "register".
2009  * Returns 0 on success, non-0 otherwise.
2010  * Assumes vcpu_load() was already called.
2011  */
2012 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2013 {
2014         struct vcpu_vmx *vmx = to_vmx(vcpu);
2015         struct shared_msr_entry *msr;
2016         int ret = 0;
2017
2018         switch (msr_index) {
2019         case MSR_EFER:
2020                 vmx_load_host_state(vmx);
2021                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2022                 break;
2023 #ifdef CONFIG_X86_64
2024         case MSR_FS_BASE:
2025                 vmx_segment_cache_clear(vmx);
2026                 vmcs_writel(GUEST_FS_BASE, data);
2027                 break;
2028         case MSR_GS_BASE:
2029                 vmx_segment_cache_clear(vmx);
2030                 vmcs_writel(GUEST_GS_BASE, data);
2031                 break;
2032         case MSR_KERNEL_GS_BASE:
2033                 vmx_load_host_state(vmx);
2034                 vmx->msr_guest_kernel_gs_base = data;
2035                 break;
2036 #endif
2037         case MSR_IA32_SYSENTER_CS:
2038                 vmcs_write32(GUEST_SYSENTER_CS, data);
2039                 break;
2040         case MSR_IA32_SYSENTER_EIP:
2041                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2042                 break;
2043         case MSR_IA32_SYSENTER_ESP:
2044                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2045                 break;
2046         case MSR_IA32_TSC:
2047                 kvm_write_tsc(vcpu, data);
2048                 break;
2049         case MSR_IA32_CR_PAT:
2050                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2051                         vmcs_write64(GUEST_IA32_PAT, data);
2052                         vcpu->arch.pat = data;
2053                         break;
2054                 }
2055                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2056                 break;
2057         case MSR_TSC_AUX:
2058                 if (!vmx->rdtscp_enabled)
2059                         return 1;
2060                 /* Check reserved bit, higher 32 bits should be zero */
2061                 if ((data >> 32) != 0)
2062                         return 1;
2063                 /* Otherwise falls through */
2064         default:
2065                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2066                         break;
2067                 msr = find_msr_entry(vmx, msr_index);
2068                 if (msr) {
2069                         vmx_load_host_state(vmx);
2070                         msr->data = data;
2071                         break;
2072                 }
2073                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2074         }
2075
2076         return ret;
2077 }
2078
2079 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2080 {
2081         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2082         switch (reg) {
2083         case VCPU_REGS_RSP:
2084                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2085                 break;
2086         case VCPU_REGS_RIP:
2087                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2088                 break;
2089         case VCPU_EXREG_PDPTR:
2090                 if (enable_ept)
2091                         ept_save_pdptrs(vcpu);
2092                 break;
2093         default:
2094                 break;
2095         }
2096 }
2097
2098 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2099 {
2100         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2101                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2102         else
2103                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2104
2105         update_exception_bitmap(vcpu);
2106 }
2107
2108 static __init int cpu_has_kvm_support(void)
2109 {
2110         return cpu_has_vmx();
2111 }
2112
2113 static __init int vmx_disabled_by_bios(void)
2114 {
2115         u64 msr;
2116
2117         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2118         if (msr & FEATURE_CONTROL_LOCKED) {
2119                 /* launched w/ TXT and VMX disabled */
2120                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2121                         && tboot_enabled())
2122                         return 1;
2123                 /* launched w/o TXT and VMX only enabled w/ TXT */
2124                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2125                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2126                         && !tboot_enabled()) {
2127                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2128                                 "activate TXT before enabling KVM\n");
2129                         return 1;
2130                 }
2131                 /* launched w/o TXT and VMX disabled */
2132                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2133                         && !tboot_enabled())
2134                         return 1;
2135         }
2136
2137         return 0;
2138 }
2139
2140 static void kvm_cpu_vmxon(u64 addr)
2141 {
2142         asm volatile (ASM_VMX_VMXON_RAX
2143                         : : "a"(&addr), "m"(addr)
2144                         : "memory", "cc");
2145 }
2146
2147 static int hardware_enable(void *garbage)
2148 {
2149         int cpu = raw_smp_processor_id();
2150         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2151         u64 old, test_bits;
2152
2153         if (read_cr4() & X86_CR4_VMXE)
2154                 return -EBUSY;
2155
2156         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2157         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2158
2159         test_bits = FEATURE_CONTROL_LOCKED;
2160         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2161         if (tboot_enabled())
2162                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2163
2164         if ((old & test_bits) != test_bits) {
2165                 /* enable and lock */
2166                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2167         }
2168         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2169
2170         if (vmm_exclusive) {
2171                 kvm_cpu_vmxon(phys_addr);
2172                 ept_sync_global();
2173         }
2174
2175         store_gdt(&__get_cpu_var(host_gdt));
2176
2177         return 0;
2178 }
2179
2180 static void vmclear_local_loaded_vmcss(void)
2181 {
2182         int cpu = raw_smp_processor_id();
2183         struct loaded_vmcs *v, *n;
2184
2185         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2186                                  loaded_vmcss_on_cpu_link)
2187                 __loaded_vmcs_clear(v);
2188 }
2189
2190
2191 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2192  * tricks.
2193  */
2194 static void kvm_cpu_vmxoff(void)
2195 {
2196         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2197 }
2198
2199 static void hardware_disable(void *garbage)
2200 {
2201         if (vmm_exclusive) {
2202                 vmclear_local_loaded_vmcss();
2203                 kvm_cpu_vmxoff();
2204         }
2205         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2206 }
2207
2208 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2209                                       u32 msr, u32 *result)
2210 {
2211         u32 vmx_msr_low, vmx_msr_high;
2212         u32 ctl = ctl_min | ctl_opt;
2213
2214         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2215
2216         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2217         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2218
2219         /* Ensure minimum (required) set of control bits are supported. */
2220         if (ctl_min & ~ctl)
2221                 return -EIO;
2222
2223         *result = ctl;
2224         return 0;
2225 }
2226
2227 static __init bool allow_1_setting(u32 msr, u32 ctl)
2228 {
2229         u32 vmx_msr_low, vmx_msr_high;
2230
2231         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2232         return vmx_msr_high & ctl;
2233 }
2234
2235 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2236 {
2237         u32 vmx_msr_low, vmx_msr_high;
2238         u32 min, opt, min2, opt2;
2239         u32 _pin_based_exec_control = 0;
2240         u32 _cpu_based_exec_control = 0;
2241         u32 _cpu_based_2nd_exec_control = 0;
2242         u32 _vmexit_control = 0;
2243         u32 _vmentry_control = 0;
2244
2245         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2246         opt = PIN_BASED_VIRTUAL_NMIS;
2247         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2248                                 &_pin_based_exec_control) < 0)
2249                 return -EIO;
2250
2251         min =
2252 #ifdef CONFIG_X86_64
2253               CPU_BASED_CR8_LOAD_EXITING |
2254               CPU_BASED_CR8_STORE_EXITING |
2255 #endif
2256               CPU_BASED_CR3_LOAD_EXITING |
2257               CPU_BASED_CR3_STORE_EXITING |
2258               CPU_BASED_USE_IO_BITMAPS |
2259               CPU_BASED_MOV_DR_EXITING |
2260               CPU_BASED_USE_TSC_OFFSETING |
2261               CPU_BASED_MWAIT_EXITING |
2262               CPU_BASED_MONITOR_EXITING |
2263               CPU_BASED_INVLPG_EXITING;
2264
2265         if (yield_on_hlt)
2266                 min |= CPU_BASED_HLT_EXITING;
2267
2268         opt = CPU_BASED_TPR_SHADOW |
2269               CPU_BASED_USE_MSR_BITMAPS |
2270               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2271         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2272                                 &_cpu_based_exec_control) < 0)
2273                 return -EIO;
2274 #ifdef CONFIG_X86_64
2275         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2276                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2277                                            ~CPU_BASED_CR8_STORE_EXITING;
2278 #endif
2279         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2280                 min2 = 0;
2281                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2282                         SECONDARY_EXEC_WBINVD_EXITING |
2283                         SECONDARY_EXEC_ENABLE_VPID |
2284                         SECONDARY_EXEC_ENABLE_EPT |
2285                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2286                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2287                         SECONDARY_EXEC_RDTSCP;
2288                 if (adjust_vmx_controls(min2, opt2,
2289                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2290                                         &_cpu_based_2nd_exec_control) < 0)
2291                         return -EIO;
2292         }
2293 #ifndef CONFIG_X86_64
2294         if (!(_cpu_based_2nd_exec_control &
2295                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2296                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2297 #endif
2298         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2299                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2300                    enabled */
2301                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2302                                              CPU_BASED_CR3_STORE_EXITING |
2303                                              CPU_BASED_INVLPG_EXITING);
2304                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2305                       vmx_capability.ept, vmx_capability.vpid);
2306         }
2307
2308         min = 0;
2309 #ifdef CONFIG_X86_64
2310         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2311 #endif
2312         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2313         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2314                                 &_vmexit_control) < 0)
2315                 return -EIO;
2316
2317         min = 0;
2318         opt = VM_ENTRY_LOAD_IA32_PAT;
2319         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2320                                 &_vmentry_control) < 0)
2321                 return -EIO;
2322
2323         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2324
2325         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2326         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2327                 return -EIO;
2328
2329 #ifdef CONFIG_X86_64
2330         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2331         if (vmx_msr_high & (1u<<16))
2332                 return -EIO;
2333 #endif
2334
2335         /* Require Write-Back (WB) memory type for VMCS accesses. */
2336         if (((vmx_msr_high >> 18) & 15) != 6)
2337                 return -EIO;
2338
2339         vmcs_conf->size = vmx_msr_high & 0x1fff;
2340         vmcs_conf->order = get_order(vmcs_config.size);
2341         vmcs_conf->revision_id = vmx_msr_low;
2342
2343         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2344         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2345         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2346         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2347         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2348
2349         cpu_has_load_ia32_efer =
2350                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2351                                 VM_ENTRY_LOAD_IA32_EFER)
2352                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2353                                    VM_EXIT_LOAD_IA32_EFER);
2354
2355         return 0;
2356 }
2357
2358 static struct vmcs *alloc_vmcs_cpu(int cpu)
2359 {
2360         int node = cpu_to_node(cpu);
2361         struct page *pages;
2362         struct vmcs *vmcs;
2363
2364         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2365         if (!pages)
2366                 return NULL;
2367         vmcs = page_address(pages);
2368         memset(vmcs, 0, vmcs_config.size);
2369         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2370         return vmcs;
2371 }
2372
2373 static struct vmcs *alloc_vmcs(void)
2374 {
2375         return alloc_vmcs_cpu(raw_smp_processor_id());
2376 }
2377
2378 static void free_vmcs(struct vmcs *vmcs)
2379 {
2380         free_pages((unsigned long)vmcs, vmcs_config.order);
2381 }
2382
2383 /*
2384  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2385  */
2386 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2387 {
2388         if (!loaded_vmcs->vmcs)
2389                 return;
2390         loaded_vmcs_clear(loaded_vmcs);
2391         free_vmcs(loaded_vmcs->vmcs);
2392         loaded_vmcs->vmcs = NULL;
2393 }
2394
2395 static void free_kvm_area(void)
2396 {
2397         int cpu;
2398
2399         for_each_possible_cpu(cpu) {
2400                 free_vmcs(per_cpu(vmxarea, cpu));
2401                 per_cpu(vmxarea, cpu) = NULL;
2402         }
2403 }
2404
2405 static __init int alloc_kvm_area(void)
2406 {
2407         int cpu;
2408
2409         for_each_possible_cpu(cpu) {
2410                 struct vmcs *vmcs;
2411
2412                 vmcs = alloc_vmcs_cpu(cpu);
2413                 if (!vmcs) {
2414                         free_kvm_area();
2415                         return -ENOMEM;
2416                 }
2417
2418                 per_cpu(vmxarea, cpu) = vmcs;
2419         }
2420         return 0;
2421 }
2422
2423 static __init int hardware_setup(void)
2424 {
2425         if (setup_vmcs_config(&vmcs_config) < 0)
2426                 return -EIO;
2427
2428         if (boot_cpu_has(X86_FEATURE_NX))
2429                 kvm_enable_efer_bits(EFER_NX);
2430
2431         if (!cpu_has_vmx_vpid())
2432                 enable_vpid = 0;
2433
2434         if (!cpu_has_vmx_ept() ||
2435             !cpu_has_vmx_ept_4levels()) {
2436                 enable_ept = 0;
2437                 enable_unrestricted_guest = 0;
2438         }
2439
2440         if (!cpu_has_vmx_unrestricted_guest())
2441                 enable_unrestricted_guest = 0;
2442
2443         if (!cpu_has_vmx_flexpriority())
2444                 flexpriority_enabled = 0;
2445
2446         if (!cpu_has_vmx_tpr_shadow())
2447                 kvm_x86_ops->update_cr8_intercept = NULL;
2448
2449         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2450                 kvm_disable_largepages();
2451
2452         if (!cpu_has_vmx_ple())
2453                 ple_gap = 0;
2454
2455         if (nested)
2456                 nested_vmx_setup_ctls_msrs();
2457
2458         return alloc_kvm_area();
2459 }
2460
2461 static __exit void hardware_unsetup(void)
2462 {
2463         free_kvm_area();
2464 }
2465
2466 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2467 {
2468         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2469
2470         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2471                 vmcs_write16(sf->selector, save->selector);
2472                 vmcs_writel(sf->base, save->base);
2473                 vmcs_write32(sf->limit, save->limit);
2474                 vmcs_write32(sf->ar_bytes, save->ar);
2475         } else {
2476                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2477                         << AR_DPL_SHIFT;
2478                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2479         }
2480 }
2481
2482 static void enter_pmode(struct kvm_vcpu *vcpu)
2483 {
2484         unsigned long flags;
2485         struct vcpu_vmx *vmx = to_vmx(vcpu);
2486
2487         vmx->emulation_required = 1;
2488         vmx->rmode.vm86_active = 0;
2489
2490         vmx_segment_cache_clear(vmx);
2491
2492         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2493         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2494         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2495         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2496
2497         flags = vmcs_readl(GUEST_RFLAGS);
2498         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2499         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2500         vmcs_writel(GUEST_RFLAGS, flags);
2501
2502         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2503                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2504
2505         update_exception_bitmap(vcpu);
2506
2507         if (emulate_invalid_guest_state)
2508                 return;
2509
2510         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2511         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2512         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2513         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2514
2515         vmx_segment_cache_clear(vmx);
2516
2517         vmcs_write16(GUEST_SS_SELECTOR, 0);
2518         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2519
2520         vmcs_write16(GUEST_CS_SELECTOR,
2521                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2522         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2523 }
2524
2525 static gva_t rmode_tss_base(struct kvm *kvm)
2526 {
2527         if (!kvm->arch.tss_addr) {
2528                 struct kvm_memslots *slots;
2529                 gfn_t base_gfn;
2530
2531                 slots = kvm_memslots(kvm);
2532                 base_gfn = slots->memslots[0].base_gfn +
2533                                  kvm->memslots->memslots[0].npages - 3;
2534                 return base_gfn << PAGE_SHIFT;
2535         }
2536         return kvm->arch.tss_addr;
2537 }
2538
2539 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2540 {
2541         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2542
2543         save->selector = vmcs_read16(sf->selector);
2544         save->base = vmcs_readl(sf->base);
2545         save->limit = vmcs_read32(sf->limit);
2546         save->ar = vmcs_read32(sf->ar_bytes);
2547         vmcs_write16(sf->selector, save->base >> 4);
2548         vmcs_write32(sf->base, save->base & 0xffff0);
2549         vmcs_write32(sf->limit, 0xffff);
2550         vmcs_write32(sf->ar_bytes, 0xf3);
2551         if (save->base & 0xf)
2552                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2553                             " aligned when entering protected mode (seg=%d)",
2554                             seg);
2555 }
2556
2557 static void enter_rmode(struct kvm_vcpu *vcpu)
2558 {
2559         unsigned long flags;
2560         struct vcpu_vmx *vmx = to_vmx(vcpu);
2561
2562         if (enable_unrestricted_guest)
2563                 return;
2564
2565         vmx->emulation_required = 1;
2566         vmx->rmode.vm86_active = 1;
2567
2568         /*
2569          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2570          * vcpu. Call it here with phys address pointing 16M below 4G.
2571          */
2572         if (!vcpu->kvm->arch.tss_addr) {
2573                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2574                              "called before entering vcpu\n");
2575                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2576                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2577                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2578         }
2579
2580         vmx_segment_cache_clear(vmx);
2581
2582         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2583         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2584         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2585
2586         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2587         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2588
2589         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2590         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2591
2592         flags = vmcs_readl(GUEST_RFLAGS);
2593         vmx->rmode.save_rflags = flags;
2594
2595         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2596
2597         vmcs_writel(GUEST_RFLAGS, flags);
2598         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2599         update_exception_bitmap(vcpu);
2600
2601         if (emulate_invalid_guest_state)
2602                 goto continue_rmode;
2603
2604         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2605         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2606         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2607
2608         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2609         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2610         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2611                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2612         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2613
2614         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2615         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2616         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2617         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2618
2619 continue_rmode:
2620         kvm_mmu_reset_context(vcpu);
2621 }
2622
2623 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2624 {
2625         struct vcpu_vmx *vmx = to_vmx(vcpu);
2626         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2627
2628         if (!msr)
2629                 return;
2630
2631         /*
2632          * Force kernel_gs_base reloading before EFER changes, as control
2633          * of this msr depends on is_long_mode().
2634          */
2635         vmx_load_host_state(to_vmx(vcpu));
2636         vcpu->arch.efer = efer;
2637         if (efer & EFER_LMA) {
2638                 vmcs_write32(VM_ENTRY_CONTROLS,
2639                              vmcs_read32(VM_ENTRY_CONTROLS) |
2640                              VM_ENTRY_IA32E_MODE);
2641                 msr->data = efer;
2642         } else {
2643                 vmcs_write32(VM_ENTRY_CONTROLS,
2644                              vmcs_read32(VM_ENTRY_CONTROLS) &
2645                              ~VM_ENTRY_IA32E_MODE);
2646
2647                 msr->data = efer & ~EFER_LME;
2648         }
2649         setup_msrs(vmx);
2650 }
2651
2652 #ifdef CONFIG_X86_64
2653
2654 static void enter_lmode(struct kvm_vcpu *vcpu)
2655 {
2656         u32 guest_tr_ar;
2657
2658         vmx_segment_cache_clear(to_vmx(vcpu));
2659
2660         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2661         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2662                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2663                        __func__);
2664                 vmcs_write32(GUEST_TR_AR_BYTES,
2665                              (guest_tr_ar & ~AR_TYPE_MASK)
2666                              | AR_TYPE_BUSY_64_TSS);
2667         }
2668         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2669 }
2670
2671 static void exit_lmode(struct kvm_vcpu *vcpu)
2672 {
2673         vmcs_write32(VM_ENTRY_CONTROLS,
2674                      vmcs_read32(VM_ENTRY_CONTROLS)
2675                      & ~VM_ENTRY_IA32E_MODE);
2676         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2677 }
2678
2679 #endif
2680
2681 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2682 {
2683         vpid_sync_context(to_vmx(vcpu));
2684         if (enable_ept) {
2685                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2686                         return;
2687                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2688         }
2689 }
2690
2691 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2692 {
2693         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2694
2695         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2696         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2697 }
2698
2699 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2700 {
2701         if (enable_ept && is_paging(vcpu))
2702                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2703         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2704 }
2705
2706 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2707 {
2708         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2709
2710         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2711         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2712 }
2713
2714 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2715 {
2716         if (!test_bit(VCPU_EXREG_PDPTR,
2717                       (unsigned long *)&vcpu->arch.regs_dirty))
2718                 return;
2719
2720         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2721                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2722                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2723                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2724                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2725         }
2726 }
2727
2728 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2729 {
2730         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2731                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2732                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2733                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2734                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2735         }
2736
2737         __set_bit(VCPU_EXREG_PDPTR,
2738                   (unsigned long *)&vcpu->arch.regs_avail);
2739         __set_bit(VCPU_EXREG_PDPTR,
2740                   (unsigned long *)&vcpu->arch.regs_dirty);
2741 }
2742
2743 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2744
2745 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2746                                         unsigned long cr0,
2747                                         struct kvm_vcpu *vcpu)
2748 {
2749         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2750                 vmx_decache_cr3(vcpu);
2751         if (!(cr0 & X86_CR0_PG)) {
2752                 /* From paging/starting to nonpaging */
2753                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2754                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2755                              (CPU_BASED_CR3_LOAD_EXITING |
2756                               CPU_BASED_CR3_STORE_EXITING));
2757                 vcpu->arch.cr0 = cr0;
2758                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2759         } else if (!is_paging(vcpu)) {
2760                 /* From nonpaging to paging */
2761                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2762                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2763                              ~(CPU_BASED_CR3_LOAD_EXITING |
2764                                CPU_BASED_CR3_STORE_EXITING));
2765                 vcpu->arch.cr0 = cr0;
2766                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2767         }
2768
2769         if (!(cr0 & X86_CR0_WP))
2770                 *hw_cr0 &= ~X86_CR0_WP;
2771 }
2772
2773 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2774 {
2775         struct vcpu_vmx *vmx = to_vmx(vcpu);
2776         unsigned long hw_cr0;
2777
2778         if (enable_unrestricted_guest)
2779                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2780                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2781         else
2782                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2783
2784         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2785                 enter_pmode(vcpu);
2786
2787         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2788                 enter_rmode(vcpu);
2789
2790 #ifdef CONFIG_X86_64
2791         if (vcpu->arch.efer & EFER_LME) {
2792                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2793                         enter_lmode(vcpu);
2794                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2795                         exit_lmode(vcpu);
2796         }
2797 #endif
2798
2799         if (enable_ept)
2800                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2801
2802         if (!vcpu->fpu_active)
2803                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2804
2805         vmcs_writel(CR0_READ_SHADOW, cr0);
2806         vmcs_writel(GUEST_CR0, hw_cr0);
2807         vcpu->arch.cr0 = cr0;
2808         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2809 }
2810
2811 static u64 construct_eptp(unsigned long root_hpa)
2812 {
2813         u64 eptp;
2814
2815         /* TODO write the value reading from MSR */
2816         eptp = VMX_EPT_DEFAULT_MT |
2817                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2818         eptp |= (root_hpa & PAGE_MASK);
2819
2820         return eptp;
2821 }
2822
2823 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2824 {
2825         unsigned long guest_cr3;
2826         u64 eptp;
2827
2828         guest_cr3 = cr3;
2829         if (enable_ept) {
2830                 eptp = construct_eptp(cr3);
2831                 vmcs_write64(EPT_POINTER, eptp);
2832                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2833                         vcpu->kvm->arch.ept_identity_map_addr;
2834                 ept_load_pdptrs(vcpu);
2835         }
2836
2837         vmx_flush_tlb(vcpu);
2838         vmcs_writel(GUEST_CR3, guest_cr3);
2839 }
2840
2841 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2842 {
2843         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2844                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2845
2846         if (cr4 & X86_CR4_VMXE) {
2847                 /*
2848                  * To use VMXON (and later other VMX instructions), a guest
2849                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2850                  * So basically the check on whether to allow nested VMX
2851                  * is here.
2852                  */
2853                 if (!nested_vmx_allowed(vcpu))
2854                         return 1;
2855         } else if (to_vmx(vcpu)->nested.vmxon)
2856                 return 1;
2857
2858         vcpu->arch.cr4 = cr4;
2859         if (enable_ept) {
2860                 if (!is_paging(vcpu)) {
2861                         hw_cr4 &= ~X86_CR4_PAE;
2862                         hw_cr4 |= X86_CR4_PSE;
2863                 } else if (!(cr4 & X86_CR4_PAE)) {
2864                         hw_cr4 &= ~X86_CR4_PAE;
2865                 }
2866         }
2867
2868         vmcs_writel(CR4_READ_SHADOW, cr4);
2869         vmcs_writel(GUEST_CR4, hw_cr4);
2870         return 0;
2871 }
2872
2873 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2874                             struct kvm_segment *var, int seg)
2875 {
2876         struct vcpu_vmx *vmx = to_vmx(vcpu);
2877         struct kvm_save_segment *save;
2878         u32 ar;
2879
2880         if (vmx->rmode.vm86_active
2881             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2882                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2883                 || seg == VCPU_SREG_GS)
2884             && !emulate_invalid_guest_state) {
2885                 switch (seg) {
2886                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2887                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2888                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2889                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2890                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2891                 default: BUG();
2892                 }
2893                 var->selector = save->selector;
2894                 var->base = save->base;
2895                 var->limit = save->limit;
2896                 ar = save->ar;
2897                 if (seg == VCPU_SREG_TR
2898                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2899                         goto use_saved_rmode_seg;
2900         }
2901         var->base = vmx_read_guest_seg_base(vmx, seg);
2902         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2903         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2904         ar = vmx_read_guest_seg_ar(vmx, seg);
2905 use_saved_rmode_seg:
2906         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2907                 ar = 0;
2908         var->type = ar & 15;
2909         var->s = (ar >> 4) & 1;
2910         var->dpl = (ar >> 5) & 3;
2911         var->present = (ar >> 7) & 1;
2912         var->avl = (ar >> 12) & 1;
2913         var->l = (ar >> 13) & 1;
2914         var->db = (ar >> 14) & 1;
2915         var->g = (ar >> 15) & 1;
2916         var->unusable = (ar >> 16) & 1;
2917 }
2918
2919 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2920 {
2921         struct kvm_segment s;
2922
2923         if (to_vmx(vcpu)->rmode.vm86_active) {
2924                 vmx_get_segment(vcpu, &s, seg);
2925                 return s.base;
2926         }
2927         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2928 }
2929
2930 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2931 {
2932         if (!is_protmode(vcpu))
2933                 return 0;
2934
2935         if (!is_long_mode(vcpu)
2936             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2937                 return 3;
2938
2939         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2940 }
2941
2942 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2943 {
2944         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2945                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2946                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2947         }
2948         return to_vmx(vcpu)->cpl;
2949 }
2950
2951
2952 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2953 {
2954         u32 ar;
2955
2956         if (var->unusable)
2957                 ar = 1 << 16;
2958         else {
2959                 ar = var->type & 15;
2960                 ar |= (var->s & 1) << 4;
2961                 ar |= (var->dpl & 3) << 5;
2962                 ar |= (var->present & 1) << 7;
2963                 ar |= (var->avl & 1) << 12;
2964                 ar |= (var->l & 1) << 13;
2965                 ar |= (var->db & 1) << 14;
2966                 ar |= (var->g & 1) << 15;
2967         }
2968         if (ar == 0) /* a 0 value means unusable */
2969                 ar = AR_UNUSABLE_MASK;
2970
2971         return ar;
2972 }
2973
2974 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2975                             struct kvm_segment *var, int seg)
2976 {
2977         struct vcpu_vmx *vmx = to_vmx(vcpu);
2978         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2979         u32 ar;
2980
2981         vmx_segment_cache_clear(vmx);
2982
2983         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2984                 vmcs_write16(sf->selector, var->selector);
2985                 vmx->rmode.tr.selector = var->selector;
2986                 vmx->rmode.tr.base = var->base;
2987                 vmx->rmode.tr.limit = var->limit;
2988                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2989                 return;
2990         }
2991         vmcs_writel(sf->base, var->base);
2992         vmcs_write32(sf->limit, var->limit);
2993         vmcs_write16(sf->selector, var->selector);
2994         if (vmx->rmode.vm86_active && var->s) {
2995                 /*
2996                  * Hack real-mode segments into vm86 compatibility.
2997                  */
2998                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2999                         vmcs_writel(sf->base, 0xf0000);
3000                 ar = 0xf3;
3001         } else
3002                 ar = vmx_segment_access_rights(var);
3003
3004         /*
3005          *   Fix the "Accessed" bit in AR field of segment registers for older
3006          * qemu binaries.
3007          *   IA32 arch specifies that at the time of processor reset the
3008          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3009          * is setting it to 0 in the usedland code. This causes invalid guest
3010          * state vmexit when "unrestricted guest" mode is turned on.
3011          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3012          * tree. Newer qemu binaries with that qemu fix would not need this
3013          * kvm hack.
3014          */
3015         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3016                 ar |= 0x1; /* Accessed */
3017
3018         vmcs_write32(sf->ar_bytes, ar);
3019         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3020 }
3021
3022 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3023 {
3024         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3025
3026         *db = (ar >> 14) & 1;
3027         *l = (ar >> 13) & 1;
3028 }
3029
3030 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3031 {
3032         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3033         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3034 }
3035
3036 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3037 {
3038         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3039         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3040 }
3041
3042 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3043 {
3044         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3045         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3046 }
3047
3048 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3049 {
3050         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3051         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3052 }
3053
3054 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3055 {
3056         struct kvm_segment var;
3057         u32 ar;
3058
3059         vmx_get_segment(vcpu, &var, seg);
3060         ar = vmx_segment_access_rights(&var);
3061
3062         if (var.base != (var.selector << 4))
3063                 return false;
3064         if (var.limit != 0xffff)
3065                 return false;
3066         if (ar != 0xf3)
3067                 return false;
3068
3069         return true;
3070 }
3071
3072 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3073 {
3074         struct kvm_segment cs;
3075         unsigned int cs_rpl;
3076
3077         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3078         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3079
3080         if (cs.unusable)
3081                 return false;
3082         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3083                 return false;
3084         if (!cs.s)
3085                 return false;
3086         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3087                 if (cs.dpl > cs_rpl)
3088                         return false;
3089         } else {
3090                 if (cs.dpl != cs_rpl)
3091                         return false;
3092         }
3093         if (!cs.present)
3094                 return false;
3095
3096         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3097         return true;
3098 }
3099
3100 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3101 {
3102         struct kvm_segment ss;
3103         unsigned int ss_rpl;
3104
3105         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3106         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3107
3108         if (ss.unusable)
3109                 return true;
3110         if (ss.type != 3 && ss.type != 7)
3111                 return false;
3112         if (!ss.s)
3113                 return false;
3114         if (ss.dpl != ss_rpl) /* DPL != RPL */
3115                 return false;
3116         if (!ss.present)
3117                 return false;
3118
3119         return true;
3120 }
3121
3122 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3123 {
3124         struct kvm_segment var;
3125         unsigned int rpl;
3126
3127         vmx_get_segment(vcpu, &var, seg);
3128         rpl = var.selector & SELECTOR_RPL_MASK;
3129
3130         if (var.unusable)
3131                 return true;
3132         if (!var.s)
3133                 return false;
3134         if (!var.present)
3135                 return false;
3136         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3137                 if (var.dpl < rpl) /* DPL < RPL */
3138                         return false;
3139         }
3140
3141         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3142          * rights flags
3143          */
3144         return true;
3145 }
3146
3147 static bool tr_valid(struct kvm_vcpu *vcpu)
3148 {
3149         struct kvm_segment tr;
3150
3151         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3152
3153         if (tr.unusable)
3154                 return false;
3155         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3156                 return false;
3157         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3158                 return false;
3159         if (!tr.present)
3160                 return false;
3161
3162         return true;
3163 }
3164
3165 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3166 {
3167         struct kvm_segment ldtr;
3168
3169         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3170
3171         if (ldtr.unusable)
3172                 return true;
3173         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3174                 return false;
3175         if (ldtr.type != 2)
3176                 return false;
3177         if (!ldtr.present)
3178                 return false;
3179
3180         return true;
3181 }
3182
3183 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3184 {
3185         struct kvm_segment cs, ss;
3186
3187         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3188         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3189
3190         return ((cs.selector & SELECTOR_RPL_MASK) ==
3191                  (ss.selector & SELECTOR_RPL_MASK));
3192 }
3193
3194 /*
3195  * Check if guest state is valid. Returns true if valid, false if
3196  * not.
3197  * We assume that registers are always usable
3198  */
3199 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3200 {
3201         /* real mode guest state checks */
3202         if (!is_protmode(vcpu)) {
3203                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3204                         return false;
3205                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3206                         return false;
3207                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3208                         return false;
3209                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3210                         return false;
3211                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3212                         return false;
3213                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3214                         return false;
3215         } else {
3216         /* protected mode guest state checks */
3217                 if (!cs_ss_rpl_check(vcpu))
3218                         return false;
3219                 if (!code_segment_valid(vcpu))
3220                         return false;
3221                 if (!stack_segment_valid(vcpu))
3222                         return false;
3223                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3224                         return false;
3225                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3226                         return false;
3227                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3228                         return false;
3229                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3230                         return false;
3231                 if (!tr_valid(vcpu))
3232                         return false;
3233                 if (!ldtr_valid(vcpu))
3234                         return false;
3235         }
3236         /* TODO:
3237          * - Add checks on RIP
3238          * - Add checks on RFLAGS
3239          */
3240
3241         return true;
3242 }
3243
3244 static int init_rmode_tss(struct kvm *kvm)
3245 {
3246         gfn_t fn;
3247         u16 data = 0;
3248         int r, idx, ret = 0;
3249
3250         idx = srcu_read_lock(&kvm->srcu);
3251         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3252         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3253         if (r < 0)
3254                 goto out;
3255         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3256         r = kvm_write_guest_page(kvm, fn++, &data,
3257                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3258         if (r < 0)
3259                 goto out;
3260         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3261         if (r < 0)
3262                 goto out;
3263         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3264         if (r < 0)
3265                 goto out;
3266         data = ~0;
3267         r = kvm_write_guest_page(kvm, fn, &data,
3268                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3269                                  sizeof(u8));
3270         if (r < 0)
3271                 goto out;
3272
3273         ret = 1;
3274 out:
3275         srcu_read_unlock(&kvm->srcu, idx);
3276         return ret;
3277 }
3278
3279 static int init_rmode_identity_map(struct kvm *kvm)
3280 {
3281         int i, idx, r, ret;
3282         pfn_t identity_map_pfn;
3283         u32 tmp;
3284
3285         if (!enable_ept)
3286                 return 1;
3287         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3288                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3289                         "haven't been allocated!\n");
3290                 return 0;
3291         }
3292         if (likely(kvm->arch.ept_identity_pagetable_done))
3293                 return 1;
3294         ret = 0;
3295         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3296         idx = srcu_read_lock(&kvm->srcu);
3297         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3298         if (r < 0)
3299                 goto out;
3300         /* Set up identity-mapping pagetable for EPT in real mode */
3301         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3302                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3303                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3304                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3305                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3306                 if (r < 0)
3307                         goto out;
3308         }
3309         kvm->arch.ept_identity_pagetable_done = true;
3310         ret = 1;
3311 out:
3312         srcu_read_unlock(&kvm->srcu, idx);
3313         return ret;
3314 }
3315
3316 static void seg_setup(int seg)
3317 {
3318         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3319         unsigned int ar;
3320
3321         vmcs_write16(sf->selector, 0);
3322         vmcs_writel(sf->base, 0);
3323         vmcs_write32(sf->limit, 0xffff);
3324         if (enable_unrestricted_guest) {
3325                 ar = 0x93;
3326                 if (seg == VCPU_SREG_CS)
3327                         ar |= 0x08; /* code segment */
3328         } else
3329                 ar = 0xf3;
3330
3331         vmcs_write32(sf->ar_bytes, ar);
3332 }
3333
3334 static int alloc_apic_access_page(struct kvm *kvm)
3335 {
3336         struct kvm_userspace_memory_region kvm_userspace_mem;
3337         int r = 0;
3338
3339         mutex_lock(&kvm->slots_lock);
3340         if (kvm->arch.apic_access_page)
3341                 goto out;
3342         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3343         kvm_userspace_mem.flags = 0;
3344         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3345         kvm_userspace_mem.memory_size = PAGE_SIZE;
3346         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3347         if (r)
3348                 goto out;
3349
3350         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3351 out:
3352         mutex_unlock(&kvm->slots_lock);
3353         return r;
3354 }
3355
3356 static int alloc_identity_pagetable(struct kvm *kvm)
3357 {
3358         struct kvm_userspace_memory_region kvm_userspace_mem;
3359         int r = 0;
3360
3361         mutex_lock(&kvm->slots_lock);
3362         if (kvm->arch.ept_identity_pagetable)
3363                 goto out;
3364         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3365         kvm_userspace_mem.flags = 0;
3366         kvm_userspace_mem.guest_phys_addr =
3367                 kvm->arch.ept_identity_map_addr;
3368         kvm_userspace_mem.memory_size = PAGE_SIZE;
3369         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3370         if (r)
3371                 goto out;
3372
3373         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3374                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3375 out:
3376         mutex_unlock(&kvm->slots_lock);
3377         return r;
3378 }
3379
3380 static void allocate_vpid(struct vcpu_vmx *vmx)
3381 {
3382         int vpid;
3383
3384         vmx->vpid = 0;
3385         if (!enable_vpid)
3386                 return;
3387         spin_lock(&vmx_vpid_lock);
3388         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3389         if (vpid < VMX_NR_VPIDS) {
3390                 vmx->vpid = vpid;
3391                 __set_bit(vpid, vmx_vpid_bitmap);
3392         }
3393         spin_unlock(&vmx_vpid_lock);
3394 }
3395
3396 static void free_vpid(struct vcpu_vmx *vmx)
3397 {
3398         if (!enable_vpid)
3399                 return;
3400         spin_lock(&vmx_vpid_lock);
3401         if (vmx->vpid != 0)
3402                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3403         spin_unlock(&vmx_vpid_lock);
3404 }
3405
3406 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3407 {
3408         int f = sizeof(unsigned long);
3409
3410         if (!cpu_has_vmx_msr_bitmap())
3411                 return;
3412
3413         /*
3414          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3415          * have the write-low and read-high bitmap offsets the wrong way round.
3416          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3417          */
3418         if (msr <= 0x1fff) {
3419                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3420                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3421         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3422                 msr &= 0x1fff;
3423                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3424                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3425         }
3426 }
3427
3428 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3429 {
3430         if (!longmode_only)
3431                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3432         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3433 }
3434
3435 /*
3436  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3437  * will not change in the lifetime of the guest.
3438  * Note that host-state that does change is set elsewhere. E.g., host-state
3439  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3440  */
3441 static void vmx_set_constant_host_state(void)
3442 {
3443         u32 low32, high32;
3444         unsigned long tmpl;
3445         struct desc_ptr dt;
3446
3447         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3448         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3449         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3450
3451         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3452         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3453         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3454         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3455         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3456
3457         native_store_idt(&dt);
3458         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3459
3460         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3461         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3462
3463         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3464         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3465         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3466         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3467
3468         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3469                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3470                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3471         }
3472 }
3473
3474 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3475 {
3476         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3477         if (enable_ept)
3478                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3479         if (is_guest_mode(&vmx->vcpu))
3480                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3481                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3482         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3483 }
3484
3485 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3486 {
3487         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3488         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3489                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3490 #ifdef CONFIG_X86_64
3491                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3492                                 CPU_BASED_CR8_LOAD_EXITING;
3493 #endif
3494         }
3495         if (!enable_ept)
3496                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3497                                 CPU_BASED_CR3_LOAD_EXITING  |
3498                                 CPU_BASED_INVLPG_EXITING;
3499         return exec_control;
3500 }
3501
3502 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3503 {
3504         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3505         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3506                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3507         if (vmx->vpid == 0)
3508                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3509         if (!enable_ept) {
3510                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3511                 enable_unrestricted_guest = 0;
3512         }
3513         if (!enable_unrestricted_guest)
3514                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3515         if (!ple_gap)
3516                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3517         return exec_control;
3518 }
3519
3520 /*
3521  * Sets up the vmcs for emulated real mode.
3522  */
3523 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3524 {
3525         unsigned long a;
3526         int i;
3527
3528         /* I/O */
3529         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3530         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3531
3532         if (cpu_has_vmx_msr_bitmap())
3533                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3534
3535         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3536
3537         /* Control */
3538         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3539                 vmcs_config.pin_based_exec_ctrl);
3540
3541         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3542
3543         if (cpu_has_secondary_exec_ctrls()) {
3544                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3545                                 vmx_secondary_exec_control(vmx));
3546         }
3547
3548         if (ple_gap) {
3549                 vmcs_write32(PLE_GAP, ple_gap);
3550                 vmcs_write32(PLE_WINDOW, ple_window);
3551         }
3552
3553         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3554         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
3555         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3556
3557         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3558         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3559         vmx_set_constant_host_state();
3560 #ifdef CONFIG_X86_64
3561         rdmsrl(MSR_FS_BASE, a);
3562         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3563         rdmsrl(MSR_GS_BASE, a);
3564         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3565 #else
3566         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3567         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3568 #endif
3569
3570         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3571         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3572         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3573         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3574         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3575
3576         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3577                 u32 msr_low, msr_high;
3578                 u64 host_pat;
3579                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3580                 host_pat = msr_low | ((u64) msr_high << 32);
3581                 /* Write the default value follow host pat */
3582                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3583                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3584                 vmx->vcpu.arch.pat = host_pat;
3585         }
3586
3587         for (i = 0; i < NR_VMX_MSR; ++i) {
3588                 u32 index = vmx_msr_index[i];
3589                 u32 data_low, data_high;
3590                 int j = vmx->nmsrs;
3591
3592                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3593                         continue;
3594                 if (wrmsr_safe(index, data_low, data_high) < 0)
3595                         continue;
3596                 vmx->guest_msrs[j].index = i;
3597                 vmx->guest_msrs[j].data = 0;
3598                 vmx->guest_msrs[j].mask = -1ull;
3599                 ++vmx->nmsrs;
3600         }
3601
3602         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3603
3604         /* 22.2.1, 20.8.1 */
3605         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3606
3607         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3608         set_cr4_guest_host_mask(vmx);
3609
3610         kvm_write_tsc(&vmx->vcpu, 0);
3611
3612         return 0;
3613 }
3614
3615 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3616 {
3617         struct vcpu_vmx *vmx = to_vmx(vcpu);
3618         u64 msr;
3619         int ret;
3620
3621         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3622
3623         vmx->rmode.vm86_active = 0;
3624
3625         vmx->soft_vnmi_blocked = 0;
3626
3627         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3628         kvm_set_cr8(&vmx->vcpu, 0);
3629         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3630         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3631                 msr |= MSR_IA32_APICBASE_BSP;
3632         kvm_set_apic_base(&vmx->vcpu, msr);
3633
3634         ret = fx_init(&vmx->vcpu);
3635         if (ret != 0)
3636                 goto out;
3637
3638         vmx_segment_cache_clear(vmx);
3639
3640         seg_setup(VCPU_SREG_CS);
3641         /*
3642          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3643          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3644          */
3645         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3646                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3647                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3648         } else {
3649                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3650                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3651         }
3652
3653         seg_setup(VCPU_SREG_DS);
3654         seg_setup(VCPU_SREG_ES);
3655         seg_setup(VCPU_SREG_FS);
3656         seg_setup(VCPU_SREG_GS);
3657         seg_setup(VCPU_SREG_SS);
3658
3659         vmcs_write16(GUEST_TR_SELECTOR, 0);
3660         vmcs_writel(GUEST_TR_BASE, 0);
3661         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3662         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3663
3664         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3665         vmcs_writel(GUEST_LDTR_BASE, 0);
3666         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3667         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3668
3669         vmcs_write32(GUEST_SYSENTER_CS, 0);
3670         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3671         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3672
3673         vmcs_writel(GUEST_RFLAGS, 0x02);
3674         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3675                 kvm_rip_write(vcpu, 0xfff0);
3676         else
3677                 kvm_rip_write(vcpu, 0);
3678         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3679
3680         vmcs_writel(GUEST_DR7, 0x400);
3681
3682         vmcs_writel(GUEST_GDTR_BASE, 0);
3683         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3684
3685         vmcs_writel(GUEST_IDTR_BASE, 0);
3686         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3687
3688         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3689         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3690         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3691
3692         /* Special registers */
3693         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3694
3695         setup_msrs(vmx);
3696
3697         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3698
3699         if (cpu_has_vmx_tpr_shadow()) {
3700                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3701                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3702                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3703                                      __pa(vmx->vcpu.arch.apic->regs));
3704                 vmcs_write32(TPR_THRESHOLD, 0);
3705         }
3706
3707         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3708                 vmcs_write64(APIC_ACCESS_ADDR,
3709                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3710
3711         if (vmx->vpid != 0)
3712                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3713
3714         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3715         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3716         vmx_set_cr4(&vmx->vcpu, 0);
3717         vmx_set_efer(&vmx->vcpu, 0);
3718         vmx_fpu_activate(&vmx->vcpu);
3719         update_exception_bitmap(&vmx->vcpu);
3720
3721         vpid_sync_context(vmx);
3722
3723         ret = 0;
3724
3725         /* HACK: Don't enable emulation on guest boot/reset */
3726         vmx->emulation_required = 0;
3727
3728 out:
3729         return ret;
3730 }
3731
3732 static void enable_irq_window(struct kvm_vcpu *vcpu)
3733 {
3734         u32 cpu_based_vm_exec_control;
3735
3736         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3737         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3738         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3739 }
3740
3741 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3742 {
3743         u32 cpu_based_vm_exec_control;
3744
3745         if (!cpu_has_virtual_nmis()) {
3746                 enable_irq_window(vcpu);
3747                 return;
3748         }
3749
3750         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3751                 enable_irq_window(vcpu);
3752                 return;
3753         }
3754         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3755         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3756         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3757 }
3758
3759 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3760 {
3761         struct vcpu_vmx *vmx = to_vmx(vcpu);
3762         uint32_t intr;
3763         int irq = vcpu->arch.interrupt.nr;
3764
3765         trace_kvm_inj_virq(irq);
3766
3767         ++vcpu->stat.irq_injections;
3768         if (vmx->rmode.vm86_active) {
3769                 int inc_eip = 0;
3770                 if (vcpu->arch.interrupt.soft)
3771                         inc_eip = vcpu->arch.event_exit_inst_len;
3772                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3773                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3774                 return;
3775         }
3776         intr = irq | INTR_INFO_VALID_MASK;
3777         if (vcpu->arch.interrupt.soft) {
3778                 intr |= INTR_TYPE_SOFT_INTR;
3779                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3780                              vmx->vcpu.arch.event_exit_inst_len);
3781         } else
3782                 intr |= INTR_TYPE_EXT_INTR;
3783         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3784         vmx_clear_hlt(vcpu);
3785 }
3786
3787 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3788 {
3789         struct vcpu_vmx *vmx = to_vmx(vcpu);
3790
3791         if (!cpu_has_virtual_nmis()) {
3792                 /*
3793                  * Tracking the NMI-blocked state in software is built upon
3794                  * finding the next open IRQ window. This, in turn, depends on
3795                  * well-behaving guests: They have to keep IRQs disabled at
3796                  * least as long as the NMI handler runs. Otherwise we may
3797                  * cause NMI nesting, maybe breaking the guest. But as this is
3798                  * highly unlikely, we can live with the residual risk.
3799                  */
3800                 vmx->soft_vnmi_blocked = 1;
3801                 vmx->vnmi_blocked_time = 0;
3802         }
3803
3804         ++vcpu->stat.nmi_injections;
3805         vmx->nmi_known_unmasked = false;
3806         if (vmx->rmode.vm86_active) {
3807                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3808                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3809                 return;
3810         }
3811         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3812                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3813         vmx_clear_hlt(vcpu);
3814 }
3815
3816 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3817 {
3818         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3819                 return 0;
3820
3821         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3822                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3823                    | GUEST_INTR_STATE_NMI));
3824 }
3825
3826 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3827 {
3828         if (!cpu_has_virtual_nmis())
3829                 return to_vmx(vcpu)->soft_vnmi_blocked;
3830         if (to_vmx(vcpu)->nmi_known_unmasked)
3831                 return false;
3832         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3833 }
3834
3835 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3836 {
3837         struct vcpu_vmx *vmx = to_vmx(vcpu);
3838
3839         if (!cpu_has_virtual_nmis()) {
3840                 if (vmx->soft_vnmi_blocked != masked) {
3841                         vmx->soft_vnmi_blocked = masked;
3842                         vmx->vnmi_blocked_time = 0;
3843                 }
3844         } else {
3845                 vmx->nmi_known_unmasked = !masked;
3846                 if (masked)
3847                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3848                                       GUEST_INTR_STATE_NMI);
3849                 else
3850                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3851                                         GUEST_INTR_STATE_NMI);
3852         }
3853 }
3854
3855 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3856 {
3857         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3858                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3859                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3860 }
3861
3862 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3863 {
3864         int ret;
3865         struct kvm_userspace_memory_region tss_mem = {
3866                 .slot = TSS_PRIVATE_MEMSLOT,
3867                 .guest_phys_addr = addr,
3868                 .memory_size = PAGE_SIZE * 3,
3869                 .flags = 0,
3870         };
3871
3872         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3873         if (ret)
3874                 return ret;
3875         kvm->arch.tss_addr = addr;
3876         if (!init_rmode_tss(kvm))
3877                 return  -ENOMEM;
3878
3879         return 0;
3880 }
3881
3882 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3883                                   int vec, u32 err_code)
3884 {
3885         /*
3886          * Instruction with address size override prefix opcode 0x67
3887          * Cause the #SS fault with 0 error code in VM86 mode.
3888          */
3889         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3890                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3891                         return 1;
3892         /*
3893          * Forward all other exceptions that are valid in real mode.
3894          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3895          *        the required debugging infrastructure rework.
3896          */
3897         switch (vec) {
3898         case DB_VECTOR:
3899                 if (vcpu->guest_debug &
3900                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3901                         return 0;
3902                 kvm_queue_exception(vcpu, vec);
3903                 return 1;
3904         case BP_VECTOR:
3905                 /*
3906                  * Update instruction length as we may reinject the exception
3907                  * from user space while in guest debugging mode.
3908                  */
3909                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3910                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3911                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3912                         return 0;
3913                 /* fall through */
3914         case DE_VECTOR:
3915         case OF_VECTOR:
3916         case BR_VECTOR:
3917         case UD_VECTOR:
3918         case DF_VECTOR:
3919         case SS_VECTOR:
3920         case GP_VECTOR:
3921         case MF_VECTOR:
3922                 kvm_queue_exception(vcpu, vec);
3923                 return 1;
3924         }
3925         return 0;
3926 }
3927
3928 /*
3929  * Trigger machine check on the host. We assume all the MSRs are already set up
3930  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3931  * We pass a fake environment to the machine check handler because we want
3932  * the guest to be always treated like user space, no matter what context
3933  * it used internally.
3934  */
3935 static void kvm_machine_check(void)
3936 {
3937 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3938         struct pt_regs regs = {
3939                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3940                 .flags = X86_EFLAGS_IF,
3941         };
3942
3943         do_machine_check(&regs, 0);
3944 #endif
3945 }
3946
3947 static int handle_machine_check(struct kvm_vcpu *vcpu)
3948 {
3949         /* already handled by vcpu_run */
3950         return 1;
3951 }
3952
3953 static int handle_exception(struct kvm_vcpu *vcpu)
3954 {
3955         struct vcpu_vmx *vmx = to_vmx(vcpu);
3956         struct kvm_run *kvm_run = vcpu->run;
3957         u32 intr_info, ex_no, error_code;
3958         unsigned long cr2, rip, dr6;
3959         u32 vect_info;
3960         enum emulation_result er;
3961
3962         vect_info = vmx->idt_vectoring_info;
3963         intr_info = vmx->exit_intr_info;
3964
3965         if (is_machine_check(intr_info))
3966                 return handle_machine_check(vcpu);
3967
3968         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3969             !is_page_fault(intr_info)) {
3970                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3971                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3972                 vcpu->run->internal.ndata = 2;
3973                 vcpu->run->internal.data[0] = vect_info;
3974                 vcpu->run->internal.data[1] = intr_info;
3975                 return 0;
3976         }
3977
3978         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3979                 return 1;  /* already handled by vmx_vcpu_run() */
3980
3981         if (is_no_device(intr_info)) {
3982                 vmx_fpu_activate(vcpu);
3983                 return 1;
3984         }
3985
3986         if (is_invalid_opcode(intr_info)) {
3987                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3988                 if (er != EMULATE_DONE)
3989                         kvm_queue_exception(vcpu, UD_VECTOR);
3990                 return 1;
3991         }
3992
3993         error_code = 0;
3994         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3995                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3996         if (is_page_fault(intr_info)) {
3997                 /* EPT won't cause page fault directly */
3998                 if (enable_ept)
3999                         BUG();
4000                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4001                 trace_kvm_page_fault(cr2, error_code);
4002
4003                 if (kvm_event_needs_reinjection(vcpu))
4004                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4005                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4006         }
4007
4008         if (vmx->rmode.vm86_active &&
4009             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4010                                                                 error_code)) {
4011                 if (vcpu->arch.halt_request) {
4012                         vcpu->arch.halt_request = 0;
4013                         return kvm_emulate_halt(vcpu);
4014                 }
4015                 return 1;
4016         }
4017
4018         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4019         switch (ex_no) {
4020         case DB_VECTOR:
4021                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4022                 if (!(vcpu->guest_debug &
4023                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4024                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4025                         kvm_queue_exception(vcpu, DB_VECTOR);
4026                         return 1;
4027                 }
4028                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4029                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4030                 /* fall through */
4031         case BP_VECTOR:
4032                 /*
4033                  * Update instruction length as we may reinject #BP from
4034                  * user space while in guest debugging mode. Reading it for
4035                  * #DB as well causes no harm, it is not used in that case.
4036                  */
4037                 vmx->vcpu.arch.event_exit_inst_len =
4038                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4039                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4040                 rip = kvm_rip_read(vcpu);
4041                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4042                 kvm_run->debug.arch.exception = ex_no;
4043                 break;
4044         default:
4045                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4046                 kvm_run->ex.exception = ex_no;
4047                 kvm_run->ex.error_code = error_code;
4048                 break;
4049         }
4050         return 0;
4051 }
4052
4053 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4054 {
4055         ++vcpu->stat.irq_exits;
4056         return 1;
4057 }
4058
4059 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4060 {
4061         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4062         return 0;
4063 }
4064
4065 static int handle_io(struct kvm_vcpu *vcpu)
4066 {
4067         unsigned long exit_qualification;
4068         int size, in, string;
4069         unsigned port;
4070
4071         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4072         string = (exit_qualification & 16) != 0;
4073         in = (exit_qualification & 8) != 0;
4074
4075         ++vcpu->stat.io_exits;
4076
4077         if (string || in)
4078                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4079
4080         port = exit_qualification >> 16;
4081         size = (exit_qualification & 7) + 1;
4082         skip_emulated_instruction(vcpu);
4083
4084         return kvm_fast_pio_out(vcpu, size, port);
4085 }
4086
4087 static void
4088 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4089 {
4090         /*
4091          * Patch in the VMCALL instruction:
4092          */
4093         hypercall[0] = 0x0f;
4094         hypercall[1] = 0x01;
4095         hypercall[2] = 0xc1;
4096 }
4097
4098 static int handle_cr(struct kvm_vcpu *vcpu)
4099 {
4100         unsigned long exit_qualification, val;
4101         int cr;
4102         int reg;
4103         int err;
4104
4105         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4106         cr = exit_qualification & 15;
4107         reg = (exit_qualification >> 8) & 15;
4108         switch ((exit_qualification >> 4) & 3) {
4109         case 0: /* mov to cr */
4110                 val = kvm_register_read(vcpu, reg);
4111                 trace_kvm_cr_write(cr, val);
4112                 switch (cr) {
4113                 case 0:
4114                         err = kvm_set_cr0(vcpu, val);
4115                         kvm_complete_insn_gp(vcpu, err);
4116                         return 1;
4117                 case 3:
4118                         err = kvm_set_cr3(vcpu, val);
4119                         kvm_complete_insn_gp(vcpu, err);
4120                         return 1;
4121                 case 4:
4122                         err = kvm_set_cr4(vcpu, val);
4123                         kvm_complete_insn_gp(vcpu, err);
4124                         return 1;
4125                 case 8: {
4126                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4127                                 u8 cr8 = kvm_register_read(vcpu, reg);
4128                                 err = kvm_set_cr8(vcpu, cr8);
4129                                 kvm_complete_insn_gp(vcpu, err);
4130                                 if (irqchip_in_kernel(vcpu->kvm))
4131                                         return 1;
4132                                 if (cr8_prev <= cr8)
4133                                         return 1;
4134                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4135                                 return 0;
4136                         }
4137                 };
4138                 break;
4139         case 2: /* clts */
4140                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4141                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4142                 skip_emulated_instruction(vcpu);
4143                 vmx_fpu_activate(vcpu);
4144                 return 1;
4145         case 1: /*mov from cr*/
4146                 switch (cr) {
4147                 case 3:
4148                         val = kvm_read_cr3(vcpu);
4149                         kvm_register_write(vcpu, reg, val);
4150                         trace_kvm_cr_read(cr, val);
4151                         skip_emulated_instruction(vcpu);
4152                         return 1;
4153                 case 8:
4154                         val = kvm_get_cr8(vcpu);
4155                         kvm_register_write(vcpu, reg, val);
4156                         trace_kvm_cr_read(cr, val);
4157                         skip_emulated_instruction(vcpu);
4158                         return 1;
4159                 }
4160                 break;
4161         case 3: /* lmsw */
4162                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4163                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4164                 kvm_lmsw(vcpu, val);
4165
4166                 skip_emulated_instruction(vcpu);
4167                 return 1;
4168         default:
4169                 break;
4170         }
4171         vcpu->run->exit_reason = 0;
4172         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4173                (int)(exit_qualification >> 4) & 3, cr);
4174         return 0;
4175 }
4176
4177 static int handle_dr(struct kvm_vcpu *vcpu)
4178 {
4179         unsigned long exit_qualification;
4180         int dr, reg;
4181
4182         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4183         if (!kvm_require_cpl(vcpu, 0))
4184                 return 1;
4185         dr = vmcs_readl(GUEST_DR7);
4186         if (dr & DR7_GD) {
4187                 /*
4188                  * As the vm-exit takes precedence over the debug trap, we
4189                  * need to emulate the latter, either for the host or the
4190                  * guest debugging itself.
4191                  */
4192                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4193                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4194                         vcpu->run->debug.arch.dr7 = dr;
4195                         vcpu->run->debug.arch.pc =
4196                                 vmcs_readl(GUEST_CS_BASE) +
4197                                 vmcs_readl(GUEST_RIP);
4198                         vcpu->run->debug.arch.exception = DB_VECTOR;
4199                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4200                         return 0;
4201                 } else {
4202                         vcpu->arch.dr7 &= ~DR7_GD;
4203                         vcpu->arch.dr6 |= DR6_BD;
4204                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4205                         kvm_queue_exception(vcpu, DB_VECTOR);
4206                         return 1;
4207                 }
4208         }
4209
4210         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4211         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4212         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4213         if (exit_qualification & TYPE_MOV_FROM_DR) {
4214                 unsigned long val;
4215                 if (!kvm_get_dr(vcpu, dr, &val))
4216                         kvm_register_write(vcpu, reg, val);
4217         } else
4218                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4219         skip_emulated_instruction(vcpu);
4220         return 1;
4221 }
4222
4223 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4224 {
4225         vmcs_writel(GUEST_DR7, val);
4226 }
4227
4228 static int handle_cpuid(struct kvm_vcpu *vcpu)
4229 {
4230         kvm_emulate_cpuid(vcpu);
4231         return 1;
4232 }
4233
4234 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4235 {
4236         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4237         u64 data;
4238
4239         if (vmx_get_msr(vcpu, ecx, &data)) {
4240                 trace_kvm_msr_read_ex(ecx);
4241                 kvm_inject_gp(vcpu, 0);
4242                 return 1;
4243         }
4244
4245         trace_kvm_msr_read(ecx, data);
4246
4247         /* FIXME: handling of bits 32:63 of rax, rdx */
4248         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4249         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4250         skip_emulated_instruction(vcpu);
4251         return 1;
4252 }
4253
4254 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4255 {
4256         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4257         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4258                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4259
4260         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4261                 trace_kvm_msr_write_ex(ecx, data);
4262                 kvm_inject_gp(vcpu, 0);
4263                 return 1;
4264         }
4265
4266         trace_kvm_msr_write(ecx, data);
4267         skip_emulated_instruction(vcpu);
4268         return 1;
4269 }
4270
4271 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4272 {
4273         kvm_make_request(KVM_REQ_EVENT, vcpu);
4274         return 1;
4275 }
4276
4277 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4278 {
4279         u32 cpu_based_vm_exec_control;
4280
4281         /* clear pending irq */
4282         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4283         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4284         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4285
4286         kvm_make_request(KVM_REQ_EVENT, vcpu);
4287
4288         ++vcpu->stat.irq_window_exits;
4289
4290         /*
4291          * If the user space waits to inject interrupts, exit as soon as
4292          * possible
4293          */
4294         if (!irqchip_in_kernel(vcpu->kvm) &&
4295             vcpu->run->request_interrupt_window &&
4296             !kvm_cpu_has_interrupt(vcpu)) {
4297                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4298                 return 0;
4299         }
4300         return 1;
4301 }
4302
4303 static int handle_halt(struct kvm_vcpu *vcpu)
4304 {
4305         skip_emulated_instruction(vcpu);
4306         return kvm_emulate_halt(vcpu);
4307 }
4308
4309 static int handle_vmcall(struct kvm_vcpu *vcpu)
4310 {
4311         skip_emulated_instruction(vcpu);
4312         kvm_emulate_hypercall(vcpu);
4313         return 1;
4314 }
4315
4316 static int handle_invd(struct kvm_vcpu *vcpu)
4317 {
4318         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4319 }
4320
4321 static int handle_invlpg(struct kvm_vcpu *vcpu)
4322 {
4323         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4324
4325         kvm_mmu_invlpg(vcpu, exit_qualification);
4326         skip_emulated_instruction(vcpu);
4327         return 1;
4328 }
4329
4330 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4331 {
4332         skip_emulated_instruction(vcpu);
4333         kvm_emulate_wbinvd(vcpu);
4334         return 1;
4335 }
4336
4337 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4338 {
4339         u64 new_bv = kvm_read_edx_eax(vcpu);
4340         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4341
4342         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4343                 skip_emulated_instruction(vcpu);
4344         return 1;
4345 }
4346
4347 static int handle_apic_access(struct kvm_vcpu *vcpu)
4348 {
4349         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4350 }
4351
4352 static int handle_task_switch(struct kvm_vcpu *vcpu)
4353 {
4354         struct vcpu_vmx *vmx = to_vmx(vcpu);
4355         unsigned long exit_qualification;
4356         bool has_error_code = false;
4357         u32 error_code = 0;
4358         u16 tss_selector;
4359         int reason, type, idt_v;
4360
4361         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4362         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4363
4364         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4365
4366         reason = (u32)exit_qualification >> 30;
4367         if (reason == TASK_SWITCH_GATE && idt_v) {
4368                 switch (type) {
4369                 case INTR_TYPE_NMI_INTR:
4370                         vcpu->arch.nmi_injected = false;
4371                         vmx_set_nmi_mask(vcpu, true);
4372                         break;
4373                 case INTR_TYPE_EXT_INTR:
4374                 case INTR_TYPE_SOFT_INTR:
4375                         kvm_clear_interrupt_queue(vcpu);
4376                         break;
4377                 case INTR_TYPE_HARD_EXCEPTION:
4378                         if (vmx->idt_vectoring_info &
4379                             VECTORING_INFO_DELIVER_CODE_MASK) {
4380                                 has_error_code = true;
4381                                 error_code =
4382                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4383                         }
4384                         /* fall through */
4385                 case INTR_TYPE_SOFT_EXCEPTION:
4386                         kvm_clear_exception_queue(vcpu);
4387                         break;
4388                 default:
4389                         break;
4390                 }
4391         }
4392         tss_selector = exit_qualification;
4393
4394         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4395                        type != INTR_TYPE_EXT_INTR &&
4396                        type != INTR_TYPE_NMI_INTR))
4397                 skip_emulated_instruction(vcpu);
4398
4399         if (kvm_task_switch(vcpu, tss_selector, reason,
4400                                 has_error_code, error_code) == EMULATE_FAIL) {
4401                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4402                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4403                 vcpu->run->internal.ndata = 0;
4404                 return 0;
4405         }
4406
4407         /* clear all local breakpoint enable flags */
4408         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4409
4410         /*
4411          * TODO: What about debug traps on tss switch?
4412          *       Are we supposed to inject them and update dr6?
4413          */
4414
4415         return 1;
4416 }
4417
4418 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4419 {
4420         unsigned long exit_qualification;
4421         gpa_t gpa;
4422         int gla_validity;
4423
4424         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4425
4426         if (exit_qualification & (1 << 6)) {
4427                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4428                 return -EINVAL;
4429         }
4430
4431         gla_validity = (exit_qualification >> 7) & 0x3;
4432         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4433                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4434                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4435                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4436                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4437                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4438                         (long unsigned int)exit_qualification);
4439                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4440                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4441                 return 0;
4442         }
4443
4444         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4445         trace_kvm_page_fault(gpa, exit_qualification);
4446         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4447 }
4448
4449 static u64 ept_rsvd_mask(u64 spte, int level)
4450 {
4451         int i;
4452         u64 mask = 0;
4453
4454         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4455                 mask |= (1ULL << i);
4456
4457         if (level > 2)
4458                 /* bits 7:3 reserved */
4459                 mask |= 0xf8;
4460         else if (level == 2) {
4461                 if (spte & (1ULL << 7))
4462                         /* 2MB ref, bits 20:12 reserved */
4463                         mask |= 0x1ff000;
4464                 else
4465                         /* bits 6:3 reserved */
4466                         mask |= 0x78;
4467         }
4468
4469         return mask;
4470 }
4471
4472 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4473                                        int level)
4474 {
4475         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4476
4477         /* 010b (write-only) */
4478         WARN_ON((spte & 0x7) == 0x2);
4479
4480         /* 110b (write/execute) */
4481         WARN_ON((spte & 0x7) == 0x6);
4482
4483         /* 100b (execute-only) and value not supported by logical processor */
4484         if (!cpu_has_vmx_ept_execute_only())
4485                 WARN_ON((spte & 0x7) == 0x4);
4486
4487         /* not 000b */
4488         if ((spte & 0x7)) {
4489                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4490
4491                 if (rsvd_bits != 0) {
4492                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4493                                          __func__, rsvd_bits);
4494                         WARN_ON(1);
4495                 }
4496
4497                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4498                         u64 ept_mem_type = (spte & 0x38) >> 3;
4499
4500                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4501                             ept_mem_type == 7) {
4502                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4503                                                 __func__, ept_mem_type);
4504                                 WARN_ON(1);
4505                         }
4506                 }
4507         }
4508 }
4509
4510 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4511 {
4512         u64 sptes[4];
4513         int nr_sptes, i;
4514         gpa_t gpa;
4515
4516         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4517
4518         printk(KERN_ERR "EPT: Misconfiguration.\n");
4519         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4520
4521         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4522
4523         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4524                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4525
4526         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4527         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4528
4529         return 0;
4530 }
4531
4532 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4533 {
4534         u32 cpu_based_vm_exec_control;
4535
4536         /* clear pending NMI */
4537         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4538         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4539         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4540         ++vcpu->stat.nmi_window_exits;
4541         kvm_make_request(KVM_REQ_EVENT, vcpu);
4542
4543         return 1;
4544 }
4545
4546 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4547 {
4548         struct vcpu_vmx *vmx = to_vmx(vcpu);
4549         enum emulation_result err = EMULATE_DONE;
4550         int ret = 1;
4551         u32 cpu_exec_ctrl;
4552         bool intr_window_requested;
4553
4554         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4555         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4556
4557         while (!guest_state_valid(vcpu)) {
4558                 if (intr_window_requested
4559                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4560                         return handle_interrupt_window(&vmx->vcpu);
4561
4562                 err = emulate_instruction(vcpu, 0);
4563
4564                 if (err == EMULATE_DO_MMIO) {
4565                         ret = 0;
4566                         goto out;
4567                 }
4568
4569                 if (err != EMULATE_DONE)
4570                         return 0;
4571
4572                 if (signal_pending(current))
4573                         goto out;
4574                 if (need_resched())
4575                         schedule();
4576         }
4577
4578         vmx->emulation_required = 0;
4579 out:
4580         return ret;
4581 }
4582
4583 /*
4584  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4585  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4586  */
4587 static int handle_pause(struct kvm_vcpu *vcpu)
4588 {
4589         skip_emulated_instruction(vcpu);
4590         kvm_vcpu_on_spin(vcpu);
4591
4592         return 1;
4593 }
4594
4595 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4596 {
4597         kvm_queue_exception(vcpu, UD_VECTOR);
4598         return 1;
4599 }
4600
4601 /*
4602  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4603  * We could reuse a single VMCS for all the L2 guests, but we also want the
4604  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4605  * allows keeping them loaded on the processor, and in the future will allow
4606  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4607  * every entry if they never change.
4608  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4609  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4610  *
4611  * The following functions allocate and free a vmcs02 in this pool.
4612  */
4613
4614 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4615 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4616 {
4617         struct vmcs02_list *item;
4618         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4619                 if (item->vmptr == vmx->nested.current_vmptr) {
4620                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4621                         return &item->vmcs02;
4622                 }
4623
4624         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4625                 /* Recycle the least recently used VMCS. */
4626                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4627                         struct vmcs02_list, list);
4628                 item->vmptr = vmx->nested.current_vmptr;
4629                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4630                 return &item->vmcs02;
4631         }
4632
4633         /* Create a new VMCS */
4634         item = (struct vmcs02_list *)
4635                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4636         if (!item)
4637                 return NULL;
4638         item->vmcs02.vmcs = alloc_vmcs();
4639         if (!item->vmcs02.vmcs) {
4640                 kfree(item);
4641                 return NULL;
4642         }
4643         loaded_vmcs_init(&item->vmcs02);
4644         item->vmptr = vmx->nested.current_vmptr;
4645         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4646         vmx->nested.vmcs02_num++;
4647         return &item->vmcs02;
4648 }
4649
4650 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4651 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4652 {
4653         struct vmcs02_list *item;
4654         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4655                 if (item->vmptr == vmptr) {
4656                         free_loaded_vmcs(&item->vmcs02);
4657                         list_del(&item->list);
4658                         kfree(item);
4659                         vmx->nested.vmcs02_num--;
4660                         return;
4661                 }
4662 }
4663
4664 /*
4665  * Free all VMCSs saved for this vcpu, except the one pointed by
4666  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4667  * currently used, if running L2), and vmcs01 when running L2.
4668  */
4669 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4670 {
4671         struct vmcs02_list *item, *n;
4672         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4673                 if (vmx->loaded_vmcs != &item->vmcs02)
4674                         free_loaded_vmcs(&item->vmcs02);
4675                 list_del(&item->list);
4676                 kfree(item);
4677         }
4678         vmx->nested.vmcs02_num = 0;
4679
4680         if (vmx->loaded_vmcs != &vmx->vmcs01)
4681                 free_loaded_vmcs(&vmx->vmcs01);
4682 }
4683
4684 /*
4685  * Emulate the VMXON instruction.
4686  * Currently, we just remember that VMX is active, and do not save or even
4687  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4688  * do not currently need to store anything in that guest-allocated memory
4689  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4690  * argument is different from the VMXON pointer (which the spec says they do).
4691  */
4692 static int handle_vmon(struct kvm_vcpu *vcpu)
4693 {
4694         struct kvm_segment cs;
4695         struct vcpu_vmx *vmx = to_vmx(vcpu);
4696
4697         /* The Intel VMX Instruction Reference lists a bunch of bits that
4698          * are prerequisite to running VMXON, most notably cr4.VMXE must be
4699          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4700          * Otherwise, we should fail with #UD. We test these now:
4701          */
4702         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4703             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4704             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4705                 kvm_queue_exception(vcpu, UD_VECTOR);
4706                 return 1;
4707         }
4708
4709         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4710         if (is_long_mode(vcpu) && !cs.l) {
4711                 kvm_queue_exception(vcpu, UD_VECTOR);
4712                 return 1;
4713         }
4714
4715         if (vmx_get_cpl(vcpu)) {
4716                 kvm_inject_gp(vcpu, 0);
4717                 return 1;
4718         }
4719
4720         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4721         vmx->nested.vmcs02_num = 0;
4722
4723         vmx->nested.vmxon = true;
4724
4725         skip_emulated_instruction(vcpu);
4726         return 1;
4727 }
4728
4729 /*
4730  * Intel's VMX Instruction Reference specifies a common set of prerequisites
4731  * for running VMX instructions (except VMXON, whose prerequisites are
4732  * slightly different). It also specifies what exception to inject otherwise.
4733  */
4734 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4735 {
4736         struct kvm_segment cs;
4737         struct vcpu_vmx *vmx = to_vmx(vcpu);
4738
4739         if (!vmx->nested.vmxon) {
4740                 kvm_queue_exception(vcpu, UD_VECTOR);
4741                 return 0;
4742         }
4743
4744         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4745         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4746             (is_long_mode(vcpu) && !cs.l)) {
4747                 kvm_queue_exception(vcpu, UD_VECTOR);
4748                 return 0;
4749         }
4750
4751         if (vmx_get_cpl(vcpu)) {
4752                 kvm_inject_gp(vcpu, 0);
4753                 return 0;
4754         }
4755
4756         return 1;
4757 }
4758
4759 /*
4760  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4761  * just stops using VMX.
4762  */
4763 static void free_nested(struct vcpu_vmx *vmx)
4764 {
4765         if (!vmx->nested.vmxon)
4766                 return;
4767         vmx->nested.vmxon = false;
4768         if (vmx->nested.current_vmptr != -1ull) {
4769                 kunmap(vmx->nested.current_vmcs12_page);
4770                 nested_release_page(vmx->nested.current_vmcs12_page);
4771                 vmx->nested.current_vmptr = -1ull;
4772                 vmx->nested.current_vmcs12 = NULL;
4773         }
4774         /* Unpin physical memory we referred to in current vmcs02 */
4775         if (vmx->nested.apic_access_page) {
4776                 nested_release_page(vmx->nested.apic_access_page);
4777                 vmx->nested.apic_access_page = 0;
4778         }
4779
4780         nested_free_all_saved_vmcss(vmx);
4781 }
4782
4783 /* Emulate the VMXOFF instruction */
4784 static int handle_vmoff(struct kvm_vcpu *vcpu)
4785 {
4786         if (!nested_vmx_check_permission(vcpu))
4787                 return 1;
4788         free_nested(to_vmx(vcpu));
4789         skip_emulated_instruction(vcpu);
4790         return 1;
4791 }
4792
4793 /*
4794  * Decode the memory-address operand of a vmx instruction, as recorded on an
4795  * exit caused by such an instruction (run by a guest hypervisor).
4796  * On success, returns 0. When the operand is invalid, returns 1 and throws
4797  * #UD or #GP.
4798  */
4799 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4800                                  unsigned long exit_qualification,
4801                                  u32 vmx_instruction_info, gva_t *ret)
4802 {
4803         /*
4804          * According to Vol. 3B, "Information for VM Exits Due to Instruction
4805          * Execution", on an exit, vmx_instruction_info holds most of the
4806          * addressing components of the operand. Only the displacement part
4807          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4808          * For how an actual address is calculated from all these components,
4809          * refer to Vol. 1, "Operand Addressing".
4810          */
4811         int  scaling = vmx_instruction_info & 3;
4812         int  addr_size = (vmx_instruction_info >> 7) & 7;
4813         bool is_reg = vmx_instruction_info & (1u << 10);
4814         int  seg_reg = (vmx_instruction_info >> 15) & 7;
4815         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
4816         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4817         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
4818         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
4819
4820         if (is_reg) {
4821                 kvm_queue_exception(vcpu, UD_VECTOR);
4822                 return 1;
4823         }
4824
4825         /* Addr = segment_base + offset */
4826         /* offset = base + [index * scale] + displacement */
4827         *ret = vmx_get_segment_base(vcpu, seg_reg);
4828         if (base_is_valid)
4829                 *ret += kvm_register_read(vcpu, base_reg);
4830         if (index_is_valid)
4831                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4832         *ret += exit_qualification; /* holds the displacement */
4833
4834         if (addr_size == 1) /* 32 bit */
4835                 *ret &= 0xffffffff;
4836
4837         /*
4838          * TODO: throw #GP (and return 1) in various cases that the VM*
4839          * instructions require it - e.g., offset beyond segment limit,
4840          * unusable or unreadable/unwritable segment, non-canonical 64-bit
4841          * address, and so on. Currently these are not checked.
4842          */
4843         return 0;
4844 }
4845
4846 /*
4847  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4848  * set the success or error code of an emulated VMX instruction, as specified
4849  * by Vol 2B, VMX Instruction Reference, "Conventions".
4850  */
4851 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
4852 {
4853         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
4854                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4855                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
4856 }
4857
4858 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
4859 {
4860         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4861                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
4862                             X86_EFLAGS_SF | X86_EFLAGS_OF))
4863                         | X86_EFLAGS_CF);
4864 }
4865
4866 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
4867                                         u32 vm_instruction_error)
4868 {
4869         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
4870                 /*
4871                  * failValid writes the error number to the current VMCS, which
4872                  * can't be done there isn't a current VMCS.
4873                  */
4874                 nested_vmx_failInvalid(vcpu);
4875                 return;
4876         }
4877         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4878                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4879                             X86_EFLAGS_SF | X86_EFLAGS_OF))
4880                         | X86_EFLAGS_ZF);
4881         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
4882 }
4883
4884 /* Emulate the VMCLEAR instruction */
4885 static int handle_vmclear(struct kvm_vcpu *vcpu)
4886 {
4887         struct vcpu_vmx *vmx = to_vmx(vcpu);
4888         gva_t gva;
4889         gpa_t vmptr;
4890         struct vmcs12 *vmcs12;
4891         struct page *page;
4892         struct x86_exception e;
4893
4894         if (!nested_vmx_check_permission(vcpu))
4895                 return 1;
4896
4897         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
4898                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
4899                 return 1;
4900
4901         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
4902                                 sizeof(vmptr), &e)) {
4903                 kvm_inject_page_fault(vcpu, &e);
4904                 return 1;
4905         }
4906
4907         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
4908                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
4909                 skip_emulated_instruction(vcpu);
4910                 return 1;
4911         }
4912
4913         if (vmptr == vmx->nested.current_vmptr) {
4914                 kunmap(vmx->nested.current_vmcs12_page);
4915                 nested_release_page(vmx->nested.current_vmcs12_page);
4916                 vmx->nested.current_vmptr = -1ull;
4917                 vmx->nested.current_vmcs12 = NULL;
4918         }
4919
4920         page = nested_get_page(vcpu, vmptr);
4921         if (page == NULL) {
4922                 /*
4923                  * For accurate processor emulation, VMCLEAR beyond available
4924                  * physical memory should do nothing at all. However, it is
4925                  * possible that a nested vmx bug, not a guest hypervisor bug,
4926                  * resulted in this case, so let's shut down before doing any
4927                  * more damage:
4928                  */
4929                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4930                 return 1;
4931         }
4932         vmcs12 = kmap(page);
4933         vmcs12->launch_state = 0;
4934         kunmap(page);
4935         nested_release_page(page);
4936
4937         nested_free_vmcs02(vmx, vmptr);
4938
4939         skip_emulated_instruction(vcpu);
4940         nested_vmx_succeed(vcpu);
4941         return 1;
4942 }
4943
4944 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
4945
4946 /* Emulate the VMLAUNCH instruction */
4947 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
4948 {
4949         return nested_vmx_run(vcpu, true);
4950 }
4951
4952 /* Emulate the VMRESUME instruction */
4953 static int handle_vmresume(struct kvm_vcpu *vcpu)
4954 {
4955
4956         return nested_vmx_run(vcpu, false);
4957 }
4958
4959 enum vmcs_field_type {
4960         VMCS_FIELD_TYPE_U16 = 0,
4961         VMCS_FIELD_TYPE_U64 = 1,
4962         VMCS_FIELD_TYPE_U32 = 2,
4963         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
4964 };
4965
4966 static inline int vmcs_field_type(unsigned long field)
4967 {
4968         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
4969                 return VMCS_FIELD_TYPE_U32;
4970         return (field >> 13) & 0x3 ;
4971 }
4972
4973 static inline int vmcs_field_readonly(unsigned long field)
4974 {
4975         return (((field >> 10) & 0x3) == 1);
4976 }
4977
4978 /*
4979  * Read a vmcs12 field. Since these can have varying lengths and we return
4980  * one type, we chose the biggest type (u64) and zero-extend the return value
4981  * to that size. Note that the caller, handle_vmread, might need to use only
4982  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
4983  * 64-bit fields are to be returned).
4984  */
4985 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
4986                                         unsigned long field, u64 *ret)
4987 {
4988         short offset = vmcs_field_to_offset(field);
4989         char *p;
4990
4991         if (offset < 0)
4992                 return 0;
4993
4994         p = ((char *)(get_vmcs12(vcpu))) + offset;
4995
4996         switch (vmcs_field_type(field)) {
4997         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
4998                 *ret = *((natural_width *)p);
4999                 return 1;
5000         case VMCS_FIELD_TYPE_U16:
5001                 *ret = *((u16 *)p);
5002                 return 1;
5003         case VMCS_FIELD_TYPE_U32:
5004                 *ret = *((u32 *)p);
5005                 return 1;
5006         case VMCS_FIELD_TYPE_U64:
5007                 *ret = *((u64 *)p);
5008                 return 1;
5009         default:
5010                 return 0; /* can never happen. */
5011         }
5012 }
5013
5014 /*
5015  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5016  * used before) all generate the same failure when it is missing.
5017  */
5018 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5019 {
5020         struct vcpu_vmx *vmx = to_vmx(vcpu);
5021         if (vmx->nested.current_vmptr == -1ull) {
5022                 nested_vmx_failInvalid(vcpu);
5023                 skip_emulated_instruction(vcpu);
5024                 return 0;
5025         }
5026         return 1;
5027 }
5028
5029 static int handle_vmread(struct kvm_vcpu *vcpu)
5030 {
5031         unsigned long field;
5032         u64 field_value;
5033         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5034         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5035         gva_t gva = 0;
5036
5037         if (!nested_vmx_check_permission(vcpu) ||
5038             !nested_vmx_check_vmcs12(vcpu))
5039                 return 1;
5040
5041         /* Decode instruction info and find the field to read */
5042         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5043         /* Read the field, zero-extended to a u64 field_value */
5044         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5045                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5046                 skip_emulated_instruction(vcpu);
5047                 return 1;
5048         }
5049         /*
5050          * Now copy part of this value to register or memory, as requested.
5051          * Note that the number of bits actually copied is 32 or 64 depending
5052          * on the guest's mode (32 or 64 bit), not on the given field's length.
5053          */
5054         if (vmx_instruction_info & (1u << 10)) {
5055                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5056                         field_value);
5057         } else {
5058                 if (get_vmx_mem_address(vcpu, exit_qualification,
5059                                 vmx_instruction_info, &gva))
5060                         return 1;
5061                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5062                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5063                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5064         }
5065
5066         nested_vmx_succeed(vcpu);
5067         skip_emulated_instruction(vcpu);
5068         return 1;
5069 }
5070
5071
5072 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5073 {
5074         unsigned long field;
5075         gva_t gva;
5076         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5077         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5078         char *p;
5079         short offset;
5080         /* The value to write might be 32 or 64 bits, depending on L1's long
5081          * mode, and eventually we need to write that into a field of several
5082          * possible lengths. The code below first zero-extends the value to 64
5083          * bit (field_value), and then copies only the approriate number of
5084          * bits into the vmcs12 field.
5085          */
5086         u64 field_value = 0;
5087         struct x86_exception e;
5088
5089         if (!nested_vmx_check_permission(vcpu) ||
5090             !nested_vmx_check_vmcs12(vcpu))
5091                 return 1;
5092
5093         if (vmx_instruction_info & (1u << 10))
5094                 field_value = kvm_register_read(vcpu,
5095                         (((vmx_instruction_info) >> 3) & 0xf));
5096         else {
5097                 if (get_vmx_mem_address(vcpu, exit_qualification,
5098                                 vmx_instruction_info, &gva))
5099                         return 1;
5100                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5101                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5102                         kvm_inject_page_fault(vcpu, &e);
5103                         return 1;
5104                 }
5105         }
5106
5107
5108         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5109         if (vmcs_field_readonly(field)) {
5110                 nested_vmx_failValid(vcpu,
5111                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5112                 skip_emulated_instruction(vcpu);
5113                 return 1;
5114         }
5115
5116         offset = vmcs_field_to_offset(field);
5117         if (offset < 0) {
5118                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5119                 skip_emulated_instruction(vcpu);
5120                 return 1;
5121         }
5122         p = ((char *) get_vmcs12(vcpu)) + offset;
5123
5124         switch (vmcs_field_type(field)) {
5125         case VMCS_FIELD_TYPE_U16:
5126                 *(u16 *)p = field_value;
5127                 break;
5128         case VMCS_FIELD_TYPE_U32:
5129                 *(u32 *)p = field_value;
5130                 break;
5131         case VMCS_FIELD_TYPE_U64:
5132                 *(u64 *)p = field_value;
5133                 break;
5134         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5135                 *(natural_width *)p = field_value;
5136                 break;
5137         default:
5138                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5139                 skip_emulated_instruction(vcpu);
5140                 return 1;
5141         }
5142
5143         nested_vmx_succeed(vcpu);
5144         skip_emulated_instruction(vcpu);
5145         return 1;
5146 }
5147
5148 /* Emulate the VMPTRLD instruction */
5149 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5150 {
5151         struct vcpu_vmx *vmx = to_vmx(vcpu);
5152         gva_t gva;
5153         gpa_t vmptr;
5154         struct x86_exception e;
5155
5156         if (!nested_vmx_check_permission(vcpu))
5157                 return 1;
5158
5159         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5160                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5161                 return 1;
5162
5163         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5164                                 sizeof(vmptr), &e)) {
5165                 kvm_inject_page_fault(vcpu, &e);
5166                 return 1;
5167         }
5168
5169         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5170                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5171                 skip_emulated_instruction(vcpu);
5172                 return 1;
5173         }
5174
5175         if (vmx->nested.current_vmptr != vmptr) {
5176                 struct vmcs12 *new_vmcs12;
5177                 struct page *page;
5178                 page = nested_get_page(vcpu, vmptr);
5179                 if (page == NULL) {
5180                         nested_vmx_failInvalid(vcpu);
5181                         skip_emulated_instruction(vcpu);
5182                         return 1;
5183                 }
5184                 new_vmcs12 = kmap(page);
5185                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5186                         kunmap(page);
5187                         nested_release_page_clean(page);
5188                         nested_vmx_failValid(vcpu,
5189                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5190                         skip_emulated_instruction(vcpu);
5191                         return 1;
5192                 }
5193                 if (vmx->nested.current_vmptr != -1ull) {
5194                         kunmap(vmx->nested.current_vmcs12_page);
5195                         nested_release_page(vmx->nested.current_vmcs12_page);
5196                 }
5197
5198                 vmx->nested.current_vmptr = vmptr;
5199                 vmx->nested.current_vmcs12 = new_vmcs12;
5200                 vmx->nested.current_vmcs12_page = page;
5201         }
5202
5203         nested_vmx_succeed(vcpu);
5204         skip_emulated_instruction(vcpu);
5205         return 1;
5206 }
5207
5208 /* Emulate the VMPTRST instruction */
5209 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5210 {
5211         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5212         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5213         gva_t vmcs_gva;
5214         struct x86_exception e;
5215
5216         if (!nested_vmx_check_permission(vcpu))
5217                 return 1;
5218
5219         if (get_vmx_mem_address(vcpu, exit_qualification,
5220                         vmx_instruction_info, &vmcs_gva))
5221                 return 1;
5222         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5223         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5224                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5225                                  sizeof(u64), &e)) {
5226                 kvm_inject_page_fault(vcpu, &e);
5227                 return 1;
5228         }
5229         nested_vmx_succeed(vcpu);
5230         skip_emulated_instruction(vcpu);
5231         return 1;
5232 }
5233
5234 /*
5235  * The exit handlers return 1 if the exit was handled fully and guest execution
5236  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5237  * to be done to userspace and return 0.
5238  */
5239 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5240         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5241         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5242         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5243         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5244         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5245         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5246         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5247         [EXIT_REASON_CPUID]                   = handle_cpuid,
5248         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5249         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5250         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5251         [EXIT_REASON_HLT]                     = handle_halt,
5252         [EXIT_REASON_INVD]                    = handle_invd,
5253         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5254         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5255         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5256         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5257         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5258         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5259         [EXIT_REASON_VMREAD]                  = handle_vmread,
5260         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5261         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5262         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5263         [EXIT_REASON_VMON]                    = handle_vmon,
5264         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5265         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5266         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5267         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5268         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5269         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5270         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5271         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5272         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5273         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5274         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5275 };
5276
5277 static const int kvm_vmx_max_exit_handlers =
5278         ARRAY_SIZE(kvm_vmx_exit_handlers);
5279
5280 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5281 {
5282         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5283         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5284 }
5285
5286 /*
5287  * The guest has exited.  See if we can fix it or if we need userspace
5288  * assistance.
5289  */
5290 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5291 {
5292         struct vcpu_vmx *vmx = to_vmx(vcpu);
5293         u32 exit_reason = vmx->exit_reason;
5294         u32 vectoring_info = vmx->idt_vectoring_info;
5295
5296         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5297
5298         /* If guest state is invalid, start emulating */
5299         if (vmx->emulation_required && emulate_invalid_guest_state)
5300                 return handle_invalid_guest_state(vcpu);
5301
5302         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5303                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5304                 vcpu->run->fail_entry.hardware_entry_failure_reason
5305                         = exit_reason;
5306                 return 0;
5307         }
5308
5309         if (unlikely(vmx->fail)) {
5310                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5311                 vcpu->run->fail_entry.hardware_entry_failure_reason
5312                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5313                 return 0;
5314         }
5315
5316         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5317                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5318                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5319                         exit_reason != EXIT_REASON_TASK_SWITCH))
5320                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5321                        "(0x%x) and exit reason is 0x%x\n",
5322                        __func__, vectoring_info, exit_reason);
5323
5324         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
5325                 if (vmx_interrupt_allowed(vcpu)) {
5326                         vmx->soft_vnmi_blocked = 0;
5327                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5328                            vcpu->arch.nmi_pending) {
5329                         /*
5330                          * This CPU don't support us in finding the end of an
5331                          * NMI-blocked window if the guest runs with IRQs
5332                          * disabled. So we pull the trigger after 1 s of
5333                          * futile waiting, but inform the user about this.
5334                          */
5335                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5336                                "state on VCPU %d after 1 s timeout\n",
5337                                __func__, vcpu->vcpu_id);
5338                         vmx->soft_vnmi_blocked = 0;
5339                 }
5340         }
5341
5342         if (exit_reason < kvm_vmx_max_exit_handlers
5343             && kvm_vmx_exit_handlers[exit_reason])
5344                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5345         else {
5346                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5347                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5348         }
5349         return 0;
5350 }
5351
5352 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5353 {
5354         if (irr == -1 || tpr < irr) {
5355                 vmcs_write32(TPR_THRESHOLD, 0);
5356                 return;
5357         }
5358
5359         vmcs_write32(TPR_THRESHOLD, irr);
5360 }
5361
5362 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5363 {
5364         u32 exit_intr_info;
5365
5366         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5367               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5368                 return;
5369
5370         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5371         exit_intr_info = vmx->exit_intr_info;
5372
5373         /* Handle machine checks before interrupts are enabled */
5374         if (is_machine_check(exit_intr_info))
5375                 kvm_machine_check();
5376
5377         /* We need to handle NMIs before interrupts are enabled */
5378         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5379             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5380                 kvm_before_handle_nmi(&vmx->vcpu);
5381                 asm("int $2");
5382                 kvm_after_handle_nmi(&vmx->vcpu);
5383         }
5384 }
5385
5386 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5387 {
5388         u32 exit_intr_info;
5389         bool unblock_nmi;
5390         u8 vector;
5391         bool idtv_info_valid;
5392
5393         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5394
5395         if (cpu_has_virtual_nmis()) {
5396                 if (vmx->nmi_known_unmasked)
5397                         return;
5398                 /*
5399                  * Can't use vmx->exit_intr_info since we're not sure what
5400                  * the exit reason is.
5401                  */
5402                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5403                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5404                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5405                 /*
5406                  * SDM 3: 27.7.1.2 (September 2008)
5407                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5408                  * a guest IRET fault.
5409                  * SDM 3: 23.2.2 (September 2008)
5410                  * Bit 12 is undefined in any of the following cases:
5411                  *  If the VM exit sets the valid bit in the IDT-vectoring
5412                  *   information field.
5413                  *  If the VM exit is due to a double fault.
5414                  */
5415                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5416                     vector != DF_VECTOR && !idtv_info_valid)
5417                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5418                                       GUEST_INTR_STATE_NMI);
5419                 else
5420                         vmx->nmi_known_unmasked =
5421                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5422                                   & GUEST_INTR_STATE_NMI);
5423         } else if (unlikely(vmx->soft_vnmi_blocked))
5424                 vmx->vnmi_blocked_time +=
5425                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5426 }
5427
5428 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5429                                       u32 idt_vectoring_info,
5430                                       int instr_len_field,
5431                                       int error_code_field)
5432 {
5433         u8 vector;
5434         int type;
5435         bool idtv_info_valid;
5436
5437         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5438
5439         vmx->vcpu.arch.nmi_injected = false;
5440         kvm_clear_exception_queue(&vmx->vcpu);
5441         kvm_clear_interrupt_queue(&vmx->vcpu);
5442
5443         if (!idtv_info_valid)
5444                 return;
5445
5446         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5447
5448         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5449         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
5450
5451         switch (type) {
5452         case INTR_TYPE_NMI_INTR:
5453                 vmx->vcpu.arch.nmi_injected = true;
5454                 /*
5455                  * SDM 3: 27.7.1.2 (September 2008)
5456                  * Clear bit "block by NMI" before VM entry if a NMI
5457                  * delivery faulted.
5458                  */
5459                 vmx_set_nmi_mask(&vmx->vcpu, false);
5460                 break;
5461         case INTR_TYPE_SOFT_EXCEPTION:
5462                 vmx->vcpu.arch.event_exit_inst_len =
5463                         vmcs_read32(instr_len_field);
5464                 /* fall through */
5465         case INTR_TYPE_HARD_EXCEPTION:
5466                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5467                         u32 err = vmcs_read32(error_code_field);
5468                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
5469                 } else
5470                         kvm_queue_exception(&vmx->vcpu, vector);
5471                 break;
5472         case INTR_TYPE_SOFT_INTR:
5473                 vmx->vcpu.arch.event_exit_inst_len =
5474                         vmcs_read32(instr_len_field);
5475                 /* fall through */
5476         case INTR_TYPE_EXT_INTR:
5477                 kvm_queue_interrupt(&vmx->vcpu, vector,
5478                         type == INTR_TYPE_SOFT_INTR);
5479                 break;
5480         default:
5481                 break;
5482         }
5483 }
5484
5485 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5486 {
5487         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5488                                   VM_EXIT_INSTRUCTION_LEN,
5489                                   IDT_VECTORING_ERROR_CODE);
5490 }
5491
5492 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5493 {
5494         __vmx_complete_interrupts(to_vmx(vcpu),
5495                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5496                                   VM_ENTRY_INSTRUCTION_LEN,
5497                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
5498
5499         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5500 }
5501
5502 #ifdef CONFIG_X86_64
5503 #define R "r"
5504 #define Q "q"
5505 #else
5506 #define R "e"
5507 #define Q "l"
5508 #endif
5509
5510 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5511 {
5512         struct vcpu_vmx *vmx = to_vmx(vcpu);
5513
5514         /* Record the guest's net vcpu time for enforced NMI injections. */
5515         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5516                 vmx->entry_time = ktime_get();
5517
5518         /* Don't enter VMX if guest state is invalid, let the exit handler
5519            start emulation until we arrive back to a valid state */
5520         if (vmx->emulation_required && emulate_invalid_guest_state)
5521                 return;
5522
5523         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5524                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5525         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5526                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5527
5528         /* When single-stepping over STI and MOV SS, we must clear the
5529          * corresponding interruptibility bits in the guest state. Otherwise
5530          * vmentry fails as it then expects bit 14 (BS) in pending debug
5531          * exceptions being set, but that's not correct for the guest debugging
5532          * case. */
5533         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5534                 vmx_set_interrupt_shadow(vcpu, 0);
5535
5536         vmx->__launched = vmx->loaded_vmcs->launched;
5537         asm(
5538                 /* Store host registers */
5539                 "push %%"R"dx; push %%"R"bp;"
5540                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
5541                 "push %%"R"cx \n\t"
5542                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5543                 "je 1f \n\t"
5544                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
5545                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
5546                 "1: \n\t"
5547                 /* Reload cr2 if changed */
5548                 "mov %c[cr2](%0), %%"R"ax \n\t"
5549                 "mov %%cr2, %%"R"dx \n\t"
5550                 "cmp %%"R"ax, %%"R"dx \n\t"
5551                 "je 2f \n\t"
5552                 "mov %%"R"ax, %%cr2 \n\t"
5553                 "2: \n\t"
5554                 /* Check if vmlaunch of vmresume is needed */
5555                 "cmpl $0, %c[launched](%0) \n\t"
5556                 /* Load guest registers.  Don't clobber flags. */
5557                 "mov %c[rax](%0), %%"R"ax \n\t"
5558                 "mov %c[rbx](%0), %%"R"bx \n\t"
5559                 "mov %c[rdx](%0), %%"R"dx \n\t"
5560                 "mov %c[rsi](%0), %%"R"si \n\t"
5561                 "mov %c[rdi](%0), %%"R"di \n\t"
5562                 "mov %c[rbp](%0), %%"R"bp \n\t"
5563 #ifdef CONFIG_X86_64
5564                 "mov %c[r8](%0),  %%r8  \n\t"
5565                 "mov %c[r9](%0),  %%r9  \n\t"
5566                 "mov %c[r10](%0), %%r10 \n\t"
5567                 "mov %c[r11](%0), %%r11 \n\t"
5568                 "mov %c[r12](%0), %%r12 \n\t"
5569                 "mov %c[r13](%0), %%r13 \n\t"
5570                 "mov %c[r14](%0), %%r14 \n\t"
5571                 "mov %c[r15](%0), %%r15 \n\t"
5572 #endif
5573                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5574
5575                 /* Enter guest mode */
5576                 "jne .Llaunched \n\t"
5577                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
5578                 "jmp .Lkvm_vmx_return \n\t"
5579                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
5580                 ".Lkvm_vmx_return: "
5581                 /* Save guest registers, load host registers, keep flags */
5582                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5583                 "pop %0 \n\t"
5584                 "mov %%"R"ax, %c[rax](%0) \n\t"
5585                 "mov %%"R"bx, %c[rbx](%0) \n\t"
5586                 "pop"Q" %c[rcx](%0) \n\t"
5587                 "mov %%"R"dx, %c[rdx](%0) \n\t"
5588                 "mov %%"R"si, %c[rsi](%0) \n\t"
5589                 "mov %%"R"di, %c[rdi](%0) \n\t"
5590                 "mov %%"R"bp, %c[rbp](%0) \n\t"
5591 #ifdef CONFIG_X86_64
5592                 "mov %%r8,  %c[r8](%0) \n\t"
5593                 "mov %%r9,  %c[r9](%0) \n\t"
5594                 "mov %%r10, %c[r10](%0) \n\t"
5595                 "mov %%r11, %c[r11](%0) \n\t"
5596                 "mov %%r12, %c[r12](%0) \n\t"
5597                 "mov %%r13, %c[r13](%0) \n\t"
5598                 "mov %%r14, %c[r14](%0) \n\t"
5599                 "mov %%r15, %c[r15](%0) \n\t"
5600 #endif
5601                 "mov %%cr2, %%"R"ax   \n\t"
5602                 "mov %%"R"ax, %c[cr2](%0) \n\t"
5603
5604                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
5605                 "setbe %c[fail](%0) \n\t"
5606               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
5607                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
5608                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
5609                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
5610                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
5611                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
5612                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
5613                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
5614                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
5615                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
5616                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
5617 #ifdef CONFIG_X86_64
5618                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
5619                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
5620                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
5621                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
5622                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
5623                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
5624                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
5625                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
5626 #endif
5627                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
5628                 [wordsize]"i"(sizeof(ulong))
5629               : "cc", "memory"
5630                 , R"ax", R"bx", R"di", R"si"
5631 #ifdef CONFIG_X86_64
5632                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5633 #endif
5634               );
5635
5636         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
5637                                   | (1 << VCPU_EXREG_RFLAGS)
5638                                   | (1 << VCPU_EXREG_CPL)
5639                                   | (1 << VCPU_EXREG_PDPTR)
5640                                   | (1 << VCPU_EXREG_SEGMENTS)
5641                                   | (1 << VCPU_EXREG_CR3));
5642         vcpu->arch.regs_dirty = 0;
5643
5644         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
5645
5646         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
5647         vmx->loaded_vmcs->launched = 1;
5648
5649         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
5650
5651         vmx_complete_atomic_exit(vmx);
5652         vmx_recover_nmi_blocking(vmx);
5653         vmx_complete_interrupts(vmx);
5654 }
5655
5656 #undef R
5657 #undef Q
5658
5659 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
5660 {
5661         struct vcpu_vmx *vmx = to_vmx(vcpu);
5662
5663         free_vpid(vmx);
5664         free_nested(vmx);
5665         free_loaded_vmcs(vmx->loaded_vmcs);
5666         kfree(vmx->guest_msrs);
5667         kvm_vcpu_uninit(vcpu);
5668         kmem_cache_free(kvm_vcpu_cache, vmx);
5669 }
5670
5671 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
5672 {
5673         int err;
5674         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
5675         int cpu;
5676
5677         if (!vmx)
5678                 return ERR_PTR(-ENOMEM);
5679
5680         allocate_vpid(vmx);
5681
5682         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
5683         if (err)
5684                 goto free_vcpu;
5685
5686         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
5687         err = -ENOMEM;
5688         if (!vmx->guest_msrs) {
5689                 goto uninit_vcpu;
5690         }
5691
5692         vmx->loaded_vmcs = &vmx->vmcs01;
5693         vmx->loaded_vmcs->vmcs = alloc_vmcs();
5694         if (!vmx->loaded_vmcs->vmcs)
5695                 goto free_msrs;
5696         if (!vmm_exclusive)
5697                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
5698         loaded_vmcs_init(vmx->loaded_vmcs);
5699         if (!vmm_exclusive)
5700                 kvm_cpu_vmxoff();
5701
5702         cpu = get_cpu();
5703         vmx_vcpu_load(&vmx->vcpu, cpu);
5704         vmx->vcpu.cpu = cpu;
5705         err = vmx_vcpu_setup(vmx);
5706         vmx_vcpu_put(&vmx->vcpu);
5707         put_cpu();
5708         if (err)
5709                 goto free_vmcs;
5710         if (vm_need_virtualize_apic_accesses(kvm))
5711                 err = alloc_apic_access_page(kvm);
5712                 if (err)
5713                         goto free_vmcs;
5714
5715         if (enable_ept) {
5716                 if (!kvm->arch.ept_identity_map_addr)
5717                         kvm->arch.ept_identity_map_addr =
5718                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5719                 err = -ENOMEM;
5720                 if (alloc_identity_pagetable(kvm) != 0)
5721                         goto free_vmcs;
5722                 if (!init_rmode_identity_map(kvm))
5723                         goto free_vmcs;
5724         }
5725
5726         vmx->nested.current_vmptr = -1ull;
5727         vmx->nested.current_vmcs12 = NULL;
5728
5729         return &vmx->vcpu;
5730
5731 free_vmcs:
5732         free_vmcs(vmx->loaded_vmcs->vmcs);
5733 free_msrs:
5734         kfree(vmx->guest_msrs);
5735 uninit_vcpu:
5736         kvm_vcpu_uninit(&vmx->vcpu);
5737 free_vcpu:
5738         free_vpid(vmx);
5739         kmem_cache_free(kvm_vcpu_cache, vmx);
5740         return ERR_PTR(err);
5741 }
5742
5743 static void __init vmx_check_processor_compat(void *rtn)
5744 {
5745         struct vmcs_config vmcs_conf;
5746
5747         *(int *)rtn = 0;
5748         if (setup_vmcs_config(&vmcs_conf) < 0)
5749                 *(int *)rtn = -EIO;
5750         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
5751                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
5752                                 smp_processor_id());
5753                 *(int *)rtn = -EIO;
5754         }
5755 }
5756
5757 static int get_ept_level(void)
5758 {
5759         return VMX_EPT_DEFAULT_GAW + 1;
5760 }
5761
5762 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5763 {
5764         u64 ret;
5765
5766         /* For VT-d and EPT combination
5767          * 1. MMIO: always map as UC
5768          * 2. EPT with VT-d:
5769          *   a. VT-d without snooping control feature: can't guarantee the
5770          *      result, try to trust guest.
5771          *   b. VT-d with snooping control feature: snooping control feature of
5772          *      VT-d engine can guarantee the cache correctness. Just set it
5773          *      to WB to keep consistent with host. So the same as item 3.
5774          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
5775          *    consistent with host MTRR
5776          */
5777         if (is_mmio)
5778                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
5779         else if (vcpu->kvm->arch.iommu_domain &&
5780                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
5781                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
5782                       VMX_EPT_MT_EPTE_SHIFT;
5783         else
5784                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
5785                         | VMX_EPT_IPAT_BIT;
5786
5787         return ret;
5788 }
5789
5790 #define _ER(x) { EXIT_REASON_##x, #x }
5791
5792 static const struct trace_print_flags vmx_exit_reasons_str[] = {
5793         _ER(EXCEPTION_NMI),
5794         _ER(EXTERNAL_INTERRUPT),
5795         _ER(TRIPLE_FAULT),
5796         _ER(PENDING_INTERRUPT),
5797         _ER(NMI_WINDOW),
5798         _ER(TASK_SWITCH),
5799         _ER(CPUID),
5800         _ER(HLT),
5801         _ER(INVLPG),
5802         _ER(RDPMC),
5803         _ER(RDTSC),
5804         _ER(VMCALL),
5805         _ER(VMCLEAR),
5806         _ER(VMLAUNCH),
5807         _ER(VMPTRLD),
5808         _ER(VMPTRST),
5809         _ER(VMREAD),
5810         _ER(VMRESUME),
5811         _ER(VMWRITE),
5812         _ER(VMOFF),
5813         _ER(VMON),
5814         _ER(CR_ACCESS),
5815         _ER(DR_ACCESS),
5816         _ER(IO_INSTRUCTION),
5817         _ER(MSR_READ),
5818         _ER(MSR_WRITE),
5819         _ER(MWAIT_INSTRUCTION),
5820         _ER(MONITOR_INSTRUCTION),
5821         _ER(PAUSE_INSTRUCTION),
5822         _ER(MCE_DURING_VMENTRY),
5823         _ER(TPR_BELOW_THRESHOLD),
5824         _ER(APIC_ACCESS),
5825         _ER(EPT_VIOLATION),
5826         _ER(EPT_MISCONFIG),
5827         _ER(WBINVD),
5828         { -1, NULL }
5829 };
5830
5831 #undef _ER
5832
5833 static int vmx_get_lpage_level(void)
5834 {
5835         if (enable_ept && !cpu_has_vmx_ept_1g_page())
5836                 return PT_DIRECTORY_LEVEL;
5837         else
5838                 /* For shadow and EPT supported 1GB page */
5839                 return PT_PDPE_LEVEL;
5840 }
5841
5842 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
5843 {
5844         struct kvm_cpuid_entry2 *best;
5845         struct vcpu_vmx *vmx = to_vmx(vcpu);
5846         u32 exec_control;
5847
5848         vmx->rdtscp_enabled = false;
5849         if (vmx_rdtscp_supported()) {
5850                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5851                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
5852                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
5853                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
5854                                 vmx->rdtscp_enabled = true;
5855                         else {
5856                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
5857                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5858                                                 exec_control);
5859                         }
5860                 }
5861         }
5862 }
5863
5864 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5865 {
5866 }
5867
5868 /*
5869  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
5870  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
5871  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
5872  * guest in a way that will both be appropriate to L1's requests, and our
5873  * needs. In addition to modifying the active vmcs (which is vmcs02), this
5874  * function also has additional necessary side-effects, like setting various
5875  * vcpu->arch fields.
5876  */
5877 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
5878 {
5879         struct vcpu_vmx *vmx = to_vmx(vcpu);
5880         u32 exec_control;
5881
5882         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
5883         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
5884         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
5885         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
5886         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
5887         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
5888         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
5889         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
5890         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
5891         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
5892         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
5893         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
5894         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
5895         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
5896         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
5897         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
5898         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
5899         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
5900         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
5901         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
5902         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
5903         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
5904         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
5905         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
5906         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
5907         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
5908         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
5909         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
5910         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
5911         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
5912         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
5913         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
5914         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
5915         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
5916         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
5917         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
5918
5919         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
5920         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5921                 vmcs12->vm_entry_intr_info_field);
5922         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
5923                 vmcs12->vm_entry_exception_error_code);
5924         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5925                 vmcs12->vm_entry_instruction_len);
5926         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
5927                 vmcs12->guest_interruptibility_info);
5928         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
5929         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
5930         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
5931         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
5932         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
5933                 vmcs12->guest_pending_dbg_exceptions);
5934         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
5935         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
5936
5937         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5938
5939         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
5940                 (vmcs_config.pin_based_exec_ctrl |
5941                  vmcs12->pin_based_vm_exec_control));
5942
5943         /*
5944          * Whether page-faults are trapped is determined by a combination of
5945          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
5946          * If enable_ept, L0 doesn't care about page faults and we should
5947          * set all of these to L1's desires. However, if !enable_ept, L0 does
5948          * care about (at least some) page faults, and because it is not easy
5949          * (if at all possible?) to merge L0 and L1's desires, we simply ask
5950          * to exit on each and every L2 page fault. This is done by setting
5951          * MASK=MATCH=0 and (see below) EB.PF=1.
5952          * Note that below we don't need special code to set EB.PF beyond the
5953          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
5954          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
5955          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
5956          *
5957          * A problem with this approach (when !enable_ept) is that L1 may be
5958          * injected with more page faults than it asked for. This could have
5959          * caused problems, but in practice existing hypervisors don't care.
5960          * To fix this, we will need to emulate the PFEC checking (on the L1
5961          * page tables), using walk_addr(), when injecting PFs to L1.
5962          */
5963         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
5964                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
5965         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
5966                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
5967
5968         if (cpu_has_secondary_exec_ctrls()) {
5969                 u32 exec_control = vmx_secondary_exec_control(vmx);
5970                 if (!vmx->rdtscp_enabled)
5971                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
5972                 /* Take the following fields only from vmcs12 */
5973                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5974                 if (nested_cpu_has(vmcs12,
5975                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
5976                         exec_control |= vmcs12->secondary_vm_exec_control;
5977
5978                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
5979                         /*
5980                          * Translate L1 physical address to host physical
5981                          * address for vmcs02. Keep the page pinned, so this
5982                          * physical address remains valid. We keep a reference
5983                          * to it so we can release it later.
5984                          */
5985                         if (vmx->nested.apic_access_page) /* shouldn't happen */
5986                                 nested_release_page(vmx->nested.apic_access_page);
5987                         vmx->nested.apic_access_page =
5988                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
5989                         /*
5990                          * If translation failed, no matter: This feature asks
5991                          * to exit when accessing the given address, and if it
5992                          * can never be accessed, this feature won't do
5993                          * anything anyway.
5994                          */
5995                         if (!vmx->nested.apic_access_page)
5996                                 exec_control &=
5997                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5998                         else
5999                                 vmcs_write64(APIC_ACCESS_ADDR,
6000                                   page_to_phys(vmx->nested.apic_access_page));
6001                 }
6002
6003                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6004         }
6005
6006
6007         /*
6008          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6009          * Some constant fields are set here by vmx_set_constant_host_state().
6010          * Other fields are different per CPU, and will be set later when
6011          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6012          */
6013         vmx_set_constant_host_state();
6014
6015         /*
6016          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6017          * entry, but only if the current (host) sp changed from the value
6018          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6019          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6020          * here we just force the write to happen on entry.
6021          */
6022         vmx->host_rsp = 0;
6023
6024         exec_control = vmx_exec_control(vmx); /* L0's desires */
6025         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6026         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6027         exec_control &= ~CPU_BASED_TPR_SHADOW;
6028         exec_control |= vmcs12->cpu_based_vm_exec_control;
6029         /*
6030          * Merging of IO and MSR bitmaps not currently supported.
6031          * Rather, exit every time.
6032          */
6033         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6034         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6035         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6036
6037         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6038
6039         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6040          * bitwise-or of what L1 wants to trap for L2, and what we want to
6041          * trap. Note that CR0.TS also needs updating - we do this later.
6042          */
6043         update_exception_bitmap(vcpu);
6044         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6045         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6046
6047         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6048         vmcs_write32(VM_EXIT_CONTROLS,
6049                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6050         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6051                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6052
6053         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6054                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6055         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6056                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6057
6058
6059         set_cr4_guest_host_mask(vmx);
6060
6061         vmcs_write64(TSC_OFFSET,
6062                 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6063
6064         if (enable_vpid) {
6065                 /*
6066                  * Trivially support vpid by letting L2s share their parent
6067                  * L1's vpid. TODO: move to a more elaborate solution, giving
6068                  * each L2 its own vpid and exposing the vpid feature to L1.
6069                  */
6070                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6071                 vmx_flush_tlb(vcpu);
6072         }
6073
6074         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6075                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6076         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6077                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6078         else
6079                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6080         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6081         vmx_set_efer(vcpu, vcpu->arch.efer);
6082
6083         /*
6084          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6085          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6086          * The CR0_READ_SHADOW is what L2 should have expected to read given
6087          * the specifications by L1; It's not enough to take
6088          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6089          * have more bits than L1 expected.
6090          */
6091         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6092         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6093
6094         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6095         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6096
6097         /* shadow page tables on either EPT or shadow page tables */
6098         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6099         kvm_mmu_reset_context(vcpu);
6100
6101         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6102         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6103 }
6104
6105 /*
6106  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6107  * for running an L2 nested guest.
6108  */
6109 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6110 {
6111         struct vmcs12 *vmcs12;
6112         struct vcpu_vmx *vmx = to_vmx(vcpu);
6113         int cpu;
6114         struct loaded_vmcs *vmcs02;
6115
6116         if (!nested_vmx_check_permission(vcpu) ||
6117             !nested_vmx_check_vmcs12(vcpu))
6118                 return 1;
6119
6120         skip_emulated_instruction(vcpu);
6121         vmcs12 = get_vmcs12(vcpu);
6122
6123         /*
6124          * The nested entry process starts with enforcing various prerequisites
6125          * on vmcs12 as required by the Intel SDM, and act appropriately when
6126          * they fail: As the SDM explains, some conditions should cause the
6127          * instruction to fail, while others will cause the instruction to seem
6128          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6129          * To speed up the normal (success) code path, we should avoid checking
6130          * for misconfigurations which will anyway be caught by the processor
6131          * when using the merged vmcs02.
6132          */
6133         if (vmcs12->launch_state == launch) {
6134                 nested_vmx_failValid(vcpu,
6135                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6136                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6137                 return 1;
6138         }
6139
6140         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6141                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6142                 /*TODO: Also verify bits beyond physical address width are 0*/
6143                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6144                 return 1;
6145         }
6146
6147         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6148                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6149                 /*TODO: Also verify bits beyond physical address width are 0*/
6150                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6151                 return 1;
6152         }
6153
6154         if (vmcs12->vm_entry_msr_load_count > 0 ||
6155             vmcs12->vm_exit_msr_load_count > 0 ||
6156             vmcs12->vm_exit_msr_store_count > 0) {
6157                 if (printk_ratelimit())
6158                         printk(KERN_WARNING
6159                           "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__);
6160                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6161                 return 1;
6162         }
6163
6164         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6165               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6166             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6167               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6168             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6169               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6170             !vmx_control_verify(vmcs12->vm_exit_controls,
6171               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6172             !vmx_control_verify(vmcs12->vm_entry_controls,
6173               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6174         {
6175                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6176                 return 1;
6177         }
6178
6179         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6180             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6181                 nested_vmx_failValid(vcpu,
6182                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6183                 return 1;
6184         }
6185
6186         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6187             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6188                 nested_vmx_entry_failure(vcpu, vmcs12,
6189                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6190                 return 1;
6191         }
6192         if (vmcs12->vmcs_link_pointer != -1ull) {
6193                 nested_vmx_entry_failure(vcpu, vmcs12,
6194                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6195                 return 1;
6196         }
6197
6198         /*
6199          * We're finally done with prerequisite checking, and can start with
6200          * the nested entry.
6201          */
6202
6203         vmcs02 = nested_get_current_vmcs02(vmx);
6204         if (!vmcs02)
6205                 return -ENOMEM;
6206
6207         enter_guest_mode(vcpu);
6208
6209         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6210
6211         cpu = get_cpu();
6212         vmx->loaded_vmcs = vmcs02;
6213         vmx_vcpu_put(vcpu);
6214         vmx_vcpu_load(vcpu, cpu);
6215         vcpu->cpu = cpu;
6216         put_cpu();
6217
6218         vmcs12->launch_state = 1;
6219
6220         prepare_vmcs02(vcpu, vmcs12);
6221
6222         /*
6223          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6224          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6225          * returned as far as L1 is concerned. It will only return (and set
6226          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6227          */
6228         return 1;
6229 }
6230
6231 /*
6232  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6233  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6234  * This function returns the new value we should put in vmcs12.guest_cr0.
6235  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6236  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6237  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6238  *     didn't trap the bit, because if L1 did, so would L0).
6239  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6240  *     been modified by L2, and L1 knows it. So just leave the old value of
6241  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6242  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6243  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6244  *     changed these bits, and therefore they need to be updated, but L0
6245  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6246  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6247  */
6248 static inline unsigned long
6249 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6250 {
6251         return
6252         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6253         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6254         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6255                         vcpu->arch.cr0_guest_owned_bits));
6256 }
6257
6258 static inline unsigned long
6259 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6260 {
6261         return
6262         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6263         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6264         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6265                         vcpu->arch.cr4_guest_owned_bits));
6266 }
6267
6268 /*
6269  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6270  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6271  * and this function updates it to reflect the changes to the guest state while
6272  * L2 was running (and perhaps made some exits which were handled directly by L0
6273  * without going back to L1), and to reflect the exit reason.
6274  * Note that we do not have to copy here all VMCS fields, just those that
6275  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6276  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6277  * which already writes to vmcs12 directly.
6278  */
6279 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6280 {
6281         /* update guest state fields: */
6282         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6283         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6284
6285         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6286         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6287         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6288         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6289
6290         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6291         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6292         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6293         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6294         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6295         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6296         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6297         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6298         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6299         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6300         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6301         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6302         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6303         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6304         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6305         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6306         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6307         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6308         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6309         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6310         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6311         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6312         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6313         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6314         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6315         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6316         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6317         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6318         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6319         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6320         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6321         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6322         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6323         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6324         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6325         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6326
6327         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6328         vmcs12->guest_interruptibility_info =
6329                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6330         vmcs12->guest_pending_dbg_exceptions =
6331                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6332
6333         /* TODO: These cannot have changed unless we have MSR bitmaps and
6334          * the relevant bit asks not to trap the change */
6335         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6336         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6337                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6338         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6339         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6340         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6341
6342         /* update exit information fields: */
6343
6344         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
6345         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6346
6347         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6348         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6349         vmcs12->idt_vectoring_info_field =
6350                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6351         vmcs12->idt_vectoring_error_code =
6352                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6353         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6354         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6355
6356         /* clear vm-entry fields which are to be cleared on exit */
6357         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6358                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6359 }
6360
6361 /*
6362  * A part of what we need to when the nested L2 guest exits and we want to
6363  * run its L1 parent, is to reset L1's guest state to the host state specified
6364  * in vmcs12.
6365  * This function is to be called not only on normal nested exit, but also on
6366  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6367  * Failures During or After Loading Guest State").
6368  * This function should be called when the active VMCS is L1's (vmcs01).
6369  */
6370 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6371 {
6372         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6373                 vcpu->arch.efer = vmcs12->host_ia32_efer;
6374         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6375                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6376         else
6377                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6378         vmx_set_efer(vcpu, vcpu->arch.efer);
6379
6380         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6381         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6382         /*
6383          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6384          * actually changed, because it depends on the current state of
6385          * fpu_active (which may have changed).
6386          * Note that vmx_set_cr0 refers to efer set above.
6387          */
6388         kvm_set_cr0(vcpu, vmcs12->host_cr0);
6389         /*
6390          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6391          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6392          * but we also need to update cr0_guest_host_mask and exception_bitmap.
6393          */
6394         update_exception_bitmap(vcpu);
6395         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6396         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6397
6398         /*
6399          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6400          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6401          */
6402         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6403         kvm_set_cr4(vcpu, vmcs12->host_cr4);
6404
6405         /* shadow page tables on either EPT or shadow page tables */
6406         kvm_set_cr3(vcpu, vmcs12->host_cr3);
6407         kvm_mmu_reset_context(vcpu);
6408
6409         if (enable_vpid) {
6410                 /*
6411                  * Trivially support vpid by letting L2s share their parent
6412                  * L1's vpid. TODO: move to a more elaborate solution, giving
6413                  * each L2 its own vpid and exposing the vpid feature to L1.
6414                  */
6415                 vmx_flush_tlb(vcpu);
6416         }
6417
6418
6419         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6420         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6421         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6422         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6423         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6424         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6425         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6426         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6427         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6428         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6429         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6430         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6431         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6432         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6433         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6434
6435         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6436                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6437         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6438                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6439                         vmcs12->host_ia32_perf_global_ctrl);
6440 }
6441
6442 /*
6443  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6444  * and modify vmcs12 to make it see what it would expect to see there if
6445  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6446  */
6447 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6448 {
6449         struct vcpu_vmx *vmx = to_vmx(vcpu);
6450         int cpu;
6451         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6452
6453         leave_guest_mode(vcpu);
6454         prepare_vmcs12(vcpu, vmcs12);
6455
6456         cpu = get_cpu();
6457         vmx->loaded_vmcs = &vmx->vmcs01;
6458         vmx_vcpu_put(vcpu);
6459         vmx_vcpu_load(vcpu, cpu);
6460         vcpu->cpu = cpu;
6461         put_cpu();
6462
6463         /* if no vmcs02 cache requested, remove the one we used */
6464         if (VMCS02_POOL_SIZE == 0)
6465                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6466
6467         load_vmcs12_host_state(vcpu, vmcs12);
6468
6469         /* Update TSC_OFFSET if vmx_adjust_tsc_offset() was used while L2 ran */
6470         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6471
6472         /* This is needed for same reason as it was needed in prepare_vmcs02 */
6473         vmx->host_rsp = 0;
6474
6475         /* Unpin physical memory we referred to in vmcs02 */
6476         if (vmx->nested.apic_access_page) {
6477                 nested_release_page(vmx->nested.apic_access_page);
6478                 vmx->nested.apic_access_page = 0;
6479         }
6480
6481         /*
6482          * Exiting from L2 to L1, we're now back to L1 which thinks it just
6483          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6484          * success or failure flag accordingly.
6485          */
6486         if (unlikely(vmx->fail)) {
6487                 vmx->fail = 0;
6488                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6489         } else
6490                 nested_vmx_succeed(vcpu);
6491 }
6492
6493 /*
6494  * L1's failure to enter L2 is a subset of a normal exit, as explained in
6495  * 23.7 "VM-entry failures during or after loading guest state" (this also
6496  * lists the acceptable exit-reason and exit-qualification parameters).
6497  * It should only be called before L2 actually succeeded to run, and when
6498  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6499  */
6500 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6501                         struct vmcs12 *vmcs12,
6502                         u32 reason, unsigned long qualification)
6503 {
6504         load_vmcs12_host_state(vcpu, vmcs12);
6505         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6506         vmcs12->exit_qualification = qualification;
6507         nested_vmx_succeed(vcpu);
6508 }
6509
6510 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6511                                struct x86_instruction_info *info,
6512                                enum x86_intercept_stage stage)
6513 {
6514         return X86EMUL_CONTINUE;
6515 }
6516
6517 static struct kvm_x86_ops vmx_x86_ops = {
6518         .cpu_has_kvm_support = cpu_has_kvm_support,
6519         .disabled_by_bios = vmx_disabled_by_bios,
6520         .hardware_setup = hardware_setup,
6521         .hardware_unsetup = hardware_unsetup,
6522         .check_processor_compatibility = vmx_check_processor_compat,
6523         .hardware_enable = hardware_enable,
6524         .hardware_disable = hardware_disable,
6525         .cpu_has_accelerated_tpr = report_flexpriority,
6526
6527         .vcpu_create = vmx_create_vcpu,
6528         .vcpu_free = vmx_free_vcpu,
6529         .vcpu_reset = vmx_vcpu_reset,
6530
6531         .prepare_guest_switch = vmx_save_host_state,
6532         .vcpu_load = vmx_vcpu_load,
6533         .vcpu_put = vmx_vcpu_put,
6534
6535         .set_guest_debug = set_guest_debug,
6536         .get_msr = vmx_get_msr,
6537         .set_msr = vmx_set_msr,
6538         .get_segment_base = vmx_get_segment_base,
6539         .get_segment = vmx_get_segment,
6540         .set_segment = vmx_set_segment,
6541         .get_cpl = vmx_get_cpl,
6542         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
6543         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
6544         .decache_cr3 = vmx_decache_cr3,
6545         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6546         .set_cr0 = vmx_set_cr0,
6547         .set_cr3 = vmx_set_cr3,
6548         .set_cr4 = vmx_set_cr4,
6549         .set_efer = vmx_set_efer,
6550         .get_idt = vmx_get_idt,
6551         .set_idt = vmx_set_idt,
6552         .get_gdt = vmx_get_gdt,
6553         .set_gdt = vmx_set_gdt,
6554         .set_dr7 = vmx_set_dr7,
6555         .cache_reg = vmx_cache_reg,
6556         .get_rflags = vmx_get_rflags,
6557         .set_rflags = vmx_set_rflags,
6558         .fpu_activate = vmx_fpu_activate,
6559         .fpu_deactivate = vmx_fpu_deactivate,
6560
6561         .tlb_flush = vmx_flush_tlb,
6562
6563         .run = vmx_vcpu_run,
6564         .handle_exit = vmx_handle_exit,
6565         .skip_emulated_instruction = skip_emulated_instruction,
6566         .set_interrupt_shadow = vmx_set_interrupt_shadow,
6567         .get_interrupt_shadow = vmx_get_interrupt_shadow,
6568         .patch_hypercall = vmx_patch_hypercall,
6569         .set_irq = vmx_inject_irq,
6570         .set_nmi = vmx_inject_nmi,
6571         .queue_exception = vmx_queue_exception,
6572         .cancel_injection = vmx_cancel_injection,
6573         .interrupt_allowed = vmx_interrupt_allowed,
6574         .nmi_allowed = vmx_nmi_allowed,
6575         .get_nmi_mask = vmx_get_nmi_mask,
6576         .set_nmi_mask = vmx_set_nmi_mask,
6577         .enable_nmi_window = enable_nmi_window,
6578         .enable_irq_window = enable_irq_window,
6579         .update_cr8_intercept = update_cr8_intercept,
6580
6581         .set_tss_addr = vmx_set_tss_addr,
6582         .get_tdp_level = get_ept_level,
6583         .get_mt_mask = vmx_get_mt_mask,
6584
6585         .get_exit_info = vmx_get_exit_info,
6586         .exit_reasons_str = vmx_exit_reasons_str,
6587
6588         .get_lpage_level = vmx_get_lpage_level,
6589
6590         .cpuid_update = vmx_cpuid_update,
6591
6592         .rdtscp_supported = vmx_rdtscp_supported,
6593
6594         .set_supported_cpuid = vmx_set_supported_cpuid,
6595
6596         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
6597
6598         .set_tsc_khz = vmx_set_tsc_khz,
6599         .write_tsc_offset = vmx_write_tsc_offset,
6600         .adjust_tsc_offset = vmx_adjust_tsc_offset,
6601         .compute_tsc_offset = vmx_compute_tsc_offset,
6602
6603         .set_tdp_cr3 = vmx_set_cr3,
6604
6605         .check_intercept = vmx_check_intercept,
6606 };
6607
6608 static int __init vmx_init(void)
6609 {
6610         int r, i;
6611
6612         rdmsrl_safe(MSR_EFER, &host_efer);
6613
6614         for (i = 0; i < NR_VMX_MSR; ++i)
6615                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6616
6617         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6618         if (!vmx_io_bitmap_a)
6619                 return -ENOMEM;
6620
6621         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6622         if (!vmx_io_bitmap_b) {
6623                 r = -ENOMEM;
6624                 goto out;
6625         }
6626
6627         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6628         if (!vmx_msr_bitmap_legacy) {
6629                 r = -ENOMEM;
6630                 goto out1;
6631         }
6632
6633         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6634         if (!vmx_msr_bitmap_longmode) {
6635                 r = -ENOMEM;
6636                 goto out2;
6637         }
6638
6639         /*
6640          * Allow direct access to the PC debug port (it is often used for I/O
6641          * delays, but the vmexits simply slow things down).
6642          */
6643         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6644         clear_bit(0x80, vmx_io_bitmap_a);
6645
6646         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6647
6648         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6649         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6650
6651         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6652
6653         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
6654                      __alignof__(struct vcpu_vmx), THIS_MODULE);
6655         if (r)
6656                 goto out3;
6657
6658         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6659         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6660         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6661         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6662         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6663         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6664
6665         if (enable_ept) {
6666                 bypass_guest_pf = 0;
6667                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
6668                                 VMX_EPT_EXECUTABLE_MASK);
6669                 kvm_enable_tdp();
6670         } else
6671                 kvm_disable_tdp();
6672
6673         if (bypass_guest_pf)
6674                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
6675
6676         return 0;
6677
6678 out3:
6679         free_page((unsigned long)vmx_msr_bitmap_longmode);
6680 out2:
6681         free_page((unsigned long)vmx_msr_bitmap_legacy);
6682 out1:
6683         free_page((unsigned long)vmx_io_bitmap_b);
6684 out:
6685         free_page((unsigned long)vmx_io_bitmap_a);
6686         return r;
6687 }
6688
6689 static void __exit vmx_exit(void)
6690 {
6691         free_page((unsigned long)vmx_msr_bitmap_legacy);
6692         free_page((unsigned long)vmx_msr_bitmap_longmode);
6693         free_page((unsigned long)vmx_io_bitmap_b);
6694         free_page((unsigned long)vmx_io_bitmap_a);
6695
6696         kvm_exit();
6697 }
6698
6699 module_init(vmx_init)
6700 module_exit(vmx_exit)