2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
62 static bool __read_mostly enable_vpid = 1;
63 module_param_named(vpid, enable_vpid, bool, 0444);
65 static bool __read_mostly flexpriority_enabled = 1;
66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
68 static bool __read_mostly enable_ept = 1;
69 module_param_named(ept, enable_ept, bool, S_IRUGO);
71 static bool __read_mostly enable_unrestricted_guest = 1;
72 module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
75 static bool __read_mostly enable_ept_ad_bits = 1;
76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
78 static bool __read_mostly emulate_invalid_guest_state = true;
79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
81 static bool __read_mostly vmm_exclusive = 1;
82 module_param(vmm_exclusive, bool, S_IRUGO);
84 static bool __read_mostly fasteoi = 1;
85 module_param(fasteoi, bool, S_IRUGO);
87 static bool __read_mostly enable_apicv_reg_vid;
90 * If nested=1, nested virtualization is supported, i.e., guests may use
91 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
92 * use VMX instructions.
94 static bool __read_mostly nested = 0;
95 module_param(nested, bool, S_IRUGO);
97 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
99 #define KVM_VM_CR0_ALWAYS_ON \
100 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
101 #define KVM_CR4_GUEST_OWNED_BITS \
102 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
103 | X86_CR4_OSXMMEXCPT)
105 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
106 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
111 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
112 * ple_gap: upper bound on the amount of time between two successive
113 * executions of PAUSE in a loop. Also indicate if ple enabled.
114 * According to test, this time is usually smaller than 128 cycles.
115 * ple_window: upper bound on the amount of time a guest is allowed to execute
116 * in a PAUSE loop. Tests indicate that most spinlocks are held for
117 * less than 2^12 cycles
118 * Time is measured based on a counter that runs at the same rate as the TSC,
119 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 #define KVM_VMX_DEFAULT_PLE_GAP 128
122 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
123 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
124 module_param(ple_gap, int, S_IRUGO);
126 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
127 module_param(ple_window, int, S_IRUGO);
129 extern const ulong vmx_return;
131 #define NR_AUTOLOAD_MSRS 8
132 #define VMCS02_POOL_SIZE 1
141 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
142 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
143 * loaded on this CPU (so we can clear them if the CPU goes down).
149 struct list_head loaded_vmcss_on_cpu_link;
152 struct shared_msr_entry {
159 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
160 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
161 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
162 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
163 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
164 * More than one of these structures may exist, if L1 runs multiple L2 guests.
165 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
166 * underlying hardware which will be used to run L2.
167 * This structure is packed to ensure that its layout is identical across
168 * machines (necessary for live migration).
169 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 typedef u64 natural_width;
172 struct __packed vmcs12 {
173 /* According to the Intel spec, a VMCS region must start with the
174 * following two fields. Then follow implementation-specific data.
179 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
180 u32 padding[7]; /* room for future expansion */
185 u64 vm_exit_msr_store_addr;
186 u64 vm_exit_msr_load_addr;
187 u64 vm_entry_msr_load_addr;
189 u64 virtual_apic_page_addr;
190 u64 apic_access_addr;
192 u64 guest_physical_address;
193 u64 vmcs_link_pointer;
194 u64 guest_ia32_debugctl;
197 u64 guest_ia32_perf_global_ctrl;
204 u64 host_ia32_perf_global_ctrl;
205 u64 padding64[8]; /* room for future expansion */
207 * To allow migration of L1 (complete with its L2 guests) between
208 * machines of different natural widths (32 or 64 bit), we cannot have
209 * unsigned long fields with no explict size. We use u64 (aliased
210 * natural_width) instead. Luckily, x86 is little-endian.
212 natural_width cr0_guest_host_mask;
213 natural_width cr4_guest_host_mask;
214 natural_width cr0_read_shadow;
215 natural_width cr4_read_shadow;
216 natural_width cr3_target_value0;
217 natural_width cr3_target_value1;
218 natural_width cr3_target_value2;
219 natural_width cr3_target_value3;
220 natural_width exit_qualification;
221 natural_width guest_linear_address;
222 natural_width guest_cr0;
223 natural_width guest_cr3;
224 natural_width guest_cr4;
225 natural_width guest_es_base;
226 natural_width guest_cs_base;
227 natural_width guest_ss_base;
228 natural_width guest_ds_base;
229 natural_width guest_fs_base;
230 natural_width guest_gs_base;
231 natural_width guest_ldtr_base;
232 natural_width guest_tr_base;
233 natural_width guest_gdtr_base;
234 natural_width guest_idtr_base;
235 natural_width guest_dr7;
236 natural_width guest_rsp;
237 natural_width guest_rip;
238 natural_width guest_rflags;
239 natural_width guest_pending_dbg_exceptions;
240 natural_width guest_sysenter_esp;
241 natural_width guest_sysenter_eip;
242 natural_width host_cr0;
243 natural_width host_cr3;
244 natural_width host_cr4;
245 natural_width host_fs_base;
246 natural_width host_gs_base;
247 natural_width host_tr_base;
248 natural_width host_gdtr_base;
249 natural_width host_idtr_base;
250 natural_width host_ia32_sysenter_esp;
251 natural_width host_ia32_sysenter_eip;
252 natural_width host_rsp;
253 natural_width host_rip;
254 natural_width paddingl[8]; /* room for future expansion */
255 u32 pin_based_vm_exec_control;
256 u32 cpu_based_vm_exec_control;
257 u32 exception_bitmap;
258 u32 page_fault_error_code_mask;
259 u32 page_fault_error_code_match;
260 u32 cr3_target_count;
261 u32 vm_exit_controls;
262 u32 vm_exit_msr_store_count;
263 u32 vm_exit_msr_load_count;
264 u32 vm_entry_controls;
265 u32 vm_entry_msr_load_count;
266 u32 vm_entry_intr_info_field;
267 u32 vm_entry_exception_error_code;
268 u32 vm_entry_instruction_len;
270 u32 secondary_vm_exec_control;
271 u32 vm_instruction_error;
273 u32 vm_exit_intr_info;
274 u32 vm_exit_intr_error_code;
275 u32 idt_vectoring_info_field;
276 u32 idt_vectoring_error_code;
277 u32 vm_exit_instruction_len;
278 u32 vmx_instruction_info;
285 u32 guest_ldtr_limit;
287 u32 guest_gdtr_limit;
288 u32 guest_idtr_limit;
289 u32 guest_es_ar_bytes;
290 u32 guest_cs_ar_bytes;
291 u32 guest_ss_ar_bytes;
292 u32 guest_ds_ar_bytes;
293 u32 guest_fs_ar_bytes;
294 u32 guest_gs_ar_bytes;
295 u32 guest_ldtr_ar_bytes;
296 u32 guest_tr_ar_bytes;
297 u32 guest_interruptibility_info;
298 u32 guest_activity_state;
299 u32 guest_sysenter_cs;
300 u32 host_ia32_sysenter_cs;
301 u32 padding32[8]; /* room for future expansion */
302 u16 virtual_processor_id;
303 u16 guest_es_selector;
304 u16 guest_cs_selector;
305 u16 guest_ss_selector;
306 u16 guest_ds_selector;
307 u16 guest_fs_selector;
308 u16 guest_gs_selector;
309 u16 guest_ldtr_selector;
310 u16 guest_tr_selector;
311 u16 host_es_selector;
312 u16 host_cs_selector;
313 u16 host_ss_selector;
314 u16 host_ds_selector;
315 u16 host_fs_selector;
316 u16 host_gs_selector;
317 u16 host_tr_selector;
321 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
322 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
323 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
325 #define VMCS12_REVISION 0x11e57ed0
328 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
329 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
330 * current implementation, 4K are reserved to avoid future complications.
332 #define VMCS12_SIZE 0x1000
334 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
336 struct list_head list;
338 struct loaded_vmcs vmcs02;
342 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
343 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
346 /* Has the level1 guest done vmxon? */
349 /* The guest-physical address of the current VMCS L1 keeps for L2 */
351 /* The host-usable pointer to the above */
352 struct page *current_vmcs12_page;
353 struct vmcs12 *current_vmcs12;
355 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
356 struct list_head vmcs02_pool;
358 u64 vmcs01_tsc_offset;
359 /* L2 must run next, and mustn't decide to exit to L1. */
360 bool nested_run_pending;
362 * Guest pages referred to in vmcs02 with host-physical pointers, so
363 * we must keep them pinned while L2 runs.
365 struct page *apic_access_page;
369 struct kvm_vcpu vcpu;
370 unsigned long host_rsp;
373 bool nmi_known_unmasked;
375 u32 idt_vectoring_info;
377 struct shared_msr_entry *guest_msrs;
381 u64 msr_host_kernel_gs_base;
382 u64 msr_guest_kernel_gs_base;
385 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
386 * non-nested (L1) guest, it always points to vmcs01. For a nested
387 * guest (L2), it points to a different VMCS.
389 struct loaded_vmcs vmcs01;
390 struct loaded_vmcs *loaded_vmcs;
391 bool __launched; /* temporary, used in vmx_vcpu_run */
392 struct msr_autoload {
394 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
395 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
399 u16 fs_sel, gs_sel, ldt_sel;
403 int gs_ldt_reload_needed;
404 int fs_reload_needed;
409 struct kvm_segment segs[8];
412 u32 bitmask; /* 4 bits per segment (1 bit per field) */
413 struct kvm_save_segment {
421 bool emulation_required;
423 /* Support for vnmi-less CPUs */
424 int soft_vnmi_blocked;
426 s64 vnmi_blocked_time;
431 /* Support for a guest hypervisor (nested VMX) */
432 struct nested_vmx nested;
435 enum segment_cache_field {
444 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
446 return container_of(vcpu, struct vcpu_vmx, vcpu);
449 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
450 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
451 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
452 [number##_HIGH] = VMCS12_OFFSET(name)+4
454 static const unsigned short vmcs_field_to_offset_table[] = {
455 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
456 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
457 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
458 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
459 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
460 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
461 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
462 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
463 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
464 FIELD(HOST_ES_SELECTOR, host_es_selector),
465 FIELD(HOST_CS_SELECTOR, host_cs_selector),
466 FIELD(HOST_SS_SELECTOR, host_ss_selector),
467 FIELD(HOST_DS_SELECTOR, host_ds_selector),
468 FIELD(HOST_FS_SELECTOR, host_fs_selector),
469 FIELD(HOST_GS_SELECTOR, host_gs_selector),
470 FIELD(HOST_TR_SELECTOR, host_tr_selector),
471 FIELD64(IO_BITMAP_A, io_bitmap_a),
472 FIELD64(IO_BITMAP_B, io_bitmap_b),
473 FIELD64(MSR_BITMAP, msr_bitmap),
474 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
475 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
476 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
477 FIELD64(TSC_OFFSET, tsc_offset),
478 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
479 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
480 FIELD64(EPT_POINTER, ept_pointer),
481 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
482 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
483 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
484 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
485 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
486 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
487 FIELD64(GUEST_PDPTR0, guest_pdptr0),
488 FIELD64(GUEST_PDPTR1, guest_pdptr1),
489 FIELD64(GUEST_PDPTR2, guest_pdptr2),
490 FIELD64(GUEST_PDPTR3, guest_pdptr3),
491 FIELD64(HOST_IA32_PAT, host_ia32_pat),
492 FIELD64(HOST_IA32_EFER, host_ia32_efer),
493 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
494 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
495 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
496 FIELD(EXCEPTION_BITMAP, exception_bitmap),
497 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
498 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
499 FIELD(CR3_TARGET_COUNT, cr3_target_count),
500 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
501 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
502 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
503 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
504 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
505 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
506 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
507 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
508 FIELD(TPR_THRESHOLD, tpr_threshold),
509 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
510 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
511 FIELD(VM_EXIT_REASON, vm_exit_reason),
512 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
513 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
514 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
515 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
516 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
517 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
518 FIELD(GUEST_ES_LIMIT, guest_es_limit),
519 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
520 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
521 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
522 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
523 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
524 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
525 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
526 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
527 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
528 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
529 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
530 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
531 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
532 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
533 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
534 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
535 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
536 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
537 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
538 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
539 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
540 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
541 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
542 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
543 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
544 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
545 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
546 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
547 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
548 FIELD(EXIT_QUALIFICATION, exit_qualification),
549 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
550 FIELD(GUEST_CR0, guest_cr0),
551 FIELD(GUEST_CR3, guest_cr3),
552 FIELD(GUEST_CR4, guest_cr4),
553 FIELD(GUEST_ES_BASE, guest_es_base),
554 FIELD(GUEST_CS_BASE, guest_cs_base),
555 FIELD(GUEST_SS_BASE, guest_ss_base),
556 FIELD(GUEST_DS_BASE, guest_ds_base),
557 FIELD(GUEST_FS_BASE, guest_fs_base),
558 FIELD(GUEST_GS_BASE, guest_gs_base),
559 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
560 FIELD(GUEST_TR_BASE, guest_tr_base),
561 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
562 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
563 FIELD(GUEST_DR7, guest_dr7),
564 FIELD(GUEST_RSP, guest_rsp),
565 FIELD(GUEST_RIP, guest_rip),
566 FIELD(GUEST_RFLAGS, guest_rflags),
567 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
568 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
569 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
570 FIELD(HOST_CR0, host_cr0),
571 FIELD(HOST_CR3, host_cr3),
572 FIELD(HOST_CR4, host_cr4),
573 FIELD(HOST_FS_BASE, host_fs_base),
574 FIELD(HOST_GS_BASE, host_gs_base),
575 FIELD(HOST_TR_BASE, host_tr_base),
576 FIELD(HOST_GDTR_BASE, host_gdtr_base),
577 FIELD(HOST_IDTR_BASE, host_idtr_base),
578 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
579 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
580 FIELD(HOST_RSP, host_rsp),
581 FIELD(HOST_RIP, host_rip),
583 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
585 static inline short vmcs_field_to_offset(unsigned long field)
587 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
589 return vmcs_field_to_offset_table[field];
592 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
594 return to_vmx(vcpu)->nested.current_vmcs12;
597 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
599 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
600 if (is_error_page(page))
606 static void nested_release_page(struct page *page)
608 kvm_release_page_dirty(page);
611 static void nested_release_page_clean(struct page *page)
613 kvm_release_page_clean(page);
616 static u64 construct_eptp(unsigned long root_hpa);
617 static void kvm_cpu_vmxon(u64 addr);
618 static void kvm_cpu_vmxoff(void);
619 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
620 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
621 static void vmx_set_segment(struct kvm_vcpu *vcpu,
622 struct kvm_segment *var, int seg);
623 static void vmx_get_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
625 static bool guest_state_valid(struct kvm_vcpu *vcpu);
626 static u32 vmx_segment_access_rights(struct kvm_segment *var);
628 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
629 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
631 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
632 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
634 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
635 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
637 static unsigned long *vmx_io_bitmap_a;
638 static unsigned long *vmx_io_bitmap_b;
639 static unsigned long *vmx_msr_bitmap_legacy;
640 static unsigned long *vmx_msr_bitmap_longmode;
641 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
642 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
644 static bool cpu_has_load_ia32_efer;
645 static bool cpu_has_load_perf_global_ctrl;
647 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
648 static DEFINE_SPINLOCK(vmx_vpid_lock);
650 static struct vmcs_config {
654 u32 pin_based_exec_ctrl;
655 u32 cpu_based_exec_ctrl;
656 u32 cpu_based_2nd_exec_ctrl;
661 static struct vmx_capability {
666 #define VMX_SEGMENT_FIELD(seg) \
667 [VCPU_SREG_##seg] = { \
668 .selector = GUEST_##seg##_SELECTOR, \
669 .base = GUEST_##seg##_BASE, \
670 .limit = GUEST_##seg##_LIMIT, \
671 .ar_bytes = GUEST_##seg##_AR_BYTES, \
674 static const struct kvm_vmx_segment_field {
679 } kvm_vmx_segment_fields[] = {
680 VMX_SEGMENT_FIELD(CS),
681 VMX_SEGMENT_FIELD(DS),
682 VMX_SEGMENT_FIELD(ES),
683 VMX_SEGMENT_FIELD(FS),
684 VMX_SEGMENT_FIELD(GS),
685 VMX_SEGMENT_FIELD(SS),
686 VMX_SEGMENT_FIELD(TR),
687 VMX_SEGMENT_FIELD(LDTR),
690 static u64 host_efer;
692 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
695 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
696 * away by decrementing the array size.
698 static const u32 vmx_msr_index[] = {
700 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
702 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
704 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
706 static inline bool is_page_fault(u32 intr_info)
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
709 INTR_INFO_VALID_MASK)) ==
710 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
713 static inline bool is_no_device(u32 intr_info)
715 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
716 INTR_INFO_VALID_MASK)) ==
717 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
720 static inline bool is_invalid_opcode(u32 intr_info)
722 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
723 INTR_INFO_VALID_MASK)) ==
724 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
727 static inline bool is_external_interrupt(u32 intr_info)
729 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
730 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
733 static inline bool is_machine_check(u32 intr_info)
735 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
736 INTR_INFO_VALID_MASK)) ==
737 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
740 static inline bool cpu_has_vmx_msr_bitmap(void)
742 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
745 static inline bool cpu_has_vmx_tpr_shadow(void)
747 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
750 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
752 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
755 static inline bool cpu_has_secondary_exec_ctrls(void)
757 return vmcs_config.cpu_based_exec_ctrl &
758 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
761 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
763 return vmcs_config.cpu_based_2nd_exec_ctrl &
764 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
767 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
769 return vmcs_config.cpu_based_2nd_exec_ctrl &
770 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
773 static inline bool cpu_has_vmx_apic_register_virt(void)
775 return vmcs_config.cpu_based_2nd_exec_ctrl &
776 SECONDARY_EXEC_APIC_REGISTER_VIRT;
779 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
781 return vmcs_config.cpu_based_2nd_exec_ctrl &
782 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
785 static inline bool cpu_has_vmx_flexpriority(void)
787 return cpu_has_vmx_tpr_shadow() &&
788 cpu_has_vmx_virtualize_apic_accesses();
791 static inline bool cpu_has_vmx_ept_execute_only(void)
793 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
796 static inline bool cpu_has_vmx_eptp_uncacheable(void)
798 return vmx_capability.ept & VMX_EPTP_UC_BIT;
801 static inline bool cpu_has_vmx_eptp_writeback(void)
803 return vmx_capability.ept & VMX_EPTP_WB_BIT;
806 static inline bool cpu_has_vmx_ept_2m_page(void)
808 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
811 static inline bool cpu_has_vmx_ept_1g_page(void)
813 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
816 static inline bool cpu_has_vmx_ept_4levels(void)
818 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
821 static inline bool cpu_has_vmx_ept_ad_bits(void)
823 return vmx_capability.ept & VMX_EPT_AD_BIT;
826 static inline bool cpu_has_vmx_invept_context(void)
828 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
831 static inline bool cpu_has_vmx_invept_global(void)
833 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
836 static inline bool cpu_has_vmx_invvpid_single(void)
838 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
841 static inline bool cpu_has_vmx_invvpid_global(void)
843 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
846 static inline bool cpu_has_vmx_ept(void)
848 return vmcs_config.cpu_based_2nd_exec_ctrl &
849 SECONDARY_EXEC_ENABLE_EPT;
852 static inline bool cpu_has_vmx_unrestricted_guest(void)
854 return vmcs_config.cpu_based_2nd_exec_ctrl &
855 SECONDARY_EXEC_UNRESTRICTED_GUEST;
858 static inline bool cpu_has_vmx_ple(void)
860 return vmcs_config.cpu_based_2nd_exec_ctrl &
861 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
864 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
866 return flexpriority_enabled && irqchip_in_kernel(kvm);
869 static inline bool cpu_has_vmx_vpid(void)
871 return vmcs_config.cpu_based_2nd_exec_ctrl &
872 SECONDARY_EXEC_ENABLE_VPID;
875 static inline bool cpu_has_vmx_rdtscp(void)
877 return vmcs_config.cpu_based_2nd_exec_ctrl &
878 SECONDARY_EXEC_RDTSCP;
881 static inline bool cpu_has_vmx_invpcid(void)
883 return vmcs_config.cpu_based_2nd_exec_ctrl &
884 SECONDARY_EXEC_ENABLE_INVPCID;
887 static inline bool cpu_has_virtual_nmis(void)
889 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
892 static inline bool cpu_has_vmx_wbinvd_exit(void)
894 return vmcs_config.cpu_based_2nd_exec_ctrl &
895 SECONDARY_EXEC_WBINVD_EXITING;
898 static inline bool report_flexpriority(void)
900 return flexpriority_enabled;
903 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
905 return vmcs12->cpu_based_vm_exec_control & bit;
908 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
910 return (vmcs12->cpu_based_vm_exec_control &
911 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
912 (vmcs12->secondary_vm_exec_control & bit);
915 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
916 struct kvm_vcpu *vcpu)
918 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
921 static inline bool is_exception(u32 intr_info)
923 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
924 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
927 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
928 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
929 struct vmcs12 *vmcs12,
930 u32 reason, unsigned long qualification);
932 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
936 for (i = 0; i < vmx->nmsrs; ++i)
937 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
942 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
948 } operand = { vpid, 0, gva };
950 asm volatile (__ex(ASM_VMX_INVVPID)
951 /* CF==1 or ZF==1 --> rc = -1 */
953 : : "a"(&operand), "c"(ext) : "cc", "memory");
956 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
960 } operand = {eptp, gpa};
962 asm volatile (__ex(ASM_VMX_INVEPT)
963 /* CF==1 or ZF==1 --> rc = -1 */
964 "; ja 1f ; ud2 ; 1:\n"
965 : : "a" (&operand), "c" (ext) : "cc", "memory");
968 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
972 i = __find_msr_index(vmx, msr);
974 return &vmx->guest_msrs[i];
978 static void vmcs_clear(struct vmcs *vmcs)
980 u64 phys_addr = __pa(vmcs);
983 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
984 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
987 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
991 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
993 vmcs_clear(loaded_vmcs->vmcs);
994 loaded_vmcs->cpu = -1;
995 loaded_vmcs->launched = 0;
998 static void vmcs_load(struct vmcs *vmcs)
1000 u64 phys_addr = __pa(vmcs);
1003 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1004 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1007 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1013 * This bitmap is used to indicate whether the vmclear
1014 * operation is enabled on all cpus. All disabled by
1017 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1019 static inline void crash_enable_local_vmclear(int cpu)
1021 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1024 static inline void crash_disable_local_vmclear(int cpu)
1026 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1029 static inline int crash_local_vmclear_enabled(int cpu)
1031 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1034 static void crash_vmclear_local_loaded_vmcss(void)
1036 int cpu = raw_smp_processor_id();
1037 struct loaded_vmcs *v;
1039 if (!crash_local_vmclear_enabled(cpu))
1042 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1043 loaded_vmcss_on_cpu_link)
1044 vmcs_clear(v->vmcs);
1047 static inline void crash_enable_local_vmclear(int cpu) { }
1048 static inline void crash_disable_local_vmclear(int cpu) { }
1049 #endif /* CONFIG_KEXEC */
1051 static void __loaded_vmcs_clear(void *arg)
1053 struct loaded_vmcs *loaded_vmcs = arg;
1054 int cpu = raw_smp_processor_id();
1056 if (loaded_vmcs->cpu != cpu)
1057 return; /* vcpu migration can race with cpu offline */
1058 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1059 per_cpu(current_vmcs, cpu) = NULL;
1060 crash_disable_local_vmclear(cpu);
1061 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1064 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1065 * is before setting loaded_vmcs->vcpu to -1 which is done in
1066 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1067 * then adds the vmcs into percpu list before it is deleted.
1071 loaded_vmcs_init(loaded_vmcs);
1072 crash_enable_local_vmclear(cpu);
1075 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1077 int cpu = loaded_vmcs->cpu;
1080 smp_call_function_single(cpu,
1081 __loaded_vmcs_clear, loaded_vmcs, 1);
1084 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1089 if (cpu_has_vmx_invvpid_single())
1090 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1093 static inline void vpid_sync_vcpu_global(void)
1095 if (cpu_has_vmx_invvpid_global())
1096 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1099 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1101 if (cpu_has_vmx_invvpid_single())
1102 vpid_sync_vcpu_single(vmx);
1104 vpid_sync_vcpu_global();
1107 static inline void ept_sync_global(void)
1109 if (cpu_has_vmx_invept_global())
1110 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1113 static inline void ept_sync_context(u64 eptp)
1116 if (cpu_has_vmx_invept_context())
1117 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1123 static __always_inline unsigned long vmcs_readl(unsigned long field)
1125 unsigned long value;
1127 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1128 : "=a"(value) : "d"(field) : "cc");
1132 static __always_inline u16 vmcs_read16(unsigned long field)
1134 return vmcs_readl(field);
1137 static __always_inline u32 vmcs_read32(unsigned long field)
1139 return vmcs_readl(field);
1142 static __always_inline u64 vmcs_read64(unsigned long field)
1144 #ifdef CONFIG_X86_64
1145 return vmcs_readl(field);
1147 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1151 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1153 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1154 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1158 static void vmcs_writel(unsigned long field, unsigned long value)
1162 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1163 : "=q"(error) : "a"(value), "d"(field) : "cc");
1164 if (unlikely(error))
1165 vmwrite_error(field, value);
1168 static void vmcs_write16(unsigned long field, u16 value)
1170 vmcs_writel(field, value);
1173 static void vmcs_write32(unsigned long field, u32 value)
1175 vmcs_writel(field, value);
1178 static void vmcs_write64(unsigned long field, u64 value)
1180 vmcs_writel(field, value);
1181 #ifndef CONFIG_X86_64
1183 vmcs_writel(field+1, value >> 32);
1187 static void vmcs_clear_bits(unsigned long field, u32 mask)
1189 vmcs_writel(field, vmcs_readl(field) & ~mask);
1192 static void vmcs_set_bits(unsigned long field, u32 mask)
1194 vmcs_writel(field, vmcs_readl(field) | mask);
1197 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1199 vmx->segment_cache.bitmask = 0;
1202 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1206 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1208 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1209 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1210 vmx->segment_cache.bitmask = 0;
1212 ret = vmx->segment_cache.bitmask & mask;
1213 vmx->segment_cache.bitmask |= mask;
1217 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1219 u16 *p = &vmx->segment_cache.seg[seg].selector;
1221 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1222 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1226 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1228 ulong *p = &vmx->segment_cache.seg[seg].base;
1230 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1231 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1235 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1237 u32 *p = &vmx->segment_cache.seg[seg].limit;
1239 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1240 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1244 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1246 u32 *p = &vmx->segment_cache.seg[seg].ar;
1248 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1249 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1253 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1257 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1258 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1259 if ((vcpu->guest_debug &
1260 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1261 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1262 eb |= 1u << BP_VECTOR;
1263 if (to_vmx(vcpu)->rmode.vm86_active)
1266 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1267 if (vcpu->fpu_active)
1268 eb &= ~(1u << NM_VECTOR);
1270 /* When we are running a nested L2 guest and L1 specified for it a
1271 * certain exception bitmap, we must trap the same exceptions and pass
1272 * them to L1. When running L2, we will only handle the exceptions
1273 * specified above if L1 did not want them.
1275 if (is_guest_mode(vcpu))
1276 eb |= get_vmcs12(vcpu)->exception_bitmap;
1278 vmcs_write32(EXCEPTION_BITMAP, eb);
1281 static void clear_atomic_switch_msr_special(unsigned long entry,
1284 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1285 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1288 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1291 struct msr_autoload *m = &vmx->msr_autoload;
1295 if (cpu_has_load_ia32_efer) {
1296 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1297 VM_EXIT_LOAD_IA32_EFER);
1301 case MSR_CORE_PERF_GLOBAL_CTRL:
1302 if (cpu_has_load_perf_global_ctrl) {
1303 clear_atomic_switch_msr_special(
1304 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1305 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1311 for (i = 0; i < m->nr; ++i)
1312 if (m->guest[i].index == msr)
1318 m->guest[i] = m->guest[m->nr];
1319 m->host[i] = m->host[m->nr];
1320 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1321 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1324 static void add_atomic_switch_msr_special(unsigned long entry,
1325 unsigned long exit, unsigned long guest_val_vmcs,
1326 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1328 vmcs_write64(guest_val_vmcs, guest_val);
1329 vmcs_write64(host_val_vmcs, host_val);
1330 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1331 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1334 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1335 u64 guest_val, u64 host_val)
1338 struct msr_autoload *m = &vmx->msr_autoload;
1342 if (cpu_has_load_ia32_efer) {
1343 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1344 VM_EXIT_LOAD_IA32_EFER,
1347 guest_val, host_val);
1351 case MSR_CORE_PERF_GLOBAL_CTRL:
1352 if (cpu_has_load_perf_global_ctrl) {
1353 add_atomic_switch_msr_special(
1354 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1355 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1356 GUEST_IA32_PERF_GLOBAL_CTRL,
1357 HOST_IA32_PERF_GLOBAL_CTRL,
1358 guest_val, host_val);
1364 for (i = 0; i < m->nr; ++i)
1365 if (m->guest[i].index == msr)
1368 if (i == NR_AUTOLOAD_MSRS) {
1369 printk_once(KERN_WARNING"Not enough mst switch entries. "
1370 "Can't add msr %x\n", msr);
1372 } else if (i == m->nr) {
1374 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1375 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1378 m->guest[i].index = msr;
1379 m->guest[i].value = guest_val;
1380 m->host[i].index = msr;
1381 m->host[i].value = host_val;
1384 static void reload_tss(void)
1387 * VT restores TR but not its size. Useless.
1389 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1390 struct desc_struct *descs;
1392 descs = (void *)gdt->address;
1393 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1397 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1402 guest_efer = vmx->vcpu.arch.efer;
1405 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1408 ignore_bits = EFER_NX | EFER_SCE;
1409 #ifdef CONFIG_X86_64
1410 ignore_bits |= EFER_LMA | EFER_LME;
1411 /* SCE is meaningful only in long mode on Intel */
1412 if (guest_efer & EFER_LMA)
1413 ignore_bits &= ~(u64)EFER_SCE;
1415 guest_efer &= ~ignore_bits;
1416 guest_efer |= host_efer & ignore_bits;
1417 vmx->guest_msrs[efer_offset].data = guest_efer;
1418 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1420 clear_atomic_switch_msr(vmx, MSR_EFER);
1421 /* On ept, can't emulate nx, and must switch nx atomically */
1422 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1423 guest_efer = vmx->vcpu.arch.efer;
1424 if (!(guest_efer & EFER_LMA))
1425 guest_efer &= ~EFER_LME;
1426 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1433 static unsigned long segment_base(u16 selector)
1435 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1436 struct desc_struct *d;
1437 unsigned long table_base;
1440 if (!(selector & ~3))
1443 table_base = gdt->address;
1445 if (selector & 4) { /* from ldt */
1446 u16 ldt_selector = kvm_read_ldt();
1448 if (!(ldt_selector & ~3))
1451 table_base = segment_base(ldt_selector);
1453 d = (struct desc_struct *)(table_base + (selector & ~7));
1454 v = get_desc_base(d);
1455 #ifdef CONFIG_X86_64
1456 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1457 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1462 static inline unsigned long kvm_read_tr_base(void)
1465 asm("str %0" : "=g"(tr));
1466 return segment_base(tr);
1469 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1471 struct vcpu_vmx *vmx = to_vmx(vcpu);
1474 if (vmx->host_state.loaded)
1477 vmx->host_state.loaded = 1;
1479 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1480 * allow segment selectors with cpl > 0 or ti == 1.
1482 vmx->host_state.ldt_sel = kvm_read_ldt();
1483 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1484 savesegment(fs, vmx->host_state.fs_sel);
1485 if (!(vmx->host_state.fs_sel & 7)) {
1486 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1487 vmx->host_state.fs_reload_needed = 0;
1489 vmcs_write16(HOST_FS_SELECTOR, 0);
1490 vmx->host_state.fs_reload_needed = 1;
1492 savesegment(gs, vmx->host_state.gs_sel);
1493 if (!(vmx->host_state.gs_sel & 7))
1494 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1496 vmcs_write16(HOST_GS_SELECTOR, 0);
1497 vmx->host_state.gs_ldt_reload_needed = 1;
1500 #ifdef CONFIG_X86_64
1501 savesegment(ds, vmx->host_state.ds_sel);
1502 savesegment(es, vmx->host_state.es_sel);
1505 #ifdef CONFIG_X86_64
1506 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1507 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1509 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1510 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1513 #ifdef CONFIG_X86_64
1514 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1515 if (is_long_mode(&vmx->vcpu))
1516 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1518 for (i = 0; i < vmx->save_nmsrs; ++i)
1519 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1520 vmx->guest_msrs[i].data,
1521 vmx->guest_msrs[i].mask);
1524 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1526 if (!vmx->host_state.loaded)
1529 ++vmx->vcpu.stat.host_state_reload;
1530 vmx->host_state.loaded = 0;
1531 #ifdef CONFIG_X86_64
1532 if (is_long_mode(&vmx->vcpu))
1533 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1535 if (vmx->host_state.gs_ldt_reload_needed) {
1536 kvm_load_ldt(vmx->host_state.ldt_sel);
1537 #ifdef CONFIG_X86_64
1538 load_gs_index(vmx->host_state.gs_sel);
1540 loadsegment(gs, vmx->host_state.gs_sel);
1543 if (vmx->host_state.fs_reload_needed)
1544 loadsegment(fs, vmx->host_state.fs_sel);
1545 #ifdef CONFIG_X86_64
1546 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1547 loadsegment(ds, vmx->host_state.ds_sel);
1548 loadsegment(es, vmx->host_state.es_sel);
1552 #ifdef CONFIG_X86_64
1553 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1556 * If the FPU is not active (through the host task or
1557 * the guest vcpu), then restore the cr0.TS bit.
1559 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1561 load_gdt(&__get_cpu_var(host_gdt));
1564 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1567 __vmx_load_host_state(vmx);
1572 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1573 * vcpu mutex is already taken.
1575 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1577 struct vcpu_vmx *vmx = to_vmx(vcpu);
1578 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1581 kvm_cpu_vmxon(phys_addr);
1582 else if (vmx->loaded_vmcs->cpu != cpu)
1583 loaded_vmcs_clear(vmx->loaded_vmcs);
1585 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1586 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1587 vmcs_load(vmx->loaded_vmcs->vmcs);
1590 if (vmx->loaded_vmcs->cpu != cpu) {
1591 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1592 unsigned long sysenter_esp;
1594 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1595 local_irq_disable();
1596 crash_disable_local_vmclear(cpu);
1599 * Read loaded_vmcs->cpu should be before fetching
1600 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1601 * See the comments in __loaded_vmcs_clear().
1605 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1606 &per_cpu(loaded_vmcss_on_cpu, cpu));
1607 crash_enable_local_vmclear(cpu);
1611 * Linux uses per-cpu TSS and GDT, so set these when switching
1614 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1615 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1617 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1618 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1619 vmx->loaded_vmcs->cpu = cpu;
1623 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1625 __vmx_load_host_state(to_vmx(vcpu));
1626 if (!vmm_exclusive) {
1627 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1633 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1637 if (vcpu->fpu_active)
1639 vcpu->fpu_active = 1;
1640 cr0 = vmcs_readl(GUEST_CR0);
1641 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1642 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1643 vmcs_writel(GUEST_CR0, cr0);
1644 update_exception_bitmap(vcpu);
1645 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1646 if (is_guest_mode(vcpu))
1647 vcpu->arch.cr0_guest_owned_bits &=
1648 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1649 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1652 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1655 * Return the cr0 value that a nested guest would read. This is a combination
1656 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1657 * its hypervisor (cr0_read_shadow).
1659 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1661 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1662 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1664 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1666 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1667 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1670 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1672 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1673 * set this *before* calling this function.
1675 vmx_decache_cr0_guest_bits(vcpu);
1676 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1677 update_exception_bitmap(vcpu);
1678 vcpu->arch.cr0_guest_owned_bits = 0;
1679 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1680 if (is_guest_mode(vcpu)) {
1682 * L1's specified read shadow might not contain the TS bit,
1683 * so now that we turned on shadowing of this bit, we need to
1684 * set this bit of the shadow. Like in nested_vmx_run we need
1685 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1686 * up-to-date here because we just decached cr0.TS (and we'll
1687 * only update vmcs12->guest_cr0 on nested exit).
1689 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1690 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1691 (vcpu->arch.cr0 & X86_CR0_TS);
1692 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1694 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1697 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1699 unsigned long rflags, save_rflags;
1701 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1702 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1703 rflags = vmcs_readl(GUEST_RFLAGS);
1704 if (to_vmx(vcpu)->rmode.vm86_active) {
1705 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1706 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1707 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1709 to_vmx(vcpu)->rflags = rflags;
1711 return to_vmx(vcpu)->rflags;
1714 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1716 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1717 to_vmx(vcpu)->rflags = rflags;
1718 if (to_vmx(vcpu)->rmode.vm86_active) {
1719 to_vmx(vcpu)->rmode.save_rflags = rflags;
1720 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1722 vmcs_writel(GUEST_RFLAGS, rflags);
1725 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1727 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1730 if (interruptibility & GUEST_INTR_STATE_STI)
1731 ret |= KVM_X86_SHADOW_INT_STI;
1732 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1733 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1738 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1740 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1741 u32 interruptibility = interruptibility_old;
1743 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1745 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1746 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1747 else if (mask & KVM_X86_SHADOW_INT_STI)
1748 interruptibility |= GUEST_INTR_STATE_STI;
1750 if ((interruptibility != interruptibility_old))
1751 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1754 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1758 rip = kvm_rip_read(vcpu);
1759 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1760 kvm_rip_write(vcpu, rip);
1762 /* skipping an emulated instruction also counts */
1763 vmx_set_interrupt_shadow(vcpu, 0);
1767 * KVM wants to inject page-faults which it got to the guest. This function
1768 * checks whether in a nested guest, we need to inject them to L1 or L2.
1769 * This function assumes it is called with the exit reason in vmcs02 being
1770 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1773 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1775 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1777 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1778 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1781 nested_vmx_vmexit(vcpu);
1785 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1786 bool has_error_code, u32 error_code,
1789 struct vcpu_vmx *vmx = to_vmx(vcpu);
1790 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1792 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1793 nested_pf_handled(vcpu))
1796 if (has_error_code) {
1797 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1798 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1801 if (vmx->rmode.vm86_active) {
1803 if (kvm_exception_is_soft(nr))
1804 inc_eip = vcpu->arch.event_exit_inst_len;
1805 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1806 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1810 if (kvm_exception_is_soft(nr)) {
1811 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1812 vmx->vcpu.arch.event_exit_inst_len);
1813 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1815 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1817 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1820 static bool vmx_rdtscp_supported(void)
1822 return cpu_has_vmx_rdtscp();
1825 static bool vmx_invpcid_supported(void)
1827 return cpu_has_vmx_invpcid() && enable_ept;
1831 * Swap MSR entry in host/guest MSR entry array.
1833 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1835 struct shared_msr_entry tmp;
1837 tmp = vmx->guest_msrs[to];
1838 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1839 vmx->guest_msrs[from] = tmp;
1842 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1844 unsigned long *msr_bitmap;
1846 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1847 if (is_long_mode(vcpu))
1848 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1850 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1852 if (is_long_mode(vcpu))
1853 msr_bitmap = vmx_msr_bitmap_longmode;
1855 msr_bitmap = vmx_msr_bitmap_legacy;
1858 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1862 * Set up the vmcs to automatically save and restore system
1863 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1864 * mode, as fiddling with msrs is very expensive.
1866 static void setup_msrs(struct vcpu_vmx *vmx)
1868 int save_nmsrs, index;
1871 #ifdef CONFIG_X86_64
1872 if (is_long_mode(&vmx->vcpu)) {
1873 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1875 move_msr_up(vmx, index, save_nmsrs++);
1876 index = __find_msr_index(vmx, MSR_LSTAR);
1878 move_msr_up(vmx, index, save_nmsrs++);
1879 index = __find_msr_index(vmx, MSR_CSTAR);
1881 move_msr_up(vmx, index, save_nmsrs++);
1882 index = __find_msr_index(vmx, MSR_TSC_AUX);
1883 if (index >= 0 && vmx->rdtscp_enabled)
1884 move_msr_up(vmx, index, save_nmsrs++);
1886 * MSR_STAR is only needed on long mode guests, and only
1887 * if efer.sce is enabled.
1889 index = __find_msr_index(vmx, MSR_STAR);
1890 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1891 move_msr_up(vmx, index, save_nmsrs++);
1894 index = __find_msr_index(vmx, MSR_EFER);
1895 if (index >= 0 && update_transition_efer(vmx, index))
1896 move_msr_up(vmx, index, save_nmsrs++);
1898 vmx->save_nmsrs = save_nmsrs;
1900 if (cpu_has_vmx_msr_bitmap())
1901 vmx_set_msr_bitmap(&vmx->vcpu);
1905 * reads and returns guest's timestamp counter "register"
1906 * guest_tsc = host_tsc + tsc_offset -- 21.3
1908 static u64 guest_read_tsc(void)
1910 u64 host_tsc, tsc_offset;
1913 tsc_offset = vmcs_read64(TSC_OFFSET);
1914 return host_tsc + tsc_offset;
1918 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1919 * counter, even if a nested guest (L2) is currently running.
1921 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1925 tsc_offset = is_guest_mode(vcpu) ?
1926 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1927 vmcs_read64(TSC_OFFSET);
1928 return host_tsc + tsc_offset;
1932 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1933 * software catchup for faster rates on slower CPUs.
1935 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1940 if (user_tsc_khz > tsc_khz) {
1941 vcpu->arch.tsc_catchup = 1;
1942 vcpu->arch.tsc_always_catchup = 1;
1944 WARN(1, "user requested TSC rate below hardware speed\n");
1947 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1949 return vmcs_read64(TSC_OFFSET);
1953 * writes 'offset' into guest's timestamp counter offset register
1955 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1957 if (is_guest_mode(vcpu)) {
1959 * We're here if L1 chose not to trap WRMSR to TSC. According
1960 * to the spec, this should set L1's TSC; The offset that L1
1961 * set for L2 remains unchanged, and still needs to be added
1962 * to the newly set TSC to get L2's TSC.
1964 struct vmcs12 *vmcs12;
1965 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1966 /* recalculate vmcs02.TSC_OFFSET: */
1967 vmcs12 = get_vmcs12(vcpu);
1968 vmcs_write64(TSC_OFFSET, offset +
1969 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1970 vmcs12->tsc_offset : 0));
1972 vmcs_write64(TSC_OFFSET, offset);
1976 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1978 u64 offset = vmcs_read64(TSC_OFFSET);
1979 vmcs_write64(TSC_OFFSET, offset + adjustment);
1980 if (is_guest_mode(vcpu)) {
1981 /* Even when running L2, the adjustment needs to apply to L1 */
1982 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1986 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1988 return target_tsc - native_read_tsc();
1991 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1993 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1994 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1998 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1999 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2000 * all guests if the "nested" module option is off, and can also be disabled
2001 * for a single guest by disabling its VMX cpuid bit.
2003 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2005 return nested && guest_cpuid_has_vmx(vcpu);
2009 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2010 * returned for the various VMX controls MSRs when nested VMX is enabled.
2011 * The same values should also be used to verify that vmcs12 control fields are
2012 * valid during nested entry from L1 to L2.
2013 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2014 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2015 * bit in the high half is on if the corresponding bit in the control field
2016 * may be on. See also vmx_control_verify().
2017 * TODO: allow these variables to be modified (downgraded) by module options
2020 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2021 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2022 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2023 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2024 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2025 static __init void nested_vmx_setup_ctls_msrs(void)
2028 * Note that as a general rule, the high half of the MSRs (bits in
2029 * the control fields which may be 1) should be initialized by the
2030 * intersection of the underlying hardware's MSR (i.e., features which
2031 * can be supported) and the list of features we want to expose -
2032 * because they are known to be properly supported in our code.
2033 * Also, usually, the low half of the MSRs (bits which must be 1) can
2034 * be set to 0, meaning that L1 may turn off any of these bits. The
2035 * reason is that if one of these bits is necessary, it will appear
2036 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2037 * fields of vmcs01 and vmcs02, will turn these bits off - and
2038 * nested_vmx_exit_handled() will not pass related exits to L1.
2039 * These rules have exceptions below.
2042 /* pin-based controls */
2044 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2045 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2047 nested_vmx_pinbased_ctls_low = 0x16 ;
2048 nested_vmx_pinbased_ctls_high = 0x16 |
2049 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2050 PIN_BASED_VIRTUAL_NMIS;
2054 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2057 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2058 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2059 #ifdef CONFIG_X86_64
2060 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2062 nested_vmx_exit_ctls_high = 0;
2064 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2066 /* entry controls */
2067 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2068 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2069 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2070 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2071 nested_vmx_entry_ctls_high &=
2072 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2073 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2075 /* cpu-based controls */
2076 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2077 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2078 nested_vmx_procbased_ctls_low = 0;
2079 nested_vmx_procbased_ctls_high &=
2080 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2081 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2082 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2083 CPU_BASED_CR3_STORE_EXITING |
2084 #ifdef CONFIG_X86_64
2085 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2087 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2088 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2089 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2090 CPU_BASED_PAUSE_EXITING |
2091 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2093 * We can allow some features even when not supported by the
2094 * hardware. For example, L1 can specify an MSR bitmap - and we
2095 * can use it to avoid exits to L1 - even when L0 runs L2
2096 * without MSR bitmaps.
2098 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2100 /* secondary cpu-based controls */
2101 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2102 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2103 nested_vmx_secondary_ctls_low = 0;
2104 nested_vmx_secondary_ctls_high &=
2105 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2106 SECONDARY_EXEC_WBINVD_EXITING;
2109 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2112 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2114 return ((control & high) | low) == control;
2117 static inline u64 vmx_control_msr(u32 low, u32 high)
2119 return low | ((u64)high << 32);
2123 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2124 * also let it use VMX-specific MSRs.
2125 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2126 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2127 * like all other MSRs).
2129 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2131 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2132 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2134 * According to the spec, processors which do not support VMX
2135 * should throw a #GP(0) when VMX capability MSRs are read.
2137 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2141 switch (msr_index) {
2142 case MSR_IA32_FEATURE_CONTROL:
2145 case MSR_IA32_VMX_BASIC:
2147 * This MSR reports some information about VMX support. We
2148 * should return information about the VMX we emulate for the
2149 * guest, and the VMCS structure we give it - not about the
2150 * VMX support of the underlying hardware.
2152 *pdata = VMCS12_REVISION |
2153 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2154 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2156 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2157 case MSR_IA32_VMX_PINBASED_CTLS:
2158 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2159 nested_vmx_pinbased_ctls_high);
2161 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2162 case MSR_IA32_VMX_PROCBASED_CTLS:
2163 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2164 nested_vmx_procbased_ctls_high);
2166 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2167 case MSR_IA32_VMX_EXIT_CTLS:
2168 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2169 nested_vmx_exit_ctls_high);
2171 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2172 case MSR_IA32_VMX_ENTRY_CTLS:
2173 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2174 nested_vmx_entry_ctls_high);
2176 case MSR_IA32_VMX_MISC:
2180 * These MSRs specify bits which the guest must keep fixed (on or off)
2181 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2182 * We picked the standard core2 setting.
2184 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2185 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2186 case MSR_IA32_VMX_CR0_FIXED0:
2187 *pdata = VMXON_CR0_ALWAYSON;
2189 case MSR_IA32_VMX_CR0_FIXED1:
2192 case MSR_IA32_VMX_CR4_FIXED0:
2193 *pdata = VMXON_CR4_ALWAYSON;
2195 case MSR_IA32_VMX_CR4_FIXED1:
2198 case MSR_IA32_VMX_VMCS_ENUM:
2201 case MSR_IA32_VMX_PROCBASED_CTLS2:
2202 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2203 nested_vmx_secondary_ctls_high);
2205 case MSR_IA32_VMX_EPT_VPID_CAP:
2206 /* Currently, no nested ept or nested vpid */
2216 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2218 if (!nested_vmx_allowed(vcpu))
2221 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2222 /* TODO: the right thing. */
2225 * No need to treat VMX capability MSRs specially: If we don't handle
2226 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2232 * Reads an msr value (of 'msr_index') into 'pdata'.
2233 * Returns 0 on success, non-0 otherwise.
2234 * Assumes vcpu_load() was already called.
2236 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2239 struct shared_msr_entry *msr;
2242 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2246 switch (msr_index) {
2247 #ifdef CONFIG_X86_64
2249 data = vmcs_readl(GUEST_FS_BASE);
2252 data = vmcs_readl(GUEST_GS_BASE);
2254 case MSR_KERNEL_GS_BASE:
2255 vmx_load_host_state(to_vmx(vcpu));
2256 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2260 return kvm_get_msr_common(vcpu, msr_index, pdata);
2262 data = guest_read_tsc();
2264 case MSR_IA32_SYSENTER_CS:
2265 data = vmcs_read32(GUEST_SYSENTER_CS);
2267 case MSR_IA32_SYSENTER_EIP:
2268 data = vmcs_readl(GUEST_SYSENTER_EIP);
2270 case MSR_IA32_SYSENTER_ESP:
2271 data = vmcs_readl(GUEST_SYSENTER_ESP);
2274 if (!to_vmx(vcpu)->rdtscp_enabled)
2276 /* Otherwise falls through */
2278 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2280 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2285 return kvm_get_msr_common(vcpu, msr_index, pdata);
2293 * Writes msr value into into the appropriate "register".
2294 * Returns 0 on success, non-0 otherwise.
2295 * Assumes vcpu_load() was already called.
2297 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2299 struct vcpu_vmx *vmx = to_vmx(vcpu);
2300 struct shared_msr_entry *msr;
2302 u32 msr_index = msr_info->index;
2303 u64 data = msr_info->data;
2305 switch (msr_index) {
2307 ret = kvm_set_msr_common(vcpu, msr_info);
2309 #ifdef CONFIG_X86_64
2311 vmx_segment_cache_clear(vmx);
2312 vmcs_writel(GUEST_FS_BASE, data);
2315 vmx_segment_cache_clear(vmx);
2316 vmcs_writel(GUEST_GS_BASE, data);
2318 case MSR_KERNEL_GS_BASE:
2319 vmx_load_host_state(vmx);
2320 vmx->msr_guest_kernel_gs_base = data;
2323 case MSR_IA32_SYSENTER_CS:
2324 vmcs_write32(GUEST_SYSENTER_CS, data);
2326 case MSR_IA32_SYSENTER_EIP:
2327 vmcs_writel(GUEST_SYSENTER_EIP, data);
2329 case MSR_IA32_SYSENTER_ESP:
2330 vmcs_writel(GUEST_SYSENTER_ESP, data);
2333 kvm_write_tsc(vcpu, msr_info);
2335 case MSR_IA32_CR_PAT:
2336 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2337 vmcs_write64(GUEST_IA32_PAT, data);
2338 vcpu->arch.pat = data;
2341 ret = kvm_set_msr_common(vcpu, msr_info);
2343 case MSR_IA32_TSC_ADJUST:
2344 ret = kvm_set_msr_common(vcpu, msr_info);
2347 if (!vmx->rdtscp_enabled)
2349 /* Check reserved bit, higher 32 bits should be zero */
2350 if ((data >> 32) != 0)
2352 /* Otherwise falls through */
2354 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2356 msr = find_msr_entry(vmx, msr_index);
2359 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2361 kvm_set_shared_msr(msr->index, msr->data,
2367 ret = kvm_set_msr_common(vcpu, msr_info);
2373 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2375 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2378 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2381 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2383 case VCPU_EXREG_PDPTR:
2385 ept_save_pdptrs(vcpu);
2392 static __init int cpu_has_kvm_support(void)
2394 return cpu_has_vmx();
2397 static __init int vmx_disabled_by_bios(void)
2401 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2402 if (msr & FEATURE_CONTROL_LOCKED) {
2403 /* launched w/ TXT and VMX disabled */
2404 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2407 /* launched w/o TXT and VMX only enabled w/ TXT */
2408 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2409 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2410 && !tboot_enabled()) {
2411 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2412 "activate TXT before enabling KVM\n");
2415 /* launched w/o TXT and VMX disabled */
2416 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2417 && !tboot_enabled())
2424 static void kvm_cpu_vmxon(u64 addr)
2426 asm volatile (ASM_VMX_VMXON_RAX
2427 : : "a"(&addr), "m"(addr)
2431 static int hardware_enable(void *garbage)
2433 int cpu = raw_smp_processor_id();
2434 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2437 if (read_cr4() & X86_CR4_VMXE)
2440 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2443 * Now we can enable the vmclear operation in kdump
2444 * since the loaded_vmcss_on_cpu list on this cpu
2445 * has been initialized.
2447 * Though the cpu is not in VMX operation now, there
2448 * is no problem to enable the vmclear operation
2449 * for the loaded_vmcss_on_cpu list is empty!
2451 crash_enable_local_vmclear(cpu);
2453 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2455 test_bits = FEATURE_CONTROL_LOCKED;
2456 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2457 if (tboot_enabled())
2458 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2460 if ((old & test_bits) != test_bits) {
2461 /* enable and lock */
2462 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2464 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2466 if (vmm_exclusive) {
2467 kvm_cpu_vmxon(phys_addr);
2471 store_gdt(&__get_cpu_var(host_gdt));
2476 static void vmclear_local_loaded_vmcss(void)
2478 int cpu = raw_smp_processor_id();
2479 struct loaded_vmcs *v, *n;
2481 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2482 loaded_vmcss_on_cpu_link)
2483 __loaded_vmcs_clear(v);
2487 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2490 static void kvm_cpu_vmxoff(void)
2492 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2495 static void hardware_disable(void *garbage)
2497 if (vmm_exclusive) {
2498 vmclear_local_loaded_vmcss();
2501 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2504 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2505 u32 msr, u32 *result)
2507 u32 vmx_msr_low, vmx_msr_high;
2508 u32 ctl = ctl_min | ctl_opt;
2510 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2512 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2513 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2515 /* Ensure minimum (required) set of control bits are supported. */
2523 static __init bool allow_1_setting(u32 msr, u32 ctl)
2525 u32 vmx_msr_low, vmx_msr_high;
2527 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2528 return vmx_msr_high & ctl;
2531 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2533 u32 vmx_msr_low, vmx_msr_high;
2534 u32 min, opt, min2, opt2;
2535 u32 _pin_based_exec_control = 0;
2536 u32 _cpu_based_exec_control = 0;
2537 u32 _cpu_based_2nd_exec_control = 0;
2538 u32 _vmexit_control = 0;
2539 u32 _vmentry_control = 0;
2541 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2542 opt = PIN_BASED_VIRTUAL_NMIS;
2543 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2544 &_pin_based_exec_control) < 0)
2547 min = CPU_BASED_HLT_EXITING |
2548 #ifdef CONFIG_X86_64
2549 CPU_BASED_CR8_LOAD_EXITING |
2550 CPU_BASED_CR8_STORE_EXITING |
2552 CPU_BASED_CR3_LOAD_EXITING |
2553 CPU_BASED_CR3_STORE_EXITING |
2554 CPU_BASED_USE_IO_BITMAPS |
2555 CPU_BASED_MOV_DR_EXITING |
2556 CPU_BASED_USE_TSC_OFFSETING |
2557 CPU_BASED_MWAIT_EXITING |
2558 CPU_BASED_MONITOR_EXITING |
2559 CPU_BASED_INVLPG_EXITING |
2560 CPU_BASED_RDPMC_EXITING;
2562 opt = CPU_BASED_TPR_SHADOW |
2563 CPU_BASED_USE_MSR_BITMAPS |
2564 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2565 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2566 &_cpu_based_exec_control) < 0)
2568 #ifdef CONFIG_X86_64
2569 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2570 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2571 ~CPU_BASED_CR8_STORE_EXITING;
2573 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2575 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2576 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2577 SECONDARY_EXEC_WBINVD_EXITING |
2578 SECONDARY_EXEC_ENABLE_VPID |
2579 SECONDARY_EXEC_ENABLE_EPT |
2580 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2581 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2582 SECONDARY_EXEC_RDTSCP |
2583 SECONDARY_EXEC_ENABLE_INVPCID |
2584 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2585 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
2586 if (adjust_vmx_controls(min2, opt2,
2587 MSR_IA32_VMX_PROCBASED_CTLS2,
2588 &_cpu_based_2nd_exec_control) < 0)
2591 #ifndef CONFIG_X86_64
2592 if (!(_cpu_based_2nd_exec_control &
2593 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2594 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2597 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2598 _cpu_based_2nd_exec_control &= ~(
2599 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2600 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2601 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2603 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2604 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2606 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2607 CPU_BASED_CR3_STORE_EXITING |
2608 CPU_BASED_INVLPG_EXITING);
2609 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2610 vmx_capability.ept, vmx_capability.vpid);
2614 #ifdef CONFIG_X86_64
2615 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2617 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2618 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2619 &_vmexit_control) < 0)
2623 opt = VM_ENTRY_LOAD_IA32_PAT;
2624 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2625 &_vmentry_control) < 0)
2628 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2630 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2631 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2634 #ifdef CONFIG_X86_64
2635 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2636 if (vmx_msr_high & (1u<<16))
2640 /* Require Write-Back (WB) memory type for VMCS accesses. */
2641 if (((vmx_msr_high >> 18) & 15) != 6)
2644 vmcs_conf->size = vmx_msr_high & 0x1fff;
2645 vmcs_conf->order = get_order(vmcs_config.size);
2646 vmcs_conf->revision_id = vmx_msr_low;
2648 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2649 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2650 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2651 vmcs_conf->vmexit_ctrl = _vmexit_control;
2652 vmcs_conf->vmentry_ctrl = _vmentry_control;
2654 cpu_has_load_ia32_efer =
2655 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2656 VM_ENTRY_LOAD_IA32_EFER)
2657 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2658 VM_EXIT_LOAD_IA32_EFER);
2660 cpu_has_load_perf_global_ctrl =
2661 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2662 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2663 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2664 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2667 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2668 * but due to arrata below it can't be used. Workaround is to use
2669 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2671 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2676 * BC86,AAY89,BD102 (model 44)
2680 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2681 switch (boot_cpu_data.x86_model) {
2687 cpu_has_load_perf_global_ctrl = false;
2688 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2689 "does not work properly. Using workaround\n");
2699 static struct vmcs *alloc_vmcs_cpu(int cpu)
2701 int node = cpu_to_node(cpu);
2705 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2708 vmcs = page_address(pages);
2709 memset(vmcs, 0, vmcs_config.size);
2710 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2714 static struct vmcs *alloc_vmcs(void)
2716 return alloc_vmcs_cpu(raw_smp_processor_id());
2719 static void free_vmcs(struct vmcs *vmcs)
2721 free_pages((unsigned long)vmcs, vmcs_config.order);
2725 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2727 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2729 if (!loaded_vmcs->vmcs)
2731 loaded_vmcs_clear(loaded_vmcs);
2732 free_vmcs(loaded_vmcs->vmcs);
2733 loaded_vmcs->vmcs = NULL;
2736 static void free_kvm_area(void)
2740 for_each_possible_cpu(cpu) {
2741 free_vmcs(per_cpu(vmxarea, cpu));
2742 per_cpu(vmxarea, cpu) = NULL;
2746 static __init int alloc_kvm_area(void)
2750 for_each_possible_cpu(cpu) {
2753 vmcs = alloc_vmcs_cpu(cpu);
2759 per_cpu(vmxarea, cpu) = vmcs;
2764 static __init int hardware_setup(void)
2766 if (setup_vmcs_config(&vmcs_config) < 0)
2769 if (boot_cpu_has(X86_FEATURE_NX))
2770 kvm_enable_efer_bits(EFER_NX);
2772 if (!cpu_has_vmx_vpid())
2775 if (!cpu_has_vmx_ept() ||
2776 !cpu_has_vmx_ept_4levels()) {
2778 enable_unrestricted_guest = 0;
2779 enable_ept_ad_bits = 0;
2782 if (!cpu_has_vmx_ept_ad_bits())
2783 enable_ept_ad_bits = 0;
2785 if (!cpu_has_vmx_unrestricted_guest())
2786 enable_unrestricted_guest = 0;
2788 if (!cpu_has_vmx_flexpriority())
2789 flexpriority_enabled = 0;
2791 if (!cpu_has_vmx_tpr_shadow())
2792 kvm_x86_ops->update_cr8_intercept = NULL;
2794 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2795 kvm_disable_largepages();
2797 if (!cpu_has_vmx_ple())
2800 if (!cpu_has_vmx_apic_register_virt() ||
2801 !cpu_has_vmx_virtual_intr_delivery())
2802 enable_apicv_reg_vid = 0;
2804 if (enable_apicv_reg_vid)
2805 kvm_x86_ops->update_cr8_intercept = NULL;
2807 kvm_x86_ops->hwapic_irr_update = NULL;
2810 nested_vmx_setup_ctls_msrs();
2812 return alloc_kvm_area();
2815 static __exit void hardware_unsetup(void)
2820 static bool emulation_required(struct kvm_vcpu *vcpu)
2822 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2825 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2826 struct kvm_segment *save)
2828 if (!emulate_invalid_guest_state) {
2830 * CS and SS RPL should be equal during guest entry according
2831 * to VMX spec, but in reality it is not always so. Since vcpu
2832 * is in the middle of the transition from real mode to
2833 * protected mode it is safe to assume that RPL 0 is a good
2836 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2837 save->selector &= ~SELECTOR_RPL_MASK;
2838 save->dpl = save->selector & SELECTOR_RPL_MASK;
2841 vmx_set_segment(vcpu, save, seg);
2844 static void enter_pmode(struct kvm_vcpu *vcpu)
2846 unsigned long flags;
2847 struct vcpu_vmx *vmx = to_vmx(vcpu);
2850 * Update real mode segment cache. It may be not up-to-date if sement
2851 * register was written while vcpu was in a guest mode.
2853 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2854 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2855 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2856 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2857 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2858 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2860 vmx->rmode.vm86_active = 0;
2862 vmx_segment_cache_clear(vmx);
2864 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2866 flags = vmcs_readl(GUEST_RFLAGS);
2867 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2868 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2869 vmcs_writel(GUEST_RFLAGS, flags);
2871 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2872 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2874 update_exception_bitmap(vcpu);
2876 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2877 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2878 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2879 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2880 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2881 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2883 /* CPL is always 0 when CPU enters protected mode */
2884 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2888 static gva_t rmode_tss_base(struct kvm *kvm)
2890 if (!kvm->arch.tss_addr) {
2891 struct kvm_memslots *slots;
2892 struct kvm_memory_slot *slot;
2895 slots = kvm_memslots(kvm);
2896 slot = id_to_memslot(slots, 0);
2897 base_gfn = slot->base_gfn + slot->npages - 3;
2899 return base_gfn << PAGE_SHIFT;
2901 return kvm->arch.tss_addr;
2904 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2906 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2907 struct kvm_segment var = *save;
2910 if (seg == VCPU_SREG_CS)
2913 if (!emulate_invalid_guest_state) {
2914 var.selector = var.base >> 4;
2915 var.base = var.base & 0xffff0;
2925 if (save->base & 0xf)
2926 printk_once(KERN_WARNING "kvm: segment base is not "
2927 "paragraph aligned when entering "
2928 "protected mode (seg=%d)", seg);
2931 vmcs_write16(sf->selector, var.selector);
2932 vmcs_write32(sf->base, var.base);
2933 vmcs_write32(sf->limit, var.limit);
2934 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2937 static void enter_rmode(struct kvm_vcpu *vcpu)
2939 unsigned long flags;
2940 struct vcpu_vmx *vmx = to_vmx(vcpu);
2942 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2943 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2944 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2945 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2946 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2947 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2948 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2950 vmx->rmode.vm86_active = 1;
2953 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2954 * vcpu. Call it here with phys address pointing 16M below 4G.
2956 if (!vcpu->kvm->arch.tss_addr) {
2957 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2958 "called before entering vcpu\n");
2959 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2960 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2961 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2964 vmx_segment_cache_clear(vmx);
2966 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2967 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2968 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2970 flags = vmcs_readl(GUEST_RFLAGS);
2971 vmx->rmode.save_rflags = flags;
2973 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2975 vmcs_writel(GUEST_RFLAGS, flags);
2976 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2977 update_exception_bitmap(vcpu);
2979 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2980 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2981 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2982 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2983 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2984 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2986 kvm_mmu_reset_context(vcpu);
2989 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2991 struct vcpu_vmx *vmx = to_vmx(vcpu);
2992 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2998 * Force kernel_gs_base reloading before EFER changes, as control
2999 * of this msr depends on is_long_mode().
3001 vmx_load_host_state(to_vmx(vcpu));
3002 vcpu->arch.efer = efer;
3003 if (efer & EFER_LMA) {
3004 vmcs_write32(VM_ENTRY_CONTROLS,
3005 vmcs_read32(VM_ENTRY_CONTROLS) |
3006 VM_ENTRY_IA32E_MODE);
3009 vmcs_write32(VM_ENTRY_CONTROLS,
3010 vmcs_read32(VM_ENTRY_CONTROLS) &
3011 ~VM_ENTRY_IA32E_MODE);
3013 msr->data = efer & ~EFER_LME;
3018 #ifdef CONFIG_X86_64
3020 static void enter_lmode(struct kvm_vcpu *vcpu)
3024 vmx_segment_cache_clear(to_vmx(vcpu));
3026 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3027 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3028 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3030 vmcs_write32(GUEST_TR_AR_BYTES,
3031 (guest_tr_ar & ~AR_TYPE_MASK)
3032 | AR_TYPE_BUSY_64_TSS);
3034 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3037 static void exit_lmode(struct kvm_vcpu *vcpu)
3039 vmcs_write32(VM_ENTRY_CONTROLS,
3040 vmcs_read32(VM_ENTRY_CONTROLS)
3041 & ~VM_ENTRY_IA32E_MODE);
3042 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3047 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3049 vpid_sync_context(to_vmx(vcpu));
3051 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3053 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3057 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3059 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3061 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3062 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3065 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3067 if (enable_ept && is_paging(vcpu))
3068 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3069 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3072 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3074 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3076 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3077 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3080 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3082 if (!test_bit(VCPU_EXREG_PDPTR,
3083 (unsigned long *)&vcpu->arch.regs_dirty))
3086 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3087 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3088 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3089 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3090 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3094 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3096 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3097 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3098 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3099 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3100 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3103 __set_bit(VCPU_EXREG_PDPTR,
3104 (unsigned long *)&vcpu->arch.regs_avail);
3105 __set_bit(VCPU_EXREG_PDPTR,
3106 (unsigned long *)&vcpu->arch.regs_dirty);
3109 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3111 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3113 struct kvm_vcpu *vcpu)
3115 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3116 vmx_decache_cr3(vcpu);
3117 if (!(cr0 & X86_CR0_PG)) {
3118 /* From paging/starting to nonpaging */
3119 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3120 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3121 (CPU_BASED_CR3_LOAD_EXITING |
3122 CPU_BASED_CR3_STORE_EXITING));
3123 vcpu->arch.cr0 = cr0;
3124 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3125 } else if (!is_paging(vcpu)) {
3126 /* From nonpaging to paging */
3127 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3128 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3129 ~(CPU_BASED_CR3_LOAD_EXITING |
3130 CPU_BASED_CR3_STORE_EXITING));
3131 vcpu->arch.cr0 = cr0;
3132 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3135 if (!(cr0 & X86_CR0_WP))
3136 *hw_cr0 &= ~X86_CR0_WP;
3139 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3141 struct vcpu_vmx *vmx = to_vmx(vcpu);
3142 unsigned long hw_cr0;
3144 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3145 if (enable_unrestricted_guest)
3146 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3148 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3150 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3153 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3157 #ifdef CONFIG_X86_64
3158 if (vcpu->arch.efer & EFER_LME) {
3159 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3161 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3167 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3169 if (!vcpu->fpu_active)
3170 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3172 vmcs_writel(CR0_READ_SHADOW, cr0);
3173 vmcs_writel(GUEST_CR0, hw_cr0);
3174 vcpu->arch.cr0 = cr0;
3176 /* depends on vcpu->arch.cr0 to be set to a new value */
3177 vmx->emulation_required = emulation_required(vcpu);
3180 static u64 construct_eptp(unsigned long root_hpa)
3184 /* TODO write the value reading from MSR */
3185 eptp = VMX_EPT_DEFAULT_MT |
3186 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3187 if (enable_ept_ad_bits)
3188 eptp |= VMX_EPT_AD_ENABLE_BIT;
3189 eptp |= (root_hpa & PAGE_MASK);
3194 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3196 unsigned long guest_cr3;
3201 eptp = construct_eptp(cr3);
3202 vmcs_write64(EPT_POINTER, eptp);
3203 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3204 vcpu->kvm->arch.ept_identity_map_addr;
3205 ept_load_pdptrs(vcpu);
3208 vmx_flush_tlb(vcpu);
3209 vmcs_writel(GUEST_CR3, guest_cr3);
3212 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3214 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3215 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3217 if (cr4 & X86_CR4_VMXE) {
3219 * To use VMXON (and later other VMX instructions), a guest
3220 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3221 * So basically the check on whether to allow nested VMX
3224 if (!nested_vmx_allowed(vcpu))
3226 } else if (to_vmx(vcpu)->nested.vmxon)
3229 vcpu->arch.cr4 = cr4;
3231 if (!is_paging(vcpu)) {
3232 hw_cr4 &= ~X86_CR4_PAE;
3233 hw_cr4 |= X86_CR4_PSE;
3235 * SMEP is disabled if CPU is in non-paging mode in
3236 * hardware. However KVM always uses paging mode to
3237 * emulate guest non-paging mode with TDP.
3238 * To emulate this behavior, SMEP needs to be manually
3239 * disabled when guest switches to non-paging mode.
3241 hw_cr4 &= ~X86_CR4_SMEP;
3242 } else if (!(cr4 & X86_CR4_PAE)) {
3243 hw_cr4 &= ~X86_CR4_PAE;
3247 vmcs_writel(CR4_READ_SHADOW, cr4);
3248 vmcs_writel(GUEST_CR4, hw_cr4);
3252 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3253 struct kvm_segment *var, int seg)
3255 struct vcpu_vmx *vmx = to_vmx(vcpu);
3258 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3259 *var = vmx->rmode.segs[seg];
3260 if (seg == VCPU_SREG_TR
3261 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3263 var->base = vmx_read_guest_seg_base(vmx, seg);
3264 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3267 var->base = vmx_read_guest_seg_base(vmx, seg);
3268 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3269 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3270 ar = vmx_read_guest_seg_ar(vmx, seg);
3271 var->type = ar & 15;
3272 var->s = (ar >> 4) & 1;
3273 var->dpl = (ar >> 5) & 3;
3274 var->present = (ar >> 7) & 1;
3275 var->avl = (ar >> 12) & 1;
3276 var->l = (ar >> 13) & 1;
3277 var->db = (ar >> 14) & 1;
3278 var->g = (ar >> 15) & 1;
3279 var->unusable = (ar >> 16) & 1;
3282 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3284 struct kvm_segment s;
3286 if (to_vmx(vcpu)->rmode.vm86_active) {
3287 vmx_get_segment(vcpu, &s, seg);
3290 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3293 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3295 struct vcpu_vmx *vmx = to_vmx(vcpu);
3297 if (!is_protmode(vcpu))
3300 if (!is_long_mode(vcpu)
3301 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3304 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3305 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3306 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3313 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3317 if (var->unusable || !var->present)
3320 ar = var->type & 15;
3321 ar |= (var->s & 1) << 4;
3322 ar |= (var->dpl & 3) << 5;
3323 ar |= (var->present & 1) << 7;
3324 ar |= (var->avl & 1) << 12;
3325 ar |= (var->l & 1) << 13;
3326 ar |= (var->db & 1) << 14;
3327 ar |= (var->g & 1) << 15;
3333 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3334 struct kvm_segment *var, int seg)
3336 struct vcpu_vmx *vmx = to_vmx(vcpu);
3337 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3339 vmx_segment_cache_clear(vmx);
3340 if (seg == VCPU_SREG_CS)
3341 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3343 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3344 vmx->rmode.segs[seg] = *var;
3345 if (seg == VCPU_SREG_TR)
3346 vmcs_write16(sf->selector, var->selector);
3348 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3352 vmcs_writel(sf->base, var->base);
3353 vmcs_write32(sf->limit, var->limit);
3354 vmcs_write16(sf->selector, var->selector);
3357 * Fix the "Accessed" bit in AR field of segment registers for older
3359 * IA32 arch specifies that at the time of processor reset the
3360 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3361 * is setting it to 0 in the userland code. This causes invalid guest
3362 * state vmexit when "unrestricted guest" mode is turned on.
3363 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3364 * tree. Newer qemu binaries with that qemu fix would not need this
3367 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3368 var->type |= 0x1; /* Accessed */
3370 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3373 vmx->emulation_required |= emulation_required(vcpu);
3376 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3378 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3380 *db = (ar >> 14) & 1;
3381 *l = (ar >> 13) & 1;
3384 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3386 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3387 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3390 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3392 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3393 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3396 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3398 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3399 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3402 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3404 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3405 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3408 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3410 struct kvm_segment var;
3413 vmx_get_segment(vcpu, &var, seg);
3415 if (seg == VCPU_SREG_CS)
3417 ar = vmx_segment_access_rights(&var);
3419 if (var.base != (var.selector << 4))
3421 if (var.limit != 0xffff)
3429 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3431 struct kvm_segment cs;
3432 unsigned int cs_rpl;
3434 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3435 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3439 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3443 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3444 if (cs.dpl > cs_rpl)
3447 if (cs.dpl != cs_rpl)
3453 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3457 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3459 struct kvm_segment ss;
3460 unsigned int ss_rpl;
3462 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3463 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3467 if (ss.type != 3 && ss.type != 7)
3471 if (ss.dpl != ss_rpl) /* DPL != RPL */
3479 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3481 struct kvm_segment var;
3484 vmx_get_segment(vcpu, &var, seg);
3485 rpl = var.selector & SELECTOR_RPL_MASK;
3493 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3494 if (var.dpl < rpl) /* DPL < RPL */
3498 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3504 static bool tr_valid(struct kvm_vcpu *vcpu)
3506 struct kvm_segment tr;
3508 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3512 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3514 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3522 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3524 struct kvm_segment ldtr;
3526 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3530 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3540 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3542 struct kvm_segment cs, ss;
3544 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3545 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3547 return ((cs.selector & SELECTOR_RPL_MASK) ==
3548 (ss.selector & SELECTOR_RPL_MASK));
3552 * Check if guest state is valid. Returns true if valid, false if
3554 * We assume that registers are always usable
3556 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3558 if (enable_unrestricted_guest)
3561 /* real mode guest state checks */
3562 if (!is_protmode(vcpu)) {
3563 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3565 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3567 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3569 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3571 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3573 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3576 /* protected mode guest state checks */
3577 if (!cs_ss_rpl_check(vcpu))
3579 if (!code_segment_valid(vcpu))
3581 if (!stack_segment_valid(vcpu))
3583 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3585 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3587 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3589 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3591 if (!tr_valid(vcpu))
3593 if (!ldtr_valid(vcpu))
3597 * - Add checks on RIP
3598 * - Add checks on RFLAGS
3604 static int init_rmode_tss(struct kvm *kvm)
3608 int r, idx, ret = 0;
3610 idx = srcu_read_lock(&kvm->srcu);
3611 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3612 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3615 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3616 r = kvm_write_guest_page(kvm, fn++, &data,
3617 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3620 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3623 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3627 r = kvm_write_guest_page(kvm, fn, &data,
3628 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3635 srcu_read_unlock(&kvm->srcu, idx);
3639 static int init_rmode_identity_map(struct kvm *kvm)
3642 pfn_t identity_map_pfn;
3647 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3648 printk(KERN_ERR "EPT: identity-mapping pagetable "
3649 "haven't been allocated!\n");
3652 if (likely(kvm->arch.ept_identity_pagetable_done))
3655 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3656 idx = srcu_read_lock(&kvm->srcu);
3657 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3660 /* Set up identity-mapping pagetable for EPT in real mode */
3661 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3662 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3663 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3664 r = kvm_write_guest_page(kvm, identity_map_pfn,
3665 &tmp, i * sizeof(tmp), sizeof(tmp));
3669 kvm->arch.ept_identity_pagetable_done = true;
3672 srcu_read_unlock(&kvm->srcu, idx);
3676 static void seg_setup(int seg)
3678 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3681 vmcs_write16(sf->selector, 0);
3682 vmcs_writel(sf->base, 0);
3683 vmcs_write32(sf->limit, 0xffff);
3685 if (seg == VCPU_SREG_CS)
3686 ar |= 0x08; /* code segment */
3688 vmcs_write32(sf->ar_bytes, ar);
3691 static int alloc_apic_access_page(struct kvm *kvm)
3694 struct kvm_userspace_memory_region kvm_userspace_mem;
3697 mutex_lock(&kvm->slots_lock);
3698 if (kvm->arch.apic_access_page)
3700 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3701 kvm_userspace_mem.flags = 0;
3702 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3703 kvm_userspace_mem.memory_size = PAGE_SIZE;
3704 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3708 page = gfn_to_page(kvm, 0xfee00);
3709 if (is_error_page(page)) {
3714 kvm->arch.apic_access_page = page;
3716 mutex_unlock(&kvm->slots_lock);
3720 static int alloc_identity_pagetable(struct kvm *kvm)
3723 struct kvm_userspace_memory_region kvm_userspace_mem;
3726 mutex_lock(&kvm->slots_lock);
3727 if (kvm->arch.ept_identity_pagetable)
3729 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3730 kvm_userspace_mem.flags = 0;
3731 kvm_userspace_mem.guest_phys_addr =
3732 kvm->arch.ept_identity_map_addr;
3733 kvm_userspace_mem.memory_size = PAGE_SIZE;
3734 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3738 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3739 if (is_error_page(page)) {
3744 kvm->arch.ept_identity_pagetable = page;
3746 mutex_unlock(&kvm->slots_lock);
3750 static void allocate_vpid(struct vcpu_vmx *vmx)
3757 spin_lock(&vmx_vpid_lock);
3758 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3759 if (vpid < VMX_NR_VPIDS) {
3761 __set_bit(vpid, vmx_vpid_bitmap);
3763 spin_unlock(&vmx_vpid_lock);
3766 static void free_vpid(struct vcpu_vmx *vmx)
3770 spin_lock(&vmx_vpid_lock);
3772 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3773 spin_unlock(&vmx_vpid_lock);
3776 #define MSR_TYPE_R 1
3777 #define MSR_TYPE_W 2
3778 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3781 int f = sizeof(unsigned long);
3783 if (!cpu_has_vmx_msr_bitmap())
3787 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3788 * have the write-low and read-high bitmap offsets the wrong way round.
3789 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3791 if (msr <= 0x1fff) {
3792 if (type & MSR_TYPE_R)
3794 __clear_bit(msr, msr_bitmap + 0x000 / f);
3796 if (type & MSR_TYPE_W)
3798 __clear_bit(msr, msr_bitmap + 0x800 / f);
3800 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3802 if (type & MSR_TYPE_R)
3804 __clear_bit(msr, msr_bitmap + 0x400 / f);
3806 if (type & MSR_TYPE_W)
3808 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3813 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3816 int f = sizeof(unsigned long);
3818 if (!cpu_has_vmx_msr_bitmap())
3822 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3823 * have the write-low and read-high bitmap offsets the wrong way round.
3824 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3826 if (msr <= 0x1fff) {
3827 if (type & MSR_TYPE_R)
3829 __set_bit(msr, msr_bitmap + 0x000 / f);
3831 if (type & MSR_TYPE_W)
3833 __set_bit(msr, msr_bitmap + 0x800 / f);
3835 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3837 if (type & MSR_TYPE_R)
3839 __set_bit(msr, msr_bitmap + 0x400 / f);
3841 if (type & MSR_TYPE_W)
3843 __set_bit(msr, msr_bitmap + 0xc00 / f);
3848 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3851 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3852 msr, MSR_TYPE_R | MSR_TYPE_W);
3853 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3854 msr, MSR_TYPE_R | MSR_TYPE_W);
3857 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3859 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3861 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3865 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3867 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3869 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3873 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3875 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3877 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3882 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3883 * will not change in the lifetime of the guest.
3884 * Note that host-state that does change is set elsewhere. E.g., host-state
3885 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3887 static void vmx_set_constant_host_state(void)
3893 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
3894 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3895 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3897 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3898 #ifdef CONFIG_X86_64
3900 * Load null selectors, so we can avoid reloading them in
3901 * __vmx_load_host_state(), in case userspace uses the null selectors
3902 * too (the expected case).
3904 vmcs_write16(HOST_DS_SELECTOR, 0);
3905 vmcs_write16(HOST_ES_SELECTOR, 0);
3907 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3908 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3910 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3911 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3913 native_store_idt(&dt);
3914 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3916 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
3918 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3919 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3920 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3921 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3923 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3924 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3925 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3929 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3931 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3933 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3934 if (is_guest_mode(&vmx->vcpu))
3935 vmx->vcpu.arch.cr4_guest_owned_bits &=
3936 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3937 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3940 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3942 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3943 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3944 exec_control &= ~CPU_BASED_TPR_SHADOW;
3945 #ifdef CONFIG_X86_64
3946 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3947 CPU_BASED_CR8_LOAD_EXITING;
3951 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3952 CPU_BASED_CR3_LOAD_EXITING |
3953 CPU_BASED_INVLPG_EXITING;
3954 return exec_control;
3957 static int vmx_vm_has_apicv(struct kvm *kvm)
3959 return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
3962 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3964 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3965 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3966 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3968 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3970 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3971 enable_unrestricted_guest = 0;
3972 /* Enable INVPCID for non-ept guests may cause performance regression. */
3973 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3975 if (!enable_unrestricted_guest)
3976 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3978 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3979 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
3980 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3982 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3983 return exec_control;
3986 static void ept_set_mmio_spte_mask(void)
3989 * EPT Misconfigurations can be generated if the value of bits 2:0
3990 * of an EPT paging-structure entry is 110b (write/execute).
3991 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3994 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3998 * Sets up the vmcs for emulated real mode.
4000 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4002 #ifdef CONFIG_X86_64
4008 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4009 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4011 if (cpu_has_vmx_msr_bitmap())
4012 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4014 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4017 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
4018 vmcs_config.pin_based_exec_ctrl);
4020 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4022 if (cpu_has_secondary_exec_ctrls()) {
4023 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4024 vmx_secondary_exec_control(vmx));
4027 if (enable_apicv_reg_vid) {
4028 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4029 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4030 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4031 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4033 vmcs_write16(GUEST_INTR_STATUS, 0);
4037 vmcs_write32(PLE_GAP, ple_gap);
4038 vmcs_write32(PLE_WINDOW, ple_window);
4041 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4042 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4043 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4045 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4046 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4047 vmx_set_constant_host_state();
4048 #ifdef CONFIG_X86_64
4049 rdmsrl(MSR_FS_BASE, a);
4050 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4051 rdmsrl(MSR_GS_BASE, a);
4052 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4054 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4055 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4058 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4059 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4060 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4061 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4062 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4064 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4065 u32 msr_low, msr_high;
4067 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4068 host_pat = msr_low | ((u64) msr_high << 32);
4069 /* Write the default value follow host pat */
4070 vmcs_write64(GUEST_IA32_PAT, host_pat);
4071 /* Keep arch.pat sync with GUEST_IA32_PAT */
4072 vmx->vcpu.arch.pat = host_pat;
4075 for (i = 0; i < NR_VMX_MSR; ++i) {
4076 u32 index = vmx_msr_index[i];
4077 u32 data_low, data_high;
4080 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4082 if (wrmsr_safe(index, data_low, data_high) < 0)
4084 vmx->guest_msrs[j].index = i;
4085 vmx->guest_msrs[j].data = 0;
4086 vmx->guest_msrs[j].mask = -1ull;
4090 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4092 /* 22.2.1, 20.8.1 */
4093 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4095 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4096 set_cr4_guest_host_mask(vmx);
4101 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4103 struct vcpu_vmx *vmx = to_vmx(vcpu);
4107 vmx->rmode.vm86_active = 0;
4109 vmx->soft_vnmi_blocked = 0;
4111 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4112 kvm_set_cr8(&vmx->vcpu, 0);
4113 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4114 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4115 msr |= MSR_IA32_APICBASE_BSP;
4116 kvm_set_apic_base(&vmx->vcpu, msr);
4118 vmx_segment_cache_clear(vmx);
4120 seg_setup(VCPU_SREG_CS);
4121 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4122 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4124 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
4125 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
4128 seg_setup(VCPU_SREG_DS);
4129 seg_setup(VCPU_SREG_ES);
4130 seg_setup(VCPU_SREG_FS);
4131 seg_setup(VCPU_SREG_GS);
4132 seg_setup(VCPU_SREG_SS);
4134 vmcs_write16(GUEST_TR_SELECTOR, 0);
4135 vmcs_writel(GUEST_TR_BASE, 0);
4136 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4137 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4139 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4140 vmcs_writel(GUEST_LDTR_BASE, 0);
4141 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4142 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4144 vmcs_write32(GUEST_SYSENTER_CS, 0);
4145 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4146 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4148 vmcs_writel(GUEST_RFLAGS, 0x02);
4149 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4150 kvm_rip_write(vcpu, 0xfff0);
4152 kvm_rip_write(vcpu, 0);
4154 vmcs_writel(GUEST_GDTR_BASE, 0);
4155 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4157 vmcs_writel(GUEST_IDTR_BASE, 0);
4158 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4160 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4161 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4162 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4164 /* Special registers */
4165 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4169 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4171 if (cpu_has_vmx_tpr_shadow()) {
4172 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4173 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4174 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4175 __pa(vmx->vcpu.arch.apic->regs));
4176 vmcs_write32(TPR_THRESHOLD, 0);
4179 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4180 vmcs_write64(APIC_ACCESS_ADDR,
4181 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4184 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4186 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4187 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4188 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4189 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4190 vmx_set_cr4(&vmx->vcpu, 0);
4191 vmx_set_efer(&vmx->vcpu, 0);
4192 vmx_fpu_activate(&vmx->vcpu);
4193 update_exception_bitmap(&vmx->vcpu);
4195 vpid_sync_context(vmx);
4203 * In nested virtualization, check if L1 asked to exit on external interrupts.
4204 * For most existing hypervisors, this will always return true.
4206 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4208 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4209 PIN_BASED_EXT_INTR_MASK;
4212 static void enable_irq_window(struct kvm_vcpu *vcpu)
4214 u32 cpu_based_vm_exec_control;
4215 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4217 * We get here if vmx_interrupt_allowed() said we can't
4218 * inject to L1 now because L2 must run. Ask L2 to exit
4219 * right after entry, so we can inject to L1 more promptly.
4221 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4225 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4226 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4227 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4230 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4232 u32 cpu_based_vm_exec_control;
4234 if (!cpu_has_virtual_nmis()) {
4235 enable_irq_window(vcpu);
4239 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4240 enable_irq_window(vcpu);
4243 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4244 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4245 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4248 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4250 struct vcpu_vmx *vmx = to_vmx(vcpu);
4252 int irq = vcpu->arch.interrupt.nr;
4254 trace_kvm_inj_virq(irq);
4256 ++vcpu->stat.irq_injections;
4257 if (vmx->rmode.vm86_active) {
4259 if (vcpu->arch.interrupt.soft)
4260 inc_eip = vcpu->arch.event_exit_inst_len;
4261 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4262 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4265 intr = irq | INTR_INFO_VALID_MASK;
4266 if (vcpu->arch.interrupt.soft) {
4267 intr |= INTR_TYPE_SOFT_INTR;
4268 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4269 vmx->vcpu.arch.event_exit_inst_len);
4271 intr |= INTR_TYPE_EXT_INTR;
4272 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4275 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4277 struct vcpu_vmx *vmx = to_vmx(vcpu);
4279 if (is_guest_mode(vcpu))
4282 if (!cpu_has_virtual_nmis()) {
4284 * Tracking the NMI-blocked state in software is built upon
4285 * finding the next open IRQ window. This, in turn, depends on
4286 * well-behaving guests: They have to keep IRQs disabled at
4287 * least as long as the NMI handler runs. Otherwise we may
4288 * cause NMI nesting, maybe breaking the guest. But as this is
4289 * highly unlikely, we can live with the residual risk.
4291 vmx->soft_vnmi_blocked = 1;
4292 vmx->vnmi_blocked_time = 0;
4295 ++vcpu->stat.nmi_injections;
4296 vmx->nmi_known_unmasked = false;
4297 if (vmx->rmode.vm86_active) {
4298 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4299 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4302 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4303 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4306 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4308 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4311 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4312 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4313 | GUEST_INTR_STATE_NMI));
4316 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4318 if (!cpu_has_virtual_nmis())
4319 return to_vmx(vcpu)->soft_vnmi_blocked;
4320 if (to_vmx(vcpu)->nmi_known_unmasked)
4322 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4325 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4327 struct vcpu_vmx *vmx = to_vmx(vcpu);
4329 if (!cpu_has_virtual_nmis()) {
4330 if (vmx->soft_vnmi_blocked != masked) {
4331 vmx->soft_vnmi_blocked = masked;
4332 vmx->vnmi_blocked_time = 0;
4335 vmx->nmi_known_unmasked = !masked;
4337 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4338 GUEST_INTR_STATE_NMI);
4340 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4341 GUEST_INTR_STATE_NMI);
4345 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4347 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4348 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4349 if (to_vmx(vcpu)->nested.nested_run_pending ||
4350 (vmcs12->idt_vectoring_info_field &
4351 VECTORING_INFO_VALID_MASK))
4353 nested_vmx_vmexit(vcpu);
4354 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4355 vmcs12->vm_exit_intr_info = 0;
4356 /* fall through to normal code, but now in L1, not L2 */
4359 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4360 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4361 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4364 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4367 struct kvm_userspace_memory_region tss_mem = {
4368 .slot = TSS_PRIVATE_MEMSLOT,
4369 .guest_phys_addr = addr,
4370 .memory_size = PAGE_SIZE * 3,
4374 ret = kvm_set_memory_region(kvm, &tss_mem);
4377 kvm->arch.tss_addr = addr;
4378 if (!init_rmode_tss(kvm))
4384 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4389 * Update instruction length as we may reinject the exception
4390 * from user space while in guest debugging mode.
4392 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4393 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4394 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4398 if (vcpu->guest_debug &
4399 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4416 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4417 int vec, u32 err_code)
4420 * Instruction with address size override prefix opcode 0x67
4421 * Cause the #SS fault with 0 error code in VM86 mode.
4423 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4424 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4425 if (vcpu->arch.halt_request) {
4426 vcpu->arch.halt_request = 0;
4427 return kvm_emulate_halt(vcpu);
4435 * Forward all other exceptions that are valid in real mode.
4436 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4437 * the required debugging infrastructure rework.
4439 kvm_queue_exception(vcpu, vec);
4444 * Trigger machine check on the host. We assume all the MSRs are already set up
4445 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4446 * We pass a fake environment to the machine check handler because we want
4447 * the guest to be always treated like user space, no matter what context
4448 * it used internally.
4450 static void kvm_machine_check(void)
4452 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4453 struct pt_regs regs = {
4454 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4455 .flags = X86_EFLAGS_IF,
4458 do_machine_check(®s, 0);
4462 static int handle_machine_check(struct kvm_vcpu *vcpu)
4464 /* already handled by vcpu_run */
4468 static int handle_exception(struct kvm_vcpu *vcpu)
4470 struct vcpu_vmx *vmx = to_vmx(vcpu);
4471 struct kvm_run *kvm_run = vcpu->run;
4472 u32 intr_info, ex_no, error_code;
4473 unsigned long cr2, rip, dr6;
4475 enum emulation_result er;
4477 vect_info = vmx->idt_vectoring_info;
4478 intr_info = vmx->exit_intr_info;
4480 if (is_machine_check(intr_info))
4481 return handle_machine_check(vcpu);
4483 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4484 return 1; /* already handled by vmx_vcpu_run() */
4486 if (is_no_device(intr_info)) {
4487 vmx_fpu_activate(vcpu);
4491 if (is_invalid_opcode(intr_info)) {
4492 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4493 if (er != EMULATE_DONE)
4494 kvm_queue_exception(vcpu, UD_VECTOR);
4499 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4500 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4503 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4504 * MMIO, it is better to report an internal error.
4505 * See the comments in vmx_handle_exit.
4507 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4508 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4509 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4510 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4511 vcpu->run->internal.ndata = 2;
4512 vcpu->run->internal.data[0] = vect_info;
4513 vcpu->run->internal.data[1] = intr_info;
4517 if (is_page_fault(intr_info)) {
4518 /* EPT won't cause page fault directly */
4520 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4521 trace_kvm_page_fault(cr2, error_code);
4523 if (kvm_event_needs_reinjection(vcpu))
4524 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4525 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4528 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4530 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4531 return handle_rmode_exception(vcpu, ex_no, error_code);
4535 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4536 if (!(vcpu->guest_debug &
4537 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4538 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4539 kvm_queue_exception(vcpu, DB_VECTOR);
4542 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4543 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4547 * Update instruction length as we may reinject #BP from
4548 * user space while in guest debugging mode. Reading it for
4549 * #DB as well causes no harm, it is not used in that case.
4551 vmx->vcpu.arch.event_exit_inst_len =
4552 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4553 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4554 rip = kvm_rip_read(vcpu);
4555 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4556 kvm_run->debug.arch.exception = ex_no;
4559 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4560 kvm_run->ex.exception = ex_no;
4561 kvm_run->ex.error_code = error_code;
4567 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4569 ++vcpu->stat.irq_exits;
4573 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4575 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4579 static int handle_io(struct kvm_vcpu *vcpu)
4581 unsigned long exit_qualification;
4582 int size, in, string;
4585 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4586 string = (exit_qualification & 16) != 0;
4587 in = (exit_qualification & 8) != 0;
4589 ++vcpu->stat.io_exits;
4592 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4594 port = exit_qualification >> 16;
4595 size = (exit_qualification & 7) + 1;
4596 skip_emulated_instruction(vcpu);
4598 return kvm_fast_pio_out(vcpu, size, port);
4602 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4605 * Patch in the VMCALL instruction:
4607 hypercall[0] = 0x0f;
4608 hypercall[1] = 0x01;
4609 hypercall[2] = 0xc1;
4612 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4613 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4615 if (to_vmx(vcpu)->nested.vmxon &&
4616 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4619 if (is_guest_mode(vcpu)) {
4621 * We get here when L2 changed cr0 in a way that did not change
4622 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4623 * but did change L0 shadowed bits. This can currently happen
4624 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4625 * loading) while pretending to allow the guest to change it.
4627 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4628 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4630 vmcs_writel(CR0_READ_SHADOW, val);
4633 return kvm_set_cr0(vcpu, val);
4636 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4638 if (is_guest_mode(vcpu)) {
4639 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4640 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4642 vmcs_writel(CR4_READ_SHADOW, val);
4645 return kvm_set_cr4(vcpu, val);
4648 /* called to set cr0 as approriate for clts instruction exit. */
4649 static void handle_clts(struct kvm_vcpu *vcpu)
4651 if (is_guest_mode(vcpu)) {
4653 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4654 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4655 * just pretend it's off (also in arch.cr0 for fpu_activate).
4657 vmcs_writel(CR0_READ_SHADOW,
4658 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4659 vcpu->arch.cr0 &= ~X86_CR0_TS;
4661 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4664 static int handle_cr(struct kvm_vcpu *vcpu)
4666 unsigned long exit_qualification, val;
4671 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4672 cr = exit_qualification & 15;
4673 reg = (exit_qualification >> 8) & 15;
4674 switch ((exit_qualification >> 4) & 3) {
4675 case 0: /* mov to cr */
4676 val = kvm_register_read(vcpu, reg);
4677 trace_kvm_cr_write(cr, val);
4680 err = handle_set_cr0(vcpu, val);
4681 kvm_complete_insn_gp(vcpu, err);
4684 err = kvm_set_cr3(vcpu, val);
4685 kvm_complete_insn_gp(vcpu, err);
4688 err = handle_set_cr4(vcpu, val);
4689 kvm_complete_insn_gp(vcpu, err);
4692 u8 cr8_prev = kvm_get_cr8(vcpu);
4693 u8 cr8 = kvm_register_read(vcpu, reg);
4694 err = kvm_set_cr8(vcpu, cr8);
4695 kvm_complete_insn_gp(vcpu, err);
4696 if (irqchip_in_kernel(vcpu->kvm))
4698 if (cr8_prev <= cr8)
4700 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4707 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4708 skip_emulated_instruction(vcpu);
4709 vmx_fpu_activate(vcpu);
4711 case 1: /*mov from cr*/
4714 val = kvm_read_cr3(vcpu);
4715 kvm_register_write(vcpu, reg, val);
4716 trace_kvm_cr_read(cr, val);
4717 skip_emulated_instruction(vcpu);
4720 val = kvm_get_cr8(vcpu);
4721 kvm_register_write(vcpu, reg, val);
4722 trace_kvm_cr_read(cr, val);
4723 skip_emulated_instruction(vcpu);
4728 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4729 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4730 kvm_lmsw(vcpu, val);
4732 skip_emulated_instruction(vcpu);
4737 vcpu->run->exit_reason = 0;
4738 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4739 (int)(exit_qualification >> 4) & 3, cr);
4743 static int handle_dr(struct kvm_vcpu *vcpu)
4745 unsigned long exit_qualification;
4748 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4749 if (!kvm_require_cpl(vcpu, 0))
4751 dr = vmcs_readl(GUEST_DR7);
4754 * As the vm-exit takes precedence over the debug trap, we
4755 * need to emulate the latter, either for the host or the
4756 * guest debugging itself.
4758 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4759 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4760 vcpu->run->debug.arch.dr7 = dr;
4761 vcpu->run->debug.arch.pc =
4762 vmcs_readl(GUEST_CS_BASE) +
4763 vmcs_readl(GUEST_RIP);
4764 vcpu->run->debug.arch.exception = DB_VECTOR;
4765 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4768 vcpu->arch.dr7 &= ~DR7_GD;
4769 vcpu->arch.dr6 |= DR6_BD;
4770 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4771 kvm_queue_exception(vcpu, DB_VECTOR);
4776 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4777 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4778 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4779 if (exit_qualification & TYPE_MOV_FROM_DR) {
4781 if (!kvm_get_dr(vcpu, dr, &val))
4782 kvm_register_write(vcpu, reg, val);
4784 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4785 skip_emulated_instruction(vcpu);
4789 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4791 vmcs_writel(GUEST_DR7, val);
4794 static int handle_cpuid(struct kvm_vcpu *vcpu)
4796 kvm_emulate_cpuid(vcpu);
4800 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4802 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4805 if (vmx_get_msr(vcpu, ecx, &data)) {
4806 trace_kvm_msr_read_ex(ecx);
4807 kvm_inject_gp(vcpu, 0);
4811 trace_kvm_msr_read(ecx, data);
4813 /* FIXME: handling of bits 32:63 of rax, rdx */
4814 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4815 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4816 skip_emulated_instruction(vcpu);
4820 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4822 struct msr_data msr;
4823 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4824 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4825 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4829 msr.host_initiated = false;
4830 if (vmx_set_msr(vcpu, &msr) != 0) {
4831 trace_kvm_msr_write_ex(ecx, data);
4832 kvm_inject_gp(vcpu, 0);
4836 trace_kvm_msr_write(ecx, data);
4837 skip_emulated_instruction(vcpu);
4841 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4843 kvm_make_request(KVM_REQ_EVENT, vcpu);
4847 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4849 u32 cpu_based_vm_exec_control;
4851 /* clear pending irq */
4852 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4853 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4854 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4856 kvm_make_request(KVM_REQ_EVENT, vcpu);
4858 ++vcpu->stat.irq_window_exits;
4861 * If the user space waits to inject interrupts, exit as soon as
4864 if (!irqchip_in_kernel(vcpu->kvm) &&
4865 vcpu->run->request_interrupt_window &&
4866 !kvm_cpu_has_interrupt(vcpu)) {
4867 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4873 static int handle_halt(struct kvm_vcpu *vcpu)
4875 skip_emulated_instruction(vcpu);
4876 return kvm_emulate_halt(vcpu);
4879 static int handle_vmcall(struct kvm_vcpu *vcpu)
4881 skip_emulated_instruction(vcpu);
4882 kvm_emulate_hypercall(vcpu);
4886 static int handle_invd(struct kvm_vcpu *vcpu)
4888 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4891 static int handle_invlpg(struct kvm_vcpu *vcpu)
4893 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4895 kvm_mmu_invlpg(vcpu, exit_qualification);
4896 skip_emulated_instruction(vcpu);
4900 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4904 err = kvm_rdpmc(vcpu);
4905 kvm_complete_insn_gp(vcpu, err);
4910 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4912 skip_emulated_instruction(vcpu);
4913 kvm_emulate_wbinvd(vcpu);
4917 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4919 u64 new_bv = kvm_read_edx_eax(vcpu);
4920 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4922 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4923 skip_emulated_instruction(vcpu);
4927 static int handle_apic_access(struct kvm_vcpu *vcpu)
4929 if (likely(fasteoi)) {
4930 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4931 int access_type, offset;
4933 access_type = exit_qualification & APIC_ACCESS_TYPE;
4934 offset = exit_qualification & APIC_ACCESS_OFFSET;
4936 * Sane guest uses MOV to write EOI, with written value
4937 * not cared. So make a short-circuit here by avoiding
4938 * heavy instruction emulation.
4940 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4941 (offset == APIC_EOI)) {
4942 kvm_lapic_set_eoi(vcpu);
4943 skip_emulated_instruction(vcpu);
4947 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4950 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4952 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4953 int vector = exit_qualification & 0xff;
4955 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4956 kvm_apic_set_eoi_accelerated(vcpu, vector);
4960 static int handle_apic_write(struct kvm_vcpu *vcpu)
4962 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4963 u32 offset = exit_qualification & 0xfff;
4965 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4966 kvm_apic_write_nodecode(vcpu, offset);
4970 static int handle_task_switch(struct kvm_vcpu *vcpu)
4972 struct vcpu_vmx *vmx = to_vmx(vcpu);
4973 unsigned long exit_qualification;
4974 bool has_error_code = false;
4977 int reason, type, idt_v, idt_index;
4979 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4980 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4981 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4983 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4985 reason = (u32)exit_qualification >> 30;
4986 if (reason == TASK_SWITCH_GATE && idt_v) {
4988 case INTR_TYPE_NMI_INTR:
4989 vcpu->arch.nmi_injected = false;
4990 vmx_set_nmi_mask(vcpu, true);
4992 case INTR_TYPE_EXT_INTR:
4993 case INTR_TYPE_SOFT_INTR:
4994 kvm_clear_interrupt_queue(vcpu);
4996 case INTR_TYPE_HARD_EXCEPTION:
4997 if (vmx->idt_vectoring_info &
4998 VECTORING_INFO_DELIVER_CODE_MASK) {
4999 has_error_code = true;
5001 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5004 case INTR_TYPE_SOFT_EXCEPTION:
5005 kvm_clear_exception_queue(vcpu);
5011 tss_selector = exit_qualification;
5013 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5014 type != INTR_TYPE_EXT_INTR &&
5015 type != INTR_TYPE_NMI_INTR))
5016 skip_emulated_instruction(vcpu);
5018 if (kvm_task_switch(vcpu, tss_selector,
5019 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5020 has_error_code, error_code) == EMULATE_FAIL) {
5021 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5022 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5023 vcpu->run->internal.ndata = 0;
5027 /* clear all local breakpoint enable flags */
5028 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5031 * TODO: What about debug traps on tss switch?
5032 * Are we supposed to inject them and update dr6?
5038 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5040 unsigned long exit_qualification;
5045 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5047 gla_validity = (exit_qualification >> 7) & 0x3;
5048 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5049 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5050 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5051 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5052 vmcs_readl(GUEST_LINEAR_ADDRESS));
5053 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5054 (long unsigned int)exit_qualification);
5055 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5056 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5060 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5061 trace_kvm_page_fault(gpa, exit_qualification);
5063 /* It is a write fault? */
5064 error_code = exit_qualification & (1U << 1);
5065 /* ept page table is present? */
5066 error_code |= (exit_qualification >> 3) & 0x1;
5068 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5071 static u64 ept_rsvd_mask(u64 spte, int level)
5076 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5077 mask |= (1ULL << i);
5080 /* bits 7:3 reserved */
5082 else if (level == 2) {
5083 if (spte & (1ULL << 7))
5084 /* 2MB ref, bits 20:12 reserved */
5087 /* bits 6:3 reserved */
5094 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5097 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5099 /* 010b (write-only) */
5100 WARN_ON((spte & 0x7) == 0x2);
5102 /* 110b (write/execute) */
5103 WARN_ON((spte & 0x7) == 0x6);
5105 /* 100b (execute-only) and value not supported by logical processor */
5106 if (!cpu_has_vmx_ept_execute_only())
5107 WARN_ON((spte & 0x7) == 0x4);
5111 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5113 if (rsvd_bits != 0) {
5114 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5115 __func__, rsvd_bits);
5119 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5120 u64 ept_mem_type = (spte & 0x38) >> 3;
5122 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5123 ept_mem_type == 7) {
5124 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5125 __func__, ept_mem_type);
5132 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5135 int nr_sptes, i, ret;
5138 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5140 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5141 if (likely(ret == 1))
5142 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5147 /* It is the real ept misconfig */
5148 printk(KERN_ERR "EPT: Misconfiguration.\n");
5149 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5151 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5153 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5154 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5156 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5157 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5162 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5164 u32 cpu_based_vm_exec_control;
5166 /* clear pending NMI */
5167 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5168 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5169 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5170 ++vcpu->stat.nmi_window_exits;
5171 kvm_make_request(KVM_REQ_EVENT, vcpu);
5176 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5178 struct vcpu_vmx *vmx = to_vmx(vcpu);
5179 enum emulation_result err = EMULATE_DONE;
5182 bool intr_window_requested;
5183 unsigned count = 130;
5185 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5186 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5188 while (!guest_state_valid(vcpu) && count-- != 0) {
5189 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5190 return handle_interrupt_window(&vmx->vcpu);
5192 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5195 err = emulate_instruction(vcpu, 0);
5197 if (err == EMULATE_DO_MMIO) {
5202 if (err != EMULATE_DONE) {
5203 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5204 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5205 vcpu->run->internal.ndata = 0;
5209 if (signal_pending(current))
5215 vmx->emulation_required = emulation_required(vcpu);
5221 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5222 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5224 static int handle_pause(struct kvm_vcpu *vcpu)
5226 skip_emulated_instruction(vcpu);
5227 kvm_vcpu_on_spin(vcpu);
5232 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5234 kvm_queue_exception(vcpu, UD_VECTOR);
5239 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5240 * We could reuse a single VMCS for all the L2 guests, but we also want the
5241 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5242 * allows keeping them loaded on the processor, and in the future will allow
5243 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5244 * every entry if they never change.
5245 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5246 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5248 * The following functions allocate and free a vmcs02 in this pool.
5251 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5252 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5254 struct vmcs02_list *item;
5255 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5256 if (item->vmptr == vmx->nested.current_vmptr) {
5257 list_move(&item->list, &vmx->nested.vmcs02_pool);
5258 return &item->vmcs02;
5261 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5262 /* Recycle the least recently used VMCS. */
5263 item = list_entry(vmx->nested.vmcs02_pool.prev,
5264 struct vmcs02_list, list);
5265 item->vmptr = vmx->nested.current_vmptr;
5266 list_move(&item->list, &vmx->nested.vmcs02_pool);
5267 return &item->vmcs02;
5270 /* Create a new VMCS */
5271 item = (struct vmcs02_list *)
5272 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5275 item->vmcs02.vmcs = alloc_vmcs();
5276 if (!item->vmcs02.vmcs) {
5280 loaded_vmcs_init(&item->vmcs02);
5281 item->vmptr = vmx->nested.current_vmptr;
5282 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5283 vmx->nested.vmcs02_num++;
5284 return &item->vmcs02;
5287 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5288 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5290 struct vmcs02_list *item;
5291 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5292 if (item->vmptr == vmptr) {
5293 free_loaded_vmcs(&item->vmcs02);
5294 list_del(&item->list);
5296 vmx->nested.vmcs02_num--;
5302 * Free all VMCSs saved for this vcpu, except the one pointed by
5303 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5304 * currently used, if running L2), and vmcs01 when running L2.
5306 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5308 struct vmcs02_list *item, *n;
5309 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5310 if (vmx->loaded_vmcs != &item->vmcs02)
5311 free_loaded_vmcs(&item->vmcs02);
5312 list_del(&item->list);
5315 vmx->nested.vmcs02_num = 0;
5317 if (vmx->loaded_vmcs != &vmx->vmcs01)
5318 free_loaded_vmcs(&vmx->vmcs01);
5322 * Emulate the VMXON instruction.
5323 * Currently, we just remember that VMX is active, and do not save or even
5324 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5325 * do not currently need to store anything in that guest-allocated memory
5326 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5327 * argument is different from the VMXON pointer (which the spec says they do).
5329 static int handle_vmon(struct kvm_vcpu *vcpu)
5331 struct kvm_segment cs;
5332 struct vcpu_vmx *vmx = to_vmx(vcpu);
5334 /* The Intel VMX Instruction Reference lists a bunch of bits that
5335 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5336 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5337 * Otherwise, we should fail with #UD. We test these now:
5339 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5340 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5341 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5342 kvm_queue_exception(vcpu, UD_VECTOR);
5346 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5347 if (is_long_mode(vcpu) && !cs.l) {
5348 kvm_queue_exception(vcpu, UD_VECTOR);
5352 if (vmx_get_cpl(vcpu)) {
5353 kvm_inject_gp(vcpu, 0);
5357 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5358 vmx->nested.vmcs02_num = 0;
5360 vmx->nested.vmxon = true;
5362 skip_emulated_instruction(vcpu);
5367 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5368 * for running VMX instructions (except VMXON, whose prerequisites are
5369 * slightly different). It also specifies what exception to inject otherwise.
5371 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5373 struct kvm_segment cs;
5374 struct vcpu_vmx *vmx = to_vmx(vcpu);
5376 if (!vmx->nested.vmxon) {
5377 kvm_queue_exception(vcpu, UD_VECTOR);
5381 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5382 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5383 (is_long_mode(vcpu) && !cs.l)) {
5384 kvm_queue_exception(vcpu, UD_VECTOR);
5388 if (vmx_get_cpl(vcpu)) {
5389 kvm_inject_gp(vcpu, 0);
5397 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5398 * just stops using VMX.
5400 static void free_nested(struct vcpu_vmx *vmx)
5402 if (!vmx->nested.vmxon)
5404 vmx->nested.vmxon = false;
5405 if (vmx->nested.current_vmptr != -1ull) {
5406 kunmap(vmx->nested.current_vmcs12_page);
5407 nested_release_page(vmx->nested.current_vmcs12_page);
5408 vmx->nested.current_vmptr = -1ull;
5409 vmx->nested.current_vmcs12 = NULL;
5411 /* Unpin physical memory we referred to in current vmcs02 */
5412 if (vmx->nested.apic_access_page) {
5413 nested_release_page(vmx->nested.apic_access_page);
5414 vmx->nested.apic_access_page = 0;
5417 nested_free_all_saved_vmcss(vmx);
5420 /* Emulate the VMXOFF instruction */
5421 static int handle_vmoff(struct kvm_vcpu *vcpu)
5423 if (!nested_vmx_check_permission(vcpu))
5425 free_nested(to_vmx(vcpu));
5426 skip_emulated_instruction(vcpu);
5431 * Decode the memory-address operand of a vmx instruction, as recorded on an
5432 * exit caused by such an instruction (run by a guest hypervisor).
5433 * On success, returns 0. When the operand is invalid, returns 1 and throws
5436 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5437 unsigned long exit_qualification,
5438 u32 vmx_instruction_info, gva_t *ret)
5441 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5442 * Execution", on an exit, vmx_instruction_info holds most of the
5443 * addressing components of the operand. Only the displacement part
5444 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5445 * For how an actual address is calculated from all these components,
5446 * refer to Vol. 1, "Operand Addressing".
5448 int scaling = vmx_instruction_info & 3;
5449 int addr_size = (vmx_instruction_info >> 7) & 7;
5450 bool is_reg = vmx_instruction_info & (1u << 10);
5451 int seg_reg = (vmx_instruction_info >> 15) & 7;
5452 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5453 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5454 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5455 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5458 kvm_queue_exception(vcpu, UD_VECTOR);
5462 /* Addr = segment_base + offset */
5463 /* offset = base + [index * scale] + displacement */
5464 *ret = vmx_get_segment_base(vcpu, seg_reg);
5466 *ret += kvm_register_read(vcpu, base_reg);
5468 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5469 *ret += exit_qualification; /* holds the displacement */
5471 if (addr_size == 1) /* 32 bit */
5475 * TODO: throw #GP (and return 1) in various cases that the VM*
5476 * instructions require it - e.g., offset beyond segment limit,
5477 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5478 * address, and so on. Currently these are not checked.
5484 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5485 * set the success or error code of an emulated VMX instruction, as specified
5486 * by Vol 2B, VMX Instruction Reference, "Conventions".
5488 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5490 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5491 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5492 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5495 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5497 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5498 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5499 X86_EFLAGS_SF | X86_EFLAGS_OF))
5503 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5504 u32 vm_instruction_error)
5506 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5508 * failValid writes the error number to the current VMCS, which
5509 * can't be done there isn't a current VMCS.
5511 nested_vmx_failInvalid(vcpu);
5514 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5515 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5516 X86_EFLAGS_SF | X86_EFLAGS_OF))
5518 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5521 /* Emulate the VMCLEAR instruction */
5522 static int handle_vmclear(struct kvm_vcpu *vcpu)
5524 struct vcpu_vmx *vmx = to_vmx(vcpu);
5527 struct vmcs12 *vmcs12;
5529 struct x86_exception e;
5531 if (!nested_vmx_check_permission(vcpu))
5534 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5535 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5538 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5539 sizeof(vmptr), &e)) {
5540 kvm_inject_page_fault(vcpu, &e);
5544 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5545 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5546 skip_emulated_instruction(vcpu);
5550 if (vmptr == vmx->nested.current_vmptr) {
5551 kunmap(vmx->nested.current_vmcs12_page);
5552 nested_release_page(vmx->nested.current_vmcs12_page);
5553 vmx->nested.current_vmptr = -1ull;
5554 vmx->nested.current_vmcs12 = NULL;
5557 page = nested_get_page(vcpu, vmptr);
5560 * For accurate processor emulation, VMCLEAR beyond available
5561 * physical memory should do nothing at all. However, it is
5562 * possible that a nested vmx bug, not a guest hypervisor bug,
5563 * resulted in this case, so let's shut down before doing any
5566 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5569 vmcs12 = kmap(page);
5570 vmcs12->launch_state = 0;
5572 nested_release_page(page);
5574 nested_free_vmcs02(vmx, vmptr);
5576 skip_emulated_instruction(vcpu);
5577 nested_vmx_succeed(vcpu);
5581 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5583 /* Emulate the VMLAUNCH instruction */
5584 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5586 return nested_vmx_run(vcpu, true);
5589 /* Emulate the VMRESUME instruction */
5590 static int handle_vmresume(struct kvm_vcpu *vcpu)
5593 return nested_vmx_run(vcpu, false);
5596 enum vmcs_field_type {
5597 VMCS_FIELD_TYPE_U16 = 0,
5598 VMCS_FIELD_TYPE_U64 = 1,
5599 VMCS_FIELD_TYPE_U32 = 2,
5600 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5603 static inline int vmcs_field_type(unsigned long field)
5605 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5606 return VMCS_FIELD_TYPE_U32;
5607 return (field >> 13) & 0x3 ;
5610 static inline int vmcs_field_readonly(unsigned long field)
5612 return (((field >> 10) & 0x3) == 1);
5616 * Read a vmcs12 field. Since these can have varying lengths and we return
5617 * one type, we chose the biggest type (u64) and zero-extend the return value
5618 * to that size. Note that the caller, handle_vmread, might need to use only
5619 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5620 * 64-bit fields are to be returned).
5622 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5623 unsigned long field, u64 *ret)
5625 short offset = vmcs_field_to_offset(field);
5631 p = ((char *)(get_vmcs12(vcpu))) + offset;
5633 switch (vmcs_field_type(field)) {
5634 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5635 *ret = *((natural_width *)p);
5637 case VMCS_FIELD_TYPE_U16:
5640 case VMCS_FIELD_TYPE_U32:
5643 case VMCS_FIELD_TYPE_U64:
5647 return 0; /* can never happen. */
5652 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5653 * used before) all generate the same failure when it is missing.
5655 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5657 struct vcpu_vmx *vmx = to_vmx(vcpu);
5658 if (vmx->nested.current_vmptr == -1ull) {
5659 nested_vmx_failInvalid(vcpu);
5660 skip_emulated_instruction(vcpu);
5666 static int handle_vmread(struct kvm_vcpu *vcpu)
5668 unsigned long field;
5670 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5671 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5674 if (!nested_vmx_check_permission(vcpu) ||
5675 !nested_vmx_check_vmcs12(vcpu))
5678 /* Decode instruction info and find the field to read */
5679 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5680 /* Read the field, zero-extended to a u64 field_value */
5681 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5682 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5683 skip_emulated_instruction(vcpu);
5687 * Now copy part of this value to register or memory, as requested.
5688 * Note that the number of bits actually copied is 32 or 64 depending
5689 * on the guest's mode (32 or 64 bit), not on the given field's length.
5691 if (vmx_instruction_info & (1u << 10)) {
5692 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5695 if (get_vmx_mem_address(vcpu, exit_qualification,
5696 vmx_instruction_info, &gva))
5698 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5699 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5700 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5703 nested_vmx_succeed(vcpu);
5704 skip_emulated_instruction(vcpu);
5709 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5711 unsigned long field;
5713 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5714 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5717 /* The value to write might be 32 or 64 bits, depending on L1's long
5718 * mode, and eventually we need to write that into a field of several
5719 * possible lengths. The code below first zero-extends the value to 64
5720 * bit (field_value), and then copies only the approriate number of
5721 * bits into the vmcs12 field.
5723 u64 field_value = 0;
5724 struct x86_exception e;
5726 if (!nested_vmx_check_permission(vcpu) ||
5727 !nested_vmx_check_vmcs12(vcpu))
5730 if (vmx_instruction_info & (1u << 10))
5731 field_value = kvm_register_read(vcpu,
5732 (((vmx_instruction_info) >> 3) & 0xf));
5734 if (get_vmx_mem_address(vcpu, exit_qualification,
5735 vmx_instruction_info, &gva))
5737 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5738 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5739 kvm_inject_page_fault(vcpu, &e);
5745 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5746 if (vmcs_field_readonly(field)) {
5747 nested_vmx_failValid(vcpu,
5748 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5749 skip_emulated_instruction(vcpu);
5753 offset = vmcs_field_to_offset(field);
5755 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5756 skip_emulated_instruction(vcpu);
5759 p = ((char *) get_vmcs12(vcpu)) + offset;
5761 switch (vmcs_field_type(field)) {
5762 case VMCS_FIELD_TYPE_U16:
5763 *(u16 *)p = field_value;
5765 case VMCS_FIELD_TYPE_U32:
5766 *(u32 *)p = field_value;
5768 case VMCS_FIELD_TYPE_U64:
5769 *(u64 *)p = field_value;
5771 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5772 *(natural_width *)p = field_value;
5775 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5776 skip_emulated_instruction(vcpu);
5780 nested_vmx_succeed(vcpu);
5781 skip_emulated_instruction(vcpu);
5785 /* Emulate the VMPTRLD instruction */
5786 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5788 struct vcpu_vmx *vmx = to_vmx(vcpu);
5791 struct x86_exception e;
5793 if (!nested_vmx_check_permission(vcpu))
5796 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5797 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5800 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5801 sizeof(vmptr), &e)) {
5802 kvm_inject_page_fault(vcpu, &e);
5806 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5807 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5808 skip_emulated_instruction(vcpu);
5812 if (vmx->nested.current_vmptr != vmptr) {
5813 struct vmcs12 *new_vmcs12;
5815 page = nested_get_page(vcpu, vmptr);
5817 nested_vmx_failInvalid(vcpu);
5818 skip_emulated_instruction(vcpu);
5821 new_vmcs12 = kmap(page);
5822 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5824 nested_release_page_clean(page);
5825 nested_vmx_failValid(vcpu,
5826 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5827 skip_emulated_instruction(vcpu);
5830 if (vmx->nested.current_vmptr != -1ull) {
5831 kunmap(vmx->nested.current_vmcs12_page);
5832 nested_release_page(vmx->nested.current_vmcs12_page);
5835 vmx->nested.current_vmptr = vmptr;
5836 vmx->nested.current_vmcs12 = new_vmcs12;
5837 vmx->nested.current_vmcs12_page = page;
5840 nested_vmx_succeed(vcpu);
5841 skip_emulated_instruction(vcpu);
5845 /* Emulate the VMPTRST instruction */
5846 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5848 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5849 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5851 struct x86_exception e;
5853 if (!nested_vmx_check_permission(vcpu))
5856 if (get_vmx_mem_address(vcpu, exit_qualification,
5857 vmx_instruction_info, &vmcs_gva))
5859 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5860 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5861 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5863 kvm_inject_page_fault(vcpu, &e);
5866 nested_vmx_succeed(vcpu);
5867 skip_emulated_instruction(vcpu);
5872 * The exit handlers return 1 if the exit was handled fully and guest execution
5873 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5874 * to be done to userspace and return 0.
5876 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5877 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5878 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5879 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5880 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5881 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5882 [EXIT_REASON_CR_ACCESS] = handle_cr,
5883 [EXIT_REASON_DR_ACCESS] = handle_dr,
5884 [EXIT_REASON_CPUID] = handle_cpuid,
5885 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5886 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5887 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5888 [EXIT_REASON_HLT] = handle_halt,
5889 [EXIT_REASON_INVD] = handle_invd,
5890 [EXIT_REASON_INVLPG] = handle_invlpg,
5891 [EXIT_REASON_RDPMC] = handle_rdpmc,
5892 [EXIT_REASON_VMCALL] = handle_vmcall,
5893 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5894 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5895 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5896 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5897 [EXIT_REASON_VMREAD] = handle_vmread,
5898 [EXIT_REASON_VMRESUME] = handle_vmresume,
5899 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5900 [EXIT_REASON_VMOFF] = handle_vmoff,
5901 [EXIT_REASON_VMON] = handle_vmon,
5902 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5903 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5904 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5905 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5906 [EXIT_REASON_WBINVD] = handle_wbinvd,
5907 [EXIT_REASON_XSETBV] = handle_xsetbv,
5908 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5909 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5910 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5911 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5912 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5913 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5914 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5917 static const int kvm_vmx_max_exit_handlers =
5918 ARRAY_SIZE(kvm_vmx_exit_handlers);
5920 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5921 struct vmcs12 *vmcs12)
5923 unsigned long exit_qualification;
5924 gpa_t bitmap, last_bitmap;
5929 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
5932 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5935 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5937 port = exit_qualification >> 16;
5938 size = (exit_qualification & 7) + 1;
5940 last_bitmap = (gpa_t)-1;
5945 bitmap = vmcs12->io_bitmap_a;
5946 else if (port < 0x10000)
5947 bitmap = vmcs12->io_bitmap_b;
5950 bitmap += (port & 0x7fff) / 8;
5952 if (last_bitmap != bitmap)
5953 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
5955 if (b & (1 << (port & 7)))
5960 last_bitmap = bitmap;
5967 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5968 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5969 * disinterest in the current event (read or write a specific MSR) by using an
5970 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5972 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5973 struct vmcs12 *vmcs12, u32 exit_reason)
5975 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5978 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
5982 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5983 * for the four combinations of read/write and low/high MSR numbers.
5984 * First we need to figure out which of the four to use:
5986 bitmap = vmcs12->msr_bitmap;
5987 if (exit_reason == EXIT_REASON_MSR_WRITE)
5989 if (msr_index >= 0xc0000000) {
5990 msr_index -= 0xc0000000;
5994 /* Then read the msr_index'th bit from this bitmap: */
5995 if (msr_index < 1024*8) {
5997 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
5999 return 1 & (b >> (msr_index & 7));
6001 return 1; /* let L1 handle the wrong parameter */
6005 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6006 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6007 * intercept (via guest_host_mask etc.) the current event.
6009 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6010 struct vmcs12 *vmcs12)
6012 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6013 int cr = exit_qualification & 15;
6014 int reg = (exit_qualification >> 8) & 15;
6015 unsigned long val = kvm_register_read(vcpu, reg);
6017 switch ((exit_qualification >> 4) & 3) {
6018 case 0: /* mov to cr */
6021 if (vmcs12->cr0_guest_host_mask &
6022 (val ^ vmcs12->cr0_read_shadow))
6026 if ((vmcs12->cr3_target_count >= 1 &&
6027 vmcs12->cr3_target_value0 == val) ||
6028 (vmcs12->cr3_target_count >= 2 &&
6029 vmcs12->cr3_target_value1 == val) ||
6030 (vmcs12->cr3_target_count >= 3 &&
6031 vmcs12->cr3_target_value2 == val) ||
6032 (vmcs12->cr3_target_count >= 4 &&
6033 vmcs12->cr3_target_value3 == val))
6035 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6039 if (vmcs12->cr4_guest_host_mask &
6040 (vmcs12->cr4_read_shadow ^ val))
6044 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6050 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6051 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6054 case 1: /* mov from cr */
6057 if (vmcs12->cpu_based_vm_exec_control &
6058 CPU_BASED_CR3_STORE_EXITING)
6062 if (vmcs12->cpu_based_vm_exec_control &
6063 CPU_BASED_CR8_STORE_EXITING)
6070 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6071 * cr0. Other attempted changes are ignored, with no exit.
6073 if (vmcs12->cr0_guest_host_mask & 0xe &
6074 (val ^ vmcs12->cr0_read_shadow))
6076 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6077 !(vmcs12->cr0_read_shadow & 0x1) &&
6086 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6087 * should handle it ourselves in L0 (and then continue L2). Only call this
6088 * when in is_guest_mode (L2).
6090 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6092 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6093 struct vcpu_vmx *vmx = to_vmx(vcpu);
6094 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6095 u32 exit_reason = vmx->exit_reason;
6097 if (vmx->nested.nested_run_pending)
6100 if (unlikely(vmx->fail)) {
6101 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6102 vmcs_read32(VM_INSTRUCTION_ERROR));
6106 switch (exit_reason) {
6107 case EXIT_REASON_EXCEPTION_NMI:
6108 if (!is_exception(intr_info))
6110 else if (is_page_fault(intr_info))
6112 return vmcs12->exception_bitmap &
6113 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6114 case EXIT_REASON_EXTERNAL_INTERRUPT:
6116 case EXIT_REASON_TRIPLE_FAULT:
6118 case EXIT_REASON_PENDING_INTERRUPT:
6119 case EXIT_REASON_NMI_WINDOW:
6121 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
6122 * (aka Interrupt Window Exiting) only when L1 turned it on,
6123 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
6124 * Same for NMI Window Exiting.
6127 case EXIT_REASON_TASK_SWITCH:
6129 case EXIT_REASON_CPUID:
6131 case EXIT_REASON_HLT:
6132 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6133 case EXIT_REASON_INVD:
6135 case EXIT_REASON_INVLPG:
6136 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6137 case EXIT_REASON_RDPMC:
6138 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6139 case EXIT_REASON_RDTSC:
6140 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6141 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6142 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6143 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6144 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6145 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6147 * VMX instructions trap unconditionally. This allows L1 to
6148 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6151 case EXIT_REASON_CR_ACCESS:
6152 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6153 case EXIT_REASON_DR_ACCESS:
6154 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6155 case EXIT_REASON_IO_INSTRUCTION:
6156 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6157 case EXIT_REASON_MSR_READ:
6158 case EXIT_REASON_MSR_WRITE:
6159 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6160 case EXIT_REASON_INVALID_STATE:
6162 case EXIT_REASON_MWAIT_INSTRUCTION:
6163 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6164 case EXIT_REASON_MONITOR_INSTRUCTION:
6165 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6166 case EXIT_REASON_PAUSE_INSTRUCTION:
6167 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6168 nested_cpu_has2(vmcs12,
6169 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6170 case EXIT_REASON_MCE_DURING_VMENTRY:
6172 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6174 case EXIT_REASON_APIC_ACCESS:
6175 return nested_cpu_has2(vmcs12,
6176 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6177 case EXIT_REASON_EPT_VIOLATION:
6178 case EXIT_REASON_EPT_MISCONFIG:
6180 case EXIT_REASON_WBINVD:
6181 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6182 case EXIT_REASON_XSETBV:
6189 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6191 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6192 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6196 * The guest has exited. See if we can fix it or if we need userspace
6199 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6201 struct vcpu_vmx *vmx = to_vmx(vcpu);
6202 u32 exit_reason = vmx->exit_reason;
6203 u32 vectoring_info = vmx->idt_vectoring_info;
6205 /* If guest state is invalid, start emulating */
6206 if (vmx->emulation_required)
6207 return handle_invalid_guest_state(vcpu);
6210 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6211 * we did not inject a still-pending event to L1 now because of
6212 * nested_run_pending, we need to re-enable this bit.
6214 if (vmx->nested.nested_run_pending)
6215 kvm_make_request(KVM_REQ_EVENT, vcpu);
6217 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6218 exit_reason == EXIT_REASON_VMRESUME))
6219 vmx->nested.nested_run_pending = 1;
6221 vmx->nested.nested_run_pending = 0;
6223 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6224 nested_vmx_vmexit(vcpu);
6228 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6229 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6230 vcpu->run->fail_entry.hardware_entry_failure_reason
6235 if (unlikely(vmx->fail)) {
6236 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6237 vcpu->run->fail_entry.hardware_entry_failure_reason
6238 = vmcs_read32(VM_INSTRUCTION_ERROR);
6244 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6245 * delivery event since it indicates guest is accessing MMIO.
6246 * The vm-exit can be triggered again after return to guest that
6247 * will cause infinite loop.
6249 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6250 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6251 exit_reason != EXIT_REASON_EPT_VIOLATION &&
6252 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6253 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6254 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6255 vcpu->run->internal.ndata = 2;
6256 vcpu->run->internal.data[0] = vectoring_info;
6257 vcpu->run->internal.data[1] = exit_reason;
6261 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6262 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6263 get_vmcs12(vcpu), vcpu)))) {
6264 if (vmx_interrupt_allowed(vcpu)) {
6265 vmx->soft_vnmi_blocked = 0;
6266 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6267 vcpu->arch.nmi_pending) {
6269 * This CPU don't support us in finding the end of an
6270 * NMI-blocked window if the guest runs with IRQs
6271 * disabled. So we pull the trigger after 1 s of
6272 * futile waiting, but inform the user about this.
6274 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6275 "state on VCPU %d after 1 s timeout\n",
6276 __func__, vcpu->vcpu_id);
6277 vmx->soft_vnmi_blocked = 0;
6281 if (exit_reason < kvm_vmx_max_exit_handlers
6282 && kvm_vmx_exit_handlers[exit_reason])
6283 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6285 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6286 vcpu->run->hw.hardware_exit_reason = exit_reason;
6291 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6293 if (irr == -1 || tpr < irr) {
6294 vmcs_write32(TPR_THRESHOLD, 0);
6298 vmcs_write32(TPR_THRESHOLD, irr);
6301 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6303 u32 sec_exec_control;
6306 * There is not point to enable virtualize x2apic without enable
6309 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6310 !vmx_vm_has_apicv(vcpu->kvm))
6313 if (!vm_need_tpr_shadow(vcpu->kvm))
6316 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6319 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6320 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6322 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6323 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6325 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6327 vmx_set_msr_bitmap(vcpu);
6330 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6335 if (!vmx_vm_has_apicv(kvm))
6341 status = vmcs_read16(GUEST_INTR_STATUS);
6346 vmcs_write16(GUEST_INTR_STATUS, status);
6350 static void vmx_set_rvi(int vector)
6355 status = vmcs_read16(GUEST_INTR_STATUS);
6356 old = (u8)status & 0xff;
6357 if ((u8)vector != old) {
6359 status |= (u8)vector;
6360 vmcs_write16(GUEST_INTR_STATUS, status);
6364 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6369 vmx_set_rvi(max_irr);
6372 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6374 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6375 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6376 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6377 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6380 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6384 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6385 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6388 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6389 exit_intr_info = vmx->exit_intr_info;
6391 /* Handle machine checks before interrupts are enabled */
6392 if (is_machine_check(exit_intr_info))
6393 kvm_machine_check();
6395 /* We need to handle NMIs before interrupts are enabled */
6396 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6397 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6398 kvm_before_handle_nmi(&vmx->vcpu);
6400 kvm_after_handle_nmi(&vmx->vcpu);
6404 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6409 bool idtv_info_valid;
6411 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6413 if (cpu_has_virtual_nmis()) {
6414 if (vmx->nmi_known_unmasked)
6417 * Can't use vmx->exit_intr_info since we're not sure what
6418 * the exit reason is.
6420 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6421 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6422 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6424 * SDM 3: 27.7.1.2 (September 2008)
6425 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6426 * a guest IRET fault.
6427 * SDM 3: 23.2.2 (September 2008)
6428 * Bit 12 is undefined in any of the following cases:
6429 * If the VM exit sets the valid bit in the IDT-vectoring
6430 * information field.
6431 * If the VM exit is due to a double fault.
6433 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6434 vector != DF_VECTOR && !idtv_info_valid)
6435 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6436 GUEST_INTR_STATE_NMI);
6438 vmx->nmi_known_unmasked =
6439 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6440 & GUEST_INTR_STATE_NMI);
6441 } else if (unlikely(vmx->soft_vnmi_blocked))
6442 vmx->vnmi_blocked_time +=
6443 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6446 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6447 u32 idt_vectoring_info,
6448 int instr_len_field,
6449 int error_code_field)
6453 bool idtv_info_valid;
6455 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6457 vcpu->arch.nmi_injected = false;
6458 kvm_clear_exception_queue(vcpu);
6459 kvm_clear_interrupt_queue(vcpu);
6461 if (!idtv_info_valid)
6464 kvm_make_request(KVM_REQ_EVENT, vcpu);
6466 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6467 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6470 case INTR_TYPE_NMI_INTR:
6471 vcpu->arch.nmi_injected = true;
6473 * SDM 3: 27.7.1.2 (September 2008)
6474 * Clear bit "block by NMI" before VM entry if a NMI
6477 vmx_set_nmi_mask(vcpu, false);
6479 case INTR_TYPE_SOFT_EXCEPTION:
6480 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6482 case INTR_TYPE_HARD_EXCEPTION:
6483 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6484 u32 err = vmcs_read32(error_code_field);
6485 kvm_queue_exception_e(vcpu, vector, err);
6487 kvm_queue_exception(vcpu, vector);
6489 case INTR_TYPE_SOFT_INTR:
6490 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6492 case INTR_TYPE_EXT_INTR:
6493 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6500 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6502 if (is_guest_mode(&vmx->vcpu))
6504 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6505 VM_EXIT_INSTRUCTION_LEN,
6506 IDT_VECTORING_ERROR_CODE);
6509 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6511 if (is_guest_mode(vcpu))
6513 __vmx_complete_interrupts(vcpu,
6514 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6515 VM_ENTRY_INSTRUCTION_LEN,
6516 VM_ENTRY_EXCEPTION_ERROR_CODE);
6518 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6521 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6524 struct perf_guest_switch_msr *msrs;
6526 msrs = perf_guest_get_msrs(&nr_msrs);
6531 for (i = 0; i < nr_msrs; i++)
6532 if (msrs[i].host == msrs[i].guest)
6533 clear_atomic_switch_msr(vmx, msrs[i].msr);
6535 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6539 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6541 struct vcpu_vmx *vmx = to_vmx(vcpu);
6542 unsigned long debugctlmsr;
6544 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6545 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6546 if (vmcs12->idt_vectoring_info_field &
6547 VECTORING_INFO_VALID_MASK) {
6548 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6549 vmcs12->idt_vectoring_info_field);
6550 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6551 vmcs12->vm_exit_instruction_len);
6552 if (vmcs12->idt_vectoring_info_field &
6553 VECTORING_INFO_DELIVER_CODE_MASK)
6554 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6555 vmcs12->idt_vectoring_error_code);
6559 /* Record the guest's net vcpu time for enforced NMI injections. */
6560 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6561 vmx->entry_time = ktime_get();
6563 /* Don't enter VMX if guest state is invalid, let the exit handler
6564 start emulation until we arrive back to a valid state */
6565 if (vmx->emulation_required)
6568 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6569 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6570 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6571 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6573 /* When single-stepping over STI and MOV SS, we must clear the
6574 * corresponding interruptibility bits in the guest state. Otherwise
6575 * vmentry fails as it then expects bit 14 (BS) in pending debug
6576 * exceptions being set, but that's not correct for the guest debugging
6578 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6579 vmx_set_interrupt_shadow(vcpu, 0);
6581 atomic_switch_perf_msrs(vmx);
6582 debugctlmsr = get_debugctlmsr();
6584 vmx->__launched = vmx->loaded_vmcs->launched;
6586 /* Store host registers */
6587 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6588 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6589 "push %%" _ASM_CX " \n\t"
6590 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6592 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6593 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6595 /* Reload cr2 if changed */
6596 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6597 "mov %%cr2, %%" _ASM_DX " \n\t"
6598 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6600 "mov %%" _ASM_AX", %%cr2 \n\t"
6602 /* Check if vmlaunch of vmresume is needed */
6603 "cmpl $0, %c[launched](%0) \n\t"
6604 /* Load guest registers. Don't clobber flags. */
6605 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6606 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6607 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6608 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6609 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6610 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
6611 #ifdef CONFIG_X86_64
6612 "mov %c[r8](%0), %%r8 \n\t"
6613 "mov %c[r9](%0), %%r9 \n\t"
6614 "mov %c[r10](%0), %%r10 \n\t"
6615 "mov %c[r11](%0), %%r11 \n\t"
6616 "mov %c[r12](%0), %%r12 \n\t"
6617 "mov %c[r13](%0), %%r13 \n\t"
6618 "mov %c[r14](%0), %%r14 \n\t"
6619 "mov %c[r15](%0), %%r15 \n\t"
6621 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
6623 /* Enter guest mode */
6625 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6627 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6629 /* Save guest registers, load host registers, keep flags */
6630 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
6632 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6633 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6634 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6635 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6636 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6637 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6638 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
6639 #ifdef CONFIG_X86_64
6640 "mov %%r8, %c[r8](%0) \n\t"
6641 "mov %%r9, %c[r9](%0) \n\t"
6642 "mov %%r10, %c[r10](%0) \n\t"
6643 "mov %%r11, %c[r11](%0) \n\t"
6644 "mov %%r12, %c[r12](%0) \n\t"
6645 "mov %%r13, %c[r13](%0) \n\t"
6646 "mov %%r14, %c[r14](%0) \n\t"
6647 "mov %%r15, %c[r15](%0) \n\t"
6649 "mov %%cr2, %%" _ASM_AX " \n\t"
6650 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
6652 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
6653 "setbe %c[fail](%0) \n\t"
6654 ".pushsection .rodata \n\t"
6655 ".global vmx_return \n\t"
6656 "vmx_return: " _ASM_PTR " 2b \n\t"
6658 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6659 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6660 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6661 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6662 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6663 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6664 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6665 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6666 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6667 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6668 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6669 #ifdef CONFIG_X86_64
6670 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6671 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6672 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6673 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6674 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6675 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6676 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6677 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6679 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6680 [wordsize]"i"(sizeof(ulong))
6682 #ifdef CONFIG_X86_64
6683 , "rax", "rbx", "rdi", "rsi"
6684 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6686 , "eax", "ebx", "edi", "esi"
6690 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6692 update_debugctlmsr(debugctlmsr);
6694 #ifndef CONFIG_X86_64
6696 * The sysexit path does not restore ds/es, so we must set them to
6697 * a reasonable value ourselves.
6699 * We can't defer this to vmx_load_host_state() since that function
6700 * may be executed in interrupt context, which saves and restore segments
6701 * around it, nullifying its effect.
6703 loadsegment(ds, __USER_DS);
6704 loadsegment(es, __USER_DS);
6707 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6708 | (1 << VCPU_EXREG_RFLAGS)
6709 | (1 << VCPU_EXREG_CPL)
6710 | (1 << VCPU_EXREG_PDPTR)
6711 | (1 << VCPU_EXREG_SEGMENTS)
6712 | (1 << VCPU_EXREG_CR3));
6713 vcpu->arch.regs_dirty = 0;
6715 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6717 if (is_guest_mode(vcpu)) {
6718 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6719 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6720 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6721 vmcs12->idt_vectoring_error_code =
6722 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6723 vmcs12->vm_exit_instruction_len =
6724 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6728 vmx->loaded_vmcs->launched = 1;
6730 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6731 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6733 vmx_complete_atomic_exit(vmx);
6734 vmx_recover_nmi_blocking(vmx);
6735 vmx_complete_interrupts(vmx);
6738 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6740 struct vcpu_vmx *vmx = to_vmx(vcpu);
6744 free_loaded_vmcs(vmx->loaded_vmcs);
6745 kfree(vmx->guest_msrs);
6746 kvm_vcpu_uninit(vcpu);
6747 kmem_cache_free(kvm_vcpu_cache, vmx);
6750 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6753 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6757 return ERR_PTR(-ENOMEM);
6761 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6765 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6767 if (!vmx->guest_msrs) {
6771 vmx->loaded_vmcs = &vmx->vmcs01;
6772 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6773 if (!vmx->loaded_vmcs->vmcs)
6776 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6777 loaded_vmcs_init(vmx->loaded_vmcs);
6782 vmx_vcpu_load(&vmx->vcpu, cpu);
6783 vmx->vcpu.cpu = cpu;
6784 err = vmx_vcpu_setup(vmx);
6785 vmx_vcpu_put(&vmx->vcpu);
6789 if (vm_need_virtualize_apic_accesses(kvm))
6790 err = alloc_apic_access_page(kvm);
6795 if (!kvm->arch.ept_identity_map_addr)
6796 kvm->arch.ept_identity_map_addr =
6797 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6799 if (alloc_identity_pagetable(kvm) != 0)
6801 if (!init_rmode_identity_map(kvm))
6805 vmx->nested.current_vmptr = -1ull;
6806 vmx->nested.current_vmcs12 = NULL;
6811 free_loaded_vmcs(vmx->loaded_vmcs);
6813 kfree(vmx->guest_msrs);
6815 kvm_vcpu_uninit(&vmx->vcpu);
6818 kmem_cache_free(kvm_vcpu_cache, vmx);
6819 return ERR_PTR(err);
6822 static void __init vmx_check_processor_compat(void *rtn)
6824 struct vmcs_config vmcs_conf;
6827 if (setup_vmcs_config(&vmcs_conf) < 0)
6829 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6830 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6831 smp_processor_id());
6836 static int get_ept_level(void)
6838 return VMX_EPT_DEFAULT_GAW + 1;
6841 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6845 /* For VT-d and EPT combination
6846 * 1. MMIO: always map as UC
6848 * a. VT-d without snooping control feature: can't guarantee the
6849 * result, try to trust guest.
6850 * b. VT-d with snooping control feature: snooping control feature of
6851 * VT-d engine can guarantee the cache correctness. Just set it
6852 * to WB to keep consistent with host. So the same as item 3.
6853 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6854 * consistent with host MTRR
6857 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6858 else if (vcpu->kvm->arch.iommu_domain &&
6859 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6860 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6861 VMX_EPT_MT_EPTE_SHIFT;
6863 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6869 static int vmx_get_lpage_level(void)
6871 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6872 return PT_DIRECTORY_LEVEL;
6874 /* For shadow and EPT supported 1GB page */
6875 return PT_PDPE_LEVEL;
6878 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6880 struct kvm_cpuid_entry2 *best;
6881 struct vcpu_vmx *vmx = to_vmx(vcpu);
6884 vmx->rdtscp_enabled = false;
6885 if (vmx_rdtscp_supported()) {
6886 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6887 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6888 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6889 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6890 vmx->rdtscp_enabled = true;
6892 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6893 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6899 /* Exposing INVPCID only when PCID is exposed */
6900 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6901 if (vmx_invpcid_supported() &&
6902 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
6903 guest_cpuid_has_pcid(vcpu)) {
6904 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6905 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6906 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6909 if (cpu_has_secondary_exec_ctrls()) {
6910 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6911 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6912 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6916 best->ebx &= ~bit(X86_FEATURE_INVPCID);
6920 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6922 if (func == 1 && nested)
6923 entry->ecx |= bit(X86_FEATURE_VMX);
6927 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6928 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6929 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6930 * guest in a way that will both be appropriate to L1's requests, and our
6931 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6932 * function also has additional necessary side-effects, like setting various
6933 * vcpu->arch fields.
6935 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6937 struct vcpu_vmx *vmx = to_vmx(vcpu);
6940 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6941 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6942 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6943 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6944 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6945 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6946 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6947 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6948 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6949 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6950 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6951 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6952 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6953 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6954 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6955 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6956 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6957 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6958 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6959 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6960 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6961 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6962 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6963 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6964 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6965 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6966 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6967 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6968 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6969 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6970 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6971 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6972 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6973 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6974 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6975 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6977 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6978 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6979 vmcs12->vm_entry_intr_info_field);
6980 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6981 vmcs12->vm_entry_exception_error_code);
6982 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6983 vmcs12->vm_entry_instruction_len);
6984 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6985 vmcs12->guest_interruptibility_info);
6986 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6987 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6988 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
6989 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6990 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6991 vmcs12->guest_pending_dbg_exceptions);
6992 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6993 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6995 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6997 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6998 (vmcs_config.pin_based_exec_ctrl |
6999 vmcs12->pin_based_vm_exec_control));
7002 * Whether page-faults are trapped is determined by a combination of
7003 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7004 * If enable_ept, L0 doesn't care about page faults and we should
7005 * set all of these to L1's desires. However, if !enable_ept, L0 does
7006 * care about (at least some) page faults, and because it is not easy
7007 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7008 * to exit on each and every L2 page fault. This is done by setting
7009 * MASK=MATCH=0 and (see below) EB.PF=1.
7010 * Note that below we don't need special code to set EB.PF beyond the
7011 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7012 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7013 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7015 * A problem with this approach (when !enable_ept) is that L1 may be
7016 * injected with more page faults than it asked for. This could have
7017 * caused problems, but in practice existing hypervisors don't care.
7018 * To fix this, we will need to emulate the PFEC checking (on the L1
7019 * page tables), using walk_addr(), when injecting PFs to L1.
7021 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7022 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7023 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7024 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7026 if (cpu_has_secondary_exec_ctrls()) {
7027 u32 exec_control = vmx_secondary_exec_control(vmx);
7028 if (!vmx->rdtscp_enabled)
7029 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7030 /* Take the following fields only from vmcs12 */
7031 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7032 if (nested_cpu_has(vmcs12,
7033 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7034 exec_control |= vmcs12->secondary_vm_exec_control;
7036 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7038 * Translate L1 physical address to host physical
7039 * address for vmcs02. Keep the page pinned, so this
7040 * physical address remains valid. We keep a reference
7041 * to it so we can release it later.
7043 if (vmx->nested.apic_access_page) /* shouldn't happen */
7044 nested_release_page(vmx->nested.apic_access_page);
7045 vmx->nested.apic_access_page =
7046 nested_get_page(vcpu, vmcs12->apic_access_addr);
7048 * If translation failed, no matter: This feature asks
7049 * to exit when accessing the given address, and if it
7050 * can never be accessed, this feature won't do
7053 if (!vmx->nested.apic_access_page)
7055 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7057 vmcs_write64(APIC_ACCESS_ADDR,
7058 page_to_phys(vmx->nested.apic_access_page));
7061 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7066 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7067 * Some constant fields are set here by vmx_set_constant_host_state().
7068 * Other fields are different per CPU, and will be set later when
7069 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7071 vmx_set_constant_host_state();
7074 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7075 * entry, but only if the current (host) sp changed from the value
7076 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7077 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7078 * here we just force the write to happen on entry.
7082 exec_control = vmx_exec_control(vmx); /* L0's desires */
7083 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7084 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7085 exec_control &= ~CPU_BASED_TPR_SHADOW;
7086 exec_control |= vmcs12->cpu_based_vm_exec_control;
7088 * Merging of IO and MSR bitmaps not currently supported.
7089 * Rather, exit every time.
7091 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7092 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7093 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7095 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7097 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7098 * bitwise-or of what L1 wants to trap for L2, and what we want to
7099 * trap. Note that CR0.TS also needs updating - we do this later.
7101 update_exception_bitmap(vcpu);
7102 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7103 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7105 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7106 vmcs_write32(VM_EXIT_CONTROLS,
7107 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7108 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7109 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7111 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7112 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7113 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7114 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7117 set_cr4_guest_host_mask(vmx);
7119 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7120 vmcs_write64(TSC_OFFSET,
7121 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7123 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7127 * Trivially support vpid by letting L2s share their parent
7128 * L1's vpid. TODO: move to a more elaborate solution, giving
7129 * each L2 its own vpid and exposing the vpid feature to L1.
7131 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7132 vmx_flush_tlb(vcpu);
7135 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7136 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7137 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7138 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7140 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7141 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7142 vmx_set_efer(vcpu, vcpu->arch.efer);
7145 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7146 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7147 * The CR0_READ_SHADOW is what L2 should have expected to read given
7148 * the specifications by L1; It's not enough to take
7149 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7150 * have more bits than L1 expected.
7152 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7153 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7155 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7156 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7158 /* shadow page tables on either EPT or shadow page tables */
7159 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7160 kvm_mmu_reset_context(vcpu);
7162 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7163 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7167 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7168 * for running an L2 nested guest.
7170 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7172 struct vmcs12 *vmcs12;
7173 struct vcpu_vmx *vmx = to_vmx(vcpu);
7175 struct loaded_vmcs *vmcs02;
7177 if (!nested_vmx_check_permission(vcpu) ||
7178 !nested_vmx_check_vmcs12(vcpu))
7181 skip_emulated_instruction(vcpu);
7182 vmcs12 = get_vmcs12(vcpu);
7185 * The nested entry process starts with enforcing various prerequisites
7186 * on vmcs12 as required by the Intel SDM, and act appropriately when
7187 * they fail: As the SDM explains, some conditions should cause the
7188 * instruction to fail, while others will cause the instruction to seem
7189 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7190 * To speed up the normal (success) code path, we should avoid checking
7191 * for misconfigurations which will anyway be caught by the processor
7192 * when using the merged vmcs02.
7194 if (vmcs12->launch_state == launch) {
7195 nested_vmx_failValid(vcpu,
7196 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7197 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7201 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7202 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7203 /*TODO: Also verify bits beyond physical address width are 0*/
7204 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7208 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7209 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7210 /*TODO: Also verify bits beyond physical address width are 0*/
7211 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7215 if (vmcs12->vm_entry_msr_load_count > 0 ||
7216 vmcs12->vm_exit_msr_load_count > 0 ||
7217 vmcs12->vm_exit_msr_store_count > 0) {
7218 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7220 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7224 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7225 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7226 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7227 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7228 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7229 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7230 !vmx_control_verify(vmcs12->vm_exit_controls,
7231 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7232 !vmx_control_verify(vmcs12->vm_entry_controls,
7233 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7235 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7239 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7240 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7241 nested_vmx_failValid(vcpu,
7242 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7246 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7247 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7248 nested_vmx_entry_failure(vcpu, vmcs12,
7249 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7252 if (vmcs12->vmcs_link_pointer != -1ull) {
7253 nested_vmx_entry_failure(vcpu, vmcs12,
7254 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7259 * We're finally done with prerequisite checking, and can start with
7263 vmcs02 = nested_get_current_vmcs02(vmx);
7267 enter_guest_mode(vcpu);
7269 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7272 vmx->loaded_vmcs = vmcs02;
7274 vmx_vcpu_load(vcpu, cpu);
7278 vmx_segment_cache_clear(vmx);
7280 vmcs12->launch_state = 1;
7282 prepare_vmcs02(vcpu, vmcs12);
7285 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7286 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7287 * returned as far as L1 is concerned. It will only return (and set
7288 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7294 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7295 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7296 * This function returns the new value we should put in vmcs12.guest_cr0.
7297 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7298 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7299 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7300 * didn't trap the bit, because if L1 did, so would L0).
7301 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7302 * been modified by L2, and L1 knows it. So just leave the old value of
7303 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7304 * isn't relevant, because if L0 traps this bit it can set it to anything.
7305 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7306 * changed these bits, and therefore they need to be updated, but L0
7307 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7308 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7310 static inline unsigned long
7311 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7314 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7315 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7316 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7317 vcpu->arch.cr0_guest_owned_bits));
7320 static inline unsigned long
7321 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7324 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7325 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7326 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7327 vcpu->arch.cr4_guest_owned_bits));
7331 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7332 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7333 * and this function updates it to reflect the changes to the guest state while
7334 * L2 was running (and perhaps made some exits which were handled directly by L0
7335 * without going back to L1), and to reflect the exit reason.
7336 * Note that we do not have to copy here all VMCS fields, just those that
7337 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7338 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7339 * which already writes to vmcs12 directly.
7341 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7343 /* update guest state fields: */
7344 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7345 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7347 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7348 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7349 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7350 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7352 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7353 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7354 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7355 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7356 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7357 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7358 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7359 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7360 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7361 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7362 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7363 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7364 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7365 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7366 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7367 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7368 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7369 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7370 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7371 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7372 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7373 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7374 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7375 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7376 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7377 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7378 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7379 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7380 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7381 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7382 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7383 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7384 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7385 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7386 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7387 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7389 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7390 vmcs12->guest_interruptibility_info =
7391 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7392 vmcs12->guest_pending_dbg_exceptions =
7393 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7395 /* TODO: These cannot have changed unless we have MSR bitmaps and
7396 * the relevant bit asks not to trap the change */
7397 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7398 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7399 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7400 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7401 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7402 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7404 /* update exit information fields: */
7406 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
7407 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7409 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7410 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7411 vmcs12->idt_vectoring_info_field = to_vmx(vcpu)->idt_vectoring_info;
7412 vmcs12->idt_vectoring_error_code =
7413 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7414 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7415 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7417 /* clear vm-entry fields which are to be cleared on exit */
7418 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7419 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7423 * A part of what we need to when the nested L2 guest exits and we want to
7424 * run its L1 parent, is to reset L1's guest state to the host state specified
7426 * This function is to be called not only on normal nested exit, but also on
7427 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7428 * Failures During or After Loading Guest State").
7429 * This function should be called when the active VMCS is L1's (vmcs01).
7431 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7432 struct vmcs12 *vmcs12)
7434 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7435 vcpu->arch.efer = vmcs12->host_ia32_efer;
7436 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7437 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7439 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7440 vmx_set_efer(vcpu, vcpu->arch.efer);
7442 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7443 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7444 vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
7446 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7447 * actually changed, because it depends on the current state of
7448 * fpu_active (which may have changed).
7449 * Note that vmx_set_cr0 refers to efer set above.
7451 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7453 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7454 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7455 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7457 update_exception_bitmap(vcpu);
7458 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7459 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7462 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7463 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7465 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7466 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7468 /* shadow page tables on either EPT or shadow page tables */
7469 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7470 kvm_mmu_reset_context(vcpu);
7474 * Trivially support vpid by letting L2s share their parent
7475 * L1's vpid. TODO: move to a more elaborate solution, giving
7476 * each L2 its own vpid and exposing the vpid feature to L1.
7478 vmx_flush_tlb(vcpu);
7482 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7483 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7484 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7485 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7486 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7487 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7488 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7489 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7490 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7491 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7492 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7493 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7494 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7495 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7496 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7498 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7499 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7500 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7501 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7502 vmcs12->host_ia32_perf_global_ctrl);
7504 kvm_set_dr(vcpu, 7, 0x400);
7505 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
7509 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7510 * and modify vmcs12 to make it see what it would expect to see there if
7511 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7513 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7515 struct vcpu_vmx *vmx = to_vmx(vcpu);
7517 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7519 leave_guest_mode(vcpu);
7520 prepare_vmcs12(vcpu, vmcs12);
7523 vmx->loaded_vmcs = &vmx->vmcs01;
7525 vmx_vcpu_load(vcpu, cpu);
7529 vmx_segment_cache_clear(vmx);
7531 /* if no vmcs02 cache requested, remove the one we used */
7532 if (VMCS02_POOL_SIZE == 0)
7533 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7535 load_vmcs12_host_state(vcpu, vmcs12);
7537 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7538 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7540 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7543 /* Unpin physical memory we referred to in vmcs02 */
7544 if (vmx->nested.apic_access_page) {
7545 nested_release_page(vmx->nested.apic_access_page);
7546 vmx->nested.apic_access_page = 0;
7550 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7551 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7552 * success or failure flag accordingly.
7554 if (unlikely(vmx->fail)) {
7556 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7558 nested_vmx_succeed(vcpu);
7562 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7563 * 23.7 "VM-entry failures during or after loading guest state" (this also
7564 * lists the acceptable exit-reason and exit-qualification parameters).
7565 * It should only be called before L2 actually succeeded to run, and when
7566 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7568 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7569 struct vmcs12 *vmcs12,
7570 u32 reason, unsigned long qualification)
7572 load_vmcs12_host_state(vcpu, vmcs12);
7573 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7574 vmcs12->exit_qualification = qualification;
7575 nested_vmx_succeed(vcpu);
7578 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7579 struct x86_instruction_info *info,
7580 enum x86_intercept_stage stage)
7582 return X86EMUL_CONTINUE;
7585 static struct kvm_x86_ops vmx_x86_ops = {
7586 .cpu_has_kvm_support = cpu_has_kvm_support,
7587 .disabled_by_bios = vmx_disabled_by_bios,
7588 .hardware_setup = hardware_setup,
7589 .hardware_unsetup = hardware_unsetup,
7590 .check_processor_compatibility = vmx_check_processor_compat,
7591 .hardware_enable = hardware_enable,
7592 .hardware_disable = hardware_disable,
7593 .cpu_has_accelerated_tpr = report_flexpriority,
7595 .vcpu_create = vmx_create_vcpu,
7596 .vcpu_free = vmx_free_vcpu,
7597 .vcpu_reset = vmx_vcpu_reset,
7599 .prepare_guest_switch = vmx_save_host_state,
7600 .vcpu_load = vmx_vcpu_load,
7601 .vcpu_put = vmx_vcpu_put,
7603 .update_db_bp_intercept = update_exception_bitmap,
7604 .get_msr = vmx_get_msr,
7605 .set_msr = vmx_set_msr,
7606 .get_segment_base = vmx_get_segment_base,
7607 .get_segment = vmx_get_segment,
7608 .set_segment = vmx_set_segment,
7609 .get_cpl = vmx_get_cpl,
7610 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7611 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7612 .decache_cr3 = vmx_decache_cr3,
7613 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7614 .set_cr0 = vmx_set_cr0,
7615 .set_cr3 = vmx_set_cr3,
7616 .set_cr4 = vmx_set_cr4,
7617 .set_efer = vmx_set_efer,
7618 .get_idt = vmx_get_idt,
7619 .set_idt = vmx_set_idt,
7620 .get_gdt = vmx_get_gdt,
7621 .set_gdt = vmx_set_gdt,
7622 .set_dr7 = vmx_set_dr7,
7623 .cache_reg = vmx_cache_reg,
7624 .get_rflags = vmx_get_rflags,
7625 .set_rflags = vmx_set_rflags,
7626 .fpu_activate = vmx_fpu_activate,
7627 .fpu_deactivate = vmx_fpu_deactivate,
7629 .tlb_flush = vmx_flush_tlb,
7631 .run = vmx_vcpu_run,
7632 .handle_exit = vmx_handle_exit,
7633 .skip_emulated_instruction = skip_emulated_instruction,
7634 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7635 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7636 .patch_hypercall = vmx_patch_hypercall,
7637 .set_irq = vmx_inject_irq,
7638 .set_nmi = vmx_inject_nmi,
7639 .queue_exception = vmx_queue_exception,
7640 .cancel_injection = vmx_cancel_injection,
7641 .interrupt_allowed = vmx_interrupt_allowed,
7642 .nmi_allowed = vmx_nmi_allowed,
7643 .get_nmi_mask = vmx_get_nmi_mask,
7644 .set_nmi_mask = vmx_set_nmi_mask,
7645 .enable_nmi_window = enable_nmi_window,
7646 .enable_irq_window = enable_irq_window,
7647 .update_cr8_intercept = update_cr8_intercept,
7648 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
7649 .vm_has_apicv = vmx_vm_has_apicv,
7650 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7651 .hwapic_irr_update = vmx_hwapic_irr_update,
7652 .hwapic_isr_update = vmx_hwapic_isr_update,
7654 .set_tss_addr = vmx_set_tss_addr,
7655 .get_tdp_level = get_ept_level,
7656 .get_mt_mask = vmx_get_mt_mask,
7658 .get_exit_info = vmx_get_exit_info,
7660 .get_lpage_level = vmx_get_lpage_level,
7662 .cpuid_update = vmx_cpuid_update,
7664 .rdtscp_supported = vmx_rdtscp_supported,
7665 .invpcid_supported = vmx_invpcid_supported,
7667 .set_supported_cpuid = vmx_set_supported_cpuid,
7669 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7671 .set_tsc_khz = vmx_set_tsc_khz,
7672 .read_tsc_offset = vmx_read_tsc_offset,
7673 .write_tsc_offset = vmx_write_tsc_offset,
7674 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7675 .compute_tsc_offset = vmx_compute_tsc_offset,
7676 .read_l1_tsc = vmx_read_l1_tsc,
7678 .set_tdp_cr3 = vmx_set_cr3,
7680 .check_intercept = vmx_check_intercept,
7683 static int __init vmx_init(void)
7687 rdmsrl_safe(MSR_EFER, &host_efer);
7689 for (i = 0; i < NR_VMX_MSR; ++i)
7690 kvm_define_shared_msr(i, vmx_msr_index[i]);
7692 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7693 if (!vmx_io_bitmap_a)
7698 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7699 if (!vmx_io_bitmap_b)
7702 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7703 if (!vmx_msr_bitmap_legacy)
7706 vmx_msr_bitmap_legacy_x2apic =
7707 (unsigned long *)__get_free_page(GFP_KERNEL);
7708 if (!vmx_msr_bitmap_legacy_x2apic)
7711 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7712 if (!vmx_msr_bitmap_longmode)
7715 vmx_msr_bitmap_longmode_x2apic =
7716 (unsigned long *)__get_free_page(GFP_KERNEL);
7717 if (!vmx_msr_bitmap_longmode_x2apic)
7721 * Allow direct access to the PC debug port (it is often used for I/O
7722 * delays, but the vmexits simply slow things down).
7724 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7725 clear_bit(0x80, vmx_io_bitmap_a);
7727 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7729 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7730 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7732 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7734 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7735 __alignof__(struct vcpu_vmx), THIS_MODULE);
7740 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7741 crash_vmclear_local_loaded_vmcss);
7744 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7745 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7746 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7747 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7748 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7749 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7750 memcpy(vmx_msr_bitmap_legacy_x2apic,
7751 vmx_msr_bitmap_legacy, PAGE_SIZE);
7752 memcpy(vmx_msr_bitmap_longmode_x2apic,
7753 vmx_msr_bitmap_longmode, PAGE_SIZE);
7755 if (enable_apicv_reg_vid) {
7756 for (msr = 0x800; msr <= 0x8ff; msr++)
7757 vmx_disable_intercept_msr_read_x2apic(msr);
7759 /* According SDM, in x2apic mode, the whole id reg is used.
7760 * But in KVM, it only use the highest eight bits. Need to
7762 vmx_enable_intercept_msr_read_x2apic(0x802);
7764 vmx_enable_intercept_msr_read_x2apic(0x839);
7766 vmx_disable_intercept_msr_write_x2apic(0x808);
7768 vmx_disable_intercept_msr_write_x2apic(0x80b);
7770 vmx_disable_intercept_msr_write_x2apic(0x83f);
7774 kvm_mmu_set_mask_ptes(0ull,
7775 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7776 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7777 0ull, VMX_EPT_EXECUTABLE_MASK);
7778 ept_set_mmio_spte_mask();
7786 free_page((unsigned long)vmx_msr_bitmap_longmode);
7788 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7790 free_page((unsigned long)vmx_msr_bitmap_legacy);
7792 free_page((unsigned long)vmx_io_bitmap_b);
7794 free_page((unsigned long)vmx_io_bitmap_a);
7798 static void __exit vmx_exit(void)
7800 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7801 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
7802 free_page((unsigned long)vmx_msr_bitmap_legacy);
7803 free_page((unsigned long)vmx_msr_bitmap_longmode);
7804 free_page((unsigned long)vmx_io_bitmap_b);
7805 free_page((unsigned long)vmx_io_bitmap_a);
7808 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7815 module_init(vmx_init)
7816 module_exit(vmx_exit)