2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/trace_events.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
42 #include <asm/virtext.h>
44 #include <asm/fpu/internal.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
49 #include <asm/irq_remapping.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
55 #define __ex_clear(x, reg) \
56 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
58 MODULE_AUTHOR("Qumranet");
59 MODULE_LICENSE("GPL");
61 static const struct x86_cpu_id vmx_cpu_id[] = {
62 X86_FEATURE_MATCH(X86_FEATURE_VMX),
65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
67 static bool __read_mostly enable_vpid = 1;
68 module_param_named(vpid, enable_vpid, bool, 0444);
70 static bool __read_mostly flexpriority_enabled = 1;
71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
73 static bool __read_mostly enable_ept = 1;
74 module_param_named(ept, enable_ept, bool, S_IRUGO);
76 static bool __read_mostly enable_unrestricted_guest = 1;
77 module_param_named(unrestricted_guest,
78 enable_unrestricted_guest, bool, S_IRUGO);
80 static bool __read_mostly enable_ept_ad_bits = 1;
81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
83 static bool __read_mostly emulate_invalid_guest_state = true;
84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
86 static bool __read_mostly vmm_exclusive = 1;
87 module_param(vmm_exclusive, bool, S_IRUGO);
89 static bool __read_mostly fasteoi = 1;
90 module_param(fasteoi, bool, S_IRUGO);
92 static bool __read_mostly enable_apicv = 1;
93 module_param(enable_apicv, bool, S_IRUGO);
95 static bool __read_mostly enable_shadow_vmcs = 1;
96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested = 0;
103 module_param(nested, bool, S_IRUGO);
105 static u64 __read_mostly host_xss;
107 static bool __read_mostly enable_pml = 1;
108 module_param_named(pml, enable_pml, bool, S_IRUGO);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
114 #define KVM_VM_CR0_ALWAYS_ON \
115 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
116 #define KVM_CR4_GUEST_OWNED_BITS \
117 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
118 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
128 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
129 * ple_gap: upper bound on the amount of time between two successive
130 * executions of PAUSE in a loop. Also indicate if ple enabled.
131 * According to test, this time is usually smaller than 128 cycles.
132 * ple_window: upper bound on the amount of time a guest is allowed to execute
133 * in a PAUSE loop. Tests indicate that most spinlocks are held for
134 * less than 2^12 cycles
135 * Time is measured based on a counter that runs at the same rate as the TSC,
136 * refer SDM volume 3b section 21.6.13 & 22.1.3.
138 #define KVM_VMX_DEFAULT_PLE_GAP 128
139 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
143 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
146 module_param(ple_gap, int, S_IRUGO);
148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
149 module_param(ple_window, int, S_IRUGO);
151 /* Default doubles per-vcpu window every exit. */
152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
153 module_param(ple_window_grow, int, S_IRUGO);
155 /* Default resets per-vcpu window every exit to ple_window. */
156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
157 module_param(ple_window_shrink, int, S_IRUGO);
159 /* Default is to compute the maximum so we can never overflow. */
160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
161 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
162 module_param(ple_window_max, int, S_IRUGO);
164 extern const ulong vmx_return;
166 #define NR_AUTOLOAD_MSRS 8
167 #define VMCS02_POOL_SIZE 1
176 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
177 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
178 * loaded on this CPU (so we can clear them if the CPU goes down).
184 struct list_head loaded_vmcss_on_cpu_link;
187 struct shared_msr_entry {
194 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
195 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
196 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
197 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
198 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
199 * More than one of these structures may exist, if L1 runs multiple L2 guests.
200 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
201 * underlying hardware which will be used to run L2.
202 * This structure is packed to ensure that its layout is identical across
203 * machines (necessary for live migration).
204 * If there are changes in this struct, VMCS12_REVISION must be changed.
206 typedef u64 natural_width;
207 struct __packed vmcs12 {
208 /* According to the Intel spec, a VMCS region must start with the
209 * following two fields. Then follow implementation-specific data.
214 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
215 u32 padding[7]; /* room for future expansion */
220 u64 vm_exit_msr_store_addr;
221 u64 vm_exit_msr_load_addr;
222 u64 vm_entry_msr_load_addr;
224 u64 virtual_apic_page_addr;
225 u64 apic_access_addr;
226 u64 posted_intr_desc_addr;
228 u64 eoi_exit_bitmap0;
229 u64 eoi_exit_bitmap1;
230 u64 eoi_exit_bitmap2;
231 u64 eoi_exit_bitmap3;
233 u64 guest_physical_address;
234 u64 vmcs_link_pointer;
235 u64 guest_ia32_debugctl;
238 u64 guest_ia32_perf_global_ctrl;
246 u64 host_ia32_perf_global_ctrl;
247 u64 padding64[8]; /* room for future expansion */
249 * To allow migration of L1 (complete with its L2 guests) between
250 * machines of different natural widths (32 or 64 bit), we cannot have
251 * unsigned long fields with no explict size. We use u64 (aliased
252 * natural_width) instead. Luckily, x86 is little-endian.
254 natural_width cr0_guest_host_mask;
255 natural_width cr4_guest_host_mask;
256 natural_width cr0_read_shadow;
257 natural_width cr4_read_shadow;
258 natural_width cr3_target_value0;
259 natural_width cr3_target_value1;
260 natural_width cr3_target_value2;
261 natural_width cr3_target_value3;
262 natural_width exit_qualification;
263 natural_width guest_linear_address;
264 natural_width guest_cr0;
265 natural_width guest_cr3;
266 natural_width guest_cr4;
267 natural_width guest_es_base;
268 natural_width guest_cs_base;
269 natural_width guest_ss_base;
270 natural_width guest_ds_base;
271 natural_width guest_fs_base;
272 natural_width guest_gs_base;
273 natural_width guest_ldtr_base;
274 natural_width guest_tr_base;
275 natural_width guest_gdtr_base;
276 natural_width guest_idtr_base;
277 natural_width guest_dr7;
278 natural_width guest_rsp;
279 natural_width guest_rip;
280 natural_width guest_rflags;
281 natural_width guest_pending_dbg_exceptions;
282 natural_width guest_sysenter_esp;
283 natural_width guest_sysenter_eip;
284 natural_width host_cr0;
285 natural_width host_cr3;
286 natural_width host_cr4;
287 natural_width host_fs_base;
288 natural_width host_gs_base;
289 natural_width host_tr_base;
290 natural_width host_gdtr_base;
291 natural_width host_idtr_base;
292 natural_width host_ia32_sysenter_esp;
293 natural_width host_ia32_sysenter_eip;
294 natural_width host_rsp;
295 natural_width host_rip;
296 natural_width paddingl[8]; /* room for future expansion */
297 u32 pin_based_vm_exec_control;
298 u32 cpu_based_vm_exec_control;
299 u32 exception_bitmap;
300 u32 page_fault_error_code_mask;
301 u32 page_fault_error_code_match;
302 u32 cr3_target_count;
303 u32 vm_exit_controls;
304 u32 vm_exit_msr_store_count;
305 u32 vm_exit_msr_load_count;
306 u32 vm_entry_controls;
307 u32 vm_entry_msr_load_count;
308 u32 vm_entry_intr_info_field;
309 u32 vm_entry_exception_error_code;
310 u32 vm_entry_instruction_len;
312 u32 secondary_vm_exec_control;
313 u32 vm_instruction_error;
315 u32 vm_exit_intr_info;
316 u32 vm_exit_intr_error_code;
317 u32 idt_vectoring_info_field;
318 u32 idt_vectoring_error_code;
319 u32 vm_exit_instruction_len;
320 u32 vmx_instruction_info;
327 u32 guest_ldtr_limit;
329 u32 guest_gdtr_limit;
330 u32 guest_idtr_limit;
331 u32 guest_es_ar_bytes;
332 u32 guest_cs_ar_bytes;
333 u32 guest_ss_ar_bytes;
334 u32 guest_ds_ar_bytes;
335 u32 guest_fs_ar_bytes;
336 u32 guest_gs_ar_bytes;
337 u32 guest_ldtr_ar_bytes;
338 u32 guest_tr_ar_bytes;
339 u32 guest_interruptibility_info;
340 u32 guest_activity_state;
341 u32 guest_sysenter_cs;
342 u32 host_ia32_sysenter_cs;
343 u32 vmx_preemption_timer_value;
344 u32 padding32[7]; /* room for future expansion */
345 u16 virtual_processor_id;
347 u16 guest_es_selector;
348 u16 guest_cs_selector;
349 u16 guest_ss_selector;
350 u16 guest_ds_selector;
351 u16 guest_fs_selector;
352 u16 guest_gs_selector;
353 u16 guest_ldtr_selector;
354 u16 guest_tr_selector;
355 u16 guest_intr_status;
356 u16 host_es_selector;
357 u16 host_cs_selector;
358 u16 host_ss_selector;
359 u16 host_ds_selector;
360 u16 host_fs_selector;
361 u16 host_gs_selector;
362 u16 host_tr_selector;
366 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
367 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
368 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
370 #define VMCS12_REVISION 0x11e57ed0
373 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
374 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
375 * current implementation, 4K are reserved to avoid future complications.
377 #define VMCS12_SIZE 0x1000
379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
381 struct list_head list;
383 struct loaded_vmcs vmcs02;
387 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
388 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
391 /* Has the level1 guest done vmxon? */
395 /* The guest-physical address of the current VMCS L1 keeps for L2 */
397 /* The host-usable pointer to the above */
398 struct page *current_vmcs12_page;
399 struct vmcs12 *current_vmcs12;
400 struct vmcs *current_shadow_vmcs;
402 * Indicates if the shadow vmcs must be updated with the
403 * data hold by vmcs12
405 bool sync_shadow_vmcs;
407 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
408 struct list_head vmcs02_pool;
410 u64 vmcs01_tsc_offset;
411 /* L2 must run next, and mustn't decide to exit to L1. */
412 bool nested_run_pending;
414 * Guest pages referred to in vmcs02 with host-physical pointers, so
415 * we must keep them pinned while L2 runs.
417 struct page *apic_access_page;
418 struct page *virtual_apic_page;
419 struct page *pi_desc_page;
420 struct pi_desc *pi_desc;
423 u64 msr_ia32_feature_control;
425 struct hrtimer preemption_timer;
426 bool preemption_timer_expired;
428 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
434 u32 nested_vmx_procbased_ctls_low;
435 u32 nested_vmx_procbased_ctls_high;
436 u32 nested_vmx_true_procbased_ctls_low;
437 u32 nested_vmx_secondary_ctls_low;
438 u32 nested_vmx_secondary_ctls_high;
439 u32 nested_vmx_pinbased_ctls_low;
440 u32 nested_vmx_pinbased_ctls_high;
441 u32 nested_vmx_exit_ctls_low;
442 u32 nested_vmx_exit_ctls_high;
443 u32 nested_vmx_true_exit_ctls_low;
444 u32 nested_vmx_entry_ctls_low;
445 u32 nested_vmx_entry_ctls_high;
446 u32 nested_vmx_true_entry_ctls_low;
447 u32 nested_vmx_misc_low;
448 u32 nested_vmx_misc_high;
449 u32 nested_vmx_ept_caps;
450 u32 nested_vmx_vpid_caps;
453 #define POSTED_INTR_ON 0
454 #define POSTED_INTR_SN 1
456 /* Posted-Interrupt Descriptor */
458 u32 pir[8]; /* Posted interrupt requested */
461 /* bit 256 - Outstanding Notification */
463 /* bit 257 - Suppress Notification */
465 /* bit 271:258 - Reserved */
467 /* bit 279:272 - Notification Vector */
469 /* bit 287:280 - Reserved */
471 /* bit 319:288 - Notification Destination */
479 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
481 return test_and_set_bit(POSTED_INTR_ON,
482 (unsigned long *)&pi_desc->control);
485 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
487 return test_and_clear_bit(POSTED_INTR_ON,
488 (unsigned long *)&pi_desc->control);
491 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
493 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
496 static inline void pi_clear_sn(struct pi_desc *pi_desc)
498 return clear_bit(POSTED_INTR_SN,
499 (unsigned long *)&pi_desc->control);
502 static inline void pi_set_sn(struct pi_desc *pi_desc)
504 return set_bit(POSTED_INTR_SN,
505 (unsigned long *)&pi_desc->control);
508 static inline int pi_test_on(struct pi_desc *pi_desc)
510 return test_bit(POSTED_INTR_ON,
511 (unsigned long *)&pi_desc->control);
514 static inline int pi_test_sn(struct pi_desc *pi_desc)
516 return test_bit(POSTED_INTR_SN,
517 (unsigned long *)&pi_desc->control);
521 struct kvm_vcpu vcpu;
522 unsigned long host_rsp;
524 bool nmi_known_unmasked;
526 u32 idt_vectoring_info;
528 struct shared_msr_entry *guest_msrs;
531 unsigned long host_idt_base;
533 u64 msr_host_kernel_gs_base;
534 u64 msr_guest_kernel_gs_base;
536 u32 vm_entry_controls_shadow;
537 u32 vm_exit_controls_shadow;
539 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
540 * non-nested (L1) guest, it always points to vmcs01. For a nested
541 * guest (L2), it points to a different VMCS.
543 struct loaded_vmcs vmcs01;
544 struct loaded_vmcs *loaded_vmcs;
545 bool __launched; /* temporary, used in vmx_vcpu_run */
546 struct msr_autoload {
548 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
549 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
553 u16 fs_sel, gs_sel, ldt_sel;
557 int gs_ldt_reload_needed;
558 int fs_reload_needed;
559 u64 msr_host_bndcfgs;
560 unsigned long vmcs_host_cr4; /* May not match real cr4 */
565 struct kvm_segment segs[8];
568 u32 bitmask; /* 4 bits per segment (1 bit per field) */
569 struct kvm_save_segment {
577 bool emulation_required;
579 /* Support for vnmi-less CPUs */
580 int soft_vnmi_blocked;
582 s64 vnmi_blocked_time;
585 /* Posted interrupt descriptor */
586 struct pi_desc pi_desc;
588 /* Support for a guest hypervisor (nested VMX) */
589 struct nested_vmx nested;
591 /* Dynamic PLE window. */
593 bool ple_window_dirty;
595 /* Support for PML */
596 #define PML_ENTITY_NUM 512
599 u64 current_tsc_ratio;
602 enum segment_cache_field {
611 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
613 return container_of(vcpu, struct vcpu_vmx, vcpu);
616 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
618 return &(to_vmx(vcpu)->pi_desc);
621 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
622 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
623 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
624 [number##_HIGH] = VMCS12_OFFSET(name)+4
627 static unsigned long shadow_read_only_fields[] = {
629 * We do NOT shadow fields that are modified when L0
630 * traps and emulates any vmx instruction (e.g. VMPTRLD,
631 * VMXON...) executed by L1.
632 * For example, VM_INSTRUCTION_ERROR is read
633 * by L1 if a vmx instruction fails (part of the error path).
634 * Note the code assumes this logic. If for some reason
635 * we start shadowing these fields then we need to
636 * force a shadow sync when L0 emulates vmx instructions
637 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
638 * by nested_vmx_failValid)
642 VM_EXIT_INSTRUCTION_LEN,
643 IDT_VECTORING_INFO_FIELD,
644 IDT_VECTORING_ERROR_CODE,
645 VM_EXIT_INTR_ERROR_CODE,
647 GUEST_LINEAR_ADDRESS,
648 GUEST_PHYSICAL_ADDRESS
650 static int max_shadow_read_only_fields =
651 ARRAY_SIZE(shadow_read_only_fields);
653 static unsigned long shadow_read_write_fields[] = {
660 GUEST_INTERRUPTIBILITY_INFO,
673 CPU_BASED_VM_EXEC_CONTROL,
674 VM_ENTRY_EXCEPTION_ERROR_CODE,
675 VM_ENTRY_INTR_INFO_FIELD,
676 VM_ENTRY_INSTRUCTION_LEN,
677 VM_ENTRY_EXCEPTION_ERROR_CODE,
683 static int max_shadow_read_write_fields =
684 ARRAY_SIZE(shadow_read_write_fields);
686 static const unsigned short vmcs_field_to_offset_table[] = {
687 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
688 FIELD(POSTED_INTR_NV, posted_intr_nv),
689 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
690 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
691 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
692 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
693 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
694 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
695 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
696 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
697 FIELD(GUEST_INTR_STATUS, guest_intr_status),
698 FIELD(HOST_ES_SELECTOR, host_es_selector),
699 FIELD(HOST_CS_SELECTOR, host_cs_selector),
700 FIELD(HOST_SS_SELECTOR, host_ss_selector),
701 FIELD(HOST_DS_SELECTOR, host_ds_selector),
702 FIELD(HOST_FS_SELECTOR, host_fs_selector),
703 FIELD(HOST_GS_SELECTOR, host_gs_selector),
704 FIELD(HOST_TR_SELECTOR, host_tr_selector),
705 FIELD64(IO_BITMAP_A, io_bitmap_a),
706 FIELD64(IO_BITMAP_B, io_bitmap_b),
707 FIELD64(MSR_BITMAP, msr_bitmap),
708 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
709 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
710 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
711 FIELD64(TSC_OFFSET, tsc_offset),
712 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
713 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
714 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
715 FIELD64(EPT_POINTER, ept_pointer),
716 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
717 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
718 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
719 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
720 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
721 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
722 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
723 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
724 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
725 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
726 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
727 FIELD64(GUEST_PDPTR0, guest_pdptr0),
728 FIELD64(GUEST_PDPTR1, guest_pdptr1),
729 FIELD64(GUEST_PDPTR2, guest_pdptr2),
730 FIELD64(GUEST_PDPTR3, guest_pdptr3),
731 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
732 FIELD64(HOST_IA32_PAT, host_ia32_pat),
733 FIELD64(HOST_IA32_EFER, host_ia32_efer),
734 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
735 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
736 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
737 FIELD(EXCEPTION_BITMAP, exception_bitmap),
738 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
739 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
740 FIELD(CR3_TARGET_COUNT, cr3_target_count),
741 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
742 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
743 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
744 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
745 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
746 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
747 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
748 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
749 FIELD(TPR_THRESHOLD, tpr_threshold),
750 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
751 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
752 FIELD(VM_EXIT_REASON, vm_exit_reason),
753 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
754 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
755 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
756 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
757 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
758 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
759 FIELD(GUEST_ES_LIMIT, guest_es_limit),
760 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
761 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
762 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
763 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
764 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
765 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
766 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
767 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
768 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
769 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
770 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
771 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
772 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
773 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
774 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
775 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
776 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
777 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
778 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
779 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
780 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
781 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
782 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
783 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
784 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
785 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
786 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
787 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
788 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
789 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
790 FIELD(EXIT_QUALIFICATION, exit_qualification),
791 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
792 FIELD(GUEST_CR0, guest_cr0),
793 FIELD(GUEST_CR3, guest_cr3),
794 FIELD(GUEST_CR4, guest_cr4),
795 FIELD(GUEST_ES_BASE, guest_es_base),
796 FIELD(GUEST_CS_BASE, guest_cs_base),
797 FIELD(GUEST_SS_BASE, guest_ss_base),
798 FIELD(GUEST_DS_BASE, guest_ds_base),
799 FIELD(GUEST_FS_BASE, guest_fs_base),
800 FIELD(GUEST_GS_BASE, guest_gs_base),
801 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
802 FIELD(GUEST_TR_BASE, guest_tr_base),
803 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
804 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
805 FIELD(GUEST_DR7, guest_dr7),
806 FIELD(GUEST_RSP, guest_rsp),
807 FIELD(GUEST_RIP, guest_rip),
808 FIELD(GUEST_RFLAGS, guest_rflags),
809 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
810 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
811 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
812 FIELD(HOST_CR0, host_cr0),
813 FIELD(HOST_CR3, host_cr3),
814 FIELD(HOST_CR4, host_cr4),
815 FIELD(HOST_FS_BASE, host_fs_base),
816 FIELD(HOST_GS_BASE, host_gs_base),
817 FIELD(HOST_TR_BASE, host_tr_base),
818 FIELD(HOST_GDTR_BASE, host_gdtr_base),
819 FIELD(HOST_IDTR_BASE, host_idtr_base),
820 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
821 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
822 FIELD(HOST_RSP, host_rsp),
823 FIELD(HOST_RIP, host_rip),
826 static inline short vmcs_field_to_offset(unsigned long field)
828 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
830 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
831 vmcs_field_to_offset_table[field] == 0)
834 return vmcs_field_to_offset_table[field];
837 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
839 return to_vmx(vcpu)->nested.current_vmcs12;
842 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
844 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
845 if (is_error_page(page))
851 static void nested_release_page(struct page *page)
853 kvm_release_page_dirty(page);
856 static void nested_release_page_clean(struct page *page)
858 kvm_release_page_clean(page);
861 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
862 static u64 construct_eptp(unsigned long root_hpa);
863 static void kvm_cpu_vmxon(u64 addr);
864 static void kvm_cpu_vmxoff(void);
865 static bool vmx_mpx_supported(void);
866 static bool vmx_xsaves_supported(void);
867 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
868 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
869 static void vmx_set_segment(struct kvm_vcpu *vcpu,
870 struct kvm_segment *var, int seg);
871 static void vmx_get_segment(struct kvm_vcpu *vcpu,
872 struct kvm_segment *var, int seg);
873 static bool guest_state_valid(struct kvm_vcpu *vcpu);
874 static u32 vmx_segment_access_rights(struct kvm_segment *var);
875 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
876 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
877 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
878 static int alloc_identity_pagetable(struct kvm *kvm);
880 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
881 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
883 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
884 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
886 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
887 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
890 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
891 * can find which vCPU should be waken up.
893 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
894 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
896 static unsigned long *vmx_io_bitmap_a;
897 static unsigned long *vmx_io_bitmap_b;
898 static unsigned long *vmx_msr_bitmap_legacy;
899 static unsigned long *vmx_msr_bitmap_longmode;
900 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
901 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
902 static unsigned long *vmx_msr_bitmap_nested;
903 static unsigned long *vmx_vmread_bitmap;
904 static unsigned long *vmx_vmwrite_bitmap;
906 static bool cpu_has_load_ia32_efer;
907 static bool cpu_has_load_perf_global_ctrl;
909 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
910 static DEFINE_SPINLOCK(vmx_vpid_lock);
912 static struct vmcs_config {
916 u32 pin_based_exec_ctrl;
917 u32 cpu_based_exec_ctrl;
918 u32 cpu_based_2nd_exec_ctrl;
923 static struct vmx_capability {
928 #define VMX_SEGMENT_FIELD(seg) \
929 [VCPU_SREG_##seg] = { \
930 .selector = GUEST_##seg##_SELECTOR, \
931 .base = GUEST_##seg##_BASE, \
932 .limit = GUEST_##seg##_LIMIT, \
933 .ar_bytes = GUEST_##seg##_AR_BYTES, \
936 static const struct kvm_vmx_segment_field {
941 } kvm_vmx_segment_fields[] = {
942 VMX_SEGMENT_FIELD(CS),
943 VMX_SEGMENT_FIELD(DS),
944 VMX_SEGMENT_FIELD(ES),
945 VMX_SEGMENT_FIELD(FS),
946 VMX_SEGMENT_FIELD(GS),
947 VMX_SEGMENT_FIELD(SS),
948 VMX_SEGMENT_FIELD(TR),
949 VMX_SEGMENT_FIELD(LDTR),
952 static u64 host_efer;
954 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
957 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
958 * away by decrementing the array size.
960 static const u32 vmx_msr_index[] = {
962 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
964 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
967 static inline bool is_page_fault(u32 intr_info)
969 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
970 INTR_INFO_VALID_MASK)) ==
971 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
974 static inline bool is_no_device(u32 intr_info)
976 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
977 INTR_INFO_VALID_MASK)) ==
978 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
981 static inline bool is_invalid_opcode(u32 intr_info)
983 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
984 INTR_INFO_VALID_MASK)) ==
985 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
988 static inline bool is_external_interrupt(u32 intr_info)
990 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
991 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
994 static inline bool is_machine_check(u32 intr_info)
996 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
997 INTR_INFO_VALID_MASK)) ==
998 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1001 static inline bool cpu_has_vmx_msr_bitmap(void)
1003 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1006 static inline bool cpu_has_vmx_tpr_shadow(void)
1008 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1011 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1013 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1016 static inline bool cpu_has_secondary_exec_ctrls(void)
1018 return vmcs_config.cpu_based_exec_ctrl &
1019 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1022 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1024 return vmcs_config.cpu_based_2nd_exec_ctrl &
1025 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1028 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1030 return vmcs_config.cpu_based_2nd_exec_ctrl &
1031 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1034 static inline bool cpu_has_vmx_apic_register_virt(void)
1036 return vmcs_config.cpu_based_2nd_exec_ctrl &
1037 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1040 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1042 return vmcs_config.cpu_based_2nd_exec_ctrl &
1043 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1046 static inline bool cpu_has_vmx_posted_intr(void)
1048 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1049 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1052 static inline bool cpu_has_vmx_apicv(void)
1054 return cpu_has_vmx_apic_register_virt() &&
1055 cpu_has_vmx_virtual_intr_delivery() &&
1056 cpu_has_vmx_posted_intr();
1059 static inline bool cpu_has_vmx_flexpriority(void)
1061 return cpu_has_vmx_tpr_shadow() &&
1062 cpu_has_vmx_virtualize_apic_accesses();
1065 static inline bool cpu_has_vmx_ept_execute_only(void)
1067 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1070 static inline bool cpu_has_vmx_ept_2m_page(void)
1072 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1075 static inline bool cpu_has_vmx_ept_1g_page(void)
1077 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1080 static inline bool cpu_has_vmx_ept_4levels(void)
1082 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1085 static inline bool cpu_has_vmx_ept_ad_bits(void)
1087 return vmx_capability.ept & VMX_EPT_AD_BIT;
1090 static inline bool cpu_has_vmx_invept_context(void)
1092 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1095 static inline bool cpu_has_vmx_invept_global(void)
1097 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1100 static inline bool cpu_has_vmx_invvpid_single(void)
1102 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1105 static inline bool cpu_has_vmx_invvpid_global(void)
1107 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1110 static inline bool cpu_has_vmx_ept(void)
1112 return vmcs_config.cpu_based_2nd_exec_ctrl &
1113 SECONDARY_EXEC_ENABLE_EPT;
1116 static inline bool cpu_has_vmx_unrestricted_guest(void)
1118 return vmcs_config.cpu_based_2nd_exec_ctrl &
1119 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1122 static inline bool cpu_has_vmx_ple(void)
1124 return vmcs_config.cpu_based_2nd_exec_ctrl &
1125 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1128 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1130 return flexpriority_enabled && lapic_in_kernel(vcpu);
1133 static inline bool cpu_has_vmx_vpid(void)
1135 return vmcs_config.cpu_based_2nd_exec_ctrl &
1136 SECONDARY_EXEC_ENABLE_VPID;
1139 static inline bool cpu_has_vmx_rdtscp(void)
1141 return vmcs_config.cpu_based_2nd_exec_ctrl &
1142 SECONDARY_EXEC_RDTSCP;
1145 static inline bool cpu_has_vmx_invpcid(void)
1147 return vmcs_config.cpu_based_2nd_exec_ctrl &
1148 SECONDARY_EXEC_ENABLE_INVPCID;
1151 static inline bool cpu_has_virtual_nmis(void)
1153 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1156 static inline bool cpu_has_vmx_wbinvd_exit(void)
1158 return vmcs_config.cpu_based_2nd_exec_ctrl &
1159 SECONDARY_EXEC_WBINVD_EXITING;
1162 static inline bool cpu_has_vmx_shadow_vmcs(void)
1165 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1166 /* check if the cpu supports writing r/o exit information fields */
1167 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1170 return vmcs_config.cpu_based_2nd_exec_ctrl &
1171 SECONDARY_EXEC_SHADOW_VMCS;
1174 static inline bool cpu_has_vmx_pml(void)
1176 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1179 static inline bool cpu_has_vmx_tsc_scaling(void)
1181 return vmcs_config.cpu_based_2nd_exec_ctrl &
1182 SECONDARY_EXEC_TSC_SCALING;
1185 static inline bool report_flexpriority(void)
1187 return flexpriority_enabled;
1190 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1192 return vmcs12->cpu_based_vm_exec_control & bit;
1195 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1197 return (vmcs12->cpu_based_vm_exec_control &
1198 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1199 (vmcs12->secondary_vm_exec_control & bit);
1202 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1204 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1207 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1209 return vmcs12->pin_based_vm_exec_control &
1210 PIN_BASED_VMX_PREEMPTION_TIMER;
1213 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1215 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1218 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1220 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1221 vmx_xsaves_supported();
1224 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1226 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1229 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1231 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1234 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1236 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1239 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1241 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1244 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1246 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1249 static inline bool is_exception(u32 intr_info)
1251 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1252 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1255 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1257 unsigned long exit_qualification);
1258 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1259 struct vmcs12 *vmcs12,
1260 u32 reason, unsigned long qualification);
1262 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1266 for (i = 0; i < vmx->nmsrs; ++i)
1267 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1272 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1278 } operand = { vpid, 0, gva };
1280 asm volatile (__ex(ASM_VMX_INVVPID)
1281 /* CF==1 or ZF==1 --> rc = -1 */
1282 "; ja 1f ; ud2 ; 1:"
1283 : : "a"(&operand), "c"(ext) : "cc", "memory");
1286 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1290 } operand = {eptp, gpa};
1292 asm volatile (__ex(ASM_VMX_INVEPT)
1293 /* CF==1 or ZF==1 --> rc = -1 */
1294 "; ja 1f ; ud2 ; 1:\n"
1295 : : "a" (&operand), "c" (ext) : "cc", "memory");
1298 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1302 i = __find_msr_index(vmx, msr);
1304 return &vmx->guest_msrs[i];
1308 static void vmcs_clear(struct vmcs *vmcs)
1310 u64 phys_addr = __pa(vmcs);
1313 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1314 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1317 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1321 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1323 vmcs_clear(loaded_vmcs->vmcs);
1324 loaded_vmcs->cpu = -1;
1325 loaded_vmcs->launched = 0;
1328 static void vmcs_load(struct vmcs *vmcs)
1330 u64 phys_addr = __pa(vmcs);
1333 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1334 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1337 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1341 #ifdef CONFIG_KEXEC_CORE
1343 * This bitmap is used to indicate whether the vmclear
1344 * operation is enabled on all cpus. All disabled by
1347 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1349 static inline void crash_enable_local_vmclear(int cpu)
1351 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1354 static inline void crash_disable_local_vmclear(int cpu)
1356 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1359 static inline int crash_local_vmclear_enabled(int cpu)
1361 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1364 static void crash_vmclear_local_loaded_vmcss(void)
1366 int cpu = raw_smp_processor_id();
1367 struct loaded_vmcs *v;
1369 if (!crash_local_vmclear_enabled(cpu))
1372 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1373 loaded_vmcss_on_cpu_link)
1374 vmcs_clear(v->vmcs);
1377 static inline void crash_enable_local_vmclear(int cpu) { }
1378 static inline void crash_disable_local_vmclear(int cpu) { }
1379 #endif /* CONFIG_KEXEC_CORE */
1381 static void __loaded_vmcs_clear(void *arg)
1383 struct loaded_vmcs *loaded_vmcs = arg;
1384 int cpu = raw_smp_processor_id();
1386 if (loaded_vmcs->cpu != cpu)
1387 return; /* vcpu migration can race with cpu offline */
1388 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1389 per_cpu(current_vmcs, cpu) = NULL;
1390 crash_disable_local_vmclear(cpu);
1391 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1394 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1395 * is before setting loaded_vmcs->vcpu to -1 which is done in
1396 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1397 * then adds the vmcs into percpu list before it is deleted.
1401 loaded_vmcs_init(loaded_vmcs);
1402 crash_enable_local_vmclear(cpu);
1405 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1407 int cpu = loaded_vmcs->cpu;
1410 smp_call_function_single(cpu,
1411 __loaded_vmcs_clear, loaded_vmcs, 1);
1414 static inline void vpid_sync_vcpu_single(int vpid)
1419 if (cpu_has_vmx_invvpid_single())
1420 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1423 static inline void vpid_sync_vcpu_global(void)
1425 if (cpu_has_vmx_invvpid_global())
1426 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1429 static inline void vpid_sync_context(int vpid)
1431 if (cpu_has_vmx_invvpid_single())
1432 vpid_sync_vcpu_single(vpid);
1434 vpid_sync_vcpu_global();
1437 static inline void ept_sync_global(void)
1439 if (cpu_has_vmx_invept_global())
1440 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1443 static inline void ept_sync_context(u64 eptp)
1446 if (cpu_has_vmx_invept_context())
1447 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1453 static __always_inline unsigned long vmcs_readl(unsigned long field)
1455 unsigned long value;
1457 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1458 : "=a"(value) : "d"(field) : "cc");
1462 static __always_inline u16 vmcs_read16(unsigned long field)
1464 return vmcs_readl(field);
1467 static __always_inline u32 vmcs_read32(unsigned long field)
1469 return vmcs_readl(field);
1472 static __always_inline u64 vmcs_read64(unsigned long field)
1474 #ifdef CONFIG_X86_64
1475 return vmcs_readl(field);
1477 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1481 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1483 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1484 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1488 static void vmcs_writel(unsigned long field, unsigned long value)
1492 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1493 : "=q"(error) : "a"(value), "d"(field) : "cc");
1494 if (unlikely(error))
1495 vmwrite_error(field, value);
1498 static void vmcs_write16(unsigned long field, u16 value)
1500 vmcs_writel(field, value);
1503 static void vmcs_write32(unsigned long field, u32 value)
1505 vmcs_writel(field, value);
1508 static void vmcs_write64(unsigned long field, u64 value)
1510 vmcs_writel(field, value);
1511 #ifndef CONFIG_X86_64
1513 vmcs_writel(field+1, value >> 32);
1517 static void vmcs_clear_bits(unsigned long field, u32 mask)
1519 vmcs_writel(field, vmcs_readl(field) & ~mask);
1522 static void vmcs_set_bits(unsigned long field, u32 mask)
1524 vmcs_writel(field, vmcs_readl(field) | mask);
1527 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1529 vmcs_write32(VM_ENTRY_CONTROLS, val);
1530 vmx->vm_entry_controls_shadow = val;
1533 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1535 if (vmx->vm_entry_controls_shadow != val)
1536 vm_entry_controls_init(vmx, val);
1539 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1541 return vmx->vm_entry_controls_shadow;
1545 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1547 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1550 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1552 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1555 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1557 vmcs_write32(VM_EXIT_CONTROLS, val);
1558 vmx->vm_exit_controls_shadow = val;
1561 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1563 if (vmx->vm_exit_controls_shadow != val)
1564 vm_exit_controls_init(vmx, val);
1567 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1569 return vmx->vm_exit_controls_shadow;
1573 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1575 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1578 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1580 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1583 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1585 vmx->segment_cache.bitmask = 0;
1588 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1592 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1594 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1595 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1596 vmx->segment_cache.bitmask = 0;
1598 ret = vmx->segment_cache.bitmask & mask;
1599 vmx->segment_cache.bitmask |= mask;
1603 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1605 u16 *p = &vmx->segment_cache.seg[seg].selector;
1607 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1608 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1612 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1614 ulong *p = &vmx->segment_cache.seg[seg].base;
1616 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1617 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1621 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1623 u32 *p = &vmx->segment_cache.seg[seg].limit;
1625 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1626 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1630 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1632 u32 *p = &vmx->segment_cache.seg[seg].ar;
1634 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1635 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1639 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1643 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1644 (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1645 if ((vcpu->guest_debug &
1646 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1647 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1648 eb |= 1u << BP_VECTOR;
1649 if (to_vmx(vcpu)->rmode.vm86_active)
1652 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1653 if (vcpu->fpu_active)
1654 eb &= ~(1u << NM_VECTOR);
1656 /* When we are running a nested L2 guest and L1 specified for it a
1657 * certain exception bitmap, we must trap the same exceptions and pass
1658 * them to L1. When running L2, we will only handle the exceptions
1659 * specified above if L1 did not want them.
1661 if (is_guest_mode(vcpu))
1662 eb |= get_vmcs12(vcpu)->exception_bitmap;
1664 vmcs_write32(EXCEPTION_BITMAP, eb);
1667 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1668 unsigned long entry, unsigned long exit)
1670 vm_entry_controls_clearbit(vmx, entry);
1671 vm_exit_controls_clearbit(vmx, exit);
1674 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1677 struct msr_autoload *m = &vmx->msr_autoload;
1681 if (cpu_has_load_ia32_efer) {
1682 clear_atomic_switch_msr_special(vmx,
1683 VM_ENTRY_LOAD_IA32_EFER,
1684 VM_EXIT_LOAD_IA32_EFER);
1688 case MSR_CORE_PERF_GLOBAL_CTRL:
1689 if (cpu_has_load_perf_global_ctrl) {
1690 clear_atomic_switch_msr_special(vmx,
1691 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1692 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1698 for (i = 0; i < m->nr; ++i)
1699 if (m->guest[i].index == msr)
1705 m->guest[i] = m->guest[m->nr];
1706 m->host[i] = m->host[m->nr];
1707 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1708 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1711 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1712 unsigned long entry, unsigned long exit,
1713 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1714 u64 guest_val, u64 host_val)
1716 vmcs_write64(guest_val_vmcs, guest_val);
1717 vmcs_write64(host_val_vmcs, host_val);
1718 vm_entry_controls_setbit(vmx, entry);
1719 vm_exit_controls_setbit(vmx, exit);
1722 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1723 u64 guest_val, u64 host_val)
1726 struct msr_autoload *m = &vmx->msr_autoload;
1730 if (cpu_has_load_ia32_efer) {
1731 add_atomic_switch_msr_special(vmx,
1732 VM_ENTRY_LOAD_IA32_EFER,
1733 VM_EXIT_LOAD_IA32_EFER,
1736 guest_val, host_val);
1740 case MSR_CORE_PERF_GLOBAL_CTRL:
1741 if (cpu_has_load_perf_global_ctrl) {
1742 add_atomic_switch_msr_special(vmx,
1743 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1744 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1745 GUEST_IA32_PERF_GLOBAL_CTRL,
1746 HOST_IA32_PERF_GLOBAL_CTRL,
1747 guest_val, host_val);
1751 case MSR_IA32_PEBS_ENABLE:
1752 /* PEBS needs a quiescent period after being disabled (to write
1753 * a record). Disabling PEBS through VMX MSR swapping doesn't
1754 * provide that period, so a CPU could write host's record into
1757 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1760 for (i = 0; i < m->nr; ++i)
1761 if (m->guest[i].index == msr)
1764 if (i == NR_AUTOLOAD_MSRS) {
1765 printk_once(KERN_WARNING "Not enough msr switch entries. "
1766 "Can't add msr %x\n", msr);
1768 } else if (i == m->nr) {
1770 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1771 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1774 m->guest[i].index = msr;
1775 m->guest[i].value = guest_val;
1776 m->host[i].index = msr;
1777 m->host[i].value = host_val;
1780 static void reload_tss(void)
1783 * VT restores TR but not its size. Useless.
1785 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1786 struct desc_struct *descs;
1788 descs = (void *)gdt->address;
1789 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1793 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1795 u64 guest_efer = vmx->vcpu.arch.efer;
1796 u64 ignore_bits = 0;
1800 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1801 * host CPUID is more efficient than testing guest CPUID
1802 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1804 if (boot_cpu_has(X86_FEATURE_SMEP))
1805 guest_efer |= EFER_NX;
1806 else if (!(guest_efer & EFER_NX))
1807 ignore_bits |= EFER_NX;
1811 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1813 ignore_bits |= EFER_SCE;
1814 #ifdef CONFIG_X86_64
1815 ignore_bits |= EFER_LMA | EFER_LME;
1816 /* SCE is meaningful only in long mode on Intel */
1817 if (guest_efer & EFER_LMA)
1818 ignore_bits &= ~(u64)EFER_SCE;
1821 clear_atomic_switch_msr(vmx, MSR_EFER);
1824 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1825 * On CPUs that support "load IA32_EFER", always switch EFER
1826 * atomically, since it's faster than switching it manually.
1828 if (cpu_has_load_ia32_efer ||
1829 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1830 if (!(guest_efer & EFER_LMA))
1831 guest_efer &= ~EFER_LME;
1832 if (guest_efer != host_efer)
1833 add_atomic_switch_msr(vmx, MSR_EFER,
1834 guest_efer, host_efer);
1837 guest_efer &= ~ignore_bits;
1838 guest_efer |= host_efer & ignore_bits;
1840 vmx->guest_msrs[efer_offset].data = guest_efer;
1841 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1847 static unsigned long segment_base(u16 selector)
1849 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1850 struct desc_struct *d;
1851 unsigned long table_base;
1854 if (!(selector & ~3))
1857 table_base = gdt->address;
1859 if (selector & 4) { /* from ldt */
1860 u16 ldt_selector = kvm_read_ldt();
1862 if (!(ldt_selector & ~3))
1865 table_base = segment_base(ldt_selector);
1867 d = (struct desc_struct *)(table_base + (selector & ~7));
1868 v = get_desc_base(d);
1869 #ifdef CONFIG_X86_64
1870 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1871 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1876 static inline unsigned long kvm_read_tr_base(void)
1879 asm("str %0" : "=g"(tr));
1880 return segment_base(tr);
1883 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1885 struct vcpu_vmx *vmx = to_vmx(vcpu);
1888 if (vmx->host_state.loaded)
1891 vmx->host_state.loaded = 1;
1893 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1894 * allow segment selectors with cpl > 0 or ti == 1.
1896 vmx->host_state.ldt_sel = kvm_read_ldt();
1897 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1898 savesegment(fs, vmx->host_state.fs_sel);
1899 if (!(vmx->host_state.fs_sel & 7)) {
1900 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1901 vmx->host_state.fs_reload_needed = 0;
1903 vmcs_write16(HOST_FS_SELECTOR, 0);
1904 vmx->host_state.fs_reload_needed = 1;
1906 savesegment(gs, vmx->host_state.gs_sel);
1907 if (!(vmx->host_state.gs_sel & 7))
1908 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1910 vmcs_write16(HOST_GS_SELECTOR, 0);
1911 vmx->host_state.gs_ldt_reload_needed = 1;
1914 #ifdef CONFIG_X86_64
1915 savesegment(ds, vmx->host_state.ds_sel);
1916 savesegment(es, vmx->host_state.es_sel);
1919 #ifdef CONFIG_X86_64
1920 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1921 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1923 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1924 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1927 #ifdef CONFIG_X86_64
1928 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1929 if (is_long_mode(&vmx->vcpu))
1930 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1932 if (boot_cpu_has(X86_FEATURE_MPX))
1933 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1934 for (i = 0; i < vmx->save_nmsrs; ++i)
1935 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1936 vmx->guest_msrs[i].data,
1937 vmx->guest_msrs[i].mask);
1940 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1942 if (!vmx->host_state.loaded)
1945 ++vmx->vcpu.stat.host_state_reload;
1946 vmx->host_state.loaded = 0;
1947 #ifdef CONFIG_X86_64
1948 if (is_long_mode(&vmx->vcpu))
1949 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1951 if (vmx->host_state.gs_ldt_reload_needed) {
1952 kvm_load_ldt(vmx->host_state.ldt_sel);
1953 #ifdef CONFIG_X86_64
1954 load_gs_index(vmx->host_state.gs_sel);
1956 loadsegment(gs, vmx->host_state.gs_sel);
1959 if (vmx->host_state.fs_reload_needed)
1960 loadsegment(fs, vmx->host_state.fs_sel);
1961 #ifdef CONFIG_X86_64
1962 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1963 loadsegment(ds, vmx->host_state.ds_sel);
1964 loadsegment(es, vmx->host_state.es_sel);
1968 #ifdef CONFIG_X86_64
1969 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1971 if (vmx->host_state.msr_host_bndcfgs)
1972 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1974 * If the FPU is not active (through the host task or
1975 * the guest vcpu), then restore the cr0.TS bit.
1977 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1979 load_gdt(this_cpu_ptr(&host_gdt));
1982 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1985 __vmx_load_host_state(vmx);
1989 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1991 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1992 struct pi_desc old, new;
1995 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1996 !irq_remapping_cap(IRQ_POSTING_CAP))
2000 old.control = new.control = pi_desc->control;
2003 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2004 * are two possible cases:
2005 * 1. After running 'pre_block', context switch
2006 * happened. For this case, 'sn' was set in
2007 * vmx_vcpu_put(), so we need to clear it here.
2008 * 2. After running 'pre_block', we were blocked,
2009 * and woken up by some other guy. For this case,
2010 * we don't need to do anything, 'pi_post_block'
2011 * will do everything for us. However, we cannot
2012 * check whether it is case #1 or case #2 here
2013 * (maybe, not needed), so we also clear sn here,
2014 * I think it is not a big deal.
2016 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2017 if (vcpu->cpu != cpu) {
2018 dest = cpu_physical_id(cpu);
2020 if (x2apic_enabled())
2023 new.ndst = (dest << 8) & 0xFF00;
2026 /* set 'NV' to 'notification vector' */
2027 new.nv = POSTED_INTR_VECTOR;
2030 /* Allow posting non-urgent interrupts */
2032 } while (cmpxchg(&pi_desc->control, old.control,
2033 new.control) != old.control);
2036 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2037 * vcpu mutex is already taken.
2039 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2041 struct vcpu_vmx *vmx = to_vmx(vcpu);
2042 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2045 kvm_cpu_vmxon(phys_addr);
2046 else if (vmx->loaded_vmcs->cpu != cpu)
2047 loaded_vmcs_clear(vmx->loaded_vmcs);
2049 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2050 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2051 vmcs_load(vmx->loaded_vmcs->vmcs);
2054 if (vmx->loaded_vmcs->cpu != cpu) {
2055 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2056 unsigned long sysenter_esp;
2058 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2059 local_irq_disable();
2060 crash_disable_local_vmclear(cpu);
2063 * Read loaded_vmcs->cpu should be before fetching
2064 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2065 * See the comments in __loaded_vmcs_clear().
2069 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2070 &per_cpu(loaded_vmcss_on_cpu, cpu));
2071 crash_enable_local_vmclear(cpu);
2075 * Linux uses per-cpu TSS and GDT, so set these when switching
2078 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2079 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
2081 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2082 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2084 vmx->loaded_vmcs->cpu = cpu;
2087 /* Setup TSC multiplier */
2088 if (kvm_has_tsc_control &&
2089 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2090 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2091 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2094 vmx_vcpu_pi_load(vcpu, cpu);
2097 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2099 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2101 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2102 !irq_remapping_cap(IRQ_POSTING_CAP))
2105 /* Set SN when the vCPU is preempted */
2106 if (vcpu->preempted)
2110 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2112 vmx_vcpu_pi_put(vcpu);
2114 __vmx_load_host_state(to_vmx(vcpu));
2115 if (!vmm_exclusive) {
2116 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2122 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2126 if (vcpu->fpu_active)
2128 vcpu->fpu_active = 1;
2129 cr0 = vmcs_readl(GUEST_CR0);
2130 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2131 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2132 vmcs_writel(GUEST_CR0, cr0);
2133 update_exception_bitmap(vcpu);
2134 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2135 if (is_guest_mode(vcpu))
2136 vcpu->arch.cr0_guest_owned_bits &=
2137 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2138 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2141 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2144 * Return the cr0 value that a nested guest would read. This is a combination
2145 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2146 * its hypervisor (cr0_read_shadow).
2148 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2150 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2151 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2153 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2155 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2156 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2159 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2161 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2162 * set this *before* calling this function.
2164 vmx_decache_cr0_guest_bits(vcpu);
2165 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2166 update_exception_bitmap(vcpu);
2167 vcpu->arch.cr0_guest_owned_bits = 0;
2168 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2169 if (is_guest_mode(vcpu)) {
2171 * L1's specified read shadow might not contain the TS bit,
2172 * so now that we turned on shadowing of this bit, we need to
2173 * set this bit of the shadow. Like in nested_vmx_run we need
2174 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2175 * up-to-date here because we just decached cr0.TS (and we'll
2176 * only update vmcs12->guest_cr0 on nested exit).
2178 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2179 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2180 (vcpu->arch.cr0 & X86_CR0_TS);
2181 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2183 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2186 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2188 unsigned long rflags, save_rflags;
2190 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2191 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2192 rflags = vmcs_readl(GUEST_RFLAGS);
2193 if (to_vmx(vcpu)->rmode.vm86_active) {
2194 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2195 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2196 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2198 to_vmx(vcpu)->rflags = rflags;
2200 return to_vmx(vcpu)->rflags;
2203 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2205 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2206 to_vmx(vcpu)->rflags = rflags;
2207 if (to_vmx(vcpu)->rmode.vm86_active) {
2208 to_vmx(vcpu)->rmode.save_rflags = rflags;
2209 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2211 vmcs_writel(GUEST_RFLAGS, rflags);
2214 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2216 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2219 if (interruptibility & GUEST_INTR_STATE_STI)
2220 ret |= KVM_X86_SHADOW_INT_STI;
2221 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2222 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2227 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2229 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2230 u32 interruptibility = interruptibility_old;
2232 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2234 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2235 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2236 else if (mask & KVM_X86_SHADOW_INT_STI)
2237 interruptibility |= GUEST_INTR_STATE_STI;
2239 if ((interruptibility != interruptibility_old))
2240 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2243 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2247 rip = kvm_rip_read(vcpu);
2248 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2249 kvm_rip_write(vcpu, rip);
2251 /* skipping an emulated instruction also counts */
2252 vmx_set_interrupt_shadow(vcpu, 0);
2256 * KVM wants to inject page-faults which it got to the guest. This function
2257 * checks whether in a nested guest, we need to inject them to L1 or L2.
2259 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2261 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2263 if (!(vmcs12->exception_bitmap & (1u << nr)))
2266 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2267 vmcs_read32(VM_EXIT_INTR_INFO),
2268 vmcs_readl(EXIT_QUALIFICATION));
2272 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2273 bool has_error_code, u32 error_code,
2276 struct vcpu_vmx *vmx = to_vmx(vcpu);
2277 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2279 if (!reinject && is_guest_mode(vcpu) &&
2280 nested_vmx_check_exception(vcpu, nr))
2283 if (has_error_code) {
2284 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2285 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2288 if (vmx->rmode.vm86_active) {
2290 if (kvm_exception_is_soft(nr))
2291 inc_eip = vcpu->arch.event_exit_inst_len;
2292 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2293 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2297 if (kvm_exception_is_soft(nr)) {
2298 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2299 vmx->vcpu.arch.event_exit_inst_len);
2300 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2302 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2304 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2307 static bool vmx_rdtscp_supported(void)
2309 return cpu_has_vmx_rdtscp();
2312 static bool vmx_invpcid_supported(void)
2314 return cpu_has_vmx_invpcid() && enable_ept;
2318 * Swap MSR entry in host/guest MSR entry array.
2320 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2322 struct shared_msr_entry tmp;
2324 tmp = vmx->guest_msrs[to];
2325 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2326 vmx->guest_msrs[from] = tmp;
2329 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2331 unsigned long *msr_bitmap;
2333 if (is_guest_mode(vcpu))
2334 msr_bitmap = vmx_msr_bitmap_nested;
2335 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2336 if (is_long_mode(vcpu))
2337 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2339 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2341 if (is_long_mode(vcpu))
2342 msr_bitmap = vmx_msr_bitmap_longmode;
2344 msr_bitmap = vmx_msr_bitmap_legacy;
2347 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2351 * Set up the vmcs to automatically save and restore system
2352 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2353 * mode, as fiddling with msrs is very expensive.
2355 static void setup_msrs(struct vcpu_vmx *vmx)
2357 int save_nmsrs, index;
2360 #ifdef CONFIG_X86_64
2361 if (is_long_mode(&vmx->vcpu)) {
2362 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2364 move_msr_up(vmx, index, save_nmsrs++);
2365 index = __find_msr_index(vmx, MSR_LSTAR);
2367 move_msr_up(vmx, index, save_nmsrs++);
2368 index = __find_msr_index(vmx, MSR_CSTAR);
2370 move_msr_up(vmx, index, save_nmsrs++);
2371 index = __find_msr_index(vmx, MSR_TSC_AUX);
2372 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2373 move_msr_up(vmx, index, save_nmsrs++);
2375 * MSR_STAR is only needed on long mode guests, and only
2376 * if efer.sce is enabled.
2378 index = __find_msr_index(vmx, MSR_STAR);
2379 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2380 move_msr_up(vmx, index, save_nmsrs++);
2383 index = __find_msr_index(vmx, MSR_EFER);
2384 if (index >= 0 && update_transition_efer(vmx, index))
2385 move_msr_up(vmx, index, save_nmsrs++);
2387 vmx->save_nmsrs = save_nmsrs;
2389 if (cpu_has_vmx_msr_bitmap())
2390 vmx_set_msr_bitmap(&vmx->vcpu);
2394 * reads and returns guest's timestamp counter "register"
2395 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2396 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2398 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2400 u64 host_tsc, tsc_offset;
2403 tsc_offset = vmcs_read64(TSC_OFFSET);
2404 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2408 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2409 * counter, even if a nested guest (L2) is currently running.
2411 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2415 tsc_offset = is_guest_mode(vcpu) ?
2416 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2417 vmcs_read64(TSC_OFFSET);
2418 return host_tsc + tsc_offset;
2421 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2423 return vmcs_read64(TSC_OFFSET);
2427 * writes 'offset' into guest's timestamp counter offset register
2429 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2431 if (is_guest_mode(vcpu)) {
2433 * We're here if L1 chose not to trap WRMSR to TSC. According
2434 * to the spec, this should set L1's TSC; The offset that L1
2435 * set for L2 remains unchanged, and still needs to be added
2436 * to the newly set TSC to get L2's TSC.
2438 struct vmcs12 *vmcs12;
2439 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2440 /* recalculate vmcs02.TSC_OFFSET: */
2441 vmcs12 = get_vmcs12(vcpu);
2442 vmcs_write64(TSC_OFFSET, offset +
2443 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2444 vmcs12->tsc_offset : 0));
2446 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2447 vmcs_read64(TSC_OFFSET), offset);
2448 vmcs_write64(TSC_OFFSET, offset);
2452 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2454 u64 offset = vmcs_read64(TSC_OFFSET);
2456 vmcs_write64(TSC_OFFSET, offset + adjustment);
2457 if (is_guest_mode(vcpu)) {
2458 /* Even when running L2, the adjustment needs to apply to L1 */
2459 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2461 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2462 offset + adjustment);
2465 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2467 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2468 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2472 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2473 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2474 * all guests if the "nested" module option is off, and can also be disabled
2475 * for a single guest by disabling its VMX cpuid bit.
2477 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2479 return nested && guest_cpuid_has_vmx(vcpu);
2483 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2484 * returned for the various VMX controls MSRs when nested VMX is enabled.
2485 * The same values should also be used to verify that vmcs12 control fields are
2486 * valid during nested entry from L1 to L2.
2487 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2488 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2489 * bit in the high half is on if the corresponding bit in the control field
2490 * may be on. See also vmx_control_verify().
2492 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2495 * Note that as a general rule, the high half of the MSRs (bits in
2496 * the control fields which may be 1) should be initialized by the
2497 * intersection of the underlying hardware's MSR (i.e., features which
2498 * can be supported) and the list of features we want to expose -
2499 * because they are known to be properly supported in our code.
2500 * Also, usually, the low half of the MSRs (bits which must be 1) can
2501 * be set to 0, meaning that L1 may turn off any of these bits. The
2502 * reason is that if one of these bits is necessary, it will appear
2503 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2504 * fields of vmcs01 and vmcs02, will turn these bits off - and
2505 * nested_vmx_exit_handled() will not pass related exits to L1.
2506 * These rules have exceptions below.
2509 /* pin-based controls */
2510 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2511 vmx->nested.nested_vmx_pinbased_ctls_low,
2512 vmx->nested.nested_vmx_pinbased_ctls_high);
2513 vmx->nested.nested_vmx_pinbased_ctls_low |=
2514 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2515 vmx->nested.nested_vmx_pinbased_ctls_high &=
2516 PIN_BASED_EXT_INTR_MASK |
2517 PIN_BASED_NMI_EXITING |
2518 PIN_BASED_VIRTUAL_NMIS;
2519 vmx->nested.nested_vmx_pinbased_ctls_high |=
2520 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2521 PIN_BASED_VMX_PREEMPTION_TIMER;
2522 if (vmx_cpu_uses_apicv(&vmx->vcpu))
2523 vmx->nested.nested_vmx_pinbased_ctls_high |=
2524 PIN_BASED_POSTED_INTR;
2527 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2528 vmx->nested.nested_vmx_exit_ctls_low,
2529 vmx->nested.nested_vmx_exit_ctls_high);
2530 vmx->nested.nested_vmx_exit_ctls_low =
2531 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2533 vmx->nested.nested_vmx_exit_ctls_high &=
2534 #ifdef CONFIG_X86_64
2535 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2537 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2538 vmx->nested.nested_vmx_exit_ctls_high |=
2539 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2540 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2541 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2543 if (vmx_mpx_supported())
2544 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2546 /* We support free control of debug control saving. */
2547 vmx->nested.nested_vmx_true_exit_ctls_low =
2548 vmx->nested.nested_vmx_exit_ctls_low &
2549 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2551 /* entry controls */
2552 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2553 vmx->nested.nested_vmx_entry_ctls_low,
2554 vmx->nested.nested_vmx_entry_ctls_high);
2555 vmx->nested.nested_vmx_entry_ctls_low =
2556 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2557 vmx->nested.nested_vmx_entry_ctls_high &=
2558 #ifdef CONFIG_X86_64
2559 VM_ENTRY_IA32E_MODE |
2561 VM_ENTRY_LOAD_IA32_PAT;
2562 vmx->nested.nested_vmx_entry_ctls_high |=
2563 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2564 if (vmx_mpx_supported())
2565 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2567 /* We support free control of debug control loading. */
2568 vmx->nested.nested_vmx_true_entry_ctls_low =
2569 vmx->nested.nested_vmx_entry_ctls_low &
2570 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2572 /* cpu-based controls */
2573 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2574 vmx->nested.nested_vmx_procbased_ctls_low,
2575 vmx->nested.nested_vmx_procbased_ctls_high);
2576 vmx->nested.nested_vmx_procbased_ctls_low =
2577 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2578 vmx->nested.nested_vmx_procbased_ctls_high &=
2579 CPU_BASED_VIRTUAL_INTR_PENDING |
2580 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2581 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2582 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2583 CPU_BASED_CR3_STORE_EXITING |
2584 #ifdef CONFIG_X86_64
2585 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2587 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2588 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2589 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2590 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2591 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2593 * We can allow some features even when not supported by the
2594 * hardware. For example, L1 can specify an MSR bitmap - and we
2595 * can use it to avoid exits to L1 - even when L0 runs L2
2596 * without MSR bitmaps.
2598 vmx->nested.nested_vmx_procbased_ctls_high |=
2599 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2600 CPU_BASED_USE_MSR_BITMAPS;
2602 /* We support free control of CR3 access interception. */
2603 vmx->nested.nested_vmx_true_procbased_ctls_low =
2604 vmx->nested.nested_vmx_procbased_ctls_low &
2605 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2607 /* secondary cpu-based controls */
2608 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2609 vmx->nested.nested_vmx_secondary_ctls_low,
2610 vmx->nested.nested_vmx_secondary_ctls_high);
2611 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2612 vmx->nested.nested_vmx_secondary_ctls_high &=
2613 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2614 SECONDARY_EXEC_RDTSCP |
2615 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2616 SECONDARY_EXEC_ENABLE_VPID |
2617 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2618 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2619 SECONDARY_EXEC_WBINVD_EXITING |
2620 SECONDARY_EXEC_XSAVES |
2621 SECONDARY_EXEC_PCOMMIT;
2624 /* nested EPT: emulate EPT also to L1 */
2625 vmx->nested.nested_vmx_secondary_ctls_high |=
2626 SECONDARY_EXEC_ENABLE_EPT;
2627 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2628 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2630 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2632 * For nested guests, we don't do anything specific
2633 * for single context invalidation. Hence, only advertise
2634 * support for global context invalidation.
2636 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2638 vmx->nested.nested_vmx_ept_caps = 0;
2641 * Old versions of KVM use the single-context version without
2642 * checking for support, so declare that it is supported even
2643 * though it is treated as global context. The alternative is
2644 * not failing the single-context invvpid, and it is worse.
2647 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2648 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2649 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2651 vmx->nested.nested_vmx_vpid_caps = 0;
2653 if (enable_unrestricted_guest)
2654 vmx->nested.nested_vmx_secondary_ctls_high |=
2655 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2657 /* miscellaneous data */
2658 rdmsr(MSR_IA32_VMX_MISC,
2659 vmx->nested.nested_vmx_misc_low,
2660 vmx->nested.nested_vmx_misc_high);
2661 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2662 vmx->nested.nested_vmx_misc_low |=
2663 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2664 VMX_MISC_ACTIVITY_HLT;
2665 vmx->nested.nested_vmx_misc_high = 0;
2668 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2671 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2673 return ((control & high) | low) == control;
2676 static inline u64 vmx_control_msr(u32 low, u32 high)
2678 return low | ((u64)high << 32);
2681 /* Returns 0 on success, non-0 otherwise. */
2682 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2684 struct vcpu_vmx *vmx = to_vmx(vcpu);
2686 switch (msr_index) {
2687 case MSR_IA32_VMX_BASIC:
2689 * This MSR reports some information about VMX support. We
2690 * should return information about the VMX we emulate for the
2691 * guest, and the VMCS structure we give it - not about the
2692 * VMX support of the underlying hardware.
2694 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2695 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2696 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2698 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2699 case MSR_IA32_VMX_PINBASED_CTLS:
2700 *pdata = vmx_control_msr(
2701 vmx->nested.nested_vmx_pinbased_ctls_low,
2702 vmx->nested.nested_vmx_pinbased_ctls_high);
2704 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2705 *pdata = vmx_control_msr(
2706 vmx->nested.nested_vmx_true_procbased_ctls_low,
2707 vmx->nested.nested_vmx_procbased_ctls_high);
2709 case MSR_IA32_VMX_PROCBASED_CTLS:
2710 *pdata = vmx_control_msr(
2711 vmx->nested.nested_vmx_procbased_ctls_low,
2712 vmx->nested.nested_vmx_procbased_ctls_high);
2714 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2715 *pdata = vmx_control_msr(
2716 vmx->nested.nested_vmx_true_exit_ctls_low,
2717 vmx->nested.nested_vmx_exit_ctls_high);
2719 case MSR_IA32_VMX_EXIT_CTLS:
2720 *pdata = vmx_control_msr(
2721 vmx->nested.nested_vmx_exit_ctls_low,
2722 vmx->nested.nested_vmx_exit_ctls_high);
2724 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2725 *pdata = vmx_control_msr(
2726 vmx->nested.nested_vmx_true_entry_ctls_low,
2727 vmx->nested.nested_vmx_entry_ctls_high);
2729 case MSR_IA32_VMX_ENTRY_CTLS:
2730 *pdata = vmx_control_msr(
2731 vmx->nested.nested_vmx_entry_ctls_low,
2732 vmx->nested.nested_vmx_entry_ctls_high);
2734 case MSR_IA32_VMX_MISC:
2735 *pdata = vmx_control_msr(
2736 vmx->nested.nested_vmx_misc_low,
2737 vmx->nested.nested_vmx_misc_high);
2740 * These MSRs specify bits which the guest must keep fixed (on or off)
2741 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2742 * We picked the standard core2 setting.
2744 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2745 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2746 case MSR_IA32_VMX_CR0_FIXED0:
2747 *pdata = VMXON_CR0_ALWAYSON;
2749 case MSR_IA32_VMX_CR0_FIXED1:
2752 case MSR_IA32_VMX_CR4_FIXED0:
2753 *pdata = VMXON_CR4_ALWAYSON;
2755 case MSR_IA32_VMX_CR4_FIXED1:
2758 case MSR_IA32_VMX_VMCS_ENUM:
2759 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2761 case MSR_IA32_VMX_PROCBASED_CTLS2:
2762 *pdata = vmx_control_msr(
2763 vmx->nested.nested_vmx_secondary_ctls_low,
2764 vmx->nested.nested_vmx_secondary_ctls_high);
2766 case MSR_IA32_VMX_EPT_VPID_CAP:
2767 /* Currently, no nested vpid support */
2768 *pdata = vmx->nested.nested_vmx_ept_caps |
2769 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2779 * Reads an msr value (of 'msr_index') into 'pdata'.
2780 * Returns 0 on success, non-0 otherwise.
2781 * Assumes vcpu_load() was already called.
2783 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2785 struct shared_msr_entry *msr;
2787 switch (msr_info->index) {
2788 #ifdef CONFIG_X86_64
2790 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2793 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2795 case MSR_KERNEL_GS_BASE:
2796 vmx_load_host_state(to_vmx(vcpu));
2797 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2801 return kvm_get_msr_common(vcpu, msr_info);
2803 msr_info->data = guest_read_tsc(vcpu);
2805 case MSR_IA32_SYSENTER_CS:
2806 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2808 case MSR_IA32_SYSENTER_EIP:
2809 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2811 case MSR_IA32_SYSENTER_ESP:
2812 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2814 case MSR_IA32_BNDCFGS:
2815 if (!vmx_mpx_supported())
2817 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2819 case MSR_IA32_FEATURE_CONTROL:
2820 if (!nested_vmx_allowed(vcpu))
2822 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2824 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2825 if (!nested_vmx_allowed(vcpu))
2827 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2829 if (!vmx_xsaves_supported())
2831 msr_info->data = vcpu->arch.ia32_xss;
2834 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2836 /* Otherwise falls through */
2838 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2840 msr_info->data = msr->data;
2843 return kvm_get_msr_common(vcpu, msr_info);
2849 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2852 * Writes msr value into into the appropriate "register".
2853 * Returns 0 on success, non-0 otherwise.
2854 * Assumes vcpu_load() was already called.
2856 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2858 struct vcpu_vmx *vmx = to_vmx(vcpu);
2859 struct shared_msr_entry *msr;
2861 u32 msr_index = msr_info->index;
2862 u64 data = msr_info->data;
2864 switch (msr_index) {
2866 ret = kvm_set_msr_common(vcpu, msr_info);
2868 #ifdef CONFIG_X86_64
2870 vmx_segment_cache_clear(vmx);
2871 vmcs_writel(GUEST_FS_BASE, data);
2874 vmx_segment_cache_clear(vmx);
2875 vmcs_writel(GUEST_GS_BASE, data);
2877 case MSR_KERNEL_GS_BASE:
2878 vmx_load_host_state(vmx);
2879 vmx->msr_guest_kernel_gs_base = data;
2882 case MSR_IA32_SYSENTER_CS:
2883 vmcs_write32(GUEST_SYSENTER_CS, data);
2885 case MSR_IA32_SYSENTER_EIP:
2886 vmcs_writel(GUEST_SYSENTER_EIP, data);
2888 case MSR_IA32_SYSENTER_ESP:
2889 vmcs_writel(GUEST_SYSENTER_ESP, data);
2891 case MSR_IA32_BNDCFGS:
2892 if (!vmx_mpx_supported())
2894 vmcs_write64(GUEST_BNDCFGS, data);
2897 kvm_write_tsc(vcpu, msr_info);
2899 case MSR_IA32_CR_PAT:
2900 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2901 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2903 vmcs_write64(GUEST_IA32_PAT, data);
2904 vcpu->arch.pat = data;
2907 ret = kvm_set_msr_common(vcpu, msr_info);
2909 case MSR_IA32_TSC_ADJUST:
2910 ret = kvm_set_msr_common(vcpu, msr_info);
2912 case MSR_IA32_FEATURE_CONTROL:
2913 if (!nested_vmx_allowed(vcpu) ||
2914 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2915 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2917 vmx->nested.msr_ia32_feature_control = data;
2918 if (msr_info->host_initiated && data == 0)
2919 vmx_leave_nested(vcpu);
2921 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2922 return 1; /* they are read-only */
2924 if (!vmx_xsaves_supported())
2927 * The only supported bit as of Skylake is bit 8, but
2928 * it is not supported on KVM.
2932 vcpu->arch.ia32_xss = data;
2933 if (vcpu->arch.ia32_xss != host_xss)
2934 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2935 vcpu->arch.ia32_xss, host_xss);
2937 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2940 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2942 /* Check reserved bit, higher 32 bits should be zero */
2943 if ((data >> 32) != 0)
2945 /* Otherwise falls through */
2947 msr = find_msr_entry(vmx, msr_index);
2949 u64 old_msr_data = msr->data;
2951 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2953 ret = kvm_set_shared_msr(msr->index, msr->data,
2957 msr->data = old_msr_data;
2961 ret = kvm_set_msr_common(vcpu, msr_info);
2967 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2969 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2972 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2975 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2977 case VCPU_EXREG_PDPTR:
2979 ept_save_pdptrs(vcpu);
2986 static __init int cpu_has_kvm_support(void)
2988 return cpu_has_vmx();
2991 static __init int vmx_disabled_by_bios(void)
2995 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2996 if (msr & FEATURE_CONTROL_LOCKED) {
2997 /* launched w/ TXT and VMX disabled */
2998 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3001 /* launched w/o TXT and VMX only enabled w/ TXT */
3002 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3003 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3004 && !tboot_enabled()) {
3005 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3006 "activate TXT before enabling KVM\n");
3009 /* launched w/o TXT and VMX disabled */
3010 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3011 && !tboot_enabled())
3018 static void kvm_cpu_vmxon(u64 addr)
3020 asm volatile (ASM_VMX_VMXON_RAX
3021 : : "a"(&addr), "m"(addr)
3025 static int hardware_enable(void)
3027 int cpu = raw_smp_processor_id();
3028 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3031 if (cr4_read_shadow() & X86_CR4_VMXE)
3034 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3035 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3036 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3039 * Now we can enable the vmclear operation in kdump
3040 * since the loaded_vmcss_on_cpu list on this cpu
3041 * has been initialized.
3043 * Though the cpu is not in VMX operation now, there
3044 * is no problem to enable the vmclear operation
3045 * for the loaded_vmcss_on_cpu list is empty!
3047 crash_enable_local_vmclear(cpu);
3049 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3051 test_bits = FEATURE_CONTROL_LOCKED;
3052 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3053 if (tboot_enabled())
3054 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3056 if ((old & test_bits) != test_bits) {
3057 /* enable and lock */
3058 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3060 cr4_set_bits(X86_CR4_VMXE);
3062 if (vmm_exclusive) {
3063 kvm_cpu_vmxon(phys_addr);
3067 native_store_gdt(this_cpu_ptr(&host_gdt));
3072 static void vmclear_local_loaded_vmcss(void)
3074 int cpu = raw_smp_processor_id();
3075 struct loaded_vmcs *v, *n;
3077 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3078 loaded_vmcss_on_cpu_link)
3079 __loaded_vmcs_clear(v);
3083 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3086 static void kvm_cpu_vmxoff(void)
3088 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3091 static void hardware_disable(void)
3093 if (vmm_exclusive) {
3094 vmclear_local_loaded_vmcss();
3097 cr4_clear_bits(X86_CR4_VMXE);
3100 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3101 u32 msr, u32 *result)
3103 u32 vmx_msr_low, vmx_msr_high;
3104 u32 ctl = ctl_min | ctl_opt;
3106 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3108 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3109 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3111 /* Ensure minimum (required) set of control bits are supported. */
3119 static __init bool allow_1_setting(u32 msr, u32 ctl)
3121 u32 vmx_msr_low, vmx_msr_high;
3123 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3124 return vmx_msr_high & ctl;
3127 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3129 u32 vmx_msr_low, vmx_msr_high;
3130 u32 min, opt, min2, opt2;
3131 u32 _pin_based_exec_control = 0;
3132 u32 _cpu_based_exec_control = 0;
3133 u32 _cpu_based_2nd_exec_control = 0;
3134 u32 _vmexit_control = 0;
3135 u32 _vmentry_control = 0;
3137 min = CPU_BASED_HLT_EXITING |
3138 #ifdef CONFIG_X86_64
3139 CPU_BASED_CR8_LOAD_EXITING |
3140 CPU_BASED_CR8_STORE_EXITING |
3142 CPU_BASED_CR3_LOAD_EXITING |
3143 CPU_BASED_CR3_STORE_EXITING |
3144 CPU_BASED_USE_IO_BITMAPS |
3145 CPU_BASED_MOV_DR_EXITING |
3146 CPU_BASED_USE_TSC_OFFSETING |
3147 CPU_BASED_MWAIT_EXITING |
3148 CPU_BASED_MONITOR_EXITING |
3149 CPU_BASED_INVLPG_EXITING |
3150 CPU_BASED_RDPMC_EXITING;
3152 opt = CPU_BASED_TPR_SHADOW |
3153 CPU_BASED_USE_MSR_BITMAPS |
3154 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3155 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3156 &_cpu_based_exec_control) < 0)
3158 #ifdef CONFIG_X86_64
3159 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3160 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3161 ~CPU_BASED_CR8_STORE_EXITING;
3163 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3165 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3166 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3167 SECONDARY_EXEC_WBINVD_EXITING |
3168 SECONDARY_EXEC_ENABLE_VPID |
3169 SECONDARY_EXEC_ENABLE_EPT |
3170 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3171 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3172 SECONDARY_EXEC_RDTSCP |
3173 SECONDARY_EXEC_ENABLE_INVPCID |
3174 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3175 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3176 SECONDARY_EXEC_SHADOW_VMCS |
3177 SECONDARY_EXEC_XSAVES |
3178 SECONDARY_EXEC_ENABLE_PML |
3179 SECONDARY_EXEC_PCOMMIT |
3180 SECONDARY_EXEC_TSC_SCALING;
3181 if (adjust_vmx_controls(min2, opt2,
3182 MSR_IA32_VMX_PROCBASED_CTLS2,
3183 &_cpu_based_2nd_exec_control) < 0)
3186 #ifndef CONFIG_X86_64
3187 if (!(_cpu_based_2nd_exec_control &
3188 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3189 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3192 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3193 _cpu_based_2nd_exec_control &= ~(
3194 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3195 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3196 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3198 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3199 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3201 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3202 CPU_BASED_CR3_STORE_EXITING |
3203 CPU_BASED_INVLPG_EXITING);
3204 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3205 vmx_capability.ept, vmx_capability.vpid);
3208 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3209 #ifdef CONFIG_X86_64
3210 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3212 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3213 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3214 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3215 &_vmexit_control) < 0)
3218 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3219 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3220 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3221 &_pin_based_exec_control) < 0)
3224 if (!(_cpu_based_2nd_exec_control &
3225 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3226 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3227 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3229 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3230 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3231 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3232 &_vmentry_control) < 0)
3235 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3237 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3238 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3241 #ifdef CONFIG_X86_64
3242 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3243 if (vmx_msr_high & (1u<<16))
3247 /* Require Write-Back (WB) memory type for VMCS accesses. */
3248 if (((vmx_msr_high >> 18) & 15) != 6)
3251 vmcs_conf->size = vmx_msr_high & 0x1fff;
3252 vmcs_conf->order = get_order(vmcs_config.size);
3253 vmcs_conf->revision_id = vmx_msr_low;
3255 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3256 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3257 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3258 vmcs_conf->vmexit_ctrl = _vmexit_control;
3259 vmcs_conf->vmentry_ctrl = _vmentry_control;
3261 cpu_has_load_ia32_efer =
3262 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3263 VM_ENTRY_LOAD_IA32_EFER)
3264 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3265 VM_EXIT_LOAD_IA32_EFER);
3267 cpu_has_load_perf_global_ctrl =
3268 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3269 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3270 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3271 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3274 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3275 * but due to arrata below it can't be used. Workaround is to use
3276 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3278 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3283 * BC86,AAY89,BD102 (model 44)
3287 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3288 switch (boot_cpu_data.x86_model) {
3294 cpu_has_load_perf_global_ctrl = false;
3295 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3296 "does not work properly. Using workaround\n");
3304 rdmsrl(MSR_IA32_XSS, host_xss);
3309 static struct vmcs *alloc_vmcs_cpu(int cpu)
3311 int node = cpu_to_node(cpu);
3315 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3318 vmcs = page_address(pages);
3319 memset(vmcs, 0, vmcs_config.size);
3320 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3324 static struct vmcs *alloc_vmcs(void)
3326 return alloc_vmcs_cpu(raw_smp_processor_id());
3329 static void free_vmcs(struct vmcs *vmcs)
3331 free_pages((unsigned long)vmcs, vmcs_config.order);
3335 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3337 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3339 if (!loaded_vmcs->vmcs)
3341 loaded_vmcs_clear(loaded_vmcs);
3342 free_vmcs(loaded_vmcs->vmcs);
3343 loaded_vmcs->vmcs = NULL;
3346 static void free_kvm_area(void)
3350 for_each_possible_cpu(cpu) {
3351 free_vmcs(per_cpu(vmxarea, cpu));
3352 per_cpu(vmxarea, cpu) = NULL;
3356 static void init_vmcs_shadow_fields(void)
3360 /* No checks for read only fields yet */
3362 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3363 switch (shadow_read_write_fields[i]) {
3365 if (!vmx_mpx_supported())
3373 shadow_read_write_fields[j] =
3374 shadow_read_write_fields[i];
3377 max_shadow_read_write_fields = j;
3379 /* shadowed fields guest access without vmexit */
3380 for (i = 0; i < max_shadow_read_write_fields; i++) {
3381 clear_bit(shadow_read_write_fields[i],
3382 vmx_vmwrite_bitmap);
3383 clear_bit(shadow_read_write_fields[i],
3386 for (i = 0; i < max_shadow_read_only_fields; i++)
3387 clear_bit(shadow_read_only_fields[i],
3391 static __init int alloc_kvm_area(void)
3395 for_each_possible_cpu(cpu) {
3398 vmcs = alloc_vmcs_cpu(cpu);
3404 per_cpu(vmxarea, cpu) = vmcs;
3409 static bool emulation_required(struct kvm_vcpu *vcpu)
3411 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3414 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3415 struct kvm_segment *save)
3417 if (!emulate_invalid_guest_state) {
3419 * CS and SS RPL should be equal during guest entry according
3420 * to VMX spec, but in reality it is not always so. Since vcpu
3421 * is in the middle of the transition from real mode to
3422 * protected mode it is safe to assume that RPL 0 is a good
3425 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3426 save->selector &= ~SEGMENT_RPL_MASK;
3427 save->dpl = save->selector & SEGMENT_RPL_MASK;
3430 vmx_set_segment(vcpu, save, seg);
3433 static void enter_pmode(struct kvm_vcpu *vcpu)
3435 unsigned long flags;
3436 struct vcpu_vmx *vmx = to_vmx(vcpu);
3439 * Update real mode segment cache. It may be not up-to-date if sement
3440 * register was written while vcpu was in a guest mode.
3442 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3443 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3444 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3445 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3446 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3447 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3449 vmx->rmode.vm86_active = 0;
3451 vmx_segment_cache_clear(vmx);
3453 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3455 flags = vmcs_readl(GUEST_RFLAGS);
3456 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3457 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3458 vmcs_writel(GUEST_RFLAGS, flags);
3460 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3461 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3463 update_exception_bitmap(vcpu);
3465 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3466 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3467 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3468 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3469 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3470 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3473 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3475 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3476 struct kvm_segment var = *save;
3479 if (seg == VCPU_SREG_CS)
3482 if (!emulate_invalid_guest_state) {
3483 var.selector = var.base >> 4;
3484 var.base = var.base & 0xffff0;
3494 if (save->base & 0xf)
3495 printk_once(KERN_WARNING "kvm: segment base is not "
3496 "paragraph aligned when entering "
3497 "protected mode (seg=%d)", seg);
3500 vmcs_write16(sf->selector, var.selector);
3501 vmcs_write32(sf->base, var.base);
3502 vmcs_write32(sf->limit, var.limit);
3503 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3506 static void enter_rmode(struct kvm_vcpu *vcpu)
3508 unsigned long flags;
3509 struct vcpu_vmx *vmx = to_vmx(vcpu);
3511 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3512 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3513 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3514 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3515 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3516 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3517 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3519 vmx->rmode.vm86_active = 1;
3522 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3523 * vcpu. Warn the user that an update is overdue.
3525 if (!vcpu->kvm->arch.tss_addr)
3526 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3527 "called before entering vcpu\n");
3529 vmx_segment_cache_clear(vmx);
3531 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3532 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3533 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3535 flags = vmcs_readl(GUEST_RFLAGS);
3536 vmx->rmode.save_rflags = flags;
3538 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3540 vmcs_writel(GUEST_RFLAGS, flags);
3541 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3542 update_exception_bitmap(vcpu);
3544 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3545 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3546 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3547 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3548 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3549 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3551 kvm_mmu_reset_context(vcpu);
3554 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3556 struct vcpu_vmx *vmx = to_vmx(vcpu);
3557 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3563 * Force kernel_gs_base reloading before EFER changes, as control
3564 * of this msr depends on is_long_mode().
3566 vmx_load_host_state(to_vmx(vcpu));
3567 vcpu->arch.efer = efer;
3568 if (efer & EFER_LMA) {
3569 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3572 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3574 msr->data = efer & ~EFER_LME;
3579 #ifdef CONFIG_X86_64
3581 static void enter_lmode(struct kvm_vcpu *vcpu)
3585 vmx_segment_cache_clear(to_vmx(vcpu));
3587 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3588 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3589 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3591 vmcs_write32(GUEST_TR_AR_BYTES,
3592 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3593 | VMX_AR_TYPE_BUSY_64_TSS);
3595 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3598 static void exit_lmode(struct kvm_vcpu *vcpu)
3600 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3601 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3606 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3608 vpid_sync_context(vpid);
3610 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3612 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3616 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3618 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3621 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3623 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3625 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3626 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3629 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3631 if (enable_ept && is_paging(vcpu))
3632 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3633 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3636 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3638 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3640 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3641 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3644 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3646 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3648 if (!test_bit(VCPU_EXREG_PDPTR,
3649 (unsigned long *)&vcpu->arch.regs_dirty))
3652 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3653 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3654 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3655 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3656 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3660 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3662 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3664 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3665 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3666 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3667 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3668 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3671 __set_bit(VCPU_EXREG_PDPTR,
3672 (unsigned long *)&vcpu->arch.regs_avail);
3673 __set_bit(VCPU_EXREG_PDPTR,
3674 (unsigned long *)&vcpu->arch.regs_dirty);
3677 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3679 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3681 struct kvm_vcpu *vcpu)
3683 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3684 vmx_decache_cr3(vcpu);
3685 if (!(cr0 & X86_CR0_PG)) {
3686 /* From paging/starting to nonpaging */
3687 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3688 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3689 (CPU_BASED_CR3_LOAD_EXITING |
3690 CPU_BASED_CR3_STORE_EXITING));
3691 vcpu->arch.cr0 = cr0;
3692 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3693 } else if (!is_paging(vcpu)) {
3694 /* From nonpaging to paging */
3695 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3696 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3697 ~(CPU_BASED_CR3_LOAD_EXITING |
3698 CPU_BASED_CR3_STORE_EXITING));
3699 vcpu->arch.cr0 = cr0;
3700 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3703 if (!(cr0 & X86_CR0_WP))
3704 *hw_cr0 &= ~X86_CR0_WP;
3707 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3709 struct vcpu_vmx *vmx = to_vmx(vcpu);
3710 unsigned long hw_cr0;
3712 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3713 if (enable_unrestricted_guest)
3714 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3716 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3718 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3721 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3725 #ifdef CONFIG_X86_64
3726 if (vcpu->arch.efer & EFER_LME) {
3727 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3729 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3735 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3737 if (!vcpu->fpu_active)
3738 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3740 vmcs_writel(CR0_READ_SHADOW, cr0);
3741 vmcs_writel(GUEST_CR0, hw_cr0);
3742 vcpu->arch.cr0 = cr0;
3744 /* depends on vcpu->arch.cr0 to be set to a new value */
3745 vmx->emulation_required = emulation_required(vcpu);
3748 static u64 construct_eptp(unsigned long root_hpa)
3752 /* TODO write the value reading from MSR */
3753 eptp = VMX_EPT_DEFAULT_MT |
3754 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3755 if (enable_ept_ad_bits)
3756 eptp |= VMX_EPT_AD_ENABLE_BIT;
3757 eptp |= (root_hpa & PAGE_MASK);
3762 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3764 unsigned long guest_cr3;
3769 eptp = construct_eptp(cr3);
3770 vmcs_write64(EPT_POINTER, eptp);
3771 if (is_paging(vcpu) || is_guest_mode(vcpu))
3772 guest_cr3 = kvm_read_cr3(vcpu);
3774 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3775 ept_load_pdptrs(vcpu);
3778 vmx_flush_tlb(vcpu);
3779 vmcs_writel(GUEST_CR3, guest_cr3);
3782 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3785 * Pass through host's Machine Check Enable value to hw_cr4, which
3786 * is in force while we are in guest mode. Do not let guests control
3787 * this bit, even if host CR4.MCE == 0.
3789 unsigned long hw_cr4 =
3790 (cr4_read_shadow() & X86_CR4_MCE) |
3791 (cr4 & ~X86_CR4_MCE) |
3792 (to_vmx(vcpu)->rmode.vm86_active ?
3793 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3795 if (cr4 & X86_CR4_VMXE) {
3797 * To use VMXON (and later other VMX instructions), a guest
3798 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3799 * So basically the check on whether to allow nested VMX
3802 if (!nested_vmx_allowed(vcpu))
3805 if (to_vmx(vcpu)->nested.vmxon &&
3806 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3809 vcpu->arch.cr4 = cr4;
3811 if (!is_paging(vcpu)) {
3812 hw_cr4 &= ~X86_CR4_PAE;
3813 hw_cr4 |= X86_CR4_PSE;
3814 } else if (!(cr4 & X86_CR4_PAE)) {
3815 hw_cr4 &= ~X86_CR4_PAE;
3819 if (!enable_unrestricted_guest && !is_paging(vcpu))
3821 * SMEP/SMAP is disabled if CPU is in non-paging mode in
3822 * hardware. However KVM always uses paging mode without
3823 * unrestricted guest.
3824 * To emulate this behavior, SMEP/SMAP needs to be manually
3825 * disabled when guest switches to non-paging mode.
3827 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3829 vmcs_writel(CR4_READ_SHADOW, cr4);
3830 vmcs_writel(GUEST_CR4, hw_cr4);
3834 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3835 struct kvm_segment *var, int seg)
3837 struct vcpu_vmx *vmx = to_vmx(vcpu);
3840 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3841 *var = vmx->rmode.segs[seg];
3842 if (seg == VCPU_SREG_TR
3843 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3845 var->base = vmx_read_guest_seg_base(vmx, seg);
3846 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3849 var->base = vmx_read_guest_seg_base(vmx, seg);
3850 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3851 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3852 ar = vmx_read_guest_seg_ar(vmx, seg);
3853 var->unusable = (ar >> 16) & 1;
3854 var->type = ar & 15;
3855 var->s = (ar >> 4) & 1;
3856 var->dpl = (ar >> 5) & 3;
3858 * Some userspaces do not preserve unusable property. Since usable
3859 * segment has to be present according to VMX spec we can use present
3860 * property to amend userspace bug by making unusable segment always
3861 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3862 * segment as unusable.
3864 var->present = !var->unusable;
3865 var->avl = (ar >> 12) & 1;
3866 var->l = (ar >> 13) & 1;
3867 var->db = (ar >> 14) & 1;
3868 var->g = (ar >> 15) & 1;
3871 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3873 struct kvm_segment s;
3875 if (to_vmx(vcpu)->rmode.vm86_active) {
3876 vmx_get_segment(vcpu, &s, seg);
3879 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3882 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3884 struct vcpu_vmx *vmx = to_vmx(vcpu);
3886 if (unlikely(vmx->rmode.vm86_active))
3889 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3890 return VMX_AR_DPL(ar);
3894 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3898 if (var->unusable || !var->present)
3901 ar = var->type & 15;
3902 ar |= (var->s & 1) << 4;
3903 ar |= (var->dpl & 3) << 5;
3904 ar |= (var->present & 1) << 7;
3905 ar |= (var->avl & 1) << 12;
3906 ar |= (var->l & 1) << 13;
3907 ar |= (var->db & 1) << 14;
3908 ar |= (var->g & 1) << 15;
3914 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3915 struct kvm_segment *var, int seg)
3917 struct vcpu_vmx *vmx = to_vmx(vcpu);
3918 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3920 vmx_segment_cache_clear(vmx);
3922 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3923 vmx->rmode.segs[seg] = *var;
3924 if (seg == VCPU_SREG_TR)
3925 vmcs_write16(sf->selector, var->selector);
3927 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3931 vmcs_writel(sf->base, var->base);
3932 vmcs_write32(sf->limit, var->limit);
3933 vmcs_write16(sf->selector, var->selector);
3936 * Fix the "Accessed" bit in AR field of segment registers for older
3938 * IA32 arch specifies that at the time of processor reset the
3939 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3940 * is setting it to 0 in the userland code. This causes invalid guest
3941 * state vmexit when "unrestricted guest" mode is turned on.
3942 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3943 * tree. Newer qemu binaries with that qemu fix would not need this
3946 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3947 var->type |= 0x1; /* Accessed */
3949 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3952 vmx->emulation_required = emulation_required(vcpu);
3955 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3957 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3959 *db = (ar >> 14) & 1;
3960 *l = (ar >> 13) & 1;
3963 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3965 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3966 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3969 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3971 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3972 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3975 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3977 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3978 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3981 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3983 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3984 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3987 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3989 struct kvm_segment var;
3992 vmx_get_segment(vcpu, &var, seg);
3994 if (seg == VCPU_SREG_CS)
3996 ar = vmx_segment_access_rights(&var);
3998 if (var.base != (var.selector << 4))
4000 if (var.limit != 0xffff)
4008 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4010 struct kvm_segment cs;
4011 unsigned int cs_rpl;
4013 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4014 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4018 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4022 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4023 if (cs.dpl > cs_rpl)
4026 if (cs.dpl != cs_rpl)
4032 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4036 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4038 struct kvm_segment ss;
4039 unsigned int ss_rpl;
4041 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4042 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4046 if (ss.type != 3 && ss.type != 7)
4050 if (ss.dpl != ss_rpl) /* DPL != RPL */
4058 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4060 struct kvm_segment var;
4063 vmx_get_segment(vcpu, &var, seg);
4064 rpl = var.selector & SEGMENT_RPL_MASK;
4072 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4073 if (var.dpl < rpl) /* DPL < RPL */
4077 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4083 static bool tr_valid(struct kvm_vcpu *vcpu)
4085 struct kvm_segment tr;
4087 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4091 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4093 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4101 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4103 struct kvm_segment ldtr;
4105 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4109 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4119 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4121 struct kvm_segment cs, ss;
4123 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4124 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4126 return ((cs.selector & SEGMENT_RPL_MASK) ==
4127 (ss.selector & SEGMENT_RPL_MASK));
4131 * Check if guest state is valid. Returns true if valid, false if
4133 * We assume that registers are always usable
4135 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4137 if (enable_unrestricted_guest)
4140 /* real mode guest state checks */
4141 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4142 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4144 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4146 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4148 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4150 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4152 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4155 /* protected mode guest state checks */
4156 if (!cs_ss_rpl_check(vcpu))
4158 if (!code_segment_valid(vcpu))
4160 if (!stack_segment_valid(vcpu))
4162 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4164 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4166 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4168 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4170 if (!tr_valid(vcpu))
4172 if (!ldtr_valid(vcpu))
4176 * - Add checks on RIP
4177 * - Add checks on RFLAGS
4183 static int init_rmode_tss(struct kvm *kvm)
4189 idx = srcu_read_lock(&kvm->srcu);
4190 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4191 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4194 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4195 r = kvm_write_guest_page(kvm, fn++, &data,
4196 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4199 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4202 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4206 r = kvm_write_guest_page(kvm, fn, &data,
4207 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4210 srcu_read_unlock(&kvm->srcu, idx);
4214 static int init_rmode_identity_map(struct kvm *kvm)
4217 pfn_t identity_map_pfn;
4223 /* Protect kvm->arch.ept_identity_pagetable_done. */
4224 mutex_lock(&kvm->slots_lock);
4226 if (likely(kvm->arch.ept_identity_pagetable_done))
4229 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4231 r = alloc_identity_pagetable(kvm);
4235 idx = srcu_read_lock(&kvm->srcu);
4236 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4239 /* Set up identity-mapping pagetable for EPT in real mode */
4240 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4241 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4242 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4243 r = kvm_write_guest_page(kvm, identity_map_pfn,
4244 &tmp, i * sizeof(tmp), sizeof(tmp));
4248 kvm->arch.ept_identity_pagetable_done = true;
4251 srcu_read_unlock(&kvm->srcu, idx);
4254 mutex_unlock(&kvm->slots_lock);
4258 static void seg_setup(int seg)
4260 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4263 vmcs_write16(sf->selector, 0);
4264 vmcs_writel(sf->base, 0);
4265 vmcs_write32(sf->limit, 0xffff);
4267 if (seg == VCPU_SREG_CS)
4268 ar |= 0x08; /* code segment */
4270 vmcs_write32(sf->ar_bytes, ar);
4273 static int alloc_apic_access_page(struct kvm *kvm)
4278 mutex_lock(&kvm->slots_lock);
4279 if (kvm->arch.apic_access_page_done)
4281 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4282 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4286 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4287 if (is_error_page(page)) {
4293 * Do not pin the page in memory, so that memory hot-unplug
4294 * is able to migrate it.
4297 kvm->arch.apic_access_page_done = true;
4299 mutex_unlock(&kvm->slots_lock);
4303 static int alloc_identity_pagetable(struct kvm *kvm)
4305 /* Called with kvm->slots_lock held. */
4309 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4311 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4312 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4317 static int allocate_vpid(void)
4323 spin_lock(&vmx_vpid_lock);
4324 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4325 if (vpid < VMX_NR_VPIDS)
4326 __set_bit(vpid, vmx_vpid_bitmap);
4329 spin_unlock(&vmx_vpid_lock);
4333 static void free_vpid(int vpid)
4335 if (!enable_vpid || vpid == 0)
4337 spin_lock(&vmx_vpid_lock);
4338 __clear_bit(vpid, vmx_vpid_bitmap);
4339 spin_unlock(&vmx_vpid_lock);
4342 #define MSR_TYPE_R 1
4343 #define MSR_TYPE_W 2
4344 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4347 int f = sizeof(unsigned long);
4349 if (!cpu_has_vmx_msr_bitmap())
4353 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4354 * have the write-low and read-high bitmap offsets the wrong way round.
4355 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4357 if (msr <= 0x1fff) {
4358 if (type & MSR_TYPE_R)
4360 __clear_bit(msr, msr_bitmap + 0x000 / f);
4362 if (type & MSR_TYPE_W)
4364 __clear_bit(msr, msr_bitmap + 0x800 / f);
4366 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4368 if (type & MSR_TYPE_R)
4370 __clear_bit(msr, msr_bitmap + 0x400 / f);
4372 if (type & MSR_TYPE_W)
4374 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4379 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4382 int f = sizeof(unsigned long);
4384 if (!cpu_has_vmx_msr_bitmap())
4388 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4389 * have the write-low and read-high bitmap offsets the wrong way round.
4390 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4392 if (msr <= 0x1fff) {
4393 if (type & MSR_TYPE_R)
4395 __set_bit(msr, msr_bitmap + 0x000 / f);
4397 if (type & MSR_TYPE_W)
4399 __set_bit(msr, msr_bitmap + 0x800 / f);
4401 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4403 if (type & MSR_TYPE_R)
4405 __set_bit(msr, msr_bitmap + 0x400 / f);
4407 if (type & MSR_TYPE_W)
4409 __set_bit(msr, msr_bitmap + 0xc00 / f);
4415 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4416 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4418 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4419 unsigned long *msr_bitmap_nested,
4422 int f = sizeof(unsigned long);
4424 if (!cpu_has_vmx_msr_bitmap()) {
4430 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4431 * have the write-low and read-high bitmap offsets the wrong way round.
4432 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4434 if (msr <= 0x1fff) {
4435 if (type & MSR_TYPE_R &&
4436 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4438 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4440 if (type & MSR_TYPE_W &&
4441 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4443 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4445 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4447 if (type & MSR_TYPE_R &&
4448 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4450 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4452 if (type & MSR_TYPE_W &&
4453 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4455 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4460 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4463 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4464 msr, MSR_TYPE_R | MSR_TYPE_W);
4465 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4466 msr, MSR_TYPE_R | MSR_TYPE_W);
4469 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4471 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4473 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4477 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4479 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4481 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4485 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4487 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4489 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4493 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4495 return enable_apicv && lapic_in_kernel(vcpu);
4498 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4500 struct vcpu_vmx *vmx = to_vmx(vcpu);
4505 if (vmx->nested.pi_desc &&
4506 vmx->nested.pi_pending) {
4507 vmx->nested.pi_pending = false;
4508 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4511 max_irr = find_last_bit(
4512 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4517 vapic_page = kmap(vmx->nested.virtual_apic_page);
4522 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4523 kunmap(vmx->nested.virtual_apic_page);
4525 status = vmcs_read16(GUEST_INTR_STATUS);
4526 if ((u8)max_irr > ((u8)status & 0xff)) {
4528 status |= (u8)max_irr;
4529 vmcs_write16(GUEST_INTR_STATUS, status);
4535 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4538 if (vcpu->mode == IN_GUEST_MODE) {
4539 struct vcpu_vmx *vmx = to_vmx(vcpu);
4542 * Currently, we don't support urgent interrupt,
4543 * all interrupts are recognized as non-urgent
4544 * interrupt, so we cannot post interrupts when
4547 * If the vcpu is in guest mode, it means it is
4548 * running instead of being scheduled out and
4549 * waiting in the run queue, and that's the only
4550 * case when 'SN' is set currently, warning if
4553 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4555 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4556 POSTED_INTR_VECTOR);
4563 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4566 struct vcpu_vmx *vmx = to_vmx(vcpu);
4568 if (is_guest_mode(vcpu) &&
4569 vector == vmx->nested.posted_intr_nv) {
4570 /* the PIR and ON have been set by L1. */
4571 kvm_vcpu_trigger_posted_interrupt(vcpu);
4573 * If a posted intr is not recognized by hardware,
4574 * we will accomplish it in the next vmentry.
4576 vmx->nested.pi_pending = true;
4577 kvm_make_request(KVM_REQ_EVENT, vcpu);
4583 * Send interrupt to vcpu via posted interrupt way.
4584 * 1. If target vcpu is running(non-root mode), send posted interrupt
4585 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4586 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4587 * interrupt from PIR in next vmentry.
4589 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4591 struct vcpu_vmx *vmx = to_vmx(vcpu);
4594 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4598 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4601 r = pi_test_and_set_on(&vmx->pi_desc);
4602 kvm_make_request(KVM_REQ_EVENT, vcpu);
4603 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4604 kvm_vcpu_kick(vcpu);
4607 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4609 struct vcpu_vmx *vmx = to_vmx(vcpu);
4611 if (!pi_test_and_clear_on(&vmx->pi_desc))
4614 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4617 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4623 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4624 * will not change in the lifetime of the guest.
4625 * Note that host-state that does change is set elsewhere. E.g., host-state
4626 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4628 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4635 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4636 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4638 /* Save the most likely value for this task's CR4 in the VMCS. */
4639 cr4 = cr4_read_shadow();
4640 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4641 vmx->host_state.vmcs_host_cr4 = cr4;
4643 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4644 #ifdef CONFIG_X86_64
4646 * Load null selectors, so we can avoid reloading them in
4647 * __vmx_load_host_state(), in case userspace uses the null selectors
4648 * too (the expected case).
4650 vmcs_write16(HOST_DS_SELECTOR, 0);
4651 vmcs_write16(HOST_ES_SELECTOR, 0);
4653 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4654 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4656 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4657 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4659 native_store_idt(&dt);
4660 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4661 vmx->host_idt_base = dt.address;
4663 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4665 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4666 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4667 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4668 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4670 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4671 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4672 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4676 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4678 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4680 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4681 if (is_guest_mode(&vmx->vcpu))
4682 vmx->vcpu.arch.cr4_guest_owned_bits &=
4683 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4684 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4687 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4689 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4691 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4692 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4693 return pin_based_exec_ctrl;
4696 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4698 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4700 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4701 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4703 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4704 exec_control &= ~CPU_BASED_TPR_SHADOW;
4705 #ifdef CONFIG_X86_64
4706 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4707 CPU_BASED_CR8_LOAD_EXITING;
4711 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4712 CPU_BASED_CR3_LOAD_EXITING |
4713 CPU_BASED_INVLPG_EXITING;
4714 return exec_control;
4717 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4719 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4720 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4721 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4723 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4725 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4726 enable_unrestricted_guest = 0;
4727 /* Enable INVPCID for non-ept guests may cause performance regression. */
4728 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4730 if (!enable_unrestricted_guest)
4731 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4733 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4734 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4735 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4736 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4737 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4738 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4740 We can NOT enable shadow_vmcs here because we don't have yet
4743 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4746 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4748 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4749 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4751 return exec_control;
4754 static void ept_set_mmio_spte_mask(void)
4757 * EPT Misconfigurations can be generated if the value of bits 2:0
4758 * of an EPT paging-structure entry is 110b (write/execute).
4759 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4762 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4765 #define VMX_XSS_EXIT_BITMAP 0
4767 * Sets up the vmcs for emulated real mode.
4769 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4771 #ifdef CONFIG_X86_64
4777 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4778 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4780 if (enable_shadow_vmcs) {
4781 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4782 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4784 if (cpu_has_vmx_msr_bitmap())
4785 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4787 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4790 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4792 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4794 if (cpu_has_secondary_exec_ctrls())
4795 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4796 vmx_secondary_exec_control(vmx));
4798 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4799 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4800 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4801 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4802 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4804 vmcs_write16(GUEST_INTR_STATUS, 0);
4806 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4807 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4811 vmcs_write32(PLE_GAP, ple_gap);
4812 vmx->ple_window = ple_window;
4813 vmx->ple_window_dirty = true;
4816 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4817 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4818 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4820 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4821 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4822 vmx_set_constant_host_state(vmx);
4823 #ifdef CONFIG_X86_64
4824 rdmsrl(MSR_FS_BASE, a);
4825 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4826 rdmsrl(MSR_GS_BASE, a);
4827 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4829 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4830 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4833 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4834 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4835 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4836 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4837 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4839 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4840 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4842 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4843 u32 index = vmx_msr_index[i];
4844 u32 data_low, data_high;
4847 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4849 if (wrmsr_safe(index, data_low, data_high) < 0)
4851 vmx->guest_msrs[j].index = i;
4852 vmx->guest_msrs[j].data = 0;
4853 vmx->guest_msrs[j].mask = -1ull;
4858 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4860 /* 22.2.1, 20.8.1 */
4861 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4863 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4864 set_cr4_guest_host_mask(vmx);
4866 if (vmx_xsaves_supported())
4867 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4872 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4874 struct vcpu_vmx *vmx = to_vmx(vcpu);
4875 struct msr_data apic_base_msr;
4878 vmx->rmode.vm86_active = 0;
4880 vmx->soft_vnmi_blocked = 0;
4882 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4883 kvm_set_cr8(vcpu, 0);
4886 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4887 MSR_IA32_APICBASE_ENABLE;
4888 if (kvm_vcpu_is_reset_bsp(vcpu))
4889 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4890 apic_base_msr.host_initiated = true;
4891 kvm_set_apic_base(vcpu, &apic_base_msr);
4894 vmx_segment_cache_clear(vmx);
4896 seg_setup(VCPU_SREG_CS);
4897 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4898 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4900 seg_setup(VCPU_SREG_DS);
4901 seg_setup(VCPU_SREG_ES);
4902 seg_setup(VCPU_SREG_FS);
4903 seg_setup(VCPU_SREG_GS);
4904 seg_setup(VCPU_SREG_SS);
4906 vmcs_write16(GUEST_TR_SELECTOR, 0);
4907 vmcs_writel(GUEST_TR_BASE, 0);
4908 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4909 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4911 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4912 vmcs_writel(GUEST_LDTR_BASE, 0);
4913 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4914 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4917 vmcs_write32(GUEST_SYSENTER_CS, 0);
4918 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4919 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4920 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4923 vmcs_writel(GUEST_RFLAGS, 0x02);
4924 kvm_rip_write(vcpu, 0xfff0);
4926 vmcs_writel(GUEST_GDTR_BASE, 0);
4927 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4929 vmcs_writel(GUEST_IDTR_BASE, 0);
4930 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4932 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4933 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4934 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4938 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4940 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4941 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4942 if (cpu_need_tpr_shadow(vcpu))
4943 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4944 __pa(vcpu->arch.apic->regs));
4945 vmcs_write32(TPR_THRESHOLD, 0);
4948 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4950 if (vmx_cpu_uses_apicv(vcpu))
4951 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4954 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4956 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4957 vmx->vcpu.arch.cr0 = cr0;
4958 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4959 vmx_set_cr4(vcpu, 0);
4960 vmx_set_efer(vcpu, 0);
4961 vmx_fpu_activate(vcpu);
4962 update_exception_bitmap(vcpu);
4964 vpid_sync_context(vmx->vpid);
4968 * In nested virtualization, check if L1 asked to exit on external interrupts.
4969 * For most existing hypervisors, this will always return true.
4971 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4973 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4974 PIN_BASED_EXT_INTR_MASK;
4978 * In nested virtualization, check if L1 has set
4979 * VM_EXIT_ACK_INTR_ON_EXIT
4981 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4983 return get_vmcs12(vcpu)->vm_exit_controls &
4984 VM_EXIT_ACK_INTR_ON_EXIT;
4987 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4989 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4990 PIN_BASED_NMI_EXITING;
4993 static void enable_irq_window(struct kvm_vcpu *vcpu)
4995 u32 cpu_based_vm_exec_control;
4997 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4998 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4999 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5002 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5004 u32 cpu_based_vm_exec_control;
5006 if (!cpu_has_virtual_nmis() ||
5007 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5008 enable_irq_window(vcpu);
5012 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5013 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5014 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5017 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5019 struct vcpu_vmx *vmx = to_vmx(vcpu);
5021 int irq = vcpu->arch.interrupt.nr;
5023 trace_kvm_inj_virq(irq);
5025 ++vcpu->stat.irq_injections;
5026 if (vmx->rmode.vm86_active) {
5028 if (vcpu->arch.interrupt.soft)
5029 inc_eip = vcpu->arch.event_exit_inst_len;
5030 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5031 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5034 intr = irq | INTR_INFO_VALID_MASK;
5035 if (vcpu->arch.interrupt.soft) {
5036 intr |= INTR_TYPE_SOFT_INTR;
5037 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5038 vmx->vcpu.arch.event_exit_inst_len);
5040 intr |= INTR_TYPE_EXT_INTR;
5041 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5044 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5046 struct vcpu_vmx *vmx = to_vmx(vcpu);
5048 if (is_guest_mode(vcpu))
5051 if (!cpu_has_virtual_nmis()) {
5053 * Tracking the NMI-blocked state in software is built upon
5054 * finding the next open IRQ window. This, in turn, depends on
5055 * well-behaving guests: They have to keep IRQs disabled at
5056 * least as long as the NMI handler runs. Otherwise we may
5057 * cause NMI nesting, maybe breaking the guest. But as this is
5058 * highly unlikely, we can live with the residual risk.
5060 vmx->soft_vnmi_blocked = 1;
5061 vmx->vnmi_blocked_time = 0;
5064 ++vcpu->stat.nmi_injections;
5065 vmx->nmi_known_unmasked = false;
5066 if (vmx->rmode.vm86_active) {
5067 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5068 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5071 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5072 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5075 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5077 if (!cpu_has_virtual_nmis())
5078 return to_vmx(vcpu)->soft_vnmi_blocked;
5079 if (to_vmx(vcpu)->nmi_known_unmasked)
5081 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5084 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5086 struct vcpu_vmx *vmx = to_vmx(vcpu);
5088 if (!cpu_has_virtual_nmis()) {
5089 if (vmx->soft_vnmi_blocked != masked) {
5090 vmx->soft_vnmi_blocked = masked;
5091 vmx->vnmi_blocked_time = 0;
5094 vmx->nmi_known_unmasked = !masked;
5096 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5097 GUEST_INTR_STATE_NMI);
5099 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5100 GUEST_INTR_STATE_NMI);
5104 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5106 if (to_vmx(vcpu)->nested.nested_run_pending)
5109 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5112 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5113 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5114 | GUEST_INTR_STATE_NMI));
5117 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5119 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5120 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5121 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5122 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5125 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5129 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5133 kvm->arch.tss_addr = addr;
5134 return init_rmode_tss(kvm);
5137 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5142 * Update instruction length as we may reinject the exception
5143 * from user space while in guest debugging mode.
5145 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5146 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5147 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5151 if (vcpu->guest_debug &
5152 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5169 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5170 int vec, u32 err_code)
5173 * Instruction with address size override prefix opcode 0x67
5174 * Cause the #SS fault with 0 error code in VM86 mode.
5176 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5177 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5178 if (vcpu->arch.halt_request) {
5179 vcpu->arch.halt_request = 0;
5180 return kvm_vcpu_halt(vcpu);
5188 * Forward all other exceptions that are valid in real mode.
5189 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5190 * the required debugging infrastructure rework.
5192 kvm_queue_exception(vcpu, vec);
5197 * Trigger machine check on the host. We assume all the MSRs are already set up
5198 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5199 * We pass a fake environment to the machine check handler because we want
5200 * the guest to be always treated like user space, no matter what context
5201 * it used internally.
5203 static void kvm_machine_check(void)
5205 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5206 struct pt_regs regs = {
5207 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5208 .flags = X86_EFLAGS_IF,
5211 do_machine_check(®s, 0);
5215 static int handle_machine_check(struct kvm_vcpu *vcpu)
5217 /* already handled by vcpu_run */
5221 static int handle_exception(struct kvm_vcpu *vcpu)
5223 struct vcpu_vmx *vmx = to_vmx(vcpu);
5224 struct kvm_run *kvm_run = vcpu->run;
5225 u32 intr_info, ex_no, error_code;
5226 unsigned long cr2, rip, dr6;
5228 enum emulation_result er;
5230 vect_info = vmx->idt_vectoring_info;
5231 intr_info = vmx->exit_intr_info;
5233 if (is_machine_check(intr_info))
5234 return handle_machine_check(vcpu);
5236 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5237 return 1; /* already handled by vmx_vcpu_run() */
5239 if (is_no_device(intr_info)) {
5240 vmx_fpu_activate(vcpu);
5244 if (is_invalid_opcode(intr_info)) {
5245 if (is_guest_mode(vcpu)) {
5246 kvm_queue_exception(vcpu, UD_VECTOR);
5249 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5250 if (er != EMULATE_DONE)
5251 kvm_queue_exception(vcpu, UD_VECTOR);
5256 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5257 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5260 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5261 * MMIO, it is better to report an internal error.
5262 * See the comments in vmx_handle_exit.
5264 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5265 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5266 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5267 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5268 vcpu->run->internal.ndata = 3;
5269 vcpu->run->internal.data[0] = vect_info;
5270 vcpu->run->internal.data[1] = intr_info;
5271 vcpu->run->internal.data[2] = error_code;
5275 if (is_page_fault(intr_info)) {
5276 /* EPT won't cause page fault directly */
5278 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5279 trace_kvm_page_fault(cr2, error_code);
5281 if (kvm_event_needs_reinjection(vcpu))
5282 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5283 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5286 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5288 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5289 return handle_rmode_exception(vcpu, ex_no, error_code);
5293 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5296 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5297 if (!(vcpu->guest_debug &
5298 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5299 vcpu->arch.dr6 &= ~15;
5300 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5301 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5302 skip_emulated_instruction(vcpu);
5304 kvm_queue_exception(vcpu, DB_VECTOR);
5307 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5308 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5312 * Update instruction length as we may reinject #BP from
5313 * user space while in guest debugging mode. Reading it for
5314 * #DB as well causes no harm, it is not used in that case.
5316 vmx->vcpu.arch.event_exit_inst_len =
5317 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5318 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5319 rip = kvm_rip_read(vcpu);
5320 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5321 kvm_run->debug.arch.exception = ex_no;
5324 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5325 kvm_run->ex.exception = ex_no;
5326 kvm_run->ex.error_code = error_code;
5332 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5334 ++vcpu->stat.irq_exits;
5338 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5340 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5344 static int handle_io(struct kvm_vcpu *vcpu)
5346 unsigned long exit_qualification;
5347 int size, in, string;
5350 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5351 string = (exit_qualification & 16) != 0;
5352 in = (exit_qualification & 8) != 0;
5354 ++vcpu->stat.io_exits;
5357 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5359 port = exit_qualification >> 16;
5360 size = (exit_qualification & 7) + 1;
5361 skip_emulated_instruction(vcpu);
5363 return kvm_fast_pio_out(vcpu, size, port);
5367 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5370 * Patch in the VMCALL instruction:
5372 hypercall[0] = 0x0f;
5373 hypercall[1] = 0x01;
5374 hypercall[2] = 0xc1;
5377 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5379 unsigned long always_on = VMXON_CR0_ALWAYSON;
5380 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5382 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5383 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5384 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5385 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5386 return (val & always_on) == always_on;
5389 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5390 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5392 if (is_guest_mode(vcpu)) {
5393 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5394 unsigned long orig_val = val;
5397 * We get here when L2 changed cr0 in a way that did not change
5398 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5399 * but did change L0 shadowed bits. So we first calculate the
5400 * effective cr0 value that L1 would like to write into the
5401 * hardware. It consists of the L2-owned bits from the new
5402 * value combined with the L1-owned bits from L1's guest_cr0.
5404 val = (val & ~vmcs12->cr0_guest_host_mask) |
5405 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5407 if (!nested_cr0_valid(vcpu, val))
5410 if (kvm_set_cr0(vcpu, val))
5412 vmcs_writel(CR0_READ_SHADOW, orig_val);
5415 if (to_vmx(vcpu)->nested.vmxon &&
5416 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5418 return kvm_set_cr0(vcpu, val);
5422 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5424 if (is_guest_mode(vcpu)) {
5425 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5426 unsigned long orig_val = val;
5428 /* analogously to handle_set_cr0 */
5429 val = (val & ~vmcs12->cr4_guest_host_mask) |
5430 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5431 if (kvm_set_cr4(vcpu, val))
5433 vmcs_writel(CR4_READ_SHADOW, orig_val);
5436 return kvm_set_cr4(vcpu, val);
5439 /* called to set cr0 as approriate for clts instruction exit. */
5440 static void handle_clts(struct kvm_vcpu *vcpu)
5442 if (is_guest_mode(vcpu)) {
5444 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5445 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5446 * just pretend it's off (also in arch.cr0 for fpu_activate).
5448 vmcs_writel(CR0_READ_SHADOW,
5449 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5450 vcpu->arch.cr0 &= ~X86_CR0_TS;
5452 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5455 static int handle_cr(struct kvm_vcpu *vcpu)
5457 unsigned long exit_qualification, val;
5462 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5463 cr = exit_qualification & 15;
5464 reg = (exit_qualification >> 8) & 15;
5465 switch ((exit_qualification >> 4) & 3) {
5466 case 0: /* mov to cr */
5467 val = kvm_register_readl(vcpu, reg);
5468 trace_kvm_cr_write(cr, val);
5471 err = handle_set_cr0(vcpu, val);
5472 kvm_complete_insn_gp(vcpu, err);
5475 err = kvm_set_cr3(vcpu, val);
5476 kvm_complete_insn_gp(vcpu, err);
5479 err = handle_set_cr4(vcpu, val);
5480 kvm_complete_insn_gp(vcpu, err);
5483 u8 cr8_prev = kvm_get_cr8(vcpu);
5485 err = kvm_set_cr8(vcpu, cr8);
5486 kvm_complete_insn_gp(vcpu, err);
5487 if (lapic_in_kernel(vcpu))
5489 if (cr8_prev <= cr8)
5491 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5498 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5499 skip_emulated_instruction(vcpu);
5500 vmx_fpu_activate(vcpu);
5502 case 1: /*mov from cr*/
5505 val = kvm_read_cr3(vcpu);
5506 kvm_register_write(vcpu, reg, val);
5507 trace_kvm_cr_read(cr, val);
5508 skip_emulated_instruction(vcpu);
5511 val = kvm_get_cr8(vcpu);
5512 kvm_register_write(vcpu, reg, val);
5513 trace_kvm_cr_read(cr, val);
5514 skip_emulated_instruction(vcpu);
5519 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5520 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5521 kvm_lmsw(vcpu, val);
5523 skip_emulated_instruction(vcpu);
5528 vcpu->run->exit_reason = 0;
5529 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5530 (int)(exit_qualification >> 4) & 3, cr);
5534 static int handle_dr(struct kvm_vcpu *vcpu)
5536 unsigned long exit_qualification;
5539 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5540 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5542 /* First, if DR does not exist, trigger UD */
5543 if (!kvm_require_dr(vcpu, dr))
5546 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5547 if (!kvm_require_cpl(vcpu, 0))
5549 dr7 = vmcs_readl(GUEST_DR7);
5552 * As the vm-exit takes precedence over the debug trap, we
5553 * need to emulate the latter, either for the host or the
5554 * guest debugging itself.
5556 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5557 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5558 vcpu->run->debug.arch.dr7 = dr7;
5559 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5560 vcpu->run->debug.arch.exception = DB_VECTOR;
5561 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5564 vcpu->arch.dr6 &= ~15;
5565 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5566 kvm_queue_exception(vcpu, DB_VECTOR);
5571 if (vcpu->guest_debug == 0) {
5572 u32 cpu_based_vm_exec_control;
5574 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5575 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5576 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5579 * No more DR vmexits; force a reload of the debug registers
5580 * and reenter on this instruction. The next vmexit will
5581 * retrieve the full state of the debug registers.
5583 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5587 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5588 if (exit_qualification & TYPE_MOV_FROM_DR) {
5591 if (kvm_get_dr(vcpu, dr, &val))
5593 kvm_register_write(vcpu, reg, val);
5595 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5598 skip_emulated_instruction(vcpu);
5602 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5604 return vcpu->arch.dr6;
5607 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5611 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5613 u32 cpu_based_vm_exec_control;
5615 get_debugreg(vcpu->arch.db[0], 0);
5616 get_debugreg(vcpu->arch.db[1], 1);
5617 get_debugreg(vcpu->arch.db[2], 2);
5618 get_debugreg(vcpu->arch.db[3], 3);
5619 get_debugreg(vcpu->arch.dr6, 6);
5620 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5622 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5624 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5625 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5626 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5629 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5631 vmcs_writel(GUEST_DR7, val);
5634 static int handle_cpuid(struct kvm_vcpu *vcpu)
5636 kvm_emulate_cpuid(vcpu);
5640 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5642 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5643 struct msr_data msr_info;
5645 msr_info.index = ecx;
5646 msr_info.host_initiated = false;
5647 if (vmx_get_msr(vcpu, &msr_info)) {
5648 trace_kvm_msr_read_ex(ecx);
5649 kvm_inject_gp(vcpu, 0);
5653 trace_kvm_msr_read(ecx, msr_info.data);
5655 /* FIXME: handling of bits 32:63 of rax, rdx */
5656 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5657 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5658 skip_emulated_instruction(vcpu);
5662 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5664 struct msr_data msr;
5665 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5666 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5667 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5671 msr.host_initiated = false;
5672 if (kvm_set_msr(vcpu, &msr) != 0) {
5673 trace_kvm_msr_write_ex(ecx, data);
5674 kvm_inject_gp(vcpu, 0);
5678 trace_kvm_msr_write(ecx, data);
5679 skip_emulated_instruction(vcpu);
5683 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5685 kvm_make_request(KVM_REQ_EVENT, vcpu);
5689 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5691 u32 cpu_based_vm_exec_control;
5693 /* clear pending irq */
5694 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5695 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5696 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5698 kvm_make_request(KVM_REQ_EVENT, vcpu);
5700 ++vcpu->stat.irq_window_exits;
5704 static int handle_halt(struct kvm_vcpu *vcpu)
5706 return kvm_emulate_halt(vcpu);
5709 static int handle_vmcall(struct kvm_vcpu *vcpu)
5711 kvm_emulate_hypercall(vcpu);
5715 static int handle_invd(struct kvm_vcpu *vcpu)
5717 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5720 static int handle_invlpg(struct kvm_vcpu *vcpu)
5722 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5724 kvm_mmu_invlpg(vcpu, exit_qualification);
5725 skip_emulated_instruction(vcpu);
5729 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5733 err = kvm_rdpmc(vcpu);
5734 kvm_complete_insn_gp(vcpu, err);
5739 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5741 kvm_emulate_wbinvd(vcpu);
5745 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5747 u64 new_bv = kvm_read_edx_eax(vcpu);
5748 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5750 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5751 skip_emulated_instruction(vcpu);
5755 static int handle_xsaves(struct kvm_vcpu *vcpu)
5757 skip_emulated_instruction(vcpu);
5758 WARN(1, "this should never happen\n");
5762 static int handle_xrstors(struct kvm_vcpu *vcpu)
5764 skip_emulated_instruction(vcpu);
5765 WARN(1, "this should never happen\n");
5769 static int handle_apic_access(struct kvm_vcpu *vcpu)
5771 if (likely(fasteoi)) {
5772 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5773 int access_type, offset;
5775 access_type = exit_qualification & APIC_ACCESS_TYPE;
5776 offset = exit_qualification & APIC_ACCESS_OFFSET;
5778 * Sane guest uses MOV to write EOI, with written value
5779 * not cared. So make a short-circuit here by avoiding
5780 * heavy instruction emulation.
5782 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5783 (offset == APIC_EOI)) {
5784 kvm_lapic_set_eoi(vcpu);
5785 skip_emulated_instruction(vcpu);
5789 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5792 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5794 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5795 int vector = exit_qualification & 0xff;
5797 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5798 kvm_apic_set_eoi_accelerated(vcpu, vector);
5802 static int handle_apic_write(struct kvm_vcpu *vcpu)
5804 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5805 u32 offset = exit_qualification & 0xfff;
5807 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5808 kvm_apic_write_nodecode(vcpu, offset);
5812 static int handle_task_switch(struct kvm_vcpu *vcpu)
5814 struct vcpu_vmx *vmx = to_vmx(vcpu);
5815 unsigned long exit_qualification;
5816 bool has_error_code = false;
5819 int reason, type, idt_v, idt_index;
5821 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5822 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5823 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5825 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5827 reason = (u32)exit_qualification >> 30;
5828 if (reason == TASK_SWITCH_GATE && idt_v) {
5830 case INTR_TYPE_NMI_INTR:
5831 vcpu->arch.nmi_injected = false;
5832 vmx_set_nmi_mask(vcpu, true);
5834 case INTR_TYPE_EXT_INTR:
5835 case INTR_TYPE_SOFT_INTR:
5836 kvm_clear_interrupt_queue(vcpu);
5838 case INTR_TYPE_HARD_EXCEPTION:
5839 if (vmx->idt_vectoring_info &
5840 VECTORING_INFO_DELIVER_CODE_MASK) {
5841 has_error_code = true;
5843 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5846 case INTR_TYPE_SOFT_EXCEPTION:
5847 kvm_clear_exception_queue(vcpu);
5853 tss_selector = exit_qualification;
5855 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5856 type != INTR_TYPE_EXT_INTR &&
5857 type != INTR_TYPE_NMI_INTR))
5858 skip_emulated_instruction(vcpu);
5860 if (kvm_task_switch(vcpu, tss_selector,
5861 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5862 has_error_code, error_code) == EMULATE_FAIL) {
5863 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5864 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5865 vcpu->run->internal.ndata = 0;
5870 * TODO: What about debug traps on tss switch?
5871 * Are we supposed to inject them and update dr6?
5877 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5879 unsigned long exit_qualification;
5884 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5886 gla_validity = (exit_qualification >> 7) & 0x3;
5887 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5888 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5889 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5890 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5891 vmcs_readl(GUEST_LINEAR_ADDRESS));
5892 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5893 (long unsigned int)exit_qualification);
5894 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5895 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5900 * EPT violation happened while executing iret from NMI,
5901 * "blocked by NMI" bit has to be set before next VM entry.
5902 * There are errata that may cause this bit to not be set:
5905 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5906 cpu_has_virtual_nmis() &&
5907 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5908 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5910 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5911 trace_kvm_page_fault(gpa, exit_qualification);
5913 /* It is a write fault? */
5914 error_code = exit_qualification & PFERR_WRITE_MASK;
5915 /* It is a fetch fault? */
5916 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5917 /* ept page table is present? */
5918 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5920 vcpu->arch.exit_qualification = exit_qualification;
5922 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5925 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5930 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5931 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5932 skip_emulated_instruction(vcpu);
5933 trace_kvm_fast_mmio(gpa);
5937 ret = handle_mmio_page_fault(vcpu, gpa, true);
5938 if (likely(ret == RET_MMIO_PF_EMULATE))
5939 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5942 if (unlikely(ret == RET_MMIO_PF_INVALID))
5943 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5945 if (unlikely(ret == RET_MMIO_PF_RETRY))
5948 /* It is the real ept misconfig */
5951 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5952 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5957 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5959 u32 cpu_based_vm_exec_control;
5961 /* clear pending NMI */
5962 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5963 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5964 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5965 ++vcpu->stat.nmi_window_exits;
5966 kvm_make_request(KVM_REQ_EVENT, vcpu);
5971 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5973 struct vcpu_vmx *vmx = to_vmx(vcpu);
5974 enum emulation_result err = EMULATE_DONE;
5977 bool intr_window_requested;
5978 unsigned count = 130;
5980 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5981 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5983 while (vmx->emulation_required && count-- != 0) {
5984 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5985 return handle_interrupt_window(&vmx->vcpu);
5987 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5990 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5992 if (err == EMULATE_USER_EXIT) {
5993 ++vcpu->stat.mmio_exits;
5998 if (err != EMULATE_DONE) {
5999 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6000 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6001 vcpu->run->internal.ndata = 0;
6005 if (vcpu->arch.halt_request) {
6006 vcpu->arch.halt_request = 0;
6007 ret = kvm_vcpu_halt(vcpu);
6011 if (signal_pending(current))
6021 static int __grow_ple_window(int val)
6023 if (ple_window_grow < 1)
6026 val = min(val, ple_window_actual_max);
6028 if (ple_window_grow < ple_window)
6029 val *= ple_window_grow;
6031 val += ple_window_grow;
6036 static int __shrink_ple_window(int val, int modifier, int minimum)
6041 if (modifier < ple_window)
6046 return max(val, minimum);
6049 static void grow_ple_window(struct kvm_vcpu *vcpu)
6051 struct vcpu_vmx *vmx = to_vmx(vcpu);
6052 int old = vmx->ple_window;
6054 vmx->ple_window = __grow_ple_window(old);
6056 if (vmx->ple_window != old)
6057 vmx->ple_window_dirty = true;
6059 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6062 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6064 struct vcpu_vmx *vmx = to_vmx(vcpu);
6065 int old = vmx->ple_window;
6067 vmx->ple_window = __shrink_ple_window(old,
6068 ple_window_shrink, ple_window);
6070 if (vmx->ple_window != old)
6071 vmx->ple_window_dirty = true;
6073 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6077 * ple_window_actual_max is computed to be one grow_ple_window() below
6078 * ple_window_max. (See __grow_ple_window for the reason.)
6079 * This prevents overflows, because ple_window_max is int.
6080 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6082 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6084 static void update_ple_window_actual_max(void)
6086 ple_window_actual_max =
6087 __shrink_ple_window(max(ple_window_max, ple_window),
6088 ple_window_grow, INT_MIN);
6092 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6094 static void wakeup_handler(void)
6096 struct kvm_vcpu *vcpu;
6097 int cpu = smp_processor_id();
6099 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6100 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6101 blocked_vcpu_list) {
6102 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6104 if (pi_test_on(pi_desc) == 1)
6105 kvm_vcpu_kick(vcpu);
6107 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6110 static __init int hardware_setup(void)
6112 int r = -ENOMEM, i, msr;
6114 rdmsrl_safe(MSR_EFER, &host_efer);
6116 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6117 kvm_define_shared_msr(i, vmx_msr_index[i]);
6119 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6120 if (!vmx_io_bitmap_a)
6123 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6124 if (!vmx_io_bitmap_b)
6127 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6128 if (!vmx_msr_bitmap_legacy)
6131 vmx_msr_bitmap_legacy_x2apic =
6132 (unsigned long *)__get_free_page(GFP_KERNEL);
6133 if (!vmx_msr_bitmap_legacy_x2apic)
6136 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6137 if (!vmx_msr_bitmap_longmode)
6140 vmx_msr_bitmap_longmode_x2apic =
6141 (unsigned long *)__get_free_page(GFP_KERNEL);
6142 if (!vmx_msr_bitmap_longmode_x2apic)
6146 vmx_msr_bitmap_nested =
6147 (unsigned long *)__get_free_page(GFP_KERNEL);
6148 if (!vmx_msr_bitmap_nested)
6152 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6153 if (!vmx_vmread_bitmap)
6156 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6157 if (!vmx_vmwrite_bitmap)
6160 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6161 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6164 * Allow direct access to the PC debug port (it is often used for I/O
6165 * delays, but the vmexits simply slow things down).
6167 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6168 clear_bit(0x80, vmx_io_bitmap_a);
6170 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6172 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6173 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6175 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6177 if (setup_vmcs_config(&vmcs_config) < 0) {
6182 if (boot_cpu_has(X86_FEATURE_NX))
6183 kvm_enable_efer_bits(EFER_NX);
6185 if (!cpu_has_vmx_vpid())
6187 if (!cpu_has_vmx_shadow_vmcs())
6188 enable_shadow_vmcs = 0;
6189 if (enable_shadow_vmcs)
6190 init_vmcs_shadow_fields();
6192 if (!cpu_has_vmx_ept() ||
6193 !cpu_has_vmx_ept_4levels()) {
6195 enable_unrestricted_guest = 0;
6196 enable_ept_ad_bits = 0;
6199 if (!cpu_has_vmx_ept_ad_bits())
6200 enable_ept_ad_bits = 0;
6202 if (!cpu_has_vmx_unrestricted_guest())
6203 enable_unrestricted_guest = 0;
6205 if (!cpu_has_vmx_flexpriority())
6206 flexpriority_enabled = 0;
6209 * set_apic_access_page_addr() is used to reload apic access
6210 * page upon invalidation. No need to do anything if not
6211 * using the APIC_ACCESS_ADDR VMCS field.
6213 if (!flexpriority_enabled)
6214 kvm_x86_ops->set_apic_access_page_addr = NULL;
6216 if (!cpu_has_vmx_tpr_shadow())
6217 kvm_x86_ops->update_cr8_intercept = NULL;
6219 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6220 kvm_disable_largepages();
6222 if (!cpu_has_vmx_ple())
6225 if (!cpu_has_vmx_apicv())
6228 if (cpu_has_vmx_tsc_scaling()) {
6229 kvm_has_tsc_control = true;
6230 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6231 kvm_tsc_scaling_ratio_frac_bits = 48;
6235 kvm_x86_ops->update_cr8_intercept = NULL;
6237 kvm_x86_ops->hwapic_irr_update = NULL;
6238 kvm_x86_ops->hwapic_isr_update = NULL;
6239 kvm_x86_ops->deliver_posted_interrupt = NULL;
6240 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6243 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6244 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6245 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6246 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6247 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6248 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6249 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6251 memcpy(vmx_msr_bitmap_legacy_x2apic,
6252 vmx_msr_bitmap_legacy, PAGE_SIZE);
6253 memcpy(vmx_msr_bitmap_longmode_x2apic,
6254 vmx_msr_bitmap_longmode, PAGE_SIZE);
6256 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6259 for (msr = 0x800; msr <= 0x8ff; msr++)
6260 vmx_disable_intercept_msr_read_x2apic(msr);
6262 /* According SDM, in x2apic mode, the whole id reg is used.
6263 * But in KVM, it only use the highest eight bits. Need to
6265 vmx_enable_intercept_msr_read_x2apic(0x802);
6267 vmx_enable_intercept_msr_read_x2apic(0x839);
6269 vmx_disable_intercept_msr_write_x2apic(0x808);
6271 vmx_disable_intercept_msr_write_x2apic(0x80b);
6273 vmx_disable_intercept_msr_write_x2apic(0x83f);
6277 kvm_mmu_set_mask_ptes(0ull,
6278 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6279 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6280 0ull, VMX_EPT_EXECUTABLE_MASK);
6281 ept_set_mmio_spte_mask();
6286 update_ple_window_actual_max();
6289 * Only enable PML when hardware supports PML feature, and both EPT
6290 * and EPT A/D bit features are enabled -- PML depends on them to work.
6292 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6296 kvm_x86_ops->slot_enable_log_dirty = NULL;
6297 kvm_x86_ops->slot_disable_log_dirty = NULL;
6298 kvm_x86_ops->flush_log_dirty = NULL;
6299 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6302 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6304 return alloc_kvm_area();
6307 free_page((unsigned long)vmx_vmwrite_bitmap);
6309 free_page((unsigned long)vmx_vmread_bitmap);
6312 free_page((unsigned long)vmx_msr_bitmap_nested);
6314 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6316 free_page((unsigned long)vmx_msr_bitmap_longmode);
6318 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6320 free_page((unsigned long)vmx_msr_bitmap_legacy);
6322 free_page((unsigned long)vmx_io_bitmap_b);
6324 free_page((unsigned long)vmx_io_bitmap_a);
6329 static __exit void hardware_unsetup(void)
6331 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6332 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6333 free_page((unsigned long)vmx_msr_bitmap_legacy);
6334 free_page((unsigned long)vmx_msr_bitmap_longmode);
6335 free_page((unsigned long)vmx_io_bitmap_b);
6336 free_page((unsigned long)vmx_io_bitmap_a);
6337 free_page((unsigned long)vmx_vmwrite_bitmap);
6338 free_page((unsigned long)vmx_vmread_bitmap);
6340 free_page((unsigned long)vmx_msr_bitmap_nested);
6346 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6347 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6349 static int handle_pause(struct kvm_vcpu *vcpu)
6352 grow_ple_window(vcpu);
6354 skip_emulated_instruction(vcpu);
6355 kvm_vcpu_on_spin(vcpu);
6360 static int handle_nop(struct kvm_vcpu *vcpu)
6362 skip_emulated_instruction(vcpu);
6366 static int handle_mwait(struct kvm_vcpu *vcpu)
6368 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6369 return handle_nop(vcpu);
6372 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6377 static int handle_monitor(struct kvm_vcpu *vcpu)
6379 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6380 return handle_nop(vcpu);
6384 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6385 * We could reuse a single VMCS for all the L2 guests, but we also want the
6386 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6387 * allows keeping them loaded on the processor, and in the future will allow
6388 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6389 * every entry if they never change.
6390 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6391 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6393 * The following functions allocate and free a vmcs02 in this pool.
6396 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6397 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6399 struct vmcs02_list *item;
6400 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6401 if (item->vmptr == vmx->nested.current_vmptr) {
6402 list_move(&item->list, &vmx->nested.vmcs02_pool);
6403 return &item->vmcs02;
6406 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6407 /* Recycle the least recently used VMCS. */
6408 item = list_entry(vmx->nested.vmcs02_pool.prev,
6409 struct vmcs02_list, list);
6410 item->vmptr = vmx->nested.current_vmptr;
6411 list_move(&item->list, &vmx->nested.vmcs02_pool);
6412 return &item->vmcs02;
6415 /* Create a new VMCS */
6416 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6419 item->vmcs02.vmcs = alloc_vmcs();
6420 if (!item->vmcs02.vmcs) {
6424 loaded_vmcs_init(&item->vmcs02);
6425 item->vmptr = vmx->nested.current_vmptr;
6426 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6427 vmx->nested.vmcs02_num++;
6428 return &item->vmcs02;
6431 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6432 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6434 struct vmcs02_list *item;
6435 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6436 if (item->vmptr == vmptr) {
6437 free_loaded_vmcs(&item->vmcs02);
6438 list_del(&item->list);
6440 vmx->nested.vmcs02_num--;
6446 * Free all VMCSs saved for this vcpu, except the one pointed by
6447 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6448 * must be &vmx->vmcs01.
6450 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6452 struct vmcs02_list *item, *n;
6454 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6455 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6457 * Something will leak if the above WARN triggers. Better than
6460 if (vmx->loaded_vmcs == &item->vmcs02)
6463 free_loaded_vmcs(&item->vmcs02);
6464 list_del(&item->list);
6466 vmx->nested.vmcs02_num--;
6471 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6472 * set the success or error code of an emulated VMX instruction, as specified
6473 * by Vol 2B, VMX Instruction Reference, "Conventions".
6475 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6477 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6478 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6479 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6482 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6484 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6485 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6486 X86_EFLAGS_SF | X86_EFLAGS_OF))
6490 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6491 u32 vm_instruction_error)
6493 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6495 * failValid writes the error number to the current VMCS, which
6496 * can't be done there isn't a current VMCS.
6498 nested_vmx_failInvalid(vcpu);
6501 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6502 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6503 X86_EFLAGS_SF | X86_EFLAGS_OF))
6505 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6507 * We don't need to force a shadow sync because
6508 * VM_INSTRUCTION_ERROR is not shadowed
6512 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6514 /* TODO: not to reset guest simply here. */
6515 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6516 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6519 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6521 struct vcpu_vmx *vmx =
6522 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6524 vmx->nested.preemption_timer_expired = true;
6525 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6526 kvm_vcpu_kick(&vmx->vcpu);
6528 return HRTIMER_NORESTART;
6532 * Decode the memory-address operand of a vmx instruction, as recorded on an
6533 * exit caused by such an instruction (run by a guest hypervisor).
6534 * On success, returns 0. When the operand is invalid, returns 1 and throws
6537 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6538 unsigned long exit_qualification,
6539 u32 vmx_instruction_info, bool wr, gva_t *ret)
6543 struct kvm_segment s;
6546 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6547 * Execution", on an exit, vmx_instruction_info holds most of the
6548 * addressing components of the operand. Only the displacement part
6549 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6550 * For how an actual address is calculated from all these components,
6551 * refer to Vol. 1, "Operand Addressing".
6553 int scaling = vmx_instruction_info & 3;
6554 int addr_size = (vmx_instruction_info >> 7) & 7;
6555 bool is_reg = vmx_instruction_info & (1u << 10);
6556 int seg_reg = (vmx_instruction_info >> 15) & 7;
6557 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6558 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6559 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6560 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6563 kvm_queue_exception(vcpu, UD_VECTOR);
6567 /* Addr = segment_base + offset */
6568 /* offset = base + [index * scale] + displacement */
6569 off = exit_qualification; /* holds the displacement */
6571 off += kvm_register_read(vcpu, base_reg);
6573 off += kvm_register_read(vcpu, index_reg)<<scaling;
6574 vmx_get_segment(vcpu, &s, seg_reg);
6575 *ret = s.base + off;
6577 if (addr_size == 1) /* 32 bit */
6580 /* Checks for #GP/#SS exceptions. */
6582 if (is_protmode(vcpu)) {
6583 /* Protected mode: apply checks for segment validity in the
6585 * - segment type check (#GP(0) may be thrown)
6586 * - usability check (#GP(0)/#SS(0))
6587 * - limit check (#GP(0)/#SS(0))
6590 /* #GP(0) if the destination operand is located in a
6591 * read-only data segment or any code segment.
6593 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6595 /* #GP(0) if the source operand is located in an
6596 * execute-only code segment
6598 exn = ((s.type & 0xa) == 8);
6601 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6604 if (is_long_mode(vcpu)) {
6605 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6606 * non-canonical form. This is an only check for long mode.
6608 exn = is_noncanonical_address(*ret);
6609 } else if (is_protmode(vcpu)) {
6610 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6612 exn = (s.unusable != 0);
6613 /* Protected mode: #GP(0)/#SS(0) if the memory
6614 * operand is outside the segment limit.
6616 exn = exn || (off + sizeof(u64) > s.limit);
6619 kvm_queue_exception_e(vcpu,
6620 seg_reg == VCPU_SREG_SS ?
6621 SS_VECTOR : GP_VECTOR,
6630 * This function performs the various checks including
6631 * - if it's 4KB aligned
6632 * - No bits beyond the physical address width are set
6633 * - Returns 0 on success or else 1
6634 * (Intel SDM Section 30.3)
6636 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6641 struct x86_exception e;
6643 struct vcpu_vmx *vmx = to_vmx(vcpu);
6644 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6646 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6647 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6650 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6651 sizeof(vmptr), &e)) {
6652 kvm_inject_page_fault(vcpu, &e);
6656 switch (exit_reason) {
6657 case EXIT_REASON_VMON:
6660 * The first 4 bytes of VMXON region contain the supported
6661 * VMCS revision identifier
6663 * Note - IA32_VMX_BASIC[48] will never be 1
6664 * for the nested case;
6665 * which replaces physical address width with 32
6668 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6669 nested_vmx_failInvalid(vcpu);
6670 skip_emulated_instruction(vcpu);
6674 page = nested_get_page(vcpu, vmptr);
6676 *(u32 *)kmap(page) != VMCS12_REVISION) {
6677 nested_vmx_failInvalid(vcpu);
6679 skip_emulated_instruction(vcpu);
6683 vmx->nested.vmxon_ptr = vmptr;
6685 case EXIT_REASON_VMCLEAR:
6686 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6687 nested_vmx_failValid(vcpu,
6688 VMXERR_VMCLEAR_INVALID_ADDRESS);
6689 skip_emulated_instruction(vcpu);
6693 if (vmptr == vmx->nested.vmxon_ptr) {
6694 nested_vmx_failValid(vcpu,
6695 VMXERR_VMCLEAR_VMXON_POINTER);
6696 skip_emulated_instruction(vcpu);
6700 case EXIT_REASON_VMPTRLD:
6701 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6702 nested_vmx_failValid(vcpu,
6703 VMXERR_VMPTRLD_INVALID_ADDRESS);
6704 skip_emulated_instruction(vcpu);
6708 if (vmptr == vmx->nested.vmxon_ptr) {
6709 nested_vmx_failValid(vcpu,
6710 VMXERR_VMCLEAR_VMXON_POINTER);
6711 skip_emulated_instruction(vcpu);
6716 return 1; /* shouldn't happen */
6725 * Emulate the VMXON instruction.
6726 * Currently, we just remember that VMX is active, and do not save or even
6727 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6728 * do not currently need to store anything in that guest-allocated memory
6729 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6730 * argument is different from the VMXON pointer (which the spec says they do).
6732 static int handle_vmon(struct kvm_vcpu *vcpu)
6734 struct kvm_segment cs;
6735 struct vcpu_vmx *vmx = to_vmx(vcpu);
6736 struct vmcs *shadow_vmcs;
6737 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6738 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6740 /* The Intel VMX Instruction Reference lists a bunch of bits that
6741 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6742 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6743 * Otherwise, we should fail with #UD. We test these now:
6745 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6746 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6747 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6748 kvm_queue_exception(vcpu, UD_VECTOR);
6752 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6753 if (is_long_mode(vcpu) && !cs.l) {
6754 kvm_queue_exception(vcpu, UD_VECTOR);
6758 if (vmx_get_cpl(vcpu)) {
6759 kvm_inject_gp(vcpu, 0);
6763 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6766 if (vmx->nested.vmxon) {
6767 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6768 skip_emulated_instruction(vcpu);
6772 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6773 != VMXON_NEEDED_FEATURES) {
6774 kvm_inject_gp(vcpu, 0);
6778 if (enable_shadow_vmcs) {
6779 shadow_vmcs = alloc_vmcs();
6782 /* mark vmcs as shadow */
6783 shadow_vmcs->revision_id |= (1u << 31);
6784 /* init shadow vmcs */
6785 vmcs_clear(shadow_vmcs);
6786 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6789 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6790 vmx->nested.vmcs02_num = 0;
6792 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6794 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6796 vmx->nested.vmxon = true;
6798 skip_emulated_instruction(vcpu);
6799 nested_vmx_succeed(vcpu);
6804 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6805 * for running VMX instructions (except VMXON, whose prerequisites are
6806 * slightly different). It also specifies what exception to inject otherwise.
6808 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6810 struct kvm_segment cs;
6811 struct vcpu_vmx *vmx = to_vmx(vcpu);
6813 if (!vmx->nested.vmxon) {
6814 kvm_queue_exception(vcpu, UD_VECTOR);
6818 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6819 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6820 (is_long_mode(vcpu) && !cs.l)) {
6821 kvm_queue_exception(vcpu, UD_VECTOR);
6825 if (vmx_get_cpl(vcpu)) {
6826 kvm_inject_gp(vcpu, 0);
6833 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6835 if (vmx->nested.current_vmptr == -1ull)
6838 /* current_vmptr and current_vmcs12 are always set/reset together */
6839 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6842 if (enable_shadow_vmcs) {
6843 /* copy to memory all shadowed fields in case
6844 they were modified */
6845 copy_shadow_to_vmcs12(vmx);
6846 vmx->nested.sync_shadow_vmcs = false;
6847 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6848 SECONDARY_EXEC_SHADOW_VMCS);
6849 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6851 vmx->nested.posted_intr_nv = -1;
6852 kunmap(vmx->nested.current_vmcs12_page);
6853 nested_release_page(vmx->nested.current_vmcs12_page);
6854 vmx->nested.current_vmptr = -1ull;
6855 vmx->nested.current_vmcs12 = NULL;
6859 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6860 * just stops using VMX.
6862 static void free_nested(struct vcpu_vmx *vmx)
6864 if (!vmx->nested.vmxon)
6867 vmx->nested.vmxon = false;
6868 free_vpid(vmx->nested.vpid02);
6869 nested_release_vmcs12(vmx);
6870 if (enable_shadow_vmcs)
6871 free_vmcs(vmx->nested.current_shadow_vmcs);
6872 /* Unpin physical memory we referred to in current vmcs02 */
6873 if (vmx->nested.apic_access_page) {
6874 nested_release_page(vmx->nested.apic_access_page);
6875 vmx->nested.apic_access_page = NULL;
6877 if (vmx->nested.virtual_apic_page) {
6878 nested_release_page(vmx->nested.virtual_apic_page);
6879 vmx->nested.virtual_apic_page = NULL;
6881 if (vmx->nested.pi_desc_page) {
6882 kunmap(vmx->nested.pi_desc_page);
6883 nested_release_page(vmx->nested.pi_desc_page);
6884 vmx->nested.pi_desc_page = NULL;
6885 vmx->nested.pi_desc = NULL;
6888 nested_free_all_saved_vmcss(vmx);
6891 /* Emulate the VMXOFF instruction */
6892 static int handle_vmoff(struct kvm_vcpu *vcpu)
6894 if (!nested_vmx_check_permission(vcpu))
6896 free_nested(to_vmx(vcpu));
6897 skip_emulated_instruction(vcpu);
6898 nested_vmx_succeed(vcpu);
6902 /* Emulate the VMCLEAR instruction */
6903 static int handle_vmclear(struct kvm_vcpu *vcpu)
6905 struct vcpu_vmx *vmx = to_vmx(vcpu);
6907 struct vmcs12 *vmcs12;
6910 if (!nested_vmx_check_permission(vcpu))
6913 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6916 if (vmptr == vmx->nested.current_vmptr)
6917 nested_release_vmcs12(vmx);
6919 page = nested_get_page(vcpu, vmptr);
6922 * For accurate processor emulation, VMCLEAR beyond available
6923 * physical memory should do nothing at all. However, it is
6924 * possible that a nested vmx bug, not a guest hypervisor bug,
6925 * resulted in this case, so let's shut down before doing any
6928 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6931 vmcs12 = kmap(page);
6932 vmcs12->launch_state = 0;
6934 nested_release_page(page);
6936 nested_free_vmcs02(vmx, vmptr);
6938 skip_emulated_instruction(vcpu);
6939 nested_vmx_succeed(vcpu);
6943 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6945 /* Emulate the VMLAUNCH instruction */
6946 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6948 return nested_vmx_run(vcpu, true);
6951 /* Emulate the VMRESUME instruction */
6952 static int handle_vmresume(struct kvm_vcpu *vcpu)
6955 return nested_vmx_run(vcpu, false);
6958 enum vmcs_field_type {
6959 VMCS_FIELD_TYPE_U16 = 0,
6960 VMCS_FIELD_TYPE_U64 = 1,
6961 VMCS_FIELD_TYPE_U32 = 2,
6962 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6965 static inline int vmcs_field_type(unsigned long field)
6967 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6968 return VMCS_FIELD_TYPE_U32;
6969 return (field >> 13) & 0x3 ;
6972 static inline int vmcs_field_readonly(unsigned long field)
6974 return (((field >> 10) & 0x3) == 1);
6978 * Read a vmcs12 field. Since these can have varying lengths and we return
6979 * one type, we chose the biggest type (u64) and zero-extend the return value
6980 * to that size. Note that the caller, handle_vmread, might need to use only
6981 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6982 * 64-bit fields are to be returned).
6984 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6985 unsigned long field, u64 *ret)
6987 short offset = vmcs_field_to_offset(field);
6993 p = ((char *)(get_vmcs12(vcpu))) + offset;
6995 switch (vmcs_field_type(field)) {
6996 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6997 *ret = *((natural_width *)p);
6999 case VMCS_FIELD_TYPE_U16:
7002 case VMCS_FIELD_TYPE_U32:
7005 case VMCS_FIELD_TYPE_U64:
7015 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7016 unsigned long field, u64 field_value){
7017 short offset = vmcs_field_to_offset(field);
7018 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7022 switch (vmcs_field_type(field)) {
7023 case VMCS_FIELD_TYPE_U16:
7024 *(u16 *)p = field_value;
7026 case VMCS_FIELD_TYPE_U32:
7027 *(u32 *)p = field_value;
7029 case VMCS_FIELD_TYPE_U64:
7030 *(u64 *)p = field_value;
7032 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7033 *(natural_width *)p = field_value;
7042 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7045 unsigned long field;
7047 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7048 const unsigned long *fields = shadow_read_write_fields;
7049 const int num_fields = max_shadow_read_write_fields;
7053 vmcs_load(shadow_vmcs);
7055 for (i = 0; i < num_fields; i++) {
7057 switch (vmcs_field_type(field)) {
7058 case VMCS_FIELD_TYPE_U16:
7059 field_value = vmcs_read16(field);
7061 case VMCS_FIELD_TYPE_U32:
7062 field_value = vmcs_read32(field);
7064 case VMCS_FIELD_TYPE_U64:
7065 field_value = vmcs_read64(field);
7067 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7068 field_value = vmcs_readl(field);
7074 vmcs12_write_any(&vmx->vcpu, field, field_value);
7077 vmcs_clear(shadow_vmcs);
7078 vmcs_load(vmx->loaded_vmcs->vmcs);
7083 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7085 const unsigned long *fields[] = {
7086 shadow_read_write_fields,
7087 shadow_read_only_fields
7089 const int max_fields[] = {
7090 max_shadow_read_write_fields,
7091 max_shadow_read_only_fields
7094 unsigned long field;
7095 u64 field_value = 0;
7096 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7098 vmcs_load(shadow_vmcs);
7100 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7101 for (i = 0; i < max_fields[q]; i++) {
7102 field = fields[q][i];
7103 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7105 switch (vmcs_field_type(field)) {
7106 case VMCS_FIELD_TYPE_U16:
7107 vmcs_write16(field, (u16)field_value);
7109 case VMCS_FIELD_TYPE_U32:
7110 vmcs_write32(field, (u32)field_value);
7112 case VMCS_FIELD_TYPE_U64:
7113 vmcs_write64(field, (u64)field_value);
7115 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7116 vmcs_writel(field, (long)field_value);
7125 vmcs_clear(shadow_vmcs);
7126 vmcs_load(vmx->loaded_vmcs->vmcs);
7130 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7131 * used before) all generate the same failure when it is missing.
7133 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7135 struct vcpu_vmx *vmx = to_vmx(vcpu);
7136 if (vmx->nested.current_vmptr == -1ull) {
7137 nested_vmx_failInvalid(vcpu);
7138 skip_emulated_instruction(vcpu);
7144 static int handle_vmread(struct kvm_vcpu *vcpu)
7146 unsigned long field;
7148 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7149 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7152 if (!nested_vmx_check_permission(vcpu) ||
7153 !nested_vmx_check_vmcs12(vcpu))
7156 /* Decode instruction info and find the field to read */
7157 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7158 /* Read the field, zero-extended to a u64 field_value */
7159 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7160 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7161 skip_emulated_instruction(vcpu);
7165 * Now copy part of this value to register or memory, as requested.
7166 * Note that the number of bits actually copied is 32 or 64 depending
7167 * on the guest's mode (32 or 64 bit), not on the given field's length.
7169 if (vmx_instruction_info & (1u << 10)) {
7170 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7173 if (get_vmx_mem_address(vcpu, exit_qualification,
7174 vmx_instruction_info, true, &gva))
7176 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7177 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7178 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7181 nested_vmx_succeed(vcpu);
7182 skip_emulated_instruction(vcpu);
7187 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7189 unsigned long field;
7191 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7192 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7193 /* The value to write might be 32 or 64 bits, depending on L1's long
7194 * mode, and eventually we need to write that into a field of several
7195 * possible lengths. The code below first zero-extends the value to 64
7196 * bit (field_value), and then copies only the approriate number of
7197 * bits into the vmcs12 field.
7199 u64 field_value = 0;
7200 struct x86_exception e;
7202 if (!nested_vmx_check_permission(vcpu) ||
7203 !nested_vmx_check_vmcs12(vcpu))
7206 if (vmx_instruction_info & (1u << 10))
7207 field_value = kvm_register_readl(vcpu,
7208 (((vmx_instruction_info) >> 3) & 0xf));
7210 if (get_vmx_mem_address(vcpu, exit_qualification,
7211 vmx_instruction_info, false, &gva))
7213 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7214 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7215 kvm_inject_page_fault(vcpu, &e);
7221 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7222 if (vmcs_field_readonly(field)) {
7223 nested_vmx_failValid(vcpu,
7224 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7225 skip_emulated_instruction(vcpu);
7229 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7230 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7231 skip_emulated_instruction(vcpu);
7235 nested_vmx_succeed(vcpu);
7236 skip_emulated_instruction(vcpu);
7240 /* Emulate the VMPTRLD instruction */
7241 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7243 struct vcpu_vmx *vmx = to_vmx(vcpu);
7246 if (!nested_vmx_check_permission(vcpu))
7249 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7252 if (vmx->nested.current_vmptr != vmptr) {
7253 struct vmcs12 *new_vmcs12;
7255 page = nested_get_page(vcpu, vmptr);
7257 nested_vmx_failInvalid(vcpu);
7258 skip_emulated_instruction(vcpu);
7261 new_vmcs12 = kmap(page);
7262 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7264 nested_release_page_clean(page);
7265 nested_vmx_failValid(vcpu,
7266 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7267 skip_emulated_instruction(vcpu);
7271 nested_release_vmcs12(vmx);
7272 vmx->nested.current_vmptr = vmptr;
7273 vmx->nested.current_vmcs12 = new_vmcs12;
7274 vmx->nested.current_vmcs12_page = page;
7275 if (enable_shadow_vmcs) {
7276 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7277 SECONDARY_EXEC_SHADOW_VMCS);
7278 vmcs_write64(VMCS_LINK_POINTER,
7279 __pa(vmx->nested.current_shadow_vmcs));
7280 vmx->nested.sync_shadow_vmcs = true;
7284 nested_vmx_succeed(vcpu);
7285 skip_emulated_instruction(vcpu);
7289 /* Emulate the VMPTRST instruction */
7290 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7292 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7293 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7295 struct x86_exception e;
7297 if (!nested_vmx_check_permission(vcpu))
7300 if (get_vmx_mem_address(vcpu, exit_qualification,
7301 vmx_instruction_info, true, &vmcs_gva))
7303 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7304 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7305 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7307 kvm_inject_page_fault(vcpu, &e);
7310 nested_vmx_succeed(vcpu);
7311 skip_emulated_instruction(vcpu);
7315 /* Emulate the INVEPT instruction */
7316 static int handle_invept(struct kvm_vcpu *vcpu)
7318 struct vcpu_vmx *vmx = to_vmx(vcpu);
7319 u32 vmx_instruction_info, types;
7322 struct x86_exception e;
7327 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7328 SECONDARY_EXEC_ENABLE_EPT) ||
7329 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7330 kvm_queue_exception(vcpu, UD_VECTOR);
7334 if (!nested_vmx_check_permission(vcpu))
7337 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7338 kvm_queue_exception(vcpu, UD_VECTOR);
7342 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7343 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7345 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7347 if (!(types & (1UL << type))) {
7348 nested_vmx_failValid(vcpu,
7349 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7350 skip_emulated_instruction(vcpu);
7354 /* According to the Intel VMX instruction reference, the memory
7355 * operand is read even if it isn't needed (e.g., for type==global)
7357 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7358 vmx_instruction_info, false, &gva))
7360 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7361 sizeof(operand), &e)) {
7362 kvm_inject_page_fault(vcpu, &e);
7367 case VMX_EPT_EXTENT_GLOBAL:
7368 kvm_mmu_sync_roots(vcpu);
7369 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7370 nested_vmx_succeed(vcpu);
7373 /* Trap single context invalidation invept calls */
7378 skip_emulated_instruction(vcpu);
7382 static int handle_invvpid(struct kvm_vcpu *vcpu)
7384 struct vcpu_vmx *vmx = to_vmx(vcpu);
7385 u32 vmx_instruction_info;
7386 unsigned long type, types;
7388 struct x86_exception e;
7391 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7392 SECONDARY_EXEC_ENABLE_VPID) ||
7393 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7394 kvm_queue_exception(vcpu, UD_VECTOR);
7398 if (!nested_vmx_check_permission(vcpu))
7401 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7402 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7404 types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7406 if (!(types & (1UL << type))) {
7407 nested_vmx_failValid(vcpu,
7408 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7409 skip_emulated_instruction(vcpu);
7413 /* according to the intel vmx instruction reference, the memory
7414 * operand is read even if it isn't needed (e.g., for type==global)
7416 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7417 vmx_instruction_info, false, &gva))
7419 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7421 kvm_inject_page_fault(vcpu, &e);
7426 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7428 * Old versions of KVM use the single-context version so we
7429 * have to support it; just treat it the same as all-context.
7431 case VMX_VPID_EXTENT_ALL_CONTEXT:
7432 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7433 nested_vmx_succeed(vcpu);
7436 /* Trap individual address invalidation invvpid calls */
7441 skip_emulated_instruction(vcpu);
7445 static int handle_pml_full(struct kvm_vcpu *vcpu)
7447 unsigned long exit_qualification;
7449 trace_kvm_pml_full(vcpu->vcpu_id);
7451 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7454 * PML buffer FULL happened while executing iret from NMI,
7455 * "blocked by NMI" bit has to be set before next VM entry.
7457 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7458 cpu_has_virtual_nmis() &&
7459 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7460 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7461 GUEST_INTR_STATE_NMI);
7464 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7465 * here.., and there's no userspace involvement needed for PML.
7470 static int handle_pcommit(struct kvm_vcpu *vcpu)
7472 /* we never catch pcommit instruct for L1 guest. */
7478 * The exit handlers return 1 if the exit was handled fully and guest execution
7479 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7480 * to be done to userspace and return 0.
7482 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7483 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7484 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7485 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7486 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7487 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7488 [EXIT_REASON_CR_ACCESS] = handle_cr,
7489 [EXIT_REASON_DR_ACCESS] = handle_dr,
7490 [EXIT_REASON_CPUID] = handle_cpuid,
7491 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7492 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7493 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7494 [EXIT_REASON_HLT] = handle_halt,
7495 [EXIT_REASON_INVD] = handle_invd,
7496 [EXIT_REASON_INVLPG] = handle_invlpg,
7497 [EXIT_REASON_RDPMC] = handle_rdpmc,
7498 [EXIT_REASON_VMCALL] = handle_vmcall,
7499 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7500 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7501 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7502 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7503 [EXIT_REASON_VMREAD] = handle_vmread,
7504 [EXIT_REASON_VMRESUME] = handle_vmresume,
7505 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7506 [EXIT_REASON_VMOFF] = handle_vmoff,
7507 [EXIT_REASON_VMON] = handle_vmon,
7508 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7509 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7510 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7511 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7512 [EXIT_REASON_WBINVD] = handle_wbinvd,
7513 [EXIT_REASON_XSETBV] = handle_xsetbv,
7514 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7515 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7516 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7517 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7518 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7519 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7520 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7521 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7522 [EXIT_REASON_INVEPT] = handle_invept,
7523 [EXIT_REASON_INVVPID] = handle_invvpid,
7524 [EXIT_REASON_XSAVES] = handle_xsaves,
7525 [EXIT_REASON_XRSTORS] = handle_xrstors,
7526 [EXIT_REASON_PML_FULL] = handle_pml_full,
7527 [EXIT_REASON_PCOMMIT] = handle_pcommit,
7530 static const int kvm_vmx_max_exit_handlers =
7531 ARRAY_SIZE(kvm_vmx_exit_handlers);
7533 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7534 struct vmcs12 *vmcs12)
7536 unsigned long exit_qualification;
7537 gpa_t bitmap, last_bitmap;
7542 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7543 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7545 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7547 port = exit_qualification >> 16;
7548 size = (exit_qualification & 7) + 1;
7550 last_bitmap = (gpa_t)-1;
7555 bitmap = vmcs12->io_bitmap_a;
7556 else if (port < 0x10000)
7557 bitmap = vmcs12->io_bitmap_b;
7560 bitmap += (port & 0x7fff) / 8;
7562 if (last_bitmap != bitmap)
7563 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7565 if (b & (1 << (port & 7)))
7570 last_bitmap = bitmap;
7577 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7578 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7579 * disinterest in the current event (read or write a specific MSR) by using an
7580 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7582 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7583 struct vmcs12 *vmcs12, u32 exit_reason)
7585 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7588 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7592 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7593 * for the four combinations of read/write and low/high MSR numbers.
7594 * First we need to figure out which of the four to use:
7596 bitmap = vmcs12->msr_bitmap;
7597 if (exit_reason == EXIT_REASON_MSR_WRITE)
7599 if (msr_index >= 0xc0000000) {
7600 msr_index -= 0xc0000000;
7604 /* Then read the msr_index'th bit from this bitmap: */
7605 if (msr_index < 1024*8) {
7607 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7609 return 1 & (b >> (msr_index & 7));
7611 return true; /* let L1 handle the wrong parameter */
7615 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7616 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7617 * intercept (via guest_host_mask etc.) the current event.
7619 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7620 struct vmcs12 *vmcs12)
7622 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7623 int cr = exit_qualification & 15;
7624 int reg = (exit_qualification >> 8) & 15;
7625 unsigned long val = kvm_register_readl(vcpu, reg);
7627 switch ((exit_qualification >> 4) & 3) {
7628 case 0: /* mov to cr */
7631 if (vmcs12->cr0_guest_host_mask &
7632 (val ^ vmcs12->cr0_read_shadow))
7636 if ((vmcs12->cr3_target_count >= 1 &&
7637 vmcs12->cr3_target_value0 == val) ||
7638 (vmcs12->cr3_target_count >= 2 &&
7639 vmcs12->cr3_target_value1 == val) ||
7640 (vmcs12->cr3_target_count >= 3 &&
7641 vmcs12->cr3_target_value2 == val) ||
7642 (vmcs12->cr3_target_count >= 4 &&
7643 vmcs12->cr3_target_value3 == val))
7645 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7649 if (vmcs12->cr4_guest_host_mask &
7650 (vmcs12->cr4_read_shadow ^ val))
7654 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7660 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7661 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7664 case 1: /* mov from cr */
7667 if (vmcs12->cpu_based_vm_exec_control &
7668 CPU_BASED_CR3_STORE_EXITING)
7672 if (vmcs12->cpu_based_vm_exec_control &
7673 CPU_BASED_CR8_STORE_EXITING)
7680 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7681 * cr0. Other attempted changes are ignored, with no exit.
7683 if (vmcs12->cr0_guest_host_mask & 0xe &
7684 (val ^ vmcs12->cr0_read_shadow))
7686 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7687 !(vmcs12->cr0_read_shadow & 0x1) &&
7696 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7697 * should handle it ourselves in L0 (and then continue L2). Only call this
7698 * when in is_guest_mode (L2).
7700 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7702 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7703 struct vcpu_vmx *vmx = to_vmx(vcpu);
7704 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7705 u32 exit_reason = vmx->exit_reason;
7707 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7708 vmcs_readl(EXIT_QUALIFICATION),
7709 vmx->idt_vectoring_info,
7711 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7714 if (vmx->nested.nested_run_pending)
7717 if (unlikely(vmx->fail)) {
7718 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7719 vmcs_read32(VM_INSTRUCTION_ERROR));
7723 switch (exit_reason) {
7724 case EXIT_REASON_EXCEPTION_NMI:
7725 if (!is_exception(intr_info))
7727 else if (is_page_fault(intr_info))
7729 else if (is_no_device(intr_info) &&
7730 !(vmcs12->guest_cr0 & X86_CR0_TS))
7732 return vmcs12->exception_bitmap &
7733 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7734 case EXIT_REASON_EXTERNAL_INTERRUPT:
7736 case EXIT_REASON_TRIPLE_FAULT:
7738 case EXIT_REASON_PENDING_INTERRUPT:
7739 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7740 case EXIT_REASON_NMI_WINDOW:
7741 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7742 case EXIT_REASON_TASK_SWITCH:
7744 case EXIT_REASON_CPUID:
7745 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7748 case EXIT_REASON_HLT:
7749 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7750 case EXIT_REASON_INVD:
7752 case EXIT_REASON_INVLPG:
7753 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7754 case EXIT_REASON_RDPMC:
7755 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7756 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7757 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7758 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7759 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7760 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7761 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7762 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7763 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7765 * VMX instructions trap unconditionally. This allows L1 to
7766 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7769 case EXIT_REASON_CR_ACCESS:
7770 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7771 case EXIT_REASON_DR_ACCESS:
7772 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7773 case EXIT_REASON_IO_INSTRUCTION:
7774 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7775 case EXIT_REASON_MSR_READ:
7776 case EXIT_REASON_MSR_WRITE:
7777 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7778 case EXIT_REASON_INVALID_STATE:
7780 case EXIT_REASON_MWAIT_INSTRUCTION:
7781 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7782 case EXIT_REASON_MONITOR_TRAP_FLAG:
7783 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7784 case EXIT_REASON_MONITOR_INSTRUCTION:
7785 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7786 case EXIT_REASON_PAUSE_INSTRUCTION:
7787 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7788 nested_cpu_has2(vmcs12,
7789 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7790 case EXIT_REASON_MCE_DURING_VMENTRY:
7792 case EXIT_REASON_TPR_BELOW_THRESHOLD:
7793 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7794 case EXIT_REASON_APIC_ACCESS:
7795 return nested_cpu_has2(vmcs12,
7796 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7797 case EXIT_REASON_APIC_WRITE:
7798 case EXIT_REASON_EOI_INDUCED:
7799 /* apic_write and eoi_induced should exit unconditionally. */
7801 case EXIT_REASON_EPT_VIOLATION:
7803 * L0 always deals with the EPT violation. If nested EPT is
7804 * used, and the nested mmu code discovers that the address is
7805 * missing in the guest EPT table (EPT12), the EPT violation
7806 * will be injected with nested_ept_inject_page_fault()
7809 case EXIT_REASON_EPT_MISCONFIG:
7811 * L2 never uses directly L1's EPT, but rather L0's own EPT
7812 * table (shadow on EPT) or a merged EPT table that L0 built
7813 * (EPT on EPT). So any problems with the structure of the
7814 * table is L0's fault.
7817 case EXIT_REASON_WBINVD:
7818 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7819 case EXIT_REASON_XSETBV:
7821 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7823 * This should never happen, since it is not possible to
7824 * set XSS to a non-zero value---neither in L1 nor in L2.
7825 * If if it were, XSS would have to be checked against
7826 * the XSS exit bitmap in vmcs12.
7828 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7829 case EXIT_REASON_PCOMMIT:
7830 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7836 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7838 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7839 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7842 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7844 struct page *pml_pg;
7846 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7850 vmx->pml_pg = pml_pg;
7852 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7853 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7858 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7861 __free_page(vmx->pml_pg);
7866 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7868 struct vcpu_vmx *vmx = to_vmx(vcpu);
7872 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7874 /* Do nothing if PML buffer is empty */
7875 if (pml_idx == (PML_ENTITY_NUM - 1))
7878 /* PML index always points to next available PML buffer entity */
7879 if (pml_idx >= PML_ENTITY_NUM)
7884 pml_buf = page_address(vmx->pml_pg);
7885 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7888 gpa = pml_buf[pml_idx];
7889 WARN_ON(gpa & (PAGE_SIZE - 1));
7890 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7893 /* reset PML index */
7894 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7898 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7899 * Called before reporting dirty_bitmap to userspace.
7901 static void kvm_flush_pml_buffers(struct kvm *kvm)
7904 struct kvm_vcpu *vcpu;
7906 * We only need to kick vcpu out of guest mode here, as PML buffer
7907 * is flushed at beginning of all VMEXITs, and it's obvious that only
7908 * vcpus running in guest are possible to have unflushed GPAs in PML
7911 kvm_for_each_vcpu(i, vcpu, kvm)
7912 kvm_vcpu_kick(vcpu);
7915 static void vmx_dump_sel(char *name, uint32_t sel)
7917 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7918 name, vmcs_read32(sel),
7919 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7920 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7921 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7924 static void vmx_dump_dtsel(char *name, uint32_t limit)
7926 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7927 name, vmcs_read32(limit),
7928 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7931 static void dump_vmcs(void)
7933 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7934 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7935 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7936 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7937 u32 secondary_exec_control = 0;
7938 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7939 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7942 if (cpu_has_secondary_exec_ctrls())
7943 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7945 pr_err("*** Guest State ***\n");
7946 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7947 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7948 vmcs_readl(CR0_GUEST_HOST_MASK));
7949 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7950 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7951 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7952 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7953 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7955 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7956 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7957 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7958 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7960 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7961 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7962 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7963 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7964 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7965 vmcs_readl(GUEST_SYSENTER_ESP),
7966 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7967 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7968 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7969 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7970 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7971 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7972 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7973 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7974 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7975 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7976 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7977 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7978 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7979 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7980 efer, vmcs_readl(GUEST_IA32_PAT));
7981 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7982 vmcs_readl(GUEST_IA32_DEBUGCTL),
7983 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7984 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7985 pr_err("PerfGlobCtl = 0x%016lx\n",
7986 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7987 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7988 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7989 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7990 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7991 vmcs_read32(GUEST_ACTIVITY_STATE));
7992 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7993 pr_err("InterruptStatus = %04x\n",
7994 vmcs_read16(GUEST_INTR_STATUS));
7996 pr_err("*** Host State ***\n");
7997 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7998 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7999 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8000 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8001 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8002 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8003 vmcs_read16(HOST_TR_SELECTOR));
8004 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8005 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8006 vmcs_readl(HOST_TR_BASE));
8007 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8008 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8009 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8010 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8011 vmcs_readl(HOST_CR4));
8012 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8013 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8014 vmcs_read32(HOST_IA32_SYSENTER_CS),
8015 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8016 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8017 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
8018 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
8019 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8020 pr_err("PerfGlobCtl = 0x%016lx\n",
8021 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
8023 pr_err("*** Control State ***\n");
8024 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8025 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8026 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8027 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8028 vmcs_read32(EXCEPTION_BITMAP),
8029 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8030 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8031 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8032 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8033 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8034 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8035 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8036 vmcs_read32(VM_EXIT_INTR_INFO),
8037 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8038 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8039 pr_err(" reason=%08x qualification=%016lx\n",
8040 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8041 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8042 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8043 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8044 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8045 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8046 pr_err("TSC Multiplier = 0x%016lx\n",
8047 vmcs_readl(TSC_MULTIPLIER));
8048 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8049 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8050 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8051 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8052 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8053 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8054 n = vmcs_read32(CR3_TARGET_COUNT);
8055 for (i = 0; i + 1 < n; i += 4)
8056 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8057 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8058 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8060 pr_err("CR3 target%u=%016lx\n",
8061 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8062 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8063 pr_err("PLE Gap=%08x Window=%08x\n",
8064 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8065 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8066 pr_err("Virtual processor ID = 0x%04x\n",
8067 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8071 * The guest has exited. See if we can fix it or if we need userspace
8074 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8076 struct vcpu_vmx *vmx = to_vmx(vcpu);
8077 u32 exit_reason = vmx->exit_reason;
8078 u32 vectoring_info = vmx->idt_vectoring_info;
8080 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8083 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8084 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8085 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8086 * mode as if vcpus is in root mode, the PML buffer must has been
8090 vmx_flush_pml_buffer(vcpu);
8092 /* If guest state is invalid, start emulating */
8093 if (vmx->emulation_required)
8094 return handle_invalid_guest_state(vcpu);
8096 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8097 nested_vmx_vmexit(vcpu, exit_reason,
8098 vmcs_read32(VM_EXIT_INTR_INFO),
8099 vmcs_readl(EXIT_QUALIFICATION));
8103 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8105 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8106 vcpu->run->fail_entry.hardware_entry_failure_reason
8111 if (unlikely(vmx->fail)) {
8112 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8113 vcpu->run->fail_entry.hardware_entry_failure_reason
8114 = vmcs_read32(VM_INSTRUCTION_ERROR);
8120 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8121 * delivery event since it indicates guest is accessing MMIO.
8122 * The vm-exit can be triggered again after return to guest that
8123 * will cause infinite loop.
8125 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8126 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8127 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8128 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8129 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8130 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8131 vcpu->run->internal.ndata = 2;
8132 vcpu->run->internal.data[0] = vectoring_info;
8133 vcpu->run->internal.data[1] = exit_reason;
8137 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8138 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8139 get_vmcs12(vcpu))))) {
8140 if (vmx_interrupt_allowed(vcpu)) {
8141 vmx->soft_vnmi_blocked = 0;
8142 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8143 vcpu->arch.nmi_pending) {
8145 * This CPU don't support us in finding the end of an
8146 * NMI-blocked window if the guest runs with IRQs
8147 * disabled. So we pull the trigger after 1 s of
8148 * futile waiting, but inform the user about this.
8150 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8151 "state on VCPU %d after 1 s timeout\n",
8152 __func__, vcpu->vcpu_id);
8153 vmx->soft_vnmi_blocked = 0;
8157 if (exit_reason < kvm_vmx_max_exit_handlers
8158 && kvm_vmx_exit_handlers[exit_reason])
8159 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8161 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8162 kvm_queue_exception(vcpu, UD_VECTOR);
8167 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8169 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8171 if (is_guest_mode(vcpu) &&
8172 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8175 if (irr == -1 || tpr < irr) {
8176 vmcs_write32(TPR_THRESHOLD, 0);
8180 vmcs_write32(TPR_THRESHOLD, irr);
8183 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8185 u32 sec_exec_control;
8188 * There is not point to enable virtualize x2apic without enable
8191 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8192 !vmx_cpu_uses_apicv(vcpu))
8195 if (!cpu_need_tpr_shadow(vcpu))
8198 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8201 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8202 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8204 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8205 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8207 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8209 vmx_set_msr_bitmap(vcpu);
8212 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8214 struct vcpu_vmx *vmx = to_vmx(vcpu);
8217 * Currently we do not handle the nested case where L2 has an
8218 * APIC access page of its own; that page is still pinned.
8219 * Hence, we skip the case where the VCPU is in guest mode _and_
8220 * L1 prepared an APIC access page for L2.
8222 * For the case where L1 and L2 share the same APIC access page
8223 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8224 * in the vmcs12), this function will only update either the vmcs01
8225 * or the vmcs02. If the former, the vmcs02 will be updated by
8226 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8227 * the next L2->L1 exit.
8229 if (!is_guest_mode(vcpu) ||
8230 !nested_cpu_has2(vmx->nested.current_vmcs12,
8231 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8232 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8235 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8243 status = vmcs_read16(GUEST_INTR_STATUS);
8248 vmcs_write16(GUEST_INTR_STATUS, status);
8252 static void vmx_set_rvi(int vector)
8260 status = vmcs_read16(GUEST_INTR_STATUS);
8261 old = (u8)status & 0xff;
8262 if ((u8)vector != old) {
8264 status |= (u8)vector;
8265 vmcs_write16(GUEST_INTR_STATUS, status);
8269 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8271 if (!is_guest_mode(vcpu)) {
8272 vmx_set_rvi(max_irr);
8280 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8283 if (nested_exit_on_intr(vcpu))
8287 * Else, fall back to pre-APICv interrupt injection since L2
8288 * is run without virtual interrupt delivery.
8290 if (!kvm_event_needs_reinjection(vcpu) &&
8291 vmx_interrupt_allowed(vcpu)) {
8292 kvm_queue_interrupt(vcpu, max_irr, false);
8293 vmx_inject_irq(vcpu);
8297 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8299 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8300 if (!vmx_cpu_uses_apicv(vcpu))
8303 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8304 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8305 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8306 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8309 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8313 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8314 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8317 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8318 exit_intr_info = vmx->exit_intr_info;
8320 /* Handle machine checks before interrupts are enabled */
8321 if (is_machine_check(exit_intr_info))
8322 kvm_machine_check();
8324 /* We need to handle NMIs before interrupts are enabled */
8325 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8326 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8327 kvm_before_handle_nmi(&vmx->vcpu);
8329 kvm_after_handle_nmi(&vmx->vcpu);
8333 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8335 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8338 * If external interrupt exists, IF bit is set in rflags/eflags on the
8339 * interrupt stack frame, and interrupt will be enabled on a return
8340 * from interrupt handler.
8342 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8343 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8344 unsigned int vector;
8345 unsigned long entry;
8347 struct vcpu_vmx *vmx = to_vmx(vcpu);
8348 #ifdef CONFIG_X86_64
8352 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8353 desc = (gate_desc *)vmx->host_idt_base + vector;
8354 entry = gate_offset(*desc);
8356 #ifdef CONFIG_X86_64
8357 "mov %%" _ASM_SP ", %[sp]\n\t"
8358 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8363 "orl $0x200, (%%" _ASM_SP ")\n\t"
8364 __ASM_SIZE(push) " $%c[cs]\n\t"
8365 "call *%[entry]\n\t"
8367 #ifdef CONFIG_X86_64
8372 [ss]"i"(__KERNEL_DS),
8373 [cs]"i"(__KERNEL_CS)
8379 static bool vmx_has_high_real_mode_segbase(void)
8381 return enable_unrestricted_guest || emulate_invalid_guest_state;
8384 static bool vmx_mpx_supported(void)
8386 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8387 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8390 static bool vmx_xsaves_supported(void)
8392 return vmcs_config.cpu_based_2nd_exec_ctrl &
8393 SECONDARY_EXEC_XSAVES;
8396 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8401 bool idtv_info_valid;
8403 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8405 if (cpu_has_virtual_nmis()) {
8406 if (vmx->nmi_known_unmasked)
8409 * Can't use vmx->exit_intr_info since we're not sure what
8410 * the exit reason is.
8412 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8413 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8414 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8416 * SDM 3: 27.7.1.2 (September 2008)
8417 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8418 * a guest IRET fault.
8419 * SDM 3: 23.2.2 (September 2008)
8420 * Bit 12 is undefined in any of the following cases:
8421 * If the VM exit sets the valid bit in the IDT-vectoring
8422 * information field.
8423 * If the VM exit is due to a double fault.
8425 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8426 vector != DF_VECTOR && !idtv_info_valid)
8427 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8428 GUEST_INTR_STATE_NMI);
8430 vmx->nmi_known_unmasked =
8431 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8432 & GUEST_INTR_STATE_NMI);
8433 } else if (unlikely(vmx->soft_vnmi_blocked))
8434 vmx->vnmi_blocked_time +=
8435 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8438 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8439 u32 idt_vectoring_info,
8440 int instr_len_field,
8441 int error_code_field)
8445 bool idtv_info_valid;
8447 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8449 vcpu->arch.nmi_injected = false;
8450 kvm_clear_exception_queue(vcpu);
8451 kvm_clear_interrupt_queue(vcpu);
8453 if (!idtv_info_valid)
8456 kvm_make_request(KVM_REQ_EVENT, vcpu);
8458 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8459 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8462 case INTR_TYPE_NMI_INTR:
8463 vcpu->arch.nmi_injected = true;
8465 * SDM 3: 27.7.1.2 (September 2008)
8466 * Clear bit "block by NMI" before VM entry if a NMI
8469 vmx_set_nmi_mask(vcpu, false);
8471 case INTR_TYPE_SOFT_EXCEPTION:
8472 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8474 case INTR_TYPE_HARD_EXCEPTION:
8475 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8476 u32 err = vmcs_read32(error_code_field);
8477 kvm_requeue_exception_e(vcpu, vector, err);
8479 kvm_requeue_exception(vcpu, vector);
8481 case INTR_TYPE_SOFT_INTR:
8482 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8484 case INTR_TYPE_EXT_INTR:
8485 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8492 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8494 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8495 VM_EXIT_INSTRUCTION_LEN,
8496 IDT_VECTORING_ERROR_CODE);
8499 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8501 __vmx_complete_interrupts(vcpu,
8502 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8503 VM_ENTRY_INSTRUCTION_LEN,
8504 VM_ENTRY_EXCEPTION_ERROR_CODE);
8506 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8509 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8512 struct perf_guest_switch_msr *msrs;
8514 msrs = perf_guest_get_msrs(&nr_msrs);
8519 for (i = 0; i < nr_msrs; i++)
8520 if (msrs[i].host == msrs[i].guest)
8521 clear_atomic_switch_msr(vmx, msrs[i].msr);
8523 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8527 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8529 struct vcpu_vmx *vmx = to_vmx(vcpu);
8530 unsigned long debugctlmsr, cr4;
8532 /* Record the guest's net vcpu time for enforced NMI injections. */
8533 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8534 vmx->entry_time = ktime_get();
8536 /* Don't enter VMX if guest state is invalid, let the exit handler
8537 start emulation until we arrive back to a valid state */
8538 if (vmx->emulation_required)
8541 if (vmx->ple_window_dirty) {
8542 vmx->ple_window_dirty = false;
8543 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8546 if (vmx->nested.sync_shadow_vmcs) {
8547 copy_vmcs12_to_shadow(vmx);
8548 vmx->nested.sync_shadow_vmcs = false;
8551 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8552 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8553 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8554 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8556 cr4 = cr4_read_shadow();
8557 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8558 vmcs_writel(HOST_CR4, cr4);
8559 vmx->host_state.vmcs_host_cr4 = cr4;
8562 /* When single-stepping over STI and MOV SS, we must clear the
8563 * corresponding interruptibility bits in the guest state. Otherwise
8564 * vmentry fails as it then expects bit 14 (BS) in pending debug
8565 * exceptions being set, but that's not correct for the guest debugging
8567 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8568 vmx_set_interrupt_shadow(vcpu, 0);
8570 atomic_switch_perf_msrs(vmx);
8571 debugctlmsr = get_debugctlmsr();
8573 vmx->__launched = vmx->loaded_vmcs->launched;
8575 /* Store host registers */
8576 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8577 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8578 "push %%" _ASM_CX " \n\t"
8579 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8581 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8582 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8584 /* Reload cr2 if changed */
8585 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8586 "mov %%cr2, %%" _ASM_DX " \n\t"
8587 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8589 "mov %%" _ASM_AX", %%cr2 \n\t"
8591 /* Check if vmlaunch of vmresume is needed */
8592 "cmpl $0, %c[launched](%0) \n\t"
8593 /* Load guest registers. Don't clobber flags. */
8594 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8595 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8596 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8597 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8598 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8599 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8600 #ifdef CONFIG_X86_64
8601 "mov %c[r8](%0), %%r8 \n\t"
8602 "mov %c[r9](%0), %%r9 \n\t"
8603 "mov %c[r10](%0), %%r10 \n\t"
8604 "mov %c[r11](%0), %%r11 \n\t"
8605 "mov %c[r12](%0), %%r12 \n\t"
8606 "mov %c[r13](%0), %%r13 \n\t"
8607 "mov %c[r14](%0), %%r14 \n\t"
8608 "mov %c[r15](%0), %%r15 \n\t"
8610 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8612 /* Enter guest mode */
8614 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8616 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8618 /* Save guest registers, load host registers, keep flags */
8619 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8621 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8622 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8623 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8624 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8625 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8626 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8627 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8628 #ifdef CONFIG_X86_64
8629 "mov %%r8, %c[r8](%0) \n\t"
8630 "mov %%r9, %c[r9](%0) \n\t"
8631 "mov %%r10, %c[r10](%0) \n\t"
8632 "mov %%r11, %c[r11](%0) \n\t"
8633 "mov %%r12, %c[r12](%0) \n\t"
8634 "mov %%r13, %c[r13](%0) \n\t"
8635 "mov %%r14, %c[r14](%0) \n\t"
8636 "mov %%r15, %c[r15](%0) \n\t"
8638 "mov %%cr2, %%" _ASM_AX " \n\t"
8639 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8641 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8642 "setbe %c[fail](%0) \n\t"
8643 ".pushsection .rodata \n\t"
8644 ".global vmx_return \n\t"
8645 "vmx_return: " _ASM_PTR " 2b \n\t"
8647 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8648 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8649 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8650 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8651 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8652 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8653 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8654 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8655 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8656 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8657 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8658 #ifdef CONFIG_X86_64
8659 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8660 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8661 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8662 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8663 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8664 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8665 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8666 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8668 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8669 [wordsize]"i"(sizeof(ulong))
8671 #ifdef CONFIG_X86_64
8672 , "rax", "rbx", "rdi", "rsi"
8673 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8675 , "eax", "ebx", "edi", "esi"
8679 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8681 update_debugctlmsr(debugctlmsr);
8683 #ifndef CONFIG_X86_64
8685 * The sysexit path does not restore ds/es, so we must set them to
8686 * a reasonable value ourselves.
8688 * We can't defer this to vmx_load_host_state() since that function
8689 * may be executed in interrupt context, which saves and restore segments
8690 * around it, nullifying its effect.
8692 loadsegment(ds, __USER_DS);
8693 loadsegment(es, __USER_DS);
8696 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8697 | (1 << VCPU_EXREG_RFLAGS)
8698 | (1 << VCPU_EXREG_PDPTR)
8699 | (1 << VCPU_EXREG_SEGMENTS)
8700 | (1 << VCPU_EXREG_CR3));
8701 vcpu->arch.regs_dirty = 0;
8703 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8705 vmx->loaded_vmcs->launched = 1;
8707 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8710 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8711 * we did not inject a still-pending event to L1 now because of
8712 * nested_run_pending, we need to re-enable this bit.
8714 if (vmx->nested.nested_run_pending)
8715 kvm_make_request(KVM_REQ_EVENT, vcpu);
8717 vmx->nested.nested_run_pending = 0;
8719 vmx_complete_atomic_exit(vmx);
8720 vmx_recover_nmi_blocking(vmx);
8721 vmx_complete_interrupts(vmx);
8724 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8726 struct vcpu_vmx *vmx = to_vmx(vcpu);
8729 if (vmx->loaded_vmcs == &vmx->vmcs01)
8733 vmx->loaded_vmcs = &vmx->vmcs01;
8735 vmx_vcpu_load(vcpu, cpu);
8740 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8742 struct vcpu_vmx *vmx = to_vmx(vcpu);
8745 vmx_destroy_pml_buffer(vmx);
8746 free_vpid(vmx->vpid);
8747 leave_guest_mode(vcpu);
8748 vmx_load_vmcs01(vcpu);
8750 free_loaded_vmcs(vmx->loaded_vmcs);
8751 kfree(vmx->guest_msrs);
8752 kvm_vcpu_uninit(vcpu);
8753 kmem_cache_free(kvm_vcpu_cache, vmx);
8756 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8759 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8763 return ERR_PTR(-ENOMEM);
8765 vmx->vpid = allocate_vpid();
8767 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8771 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8772 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8776 if (!vmx->guest_msrs) {
8780 vmx->loaded_vmcs = &vmx->vmcs01;
8781 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8782 if (!vmx->loaded_vmcs->vmcs)
8785 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8786 loaded_vmcs_init(vmx->loaded_vmcs);
8791 vmx_vcpu_load(&vmx->vcpu, cpu);
8792 vmx->vcpu.cpu = cpu;
8793 err = vmx_vcpu_setup(vmx);
8794 vmx_vcpu_put(&vmx->vcpu);
8798 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8799 err = alloc_apic_access_page(kvm);
8805 if (!kvm->arch.ept_identity_map_addr)
8806 kvm->arch.ept_identity_map_addr =
8807 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8808 err = init_rmode_identity_map(kvm);
8814 nested_vmx_setup_ctls_msrs(vmx);
8815 vmx->nested.vpid02 = allocate_vpid();
8818 vmx->nested.posted_intr_nv = -1;
8819 vmx->nested.current_vmptr = -1ull;
8820 vmx->nested.current_vmcs12 = NULL;
8823 * If PML is turned on, failure on enabling PML just results in failure
8824 * of creating the vcpu, therefore we can simplify PML logic (by
8825 * avoiding dealing with cases, such as enabling PML partially on vcpus
8826 * for the guest, etc.
8829 err = vmx_create_pml_buffer(vmx);
8837 free_vpid(vmx->nested.vpid02);
8838 free_loaded_vmcs(vmx->loaded_vmcs);
8840 kfree(vmx->guest_msrs);
8842 kvm_vcpu_uninit(&vmx->vcpu);
8844 free_vpid(vmx->vpid);
8845 kmem_cache_free(kvm_vcpu_cache, vmx);
8846 return ERR_PTR(err);
8849 static void __init vmx_check_processor_compat(void *rtn)
8851 struct vmcs_config vmcs_conf;
8854 if (setup_vmcs_config(&vmcs_conf) < 0)
8856 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8857 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8858 smp_processor_id());
8863 static int get_ept_level(void)
8865 return VMX_EPT_DEFAULT_GAW + 1;
8868 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8873 /* For VT-d and EPT combination
8874 * 1. MMIO: always map as UC
8876 * a. VT-d without snooping control feature: can't guarantee the
8877 * result, try to trust guest.
8878 * b. VT-d with snooping control feature: snooping control feature of
8879 * VT-d engine can guarantee the cache correctness. Just set it
8880 * to WB to keep consistent with host. So the same as item 3.
8881 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8882 * consistent with host MTRR
8885 cache = MTRR_TYPE_UNCACHABLE;
8889 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8890 ipat = VMX_EPT_IPAT_BIT;
8891 cache = MTRR_TYPE_WRBACK;
8895 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8896 ipat = VMX_EPT_IPAT_BIT;
8897 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8898 cache = MTRR_TYPE_WRBACK;
8900 cache = MTRR_TYPE_UNCACHABLE;
8904 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8907 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8910 static int vmx_get_lpage_level(void)
8912 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8913 return PT_DIRECTORY_LEVEL;
8915 /* For shadow and EPT supported 1GB page */
8916 return PT_PDPE_LEVEL;
8919 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8922 * These bits in the secondary execution controls field
8923 * are dynamic, the others are mostly based on the hypervisor
8924 * architecture and the guest's CPUID. Do not touch the
8928 SECONDARY_EXEC_SHADOW_VMCS |
8929 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8930 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8932 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8934 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8935 (new_ctl & ~mask) | (cur_ctl & mask));
8938 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8940 struct kvm_cpuid_entry2 *best;
8941 struct vcpu_vmx *vmx = to_vmx(vcpu);
8942 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8944 if (vmx_rdtscp_supported()) {
8945 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8946 if (!rdtscp_enabled)
8947 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8951 vmx->nested.nested_vmx_secondary_ctls_high |=
8952 SECONDARY_EXEC_RDTSCP;
8954 vmx->nested.nested_vmx_secondary_ctls_high &=
8955 ~SECONDARY_EXEC_RDTSCP;
8959 /* Exposing INVPCID only when PCID is exposed */
8960 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8961 if (vmx_invpcid_supported() &&
8962 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8963 !guest_cpuid_has_pcid(vcpu))) {
8964 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8967 best->ebx &= ~bit(X86_FEATURE_INVPCID);
8970 if (cpu_has_secondary_exec_ctrls())
8971 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8973 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8974 if (guest_cpuid_has_pcommit(vcpu))
8975 vmx->nested.nested_vmx_secondary_ctls_high |=
8976 SECONDARY_EXEC_PCOMMIT;
8978 vmx->nested.nested_vmx_secondary_ctls_high &=
8979 ~SECONDARY_EXEC_PCOMMIT;
8983 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8985 if (func == 1 && nested)
8986 entry->ecx |= bit(X86_FEATURE_VMX);
8989 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8990 struct x86_exception *fault)
8992 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8995 if (fault->error_code & PFERR_RSVD_MASK)
8996 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8998 exit_reason = EXIT_REASON_EPT_VIOLATION;
8999 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9000 vmcs12->guest_physical_address = fault->address;
9003 /* Callbacks for nested_ept_init_mmu_context: */
9005 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9007 /* return the page table to be shadowed - in our case, EPT12 */
9008 return get_vmcs12(vcpu)->ept_pointer;
9011 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9013 WARN_ON(mmu_is_nested(vcpu));
9014 kvm_init_shadow_ept_mmu(vcpu,
9015 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9016 VMX_EPT_EXECUTE_ONLY_BIT);
9017 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9018 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9019 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9021 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9024 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9026 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9029 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9032 bool inequality, bit;
9034 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9036 (error_code & vmcs12->page_fault_error_code_mask) !=
9037 vmcs12->page_fault_error_code_match;
9038 return inequality ^ bit;
9041 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9042 struct x86_exception *fault)
9044 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9046 WARN_ON(!is_guest_mode(vcpu));
9048 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9049 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9050 vmcs_read32(VM_EXIT_INTR_INFO),
9051 vmcs_readl(EXIT_QUALIFICATION));
9053 kvm_inject_page_fault(vcpu, fault);
9056 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9057 struct vmcs12 *vmcs12)
9059 struct vcpu_vmx *vmx = to_vmx(vcpu);
9060 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9062 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9063 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9064 vmcs12->apic_access_addr >> maxphyaddr)
9068 * Translate L1 physical address to host physical
9069 * address for vmcs02. Keep the page pinned, so this
9070 * physical address remains valid. We keep a reference
9071 * to it so we can release it later.
9073 if (vmx->nested.apic_access_page) /* shouldn't happen */
9074 nested_release_page(vmx->nested.apic_access_page);
9075 vmx->nested.apic_access_page =
9076 nested_get_page(vcpu, vmcs12->apic_access_addr);
9079 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9080 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9081 vmcs12->virtual_apic_page_addr >> maxphyaddr)
9084 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9085 nested_release_page(vmx->nested.virtual_apic_page);
9086 vmx->nested.virtual_apic_page =
9087 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9090 * Failing the vm entry is _not_ what the processor does
9091 * but it's basically the only possibility we have.
9092 * We could still enter the guest if CR8 load exits are
9093 * enabled, CR8 store exits are enabled, and virtualize APIC
9094 * access is disabled; in this case the processor would never
9095 * use the TPR shadow and we could simply clear the bit from
9096 * the execution control. But such a configuration is useless,
9097 * so let's keep the code simple.
9099 if (!vmx->nested.virtual_apic_page)
9103 if (nested_cpu_has_posted_intr(vmcs12)) {
9104 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9105 vmcs12->posted_intr_desc_addr >> maxphyaddr)
9108 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9109 kunmap(vmx->nested.pi_desc_page);
9110 nested_release_page(vmx->nested.pi_desc_page);
9112 vmx->nested.pi_desc_page =
9113 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9114 if (!vmx->nested.pi_desc_page)
9117 vmx->nested.pi_desc =
9118 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9119 if (!vmx->nested.pi_desc) {
9120 nested_release_page_clean(vmx->nested.pi_desc_page);
9123 vmx->nested.pi_desc =
9124 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9125 (unsigned long)(vmcs12->posted_intr_desc_addr &
9132 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9134 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9135 struct vcpu_vmx *vmx = to_vmx(vcpu);
9137 if (vcpu->arch.virtual_tsc_khz == 0)
9140 /* Make sure short timeouts reliably trigger an immediate vmexit.
9141 * hrtimer_start does not guarantee this. */
9142 if (preemption_timeout <= 1) {
9143 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9147 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9148 preemption_timeout *= 1000000;
9149 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9150 hrtimer_start(&vmx->nested.preemption_timer,
9151 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9154 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9155 struct vmcs12 *vmcs12)
9160 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9163 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9167 maxphyaddr = cpuid_maxphyaddr(vcpu);
9169 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9170 ((addr + PAGE_SIZE) >> maxphyaddr))
9177 * Merge L0's and L1's MSR bitmap, return false to indicate that
9178 * we do not use the hardware.
9180 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9181 struct vmcs12 *vmcs12)
9185 unsigned long *msr_bitmap;
9187 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9190 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9195 msr_bitmap = (unsigned long *)kmap(page);
9197 nested_release_page_clean(page);
9202 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9203 if (nested_cpu_has_apic_reg_virt(vmcs12))
9204 for (msr = 0x800; msr <= 0x8ff; msr++)
9205 nested_vmx_disable_intercept_for_msr(
9207 vmx_msr_bitmap_nested,
9209 /* TPR is allowed */
9210 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9211 vmx_msr_bitmap_nested,
9212 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9213 MSR_TYPE_R | MSR_TYPE_W);
9214 if (nested_cpu_has_vid(vmcs12)) {
9215 /* EOI and self-IPI are allowed */
9216 nested_vmx_disable_intercept_for_msr(
9218 vmx_msr_bitmap_nested,
9219 APIC_BASE_MSR + (APIC_EOI >> 4),
9221 nested_vmx_disable_intercept_for_msr(
9223 vmx_msr_bitmap_nested,
9224 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9229 * Enable reading intercept of all the x2apic
9230 * MSRs. We should not rely on vmcs12 to do any
9231 * optimizations here, it may have been modified
9234 for (msr = 0x800; msr <= 0x8ff; msr++)
9235 __vmx_enable_intercept_for_msr(
9236 vmx_msr_bitmap_nested,
9240 __vmx_enable_intercept_for_msr(
9241 vmx_msr_bitmap_nested,
9242 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9244 __vmx_enable_intercept_for_msr(
9245 vmx_msr_bitmap_nested,
9246 APIC_BASE_MSR + (APIC_EOI >> 4),
9248 __vmx_enable_intercept_for_msr(
9249 vmx_msr_bitmap_nested,
9250 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9254 nested_release_page_clean(page);
9259 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9260 struct vmcs12 *vmcs12)
9262 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9263 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9264 !nested_cpu_has_vid(vmcs12) &&
9265 !nested_cpu_has_posted_intr(vmcs12))
9269 * If virtualize x2apic mode is enabled,
9270 * virtualize apic access must be disabled.
9272 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9273 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9277 * If virtual interrupt delivery is enabled,
9278 * we must exit on external interrupts.
9280 if (nested_cpu_has_vid(vmcs12) &&
9281 !nested_exit_on_intr(vcpu))
9285 * bits 15:8 should be zero in posted_intr_nv,
9286 * the descriptor address has been already checked
9287 * in nested_get_vmcs12_pages.
9289 if (nested_cpu_has_posted_intr(vmcs12) &&
9290 (!nested_cpu_has_vid(vmcs12) ||
9291 !nested_exit_intr_ack_set(vcpu) ||
9292 vmcs12->posted_intr_nv & 0xff00))
9295 /* tpr shadow is needed by all apicv features. */
9296 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9302 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9303 unsigned long count_field,
9304 unsigned long addr_field)
9309 if (vmcs12_read_any(vcpu, count_field, &count) ||
9310 vmcs12_read_any(vcpu, addr_field, &addr)) {
9316 maxphyaddr = cpuid_maxphyaddr(vcpu);
9317 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9318 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9319 pr_warn_ratelimited(
9320 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9321 addr_field, maxphyaddr, count, addr);
9327 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9328 struct vmcs12 *vmcs12)
9330 if (vmcs12->vm_exit_msr_load_count == 0 &&
9331 vmcs12->vm_exit_msr_store_count == 0 &&
9332 vmcs12->vm_entry_msr_load_count == 0)
9333 return 0; /* Fast path */
9334 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9335 VM_EXIT_MSR_LOAD_ADDR) ||
9336 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9337 VM_EXIT_MSR_STORE_ADDR) ||
9338 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9339 VM_ENTRY_MSR_LOAD_ADDR))
9344 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9345 struct vmx_msr_entry *e)
9347 /* x2APIC MSR accesses are not allowed */
9348 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9350 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9351 e->index == MSR_IA32_UCODE_REV)
9353 if (e->reserved != 0)
9358 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9359 struct vmx_msr_entry *e)
9361 if (e->index == MSR_FS_BASE ||
9362 e->index == MSR_GS_BASE ||
9363 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9364 nested_vmx_msr_check_common(vcpu, e))
9369 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9370 struct vmx_msr_entry *e)
9372 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9373 nested_vmx_msr_check_common(vcpu, e))
9379 * Load guest's/host's msr at nested entry/exit.
9380 * return 0 for success, entry index for failure.
9382 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9385 struct vmx_msr_entry e;
9386 struct msr_data msr;
9388 msr.host_initiated = false;
9389 for (i = 0; i < count; i++) {
9390 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9392 pr_warn_ratelimited(
9393 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9394 __func__, i, gpa + i * sizeof(e));
9397 if (nested_vmx_load_msr_check(vcpu, &e)) {
9398 pr_warn_ratelimited(
9399 "%s check failed (%u, 0x%x, 0x%x)\n",
9400 __func__, i, e.index, e.reserved);
9403 msr.index = e.index;
9405 if (kvm_set_msr(vcpu, &msr)) {
9406 pr_warn_ratelimited(
9407 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9408 __func__, i, e.index, e.value);
9417 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9420 struct vmx_msr_entry e;
9422 for (i = 0; i < count; i++) {
9423 struct msr_data msr_info;
9424 if (kvm_vcpu_read_guest(vcpu,
9425 gpa + i * sizeof(e),
9426 &e, 2 * sizeof(u32))) {
9427 pr_warn_ratelimited(
9428 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9429 __func__, i, gpa + i * sizeof(e));
9432 if (nested_vmx_store_msr_check(vcpu, &e)) {
9433 pr_warn_ratelimited(
9434 "%s check failed (%u, 0x%x, 0x%x)\n",
9435 __func__, i, e.index, e.reserved);
9438 msr_info.host_initiated = false;
9439 msr_info.index = e.index;
9440 if (kvm_get_msr(vcpu, &msr_info)) {
9441 pr_warn_ratelimited(
9442 "%s cannot read MSR (%u, 0x%x)\n",
9443 __func__, i, e.index);
9446 if (kvm_vcpu_write_guest(vcpu,
9447 gpa + i * sizeof(e) +
9448 offsetof(struct vmx_msr_entry, value),
9449 &msr_info.data, sizeof(msr_info.data))) {
9450 pr_warn_ratelimited(
9451 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9452 __func__, i, e.index, msr_info.data);
9460 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9461 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9462 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9463 * guest in a way that will both be appropriate to L1's requests, and our
9464 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9465 * function also has additional necessary side-effects, like setting various
9466 * vcpu->arch fields.
9468 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9470 struct vcpu_vmx *vmx = to_vmx(vcpu);
9473 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9474 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9475 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9476 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9477 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9478 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9479 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9480 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9481 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9482 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9483 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9484 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9485 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9486 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9487 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9488 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9489 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9490 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9491 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9492 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9493 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9494 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9495 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9496 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9497 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9498 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9499 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9500 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9501 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9502 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9503 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9504 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9505 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9506 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9507 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9508 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9510 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9511 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9512 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9514 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9515 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9517 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9518 vmcs12->vm_entry_intr_info_field);
9519 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9520 vmcs12->vm_entry_exception_error_code);
9521 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9522 vmcs12->vm_entry_instruction_len);
9523 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9524 vmcs12->guest_interruptibility_info);
9525 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9526 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9527 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9528 vmcs12->guest_pending_dbg_exceptions);
9529 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9530 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9532 if (nested_cpu_has_xsaves(vmcs12))
9533 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9534 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9536 exec_control = vmcs12->pin_based_vm_exec_control;
9537 exec_control |= vmcs_config.pin_based_exec_ctrl;
9538 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9540 if (nested_cpu_has_posted_intr(vmcs12)) {
9542 * Note that we use L0's vector here and in
9543 * vmx_deliver_nested_posted_interrupt.
9545 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9546 vmx->nested.pi_pending = false;
9547 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9548 vmcs_write64(POSTED_INTR_DESC_ADDR,
9549 page_to_phys(vmx->nested.pi_desc_page) +
9550 (unsigned long)(vmcs12->posted_intr_desc_addr &
9553 exec_control &= ~PIN_BASED_POSTED_INTR;
9555 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9557 vmx->nested.preemption_timer_expired = false;
9558 if (nested_cpu_has_preemption_timer(vmcs12))
9559 vmx_start_preemption_timer(vcpu);
9562 * Whether page-faults are trapped is determined by a combination of
9563 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9564 * If enable_ept, L0 doesn't care about page faults and we should
9565 * set all of these to L1's desires. However, if !enable_ept, L0 does
9566 * care about (at least some) page faults, and because it is not easy
9567 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9568 * to exit on each and every L2 page fault. This is done by setting
9569 * MASK=MATCH=0 and (see below) EB.PF=1.
9570 * Note that below we don't need special code to set EB.PF beyond the
9571 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9572 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9573 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9575 * A problem with this approach (when !enable_ept) is that L1 may be
9576 * injected with more page faults than it asked for. This could have
9577 * caused problems, but in practice existing hypervisors don't care.
9578 * To fix this, we will need to emulate the PFEC checking (on the L1
9579 * page tables), using walk_addr(), when injecting PFs to L1.
9581 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9582 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9583 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9584 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9586 if (cpu_has_secondary_exec_ctrls()) {
9587 exec_control = vmx_secondary_exec_control(vmx);
9589 /* Take the following fields only from vmcs12 */
9590 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9591 SECONDARY_EXEC_RDTSCP |
9592 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9593 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9594 SECONDARY_EXEC_PCOMMIT);
9595 if (nested_cpu_has(vmcs12,
9596 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9597 exec_control |= vmcs12->secondary_vm_exec_control;
9599 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9601 * If translation failed, no matter: This feature asks
9602 * to exit when accessing the given address, and if it
9603 * can never be accessed, this feature won't do
9606 if (!vmx->nested.apic_access_page)
9608 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9610 vmcs_write64(APIC_ACCESS_ADDR,
9611 page_to_phys(vmx->nested.apic_access_page));
9612 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9613 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9615 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9616 kvm_vcpu_reload_apic_access_page(vcpu);
9619 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9620 vmcs_write64(EOI_EXIT_BITMAP0,
9621 vmcs12->eoi_exit_bitmap0);
9622 vmcs_write64(EOI_EXIT_BITMAP1,
9623 vmcs12->eoi_exit_bitmap1);
9624 vmcs_write64(EOI_EXIT_BITMAP2,
9625 vmcs12->eoi_exit_bitmap2);
9626 vmcs_write64(EOI_EXIT_BITMAP3,
9627 vmcs12->eoi_exit_bitmap3);
9628 vmcs_write16(GUEST_INTR_STATUS,
9629 vmcs12->guest_intr_status);
9632 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9637 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9638 * Some constant fields are set here by vmx_set_constant_host_state().
9639 * Other fields are different per CPU, and will be set later when
9640 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9642 vmx_set_constant_host_state(vmx);
9645 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9646 * entry, but only if the current (host) sp changed from the value
9647 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9648 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9649 * here we just force the write to happen on entry.
9653 exec_control = vmx_exec_control(vmx); /* L0's desires */
9654 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9655 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9656 exec_control &= ~CPU_BASED_TPR_SHADOW;
9657 exec_control |= vmcs12->cpu_based_vm_exec_control;
9659 if (exec_control & CPU_BASED_TPR_SHADOW) {
9660 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9661 page_to_phys(vmx->nested.virtual_apic_page));
9662 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9665 if (cpu_has_vmx_msr_bitmap() &&
9666 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9667 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9668 /* MSR_BITMAP will be set by following vmx_set_efer. */
9670 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9673 * Merging of IO bitmap not currently supported.
9674 * Rather, exit every time.
9676 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9677 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9679 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9681 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9682 * bitwise-or of what L1 wants to trap for L2, and what we want to
9683 * trap. Note that CR0.TS also needs updating - we do this later.
9685 update_exception_bitmap(vcpu);
9686 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9687 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9689 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9690 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9691 * bits are further modified by vmx_set_efer() below.
9693 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9695 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9696 * emulated by vmx_set_efer(), below.
9698 vm_entry_controls_init(vmx,
9699 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9700 ~VM_ENTRY_IA32E_MODE) |
9701 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9703 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9704 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9705 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9706 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9707 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9710 set_cr4_guest_host_mask(vmx);
9712 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9713 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9715 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9716 vmcs_write64(TSC_OFFSET,
9717 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9719 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9723 * There is no direct mapping between vpid02 and vpid12, the
9724 * vpid02 is per-vCPU for L0 and reused while the value of
9725 * vpid12 is changed w/ one invvpid during nested vmentry.
9726 * The vpid12 is allocated by L1 for L2, so it will not
9727 * influence global bitmap(for vpid01 and vpid02 allocation)
9728 * even if spawn a lot of nested vCPUs.
9730 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9731 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9732 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9733 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9734 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9737 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9738 vmx_flush_tlb(vcpu);
9743 if (nested_cpu_has_ept(vmcs12)) {
9744 kvm_mmu_unload(vcpu);
9745 nested_ept_init_mmu_context(vcpu);
9748 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9749 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9750 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9751 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9753 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9754 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9755 vmx_set_efer(vcpu, vcpu->arch.efer);
9758 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9759 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9760 * The CR0_READ_SHADOW is what L2 should have expected to read given
9761 * the specifications by L1; It's not enough to take
9762 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9763 * have more bits than L1 expected.
9765 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9766 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9768 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9769 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9771 /* shadow page tables on either EPT or shadow page tables */
9772 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9773 kvm_mmu_reset_context(vcpu);
9776 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9779 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9782 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9783 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9784 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9785 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9788 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9789 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9793 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9794 * for running an L2 nested guest.
9796 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9798 struct vmcs12 *vmcs12;
9799 struct vcpu_vmx *vmx = to_vmx(vcpu);
9801 struct loaded_vmcs *vmcs02;
9805 if (!nested_vmx_check_permission(vcpu) ||
9806 !nested_vmx_check_vmcs12(vcpu))
9809 skip_emulated_instruction(vcpu);
9810 vmcs12 = get_vmcs12(vcpu);
9812 if (enable_shadow_vmcs)
9813 copy_shadow_to_vmcs12(vmx);
9816 * The nested entry process starts with enforcing various prerequisites
9817 * on vmcs12 as required by the Intel SDM, and act appropriately when
9818 * they fail: As the SDM explains, some conditions should cause the
9819 * instruction to fail, while others will cause the instruction to seem
9820 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9821 * To speed up the normal (success) code path, we should avoid checking
9822 * for misconfigurations which will anyway be caught by the processor
9823 * when using the merged vmcs02.
9825 if (vmcs12->launch_state == launch) {
9826 nested_vmx_failValid(vcpu,
9827 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9828 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9832 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9833 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9834 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9838 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9839 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9843 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9844 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9848 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9849 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9853 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9854 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9858 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9859 vmx->nested.nested_vmx_true_procbased_ctls_low,
9860 vmx->nested.nested_vmx_procbased_ctls_high) ||
9861 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9862 vmx->nested.nested_vmx_secondary_ctls_low,
9863 vmx->nested.nested_vmx_secondary_ctls_high) ||
9864 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9865 vmx->nested.nested_vmx_pinbased_ctls_low,
9866 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9867 !vmx_control_verify(vmcs12->vm_exit_controls,
9868 vmx->nested.nested_vmx_true_exit_ctls_low,
9869 vmx->nested.nested_vmx_exit_ctls_high) ||
9870 !vmx_control_verify(vmcs12->vm_entry_controls,
9871 vmx->nested.nested_vmx_true_entry_ctls_low,
9872 vmx->nested.nested_vmx_entry_ctls_high))
9874 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9878 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9879 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9880 nested_vmx_failValid(vcpu,
9881 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9885 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9886 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9887 nested_vmx_entry_failure(vcpu, vmcs12,
9888 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9891 if (vmcs12->vmcs_link_pointer != -1ull) {
9892 nested_vmx_entry_failure(vcpu, vmcs12,
9893 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9898 * If the load IA32_EFER VM-entry control is 1, the following checks
9899 * are performed on the field for the IA32_EFER MSR:
9900 * - Bits reserved in the IA32_EFER MSR must be 0.
9901 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9902 * the IA-32e mode guest VM-exit control. It must also be identical
9903 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9906 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9907 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9908 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9909 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9910 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9911 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9912 nested_vmx_entry_failure(vcpu, vmcs12,
9913 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9919 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9920 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9921 * the values of the LMA and LME bits in the field must each be that of
9922 * the host address-space size VM-exit control.
9924 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9925 ia32e = (vmcs12->vm_exit_controls &
9926 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9927 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9928 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9929 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9930 nested_vmx_entry_failure(vcpu, vmcs12,
9931 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9937 * We're finally done with prerequisite checking, and can start with
9941 vmcs02 = nested_get_current_vmcs02(vmx);
9945 enter_guest_mode(vcpu);
9947 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9949 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9950 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9953 vmx->loaded_vmcs = vmcs02;
9955 vmx_vcpu_load(vcpu, cpu);
9959 vmx_segment_cache_clear(vmx);
9961 prepare_vmcs02(vcpu, vmcs12);
9963 msr_entry_idx = nested_vmx_load_msr(vcpu,
9964 vmcs12->vm_entry_msr_load_addr,
9965 vmcs12->vm_entry_msr_load_count);
9966 if (msr_entry_idx) {
9967 leave_guest_mode(vcpu);
9968 vmx_load_vmcs01(vcpu);
9969 nested_vmx_entry_failure(vcpu, vmcs12,
9970 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9974 vmcs12->launch_state = 1;
9976 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9977 return kvm_vcpu_halt(vcpu);
9979 vmx->nested.nested_run_pending = 1;
9982 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9983 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9984 * returned as far as L1 is concerned. It will only return (and set
9985 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9991 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9992 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9993 * This function returns the new value we should put in vmcs12.guest_cr0.
9994 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9995 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9996 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9997 * didn't trap the bit, because if L1 did, so would L0).
9998 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9999 * been modified by L2, and L1 knows it. So just leave the old value of
10000 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10001 * isn't relevant, because if L0 traps this bit it can set it to anything.
10002 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10003 * changed these bits, and therefore they need to be updated, but L0
10004 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10005 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10007 static inline unsigned long
10008 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10011 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10012 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10013 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10014 vcpu->arch.cr0_guest_owned_bits));
10017 static inline unsigned long
10018 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10021 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10022 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10023 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10024 vcpu->arch.cr4_guest_owned_bits));
10027 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10028 struct vmcs12 *vmcs12)
10033 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10034 nr = vcpu->arch.exception.nr;
10035 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10037 if (kvm_exception_is_soft(nr)) {
10038 vmcs12->vm_exit_instruction_len =
10039 vcpu->arch.event_exit_inst_len;
10040 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10042 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10044 if (vcpu->arch.exception.has_error_code) {
10045 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10046 vmcs12->idt_vectoring_error_code =
10047 vcpu->arch.exception.error_code;
10050 vmcs12->idt_vectoring_info_field = idt_vectoring;
10051 } else if (vcpu->arch.nmi_injected) {
10052 vmcs12->idt_vectoring_info_field =
10053 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10054 } else if (vcpu->arch.interrupt.pending) {
10055 nr = vcpu->arch.interrupt.nr;
10056 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10058 if (vcpu->arch.interrupt.soft) {
10059 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10060 vmcs12->vm_entry_instruction_len =
10061 vcpu->arch.event_exit_inst_len;
10063 idt_vectoring |= INTR_TYPE_EXT_INTR;
10065 vmcs12->idt_vectoring_info_field = idt_vectoring;
10069 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10071 struct vcpu_vmx *vmx = to_vmx(vcpu);
10073 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10074 vmx->nested.preemption_timer_expired) {
10075 if (vmx->nested.nested_run_pending)
10077 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10081 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10082 if (vmx->nested.nested_run_pending ||
10083 vcpu->arch.interrupt.pending)
10085 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10086 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10087 INTR_INFO_VALID_MASK, 0);
10089 * The NMI-triggered VM exit counts as injection:
10090 * clear this one and block further NMIs.
10092 vcpu->arch.nmi_pending = 0;
10093 vmx_set_nmi_mask(vcpu, true);
10097 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10098 nested_exit_on_intr(vcpu)) {
10099 if (vmx->nested.nested_run_pending)
10101 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10105 return vmx_complete_nested_posted_interrupt(vcpu);
10108 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10110 ktime_t remaining =
10111 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10114 if (ktime_to_ns(remaining) <= 0)
10117 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10118 do_div(value, 1000000);
10119 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10123 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10124 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10125 * and this function updates it to reflect the changes to the guest state while
10126 * L2 was running (and perhaps made some exits which were handled directly by L0
10127 * without going back to L1), and to reflect the exit reason.
10128 * Note that we do not have to copy here all VMCS fields, just those that
10129 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10130 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10131 * which already writes to vmcs12 directly.
10133 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10134 u32 exit_reason, u32 exit_intr_info,
10135 unsigned long exit_qualification)
10137 /* update guest state fields: */
10138 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10139 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10141 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10142 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10143 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10145 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10146 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10147 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10148 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10149 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10150 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10151 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10152 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10153 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10154 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10155 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10156 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10157 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10158 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10159 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10160 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10161 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10162 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10163 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10164 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10165 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10166 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10167 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10168 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10169 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10170 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10171 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10172 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10173 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10174 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10175 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10176 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10177 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10178 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10179 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10180 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10182 vmcs12->guest_interruptibility_info =
10183 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10184 vmcs12->guest_pending_dbg_exceptions =
10185 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10186 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10187 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10189 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10191 if (nested_cpu_has_preemption_timer(vmcs12)) {
10192 if (vmcs12->vm_exit_controls &
10193 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10194 vmcs12->vmx_preemption_timer_value =
10195 vmx_get_preemption_timer_value(vcpu);
10196 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10200 * In some cases (usually, nested EPT), L2 is allowed to change its
10201 * own CR3 without exiting. If it has changed it, we must keep it.
10202 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10203 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10205 * Additionally, restore L2's PDPTR to vmcs12.
10208 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10209 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10210 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10211 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10212 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10215 if (nested_cpu_has_vid(vmcs12))
10216 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10218 vmcs12->vm_entry_controls =
10219 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10220 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10222 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10223 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10224 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10227 /* TODO: These cannot have changed unless we have MSR bitmaps and
10228 * the relevant bit asks not to trap the change */
10229 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10230 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10231 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10232 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10233 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10234 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10235 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10236 if (vmx_mpx_supported())
10237 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10238 if (nested_cpu_has_xsaves(vmcs12))
10239 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10241 /* update exit information fields: */
10243 vmcs12->vm_exit_reason = exit_reason;
10244 vmcs12->exit_qualification = exit_qualification;
10246 vmcs12->vm_exit_intr_info = exit_intr_info;
10247 if ((vmcs12->vm_exit_intr_info &
10248 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10249 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10250 vmcs12->vm_exit_intr_error_code =
10251 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10252 vmcs12->idt_vectoring_info_field = 0;
10253 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10254 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10256 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10257 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10258 * instead of reading the real value. */
10259 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10262 * Transfer the event that L0 or L1 may wanted to inject into
10263 * L2 to IDT_VECTORING_INFO_FIELD.
10265 vmcs12_save_pending_event(vcpu, vmcs12);
10269 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10270 * preserved above and would only end up incorrectly in L1.
10272 vcpu->arch.nmi_injected = false;
10273 kvm_clear_exception_queue(vcpu);
10274 kvm_clear_interrupt_queue(vcpu);
10278 * A part of what we need to when the nested L2 guest exits and we want to
10279 * run its L1 parent, is to reset L1's guest state to the host state specified
10281 * This function is to be called not only on normal nested exit, but also on
10282 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10283 * Failures During or After Loading Guest State").
10284 * This function should be called when the active VMCS is L1's (vmcs01).
10286 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10287 struct vmcs12 *vmcs12)
10289 struct kvm_segment seg;
10291 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10292 vcpu->arch.efer = vmcs12->host_ia32_efer;
10293 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10294 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10296 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10297 vmx_set_efer(vcpu, vcpu->arch.efer);
10299 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10300 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10301 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10303 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10304 * actually changed, because it depends on the current state of
10305 * fpu_active (which may have changed).
10306 * Note that vmx_set_cr0 refers to efer set above.
10308 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10310 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10311 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10312 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10314 update_exception_bitmap(vcpu);
10315 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10316 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10319 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10320 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10322 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10323 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10325 nested_ept_uninit_mmu_context(vcpu);
10327 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10328 kvm_mmu_reset_context(vcpu);
10331 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10335 * Trivially support vpid by letting L2s share their parent
10336 * L1's vpid. TODO: move to a more elaborate solution, giving
10337 * each L2 its own vpid and exposing the vpid feature to L1.
10339 vmx_flush_tlb(vcpu);
10343 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10344 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10345 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10346 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10347 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10349 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10350 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10351 vmcs_write64(GUEST_BNDCFGS, 0);
10353 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10354 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10355 vcpu->arch.pat = vmcs12->host_ia32_pat;
10357 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10358 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10359 vmcs12->host_ia32_perf_global_ctrl);
10361 /* Set L1 segment info according to Intel SDM
10362 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10363 seg = (struct kvm_segment) {
10365 .limit = 0xFFFFFFFF,
10366 .selector = vmcs12->host_cs_selector,
10372 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10376 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10377 seg = (struct kvm_segment) {
10379 .limit = 0xFFFFFFFF,
10386 seg.selector = vmcs12->host_ds_selector;
10387 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10388 seg.selector = vmcs12->host_es_selector;
10389 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10390 seg.selector = vmcs12->host_ss_selector;
10391 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10392 seg.selector = vmcs12->host_fs_selector;
10393 seg.base = vmcs12->host_fs_base;
10394 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10395 seg.selector = vmcs12->host_gs_selector;
10396 seg.base = vmcs12->host_gs_base;
10397 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10398 seg = (struct kvm_segment) {
10399 .base = vmcs12->host_tr_base,
10401 .selector = vmcs12->host_tr_selector,
10405 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10407 kvm_set_dr(vcpu, 7, 0x400);
10408 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10410 if (cpu_has_vmx_msr_bitmap())
10411 vmx_set_msr_bitmap(vcpu);
10413 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10414 vmcs12->vm_exit_msr_load_count))
10415 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10419 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10420 * and modify vmcs12 to make it see what it would expect to see there if
10421 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10423 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10424 u32 exit_intr_info,
10425 unsigned long exit_qualification)
10427 struct vcpu_vmx *vmx = to_vmx(vcpu);
10428 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10430 /* trying to cancel vmlaunch/vmresume is a bug */
10431 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10433 leave_guest_mode(vcpu);
10434 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10435 exit_qualification);
10437 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10438 vmcs12->vm_exit_msr_store_count))
10439 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10441 vmx_load_vmcs01(vcpu);
10443 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10444 && nested_exit_intr_ack_set(vcpu)) {
10445 int irq = kvm_cpu_get_interrupt(vcpu);
10447 vmcs12->vm_exit_intr_info = irq |
10448 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10451 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10452 vmcs12->exit_qualification,
10453 vmcs12->idt_vectoring_info_field,
10454 vmcs12->vm_exit_intr_info,
10455 vmcs12->vm_exit_intr_error_code,
10458 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10459 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10460 vmx_segment_cache_clear(vmx);
10462 /* if no vmcs02 cache requested, remove the one we used */
10463 if (VMCS02_POOL_SIZE == 0)
10464 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10466 load_vmcs12_host_state(vcpu, vmcs12);
10468 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10469 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10471 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10474 /* Unpin physical memory we referred to in vmcs02 */
10475 if (vmx->nested.apic_access_page) {
10476 nested_release_page(vmx->nested.apic_access_page);
10477 vmx->nested.apic_access_page = NULL;
10479 if (vmx->nested.virtual_apic_page) {
10480 nested_release_page(vmx->nested.virtual_apic_page);
10481 vmx->nested.virtual_apic_page = NULL;
10483 if (vmx->nested.pi_desc_page) {
10484 kunmap(vmx->nested.pi_desc_page);
10485 nested_release_page(vmx->nested.pi_desc_page);
10486 vmx->nested.pi_desc_page = NULL;
10487 vmx->nested.pi_desc = NULL;
10491 * We are now running in L2, mmu_notifier will force to reload the
10492 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10494 kvm_vcpu_reload_apic_access_page(vcpu);
10497 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10498 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10499 * success or failure flag accordingly.
10501 if (unlikely(vmx->fail)) {
10503 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10505 nested_vmx_succeed(vcpu);
10506 if (enable_shadow_vmcs)
10507 vmx->nested.sync_shadow_vmcs = true;
10509 /* in case we halted in L2 */
10510 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10514 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10516 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10518 if (is_guest_mode(vcpu))
10519 nested_vmx_vmexit(vcpu, -1, 0, 0);
10520 free_nested(to_vmx(vcpu));
10524 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10525 * 23.7 "VM-entry failures during or after loading guest state" (this also
10526 * lists the acceptable exit-reason and exit-qualification parameters).
10527 * It should only be called before L2 actually succeeded to run, and when
10528 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10530 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10531 struct vmcs12 *vmcs12,
10532 u32 reason, unsigned long qualification)
10534 load_vmcs12_host_state(vcpu, vmcs12);
10535 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10536 vmcs12->exit_qualification = qualification;
10537 nested_vmx_succeed(vcpu);
10538 if (enable_shadow_vmcs)
10539 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10542 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10543 struct x86_instruction_info *info,
10544 enum x86_intercept_stage stage)
10546 return X86EMUL_CONTINUE;
10549 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10552 shrink_ple_window(vcpu);
10555 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10556 struct kvm_memory_slot *slot)
10558 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10559 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10562 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10563 struct kvm_memory_slot *slot)
10565 kvm_mmu_slot_set_dirty(kvm, slot);
10568 static void vmx_flush_log_dirty(struct kvm *kvm)
10570 kvm_flush_pml_buffers(kvm);
10573 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10574 struct kvm_memory_slot *memslot,
10575 gfn_t offset, unsigned long mask)
10577 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10581 * This routine does the following things for vCPU which is going
10582 * to be blocked if VT-d PI is enabled.
10583 * - Store the vCPU to the wakeup list, so when interrupts happen
10584 * we can find the right vCPU to wake up.
10585 * - Change the Posted-interrupt descriptor as below:
10586 * 'NDST' <-- vcpu->pre_pcpu
10587 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10588 * - If 'ON' is set during this process, which means at least one
10589 * interrupt is posted for this vCPU, we cannot block it, in
10590 * this case, return 1, otherwise, return 0.
10593 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10595 unsigned long flags;
10597 struct pi_desc old, new;
10598 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10600 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10601 !irq_remapping_cap(IRQ_POSTING_CAP))
10604 vcpu->pre_pcpu = vcpu->cpu;
10605 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10606 vcpu->pre_pcpu), flags);
10607 list_add_tail(&vcpu->blocked_vcpu_list,
10608 &per_cpu(blocked_vcpu_on_cpu,
10610 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10611 vcpu->pre_pcpu), flags);
10614 old.control = new.control = pi_desc->control;
10617 * We should not block the vCPU if
10618 * an interrupt is posted for it.
10620 if (pi_test_on(pi_desc) == 1) {
10621 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10622 vcpu->pre_pcpu), flags);
10623 list_del(&vcpu->blocked_vcpu_list);
10624 spin_unlock_irqrestore(
10625 &per_cpu(blocked_vcpu_on_cpu_lock,
10626 vcpu->pre_pcpu), flags);
10627 vcpu->pre_pcpu = -1;
10632 WARN((pi_desc->sn == 1),
10633 "Warning: SN field of posted-interrupts "
10634 "is set before blocking\n");
10637 * Since vCPU can be preempted during this process,
10638 * vcpu->cpu could be different with pre_pcpu, we
10639 * need to set pre_pcpu as the destination of wakeup
10640 * notification event, then we can find the right vCPU
10641 * to wakeup in wakeup handler if interrupts happen
10642 * when the vCPU is in blocked state.
10644 dest = cpu_physical_id(vcpu->pre_pcpu);
10646 if (x2apic_enabled())
10649 new.ndst = (dest << 8) & 0xFF00;
10651 /* set 'NV' to 'wakeup vector' */
10652 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10653 } while (cmpxchg(&pi_desc->control, old.control,
10654 new.control) != old.control);
10659 static void vmx_post_block(struct kvm_vcpu *vcpu)
10661 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10662 struct pi_desc old, new;
10664 unsigned long flags;
10666 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10667 !irq_remapping_cap(IRQ_POSTING_CAP))
10671 old.control = new.control = pi_desc->control;
10673 dest = cpu_physical_id(vcpu->cpu);
10675 if (x2apic_enabled())
10678 new.ndst = (dest << 8) & 0xFF00;
10680 /* Allow posting non-urgent interrupts */
10683 /* set 'NV' to 'notification vector' */
10684 new.nv = POSTED_INTR_VECTOR;
10685 } while (cmpxchg(&pi_desc->control, old.control,
10686 new.control) != old.control);
10688 if(vcpu->pre_pcpu != -1) {
10690 &per_cpu(blocked_vcpu_on_cpu_lock,
10691 vcpu->pre_pcpu), flags);
10692 list_del(&vcpu->blocked_vcpu_list);
10693 spin_unlock_irqrestore(
10694 &per_cpu(blocked_vcpu_on_cpu_lock,
10695 vcpu->pre_pcpu), flags);
10696 vcpu->pre_pcpu = -1;
10701 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10704 * @host_irq: host irq of the interrupt
10705 * @guest_irq: gsi of the interrupt
10706 * @set: set or unset PI
10707 * returns 0 on success, < 0 on failure
10709 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10710 uint32_t guest_irq, bool set)
10712 struct kvm_kernel_irq_routing_entry *e;
10713 struct kvm_irq_routing_table *irq_rt;
10714 struct kvm_lapic_irq irq;
10715 struct kvm_vcpu *vcpu;
10716 struct vcpu_data vcpu_info;
10717 int idx, ret = -EINVAL;
10719 if (!kvm_arch_has_assigned_device(kvm) ||
10720 !irq_remapping_cap(IRQ_POSTING_CAP))
10723 idx = srcu_read_lock(&kvm->irq_srcu);
10724 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10725 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10727 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10728 if (e->type != KVM_IRQ_ROUTING_MSI)
10731 * VT-d PI cannot support posting multicast/broadcast
10732 * interrupts to a vCPU, we still use interrupt remapping
10733 * for these kind of interrupts.
10735 * For lowest-priority interrupts, we only support
10736 * those with single CPU as the destination, e.g. user
10737 * configures the interrupts via /proc/irq or uses
10738 * irqbalance to make the interrupts single-CPU.
10740 * We will support full lowest-priority interrupt later.
10743 kvm_set_msi_irq(e, &irq);
10744 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10747 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10748 vcpu_info.vector = irq.vector;
10750 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10751 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10754 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10756 /* suppress notification event before unposting */
10757 pi_set_sn(vcpu_to_pi_desc(vcpu));
10758 ret = irq_set_vcpu_affinity(host_irq, NULL);
10759 pi_clear_sn(vcpu_to_pi_desc(vcpu));
10763 printk(KERN_INFO "%s: failed to update PI IRTE\n",
10771 srcu_read_unlock(&kvm->irq_srcu, idx);
10775 static struct kvm_x86_ops vmx_x86_ops = {
10776 .cpu_has_kvm_support = cpu_has_kvm_support,
10777 .disabled_by_bios = vmx_disabled_by_bios,
10778 .hardware_setup = hardware_setup,
10779 .hardware_unsetup = hardware_unsetup,
10780 .check_processor_compatibility = vmx_check_processor_compat,
10781 .hardware_enable = hardware_enable,
10782 .hardware_disable = hardware_disable,
10783 .cpu_has_accelerated_tpr = report_flexpriority,
10784 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10786 .vcpu_create = vmx_create_vcpu,
10787 .vcpu_free = vmx_free_vcpu,
10788 .vcpu_reset = vmx_vcpu_reset,
10790 .prepare_guest_switch = vmx_save_host_state,
10791 .vcpu_load = vmx_vcpu_load,
10792 .vcpu_put = vmx_vcpu_put,
10794 .update_bp_intercept = update_exception_bitmap,
10795 .get_msr = vmx_get_msr,
10796 .set_msr = vmx_set_msr,
10797 .get_segment_base = vmx_get_segment_base,
10798 .get_segment = vmx_get_segment,
10799 .set_segment = vmx_set_segment,
10800 .get_cpl = vmx_get_cpl,
10801 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10802 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10803 .decache_cr3 = vmx_decache_cr3,
10804 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10805 .set_cr0 = vmx_set_cr0,
10806 .set_cr3 = vmx_set_cr3,
10807 .set_cr4 = vmx_set_cr4,
10808 .set_efer = vmx_set_efer,
10809 .get_idt = vmx_get_idt,
10810 .set_idt = vmx_set_idt,
10811 .get_gdt = vmx_get_gdt,
10812 .set_gdt = vmx_set_gdt,
10813 .get_dr6 = vmx_get_dr6,
10814 .set_dr6 = vmx_set_dr6,
10815 .set_dr7 = vmx_set_dr7,
10816 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10817 .cache_reg = vmx_cache_reg,
10818 .get_rflags = vmx_get_rflags,
10819 .set_rflags = vmx_set_rflags,
10820 .fpu_activate = vmx_fpu_activate,
10821 .fpu_deactivate = vmx_fpu_deactivate,
10823 .tlb_flush = vmx_flush_tlb,
10825 .run = vmx_vcpu_run,
10826 .handle_exit = vmx_handle_exit,
10827 .skip_emulated_instruction = skip_emulated_instruction,
10828 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10829 .get_interrupt_shadow = vmx_get_interrupt_shadow,
10830 .patch_hypercall = vmx_patch_hypercall,
10831 .set_irq = vmx_inject_irq,
10832 .set_nmi = vmx_inject_nmi,
10833 .queue_exception = vmx_queue_exception,
10834 .cancel_injection = vmx_cancel_injection,
10835 .interrupt_allowed = vmx_interrupt_allowed,
10836 .nmi_allowed = vmx_nmi_allowed,
10837 .get_nmi_mask = vmx_get_nmi_mask,
10838 .set_nmi_mask = vmx_set_nmi_mask,
10839 .enable_nmi_window = enable_nmi_window,
10840 .enable_irq_window = enable_irq_window,
10841 .update_cr8_intercept = update_cr8_intercept,
10842 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10843 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10844 .cpu_uses_apicv = vmx_cpu_uses_apicv,
10845 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10846 .hwapic_irr_update = vmx_hwapic_irr_update,
10847 .hwapic_isr_update = vmx_hwapic_isr_update,
10848 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10849 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10851 .set_tss_addr = vmx_set_tss_addr,
10852 .get_tdp_level = get_ept_level,
10853 .get_mt_mask = vmx_get_mt_mask,
10855 .get_exit_info = vmx_get_exit_info,
10857 .get_lpage_level = vmx_get_lpage_level,
10859 .cpuid_update = vmx_cpuid_update,
10861 .rdtscp_supported = vmx_rdtscp_supported,
10862 .invpcid_supported = vmx_invpcid_supported,
10864 .set_supported_cpuid = vmx_set_supported_cpuid,
10866 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10868 .read_tsc_offset = vmx_read_tsc_offset,
10869 .write_tsc_offset = vmx_write_tsc_offset,
10870 .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10871 .read_l1_tsc = vmx_read_l1_tsc,
10873 .set_tdp_cr3 = vmx_set_cr3,
10875 .check_intercept = vmx_check_intercept,
10876 .handle_external_intr = vmx_handle_external_intr,
10877 .mpx_supported = vmx_mpx_supported,
10878 .xsaves_supported = vmx_xsaves_supported,
10880 .check_nested_events = vmx_check_nested_events,
10882 .sched_in = vmx_sched_in,
10884 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10885 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10886 .flush_log_dirty = vmx_flush_log_dirty,
10887 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10889 .pre_block = vmx_pre_block,
10890 .post_block = vmx_post_block,
10892 .pmu_ops = &intel_pmu_ops,
10894 .update_pi_irte = vmx_update_pi_irte,
10897 static int __init vmx_init(void)
10899 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10900 __alignof__(struct vcpu_vmx), THIS_MODULE);
10904 #ifdef CONFIG_KEXEC_CORE
10905 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10906 crash_vmclear_local_loaded_vmcss);
10912 static void __exit vmx_exit(void)
10914 #ifdef CONFIG_KEXEC_CORE
10915 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10922 module_init(vmx_init)
10923 module_exit(vmx_exit)