arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv_reg_vid;
  88
  89 /*
  90  * If nested=1, nested virtualization is supported, i.e., guests may use
  91  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  92  * use VMX instructions.
  93  */
  94 static bool __read_mostly nested = 0;
  95 module_param(nested, bool, S_IRUGO);
  96
  97 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
  98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
  99 #define KVM_VM_CR0_ALWAYS_ON                                            \
 100         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 101 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 102         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 103          | X86_CR4_OSXMMEXCPT)
 104
 105 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 106 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 107
 108 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 109
 110 /*
 111  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 112  * ple_gap:    upper bound on the amount of time between two successive
 113  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 114  *             According to test, this time is usually smaller than 128 cycles.
 115  * ple_window: upper bound on the amount of time a guest is allowed to execute
 116  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 117  *             less than 2^12 cycles
 118  * Time is measured based on a counter that runs at the same rate as the TSC,
 119  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 120  */
 121 #define KVM_VMX_DEFAULT_PLE_GAP    128
 122 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 123 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 124 module_param(ple_gap, int, S_IRUGO);
 125
 126 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 127 module_param(ple_window, int, S_IRUGO);
 128
 129 extern const ulong vmx_return;
 130
 131 #define NR_AUTOLOAD_MSRS 8
 132 #define VMCS02_POOL_SIZE 1
 133
 134 struct vmcs {
 135         u32 revision_id;
 136         u32 abort;
 137         char data[0];
 138 };
 139
 140 /*
 141  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 142  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 143  * loaded on this CPU (so we can clear them if the CPU goes down).
 144  */
 145 struct loaded_vmcs {
 146         struct vmcs *vmcs;
 147         int cpu;
 148         int launched;
 149         struct list_head loaded_vmcss_on_cpu_link;
 150 };
 151
 152 struct shared_msr_entry {
 153         unsigned index;
 154         u64 data;
 155         u64 mask;
 156 };
 157
 158 /*
 159  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 160  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 161  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 162  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 163  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 164  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 165  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 166  * underlying hardware which will be used to run L2.
 167  * This structure is packed to ensure that its layout is identical across
 168  * machines (necessary for live migration).
 169  * If there are changes in this struct, VMCS12_REVISION must be changed.
 170  */
 171 typedef u64 natural_width;
 172 struct __packed vmcs12 {
 173         /* According to the Intel spec, a VMCS region must start with the
 174          * following two fields. Then follow implementation-specific data.
 175          */
 176         u32 revision_id;
 177         u32 abort;
 178
 179         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 180         u32 padding[7]; /* room for future expansion */
 181
 182         u64 io_bitmap_a;
 183         u64 io_bitmap_b;
 184         u64 msr_bitmap;
 185         u64 vm_exit_msr_store_addr;
 186         u64 vm_exit_msr_load_addr;
 187         u64 vm_entry_msr_load_addr;
 188         u64 tsc_offset;
 189         u64 virtual_apic_page_addr;
 190         u64 apic_access_addr;
 191         u64 ept_pointer;
 192         u64 guest_physical_address;
 193         u64 vmcs_link_pointer;
 194         u64 guest_ia32_debugctl;
 195         u64 guest_ia32_pat;
 196         u64 guest_ia32_efer;
 197         u64 guest_ia32_perf_global_ctrl;
 198         u64 guest_pdptr0;
 199         u64 guest_pdptr1;
 200         u64 guest_pdptr2;
 201         u64 guest_pdptr3;
 202         u64 host_ia32_pat;
 203         u64 host_ia32_efer;
 204         u64 host_ia32_perf_global_ctrl;
 205         u64 padding64[8]; /* room for future expansion */
 206         /*
 207          * To allow migration of L1 (complete with its L2 guests) between
 208          * machines of different natural widths (32 or 64 bit), we cannot have
 209          * unsigned long fields with no explict size. We use u64 (aliased
 210          * natural_width) instead. Luckily, x86 is little-endian.
 211          */
 212         natural_width cr0_guest_host_mask;
 213         natural_width cr4_guest_host_mask;
 214         natural_width cr0_read_shadow;
 215         natural_width cr4_read_shadow;
 216         natural_width cr3_target_value0;
 217         natural_width cr3_target_value1;
 218         natural_width cr3_target_value2;
 219         natural_width cr3_target_value3;
 220         natural_width exit_qualification;
 221         natural_width guest_linear_address;
 222         natural_width guest_cr0;
 223         natural_width guest_cr3;
 224         natural_width guest_cr4;
 225         natural_width guest_es_base;
 226         natural_width guest_cs_base;
 227         natural_width guest_ss_base;
 228         natural_width guest_ds_base;
 229         natural_width guest_fs_base;
 230         natural_width guest_gs_base;
 231         natural_width guest_ldtr_base;
 232         natural_width guest_tr_base;
 233         natural_width guest_gdtr_base;
 234         natural_width guest_idtr_base;
 235         natural_width guest_dr7;
 236         natural_width guest_rsp;
 237         natural_width guest_rip;
 238         natural_width guest_rflags;
 239         natural_width guest_pending_dbg_exceptions;
 240         natural_width guest_sysenter_esp;
 241         natural_width guest_sysenter_eip;
 242         natural_width host_cr0;
 243         natural_width host_cr3;
 244         natural_width host_cr4;
 245         natural_width host_fs_base;
 246         natural_width host_gs_base;
 247         natural_width host_tr_base;
 248         natural_width host_gdtr_base;
 249         natural_width host_idtr_base;
 250         natural_width host_ia32_sysenter_esp;
 251         natural_width host_ia32_sysenter_eip;
 252         natural_width host_rsp;
 253         natural_width host_rip;
 254         natural_width paddingl[8]; /* room for future expansion */
 255         u32 pin_based_vm_exec_control;
 256         u32 cpu_based_vm_exec_control;
 257         u32 exception_bitmap;
 258         u32 page_fault_error_code_mask;
 259         u32 page_fault_error_code_match;
 260         u32 cr3_target_count;
 261         u32 vm_exit_controls;
 262         u32 vm_exit_msr_store_count;
 263         u32 vm_exit_msr_load_count;
 264         u32 vm_entry_controls;
 265         u32 vm_entry_msr_load_count;
 266         u32 vm_entry_intr_info_field;
 267         u32 vm_entry_exception_error_code;
 268         u32 vm_entry_instruction_len;
 269         u32 tpr_threshold;
 270         u32 secondary_vm_exec_control;
 271         u32 vm_instruction_error;
 272         u32 vm_exit_reason;
 273         u32 vm_exit_intr_info;
 274         u32 vm_exit_intr_error_code;
 275         u32 idt_vectoring_info_field;
 276         u32 idt_vectoring_error_code;
 277         u32 vm_exit_instruction_len;
 278         u32 vmx_instruction_info;
 279         u32 guest_es_limit;
 280         u32 guest_cs_limit;
 281         u32 guest_ss_limit;
 282         u32 guest_ds_limit;
 283         u32 guest_fs_limit;
 284         u32 guest_gs_limit;
 285         u32 guest_ldtr_limit;
 286         u32 guest_tr_limit;
 287         u32 guest_gdtr_limit;
 288         u32 guest_idtr_limit;
 289         u32 guest_es_ar_bytes;
 290         u32 guest_cs_ar_bytes;
 291         u32 guest_ss_ar_bytes;
 292         u32 guest_ds_ar_bytes;
 293         u32 guest_fs_ar_bytes;
 294         u32 guest_gs_ar_bytes;
 295         u32 guest_ldtr_ar_bytes;
 296         u32 guest_tr_ar_bytes;
 297         u32 guest_interruptibility_info;
 298         u32 guest_activity_state;
 299         u32 guest_sysenter_cs;
 300         u32 host_ia32_sysenter_cs;
 301         u32 padding32[8]; /* room for future expansion */
 302         u16 virtual_processor_id;
 303         u16 guest_es_selector;
 304         u16 guest_cs_selector;
 305         u16 guest_ss_selector;
 306         u16 guest_ds_selector;
 307         u16 guest_fs_selector;
 308         u16 guest_gs_selector;
 309         u16 guest_ldtr_selector;
 310         u16 guest_tr_selector;
 311         u16 host_es_selector;
 312         u16 host_cs_selector;
 313         u16 host_ss_selector;
 314         u16 host_ds_selector;
 315         u16 host_fs_selector;
 316         u16 host_gs_selector;
 317         u16 host_tr_selector;
 318 };
 319
 320 /*
 321  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 322  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 323  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 324  */
 325 #define VMCS12_REVISION 0x11e57ed0
 326
 327 /*
 328  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 329  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 330  * current implementation, 4K are reserved to avoid future complications.
 331  */
 332 #define VMCS12_SIZE 0x1000
 333
 334 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 335 struct vmcs02_list {
 336         struct list_head list;
 337         gpa_t vmptr;
 338         struct loaded_vmcs vmcs02;
 339 };
 340
 341 /*
 342  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 343  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 344  */
 345 struct nested_vmx {
 346         /* Has the level1 guest done vmxon? */
 347         bool vmxon;
 348
 349         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 350         gpa_t current_vmptr;
 351         /* The host-usable pointer to the above */
 352         struct page *current_vmcs12_page;
 353         struct vmcs12 *current_vmcs12;
 354
 355         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 356         struct list_head vmcs02_pool;
 357         int vmcs02_num;
 358         u64 vmcs01_tsc_offset;
 359         /* L2 must run next, and mustn't decide to exit to L1. */
 360         bool nested_run_pending;
 361         /*
 362          * Guest pages referred to in vmcs02 with host-physical pointers, so
 363          * we must keep them pinned while L2 runs.
 364          */
 365         struct page *apic_access_page;
 366 };
 367
 368 struct vcpu_vmx {
 369         struct kvm_vcpu       vcpu;
 370         unsigned long         host_rsp;
 371         u8                    fail;
 372         u8                    cpl;
 373         bool                  nmi_known_unmasked;
 374         u32                   exit_intr_info;
 375         u32                   idt_vectoring_info;
 376         ulong                 rflags;
 377         struct shared_msr_entry *guest_msrs;
 378         int                   nmsrs;
 379         int                   save_nmsrs;
 380 #ifdef CONFIG_X86_64
 381         u64                   msr_host_kernel_gs_base;
 382         u64                   msr_guest_kernel_gs_base;
 383 #endif
 384         /*
 385          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 386          * non-nested (L1) guest, it always points to vmcs01. For a nested
 387          * guest (L2), it points to a different VMCS.
 388          */
 389         struct loaded_vmcs    vmcs01;
 390         struct loaded_vmcs   *loaded_vmcs;
 391         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 392         struct msr_autoload {
 393                 unsigned nr;
 394                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 395                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 396         } msr_autoload;
 397         struct {
 398                 int           loaded;
 399                 u16           fs_sel, gs_sel, ldt_sel;
 400 #ifdef CONFIG_X86_64
 401                 u16           ds_sel, es_sel;
 402 #endif
 403                 int           gs_ldt_reload_needed;
 404                 int           fs_reload_needed;
 405         } host_state;
 406         struct {
 407                 int vm86_active;
 408                 ulong save_rflags;
 409                 struct kvm_segment segs[8];
 410         } rmode;
 411         struct {
 412                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 413                 struct kvm_save_segment {
 414                         u16 selector;
 415                         unsigned long base;
 416                         u32 limit;
 417                         u32 ar;
 418                 } seg[8];
 419         } segment_cache;
 420         int vpid;
 421         bool emulation_required;
 422
 423         /* Support for vnmi-less CPUs */
 424         int soft_vnmi_blocked;
 425         ktime_t entry_time;
 426         s64 vnmi_blocked_time;
 427         u32 exit_reason;
 428
 429         bool rdtscp_enabled;
 430
 431         /* Support for a guest hypervisor (nested VMX) */
 432         struct nested_vmx nested;
 433 };
 434
 435 enum segment_cache_field {
 436         SEG_FIELD_SEL = 0,
 437         SEG_FIELD_BASE = 1,
 438         SEG_FIELD_LIMIT = 2,
 439         SEG_FIELD_AR = 3,
 440
 441         SEG_FIELD_NR = 4
 442 };
 443
 444 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 445 {
 446         return container_of(vcpu, struct vcpu_vmx, vcpu);
 447 }
 448
 449 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 450 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 451 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 452                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 453
 454 static const unsigned short vmcs_field_to_offset_table[] = {
 455         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 456         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 457         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 458         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 459         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 460         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 461         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 462         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 463         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 464         FIELD(HOST_ES_SELECTOR, host_es_selector),
 465         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 466         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 467         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 468         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 469         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 470         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 471         FIELD64(IO_BITMAP_A, io_bitmap_a),
 472         FIELD64(IO_BITMAP_B, io_bitmap_b),
 473         FIELD64(MSR_BITMAP, msr_bitmap),
 474         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 475         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 476         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 477         FIELD64(TSC_OFFSET, tsc_offset),
 478         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 479         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 480         FIELD64(EPT_POINTER, ept_pointer),
 481         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 482         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 483         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 484         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 485         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 486         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 487         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 488         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 489         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 490         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 491         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 492         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 493         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 494         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 495         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 496         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 497         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 498         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 499         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 500         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 501         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 502         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 503         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 504         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 505         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 506         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 507         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 508         FIELD(TPR_THRESHOLD, tpr_threshold),
 509         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 510         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 511         FIELD(VM_EXIT_REASON, vm_exit_reason),
 512         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 513         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 514         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 515         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 516         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 517         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 518         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 519         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 520         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 521         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 522         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 523         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 524         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 525         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 526         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 527         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 528         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 529         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 530         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 531         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 532         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 533         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 534         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 535         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 536         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 537         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 538         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 539         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 540         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 541         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 542         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 543         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 544         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 545         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 546         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 547         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 548         FIELD(EXIT_QUALIFICATION, exit_qualification),
 549         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 550         FIELD(GUEST_CR0, guest_cr0),
 551         FIELD(GUEST_CR3, guest_cr3),
 552         FIELD(GUEST_CR4, guest_cr4),
 553         FIELD(GUEST_ES_BASE, guest_es_base),
 554         FIELD(GUEST_CS_BASE, guest_cs_base),
 555         FIELD(GUEST_SS_BASE, guest_ss_base),
 556         FIELD(GUEST_DS_BASE, guest_ds_base),
 557         FIELD(GUEST_FS_BASE, guest_fs_base),
 558         FIELD(GUEST_GS_BASE, guest_gs_base),
 559         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 560         FIELD(GUEST_TR_BASE, guest_tr_base),
 561         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 562         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 563         FIELD(GUEST_DR7, guest_dr7),
 564         FIELD(GUEST_RSP, guest_rsp),
 565         FIELD(GUEST_RIP, guest_rip),
 566         FIELD(GUEST_RFLAGS, guest_rflags),
 567         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 568         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 569         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 570         FIELD(HOST_CR0, host_cr0),
 571         FIELD(HOST_CR3, host_cr3),
 572         FIELD(HOST_CR4, host_cr4),
 573         FIELD(HOST_FS_BASE, host_fs_base),
 574         FIELD(HOST_GS_BASE, host_gs_base),
 575         FIELD(HOST_TR_BASE, host_tr_base),
 576         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 577         FIELD(HOST_IDTR_BASE, host_idtr_base),
 578         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 579         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 580         FIELD(HOST_RSP, host_rsp),
 581         FIELD(HOST_RIP, host_rip),
 582 };
 583 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 584
 585 static inline short vmcs_field_to_offset(unsigned long field)
 586 {
 587         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 588                 return -1;
 589         return vmcs_field_to_offset_table[field];
 590 }
 591
 592 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 593 {
 594         return to_vmx(vcpu)->nested.current_vmcs12;
 595 }
 596
 597 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 598 {
 599         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 600         if (is_error_page(page))
 601                 return NULL;
 602
 603         return page;
 604 }
 605
 606 static void nested_release_page(struct page *page)
 607 {
 608         kvm_release_page_dirty(page);
 609 }
 610
 611 static void nested_release_page_clean(struct page *page)
 612 {
 613         kvm_release_page_clean(page);
 614 }
 615
 616 static u64 construct_eptp(unsigned long root_hpa);
 617 static void kvm_cpu_vmxon(u64 addr);
 618 static void kvm_cpu_vmxoff(void);
 619 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 620 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 621 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 622                             struct kvm_segment *var, int seg);
 623 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 624                             struct kvm_segment *var, int seg);
 625 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 626 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 627
 628 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 629 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 630 /*
 631  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 632  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 633  */
 634 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 635 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 636
 637 static unsigned long *vmx_io_bitmap_a;
 638 static unsigned long *vmx_io_bitmap_b;
 639 static unsigned long *vmx_msr_bitmap_legacy;
 640 static unsigned long *vmx_msr_bitmap_longmode;
 641 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 642 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 643
 644 static bool cpu_has_load_ia32_efer;
 645 static bool cpu_has_load_perf_global_ctrl;
 646
 647 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 648 static DEFINE_SPINLOCK(vmx_vpid_lock);
 649
 650 static struct vmcs_config {
 651         int size;
 652         int order;
 653         u32 revision_id;
 654         u32 pin_based_exec_ctrl;
 655         u32 cpu_based_exec_ctrl;
 656         u32 cpu_based_2nd_exec_ctrl;
 657         u32 vmexit_ctrl;
 658         u32 vmentry_ctrl;
 659 } vmcs_config;
 660
 661 static struct vmx_capability {
 662         u32 ept;
 663         u32 vpid;
 664 } vmx_capability;
 665
 666 #define VMX_SEGMENT_FIELD(seg)                                  \
 667         [VCPU_SREG_##seg] = {                                   \
 668                 .selector = GUEST_##seg##_SELECTOR,             \
 669                 .base = GUEST_##seg##_BASE,                     \
 670                 .limit = GUEST_##seg##_LIMIT,                   \
 671                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 672         }
 673
 674 static const struct kvm_vmx_segment_field {
 675         unsigned selector;
 676         unsigned base;
 677         unsigned limit;
 678         unsigned ar_bytes;
 679 } kvm_vmx_segment_fields[] = {
 680         VMX_SEGMENT_FIELD(CS),
 681         VMX_SEGMENT_FIELD(DS),
 682         VMX_SEGMENT_FIELD(ES),
 683         VMX_SEGMENT_FIELD(FS),
 684         VMX_SEGMENT_FIELD(GS),
 685         VMX_SEGMENT_FIELD(SS),
 686         VMX_SEGMENT_FIELD(TR),
 687         VMX_SEGMENT_FIELD(LDTR),
 688 };
 689
 690 static u64 host_efer;
 691
 692 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 693
 694 /*
 695  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 696  * away by decrementing the array size.
 697  */
 698 static const u32 vmx_msr_index[] = {
 699 #ifdef CONFIG_X86_64
 700         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 701 #endif
 702         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 703 };
 704 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 705
 706 static inline bool is_page_fault(u32 intr_info)
 707 {
 708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 709                              INTR_INFO_VALID_MASK)) ==
 710                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 711 }
 712
 713 static inline bool is_no_device(u32 intr_info)
 714 {
 715         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 716                              INTR_INFO_VALID_MASK)) ==
 717                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 718 }
 719
 720 static inline bool is_invalid_opcode(u32 intr_info)
 721 {
 722         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 723                              INTR_INFO_VALID_MASK)) ==
 724                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 725 }
 726
 727 static inline bool is_external_interrupt(u32 intr_info)
 728 {
 729         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 730                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 731 }
 732
 733 static inline bool is_machine_check(u32 intr_info)
 734 {
 735         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 736                              INTR_INFO_VALID_MASK)) ==
 737                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 738 }
 739
 740 static inline bool cpu_has_vmx_msr_bitmap(void)
 741 {
 742         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 743 }
 744
 745 static inline bool cpu_has_vmx_tpr_shadow(void)
 746 {
 747         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 748 }
 749
 750 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 751 {
 752         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 753 }
 754
 755 static inline bool cpu_has_secondary_exec_ctrls(void)
 756 {
 757         return vmcs_config.cpu_based_exec_ctrl &
 758                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 759 }
 760
 761 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 762 {
 763         return vmcs_config.cpu_based_2nd_exec_ctrl &
 764                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 765 }
 766
 767 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 768 {
 769         return vmcs_config.cpu_based_2nd_exec_ctrl &
 770                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 771 }
 772
 773 static inline bool cpu_has_vmx_apic_register_virt(void)
 774 {
 775         return vmcs_config.cpu_based_2nd_exec_ctrl &
 776                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 777 }
 778
 779 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 780 {
 781         return vmcs_config.cpu_based_2nd_exec_ctrl &
 782                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 783 }
 784
 785 static inline bool cpu_has_vmx_flexpriority(void)
 786 {
 787         return cpu_has_vmx_tpr_shadow() &&
 788                 cpu_has_vmx_virtualize_apic_accesses();
 789 }
 790
 791 static inline bool cpu_has_vmx_ept_execute_only(void)
 792 {
 793         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 794 }
 795
 796 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 797 {
 798         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 799 }
 800
 801 static inline bool cpu_has_vmx_eptp_writeback(void)
 802 {
 803         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 804 }
 805
 806 static inline bool cpu_has_vmx_ept_2m_page(void)
 807 {
 808         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 809 }
 810
 811 static inline bool cpu_has_vmx_ept_1g_page(void)
 812 {
 813         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 814 }
 815
 816 static inline bool cpu_has_vmx_ept_4levels(void)
 817 {
 818         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 819 }
 820
 821 static inline bool cpu_has_vmx_ept_ad_bits(void)
 822 {
 823         return vmx_capability.ept & VMX_EPT_AD_BIT;
 824 }
 825
 826 static inline bool cpu_has_vmx_invept_context(void)
 827 {
 828         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 829 }
 830
 831 static inline bool cpu_has_vmx_invept_global(void)
 832 {
 833         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 834 }
 835
 836 static inline bool cpu_has_vmx_invvpid_single(void)
 837 {
 838         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 839 }
 840
 841 static inline bool cpu_has_vmx_invvpid_global(void)
 842 {
 843         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 844 }
 845
 846 static inline bool cpu_has_vmx_ept(void)
 847 {
 848         return vmcs_config.cpu_based_2nd_exec_ctrl &
 849                 SECONDARY_EXEC_ENABLE_EPT;
 850 }
 851
 852 static inline bool cpu_has_vmx_unrestricted_guest(void)
 853 {
 854         return vmcs_config.cpu_based_2nd_exec_ctrl &
 855                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 856 }
 857
 858 static inline bool cpu_has_vmx_ple(void)
 859 {
 860         return vmcs_config.cpu_based_2nd_exec_ctrl &
 861                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 862 }
 863
 864 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 865 {
 866         return flexpriority_enabled && irqchip_in_kernel(kvm);
 867 }
 868
 869 static inline bool cpu_has_vmx_vpid(void)
 870 {
 871         return vmcs_config.cpu_based_2nd_exec_ctrl &
 872                 SECONDARY_EXEC_ENABLE_VPID;
 873 }
 874
 875 static inline bool cpu_has_vmx_rdtscp(void)
 876 {
 877         return vmcs_config.cpu_based_2nd_exec_ctrl &
 878                 SECONDARY_EXEC_RDTSCP;
 879 }
 880
 881 static inline bool cpu_has_vmx_invpcid(void)
 882 {
 883         return vmcs_config.cpu_based_2nd_exec_ctrl &
 884                 SECONDARY_EXEC_ENABLE_INVPCID;
 885 }
 886
 887 static inline bool cpu_has_virtual_nmis(void)
 888 {
 889         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 890 }
 891
 892 static inline bool cpu_has_vmx_wbinvd_exit(void)
 893 {
 894         return vmcs_config.cpu_based_2nd_exec_ctrl &
 895                 SECONDARY_EXEC_WBINVD_EXITING;
 896 }
 897
 898 static inline bool report_flexpriority(void)
 899 {
 900         return flexpriority_enabled;
 901 }
 902
 903 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 904 {
 905         return vmcs12->cpu_based_vm_exec_control & bit;
 906 }
 907
 908 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 909 {
 910         return (vmcs12->cpu_based_vm_exec_control &
 911                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 912                 (vmcs12->secondary_vm_exec_control & bit);
 913 }
 914
 915 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 916         struct kvm_vcpu *vcpu)
 917 {
 918         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 919 }
 920
 921 static inline bool is_exception(u32 intr_info)
 922 {
 923         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 924                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 925 }
 926
 927 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 928 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 929                         struct vmcs12 *vmcs12,
 930                         u32 reason, unsigned long qualification);
 931
 932 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 933 {
 934         int i;
 935
 936         for (i = 0; i < vmx->nmsrs; ++i)
 937                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 938                         return i;
 939         return -1;
 940 }
 941
 942 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 943 {
 944     struct {
 945         u64 vpid : 16;
 946         u64 rsvd : 48;
 947         u64 gva;
 948     } operand = { vpid, 0, gva };
 949
 950     asm volatile (__ex(ASM_VMX_INVVPID)
 951                   /* CF==1 or ZF==1 --> rc = -1 */
 952                   "; ja 1f ; ud2 ; 1:"
 953                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 954 }
 955
 956 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 957 {
 958         struct {
 959                 u64 eptp, gpa;
 960         } operand = {eptp, gpa};
 961
 962         asm volatile (__ex(ASM_VMX_INVEPT)
 963                         /* CF==1 or ZF==1 --> rc = -1 */
 964                         "; ja 1f ; ud2 ; 1:\n"
 965                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 966 }
 967
 968 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 969 {
 970         int i;
 971
 972         i = __find_msr_index(vmx, msr);
 973         if (i >= 0)
 974                 return &vmx->guest_msrs[i];
 975         return NULL;
 976 }
 977
 978 static void vmcs_clear(struct vmcs *vmcs)
 979 {
 980         u64 phys_addr = __pa(vmcs);
 981         u8 error;
 982
 983         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 984                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 985                       : "cc", "memory");
 986         if (error)
 987                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 988                        vmcs, phys_addr);
 989 }
 990
 991 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 992 {
 993         vmcs_clear(loaded_vmcs->vmcs);
 994         loaded_vmcs->cpu = -1;
 995         loaded_vmcs->launched = 0;
 996 }
 997
 998 static void vmcs_load(struct vmcs *vmcs)
 999 {
1000         u64 phys_addr = __pa(vmcs);
1001         u8 error;
1002
1003         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1004                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1005                         : "cc", "memory");
1006         if (error)
1007                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1008                        vmcs, phys_addr);
1009 }
1010
1011 #ifdef CONFIG_KEXEC
1012 /*
1013  * This bitmap is used to indicate whether the vmclear
1014  * operation is enabled on all cpus. All disabled by
1015  * default.
1016  */
1017 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1018
1019 static inline void crash_enable_local_vmclear(int cpu)
1020 {
1021         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1022 }
1023
1024 static inline void crash_disable_local_vmclear(int cpu)
1025 {
1026         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1027 }
1028
1029 static inline int crash_local_vmclear_enabled(int cpu)
1030 {
1031         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1032 }
1033
1034 static void crash_vmclear_local_loaded_vmcss(void)
1035 {
1036         int cpu = raw_smp_processor_id();
1037         struct loaded_vmcs *v;
1038
1039         if (!crash_local_vmclear_enabled(cpu))
1040                 return;
1041
1042         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1043                             loaded_vmcss_on_cpu_link)
1044                 vmcs_clear(v->vmcs);
1045 }
1046 #else
1047 static inline void crash_enable_local_vmclear(int cpu) { }
1048 static inline void crash_disable_local_vmclear(int cpu) { }
1049 #endif /* CONFIG_KEXEC */
1050
1051 static void __loaded_vmcs_clear(void *arg)
1052 {
1053         struct loaded_vmcs *loaded_vmcs = arg;
1054         int cpu = raw_smp_processor_id();
1055
1056         if (loaded_vmcs->cpu != cpu)
1057                 return; /* vcpu migration can race with cpu offline */
1058         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1059                 per_cpu(current_vmcs, cpu) = NULL;
1060         crash_disable_local_vmclear(cpu);
1061         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1062
1063         /*
1064          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1065          * is before setting loaded_vmcs->vcpu to -1 which is done in
1066          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1067          * then adds the vmcs into percpu list before it is deleted.
1068          */
1069         smp_wmb();
1070
1071         loaded_vmcs_init(loaded_vmcs);
1072         crash_enable_local_vmclear(cpu);
1073 }
1074
1075 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1076 {
1077         int cpu = loaded_vmcs->cpu;
1078
1079         if (cpu != -1)
1080                 smp_call_function_single(cpu,
1081                          __loaded_vmcs_clear, loaded_vmcs, 1);
1082 }
1083
1084 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1085 {
1086         if (vmx->vpid == 0)
1087                 return;
1088
1089         if (cpu_has_vmx_invvpid_single())
1090                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1091 }
1092
1093 static inline void vpid_sync_vcpu_global(void)
1094 {
1095         if (cpu_has_vmx_invvpid_global())
1096                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1097 }
1098
1099 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1100 {
1101         if (cpu_has_vmx_invvpid_single())
1102                 vpid_sync_vcpu_single(vmx);
1103         else
1104                 vpid_sync_vcpu_global();
1105 }
1106
1107 static inline void ept_sync_global(void)
1108 {
1109         if (cpu_has_vmx_invept_global())
1110                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1111 }
1112
1113 static inline void ept_sync_context(u64 eptp)
1114 {
1115         if (enable_ept) {
1116                 if (cpu_has_vmx_invept_context())
1117                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1118                 else
1119                         ept_sync_global();
1120         }
1121 }
1122
1123 static __always_inline unsigned long vmcs_readl(unsigned long field)
1124 {
1125         unsigned long value;
1126
1127         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1128                       : "=a"(value) : "d"(field) : "cc");
1129         return value;
1130 }
1131
1132 static __always_inline u16 vmcs_read16(unsigned long field)
1133 {
1134         return vmcs_readl(field);
1135 }
1136
1137 static __always_inline u32 vmcs_read32(unsigned long field)
1138 {
1139         return vmcs_readl(field);
1140 }
1141
1142 static __always_inline u64 vmcs_read64(unsigned long field)
1143 {
1144 #ifdef CONFIG_X86_64
1145         return vmcs_readl(field);
1146 #else
1147         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1148 #endif
1149 }
1150
1151 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1152 {
1153         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1154                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1155         dump_stack();
1156 }
1157
1158 static void vmcs_writel(unsigned long field, unsigned long value)
1159 {
1160         u8 error;
1161
1162         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1163                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1164         if (unlikely(error))
1165                 vmwrite_error(field, value);
1166 }
1167
1168 static void vmcs_write16(unsigned long field, u16 value)
1169 {
1170         vmcs_writel(field, value);
1171 }
1172
1173 static void vmcs_write32(unsigned long field, u32 value)
1174 {
1175         vmcs_writel(field, value);
1176 }
1177
1178 static void vmcs_write64(unsigned long field, u64 value)
1179 {
1180         vmcs_writel(field, value);
1181 #ifndef CONFIG_X86_64
1182         asm volatile ("");
1183         vmcs_writel(field+1, value >> 32);
1184 #endif
1185 }
1186
1187 static void vmcs_clear_bits(unsigned long field, u32 mask)
1188 {
1189         vmcs_writel(field, vmcs_readl(field) & ~mask);
1190 }
1191
1192 static void vmcs_set_bits(unsigned long field, u32 mask)
1193 {
1194         vmcs_writel(field, vmcs_readl(field) | mask);
1195 }
1196
1197 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1198 {
1199         vmx->segment_cache.bitmask = 0;
1200 }
1201
1202 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1203                                        unsigned field)
1204 {
1205         bool ret;
1206         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1207
1208         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1209                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1210                 vmx->segment_cache.bitmask = 0;
1211         }
1212         ret = vmx->segment_cache.bitmask & mask;
1213         vmx->segment_cache.bitmask |= mask;
1214         return ret;
1215 }
1216
1217 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1218 {
1219         u16 *p = &vmx->segment_cache.seg[seg].selector;
1220
1221         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1222                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1223         return *p;
1224 }
1225
1226 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1227 {
1228         ulong *p = &vmx->segment_cache.seg[seg].base;
1229
1230         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1231                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1232         return *p;
1233 }
1234
1235 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1236 {
1237         u32 *p = &vmx->segment_cache.seg[seg].limit;
1238
1239         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1240                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1241         return *p;
1242 }
1243
1244 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1245 {
1246         u32 *p = &vmx->segment_cache.seg[seg].ar;
1247
1248         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1249                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1250         return *p;
1251 }
1252
1253 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1254 {
1255         u32 eb;
1256
1257         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1258              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1259         if ((vcpu->guest_debug &
1260              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1261             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1262                 eb |= 1u << BP_VECTOR;
1263         if (to_vmx(vcpu)->rmode.vm86_active)
1264                 eb = ~0;
1265         if (enable_ept)
1266                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1267         if (vcpu->fpu_active)
1268                 eb &= ~(1u << NM_VECTOR);
1269
1270         /* When we are running a nested L2 guest and L1 specified for it a
1271          * certain exception bitmap, we must trap the same exceptions and pass
1272          * them to L1. When running L2, we will only handle the exceptions
1273          * specified above if L1 did not want them.
1274          */
1275         if (is_guest_mode(vcpu))
1276                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1277
1278         vmcs_write32(EXCEPTION_BITMAP, eb);
1279 }
1280
1281 static void clear_atomic_switch_msr_special(unsigned long entry,
1282                 unsigned long exit)
1283 {
1284         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1285         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1286 }
1287
1288 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1289 {
1290         unsigned i;
1291         struct msr_autoload *m = &vmx->msr_autoload;
1292
1293         switch (msr) {
1294         case MSR_EFER:
1295                 if (cpu_has_load_ia32_efer) {
1296                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1297                                         VM_EXIT_LOAD_IA32_EFER);
1298                         return;
1299                 }
1300                 break;
1301         case MSR_CORE_PERF_GLOBAL_CTRL:
1302                 if (cpu_has_load_perf_global_ctrl) {
1303                         clear_atomic_switch_msr_special(
1304                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1305                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1306                         return;
1307                 }
1308                 break;
1309         }
1310
1311         for (i = 0; i < m->nr; ++i)
1312                 if (m->guest[i].index == msr)
1313                         break;
1314
1315         if (i == m->nr)
1316                 return;
1317         --m->nr;
1318         m->guest[i] = m->guest[m->nr];
1319         m->host[i] = m->host[m->nr];
1320         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1321         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1322 }
1323
1324 static void add_atomic_switch_msr_special(unsigned long entry,
1325                 unsigned long exit, unsigned long guest_val_vmcs,
1326                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1327 {
1328         vmcs_write64(guest_val_vmcs, guest_val);
1329         vmcs_write64(host_val_vmcs, host_val);
1330         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1331         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1332 }
1333
1334 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1335                                   u64 guest_val, u64 host_val)
1336 {
1337         unsigned i;
1338         struct msr_autoload *m = &vmx->msr_autoload;
1339
1340         switch (msr) {
1341         case MSR_EFER:
1342                 if (cpu_has_load_ia32_efer) {
1343                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1344                                         VM_EXIT_LOAD_IA32_EFER,
1345                                         GUEST_IA32_EFER,
1346                                         HOST_IA32_EFER,
1347                                         guest_val, host_val);
1348                         return;
1349                 }
1350                 break;
1351         case MSR_CORE_PERF_GLOBAL_CTRL:
1352                 if (cpu_has_load_perf_global_ctrl) {
1353                         add_atomic_switch_msr_special(
1354                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1355                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1356                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1357                                         HOST_IA32_PERF_GLOBAL_CTRL,
1358                                         guest_val, host_val);
1359                         return;
1360                 }
1361                 break;
1362         }
1363
1364         for (i = 0; i < m->nr; ++i)
1365                 if (m->guest[i].index == msr)
1366                         break;
1367
1368         if (i == NR_AUTOLOAD_MSRS) {
1369                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1370                                 "Can't add msr %x\n", msr);
1371                 return;
1372         } else if (i == m->nr) {
1373                 ++m->nr;
1374                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1375                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1376         }
1377
1378         m->guest[i].index = msr;
1379         m->guest[i].value = guest_val;
1380         m->host[i].index = msr;
1381         m->host[i].value = host_val;
1382 }
1383
1384 static void reload_tss(void)
1385 {
1386         /*
1387          * VT restores TR but not its size.  Useless.
1388          */
1389         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1390         struct desc_struct *descs;
1391
1392         descs = (void *)gdt->address;
1393         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1394         load_TR_desc();
1395 }
1396
1397 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1398 {
1399         u64 guest_efer;
1400         u64 ignore_bits;
1401
1402         guest_efer = vmx->vcpu.arch.efer;
1403
1404         /*
1405          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1406          * outside long mode
1407          */
1408         ignore_bits = EFER_NX | EFER_SCE;
1409 #ifdef CONFIG_X86_64
1410         ignore_bits |= EFER_LMA | EFER_LME;
1411         /* SCE is meaningful only in long mode on Intel */
1412         if (guest_efer & EFER_LMA)
1413                 ignore_bits &= ~(u64)EFER_SCE;
1414 #endif
1415         guest_efer &= ~ignore_bits;
1416         guest_efer |= host_efer & ignore_bits;
1417         vmx->guest_msrs[efer_offset].data = guest_efer;
1418         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1419
1420         clear_atomic_switch_msr(vmx, MSR_EFER);
1421         /* On ept, can't emulate nx, and must switch nx atomically */
1422         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1423                 guest_efer = vmx->vcpu.arch.efer;
1424                 if (!(guest_efer & EFER_LMA))
1425                         guest_efer &= ~EFER_LME;
1426                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1427                 return false;
1428         }
1429
1430         return true;
1431 }
1432
1433 static unsigned long segment_base(u16 selector)
1434 {
1435         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1436         struct desc_struct *d;
1437         unsigned long table_base;
1438         unsigned long v;
1439
1440         if (!(selector & ~3))
1441                 return 0;
1442
1443         table_base = gdt->address;
1444
1445         if (selector & 4) {           /* from ldt */
1446                 u16 ldt_selector = kvm_read_ldt();
1447
1448                 if (!(ldt_selector & ~3))
1449                         return 0;
1450
1451                 table_base = segment_base(ldt_selector);
1452         }
1453         d = (struct desc_struct *)(table_base + (selector & ~7));
1454         v = get_desc_base(d);
1455 #ifdef CONFIG_X86_64
1456        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1457                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1458 #endif
1459         return v;
1460 }
1461
1462 static inline unsigned long kvm_read_tr_base(void)
1463 {
1464         u16 tr;
1465         asm("str %0" : "=g"(tr));
1466         return segment_base(tr);
1467 }
1468
1469 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1470 {
1471         struct vcpu_vmx *vmx = to_vmx(vcpu);
1472         int i;
1473
1474         if (vmx->host_state.loaded)
1475                 return;
1476
1477         vmx->host_state.loaded = 1;
1478         /*
1479          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1480          * allow segment selectors with cpl > 0 or ti == 1.
1481          */
1482         vmx->host_state.ldt_sel = kvm_read_ldt();
1483         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1484         savesegment(fs, vmx->host_state.fs_sel);
1485         if (!(vmx->host_state.fs_sel & 7)) {
1486                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1487                 vmx->host_state.fs_reload_needed = 0;
1488         } else {
1489                 vmcs_write16(HOST_FS_SELECTOR, 0);
1490                 vmx->host_state.fs_reload_needed = 1;
1491         }
1492         savesegment(gs, vmx->host_state.gs_sel);
1493         if (!(vmx->host_state.gs_sel & 7))
1494                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1495         else {
1496                 vmcs_write16(HOST_GS_SELECTOR, 0);
1497                 vmx->host_state.gs_ldt_reload_needed = 1;
1498         }
1499
1500 #ifdef CONFIG_X86_64
1501         savesegment(ds, vmx->host_state.ds_sel);
1502         savesegment(es, vmx->host_state.es_sel);
1503 #endif
1504
1505 #ifdef CONFIG_X86_64
1506         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1507         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1508 #else
1509         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1510         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1511 #endif
1512
1513 #ifdef CONFIG_X86_64
1514         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1515         if (is_long_mode(&vmx->vcpu))
1516                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1517 #endif
1518         for (i = 0; i < vmx->save_nmsrs; ++i)
1519                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1520                                    vmx->guest_msrs[i].data,
1521                                    vmx->guest_msrs[i].mask);
1522 }
1523
1524 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1525 {
1526         if (!vmx->host_state.loaded)
1527                 return;
1528
1529         ++vmx->vcpu.stat.host_state_reload;
1530         vmx->host_state.loaded = 0;
1531 #ifdef CONFIG_X86_64
1532         if (is_long_mode(&vmx->vcpu))
1533                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1534 #endif
1535         if (vmx->host_state.gs_ldt_reload_needed) {
1536                 kvm_load_ldt(vmx->host_state.ldt_sel);
1537 #ifdef CONFIG_X86_64
1538                 load_gs_index(vmx->host_state.gs_sel);
1539 #else
1540                 loadsegment(gs, vmx->host_state.gs_sel);
1541 #endif
1542         }
1543         if (vmx->host_state.fs_reload_needed)
1544                 loadsegment(fs, vmx->host_state.fs_sel);
1545 #ifdef CONFIG_X86_64
1546         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1547                 loadsegment(ds, vmx->host_state.ds_sel);
1548                 loadsegment(es, vmx->host_state.es_sel);
1549         }
1550 #endif
1551         reload_tss();
1552 #ifdef CONFIG_X86_64
1553         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1554 #endif
1555         /*
1556          * If the FPU is not active (through the host task or
1557          * the guest vcpu), then restore the cr0.TS bit.
1558          */
1559         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1560                 stts();
1561         load_gdt(&__get_cpu_var(host_gdt));
1562 }
1563
1564 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1565 {
1566         preempt_disable();
1567         __vmx_load_host_state(vmx);
1568         preempt_enable();
1569 }
1570
1571 /*
1572  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1573  * vcpu mutex is already taken.
1574  */
1575 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1576 {
1577         struct vcpu_vmx *vmx = to_vmx(vcpu);
1578         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1579
1580         if (!vmm_exclusive)
1581                 kvm_cpu_vmxon(phys_addr);
1582         else if (vmx->loaded_vmcs->cpu != cpu)
1583                 loaded_vmcs_clear(vmx->loaded_vmcs);
1584
1585         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1586                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1587                 vmcs_load(vmx->loaded_vmcs->vmcs);
1588         }
1589
1590         if (vmx->loaded_vmcs->cpu != cpu) {
1591                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1592                 unsigned long sysenter_esp;
1593
1594                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1595                 local_irq_disable();
1596                 crash_disable_local_vmclear(cpu);
1597
1598                 /*
1599                  * Read loaded_vmcs->cpu should be before fetching
1600                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1601                  * See the comments in __loaded_vmcs_clear().
1602                  */
1603                 smp_rmb();
1604
1605                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1606                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1607                 crash_enable_local_vmclear(cpu);
1608                 local_irq_enable();
1609
1610                 /*
1611                  * Linux uses per-cpu TSS and GDT, so set these when switching
1612                  * processors.
1613                  */
1614                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1615                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1616
1617                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1618                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1619                 vmx->loaded_vmcs->cpu = cpu;
1620         }
1621 }
1622
1623 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1624 {
1625         __vmx_load_host_state(to_vmx(vcpu));
1626         if (!vmm_exclusive) {
1627                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1628                 vcpu->cpu = -1;
1629                 kvm_cpu_vmxoff();
1630         }
1631 }
1632
1633 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1634 {
1635         ulong cr0;
1636
1637         if (vcpu->fpu_active)
1638                 return;
1639         vcpu->fpu_active = 1;
1640         cr0 = vmcs_readl(GUEST_CR0);
1641         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1642         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1643         vmcs_writel(GUEST_CR0, cr0);
1644         update_exception_bitmap(vcpu);
1645         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1646         if (is_guest_mode(vcpu))
1647                 vcpu->arch.cr0_guest_owned_bits &=
1648                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1649         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1650 }
1651
1652 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1653
1654 /*
1655  * Return the cr0 value that a nested guest would read. This is a combination
1656  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1657  * its hypervisor (cr0_read_shadow).
1658  */
1659 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1660 {
1661         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1662                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1663 }
1664 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1665 {
1666         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1667                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1668 }
1669
1670 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1671 {
1672         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1673          * set this *before* calling this function.
1674          */
1675         vmx_decache_cr0_guest_bits(vcpu);
1676         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1677         update_exception_bitmap(vcpu);
1678         vcpu->arch.cr0_guest_owned_bits = 0;
1679         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1680         if (is_guest_mode(vcpu)) {
1681                 /*
1682                  * L1's specified read shadow might not contain the TS bit,
1683                  * so now that we turned on shadowing of this bit, we need to
1684                  * set this bit of the shadow. Like in nested_vmx_run we need
1685                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1686                  * up-to-date here because we just decached cr0.TS (and we'll
1687                  * only update vmcs12->guest_cr0 on nested exit).
1688                  */
1689                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1690                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1691                         (vcpu->arch.cr0 & X86_CR0_TS);
1692                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1693         } else
1694                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1695 }
1696
1697 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1698 {
1699         unsigned long rflags, save_rflags;
1700
1701         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1702                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1703                 rflags = vmcs_readl(GUEST_RFLAGS);
1704                 if (to_vmx(vcpu)->rmode.vm86_active) {
1705                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1706                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1707                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1708                 }
1709                 to_vmx(vcpu)->rflags = rflags;
1710         }
1711         return to_vmx(vcpu)->rflags;
1712 }
1713
1714 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1715 {
1716         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1717         to_vmx(vcpu)->rflags = rflags;
1718         if (to_vmx(vcpu)->rmode.vm86_active) {
1719                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1720                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1721         }
1722         vmcs_writel(GUEST_RFLAGS, rflags);
1723 }
1724
1725 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1726 {
1727         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1728         int ret = 0;
1729
1730         if (interruptibility & GUEST_INTR_STATE_STI)
1731                 ret |= KVM_X86_SHADOW_INT_STI;
1732         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1733                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1734
1735         return ret & mask;
1736 }
1737
1738 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1739 {
1740         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1741         u32 interruptibility = interruptibility_old;
1742
1743         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1744
1745         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1746                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1747         else if (mask & KVM_X86_SHADOW_INT_STI)
1748                 interruptibility |= GUEST_INTR_STATE_STI;
1749
1750         if ((interruptibility != interruptibility_old))
1751                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1752 }
1753
1754 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1755 {
1756         unsigned long rip;
1757
1758         rip = kvm_rip_read(vcpu);
1759         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1760         kvm_rip_write(vcpu, rip);
1761
1762         /* skipping an emulated instruction also counts */
1763         vmx_set_interrupt_shadow(vcpu, 0);
1764 }
1765
1766 /*
1767  * KVM wants to inject page-faults which it got to the guest. This function
1768  * checks whether in a nested guest, we need to inject them to L1 or L2.
1769  * This function assumes it is called with the exit reason in vmcs02 being
1770  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1771  * is running).
1772  */
1773 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1774 {
1775         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1776
1777         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1778         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1779                 return 0;
1780
1781         nested_vmx_vmexit(vcpu);
1782         return 1;
1783 }
1784
1785 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1786                                 bool has_error_code, u32 error_code,
1787                                 bool reinject)
1788 {
1789         struct vcpu_vmx *vmx = to_vmx(vcpu);
1790         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1791
1792         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1793                 nested_pf_handled(vcpu))
1794                 return;
1795
1796         if (has_error_code) {
1797                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1798                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1799         }
1800
1801         if (vmx->rmode.vm86_active) {
1802                 int inc_eip = 0;
1803                 if (kvm_exception_is_soft(nr))
1804                         inc_eip = vcpu->arch.event_exit_inst_len;
1805                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1806                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1807                 return;
1808         }
1809
1810         if (kvm_exception_is_soft(nr)) {
1811                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1812                              vmx->vcpu.arch.event_exit_inst_len);
1813                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1814         } else
1815                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1816
1817         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1818 }
1819
1820 static bool vmx_rdtscp_supported(void)
1821 {
1822         return cpu_has_vmx_rdtscp();
1823 }
1824
1825 static bool vmx_invpcid_supported(void)
1826 {
1827         return cpu_has_vmx_invpcid() && enable_ept;
1828 }
1829
1830 /*
1831  * Swap MSR entry in host/guest MSR entry array.
1832  */
1833 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1834 {
1835         struct shared_msr_entry tmp;
1836
1837         tmp = vmx->guest_msrs[to];
1838         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1839         vmx->guest_msrs[from] = tmp;
1840 }
1841
1842 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1843 {
1844         unsigned long *msr_bitmap;
1845
1846         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1847                 if (is_long_mode(vcpu))
1848                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1849                 else
1850                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1851         } else {
1852                 if (is_long_mode(vcpu))
1853                         msr_bitmap = vmx_msr_bitmap_longmode;
1854                 else
1855                         msr_bitmap = vmx_msr_bitmap_legacy;
1856         }
1857
1858         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1859 }
1860
1861 /*
1862  * Set up the vmcs to automatically save and restore system
1863  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1864  * mode, as fiddling with msrs is very expensive.
1865  */
1866 static void setup_msrs(struct vcpu_vmx *vmx)
1867 {
1868         int save_nmsrs, index;
1869
1870         save_nmsrs = 0;
1871 #ifdef CONFIG_X86_64
1872         if (is_long_mode(&vmx->vcpu)) {
1873                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1874                 if (index >= 0)
1875                         move_msr_up(vmx, index, save_nmsrs++);
1876                 index = __find_msr_index(vmx, MSR_LSTAR);
1877                 if (index >= 0)
1878                         move_msr_up(vmx, index, save_nmsrs++);
1879                 index = __find_msr_index(vmx, MSR_CSTAR);
1880                 if (index >= 0)
1881                         move_msr_up(vmx, index, save_nmsrs++);
1882                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1883                 if (index >= 0 && vmx->rdtscp_enabled)
1884                         move_msr_up(vmx, index, save_nmsrs++);
1885                 /*
1886                  * MSR_STAR is only needed on long mode guests, and only
1887                  * if efer.sce is enabled.
1888                  */
1889                 index = __find_msr_index(vmx, MSR_STAR);
1890                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1891                         move_msr_up(vmx, index, save_nmsrs++);
1892         }
1893 #endif
1894         index = __find_msr_index(vmx, MSR_EFER);
1895         if (index >= 0 && update_transition_efer(vmx, index))
1896                 move_msr_up(vmx, index, save_nmsrs++);
1897
1898         vmx->save_nmsrs = save_nmsrs;
1899
1900         if (cpu_has_vmx_msr_bitmap())
1901                 vmx_set_msr_bitmap(&vmx->vcpu);
1902 }
1903
1904 /*
1905  * reads and returns guest's timestamp counter "register"
1906  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1907  */
1908 static u64 guest_read_tsc(void)
1909 {
1910         u64 host_tsc, tsc_offset;
1911
1912         rdtscll(host_tsc);
1913         tsc_offset = vmcs_read64(TSC_OFFSET);
1914         return host_tsc + tsc_offset;
1915 }
1916
1917 /*
1918  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1919  * counter, even if a nested guest (L2) is currently running.
1920  */
1921 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1922 {
1923         u64 tsc_offset;
1924
1925         tsc_offset = is_guest_mode(vcpu) ?
1926                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1927                 vmcs_read64(TSC_OFFSET);
1928         return host_tsc + tsc_offset;
1929 }
1930
1931 /*
1932  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1933  * software catchup for faster rates on slower CPUs.
1934  */
1935 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1936 {
1937         if (!scale)
1938                 return;
1939
1940         if (user_tsc_khz > tsc_khz) {
1941                 vcpu->arch.tsc_catchup = 1;
1942                 vcpu->arch.tsc_always_catchup = 1;
1943         } else
1944                 WARN(1, "user requested TSC rate below hardware speed\n");
1945 }
1946
1947 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1948 {
1949         return vmcs_read64(TSC_OFFSET);
1950 }
1951
1952 /*
1953  * writes 'offset' into guest's timestamp counter offset register
1954  */
1955 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1956 {
1957         if (is_guest_mode(vcpu)) {
1958                 /*
1959                  * We're here if L1 chose not to trap WRMSR to TSC. According
1960                  * to the spec, this should set L1's TSC; The offset that L1
1961                  * set for L2 remains unchanged, and still needs to be added
1962                  * to the newly set TSC to get L2's TSC.
1963                  */
1964                 struct vmcs12 *vmcs12;
1965                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1966                 /* recalculate vmcs02.TSC_OFFSET: */
1967                 vmcs12 = get_vmcs12(vcpu);
1968                 vmcs_write64(TSC_OFFSET, offset +
1969                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1970                          vmcs12->tsc_offset : 0));
1971         } else {
1972                 vmcs_write64(TSC_OFFSET, offset);
1973         }
1974 }
1975
1976 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1977 {
1978         u64 offset = vmcs_read64(TSC_OFFSET);
1979         vmcs_write64(TSC_OFFSET, offset + adjustment);
1980         if (is_guest_mode(vcpu)) {
1981                 /* Even when running L2, the adjustment needs to apply to L1 */
1982                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1983         }
1984 }
1985
1986 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1987 {
1988         return target_tsc - native_read_tsc();
1989 }
1990
1991 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1992 {
1993         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1994         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1995 }
1996
1997 /*
1998  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1999  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2000  * all guests if the "nested" module option is off, and can also be disabled
2001  * for a single guest by disabling its VMX cpuid bit.
2002  */
2003 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2004 {
2005         return nested && guest_cpuid_has_vmx(vcpu);
2006 }
2007
2008 /*
2009  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2010  * returned for the various VMX controls MSRs when nested VMX is enabled.
2011  * The same values should also be used to verify that vmcs12 control fields are
2012  * valid during nested entry from L1 to L2.
2013  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2014  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2015  * bit in the high half is on if the corresponding bit in the control field
2016  * may be on. See also vmx_control_verify().
2017  * TODO: allow these variables to be modified (downgraded) by module options
2018  * or other means.
2019  */
2020 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2021 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2022 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2023 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2024 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2025 static __init void nested_vmx_setup_ctls_msrs(void)
2026 {
2027         /*
2028          * Note that as a general rule, the high half of the MSRs (bits in
2029          * the control fields which may be 1) should be initialized by the
2030          * intersection of the underlying hardware's MSR (i.e., features which
2031          * can be supported) and the list of features we want to expose -
2032          * because they are known to be properly supported in our code.
2033          * Also, usually, the low half of the MSRs (bits which must be 1) can
2034          * be set to 0, meaning that L1 may turn off any of these bits. The
2035          * reason is that if one of these bits is necessary, it will appear
2036          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2037          * fields of vmcs01 and vmcs02, will turn these bits off - and
2038          * nested_vmx_exit_handled() will not pass related exits to L1.
2039          * These rules have exceptions below.
2040          */
2041
2042         /* pin-based controls */
2043         /*
2044          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2045          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2046          */
2047         nested_vmx_pinbased_ctls_low = 0x16 ;
2048         nested_vmx_pinbased_ctls_high = 0x16 |
2049                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2050                 PIN_BASED_VIRTUAL_NMIS;
2051
2052         /* exit controls */
2053         nested_vmx_exit_ctls_low = 0;
2054         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2055 #ifdef CONFIG_X86_64
2056         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2057 #else
2058         nested_vmx_exit_ctls_high = 0;
2059 #endif
2060
2061         /* entry controls */
2062         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2063                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2064         nested_vmx_entry_ctls_low = 0;
2065         nested_vmx_entry_ctls_high &=
2066                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2067
2068         /* cpu-based controls */
2069         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2070                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2071         nested_vmx_procbased_ctls_low = 0;
2072         nested_vmx_procbased_ctls_high &=
2073                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2074                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2075                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2076                 CPU_BASED_CR3_STORE_EXITING |
2077 #ifdef CONFIG_X86_64
2078                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2079 #endif
2080                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2081                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2082                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2083                 CPU_BASED_PAUSE_EXITING |
2084                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2085         /*
2086          * We can allow some features even when not supported by the
2087          * hardware. For example, L1 can specify an MSR bitmap - and we
2088          * can use it to avoid exits to L1 - even when L0 runs L2
2089          * without MSR bitmaps.
2090          */
2091         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2092
2093         /* secondary cpu-based controls */
2094         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2095                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2096         nested_vmx_secondary_ctls_low = 0;
2097         nested_vmx_secondary_ctls_high &=
2098                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2099                 SECONDARY_EXEC_WBINVD_EXITING;
2100 }
2101
2102 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2103 {
2104         /*
2105          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2106          */
2107         return ((control & high) | low) == control;
2108 }
2109
2110 static inline u64 vmx_control_msr(u32 low, u32 high)
2111 {
2112         return low | ((u64)high << 32);
2113 }
2114
2115 /*
2116  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2117  * also let it use VMX-specific MSRs.
2118  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2119  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2120  * like all other MSRs).
2121  */
2122 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2123 {
2124         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2125                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2126                 /*
2127                  * According to the spec, processors which do not support VMX
2128                  * should throw a #GP(0) when VMX capability MSRs are read.
2129                  */
2130                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2131                 return 1;
2132         }
2133
2134         switch (msr_index) {
2135         case MSR_IA32_FEATURE_CONTROL:
2136                 *pdata = 0;
2137                 break;
2138         case MSR_IA32_VMX_BASIC:
2139                 /*
2140                  * This MSR reports some information about VMX support. We
2141                  * should return information about the VMX we emulate for the
2142                  * guest, and the VMCS structure we give it - not about the
2143                  * VMX support of the underlying hardware.
2144                  */
2145                 *pdata = VMCS12_REVISION |
2146                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2147                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2148                 break;
2149         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2150         case MSR_IA32_VMX_PINBASED_CTLS:
2151                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2152                                         nested_vmx_pinbased_ctls_high);
2153                 break;
2154         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2155         case MSR_IA32_VMX_PROCBASED_CTLS:
2156                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2157                                         nested_vmx_procbased_ctls_high);
2158                 break;
2159         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2160         case MSR_IA32_VMX_EXIT_CTLS:
2161                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2162                                         nested_vmx_exit_ctls_high);
2163                 break;
2164         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2165         case MSR_IA32_VMX_ENTRY_CTLS:
2166                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2167                                         nested_vmx_entry_ctls_high);
2168                 break;
2169         case MSR_IA32_VMX_MISC:
2170                 *pdata = 0;
2171                 break;
2172         /*
2173          * These MSRs specify bits which the guest must keep fixed (on or off)
2174          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2175          * We picked the standard core2 setting.
2176          */
2177 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2178 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2179         case MSR_IA32_VMX_CR0_FIXED0:
2180                 *pdata = VMXON_CR0_ALWAYSON;
2181                 break;
2182         case MSR_IA32_VMX_CR0_FIXED1:
2183                 *pdata = -1ULL;
2184                 break;
2185         case MSR_IA32_VMX_CR4_FIXED0:
2186                 *pdata = VMXON_CR4_ALWAYSON;
2187                 break;
2188         case MSR_IA32_VMX_CR4_FIXED1:
2189                 *pdata = -1ULL;
2190                 break;
2191         case MSR_IA32_VMX_VMCS_ENUM:
2192                 *pdata = 0x1f;
2193                 break;
2194         case MSR_IA32_VMX_PROCBASED_CTLS2:
2195                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2196                                         nested_vmx_secondary_ctls_high);
2197                 break;
2198         case MSR_IA32_VMX_EPT_VPID_CAP:
2199                 /* Currently, no nested ept or nested vpid */
2200                 *pdata = 0;
2201                 break;
2202         default:
2203                 return 0;
2204         }
2205
2206         return 1;
2207 }
2208
2209 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2210 {
2211         if (!nested_vmx_allowed(vcpu))
2212                 return 0;
2213
2214         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2215                 /* TODO: the right thing. */
2216                 return 1;
2217         /*
2218          * No need to treat VMX capability MSRs specially: If we don't handle
2219          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2220          */
2221         return 0;
2222 }
2223
2224 /*
2225  * Reads an msr value (of 'msr_index') into 'pdata'.
2226  * Returns 0 on success, non-0 otherwise.
2227  * Assumes vcpu_load() was already called.
2228  */
2229 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2230 {
2231         u64 data;
2232         struct shared_msr_entry *msr;
2233
2234         if (!pdata) {
2235                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2236                 return -EINVAL;
2237         }
2238
2239         switch (msr_index) {
2240 #ifdef CONFIG_X86_64
2241         case MSR_FS_BASE:
2242                 data = vmcs_readl(GUEST_FS_BASE);
2243                 break;
2244         case MSR_GS_BASE:
2245                 data = vmcs_readl(GUEST_GS_BASE);
2246                 break;
2247         case MSR_KERNEL_GS_BASE:
2248                 vmx_load_host_state(to_vmx(vcpu));
2249                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2250                 break;
2251 #endif
2252         case MSR_EFER:
2253                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2254         case MSR_IA32_TSC:
2255                 data = guest_read_tsc();
2256                 break;
2257         case MSR_IA32_SYSENTER_CS:
2258                 data = vmcs_read32(GUEST_SYSENTER_CS);
2259                 break;
2260         case MSR_IA32_SYSENTER_EIP:
2261                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2262                 break;
2263         case MSR_IA32_SYSENTER_ESP:
2264                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2265                 break;
2266         case MSR_TSC_AUX:
2267                 if (!to_vmx(vcpu)->rdtscp_enabled)
2268                         return 1;
2269                 /* Otherwise falls through */
2270         default:
2271                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2272                         return 0;
2273                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2274                 if (msr) {
2275                         data = msr->data;
2276                         break;
2277                 }
2278                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2279         }
2280
2281         *pdata = data;
2282         return 0;
2283 }
2284
2285 /*
2286  * Writes msr value into into the appropriate "register".
2287  * Returns 0 on success, non-0 otherwise.
2288  * Assumes vcpu_load() was already called.
2289  */
2290 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2291 {
2292         struct vcpu_vmx *vmx = to_vmx(vcpu);
2293         struct shared_msr_entry *msr;
2294         int ret = 0;
2295         u32 msr_index = msr_info->index;
2296         u64 data = msr_info->data;
2297
2298         switch (msr_index) {
2299         case MSR_EFER:
2300                 ret = kvm_set_msr_common(vcpu, msr_info);
2301                 break;
2302 #ifdef CONFIG_X86_64
2303         case MSR_FS_BASE:
2304                 vmx_segment_cache_clear(vmx);
2305                 vmcs_writel(GUEST_FS_BASE, data);
2306                 break;
2307         case MSR_GS_BASE:
2308                 vmx_segment_cache_clear(vmx);
2309                 vmcs_writel(GUEST_GS_BASE, data);
2310                 break;
2311         case MSR_KERNEL_GS_BASE:
2312                 vmx_load_host_state(vmx);
2313                 vmx->msr_guest_kernel_gs_base = data;
2314                 break;
2315 #endif
2316         case MSR_IA32_SYSENTER_CS:
2317                 vmcs_write32(GUEST_SYSENTER_CS, data);
2318                 break;
2319         case MSR_IA32_SYSENTER_EIP:
2320                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2321                 break;
2322         case MSR_IA32_SYSENTER_ESP:
2323                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2324                 break;
2325         case MSR_IA32_TSC:
2326                 kvm_write_tsc(vcpu, msr_info);
2327                 break;
2328         case MSR_IA32_CR_PAT:
2329                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2330                         vmcs_write64(GUEST_IA32_PAT, data);
2331                         vcpu->arch.pat = data;
2332                         break;
2333                 }
2334                 ret = kvm_set_msr_common(vcpu, msr_info);
2335                 break;
2336         case MSR_IA32_TSC_ADJUST:
2337                 ret = kvm_set_msr_common(vcpu, msr_info);
2338                 break;
2339         case MSR_TSC_AUX:
2340                 if (!vmx->rdtscp_enabled)
2341                         return 1;
2342                 /* Check reserved bit, higher 32 bits should be zero */
2343                 if ((data >> 32) != 0)
2344                         return 1;
2345                 /* Otherwise falls through */
2346         default:
2347                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2348                         break;
2349                 msr = find_msr_entry(vmx, msr_index);
2350                 if (msr) {
2351                         msr->data = data;
2352                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2353                                 preempt_disable();
2354                                 kvm_set_shared_msr(msr->index, msr->data,
2355                                                    msr->mask);
2356                                 preempt_enable();
2357                         }
2358                         break;
2359                 }
2360                 ret = kvm_set_msr_common(vcpu, msr_info);
2361         }
2362
2363         return ret;
2364 }
2365
2366 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2367 {
2368         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2369         switch (reg) {
2370         case VCPU_REGS_RSP:
2371                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2372                 break;
2373         case VCPU_REGS_RIP:
2374                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2375                 break;
2376         case VCPU_EXREG_PDPTR:
2377                 if (enable_ept)
2378                         ept_save_pdptrs(vcpu);
2379                 break;
2380         default:
2381                 break;
2382         }
2383 }
2384
2385 static __init int cpu_has_kvm_support(void)
2386 {
2387         return cpu_has_vmx();
2388 }
2389
2390 static __init int vmx_disabled_by_bios(void)
2391 {
2392         u64 msr;
2393
2394         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2395         if (msr & FEATURE_CONTROL_LOCKED) {
2396                 /* launched w/ TXT and VMX disabled */
2397                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2398                         && tboot_enabled())
2399                         return 1;
2400                 /* launched w/o TXT and VMX only enabled w/ TXT */
2401                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2402                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2403                         && !tboot_enabled()) {
2404                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2405                                 "activate TXT before enabling KVM\n");
2406                         return 1;
2407                 }
2408                 /* launched w/o TXT and VMX disabled */
2409                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2410                         && !tboot_enabled())
2411                         return 1;
2412         }
2413
2414         return 0;
2415 }
2416
2417 static void kvm_cpu_vmxon(u64 addr)
2418 {
2419         asm volatile (ASM_VMX_VMXON_RAX
2420                         : : "a"(&addr), "m"(addr)
2421                         : "memory", "cc");
2422 }
2423
2424 static int hardware_enable(void *garbage)
2425 {
2426         int cpu = raw_smp_processor_id();
2427         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2428         u64 old, test_bits;
2429
2430         if (read_cr4() & X86_CR4_VMXE)
2431                 return -EBUSY;
2432
2433         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2434
2435         /*
2436          * Now we can enable the vmclear operation in kdump
2437          * since the loaded_vmcss_on_cpu list on this cpu
2438          * has been initialized.
2439          *
2440          * Though the cpu is not in VMX operation now, there
2441          * is no problem to enable the vmclear operation
2442          * for the loaded_vmcss_on_cpu list is empty!
2443          */
2444         crash_enable_local_vmclear(cpu);
2445
2446         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2447
2448         test_bits = FEATURE_CONTROL_LOCKED;
2449         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2450         if (tboot_enabled())
2451                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2452
2453         if ((old & test_bits) != test_bits) {
2454                 /* enable and lock */
2455                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2456         }
2457         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2458
2459         if (vmm_exclusive) {
2460                 kvm_cpu_vmxon(phys_addr);
2461                 ept_sync_global();
2462         }
2463
2464         store_gdt(&__get_cpu_var(host_gdt));
2465
2466         return 0;
2467 }
2468
2469 static void vmclear_local_loaded_vmcss(void)
2470 {
2471         int cpu = raw_smp_processor_id();
2472         struct loaded_vmcs *v, *n;
2473
2474         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2475                                  loaded_vmcss_on_cpu_link)
2476                 __loaded_vmcs_clear(v);
2477 }
2478
2479
2480 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2481  * tricks.
2482  */
2483 static void kvm_cpu_vmxoff(void)
2484 {
2485         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2486 }
2487
2488 static void hardware_disable(void *garbage)
2489 {
2490         if (vmm_exclusive) {
2491                 vmclear_local_loaded_vmcss();
2492                 kvm_cpu_vmxoff();
2493         }
2494         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2495 }
2496
2497 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2498                                       u32 msr, u32 *result)
2499 {
2500         u32 vmx_msr_low, vmx_msr_high;
2501         u32 ctl = ctl_min | ctl_opt;
2502
2503         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2504
2505         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2506         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2507
2508         /* Ensure minimum (required) set of control bits are supported. */
2509         if (ctl_min & ~ctl)
2510                 return -EIO;
2511
2512         *result = ctl;
2513         return 0;
2514 }
2515
2516 static __init bool allow_1_setting(u32 msr, u32 ctl)
2517 {
2518         u32 vmx_msr_low, vmx_msr_high;
2519
2520         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2521         return vmx_msr_high & ctl;
2522 }
2523
2524 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2525 {
2526         u32 vmx_msr_low, vmx_msr_high;
2527         u32 min, opt, min2, opt2;
2528         u32 _pin_based_exec_control = 0;
2529         u32 _cpu_based_exec_control = 0;
2530         u32 _cpu_based_2nd_exec_control = 0;
2531         u32 _vmexit_control = 0;
2532         u32 _vmentry_control = 0;
2533
2534         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2535         opt = PIN_BASED_VIRTUAL_NMIS;
2536         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2537                                 &_pin_based_exec_control) < 0)
2538                 return -EIO;
2539
2540         min = CPU_BASED_HLT_EXITING |
2541 #ifdef CONFIG_X86_64
2542               CPU_BASED_CR8_LOAD_EXITING |
2543               CPU_BASED_CR8_STORE_EXITING |
2544 #endif
2545               CPU_BASED_CR3_LOAD_EXITING |
2546               CPU_BASED_CR3_STORE_EXITING |
2547               CPU_BASED_USE_IO_BITMAPS |
2548               CPU_BASED_MOV_DR_EXITING |
2549               CPU_BASED_USE_TSC_OFFSETING |
2550               CPU_BASED_MWAIT_EXITING |
2551               CPU_BASED_MONITOR_EXITING |
2552               CPU_BASED_INVLPG_EXITING |
2553               CPU_BASED_RDPMC_EXITING;
2554
2555         opt = CPU_BASED_TPR_SHADOW |
2556               CPU_BASED_USE_MSR_BITMAPS |
2557               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2558         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2559                                 &_cpu_based_exec_control) < 0)
2560                 return -EIO;
2561 #ifdef CONFIG_X86_64
2562         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2563                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2564                                            ~CPU_BASED_CR8_STORE_EXITING;
2565 #endif
2566         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2567                 min2 = 0;
2568                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2569                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2570                         SECONDARY_EXEC_WBINVD_EXITING |
2571                         SECONDARY_EXEC_ENABLE_VPID |
2572                         SECONDARY_EXEC_ENABLE_EPT |
2573                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2574                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2575                         SECONDARY_EXEC_RDTSCP |
2576                         SECONDARY_EXEC_ENABLE_INVPCID |
2577                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2578                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
2579                 if (adjust_vmx_controls(min2, opt2,
2580                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2581                                         &_cpu_based_2nd_exec_control) < 0)
2582                         return -EIO;
2583         }
2584 #ifndef CONFIG_X86_64
2585         if (!(_cpu_based_2nd_exec_control &
2586                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2587                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2588 #endif
2589
2590         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2591                 _cpu_based_2nd_exec_control &= ~(
2592                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2593                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2594                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2595
2596         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2597                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2598                    enabled */
2599                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2600                                              CPU_BASED_CR3_STORE_EXITING |
2601                                              CPU_BASED_INVLPG_EXITING);
2602                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2603                       vmx_capability.ept, vmx_capability.vpid);
2604         }
2605
2606         min = 0;
2607 #ifdef CONFIG_X86_64
2608         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2609 #endif
2610         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2611         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2612                                 &_vmexit_control) < 0)
2613                 return -EIO;
2614
2615         min = 0;
2616         opt = VM_ENTRY_LOAD_IA32_PAT;
2617         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2618                                 &_vmentry_control) < 0)
2619                 return -EIO;
2620
2621         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2622
2623         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2624         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2625                 return -EIO;
2626
2627 #ifdef CONFIG_X86_64
2628         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2629         if (vmx_msr_high & (1u<<16))
2630                 return -EIO;
2631 #endif
2632
2633         /* Require Write-Back (WB) memory type for VMCS accesses. */
2634         if (((vmx_msr_high >> 18) & 15) != 6)
2635                 return -EIO;
2636
2637         vmcs_conf->size = vmx_msr_high & 0x1fff;
2638         vmcs_conf->order = get_order(vmcs_config.size);
2639         vmcs_conf->revision_id = vmx_msr_low;
2640
2641         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2642         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2643         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2644         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2645         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2646
2647         cpu_has_load_ia32_efer =
2648                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2649                                 VM_ENTRY_LOAD_IA32_EFER)
2650                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2651                                    VM_EXIT_LOAD_IA32_EFER);
2652
2653         cpu_has_load_perf_global_ctrl =
2654                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2655                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2656                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2657                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2658
2659         /*
2660          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2661          * but due to arrata below it can't be used. Workaround is to use
2662          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2663          *
2664          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2665          *
2666          * AAK155             (model 26)
2667          * AAP115             (model 30)
2668          * AAT100             (model 37)
2669          * BC86,AAY89,BD102   (model 44)
2670          * BA97               (model 46)
2671          *
2672          */
2673         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2674                 switch (boot_cpu_data.x86_model) {
2675                 case 26:
2676                 case 30:
2677                 case 37:
2678                 case 44:
2679                 case 46:
2680                         cpu_has_load_perf_global_ctrl = false;
2681                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2682                                         "does not work properly. Using workaround\n");
2683                         break;
2684                 default:
2685                         break;
2686                 }
2687         }
2688
2689         return 0;
2690 }
2691
2692 static struct vmcs *alloc_vmcs_cpu(int cpu)
2693 {
2694         int node = cpu_to_node(cpu);
2695         struct page *pages;
2696         struct vmcs *vmcs;
2697
2698         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2699         if (!pages)
2700                 return NULL;
2701         vmcs = page_address(pages);
2702         memset(vmcs, 0, vmcs_config.size);
2703         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2704         return vmcs;
2705 }
2706
2707 static struct vmcs *alloc_vmcs(void)
2708 {
2709         return alloc_vmcs_cpu(raw_smp_processor_id());
2710 }
2711
2712 static void free_vmcs(struct vmcs *vmcs)
2713 {
2714         free_pages((unsigned long)vmcs, vmcs_config.order);
2715 }
2716
2717 /*
2718  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2719  */
2720 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2721 {
2722         if (!loaded_vmcs->vmcs)
2723                 return;
2724         loaded_vmcs_clear(loaded_vmcs);
2725         free_vmcs(loaded_vmcs->vmcs);
2726         loaded_vmcs->vmcs = NULL;
2727 }
2728
2729 static void free_kvm_area(void)
2730 {
2731         int cpu;
2732
2733         for_each_possible_cpu(cpu) {
2734                 free_vmcs(per_cpu(vmxarea, cpu));
2735                 per_cpu(vmxarea, cpu) = NULL;
2736         }
2737 }
2738
2739 static __init int alloc_kvm_area(void)
2740 {
2741         int cpu;
2742
2743         for_each_possible_cpu(cpu) {
2744                 struct vmcs *vmcs;
2745
2746                 vmcs = alloc_vmcs_cpu(cpu);
2747                 if (!vmcs) {
2748                         free_kvm_area();
2749                         return -ENOMEM;
2750                 }
2751
2752                 per_cpu(vmxarea, cpu) = vmcs;
2753         }
2754         return 0;
2755 }
2756
2757 static __init int hardware_setup(void)
2758 {
2759         if (setup_vmcs_config(&vmcs_config) < 0)
2760                 return -EIO;
2761
2762         if (boot_cpu_has(X86_FEATURE_NX))
2763                 kvm_enable_efer_bits(EFER_NX);
2764
2765         if (!cpu_has_vmx_vpid())
2766                 enable_vpid = 0;
2767
2768         if (!cpu_has_vmx_ept() ||
2769             !cpu_has_vmx_ept_4levels()) {
2770                 enable_ept = 0;
2771                 enable_unrestricted_guest = 0;
2772                 enable_ept_ad_bits = 0;
2773         }
2774
2775         if (!cpu_has_vmx_ept_ad_bits())
2776                 enable_ept_ad_bits = 0;
2777
2778         if (!cpu_has_vmx_unrestricted_guest())
2779                 enable_unrestricted_guest = 0;
2780
2781         if (!cpu_has_vmx_flexpriority())
2782                 flexpriority_enabled = 0;
2783
2784         if (!cpu_has_vmx_tpr_shadow())
2785                 kvm_x86_ops->update_cr8_intercept = NULL;
2786
2787         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2788                 kvm_disable_largepages();
2789
2790         if (!cpu_has_vmx_ple())
2791                 ple_gap = 0;
2792
2793         if (!cpu_has_vmx_apic_register_virt() ||
2794                                 !cpu_has_vmx_virtual_intr_delivery())
2795                 enable_apicv_reg_vid = 0;
2796
2797         if (enable_apicv_reg_vid)
2798                 kvm_x86_ops->update_cr8_intercept = NULL;
2799         else
2800                 kvm_x86_ops->hwapic_irr_update = NULL;
2801
2802         if (nested)
2803                 nested_vmx_setup_ctls_msrs();
2804
2805         return alloc_kvm_area();
2806 }
2807
2808 static __exit void hardware_unsetup(void)
2809 {
2810         free_kvm_area();
2811 }
2812
2813 static bool emulation_required(struct kvm_vcpu *vcpu)
2814 {
2815         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2816 }
2817
2818 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2819                 struct kvm_segment *save)
2820 {
2821         if (!emulate_invalid_guest_state) {
2822                 /*
2823                  * CS and SS RPL should be equal during guest entry according
2824                  * to VMX spec, but in reality it is not always so. Since vcpu
2825                  * is in the middle of the transition from real mode to
2826                  * protected mode it is safe to assume that RPL 0 is a good
2827                  * default value.
2828                  */
2829                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2830                         save->selector &= ~SELECTOR_RPL_MASK;
2831                 save->dpl = save->selector & SELECTOR_RPL_MASK;
2832                 save->s = 1;
2833         }
2834         vmx_set_segment(vcpu, save, seg);
2835 }
2836
2837 static void enter_pmode(struct kvm_vcpu *vcpu)
2838 {
2839         unsigned long flags;
2840         struct vcpu_vmx *vmx = to_vmx(vcpu);
2841
2842         /*
2843          * Update real mode segment cache. It may be not up-to-date if sement
2844          * register was written while vcpu was in a guest mode.
2845          */
2846         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2847         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2848         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2849         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2850         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2851         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2852
2853         vmx->rmode.vm86_active = 0;
2854
2855         vmx_segment_cache_clear(vmx);
2856
2857         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2858
2859         flags = vmcs_readl(GUEST_RFLAGS);
2860         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2861         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2862         vmcs_writel(GUEST_RFLAGS, flags);
2863
2864         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2865                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2866
2867         update_exception_bitmap(vcpu);
2868
2869         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2870         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2871         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2872         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2873         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2874         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2875
2876         /* CPL is always 0 when CPU enters protected mode */
2877         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2878         vmx->cpl = 0;
2879 }
2880
2881 static gva_t rmode_tss_base(struct kvm *kvm)
2882 {
2883         if (!kvm->arch.tss_addr) {
2884                 struct kvm_memslots *slots;
2885                 struct kvm_memory_slot *slot;
2886                 gfn_t base_gfn;
2887
2888                 slots = kvm_memslots(kvm);
2889                 slot = id_to_memslot(slots, 0);
2890                 base_gfn = slot->base_gfn + slot->npages - 3;
2891
2892                 return base_gfn << PAGE_SHIFT;
2893         }
2894         return kvm->arch.tss_addr;
2895 }
2896
2897 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2898 {
2899         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2900         struct kvm_segment var = *save;
2901
2902         var.dpl = 0x3;
2903         if (seg == VCPU_SREG_CS)
2904                 var.type = 0x3;
2905
2906         if (!emulate_invalid_guest_state) {
2907                 var.selector = var.base >> 4;
2908                 var.base = var.base & 0xffff0;
2909                 var.limit = 0xffff;
2910                 var.g = 0;
2911                 var.db = 0;
2912                 var.present = 1;
2913                 var.s = 1;
2914                 var.l = 0;
2915                 var.unusable = 0;
2916                 var.type = 0x3;
2917                 var.avl = 0;
2918                 if (save->base & 0xf)
2919                         printk_once(KERN_WARNING "kvm: segment base is not "
2920                                         "paragraph aligned when entering "
2921                                         "protected mode (seg=%d)", seg);
2922         }
2923
2924         vmcs_write16(sf->selector, var.selector);
2925         vmcs_write32(sf->base, var.base);
2926         vmcs_write32(sf->limit, var.limit);
2927         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2928 }
2929
2930 static void enter_rmode(struct kvm_vcpu *vcpu)
2931 {
2932         unsigned long flags;
2933         struct vcpu_vmx *vmx = to_vmx(vcpu);
2934
2935         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2936         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2937         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2938         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2939         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2940         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2941         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2942
2943         vmx->rmode.vm86_active = 1;
2944
2945         /*
2946          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2947          * vcpu. Call it here with phys address pointing 16M below 4G.
2948          */
2949         if (!vcpu->kvm->arch.tss_addr) {
2950                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2951                              "called before entering vcpu\n");
2952                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2953                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2954                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2955         }
2956
2957         vmx_segment_cache_clear(vmx);
2958
2959         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2960         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2961         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2962
2963         flags = vmcs_readl(GUEST_RFLAGS);
2964         vmx->rmode.save_rflags = flags;
2965
2966         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2967
2968         vmcs_writel(GUEST_RFLAGS, flags);
2969         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2970         update_exception_bitmap(vcpu);
2971
2972         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2973         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2974         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2975         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2976         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2977         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2978
2979         kvm_mmu_reset_context(vcpu);
2980 }
2981
2982 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2983 {
2984         struct vcpu_vmx *vmx = to_vmx(vcpu);
2985         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2986
2987         if (!msr)
2988                 return;
2989
2990         /*
2991          * Force kernel_gs_base reloading before EFER changes, as control
2992          * of this msr depends on is_long_mode().
2993          */
2994         vmx_load_host_state(to_vmx(vcpu));
2995         vcpu->arch.efer = efer;
2996         if (efer & EFER_LMA) {
2997                 vmcs_write32(VM_ENTRY_CONTROLS,
2998                              vmcs_read32(VM_ENTRY_CONTROLS) |
2999                              VM_ENTRY_IA32E_MODE);
3000                 msr->data = efer;
3001         } else {
3002                 vmcs_write32(VM_ENTRY_CONTROLS,
3003                              vmcs_read32(VM_ENTRY_CONTROLS) &
3004                              ~VM_ENTRY_IA32E_MODE);
3005
3006                 msr->data = efer & ~EFER_LME;
3007         }
3008         setup_msrs(vmx);
3009 }
3010
3011 #ifdef CONFIG_X86_64
3012
3013 static void enter_lmode(struct kvm_vcpu *vcpu)
3014 {
3015         u32 guest_tr_ar;
3016
3017         vmx_segment_cache_clear(to_vmx(vcpu));
3018
3019         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3020         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3021                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3022                                      __func__);
3023                 vmcs_write32(GUEST_TR_AR_BYTES,
3024                              (guest_tr_ar & ~AR_TYPE_MASK)
3025                              | AR_TYPE_BUSY_64_TSS);
3026         }
3027         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3028 }
3029
3030 static void exit_lmode(struct kvm_vcpu *vcpu)
3031 {
3032         vmcs_write32(VM_ENTRY_CONTROLS,
3033                      vmcs_read32(VM_ENTRY_CONTROLS)
3034                      & ~VM_ENTRY_IA32E_MODE);
3035         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3036 }
3037
3038 #endif
3039
3040 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3041 {
3042         vpid_sync_context(to_vmx(vcpu));
3043         if (enable_ept) {
3044                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3045                         return;
3046                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3047         }
3048 }
3049
3050 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3051 {
3052         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3053
3054         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3055         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3056 }
3057
3058 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3059 {
3060         if (enable_ept && is_paging(vcpu))
3061                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3062         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3063 }
3064
3065 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3066 {
3067         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3068
3069         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3070         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3071 }
3072
3073 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3074 {
3075         if (!test_bit(VCPU_EXREG_PDPTR,
3076                       (unsigned long *)&vcpu->arch.regs_dirty))
3077                 return;
3078
3079         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3080                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3081                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3082                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3083                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3084         }
3085 }
3086
3087 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3088 {
3089         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3090                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3091                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3092                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3093                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3094         }
3095
3096         __set_bit(VCPU_EXREG_PDPTR,
3097                   (unsigned long *)&vcpu->arch.regs_avail);
3098         __set_bit(VCPU_EXREG_PDPTR,
3099                   (unsigned long *)&vcpu->arch.regs_dirty);
3100 }
3101
3102 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3103
3104 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3105                                         unsigned long cr0,
3106                                         struct kvm_vcpu *vcpu)
3107 {
3108         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3109                 vmx_decache_cr3(vcpu);
3110         if (!(cr0 & X86_CR0_PG)) {
3111                 /* From paging/starting to nonpaging */
3112                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3113                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3114                              (CPU_BASED_CR3_LOAD_EXITING |
3115                               CPU_BASED_CR3_STORE_EXITING));
3116                 vcpu->arch.cr0 = cr0;
3117                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3118         } else if (!is_paging(vcpu)) {
3119                 /* From nonpaging to paging */
3120                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3121                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3122                              ~(CPU_BASED_CR3_LOAD_EXITING |
3123                                CPU_BASED_CR3_STORE_EXITING));
3124                 vcpu->arch.cr0 = cr0;
3125                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3126         }
3127
3128         if (!(cr0 & X86_CR0_WP))
3129                 *hw_cr0 &= ~X86_CR0_WP;
3130 }
3131
3132 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3133 {
3134         struct vcpu_vmx *vmx = to_vmx(vcpu);
3135         unsigned long hw_cr0;
3136
3137         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3138         if (enable_unrestricted_guest)
3139                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3140         else {
3141                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3142
3143                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3144                         enter_pmode(vcpu);
3145
3146                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3147                         enter_rmode(vcpu);
3148         }
3149
3150 #ifdef CONFIG_X86_64
3151         if (vcpu->arch.efer & EFER_LME) {
3152                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3153                         enter_lmode(vcpu);
3154                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3155                         exit_lmode(vcpu);
3156         }
3157 #endif
3158
3159         if (enable_ept)
3160                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3161
3162         if (!vcpu->fpu_active)
3163                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3164
3165         vmcs_writel(CR0_READ_SHADOW, cr0);
3166         vmcs_writel(GUEST_CR0, hw_cr0);
3167         vcpu->arch.cr0 = cr0;
3168
3169         /* depends on vcpu->arch.cr0 to be set to a new value */
3170         vmx->emulation_required = emulation_required(vcpu);
3171 }
3172
3173 static u64 construct_eptp(unsigned long root_hpa)
3174 {
3175         u64 eptp;
3176
3177         /* TODO write the value reading from MSR */
3178         eptp = VMX_EPT_DEFAULT_MT |
3179                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3180         if (enable_ept_ad_bits)
3181                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3182         eptp |= (root_hpa & PAGE_MASK);
3183
3184         return eptp;
3185 }
3186
3187 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3188 {
3189         unsigned long guest_cr3;
3190         u64 eptp;
3191
3192         guest_cr3 = cr3;
3193         if (enable_ept) {
3194                 eptp = construct_eptp(cr3);
3195                 vmcs_write64(EPT_POINTER, eptp);
3196                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3197                         vcpu->kvm->arch.ept_identity_map_addr;
3198                 ept_load_pdptrs(vcpu);
3199         }
3200
3201         vmx_flush_tlb(vcpu);
3202         vmcs_writel(GUEST_CR3, guest_cr3);
3203 }
3204
3205 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3206 {
3207         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3208                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3209
3210         if (cr4 & X86_CR4_VMXE) {
3211                 /*
3212                  * To use VMXON (and later other VMX instructions), a guest
3213                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3214                  * So basically the check on whether to allow nested VMX
3215                  * is here.
3216                  */
3217                 if (!nested_vmx_allowed(vcpu))
3218                         return 1;
3219         } else if (to_vmx(vcpu)->nested.vmxon)
3220                 return 1;
3221
3222         vcpu->arch.cr4 = cr4;
3223         if (enable_ept) {
3224                 if (!is_paging(vcpu)) {
3225                         hw_cr4 &= ~X86_CR4_PAE;
3226                         hw_cr4 |= X86_CR4_PSE;
3227                         /*
3228                          * SMEP is disabled if CPU is in non-paging mode in
3229                          * hardware. However KVM always uses paging mode to
3230                          * emulate guest non-paging mode with TDP.
3231                          * To emulate this behavior, SMEP needs to be manually
3232                          * disabled when guest switches to non-paging mode.
3233                          */
3234                         hw_cr4 &= ~X86_CR4_SMEP;
3235                 } else if (!(cr4 & X86_CR4_PAE)) {
3236                         hw_cr4 &= ~X86_CR4_PAE;
3237                 }
3238         }
3239
3240         vmcs_writel(CR4_READ_SHADOW, cr4);
3241         vmcs_writel(GUEST_CR4, hw_cr4);
3242         return 0;
3243 }
3244
3245 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3246                             struct kvm_segment *var, int seg)
3247 {
3248         struct vcpu_vmx *vmx = to_vmx(vcpu);
3249         u32 ar;
3250
3251         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3252                 *var = vmx->rmode.segs[seg];
3253                 if (seg == VCPU_SREG_TR
3254                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3255                         return;
3256                 var->base = vmx_read_guest_seg_base(vmx, seg);
3257                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3258                 return;
3259         }
3260         var->base = vmx_read_guest_seg_base(vmx, seg);
3261         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3262         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3263         ar = vmx_read_guest_seg_ar(vmx, seg);
3264         var->type = ar & 15;
3265         var->s = (ar >> 4) & 1;
3266         var->dpl = (ar >> 5) & 3;
3267         var->present = (ar >> 7) & 1;
3268         var->avl = (ar >> 12) & 1;
3269         var->l = (ar >> 13) & 1;
3270         var->db = (ar >> 14) & 1;
3271         var->g = (ar >> 15) & 1;
3272         var->unusable = (ar >> 16) & 1;
3273 }
3274
3275 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3276 {
3277         struct kvm_segment s;
3278
3279         if (to_vmx(vcpu)->rmode.vm86_active) {
3280                 vmx_get_segment(vcpu, &s, seg);
3281                 return s.base;
3282         }
3283         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3284 }
3285
3286 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3287 {
3288         struct vcpu_vmx *vmx = to_vmx(vcpu);
3289
3290         if (!is_protmode(vcpu))
3291                 return 0;
3292
3293         if (!is_long_mode(vcpu)
3294             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3295                 return 3;
3296
3297         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3298                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3299                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3300         }
3301
3302         return vmx->cpl;
3303 }
3304
3305
3306 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3307 {
3308         u32 ar;
3309
3310         if (var->unusable || !var->present)
3311                 ar = 1 << 16;
3312         else {
3313                 ar = var->type & 15;
3314                 ar |= (var->s & 1) << 4;
3315                 ar |= (var->dpl & 3) << 5;
3316                 ar |= (var->present & 1) << 7;
3317                 ar |= (var->avl & 1) << 12;
3318                 ar |= (var->l & 1) << 13;
3319                 ar |= (var->db & 1) << 14;
3320                 ar |= (var->g & 1) << 15;
3321         }
3322
3323         return ar;
3324 }
3325
3326 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3327                             struct kvm_segment *var, int seg)
3328 {
3329         struct vcpu_vmx *vmx = to_vmx(vcpu);
3330         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3331
3332         vmx_segment_cache_clear(vmx);
3333         if (seg == VCPU_SREG_CS)
3334                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3335
3336         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3337                 vmx->rmode.segs[seg] = *var;
3338                 if (seg == VCPU_SREG_TR)
3339                         vmcs_write16(sf->selector, var->selector);
3340                 else if (var->s)
3341                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3342                 goto out;
3343         }
3344
3345         vmcs_writel(sf->base, var->base);
3346         vmcs_write32(sf->limit, var->limit);
3347         vmcs_write16(sf->selector, var->selector);
3348
3349         /*
3350          *   Fix the "Accessed" bit in AR field of segment registers for older
3351          * qemu binaries.
3352          *   IA32 arch specifies that at the time of processor reset the
3353          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3354          * is setting it to 0 in the userland code. This causes invalid guest
3355          * state vmexit when "unrestricted guest" mode is turned on.
3356          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3357          * tree. Newer qemu binaries with that qemu fix would not need this
3358          * kvm hack.
3359          */
3360         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3361                 var->type |= 0x1; /* Accessed */
3362
3363         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3364
3365 out:
3366         vmx->emulation_required |= emulation_required(vcpu);
3367 }
3368
3369 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3370 {
3371         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3372
3373         *db = (ar >> 14) & 1;
3374         *l = (ar >> 13) & 1;
3375 }
3376
3377 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3378 {
3379         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3380         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3381 }
3382
3383 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3384 {
3385         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3386         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3387 }
3388
3389 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3390 {
3391         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3392         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3393 }
3394
3395 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3396 {
3397         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3398         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3399 }
3400
3401 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3402 {
3403         struct kvm_segment var;
3404         u32 ar;
3405
3406         vmx_get_segment(vcpu, &var, seg);
3407         var.dpl = 0x3;
3408         if (seg == VCPU_SREG_CS)
3409                 var.type = 0x3;
3410         ar = vmx_segment_access_rights(&var);
3411
3412         if (var.base != (var.selector << 4))
3413                 return false;
3414         if (var.limit != 0xffff)
3415                 return false;
3416         if (ar != 0xf3)
3417                 return false;
3418
3419         return true;
3420 }
3421
3422 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3423 {
3424         struct kvm_segment cs;
3425         unsigned int cs_rpl;
3426
3427         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3428         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3429
3430         if (cs.unusable)
3431                 return false;
3432         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3433                 return false;
3434         if (!cs.s)
3435                 return false;
3436         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3437                 if (cs.dpl > cs_rpl)
3438                         return false;
3439         } else {
3440                 if (cs.dpl != cs_rpl)
3441                         return false;
3442         }
3443         if (!cs.present)
3444                 return false;
3445
3446         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3447         return true;
3448 }
3449
3450 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3451 {
3452         struct kvm_segment ss;
3453         unsigned int ss_rpl;
3454
3455         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3456         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3457
3458         if (ss.unusable)
3459                 return true;
3460         if (ss.type != 3 && ss.type != 7)
3461                 return false;
3462         if (!ss.s)
3463                 return false;
3464         if (ss.dpl != ss_rpl) /* DPL != RPL */
3465                 return false;
3466         if (!ss.present)
3467                 return false;
3468
3469         return true;
3470 }
3471
3472 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3473 {
3474         struct kvm_segment var;
3475         unsigned int rpl;
3476
3477         vmx_get_segment(vcpu, &var, seg);
3478         rpl = var.selector & SELECTOR_RPL_MASK;
3479
3480         if (var.unusable)
3481                 return true;
3482         if (!var.s)
3483                 return false;
3484         if (!var.present)
3485                 return false;
3486         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3487                 if (var.dpl < rpl) /* DPL < RPL */
3488                         return false;
3489         }
3490
3491         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3492          * rights flags
3493          */
3494         return true;
3495 }
3496
3497 static bool tr_valid(struct kvm_vcpu *vcpu)
3498 {
3499         struct kvm_segment tr;
3500
3501         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3502
3503         if (tr.unusable)
3504                 return false;
3505         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3506                 return false;
3507         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3508                 return false;
3509         if (!tr.present)
3510                 return false;
3511
3512         return true;
3513 }
3514
3515 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3516 {
3517         struct kvm_segment ldtr;
3518
3519         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3520
3521         if (ldtr.unusable)
3522                 return true;
3523         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3524                 return false;
3525         if (ldtr.type != 2)
3526                 return false;
3527         if (!ldtr.present)
3528                 return false;
3529
3530         return true;
3531 }
3532
3533 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3534 {
3535         struct kvm_segment cs, ss;
3536
3537         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3538         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3539
3540         return ((cs.selector & SELECTOR_RPL_MASK) ==
3541                  (ss.selector & SELECTOR_RPL_MASK));
3542 }
3543
3544 /*
3545  * Check if guest state is valid. Returns true if valid, false if
3546  * not.
3547  * We assume that registers are always usable
3548  */
3549 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3550 {
3551         if (enable_unrestricted_guest)
3552                 return true;
3553
3554         /* real mode guest state checks */
3555         if (!is_protmode(vcpu)) {
3556                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3557                         return false;
3558                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3559                         return false;
3560                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3561                         return false;
3562                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3563                         return false;
3564                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3565                         return false;
3566                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3567                         return false;
3568         } else {
3569         /* protected mode guest state checks */
3570                 if (!cs_ss_rpl_check(vcpu))
3571                         return false;
3572                 if (!code_segment_valid(vcpu))
3573                         return false;
3574                 if (!stack_segment_valid(vcpu))
3575                         return false;
3576                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3577                         return false;
3578                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3579                         return false;
3580                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3581                         return false;
3582                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3583                         return false;
3584                 if (!tr_valid(vcpu))
3585                         return false;
3586                 if (!ldtr_valid(vcpu))
3587                         return false;
3588         }
3589         /* TODO:
3590          * - Add checks on RIP
3591          * - Add checks on RFLAGS
3592          */
3593
3594         return true;
3595 }
3596
3597 static int init_rmode_tss(struct kvm *kvm)
3598 {
3599         gfn_t fn;
3600         u16 data = 0;
3601         int r, idx, ret = 0;
3602
3603         idx = srcu_read_lock(&kvm->srcu);
3604         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3605         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3606         if (r < 0)
3607                 goto out;
3608         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3609         r = kvm_write_guest_page(kvm, fn++, &data,
3610                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3611         if (r < 0)
3612                 goto out;
3613         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3614         if (r < 0)
3615                 goto out;
3616         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3617         if (r < 0)
3618                 goto out;
3619         data = ~0;
3620         r = kvm_write_guest_page(kvm, fn, &data,
3621                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3622                                  sizeof(u8));
3623         if (r < 0)
3624                 goto out;
3625
3626         ret = 1;
3627 out:
3628         srcu_read_unlock(&kvm->srcu, idx);
3629         return ret;
3630 }
3631
3632 static int init_rmode_identity_map(struct kvm *kvm)
3633 {
3634         int i, idx, r, ret;
3635         pfn_t identity_map_pfn;
3636         u32 tmp;
3637
3638         if (!enable_ept)
3639                 return 1;
3640         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3641                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3642                         "haven't been allocated!\n");
3643                 return 0;
3644         }
3645         if (likely(kvm->arch.ept_identity_pagetable_done))
3646                 return 1;
3647         ret = 0;
3648         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3649         idx = srcu_read_lock(&kvm->srcu);
3650         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3651         if (r < 0)
3652                 goto out;
3653         /* Set up identity-mapping pagetable for EPT in real mode */
3654         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3655                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3656                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3657                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3658                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3659                 if (r < 0)
3660                         goto out;
3661         }
3662         kvm->arch.ept_identity_pagetable_done = true;
3663         ret = 1;
3664 out:
3665         srcu_read_unlock(&kvm->srcu, idx);
3666         return ret;
3667 }
3668
3669 static void seg_setup(int seg)
3670 {
3671         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3672         unsigned int ar;
3673
3674         vmcs_write16(sf->selector, 0);
3675         vmcs_writel(sf->base, 0);
3676         vmcs_write32(sf->limit, 0xffff);
3677         ar = 0x93;
3678         if (seg == VCPU_SREG_CS)
3679                 ar |= 0x08; /* code segment */
3680
3681         vmcs_write32(sf->ar_bytes, ar);
3682 }
3683
3684 static int alloc_apic_access_page(struct kvm *kvm)
3685 {
3686         struct page *page;
3687         struct kvm_userspace_memory_region kvm_userspace_mem;
3688         int r = 0;
3689
3690         mutex_lock(&kvm->slots_lock);
3691         if (kvm->arch.apic_access_page)
3692                 goto out;
3693         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3694         kvm_userspace_mem.flags = 0;
3695         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3696         kvm_userspace_mem.memory_size = PAGE_SIZE;
3697         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3698         if (r)
3699                 goto out;
3700
3701         page = gfn_to_page(kvm, 0xfee00);
3702         if (is_error_page(page)) {
3703                 r = -EFAULT;
3704                 goto out;
3705         }
3706
3707         kvm->arch.apic_access_page = page;
3708 out:
3709         mutex_unlock(&kvm->slots_lock);
3710         return r;
3711 }
3712
3713 static int alloc_identity_pagetable(struct kvm *kvm)
3714 {
3715         struct page *page;
3716         struct kvm_userspace_memory_region kvm_userspace_mem;
3717         int r = 0;
3718
3719         mutex_lock(&kvm->slots_lock);
3720         if (kvm->arch.ept_identity_pagetable)
3721                 goto out;
3722         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3723         kvm_userspace_mem.flags = 0;
3724         kvm_userspace_mem.guest_phys_addr =
3725                 kvm->arch.ept_identity_map_addr;
3726         kvm_userspace_mem.memory_size = PAGE_SIZE;
3727         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3728         if (r)
3729                 goto out;
3730
3731         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3732         if (is_error_page(page)) {
3733                 r = -EFAULT;
3734                 goto out;
3735         }
3736
3737         kvm->arch.ept_identity_pagetable = page;
3738 out:
3739         mutex_unlock(&kvm->slots_lock);
3740         return r;
3741 }
3742
3743 static void allocate_vpid(struct vcpu_vmx *vmx)
3744 {
3745         int vpid;
3746
3747         vmx->vpid = 0;
3748         if (!enable_vpid)
3749                 return;
3750         spin_lock(&vmx_vpid_lock);
3751         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3752         if (vpid < VMX_NR_VPIDS) {
3753                 vmx->vpid = vpid;
3754                 __set_bit(vpid, vmx_vpid_bitmap);
3755         }
3756         spin_unlock(&vmx_vpid_lock);
3757 }
3758
3759 static void free_vpid(struct vcpu_vmx *vmx)
3760 {
3761         if (!enable_vpid)
3762                 return;
3763         spin_lock(&vmx_vpid_lock);
3764         if (vmx->vpid != 0)
3765                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3766         spin_unlock(&vmx_vpid_lock);
3767 }
3768
3769 #define MSR_TYPE_R      1
3770 #define MSR_TYPE_W      2
3771 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3772                                                 u32 msr, int type)
3773 {
3774         int f = sizeof(unsigned long);
3775
3776         if (!cpu_has_vmx_msr_bitmap())
3777                 return;
3778
3779         /*
3780          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3781          * have the write-low and read-high bitmap offsets the wrong way round.
3782          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3783          */
3784         if (msr <= 0x1fff) {
3785                 if (type & MSR_TYPE_R)
3786                         /* read-low */
3787                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3788
3789                 if (type & MSR_TYPE_W)
3790                         /* write-low */
3791                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3792
3793         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3794                 msr &= 0x1fff;
3795                 if (type & MSR_TYPE_R)
3796                         /* read-high */
3797                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3798
3799                 if (type & MSR_TYPE_W)
3800                         /* write-high */
3801                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
3802
3803         }
3804 }
3805
3806 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3807                                                 u32 msr, int type)
3808 {
3809         int f = sizeof(unsigned long);
3810
3811         if (!cpu_has_vmx_msr_bitmap())
3812                 return;
3813
3814         /*
3815          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3816          * have the write-low and read-high bitmap offsets the wrong way round.
3817          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3818          */
3819         if (msr <= 0x1fff) {
3820                 if (type & MSR_TYPE_R)
3821                         /* read-low */
3822                         __set_bit(msr, msr_bitmap + 0x000 / f);
3823
3824                 if (type & MSR_TYPE_W)
3825                         /* write-low */
3826                         __set_bit(msr, msr_bitmap + 0x800 / f);
3827
3828         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3829                 msr &= 0x1fff;
3830                 if (type & MSR_TYPE_R)
3831                         /* read-high */
3832                         __set_bit(msr, msr_bitmap + 0x400 / f);
3833
3834                 if (type & MSR_TYPE_W)
3835                         /* write-high */
3836                         __set_bit(msr, msr_bitmap + 0xc00 / f);
3837
3838         }
3839 }
3840
3841 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3842 {
3843         if (!longmode_only)
3844                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3845                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3846         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3847                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
3848 }
3849
3850 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3851 {
3852         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3853                         msr, MSR_TYPE_R);
3854         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3855                         msr, MSR_TYPE_R);
3856 }
3857
3858 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3859 {
3860         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3861                         msr, MSR_TYPE_R);
3862         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3863                         msr, MSR_TYPE_R);
3864 }
3865
3866 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3867 {
3868         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3869                         msr, MSR_TYPE_W);
3870         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3871                         msr, MSR_TYPE_W);
3872 }
3873
3874 /*
3875  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3876  * will not change in the lifetime of the guest.
3877  * Note that host-state that does change is set elsewhere. E.g., host-state
3878  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3879  */
3880 static void vmx_set_constant_host_state(void)
3881 {
3882         u32 low32, high32;
3883         unsigned long tmpl;
3884         struct desc_ptr dt;
3885
3886         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
3887         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3888         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3889
3890         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3891 #ifdef CONFIG_X86_64
3892         /*
3893          * Load null selectors, so we can avoid reloading them in
3894          * __vmx_load_host_state(), in case userspace uses the null selectors
3895          * too (the expected case).
3896          */
3897         vmcs_write16(HOST_DS_SELECTOR, 0);
3898         vmcs_write16(HOST_ES_SELECTOR, 0);
3899 #else
3900         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3901         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3902 #endif
3903         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3904         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3905
3906         native_store_idt(&dt);
3907         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3908
3909         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
3910
3911         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3912         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3913         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3914         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3915
3916         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3917                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3918                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3919         }
3920 }
3921
3922 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3923 {
3924         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3925         if (enable_ept)
3926                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3927         if (is_guest_mode(&vmx->vcpu))
3928                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3929                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3930         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3931 }
3932
3933 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3934 {
3935         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3936         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3937                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3938 #ifdef CONFIG_X86_64
3939                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3940                                 CPU_BASED_CR8_LOAD_EXITING;
3941 #endif
3942         }
3943         if (!enable_ept)
3944                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3945                                 CPU_BASED_CR3_LOAD_EXITING  |
3946                                 CPU_BASED_INVLPG_EXITING;
3947         return exec_control;
3948 }
3949
3950 static int vmx_vm_has_apicv(struct kvm *kvm)
3951 {
3952         return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
3953 }
3954
3955 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3956 {
3957         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3958         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3959                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3960         if (vmx->vpid == 0)
3961                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3962         if (!enable_ept) {
3963                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3964                 enable_unrestricted_guest = 0;
3965                 /* Enable INVPCID for non-ept guests may cause performance regression. */
3966                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3967         }
3968         if (!enable_unrestricted_guest)
3969                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3970         if (!ple_gap)
3971                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3972         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
3973                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3974                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3975         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3976         return exec_control;
3977 }
3978
3979 static void ept_set_mmio_spte_mask(void)
3980 {
3981         /*
3982          * EPT Misconfigurations can be generated if the value of bits 2:0
3983          * of an EPT paging-structure entry is 110b (write/execute).
3984          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3985          * spte.
3986          */
3987         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3988 }
3989
3990 /*
3991  * Sets up the vmcs for emulated real mode.
3992  */
3993 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3994 {
3995 #ifdef CONFIG_X86_64
3996         unsigned long a;
3997 #endif
3998         int i;
3999
4000         /* I/O */
4001         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4002         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4003
4004         if (cpu_has_vmx_msr_bitmap())
4005                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4006
4007         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4008
4009         /* Control */
4010         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
4011                 vmcs_config.pin_based_exec_ctrl);
4012
4013         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4014
4015         if (cpu_has_secondary_exec_ctrls()) {
4016                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4017                                 vmx_secondary_exec_control(vmx));
4018         }
4019
4020         if (enable_apicv_reg_vid) {
4021                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4022                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4023                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4024                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4025
4026                 vmcs_write16(GUEST_INTR_STATUS, 0);
4027         }
4028
4029         if (ple_gap) {
4030                 vmcs_write32(PLE_GAP, ple_gap);
4031                 vmcs_write32(PLE_WINDOW, ple_window);
4032         }
4033
4034         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4035         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4036         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4037
4038         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4039         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4040         vmx_set_constant_host_state();
4041 #ifdef CONFIG_X86_64
4042         rdmsrl(MSR_FS_BASE, a);
4043         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4044         rdmsrl(MSR_GS_BASE, a);
4045         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4046 #else
4047         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4048         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4049 #endif
4050
4051         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4052         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4053         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4054         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4055         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4056
4057         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4058                 u32 msr_low, msr_high;
4059                 u64 host_pat;
4060                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4061                 host_pat = msr_low | ((u64) msr_high << 32);
4062                 /* Write the default value follow host pat */
4063                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4064                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4065                 vmx->vcpu.arch.pat = host_pat;
4066         }
4067
4068         for (i = 0; i < NR_VMX_MSR; ++i) {
4069                 u32 index = vmx_msr_index[i];
4070                 u32 data_low, data_high;
4071                 int j = vmx->nmsrs;
4072
4073                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4074                         continue;
4075                 if (wrmsr_safe(index, data_low, data_high) < 0)
4076                         continue;
4077                 vmx->guest_msrs[j].index = i;
4078                 vmx->guest_msrs[j].data = 0;
4079                 vmx->guest_msrs[j].mask = -1ull;
4080                 ++vmx->nmsrs;
4081         }
4082
4083         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4084
4085         /* 22.2.1, 20.8.1 */
4086         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4087
4088         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4089         set_cr4_guest_host_mask(vmx);
4090
4091         return 0;
4092 }
4093
4094 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4095 {
4096         struct vcpu_vmx *vmx = to_vmx(vcpu);
4097         u64 msr;
4098         int ret;
4099
4100         vmx->rmode.vm86_active = 0;
4101
4102         vmx->soft_vnmi_blocked = 0;
4103
4104         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4105         kvm_set_cr8(&vmx->vcpu, 0);
4106         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4107         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4108                 msr |= MSR_IA32_APICBASE_BSP;
4109         kvm_set_apic_base(&vmx->vcpu, msr);
4110
4111         vmx_segment_cache_clear(vmx);
4112
4113         seg_setup(VCPU_SREG_CS);
4114         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4115                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4116         else {
4117                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
4118                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
4119         }
4120
4121         seg_setup(VCPU_SREG_DS);
4122         seg_setup(VCPU_SREG_ES);
4123         seg_setup(VCPU_SREG_FS);
4124         seg_setup(VCPU_SREG_GS);
4125         seg_setup(VCPU_SREG_SS);
4126
4127         vmcs_write16(GUEST_TR_SELECTOR, 0);
4128         vmcs_writel(GUEST_TR_BASE, 0);
4129         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4130         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4131
4132         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4133         vmcs_writel(GUEST_LDTR_BASE, 0);
4134         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4135         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4136
4137         vmcs_write32(GUEST_SYSENTER_CS, 0);
4138         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4139         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4140
4141         vmcs_writel(GUEST_RFLAGS, 0x02);
4142         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4143                 kvm_rip_write(vcpu, 0xfff0);
4144         else
4145                 kvm_rip_write(vcpu, 0);
4146
4147         vmcs_writel(GUEST_GDTR_BASE, 0);
4148         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4149
4150         vmcs_writel(GUEST_IDTR_BASE, 0);
4151         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4152
4153         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4154         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4155         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4156
4157         /* Special registers */
4158         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4159
4160         setup_msrs(vmx);
4161
4162         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4163
4164         if (cpu_has_vmx_tpr_shadow()) {
4165                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4166                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4167                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4168                                      __pa(vmx->vcpu.arch.apic->regs));
4169                 vmcs_write32(TPR_THRESHOLD, 0);
4170         }
4171
4172         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4173                 vmcs_write64(APIC_ACCESS_ADDR,
4174                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4175
4176         if (vmx->vpid != 0)
4177                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4178
4179         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4180         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4181         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4182         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4183         vmx_set_cr4(&vmx->vcpu, 0);
4184         vmx_set_efer(&vmx->vcpu, 0);
4185         vmx_fpu_activate(&vmx->vcpu);
4186         update_exception_bitmap(&vmx->vcpu);
4187
4188         vpid_sync_context(vmx);
4189
4190         ret = 0;
4191
4192         return ret;
4193 }
4194
4195 /*
4196  * In nested virtualization, check if L1 asked to exit on external interrupts.
4197  * For most existing hypervisors, this will always return true.
4198  */
4199 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4200 {
4201         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4202                 PIN_BASED_EXT_INTR_MASK;
4203 }
4204
4205 static void enable_irq_window(struct kvm_vcpu *vcpu)
4206 {
4207         u32 cpu_based_vm_exec_control;
4208         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4209                 /*
4210                  * We get here if vmx_interrupt_allowed() said we can't
4211                  * inject to L1 now because L2 must run. Ask L2 to exit
4212                  * right after entry, so we can inject to L1 more promptly.
4213                  */
4214                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4215                 return;
4216         }
4217
4218         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4219         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4220         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4221 }
4222
4223 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4224 {
4225         u32 cpu_based_vm_exec_control;
4226
4227         if (!cpu_has_virtual_nmis()) {
4228                 enable_irq_window(vcpu);
4229                 return;
4230         }
4231
4232         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4233                 enable_irq_window(vcpu);
4234                 return;
4235         }
4236         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4237         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4238         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4239 }
4240
4241 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4242 {
4243         struct vcpu_vmx *vmx = to_vmx(vcpu);
4244         uint32_t intr;
4245         int irq = vcpu->arch.interrupt.nr;
4246
4247         trace_kvm_inj_virq(irq);
4248
4249         ++vcpu->stat.irq_injections;
4250         if (vmx->rmode.vm86_active) {
4251                 int inc_eip = 0;
4252                 if (vcpu->arch.interrupt.soft)
4253                         inc_eip = vcpu->arch.event_exit_inst_len;
4254                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4255                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4256                 return;
4257         }
4258         intr = irq | INTR_INFO_VALID_MASK;
4259         if (vcpu->arch.interrupt.soft) {
4260                 intr |= INTR_TYPE_SOFT_INTR;
4261                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4262                              vmx->vcpu.arch.event_exit_inst_len);
4263         } else
4264                 intr |= INTR_TYPE_EXT_INTR;
4265         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4266 }
4267
4268 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4269 {
4270         struct vcpu_vmx *vmx = to_vmx(vcpu);
4271
4272         if (is_guest_mode(vcpu))
4273                 return;
4274
4275         if (!cpu_has_virtual_nmis()) {
4276                 /*
4277                  * Tracking the NMI-blocked state in software is built upon
4278                  * finding the next open IRQ window. This, in turn, depends on
4279                  * well-behaving guests: They have to keep IRQs disabled at
4280                  * least as long as the NMI handler runs. Otherwise we may
4281                  * cause NMI nesting, maybe breaking the guest. But as this is
4282                  * highly unlikely, we can live with the residual risk.
4283                  */
4284                 vmx->soft_vnmi_blocked = 1;
4285                 vmx->vnmi_blocked_time = 0;
4286         }
4287
4288         ++vcpu->stat.nmi_injections;
4289         vmx->nmi_known_unmasked = false;
4290         if (vmx->rmode.vm86_active) {
4291                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4292                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4293                 return;
4294         }
4295         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4296                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4297 }
4298
4299 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4300 {
4301         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4302                 return 0;
4303
4304         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4305                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4306                    | GUEST_INTR_STATE_NMI));
4307 }
4308
4309 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4310 {
4311         if (!cpu_has_virtual_nmis())
4312                 return to_vmx(vcpu)->soft_vnmi_blocked;
4313         if (to_vmx(vcpu)->nmi_known_unmasked)
4314                 return false;
4315         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4316 }
4317
4318 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4319 {
4320         struct vcpu_vmx *vmx = to_vmx(vcpu);
4321
4322         if (!cpu_has_virtual_nmis()) {
4323                 if (vmx->soft_vnmi_blocked != masked) {
4324                         vmx->soft_vnmi_blocked = masked;
4325                         vmx->vnmi_blocked_time = 0;
4326                 }
4327         } else {
4328                 vmx->nmi_known_unmasked = !masked;
4329                 if (masked)
4330                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4331                                       GUEST_INTR_STATE_NMI);
4332                 else
4333                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4334                                         GUEST_INTR_STATE_NMI);
4335         }
4336 }
4337
4338 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4339 {
4340         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4341                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4342                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4343                     (vmcs12->idt_vectoring_info_field &
4344                      VECTORING_INFO_VALID_MASK))
4345                         return 0;
4346                 nested_vmx_vmexit(vcpu);
4347                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4348                 vmcs12->vm_exit_intr_info = 0;
4349                 /* fall through to normal code, but now in L1, not L2 */
4350         }
4351
4352         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4353                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4354                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4355 }
4356
4357 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4358 {
4359         int ret;
4360         struct kvm_userspace_memory_region tss_mem = {
4361                 .slot = TSS_PRIVATE_MEMSLOT,
4362                 .guest_phys_addr = addr,
4363                 .memory_size = PAGE_SIZE * 3,
4364                 .flags = 0,
4365         };
4366
4367         ret = kvm_set_memory_region(kvm, &tss_mem);
4368         if (ret)
4369                 return ret;
4370         kvm->arch.tss_addr = addr;
4371         if (!init_rmode_tss(kvm))
4372                 return  -ENOMEM;
4373
4374         return 0;
4375 }
4376
4377 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4378 {
4379         switch (vec) {
4380         case BP_VECTOR:
4381                 /*
4382                  * Update instruction length as we may reinject the exception
4383                  * from user space while in guest debugging mode.
4384                  */
4385                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4386                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4387                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4388                         return false;
4389                 /* fall through */
4390         case DB_VECTOR:
4391                 if (vcpu->guest_debug &
4392                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4393                         return false;
4394                 /* fall through */
4395         case DE_VECTOR:
4396         case OF_VECTOR:
4397         case BR_VECTOR:
4398         case UD_VECTOR:
4399         case DF_VECTOR:
4400         case SS_VECTOR:
4401         case GP_VECTOR:
4402         case MF_VECTOR:
4403                 return true;
4404         break;
4405         }
4406         return false;
4407 }
4408
4409 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4410                                   int vec, u32 err_code)
4411 {
4412         /*
4413          * Instruction with address size override prefix opcode 0x67
4414          * Cause the #SS fault with 0 error code in VM86 mode.
4415          */
4416         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4417                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4418                         if (vcpu->arch.halt_request) {
4419                                 vcpu->arch.halt_request = 0;
4420                                 return kvm_emulate_halt(vcpu);
4421                         }
4422                         return 1;
4423                 }
4424                 return 0;
4425         }
4426
4427         /*
4428          * Forward all other exceptions that are valid in real mode.
4429          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4430          *        the required debugging infrastructure rework.
4431          */
4432         kvm_queue_exception(vcpu, vec);
4433         return 1;
4434 }
4435
4436 /*
4437  * Trigger machine check on the host. We assume all the MSRs are already set up
4438  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4439  * We pass a fake environment to the machine check handler because we want
4440  * the guest to be always treated like user space, no matter what context
4441  * it used internally.
4442  */
4443 static void kvm_machine_check(void)
4444 {
4445 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4446         struct pt_regs regs = {
4447                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4448                 .flags = X86_EFLAGS_IF,
4449         };
4450
4451         do_machine_check(&regs, 0);
4452 #endif
4453 }
4454
4455 static int handle_machine_check(struct kvm_vcpu *vcpu)
4456 {
4457         /* already handled by vcpu_run */
4458         return 1;
4459 }
4460
4461 static int handle_exception(struct kvm_vcpu *vcpu)
4462 {
4463         struct vcpu_vmx *vmx = to_vmx(vcpu);
4464         struct kvm_run *kvm_run = vcpu->run;
4465         u32 intr_info, ex_no, error_code;
4466         unsigned long cr2, rip, dr6;
4467         u32 vect_info;
4468         enum emulation_result er;
4469
4470         vect_info = vmx->idt_vectoring_info;
4471         intr_info = vmx->exit_intr_info;
4472
4473         if (is_machine_check(intr_info))
4474                 return handle_machine_check(vcpu);
4475
4476         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4477                 return 1;  /* already handled by vmx_vcpu_run() */
4478
4479         if (is_no_device(intr_info)) {
4480                 vmx_fpu_activate(vcpu);
4481                 return 1;
4482         }
4483
4484         if (is_invalid_opcode(intr_info)) {
4485                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4486                 if (er != EMULATE_DONE)
4487                         kvm_queue_exception(vcpu, UD_VECTOR);
4488                 return 1;
4489         }
4490
4491         error_code = 0;
4492         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4493                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4494
4495         /*
4496          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4497          * MMIO, it is better to report an internal error.
4498          * See the comments in vmx_handle_exit.
4499          */
4500         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4501             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4502                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4503                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4504                 vcpu->run->internal.ndata = 2;
4505                 vcpu->run->internal.data[0] = vect_info;
4506                 vcpu->run->internal.data[1] = intr_info;
4507                 return 0;
4508         }
4509
4510         if (is_page_fault(intr_info)) {
4511                 /* EPT won't cause page fault directly */
4512                 BUG_ON(enable_ept);
4513                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4514                 trace_kvm_page_fault(cr2, error_code);
4515
4516                 if (kvm_event_needs_reinjection(vcpu))
4517                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4518                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4519         }
4520
4521         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4522
4523         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4524                 return handle_rmode_exception(vcpu, ex_no, error_code);
4525
4526         switch (ex_no) {
4527         case DB_VECTOR:
4528                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4529                 if (!(vcpu->guest_debug &
4530                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4531                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4532                         kvm_queue_exception(vcpu, DB_VECTOR);
4533                         return 1;
4534                 }
4535                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4536                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4537                 /* fall through */
4538         case BP_VECTOR:
4539                 /*
4540                  * Update instruction length as we may reinject #BP from
4541                  * user space while in guest debugging mode. Reading it for
4542                  * #DB as well causes no harm, it is not used in that case.
4543                  */
4544                 vmx->vcpu.arch.event_exit_inst_len =
4545                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4546                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4547                 rip = kvm_rip_read(vcpu);
4548                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4549                 kvm_run->debug.arch.exception = ex_no;
4550                 break;
4551         default:
4552                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4553                 kvm_run->ex.exception = ex_no;
4554                 kvm_run->ex.error_code = error_code;
4555                 break;
4556         }
4557         return 0;
4558 }
4559
4560 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4561 {
4562         ++vcpu->stat.irq_exits;
4563         return 1;
4564 }
4565
4566 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4567 {
4568         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4569         return 0;
4570 }
4571
4572 static int handle_io(struct kvm_vcpu *vcpu)
4573 {
4574         unsigned long exit_qualification;
4575         int size, in, string;
4576         unsigned port;
4577
4578         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4579         string = (exit_qualification & 16) != 0;
4580         in = (exit_qualification & 8) != 0;
4581
4582         ++vcpu->stat.io_exits;
4583
4584         if (string || in)
4585                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4586
4587         port = exit_qualification >> 16;
4588         size = (exit_qualification & 7) + 1;
4589         skip_emulated_instruction(vcpu);
4590
4591         return kvm_fast_pio_out(vcpu, size, port);
4592 }
4593
4594 static void
4595 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4596 {
4597         /*
4598          * Patch in the VMCALL instruction:
4599          */
4600         hypercall[0] = 0x0f;
4601         hypercall[1] = 0x01;
4602         hypercall[2] = 0xc1;
4603 }
4604
4605 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4606 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4607 {
4608         if (to_vmx(vcpu)->nested.vmxon &&
4609             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4610                 return 1;
4611
4612         if (is_guest_mode(vcpu)) {
4613                 /*
4614                  * We get here when L2 changed cr0 in a way that did not change
4615                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4616                  * but did change L0 shadowed bits. This can currently happen
4617                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4618                  * loading) while pretending to allow the guest to change it.
4619                  */
4620                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4621                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4622                         return 1;
4623                 vmcs_writel(CR0_READ_SHADOW, val);
4624                 return 0;
4625         } else
4626                 return kvm_set_cr0(vcpu, val);
4627 }
4628
4629 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4630 {
4631         if (is_guest_mode(vcpu)) {
4632                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4633                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4634                         return 1;
4635                 vmcs_writel(CR4_READ_SHADOW, val);
4636                 return 0;
4637         } else
4638                 return kvm_set_cr4(vcpu, val);
4639 }
4640
4641 /* called to set cr0 as approriate for clts instruction exit. */
4642 static void handle_clts(struct kvm_vcpu *vcpu)
4643 {
4644         if (is_guest_mode(vcpu)) {
4645                 /*
4646                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4647                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4648                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4649                  */
4650                 vmcs_writel(CR0_READ_SHADOW,
4651                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4652                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4653         } else
4654                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4655 }
4656
4657 static int handle_cr(struct kvm_vcpu *vcpu)
4658 {
4659         unsigned long exit_qualification, val;
4660         int cr;
4661         int reg;
4662         int err;
4663
4664         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4665         cr = exit_qualification & 15;
4666         reg = (exit_qualification >> 8) & 15;
4667         switch ((exit_qualification >> 4) & 3) {
4668         case 0: /* mov to cr */
4669                 val = kvm_register_read(vcpu, reg);
4670                 trace_kvm_cr_write(cr, val);
4671                 switch (cr) {
4672                 case 0:
4673                         err = handle_set_cr0(vcpu, val);
4674                         kvm_complete_insn_gp(vcpu, err);
4675                         return 1;
4676                 case 3:
4677                         err = kvm_set_cr3(vcpu, val);
4678                         kvm_complete_insn_gp(vcpu, err);
4679                         return 1;
4680                 case 4:
4681                         err = handle_set_cr4(vcpu, val);
4682                         kvm_complete_insn_gp(vcpu, err);
4683                         return 1;
4684                 case 8: {
4685                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4686                                 u8 cr8 = kvm_register_read(vcpu, reg);
4687                                 err = kvm_set_cr8(vcpu, cr8);
4688                                 kvm_complete_insn_gp(vcpu, err);
4689                                 if (irqchip_in_kernel(vcpu->kvm))
4690                                         return 1;
4691                                 if (cr8_prev <= cr8)
4692                                         return 1;
4693                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4694                                 return 0;
4695                         }
4696                 }
4697                 break;
4698         case 2: /* clts */
4699                 handle_clts(vcpu);
4700                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4701                 skip_emulated_instruction(vcpu);
4702                 vmx_fpu_activate(vcpu);
4703                 return 1;
4704         case 1: /*mov from cr*/
4705                 switch (cr) {
4706                 case 3:
4707                         val = kvm_read_cr3(vcpu);
4708                         kvm_register_write(vcpu, reg, val);
4709                         trace_kvm_cr_read(cr, val);
4710                         skip_emulated_instruction(vcpu);
4711                         return 1;
4712                 case 8:
4713                         val = kvm_get_cr8(vcpu);
4714                         kvm_register_write(vcpu, reg, val);
4715                         trace_kvm_cr_read(cr, val);
4716                         skip_emulated_instruction(vcpu);
4717                         return 1;
4718                 }
4719                 break;
4720         case 3: /* lmsw */
4721                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4722                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4723                 kvm_lmsw(vcpu, val);
4724
4725                 skip_emulated_instruction(vcpu);
4726                 return 1;
4727         default:
4728                 break;
4729         }
4730         vcpu->run->exit_reason = 0;
4731         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4732                (int)(exit_qualification >> 4) & 3, cr);
4733         return 0;
4734 }
4735
4736 static int handle_dr(struct kvm_vcpu *vcpu)
4737 {
4738         unsigned long exit_qualification;
4739         int dr, reg;
4740
4741         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4742         if (!kvm_require_cpl(vcpu, 0))
4743                 return 1;
4744         dr = vmcs_readl(GUEST_DR7);
4745         if (dr & DR7_GD) {
4746                 /*
4747                  * As the vm-exit takes precedence over the debug trap, we
4748                  * need to emulate the latter, either for the host or the
4749                  * guest debugging itself.
4750                  */
4751                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4752                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4753                         vcpu->run->debug.arch.dr7 = dr;
4754                         vcpu->run->debug.arch.pc =
4755                                 vmcs_readl(GUEST_CS_BASE) +
4756                                 vmcs_readl(GUEST_RIP);
4757                         vcpu->run->debug.arch.exception = DB_VECTOR;
4758                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4759                         return 0;
4760                 } else {
4761                         vcpu->arch.dr7 &= ~DR7_GD;
4762                         vcpu->arch.dr6 |= DR6_BD;
4763                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4764                         kvm_queue_exception(vcpu, DB_VECTOR);
4765                         return 1;
4766                 }
4767         }
4768
4769         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4770         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4771         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4772         if (exit_qualification & TYPE_MOV_FROM_DR) {
4773                 unsigned long val;
4774                 if (!kvm_get_dr(vcpu, dr, &val))
4775                         kvm_register_write(vcpu, reg, val);
4776         } else
4777                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4778         skip_emulated_instruction(vcpu);
4779         return 1;
4780 }
4781
4782 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4783 {
4784         vmcs_writel(GUEST_DR7, val);
4785 }
4786
4787 static int handle_cpuid(struct kvm_vcpu *vcpu)
4788 {
4789         kvm_emulate_cpuid(vcpu);
4790         return 1;
4791 }
4792
4793 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4794 {
4795         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4796         u64 data;
4797
4798         if (vmx_get_msr(vcpu, ecx, &data)) {
4799                 trace_kvm_msr_read_ex(ecx);
4800                 kvm_inject_gp(vcpu, 0);
4801                 return 1;
4802         }
4803
4804         trace_kvm_msr_read(ecx, data);
4805
4806         /* FIXME: handling of bits 32:63 of rax, rdx */
4807         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4808         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4809         skip_emulated_instruction(vcpu);
4810         return 1;
4811 }
4812
4813 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4814 {
4815         struct msr_data msr;
4816         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4817         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4818                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4819
4820         msr.data = data;
4821         msr.index = ecx;
4822         msr.host_initiated = false;
4823         if (vmx_set_msr(vcpu, &msr) != 0) {
4824                 trace_kvm_msr_write_ex(ecx, data);
4825                 kvm_inject_gp(vcpu, 0);
4826                 return 1;
4827         }
4828
4829         trace_kvm_msr_write(ecx, data);
4830         skip_emulated_instruction(vcpu);
4831         return 1;
4832 }
4833
4834 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4835 {
4836         kvm_make_request(KVM_REQ_EVENT, vcpu);
4837         return 1;
4838 }
4839
4840 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4841 {
4842         u32 cpu_based_vm_exec_control;
4843
4844         /* clear pending irq */
4845         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4846         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4847         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4848
4849         kvm_make_request(KVM_REQ_EVENT, vcpu);
4850
4851         ++vcpu->stat.irq_window_exits;
4852
4853         /*
4854          * If the user space waits to inject interrupts, exit as soon as
4855          * possible
4856          */
4857         if (!irqchip_in_kernel(vcpu->kvm) &&
4858             vcpu->run->request_interrupt_window &&
4859             !kvm_cpu_has_interrupt(vcpu)) {
4860                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4861                 return 0;
4862         }
4863         return 1;
4864 }
4865
4866 static int handle_halt(struct kvm_vcpu *vcpu)
4867 {
4868         skip_emulated_instruction(vcpu);
4869         return kvm_emulate_halt(vcpu);
4870 }
4871
4872 static int handle_vmcall(struct kvm_vcpu *vcpu)
4873 {
4874         skip_emulated_instruction(vcpu);
4875         kvm_emulate_hypercall(vcpu);
4876         return 1;
4877 }
4878
4879 static int handle_invd(struct kvm_vcpu *vcpu)
4880 {
4881         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4882 }
4883
4884 static int handle_invlpg(struct kvm_vcpu *vcpu)
4885 {
4886         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4887
4888         kvm_mmu_invlpg(vcpu, exit_qualification);
4889         skip_emulated_instruction(vcpu);
4890         return 1;
4891 }
4892
4893 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4894 {
4895         int err;
4896
4897         err = kvm_rdpmc(vcpu);
4898         kvm_complete_insn_gp(vcpu, err);
4899
4900         return 1;
4901 }
4902
4903 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4904 {
4905         skip_emulated_instruction(vcpu);
4906         kvm_emulate_wbinvd(vcpu);
4907         return 1;
4908 }
4909
4910 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4911 {
4912         u64 new_bv = kvm_read_edx_eax(vcpu);
4913         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4914
4915         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4916                 skip_emulated_instruction(vcpu);
4917         return 1;
4918 }
4919
4920 static int handle_apic_access(struct kvm_vcpu *vcpu)
4921 {
4922         if (likely(fasteoi)) {
4923                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4924                 int access_type, offset;
4925
4926                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4927                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4928                 /*
4929                  * Sane guest uses MOV to write EOI, with written value
4930                  * not cared. So make a short-circuit here by avoiding
4931                  * heavy instruction emulation.
4932                  */
4933                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4934                     (offset == APIC_EOI)) {
4935                         kvm_lapic_set_eoi(vcpu);
4936                         skip_emulated_instruction(vcpu);
4937                         return 1;
4938                 }
4939         }
4940         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4941 }
4942
4943 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4944 {
4945         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4946         int vector = exit_qualification & 0xff;
4947
4948         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4949         kvm_apic_set_eoi_accelerated(vcpu, vector);
4950         return 1;
4951 }
4952
4953 static int handle_apic_write(struct kvm_vcpu *vcpu)
4954 {
4955         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4956         u32 offset = exit_qualification & 0xfff;
4957
4958         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4959         kvm_apic_write_nodecode(vcpu, offset);
4960         return 1;
4961 }
4962
4963 static int handle_task_switch(struct kvm_vcpu *vcpu)
4964 {
4965         struct vcpu_vmx *vmx = to_vmx(vcpu);
4966         unsigned long exit_qualification;
4967         bool has_error_code = false;
4968         u32 error_code = 0;
4969         u16 tss_selector;
4970         int reason, type, idt_v, idt_index;
4971
4972         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4973         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4974         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4975
4976         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4977
4978         reason = (u32)exit_qualification >> 30;
4979         if (reason == TASK_SWITCH_GATE && idt_v) {
4980                 switch (type) {
4981                 case INTR_TYPE_NMI_INTR:
4982                         vcpu->arch.nmi_injected = false;
4983                         vmx_set_nmi_mask(vcpu, true);
4984                         break;
4985                 case INTR_TYPE_EXT_INTR:
4986                 case INTR_TYPE_SOFT_INTR:
4987                         kvm_clear_interrupt_queue(vcpu);
4988                         break;
4989                 case INTR_TYPE_HARD_EXCEPTION:
4990                         if (vmx->idt_vectoring_info &
4991                             VECTORING_INFO_DELIVER_CODE_MASK) {
4992                                 has_error_code = true;
4993                                 error_code =
4994                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4995                         }
4996                         /* fall through */
4997                 case INTR_TYPE_SOFT_EXCEPTION:
4998                         kvm_clear_exception_queue(vcpu);
4999                         break;
5000                 default:
5001                         break;
5002                 }
5003         }
5004         tss_selector = exit_qualification;
5005
5006         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5007                        type != INTR_TYPE_EXT_INTR &&
5008                        type != INTR_TYPE_NMI_INTR))
5009                 skip_emulated_instruction(vcpu);
5010
5011         if (kvm_task_switch(vcpu, tss_selector,
5012                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5013                             has_error_code, error_code) == EMULATE_FAIL) {
5014                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5015                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5016                 vcpu->run->internal.ndata = 0;
5017                 return 0;
5018         }
5019
5020         /* clear all local breakpoint enable flags */
5021         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5022
5023         /*
5024          * TODO: What about debug traps on tss switch?
5025          *       Are we supposed to inject them and update dr6?
5026          */
5027
5028         return 1;
5029 }
5030
5031 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5032 {
5033         unsigned long exit_qualification;
5034         gpa_t gpa;
5035         u32 error_code;
5036         int gla_validity;
5037
5038         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5039
5040         gla_validity = (exit_qualification >> 7) & 0x3;
5041         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5042                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5043                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5044                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5045                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5046                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5047                         (long unsigned int)exit_qualification);
5048                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5049                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5050                 return 0;
5051         }
5052
5053         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5054         trace_kvm_page_fault(gpa, exit_qualification);
5055
5056         /* It is a write fault? */
5057         error_code = exit_qualification & (1U << 1);
5058         /* ept page table is present? */
5059         error_code |= (exit_qualification >> 3) & 0x1;
5060
5061         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5062 }
5063
5064 static u64 ept_rsvd_mask(u64 spte, int level)
5065 {
5066         int i;
5067         u64 mask = 0;
5068
5069         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5070                 mask |= (1ULL << i);
5071
5072         if (level > 2)
5073                 /* bits 7:3 reserved */
5074                 mask |= 0xf8;
5075         else if (level == 2) {
5076                 if (spte & (1ULL << 7))
5077                         /* 2MB ref, bits 20:12 reserved */
5078                         mask |= 0x1ff000;
5079                 else
5080                         /* bits 6:3 reserved */
5081                         mask |= 0x78;
5082         }
5083
5084         return mask;
5085 }
5086
5087 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5088                                        int level)
5089 {
5090         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5091
5092         /* 010b (write-only) */
5093         WARN_ON((spte & 0x7) == 0x2);
5094
5095         /* 110b (write/execute) */
5096         WARN_ON((spte & 0x7) == 0x6);
5097
5098         /* 100b (execute-only) and value not supported by logical processor */
5099         if (!cpu_has_vmx_ept_execute_only())
5100                 WARN_ON((spte & 0x7) == 0x4);
5101
5102         /* not 000b */
5103         if ((spte & 0x7)) {
5104                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5105
5106                 if (rsvd_bits != 0) {
5107                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5108                                          __func__, rsvd_bits);
5109                         WARN_ON(1);
5110                 }
5111
5112                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5113                         u64 ept_mem_type = (spte & 0x38) >> 3;
5114
5115                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5116                             ept_mem_type == 7) {
5117                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5118                                                 __func__, ept_mem_type);
5119                                 WARN_ON(1);
5120                         }
5121                 }
5122         }
5123 }
5124
5125 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5126 {
5127         u64 sptes[4];
5128         int nr_sptes, i, ret;
5129         gpa_t gpa;
5130
5131         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5132
5133         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5134         if (likely(ret == 1))
5135                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5136                                               EMULATE_DONE;
5137         if (unlikely(!ret))
5138                 return 1;
5139
5140         /* It is the real ept misconfig */
5141         printk(KERN_ERR "EPT: Misconfiguration.\n");
5142         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5143
5144         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5145
5146         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5147                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5148
5149         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5150         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5151
5152         return 0;
5153 }
5154
5155 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5156 {
5157         u32 cpu_based_vm_exec_control;
5158
5159         /* clear pending NMI */
5160         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5161         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5162         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5163         ++vcpu->stat.nmi_window_exits;
5164         kvm_make_request(KVM_REQ_EVENT, vcpu);
5165
5166         return 1;
5167 }
5168
5169 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5170 {
5171         struct vcpu_vmx *vmx = to_vmx(vcpu);
5172         enum emulation_result err = EMULATE_DONE;
5173         int ret = 1;
5174         u32 cpu_exec_ctrl;
5175         bool intr_window_requested;
5176         unsigned count = 130;
5177
5178         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5179         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5180
5181         while (!guest_state_valid(vcpu) && count-- != 0) {
5182                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5183                         return handle_interrupt_window(&vmx->vcpu);
5184
5185                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5186                         return 1;
5187
5188                 err = emulate_instruction(vcpu, 0);
5189
5190                 if (err == EMULATE_DO_MMIO) {
5191                         ret = 0;
5192                         goto out;
5193                 }
5194
5195                 if (err != EMULATE_DONE) {
5196                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5197                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5198                         vcpu->run->internal.ndata = 0;
5199                         return 0;
5200                 }
5201
5202                 if (signal_pending(current))
5203                         goto out;
5204                 if (need_resched())
5205                         schedule();
5206         }
5207
5208         vmx->emulation_required = emulation_required(vcpu);
5209 out:
5210         return ret;
5211 }
5212
5213 /*
5214  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5215  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5216  */
5217 static int handle_pause(struct kvm_vcpu *vcpu)
5218 {
5219         skip_emulated_instruction(vcpu);
5220         kvm_vcpu_on_spin(vcpu);
5221
5222         return 1;
5223 }
5224
5225 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5226 {
5227         kvm_queue_exception(vcpu, UD_VECTOR);
5228         return 1;
5229 }
5230
5231 /*
5232  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5233  * We could reuse a single VMCS for all the L2 guests, but we also want the
5234  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5235  * allows keeping them loaded on the processor, and in the future will allow
5236  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5237  * every entry if they never change.
5238  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5239  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5240  *
5241  * The following functions allocate and free a vmcs02 in this pool.
5242  */
5243
5244 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5245 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5246 {
5247         struct vmcs02_list *item;
5248         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5249                 if (item->vmptr == vmx->nested.current_vmptr) {
5250                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5251                         return &item->vmcs02;
5252                 }
5253
5254         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5255                 /* Recycle the least recently used VMCS. */
5256                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5257                         struct vmcs02_list, list);
5258                 item->vmptr = vmx->nested.current_vmptr;
5259                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5260                 return &item->vmcs02;
5261         }
5262
5263         /* Create a new VMCS */
5264         item = (struct vmcs02_list *)
5265                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5266         if (!item)
5267                 return NULL;
5268         item->vmcs02.vmcs = alloc_vmcs();
5269         if (!item->vmcs02.vmcs) {
5270                 kfree(item);
5271                 return NULL;
5272         }
5273         loaded_vmcs_init(&item->vmcs02);
5274         item->vmptr = vmx->nested.current_vmptr;
5275         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5276         vmx->nested.vmcs02_num++;
5277         return &item->vmcs02;
5278 }
5279
5280 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5281 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5282 {
5283         struct vmcs02_list *item;
5284         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5285                 if (item->vmptr == vmptr) {
5286                         free_loaded_vmcs(&item->vmcs02);
5287                         list_del(&item->list);
5288                         kfree(item);
5289                         vmx->nested.vmcs02_num--;
5290                         return;
5291                 }
5292 }
5293
5294 /*
5295  * Free all VMCSs saved for this vcpu, except the one pointed by
5296  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5297  * currently used, if running L2), and vmcs01 when running L2.
5298  */
5299 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5300 {
5301         struct vmcs02_list *item, *n;
5302         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5303                 if (vmx->loaded_vmcs != &item->vmcs02)
5304                         free_loaded_vmcs(&item->vmcs02);
5305                 list_del(&item->list);
5306                 kfree(item);
5307         }
5308         vmx->nested.vmcs02_num = 0;
5309
5310         if (vmx->loaded_vmcs != &vmx->vmcs01)
5311                 free_loaded_vmcs(&vmx->vmcs01);
5312 }
5313
5314 /*
5315  * Emulate the VMXON instruction.
5316  * Currently, we just remember that VMX is active, and do not save or even
5317  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5318  * do not currently need to store anything in that guest-allocated memory
5319  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5320  * argument is different from the VMXON pointer (which the spec says they do).
5321  */
5322 static int handle_vmon(struct kvm_vcpu *vcpu)
5323 {
5324         struct kvm_segment cs;
5325         struct vcpu_vmx *vmx = to_vmx(vcpu);
5326
5327         /* The Intel VMX Instruction Reference lists a bunch of bits that
5328          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5329          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5330          * Otherwise, we should fail with #UD. We test these now:
5331          */
5332         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5333             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5334             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5335                 kvm_queue_exception(vcpu, UD_VECTOR);
5336                 return 1;
5337         }
5338
5339         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5340         if (is_long_mode(vcpu) && !cs.l) {
5341                 kvm_queue_exception(vcpu, UD_VECTOR);
5342                 return 1;
5343         }
5344
5345         if (vmx_get_cpl(vcpu)) {
5346                 kvm_inject_gp(vcpu, 0);
5347                 return 1;
5348         }
5349
5350         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5351         vmx->nested.vmcs02_num = 0;
5352
5353         vmx->nested.vmxon = true;
5354
5355         skip_emulated_instruction(vcpu);
5356         return 1;
5357 }
5358
5359 /*
5360  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5361  * for running VMX instructions (except VMXON, whose prerequisites are
5362  * slightly different). It also specifies what exception to inject otherwise.
5363  */
5364 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5365 {
5366         struct kvm_segment cs;
5367         struct vcpu_vmx *vmx = to_vmx(vcpu);
5368
5369         if (!vmx->nested.vmxon) {
5370                 kvm_queue_exception(vcpu, UD_VECTOR);
5371                 return 0;
5372         }
5373
5374         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5375         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5376             (is_long_mode(vcpu) && !cs.l)) {
5377                 kvm_queue_exception(vcpu, UD_VECTOR);
5378                 return 0;
5379         }
5380
5381         if (vmx_get_cpl(vcpu)) {
5382                 kvm_inject_gp(vcpu, 0);
5383                 return 0;
5384         }
5385
5386         return 1;
5387 }
5388
5389 /*
5390  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5391  * just stops using VMX.
5392  */
5393 static void free_nested(struct vcpu_vmx *vmx)
5394 {
5395         if (!vmx->nested.vmxon)
5396                 return;
5397         vmx->nested.vmxon = false;
5398         if (vmx->nested.current_vmptr != -1ull) {
5399                 kunmap(vmx->nested.current_vmcs12_page);
5400                 nested_release_page(vmx->nested.current_vmcs12_page);
5401                 vmx->nested.current_vmptr = -1ull;
5402                 vmx->nested.current_vmcs12 = NULL;
5403         }
5404         /* Unpin physical memory we referred to in current vmcs02 */
5405         if (vmx->nested.apic_access_page) {
5406                 nested_release_page(vmx->nested.apic_access_page);
5407                 vmx->nested.apic_access_page = 0;
5408         }
5409
5410         nested_free_all_saved_vmcss(vmx);
5411 }
5412
5413 /* Emulate the VMXOFF instruction */
5414 static int handle_vmoff(struct kvm_vcpu *vcpu)
5415 {
5416         if (!nested_vmx_check_permission(vcpu))
5417                 return 1;
5418         free_nested(to_vmx(vcpu));
5419         skip_emulated_instruction(vcpu);
5420         return 1;
5421 }
5422
5423 /*
5424  * Decode the memory-address operand of a vmx instruction, as recorded on an
5425  * exit caused by such an instruction (run by a guest hypervisor).
5426  * On success, returns 0. When the operand is invalid, returns 1 and throws
5427  * #UD or #GP.
5428  */
5429 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5430                                  unsigned long exit_qualification,
5431                                  u32 vmx_instruction_info, gva_t *ret)
5432 {
5433         /*
5434          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5435          * Execution", on an exit, vmx_instruction_info holds most of the
5436          * addressing components of the operand. Only the displacement part
5437          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5438          * For how an actual address is calculated from all these components,
5439          * refer to Vol. 1, "Operand Addressing".
5440          */
5441         int  scaling = vmx_instruction_info & 3;
5442         int  addr_size = (vmx_instruction_info >> 7) & 7;
5443         bool is_reg = vmx_instruction_info & (1u << 10);
5444         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5445         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5446         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5447         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5448         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5449
5450         if (is_reg) {
5451                 kvm_queue_exception(vcpu, UD_VECTOR);
5452                 return 1;
5453         }
5454
5455         /* Addr = segment_base + offset */
5456         /* offset = base + [index * scale] + displacement */
5457         *ret = vmx_get_segment_base(vcpu, seg_reg);
5458         if (base_is_valid)
5459                 *ret += kvm_register_read(vcpu, base_reg);
5460         if (index_is_valid)
5461                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5462         *ret += exit_qualification; /* holds the displacement */
5463
5464         if (addr_size == 1) /* 32 bit */
5465                 *ret &= 0xffffffff;
5466
5467         /*
5468          * TODO: throw #GP (and return 1) in various cases that the VM*
5469          * instructions require it - e.g., offset beyond segment limit,
5470          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5471          * address, and so on. Currently these are not checked.
5472          */
5473         return 0;
5474 }
5475
5476 /*
5477  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5478  * set the success or error code of an emulated VMX instruction, as specified
5479  * by Vol 2B, VMX Instruction Reference, "Conventions".
5480  */
5481 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5482 {
5483         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5484                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5485                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5486 }
5487
5488 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5489 {
5490         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5491                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5492                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5493                         | X86_EFLAGS_CF);
5494 }
5495
5496 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5497                                         u32 vm_instruction_error)
5498 {
5499         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5500                 /*
5501                  * failValid writes the error number to the current VMCS, which
5502                  * can't be done there isn't a current VMCS.
5503                  */
5504                 nested_vmx_failInvalid(vcpu);
5505                 return;
5506         }
5507         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5508                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5509                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5510                         | X86_EFLAGS_ZF);
5511         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5512 }
5513
5514 /* Emulate the VMCLEAR instruction */
5515 static int handle_vmclear(struct kvm_vcpu *vcpu)
5516 {
5517         struct vcpu_vmx *vmx = to_vmx(vcpu);
5518         gva_t gva;
5519         gpa_t vmptr;
5520         struct vmcs12 *vmcs12;
5521         struct page *page;
5522         struct x86_exception e;
5523
5524         if (!nested_vmx_check_permission(vcpu))
5525                 return 1;
5526
5527         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5528                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5529                 return 1;
5530
5531         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5532                                 sizeof(vmptr), &e)) {
5533                 kvm_inject_page_fault(vcpu, &e);
5534                 return 1;
5535         }
5536
5537         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5538                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5539                 skip_emulated_instruction(vcpu);
5540                 return 1;
5541         }
5542
5543         if (vmptr == vmx->nested.current_vmptr) {
5544                 kunmap(vmx->nested.current_vmcs12_page);
5545                 nested_release_page(vmx->nested.current_vmcs12_page);
5546                 vmx->nested.current_vmptr = -1ull;
5547                 vmx->nested.current_vmcs12 = NULL;
5548         }
5549
5550         page = nested_get_page(vcpu, vmptr);
5551         if (page == NULL) {
5552                 /*
5553                  * For accurate processor emulation, VMCLEAR beyond available
5554                  * physical memory should do nothing at all. However, it is
5555                  * possible that a nested vmx bug, not a guest hypervisor bug,
5556                  * resulted in this case, so let's shut down before doing any
5557                  * more damage:
5558                  */
5559                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5560                 return 1;
5561         }
5562         vmcs12 = kmap(page);
5563         vmcs12->launch_state = 0;
5564         kunmap(page);
5565         nested_release_page(page);
5566
5567         nested_free_vmcs02(vmx, vmptr);
5568
5569         skip_emulated_instruction(vcpu);
5570         nested_vmx_succeed(vcpu);
5571         return 1;
5572 }
5573
5574 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5575
5576 /* Emulate the VMLAUNCH instruction */
5577 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5578 {
5579         return nested_vmx_run(vcpu, true);
5580 }
5581
5582 /* Emulate the VMRESUME instruction */
5583 static int handle_vmresume(struct kvm_vcpu *vcpu)
5584 {
5585
5586         return nested_vmx_run(vcpu, false);
5587 }
5588
5589 enum vmcs_field_type {
5590         VMCS_FIELD_TYPE_U16 = 0,
5591         VMCS_FIELD_TYPE_U64 = 1,
5592         VMCS_FIELD_TYPE_U32 = 2,
5593         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5594 };
5595
5596 static inline int vmcs_field_type(unsigned long field)
5597 {
5598         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5599                 return VMCS_FIELD_TYPE_U32;
5600         return (field >> 13) & 0x3 ;
5601 }
5602
5603 static inline int vmcs_field_readonly(unsigned long field)
5604 {
5605         return (((field >> 10) & 0x3) == 1);
5606 }
5607
5608 /*
5609  * Read a vmcs12 field. Since these can have varying lengths and we return
5610  * one type, we chose the biggest type (u64) and zero-extend the return value
5611  * to that size. Note that the caller, handle_vmread, might need to use only
5612  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5613  * 64-bit fields are to be returned).
5614  */
5615 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5616                                         unsigned long field, u64 *ret)
5617 {
5618         short offset = vmcs_field_to_offset(field);
5619         char *p;
5620
5621         if (offset < 0)
5622                 return 0;
5623
5624         p = ((char *)(get_vmcs12(vcpu))) + offset;
5625
5626         switch (vmcs_field_type(field)) {
5627         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5628                 *ret = *((natural_width *)p);
5629                 return 1;
5630         case VMCS_FIELD_TYPE_U16:
5631                 *ret = *((u16 *)p);
5632                 return 1;
5633         case VMCS_FIELD_TYPE_U32:
5634                 *ret = *((u32 *)p);
5635                 return 1;
5636         case VMCS_FIELD_TYPE_U64:
5637                 *ret = *((u64 *)p);
5638                 return 1;
5639         default:
5640                 return 0; /* can never happen. */
5641         }
5642 }
5643
5644 /*
5645  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5646  * used before) all generate the same failure when it is missing.
5647  */
5648 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5649 {
5650         struct vcpu_vmx *vmx = to_vmx(vcpu);
5651         if (vmx->nested.current_vmptr == -1ull) {
5652                 nested_vmx_failInvalid(vcpu);
5653                 skip_emulated_instruction(vcpu);
5654                 return 0;
5655         }
5656         return 1;
5657 }
5658
5659 static int handle_vmread(struct kvm_vcpu *vcpu)
5660 {
5661         unsigned long field;
5662         u64 field_value;
5663         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5664         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5665         gva_t gva = 0;
5666
5667         if (!nested_vmx_check_permission(vcpu) ||
5668             !nested_vmx_check_vmcs12(vcpu))
5669                 return 1;
5670
5671         /* Decode instruction info and find the field to read */
5672         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5673         /* Read the field, zero-extended to a u64 field_value */
5674         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5675                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5676                 skip_emulated_instruction(vcpu);
5677                 return 1;
5678         }
5679         /*
5680          * Now copy part of this value to register or memory, as requested.
5681          * Note that the number of bits actually copied is 32 or 64 depending
5682          * on the guest's mode (32 or 64 bit), not on the given field's length.
5683          */
5684         if (vmx_instruction_info & (1u << 10)) {
5685                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5686                         field_value);
5687         } else {
5688                 if (get_vmx_mem_address(vcpu, exit_qualification,
5689                                 vmx_instruction_info, &gva))
5690                         return 1;
5691                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5692                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5693                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5694         }
5695
5696         nested_vmx_succeed(vcpu);
5697         skip_emulated_instruction(vcpu);
5698         return 1;
5699 }
5700
5701
5702 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5703 {
5704         unsigned long field;
5705         gva_t gva;
5706         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5707         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5708         char *p;
5709         short offset;
5710         /* The value to write might be 32 or 64 bits, depending on L1's long
5711          * mode, and eventually we need to write that into a field of several
5712          * possible lengths. The code below first zero-extends the value to 64
5713          * bit (field_value), and then copies only the approriate number of
5714          * bits into the vmcs12 field.
5715          */
5716         u64 field_value = 0;
5717         struct x86_exception e;
5718
5719         if (!nested_vmx_check_permission(vcpu) ||
5720             !nested_vmx_check_vmcs12(vcpu))
5721                 return 1;
5722
5723         if (vmx_instruction_info & (1u << 10))
5724                 field_value = kvm_register_read(vcpu,
5725                         (((vmx_instruction_info) >> 3) & 0xf));
5726         else {
5727                 if (get_vmx_mem_address(vcpu, exit_qualification,
5728                                 vmx_instruction_info, &gva))
5729                         return 1;
5730                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5731                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5732                         kvm_inject_page_fault(vcpu, &e);
5733                         return 1;
5734                 }
5735         }
5736
5737
5738         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5739         if (vmcs_field_readonly(field)) {
5740                 nested_vmx_failValid(vcpu,
5741                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5742                 skip_emulated_instruction(vcpu);
5743                 return 1;
5744         }
5745
5746         offset = vmcs_field_to_offset(field);
5747         if (offset < 0) {
5748                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5749                 skip_emulated_instruction(vcpu);
5750                 return 1;
5751         }
5752         p = ((char *) get_vmcs12(vcpu)) + offset;
5753
5754         switch (vmcs_field_type(field)) {
5755         case VMCS_FIELD_TYPE_U16:
5756                 *(u16 *)p = field_value;
5757                 break;
5758         case VMCS_FIELD_TYPE_U32:
5759                 *(u32 *)p = field_value;
5760                 break;
5761         case VMCS_FIELD_TYPE_U64:
5762                 *(u64 *)p = field_value;
5763                 break;
5764         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5765                 *(natural_width *)p = field_value;
5766                 break;
5767         default:
5768                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5769                 skip_emulated_instruction(vcpu);
5770                 return 1;
5771         }
5772
5773         nested_vmx_succeed(vcpu);
5774         skip_emulated_instruction(vcpu);
5775         return 1;
5776 }
5777
5778 /* Emulate the VMPTRLD instruction */
5779 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5780 {
5781         struct vcpu_vmx *vmx = to_vmx(vcpu);
5782         gva_t gva;
5783         gpa_t vmptr;
5784         struct x86_exception e;
5785
5786         if (!nested_vmx_check_permission(vcpu))
5787                 return 1;
5788
5789         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5790                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5791                 return 1;
5792
5793         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5794                                 sizeof(vmptr), &e)) {
5795                 kvm_inject_page_fault(vcpu, &e);
5796                 return 1;
5797         }
5798
5799         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5800                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5801                 skip_emulated_instruction(vcpu);
5802                 return 1;
5803         }
5804
5805         if (vmx->nested.current_vmptr != vmptr) {
5806                 struct vmcs12 *new_vmcs12;
5807                 struct page *page;
5808                 page = nested_get_page(vcpu, vmptr);
5809                 if (page == NULL) {
5810                         nested_vmx_failInvalid(vcpu);
5811                         skip_emulated_instruction(vcpu);
5812                         return 1;
5813                 }
5814                 new_vmcs12 = kmap(page);
5815                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5816                         kunmap(page);
5817                         nested_release_page_clean(page);
5818                         nested_vmx_failValid(vcpu,
5819                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5820                         skip_emulated_instruction(vcpu);
5821                         return 1;
5822                 }
5823                 if (vmx->nested.current_vmptr != -1ull) {
5824                         kunmap(vmx->nested.current_vmcs12_page);
5825                         nested_release_page(vmx->nested.current_vmcs12_page);
5826                 }
5827
5828                 vmx->nested.current_vmptr = vmptr;
5829                 vmx->nested.current_vmcs12 = new_vmcs12;
5830                 vmx->nested.current_vmcs12_page = page;
5831         }
5832
5833         nested_vmx_succeed(vcpu);
5834         skip_emulated_instruction(vcpu);
5835         return 1;
5836 }
5837
5838 /* Emulate the VMPTRST instruction */
5839 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5840 {
5841         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5842         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5843         gva_t vmcs_gva;
5844         struct x86_exception e;
5845
5846         if (!nested_vmx_check_permission(vcpu))
5847                 return 1;
5848
5849         if (get_vmx_mem_address(vcpu, exit_qualification,
5850                         vmx_instruction_info, &vmcs_gva))
5851                 return 1;
5852         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5853         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5854                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5855                                  sizeof(u64), &e)) {
5856                 kvm_inject_page_fault(vcpu, &e);
5857                 return 1;
5858         }
5859         nested_vmx_succeed(vcpu);
5860         skip_emulated_instruction(vcpu);
5861         return 1;
5862 }
5863
5864 /*
5865  * The exit handlers return 1 if the exit was handled fully and guest execution
5866  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5867  * to be done to userspace and return 0.
5868  */
5869 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5870         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5871         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5872         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5873         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5874         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5875         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5876         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5877         [EXIT_REASON_CPUID]                   = handle_cpuid,
5878         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5879         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5880         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5881         [EXIT_REASON_HLT]                     = handle_halt,
5882         [EXIT_REASON_INVD]                    = handle_invd,
5883         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5884         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5885         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5886         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5887         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5888         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5889         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5890         [EXIT_REASON_VMREAD]                  = handle_vmread,
5891         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5892         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5893         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5894         [EXIT_REASON_VMON]                    = handle_vmon,
5895         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5896         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5897         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5898         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5899         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5900         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5901         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5902         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5903         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5904         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5905         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5906         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5907         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5908 };
5909
5910 static const int kvm_vmx_max_exit_handlers =
5911         ARRAY_SIZE(kvm_vmx_exit_handlers);
5912
5913 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5914                                        struct vmcs12 *vmcs12)
5915 {
5916         unsigned long exit_qualification;
5917         gpa_t bitmap, last_bitmap;
5918         unsigned int port;
5919         int size;
5920         u8 b;
5921
5922         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
5923                 return 1;
5924
5925         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5926                 return 0;
5927
5928         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5929
5930         port = exit_qualification >> 16;
5931         size = (exit_qualification & 7) + 1;
5932
5933         last_bitmap = (gpa_t)-1;
5934         b = -1;
5935
5936         while (size > 0) {
5937                 if (port < 0x8000)
5938                         bitmap = vmcs12->io_bitmap_a;
5939                 else if (port < 0x10000)
5940                         bitmap = vmcs12->io_bitmap_b;
5941                 else
5942                         return 1;
5943                 bitmap += (port & 0x7fff) / 8;
5944
5945                 if (last_bitmap != bitmap)
5946                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
5947                                 return 1;
5948                 if (b & (1 << (port & 7)))
5949                         return 1;
5950
5951                 port++;
5952                 size--;
5953                 last_bitmap = bitmap;
5954         }
5955
5956         return 0;
5957 }
5958
5959 /*
5960  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5961  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5962  * disinterest in the current event (read or write a specific MSR) by using an
5963  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5964  */
5965 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5966         struct vmcs12 *vmcs12, u32 exit_reason)
5967 {
5968         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5969         gpa_t bitmap;
5970
5971         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
5972                 return 1;
5973
5974         /*
5975          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5976          * for the four combinations of read/write and low/high MSR numbers.
5977          * First we need to figure out which of the four to use:
5978          */
5979         bitmap = vmcs12->msr_bitmap;
5980         if (exit_reason == EXIT_REASON_MSR_WRITE)
5981                 bitmap += 2048;
5982         if (msr_index >= 0xc0000000) {
5983                 msr_index -= 0xc0000000;
5984                 bitmap += 1024;
5985         }
5986
5987         /* Then read the msr_index'th bit from this bitmap: */
5988         if (msr_index < 1024*8) {
5989                 unsigned char b;
5990                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
5991                         return 1;
5992                 return 1 & (b >> (msr_index & 7));
5993         } else
5994                 return 1; /* let L1 handle the wrong parameter */
5995 }
5996
5997 /*
5998  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5999  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6000  * intercept (via guest_host_mask etc.) the current event.
6001  */
6002 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6003         struct vmcs12 *vmcs12)
6004 {
6005         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6006         int cr = exit_qualification & 15;
6007         int reg = (exit_qualification >> 8) & 15;
6008         unsigned long val = kvm_register_read(vcpu, reg);
6009
6010         switch ((exit_qualification >> 4) & 3) {
6011         case 0: /* mov to cr */
6012                 switch (cr) {
6013                 case 0:
6014                         if (vmcs12->cr0_guest_host_mask &
6015                             (val ^ vmcs12->cr0_read_shadow))
6016                                 return 1;
6017                         break;
6018                 case 3:
6019                         if ((vmcs12->cr3_target_count >= 1 &&
6020                                         vmcs12->cr3_target_value0 == val) ||
6021                                 (vmcs12->cr3_target_count >= 2 &&
6022                                         vmcs12->cr3_target_value1 == val) ||
6023                                 (vmcs12->cr3_target_count >= 3 &&
6024                                         vmcs12->cr3_target_value2 == val) ||
6025                                 (vmcs12->cr3_target_count >= 4 &&
6026                                         vmcs12->cr3_target_value3 == val))
6027                                 return 0;
6028                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6029                                 return 1;
6030                         break;
6031                 case 4:
6032                         if (vmcs12->cr4_guest_host_mask &
6033                             (vmcs12->cr4_read_shadow ^ val))
6034                                 return 1;
6035                         break;
6036                 case 8:
6037                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6038                                 return 1;
6039                         break;
6040                 }
6041                 break;
6042         case 2: /* clts */
6043                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6044                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6045                         return 1;
6046                 break;
6047         case 1: /* mov from cr */
6048                 switch (cr) {
6049                 case 3:
6050                         if (vmcs12->cpu_based_vm_exec_control &
6051                             CPU_BASED_CR3_STORE_EXITING)
6052                                 return 1;
6053                         break;
6054                 case 8:
6055                         if (vmcs12->cpu_based_vm_exec_control &
6056                             CPU_BASED_CR8_STORE_EXITING)
6057                                 return 1;
6058                         break;
6059                 }
6060                 break;
6061         case 3: /* lmsw */
6062                 /*
6063                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6064                  * cr0. Other attempted changes are ignored, with no exit.
6065                  */
6066                 if (vmcs12->cr0_guest_host_mask & 0xe &
6067                     (val ^ vmcs12->cr0_read_shadow))
6068                         return 1;
6069                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6070                     !(vmcs12->cr0_read_shadow & 0x1) &&
6071                     (val & 0x1))
6072                         return 1;
6073                 break;
6074         }
6075         return 0;
6076 }
6077
6078 /*
6079  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6080  * should handle it ourselves in L0 (and then continue L2). Only call this
6081  * when in is_guest_mode (L2).
6082  */
6083 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6084 {
6085         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6086         struct vcpu_vmx *vmx = to_vmx(vcpu);
6087         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6088         u32 exit_reason = vmx->exit_reason;
6089
6090         if (vmx->nested.nested_run_pending)
6091                 return 0;
6092
6093         if (unlikely(vmx->fail)) {
6094                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6095                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6096                 return 1;
6097         }
6098
6099         switch (exit_reason) {
6100         case EXIT_REASON_EXCEPTION_NMI:
6101                 if (!is_exception(intr_info))
6102                         return 0;
6103                 else if (is_page_fault(intr_info))
6104                         return enable_ept;
6105                 return vmcs12->exception_bitmap &
6106                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6107         case EXIT_REASON_EXTERNAL_INTERRUPT:
6108                 return 0;
6109         case EXIT_REASON_TRIPLE_FAULT:
6110                 return 1;
6111         case EXIT_REASON_PENDING_INTERRUPT:
6112         case EXIT_REASON_NMI_WINDOW:
6113                 /*
6114                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
6115                  * (aka Interrupt Window Exiting) only when L1 turned it on,
6116                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
6117                  * Same for NMI Window Exiting.
6118                  */
6119                 return 1;
6120         case EXIT_REASON_TASK_SWITCH:
6121                 return 1;
6122         case EXIT_REASON_CPUID:
6123                 return 1;
6124         case EXIT_REASON_HLT:
6125                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6126         case EXIT_REASON_INVD:
6127                 return 1;
6128         case EXIT_REASON_INVLPG:
6129                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6130         case EXIT_REASON_RDPMC:
6131                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6132         case EXIT_REASON_RDTSC:
6133                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6134         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6135         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6136         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6137         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6138         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6139                 /*
6140                  * VMX instructions trap unconditionally. This allows L1 to
6141                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6142                  */
6143                 return 1;
6144         case EXIT_REASON_CR_ACCESS:
6145                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6146         case EXIT_REASON_DR_ACCESS:
6147                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6148         case EXIT_REASON_IO_INSTRUCTION:
6149                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6150         case EXIT_REASON_MSR_READ:
6151         case EXIT_REASON_MSR_WRITE:
6152                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6153         case EXIT_REASON_INVALID_STATE:
6154                 return 1;
6155         case EXIT_REASON_MWAIT_INSTRUCTION:
6156                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6157         case EXIT_REASON_MONITOR_INSTRUCTION:
6158                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6159         case EXIT_REASON_PAUSE_INSTRUCTION:
6160                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6161                         nested_cpu_has2(vmcs12,
6162                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6163         case EXIT_REASON_MCE_DURING_VMENTRY:
6164                 return 0;
6165         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6166                 return 1;
6167         case EXIT_REASON_APIC_ACCESS:
6168                 return nested_cpu_has2(vmcs12,
6169                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6170         case EXIT_REASON_EPT_VIOLATION:
6171         case EXIT_REASON_EPT_MISCONFIG:
6172                 return 0;
6173         case EXIT_REASON_WBINVD:
6174                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6175         case EXIT_REASON_XSETBV:
6176                 return 1;
6177         default:
6178                 return 1;
6179         }
6180 }
6181
6182 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6183 {
6184         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6185         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6186 }
6187
6188 /*
6189  * The guest has exited.  See if we can fix it or if we need userspace
6190  * assistance.
6191  */
6192 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6193 {
6194         struct vcpu_vmx *vmx = to_vmx(vcpu);
6195         u32 exit_reason = vmx->exit_reason;
6196         u32 vectoring_info = vmx->idt_vectoring_info;
6197
6198         /* If guest state is invalid, start emulating */
6199         if (vmx->emulation_required)
6200                 return handle_invalid_guest_state(vcpu);
6201
6202         /*
6203          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6204          * we did not inject a still-pending event to L1 now because of
6205          * nested_run_pending, we need to re-enable this bit.
6206          */
6207         if (vmx->nested.nested_run_pending)
6208                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6209
6210         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6211             exit_reason == EXIT_REASON_VMRESUME))
6212                 vmx->nested.nested_run_pending = 1;
6213         else
6214                 vmx->nested.nested_run_pending = 0;
6215
6216         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6217                 nested_vmx_vmexit(vcpu);
6218                 return 1;
6219         }
6220
6221         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6222                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6223                 vcpu->run->fail_entry.hardware_entry_failure_reason
6224                         = exit_reason;
6225                 return 0;
6226         }
6227
6228         if (unlikely(vmx->fail)) {
6229                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6230                 vcpu->run->fail_entry.hardware_entry_failure_reason
6231                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6232                 return 0;
6233         }
6234
6235         /*
6236          * Note:
6237          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6238          * delivery event since it indicates guest is accessing MMIO.
6239          * The vm-exit can be triggered again after return to guest that
6240          * will cause infinite loop.
6241          */
6242         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6243                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6244                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6245                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6246                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6247                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6248                 vcpu->run->internal.ndata = 2;
6249                 vcpu->run->internal.data[0] = vectoring_info;
6250                 vcpu->run->internal.data[1] = exit_reason;
6251                 return 0;
6252         }
6253
6254         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6255             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6256                                         get_vmcs12(vcpu), vcpu)))) {
6257                 if (vmx_interrupt_allowed(vcpu)) {
6258                         vmx->soft_vnmi_blocked = 0;
6259                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6260                            vcpu->arch.nmi_pending) {
6261                         /*
6262                          * This CPU don't support us in finding the end of an
6263                          * NMI-blocked window if the guest runs with IRQs
6264                          * disabled. So we pull the trigger after 1 s of
6265                          * futile waiting, but inform the user about this.
6266                          */
6267                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6268                                "state on VCPU %d after 1 s timeout\n",
6269                                __func__, vcpu->vcpu_id);
6270                         vmx->soft_vnmi_blocked = 0;
6271                 }
6272         }
6273
6274         if (exit_reason < kvm_vmx_max_exit_handlers
6275             && kvm_vmx_exit_handlers[exit_reason])
6276                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6277         else {
6278                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6279                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6280         }
6281         return 0;
6282 }
6283
6284 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6285 {
6286         if (irr == -1 || tpr < irr) {
6287                 vmcs_write32(TPR_THRESHOLD, 0);
6288                 return;
6289         }
6290
6291         vmcs_write32(TPR_THRESHOLD, irr);
6292 }
6293
6294 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6295 {
6296         u32 sec_exec_control;
6297
6298         /*
6299          * There is not point to enable virtualize x2apic without enable
6300          * apicv
6301          */
6302         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6303                                 !vmx_vm_has_apicv(vcpu->kvm))
6304                 return;
6305
6306         if (!vm_need_tpr_shadow(vcpu->kvm))
6307                 return;
6308
6309         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6310
6311         if (set) {
6312                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6313                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6314         } else {
6315                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6316                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6317         }
6318         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6319
6320         vmx_set_msr_bitmap(vcpu);
6321 }
6322
6323 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6324 {
6325         u16 status;
6326         u8 old;
6327
6328         if (!vmx_vm_has_apicv(kvm))
6329                 return;
6330
6331         if (isr == -1)
6332                 isr = 0;
6333
6334         status = vmcs_read16(GUEST_INTR_STATUS);
6335         old = status >> 8;
6336         if (isr != old) {
6337                 status &= 0xff;
6338                 status |= isr << 8;
6339                 vmcs_write16(GUEST_INTR_STATUS, status);
6340         }
6341 }
6342
6343 static void vmx_set_rvi(int vector)
6344 {
6345         u16 status;
6346         u8 old;
6347
6348         status = vmcs_read16(GUEST_INTR_STATUS);
6349         old = (u8)status & 0xff;
6350         if ((u8)vector != old) {
6351                 status &= ~0xff;
6352                 status |= (u8)vector;
6353                 vmcs_write16(GUEST_INTR_STATUS, status);
6354         }
6355 }
6356
6357 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6358 {
6359         if (max_irr == -1)
6360                 return;
6361
6362         vmx_set_rvi(max_irr);
6363 }
6364
6365 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6366 {
6367         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6368         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6369         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6370         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6371 }
6372
6373 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6374 {
6375         u32 exit_intr_info;
6376
6377         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6378               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6379                 return;
6380
6381         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6382         exit_intr_info = vmx->exit_intr_info;
6383
6384         /* Handle machine checks before interrupts are enabled */
6385         if (is_machine_check(exit_intr_info))
6386                 kvm_machine_check();
6387
6388         /* We need to handle NMIs before interrupts are enabled */
6389         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6390             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6391                 kvm_before_handle_nmi(&vmx->vcpu);
6392                 asm("int $2");
6393                 kvm_after_handle_nmi(&vmx->vcpu);
6394         }
6395 }
6396
6397 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6398 {
6399         u32 exit_intr_info;
6400         bool unblock_nmi;
6401         u8 vector;
6402         bool idtv_info_valid;
6403
6404         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6405
6406         if (cpu_has_virtual_nmis()) {
6407                 if (vmx->nmi_known_unmasked)
6408                         return;
6409                 /*
6410                  * Can't use vmx->exit_intr_info since we're not sure what
6411                  * the exit reason is.
6412                  */
6413                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6414                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6415                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6416                 /*
6417                  * SDM 3: 27.7.1.2 (September 2008)
6418                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6419                  * a guest IRET fault.
6420                  * SDM 3: 23.2.2 (September 2008)
6421                  * Bit 12 is undefined in any of the following cases:
6422                  *  If the VM exit sets the valid bit in the IDT-vectoring
6423                  *   information field.
6424                  *  If the VM exit is due to a double fault.
6425                  */
6426                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6427                     vector != DF_VECTOR && !idtv_info_valid)
6428                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6429                                       GUEST_INTR_STATE_NMI);
6430                 else
6431                         vmx->nmi_known_unmasked =
6432                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6433                                   & GUEST_INTR_STATE_NMI);
6434         } else if (unlikely(vmx->soft_vnmi_blocked))
6435                 vmx->vnmi_blocked_time +=
6436                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6437 }
6438
6439 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6440                                       u32 idt_vectoring_info,
6441                                       int instr_len_field,
6442                                       int error_code_field)
6443 {
6444         u8 vector;
6445         int type;
6446         bool idtv_info_valid;
6447
6448         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6449
6450         vcpu->arch.nmi_injected = false;
6451         kvm_clear_exception_queue(vcpu);
6452         kvm_clear_interrupt_queue(vcpu);
6453
6454         if (!idtv_info_valid)
6455                 return;
6456
6457         kvm_make_request(KVM_REQ_EVENT, vcpu);
6458
6459         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6460         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6461
6462         switch (type) {
6463         case INTR_TYPE_NMI_INTR:
6464                 vcpu->arch.nmi_injected = true;
6465                 /*
6466                  * SDM 3: 27.7.1.2 (September 2008)
6467                  * Clear bit "block by NMI" before VM entry if a NMI
6468                  * delivery faulted.
6469                  */
6470                 vmx_set_nmi_mask(vcpu, false);
6471                 break;
6472         case INTR_TYPE_SOFT_EXCEPTION:
6473                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6474                 /* fall through */
6475         case INTR_TYPE_HARD_EXCEPTION:
6476                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6477                         u32 err = vmcs_read32(error_code_field);
6478                         kvm_queue_exception_e(vcpu, vector, err);
6479                 } else
6480                         kvm_queue_exception(vcpu, vector);
6481                 break;
6482         case INTR_TYPE_SOFT_INTR:
6483                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6484                 /* fall through */
6485         case INTR_TYPE_EXT_INTR:
6486                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6487                 break;
6488         default:
6489                 break;
6490         }
6491 }
6492
6493 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6494 {
6495         if (is_guest_mode(&vmx->vcpu))
6496                 return;
6497         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6498                                   VM_EXIT_INSTRUCTION_LEN,
6499                                   IDT_VECTORING_ERROR_CODE);
6500 }
6501
6502 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6503 {
6504         if (is_guest_mode(vcpu))
6505                 return;
6506         __vmx_complete_interrupts(vcpu,
6507                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6508                                   VM_ENTRY_INSTRUCTION_LEN,
6509                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6510
6511         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6512 }
6513
6514 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6515 {
6516         int i, nr_msrs;
6517         struct perf_guest_switch_msr *msrs;
6518
6519         msrs = perf_guest_get_msrs(&nr_msrs);
6520
6521         if (!msrs)
6522                 return;
6523
6524         for (i = 0; i < nr_msrs; i++)
6525                 if (msrs[i].host == msrs[i].guest)
6526                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6527                 else
6528                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6529                                         msrs[i].host);
6530 }
6531
6532 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6533 {
6534         struct vcpu_vmx *vmx = to_vmx(vcpu);
6535         unsigned long debugctlmsr;
6536
6537         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6538                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6539                 if (vmcs12->idt_vectoring_info_field &
6540                                 VECTORING_INFO_VALID_MASK) {
6541                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6542                                 vmcs12->idt_vectoring_info_field);
6543                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6544                                 vmcs12->vm_exit_instruction_len);
6545                         if (vmcs12->idt_vectoring_info_field &
6546                                         VECTORING_INFO_DELIVER_CODE_MASK)
6547                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6548                                         vmcs12->idt_vectoring_error_code);
6549                 }
6550         }
6551
6552         /* Record the guest's net vcpu time for enforced NMI injections. */
6553         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6554                 vmx->entry_time = ktime_get();
6555
6556         /* Don't enter VMX if guest state is invalid, let the exit handler
6557            start emulation until we arrive back to a valid state */
6558         if (vmx->emulation_required)
6559                 return;
6560
6561         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6562                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6563         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6564                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6565
6566         /* When single-stepping over STI and MOV SS, we must clear the
6567          * corresponding interruptibility bits in the guest state. Otherwise
6568          * vmentry fails as it then expects bit 14 (BS) in pending debug
6569          * exceptions being set, but that's not correct for the guest debugging
6570          * case. */
6571         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6572                 vmx_set_interrupt_shadow(vcpu, 0);
6573
6574         atomic_switch_perf_msrs(vmx);
6575         debugctlmsr = get_debugctlmsr();
6576
6577         vmx->__launched = vmx->loaded_vmcs->launched;
6578         asm(
6579                 /* Store host registers */
6580                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6581                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6582                 "push %%" _ASM_CX " \n\t"
6583                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6584                 "je 1f \n\t"
6585                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6586                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6587                 "1: \n\t"
6588                 /* Reload cr2 if changed */
6589                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6590                 "mov %%cr2, %%" _ASM_DX " \n\t"
6591                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6592                 "je 2f \n\t"
6593                 "mov %%" _ASM_AX", %%cr2 \n\t"
6594                 "2: \n\t"
6595                 /* Check if vmlaunch of vmresume is needed */
6596                 "cmpl $0, %c[launched](%0) \n\t"
6597                 /* Load guest registers.  Don't clobber flags. */
6598                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6599                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6600                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6601                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6602                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6603                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
6604 #ifdef CONFIG_X86_64
6605                 "mov %c[r8](%0),  %%r8  \n\t"
6606                 "mov %c[r9](%0),  %%r9  \n\t"
6607                 "mov %c[r10](%0), %%r10 \n\t"
6608                 "mov %c[r11](%0), %%r11 \n\t"
6609                 "mov %c[r12](%0), %%r12 \n\t"
6610                 "mov %c[r13](%0), %%r13 \n\t"
6611                 "mov %c[r14](%0), %%r14 \n\t"
6612                 "mov %c[r15](%0), %%r15 \n\t"
6613 #endif
6614                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
6615
6616                 /* Enter guest mode */
6617                 "jne 1f \n\t"
6618                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6619                 "jmp 2f \n\t"
6620                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6621                 "2: "
6622                 /* Save guest registers, load host registers, keep flags */
6623                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
6624                 "pop %0 \n\t"
6625                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6626                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6627                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6628                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6629                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6630                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6631                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
6632 #ifdef CONFIG_X86_64
6633                 "mov %%r8,  %c[r8](%0) \n\t"
6634                 "mov %%r9,  %c[r9](%0) \n\t"
6635                 "mov %%r10, %c[r10](%0) \n\t"
6636                 "mov %%r11, %c[r11](%0) \n\t"
6637                 "mov %%r12, %c[r12](%0) \n\t"
6638                 "mov %%r13, %c[r13](%0) \n\t"
6639                 "mov %%r14, %c[r14](%0) \n\t"
6640                 "mov %%r15, %c[r15](%0) \n\t"
6641 #endif
6642                 "mov %%cr2, %%" _ASM_AX "   \n\t"
6643                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
6644
6645                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
6646                 "setbe %c[fail](%0) \n\t"
6647                 ".pushsection .rodata \n\t"
6648                 ".global vmx_return \n\t"
6649                 "vmx_return: " _ASM_PTR " 2b \n\t"
6650                 ".popsection"
6651               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6652                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6653                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6654                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6655                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6656                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6657                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6658                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6659                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6660                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6661                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6662 #ifdef CONFIG_X86_64
6663                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6664                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6665                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6666                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6667                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6668                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6669                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6670                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6671 #endif
6672                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6673                 [wordsize]"i"(sizeof(ulong))
6674               : "cc", "memory"
6675 #ifdef CONFIG_X86_64
6676                 , "rax", "rbx", "rdi", "rsi"
6677                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6678 #else
6679                 , "eax", "ebx", "edi", "esi"
6680 #endif
6681               );
6682
6683         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6684         if (debugctlmsr)
6685                 update_debugctlmsr(debugctlmsr);
6686
6687 #ifndef CONFIG_X86_64
6688         /*
6689          * The sysexit path does not restore ds/es, so we must set them to
6690          * a reasonable value ourselves.
6691          *
6692          * We can't defer this to vmx_load_host_state() since that function
6693          * may be executed in interrupt context, which saves and restore segments
6694          * around it, nullifying its effect.
6695          */
6696         loadsegment(ds, __USER_DS);
6697         loadsegment(es, __USER_DS);
6698 #endif
6699
6700         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6701                                   | (1 << VCPU_EXREG_RFLAGS)
6702                                   | (1 << VCPU_EXREG_CPL)
6703                                   | (1 << VCPU_EXREG_PDPTR)
6704                                   | (1 << VCPU_EXREG_SEGMENTS)
6705                                   | (1 << VCPU_EXREG_CR3));
6706         vcpu->arch.regs_dirty = 0;
6707
6708         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6709
6710         if (is_guest_mode(vcpu)) {
6711                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6712                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6713                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6714                         vmcs12->idt_vectoring_error_code =
6715                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6716                         vmcs12->vm_exit_instruction_len =
6717                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6718                 }
6719         }
6720
6721         vmx->loaded_vmcs->launched = 1;
6722
6723         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6724         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6725
6726         vmx_complete_atomic_exit(vmx);
6727         vmx_recover_nmi_blocking(vmx);
6728         vmx_complete_interrupts(vmx);
6729 }
6730
6731 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6732 {
6733         struct vcpu_vmx *vmx = to_vmx(vcpu);
6734
6735         free_vpid(vmx);
6736         free_nested(vmx);
6737         free_loaded_vmcs(vmx->loaded_vmcs);
6738         kfree(vmx->guest_msrs);
6739         kvm_vcpu_uninit(vcpu);
6740         kmem_cache_free(kvm_vcpu_cache, vmx);
6741 }
6742
6743 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6744 {
6745         int err;
6746         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6747         int cpu;
6748
6749         if (!vmx)
6750                 return ERR_PTR(-ENOMEM);
6751
6752         allocate_vpid(vmx);
6753
6754         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6755         if (err)
6756                 goto free_vcpu;
6757
6758         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6759         err = -ENOMEM;
6760         if (!vmx->guest_msrs) {
6761                 goto uninit_vcpu;
6762         }
6763
6764         vmx->loaded_vmcs = &vmx->vmcs01;
6765         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6766         if (!vmx->loaded_vmcs->vmcs)
6767                 goto free_msrs;
6768         if (!vmm_exclusive)
6769                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6770         loaded_vmcs_init(vmx->loaded_vmcs);
6771         if (!vmm_exclusive)
6772                 kvm_cpu_vmxoff();
6773
6774         cpu = get_cpu();
6775         vmx_vcpu_load(&vmx->vcpu, cpu);
6776         vmx->vcpu.cpu = cpu;
6777         err = vmx_vcpu_setup(vmx);
6778         vmx_vcpu_put(&vmx->vcpu);
6779         put_cpu();
6780         if (err)
6781                 goto free_vmcs;
6782         if (vm_need_virtualize_apic_accesses(kvm))
6783                 err = alloc_apic_access_page(kvm);
6784                 if (err)
6785                         goto free_vmcs;
6786
6787         if (enable_ept) {
6788                 if (!kvm->arch.ept_identity_map_addr)
6789                         kvm->arch.ept_identity_map_addr =
6790                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6791                 err = -ENOMEM;
6792                 if (alloc_identity_pagetable(kvm) != 0)
6793                         goto free_vmcs;
6794                 if (!init_rmode_identity_map(kvm))
6795                         goto free_vmcs;
6796         }
6797
6798         vmx->nested.current_vmptr = -1ull;
6799         vmx->nested.current_vmcs12 = NULL;
6800
6801         return &vmx->vcpu;
6802
6803 free_vmcs:
6804         free_loaded_vmcs(vmx->loaded_vmcs);
6805 free_msrs:
6806         kfree(vmx->guest_msrs);
6807 uninit_vcpu:
6808         kvm_vcpu_uninit(&vmx->vcpu);
6809 free_vcpu:
6810         free_vpid(vmx);
6811         kmem_cache_free(kvm_vcpu_cache, vmx);
6812         return ERR_PTR(err);
6813 }
6814
6815 static void __init vmx_check_processor_compat(void *rtn)
6816 {
6817         struct vmcs_config vmcs_conf;
6818
6819         *(int *)rtn = 0;
6820         if (setup_vmcs_config(&vmcs_conf) < 0)
6821                 *(int *)rtn = -EIO;
6822         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6823                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6824                                 smp_processor_id());
6825                 *(int *)rtn = -EIO;
6826         }
6827 }
6828
6829 static int get_ept_level(void)
6830 {
6831         return VMX_EPT_DEFAULT_GAW + 1;
6832 }
6833
6834 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6835 {
6836         u64 ret;
6837
6838         /* For VT-d and EPT combination
6839          * 1. MMIO: always map as UC
6840          * 2. EPT with VT-d:
6841          *   a. VT-d without snooping control feature: can't guarantee the
6842          *      result, try to trust guest.
6843          *   b. VT-d with snooping control feature: snooping control feature of
6844          *      VT-d engine can guarantee the cache correctness. Just set it
6845          *      to WB to keep consistent with host. So the same as item 3.
6846          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6847          *    consistent with host MTRR
6848          */
6849         if (is_mmio)
6850                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6851         else if (vcpu->kvm->arch.iommu_domain &&
6852                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6853                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6854                       VMX_EPT_MT_EPTE_SHIFT;
6855         else
6856                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6857                         | VMX_EPT_IPAT_BIT;
6858
6859         return ret;
6860 }
6861
6862 static int vmx_get_lpage_level(void)
6863 {
6864         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6865                 return PT_DIRECTORY_LEVEL;
6866         else
6867                 /* For shadow and EPT supported 1GB page */
6868                 return PT_PDPE_LEVEL;
6869 }
6870
6871 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6872 {
6873         struct kvm_cpuid_entry2 *best;
6874         struct vcpu_vmx *vmx = to_vmx(vcpu);
6875         u32 exec_control;
6876
6877         vmx->rdtscp_enabled = false;
6878         if (vmx_rdtscp_supported()) {
6879                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6880                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6881                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6882                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6883                                 vmx->rdtscp_enabled = true;
6884                         else {
6885                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6886                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6887                                                 exec_control);
6888                         }
6889                 }
6890         }
6891
6892         /* Exposing INVPCID only when PCID is exposed */
6893         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6894         if (vmx_invpcid_supported() &&
6895             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
6896             guest_cpuid_has_pcid(vcpu)) {
6897                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6898                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6899                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6900                              exec_control);
6901         } else {
6902                 if (cpu_has_secondary_exec_ctrls()) {
6903                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6904                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6905                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6906                                      exec_control);
6907                 }
6908                 if (best)
6909                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
6910         }
6911 }
6912
6913 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6914 {
6915         if (func == 1 && nested)
6916                 entry->ecx |= bit(X86_FEATURE_VMX);
6917 }
6918
6919 /*
6920  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6921  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6922  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6923  * guest in a way that will both be appropriate to L1's requests, and our
6924  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6925  * function also has additional necessary side-effects, like setting various
6926  * vcpu->arch fields.
6927  */
6928 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6929 {
6930         struct vcpu_vmx *vmx = to_vmx(vcpu);
6931         u32 exec_control;
6932
6933         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6934         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6935         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6936         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6937         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6938         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6939         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6940         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6941         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6942         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6943         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6944         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6945         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6946         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6947         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6948         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6949         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6950         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6951         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6952         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6953         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6954         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6955         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6956         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6957         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6958         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6959         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6960         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6961         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6962         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6963         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6964         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6965         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6966         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6967         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6968         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6969
6970         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6971         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6972                 vmcs12->vm_entry_intr_info_field);
6973         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6974                 vmcs12->vm_entry_exception_error_code);
6975         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6976                 vmcs12->vm_entry_instruction_len);
6977         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6978                 vmcs12->guest_interruptibility_info);
6979         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6980         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6981         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
6982         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6983         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6984                 vmcs12->guest_pending_dbg_exceptions);
6985         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6986         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6987
6988         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6989
6990         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6991                 (vmcs_config.pin_based_exec_ctrl |
6992                  vmcs12->pin_based_vm_exec_control));
6993
6994         /*
6995          * Whether page-faults are trapped is determined by a combination of
6996          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6997          * If enable_ept, L0 doesn't care about page faults and we should
6998          * set all of these to L1's desires. However, if !enable_ept, L0 does
6999          * care about (at least some) page faults, and because it is not easy
7000          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7001          * to exit on each and every L2 page fault. This is done by setting
7002          * MASK=MATCH=0 and (see below) EB.PF=1.
7003          * Note that below we don't need special code to set EB.PF beyond the
7004          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7005          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7006          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7007          *
7008          * A problem with this approach (when !enable_ept) is that L1 may be
7009          * injected with more page faults than it asked for. This could have
7010          * caused problems, but in practice existing hypervisors don't care.
7011          * To fix this, we will need to emulate the PFEC checking (on the L1
7012          * page tables), using walk_addr(), when injecting PFs to L1.
7013          */
7014         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7015                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7016         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7017                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7018
7019         if (cpu_has_secondary_exec_ctrls()) {
7020                 u32 exec_control = vmx_secondary_exec_control(vmx);
7021                 if (!vmx->rdtscp_enabled)
7022                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7023                 /* Take the following fields only from vmcs12 */
7024                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7025                 if (nested_cpu_has(vmcs12,
7026                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7027                         exec_control |= vmcs12->secondary_vm_exec_control;
7028
7029                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7030                         /*
7031                          * Translate L1 physical address to host physical
7032                          * address for vmcs02. Keep the page pinned, so this
7033                          * physical address remains valid. We keep a reference
7034                          * to it so we can release it later.
7035                          */
7036                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7037                                 nested_release_page(vmx->nested.apic_access_page);
7038                         vmx->nested.apic_access_page =
7039                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7040                         /*
7041                          * If translation failed, no matter: This feature asks
7042                          * to exit when accessing the given address, and if it
7043                          * can never be accessed, this feature won't do
7044                          * anything anyway.
7045                          */
7046                         if (!vmx->nested.apic_access_page)
7047                                 exec_control &=
7048                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7049                         else
7050                                 vmcs_write64(APIC_ACCESS_ADDR,
7051                                   page_to_phys(vmx->nested.apic_access_page));
7052                 }
7053
7054                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7055         }
7056
7057
7058         /*
7059          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7060          * Some constant fields are set here by vmx_set_constant_host_state().
7061          * Other fields are different per CPU, and will be set later when
7062          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7063          */
7064         vmx_set_constant_host_state();
7065
7066         /*
7067          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7068          * entry, but only if the current (host) sp changed from the value
7069          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7070          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7071          * here we just force the write to happen on entry.
7072          */
7073         vmx->host_rsp = 0;
7074
7075         exec_control = vmx_exec_control(vmx); /* L0's desires */
7076         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7077         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7078         exec_control &= ~CPU_BASED_TPR_SHADOW;
7079         exec_control |= vmcs12->cpu_based_vm_exec_control;
7080         /*
7081          * Merging of IO and MSR bitmaps not currently supported.
7082          * Rather, exit every time.
7083          */
7084         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7085         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7086         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7087
7088         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7089
7090         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7091          * bitwise-or of what L1 wants to trap for L2, and what we want to
7092          * trap. Note that CR0.TS also needs updating - we do this later.
7093          */
7094         update_exception_bitmap(vcpu);
7095         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7096         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7097
7098         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7099         vmcs_write32(VM_EXIT_CONTROLS,
7100                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7101         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7102                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7103
7104         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7105                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7106         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7107                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7108
7109
7110         set_cr4_guest_host_mask(vmx);
7111
7112         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7113                 vmcs_write64(TSC_OFFSET,
7114                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7115         else
7116                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7117
7118         if (enable_vpid) {
7119                 /*
7120                  * Trivially support vpid by letting L2s share their parent
7121                  * L1's vpid. TODO: move to a more elaborate solution, giving
7122                  * each L2 its own vpid and exposing the vpid feature to L1.
7123                  */
7124                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7125                 vmx_flush_tlb(vcpu);
7126         }
7127
7128         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7129                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7130         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7131                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7132         else
7133                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7134         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7135         vmx_set_efer(vcpu, vcpu->arch.efer);
7136
7137         /*
7138          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7139          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7140          * The CR0_READ_SHADOW is what L2 should have expected to read given
7141          * the specifications by L1; It's not enough to take
7142          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7143          * have more bits than L1 expected.
7144          */
7145         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7146         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7147
7148         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7149         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7150
7151         /* shadow page tables on either EPT or shadow page tables */
7152         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7153         kvm_mmu_reset_context(vcpu);
7154
7155         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7156         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7157 }
7158
7159 /*
7160  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7161  * for running an L2 nested guest.
7162  */
7163 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7164 {
7165         struct vmcs12 *vmcs12;
7166         struct vcpu_vmx *vmx = to_vmx(vcpu);
7167         int cpu;
7168         struct loaded_vmcs *vmcs02;
7169
7170         if (!nested_vmx_check_permission(vcpu) ||
7171             !nested_vmx_check_vmcs12(vcpu))
7172                 return 1;
7173
7174         skip_emulated_instruction(vcpu);
7175         vmcs12 = get_vmcs12(vcpu);
7176
7177         /*
7178          * The nested entry process starts with enforcing various prerequisites
7179          * on vmcs12 as required by the Intel SDM, and act appropriately when
7180          * they fail: As the SDM explains, some conditions should cause the
7181          * instruction to fail, while others will cause the instruction to seem
7182          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7183          * To speed up the normal (success) code path, we should avoid checking
7184          * for misconfigurations which will anyway be caught by the processor
7185          * when using the merged vmcs02.
7186          */
7187         if (vmcs12->launch_state == launch) {
7188                 nested_vmx_failValid(vcpu,
7189                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7190                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7191                 return 1;
7192         }
7193
7194         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7195                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7196                 /*TODO: Also verify bits beyond physical address width are 0*/
7197                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7198                 return 1;
7199         }
7200
7201         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7202                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7203                 /*TODO: Also verify bits beyond physical address width are 0*/
7204                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7205                 return 1;
7206         }
7207
7208         if (vmcs12->vm_entry_msr_load_count > 0 ||
7209             vmcs12->vm_exit_msr_load_count > 0 ||
7210             vmcs12->vm_exit_msr_store_count > 0) {
7211                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7212                                     __func__);
7213                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7214                 return 1;
7215         }
7216
7217         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7218               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7219             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7220               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7221             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7222               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7223             !vmx_control_verify(vmcs12->vm_exit_controls,
7224               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7225             !vmx_control_verify(vmcs12->vm_entry_controls,
7226               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7227         {
7228                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7229                 return 1;
7230         }
7231
7232         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7233             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7234                 nested_vmx_failValid(vcpu,
7235                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7236                 return 1;
7237         }
7238
7239         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7240             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7241                 nested_vmx_entry_failure(vcpu, vmcs12,
7242                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7243                 return 1;
7244         }
7245         if (vmcs12->vmcs_link_pointer != -1ull) {
7246                 nested_vmx_entry_failure(vcpu, vmcs12,
7247                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7248                 return 1;
7249         }
7250
7251         /*
7252          * We're finally done with prerequisite checking, and can start with
7253          * the nested entry.
7254          */
7255
7256         vmcs02 = nested_get_current_vmcs02(vmx);
7257         if (!vmcs02)
7258                 return -ENOMEM;
7259
7260         enter_guest_mode(vcpu);
7261
7262         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7263
7264         cpu = get_cpu();
7265         vmx->loaded_vmcs = vmcs02;
7266         vmx_vcpu_put(vcpu);
7267         vmx_vcpu_load(vcpu, cpu);
7268         vcpu->cpu = cpu;
7269         put_cpu();
7270
7271         vmx_segment_cache_clear(vmx);
7272
7273         vmcs12->launch_state = 1;
7274
7275         prepare_vmcs02(vcpu, vmcs12);
7276
7277         /*
7278          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7279          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7280          * returned as far as L1 is concerned. It will only return (and set
7281          * the success flag) when L2 exits (see nested_vmx_vmexit()).
7282          */
7283         return 1;
7284 }
7285
7286 /*
7287  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7288  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7289  * This function returns the new value we should put in vmcs12.guest_cr0.
7290  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7291  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7292  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7293  *     didn't trap the bit, because if L1 did, so would L0).
7294  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7295  *     been modified by L2, and L1 knows it. So just leave the old value of
7296  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7297  *     isn't relevant, because if L0 traps this bit it can set it to anything.
7298  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7299  *     changed these bits, and therefore they need to be updated, but L0
7300  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7301  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7302  */
7303 static inline unsigned long
7304 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7305 {
7306         return
7307         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7308         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7309         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7310                         vcpu->arch.cr0_guest_owned_bits));
7311 }
7312
7313 static inline unsigned long
7314 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7315 {
7316         return
7317         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7318         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7319         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7320                         vcpu->arch.cr4_guest_owned_bits));
7321 }
7322
7323 /*
7324  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7325  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7326  * and this function updates it to reflect the changes to the guest state while
7327  * L2 was running (and perhaps made some exits which were handled directly by L0
7328  * without going back to L1), and to reflect the exit reason.
7329  * Note that we do not have to copy here all VMCS fields, just those that
7330  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7331  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7332  * which already writes to vmcs12 directly.
7333  */
7334 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7335 {
7336         /* update guest state fields: */
7337         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7338         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7339
7340         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7341         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7342         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7343         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7344
7345         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7346         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7347         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7348         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7349         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7350         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7351         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7352         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7353         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7354         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7355         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7356         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7357         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7358         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7359         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7360         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7361         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7362         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7363         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7364         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7365         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7366         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7367         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7368         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7369         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7370         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7371         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7372         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7373         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7374         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7375         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7376         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7377         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7378         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7379         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7380         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7381
7382         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7383         vmcs12->guest_interruptibility_info =
7384                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7385         vmcs12->guest_pending_dbg_exceptions =
7386                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7387
7388         /* TODO: These cannot have changed unless we have MSR bitmaps and
7389          * the relevant bit asks not to trap the change */
7390         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7391         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7392                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7393         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7394         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7395         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7396
7397         /* update exit information fields: */
7398
7399         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
7400         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7401
7402         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7403         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7404         vmcs12->idt_vectoring_info_field = to_vmx(vcpu)->idt_vectoring_info;
7405         vmcs12->idt_vectoring_error_code =
7406                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7407         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7408         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7409
7410         /* clear vm-entry fields which are to be cleared on exit */
7411         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7412                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7413 }
7414
7415 /*
7416  * A part of what we need to when the nested L2 guest exits and we want to
7417  * run its L1 parent, is to reset L1's guest state to the host state specified
7418  * in vmcs12.
7419  * This function is to be called not only on normal nested exit, but also on
7420  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7421  * Failures During or After Loading Guest State").
7422  * This function should be called when the active VMCS is L1's (vmcs01).
7423  */
7424 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7425                                    struct vmcs12 *vmcs12)
7426 {
7427         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7428                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7429         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7430                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7431         else
7432                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7433         vmx_set_efer(vcpu, vcpu->arch.efer);
7434
7435         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7436         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7437         /*
7438          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7439          * actually changed, because it depends on the current state of
7440          * fpu_active (which may have changed).
7441          * Note that vmx_set_cr0 refers to efer set above.
7442          */
7443         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7444         /*
7445          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7446          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7447          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7448          */
7449         update_exception_bitmap(vcpu);
7450         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7451         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7452
7453         /*
7454          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7455          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7456          */
7457         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7458         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7459
7460         /* shadow page tables on either EPT or shadow page tables */
7461         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7462         kvm_mmu_reset_context(vcpu);
7463
7464         if (enable_vpid) {
7465                 /*
7466                  * Trivially support vpid by letting L2s share their parent
7467                  * L1's vpid. TODO: move to a more elaborate solution, giving
7468                  * each L2 its own vpid and exposing the vpid feature to L1.
7469                  */
7470                 vmx_flush_tlb(vcpu);
7471         }
7472
7473
7474         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7475         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7476         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7477         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7478         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7479         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7480         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7481         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7482         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7483         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7484         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7485         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7486         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7487         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7488         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7489
7490         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7491                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7492         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7493                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7494                         vmcs12->host_ia32_perf_global_ctrl);
7495
7496         kvm_set_dr(vcpu, 7, 0x400);
7497         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
7498 }
7499
7500 /*
7501  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7502  * and modify vmcs12 to make it see what it would expect to see there if
7503  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7504  */
7505 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7506 {
7507         struct vcpu_vmx *vmx = to_vmx(vcpu);
7508         int cpu;
7509         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7510
7511         leave_guest_mode(vcpu);
7512         prepare_vmcs12(vcpu, vmcs12);
7513
7514         cpu = get_cpu();
7515         vmx->loaded_vmcs = &vmx->vmcs01;
7516         vmx_vcpu_put(vcpu);
7517         vmx_vcpu_load(vcpu, cpu);
7518         vcpu->cpu = cpu;
7519         put_cpu();
7520
7521         vmx_segment_cache_clear(vmx);
7522
7523         /* if no vmcs02 cache requested, remove the one we used */
7524         if (VMCS02_POOL_SIZE == 0)
7525                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7526
7527         load_vmcs12_host_state(vcpu, vmcs12);
7528
7529         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7530         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7531
7532         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7533         vmx->host_rsp = 0;
7534
7535         /* Unpin physical memory we referred to in vmcs02 */
7536         if (vmx->nested.apic_access_page) {
7537                 nested_release_page(vmx->nested.apic_access_page);
7538                 vmx->nested.apic_access_page = 0;
7539         }
7540
7541         /*
7542          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7543          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7544          * success or failure flag accordingly.
7545          */
7546         if (unlikely(vmx->fail)) {
7547                 vmx->fail = 0;
7548                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7549         } else
7550                 nested_vmx_succeed(vcpu);
7551 }
7552
7553 /*
7554  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7555  * 23.7 "VM-entry failures during or after loading guest state" (this also
7556  * lists the acceptable exit-reason and exit-qualification parameters).
7557  * It should only be called before L2 actually succeeded to run, and when
7558  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7559  */
7560 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7561                         struct vmcs12 *vmcs12,
7562                         u32 reason, unsigned long qualification)
7563 {
7564         load_vmcs12_host_state(vcpu, vmcs12);
7565         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7566         vmcs12->exit_qualification = qualification;
7567         nested_vmx_succeed(vcpu);
7568 }
7569
7570 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7571                                struct x86_instruction_info *info,
7572                                enum x86_intercept_stage stage)
7573 {
7574         return X86EMUL_CONTINUE;
7575 }
7576
7577 static struct kvm_x86_ops vmx_x86_ops = {
7578         .cpu_has_kvm_support = cpu_has_kvm_support,
7579         .disabled_by_bios = vmx_disabled_by_bios,
7580         .hardware_setup = hardware_setup,
7581         .hardware_unsetup = hardware_unsetup,
7582         .check_processor_compatibility = vmx_check_processor_compat,
7583         .hardware_enable = hardware_enable,
7584         .hardware_disable = hardware_disable,
7585         .cpu_has_accelerated_tpr = report_flexpriority,
7586
7587         .vcpu_create = vmx_create_vcpu,
7588         .vcpu_free = vmx_free_vcpu,
7589         .vcpu_reset = vmx_vcpu_reset,
7590
7591         .prepare_guest_switch = vmx_save_host_state,
7592         .vcpu_load = vmx_vcpu_load,
7593         .vcpu_put = vmx_vcpu_put,
7594
7595         .update_db_bp_intercept = update_exception_bitmap,
7596         .get_msr = vmx_get_msr,
7597         .set_msr = vmx_set_msr,
7598         .get_segment_base = vmx_get_segment_base,
7599         .get_segment = vmx_get_segment,
7600         .set_segment = vmx_set_segment,
7601         .get_cpl = vmx_get_cpl,
7602         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7603         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7604         .decache_cr3 = vmx_decache_cr3,
7605         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7606         .set_cr0 = vmx_set_cr0,
7607         .set_cr3 = vmx_set_cr3,
7608         .set_cr4 = vmx_set_cr4,
7609         .set_efer = vmx_set_efer,
7610         .get_idt = vmx_get_idt,
7611         .set_idt = vmx_set_idt,
7612         .get_gdt = vmx_get_gdt,
7613         .set_gdt = vmx_set_gdt,
7614         .set_dr7 = vmx_set_dr7,
7615         .cache_reg = vmx_cache_reg,
7616         .get_rflags = vmx_get_rflags,
7617         .set_rflags = vmx_set_rflags,
7618         .fpu_activate = vmx_fpu_activate,
7619         .fpu_deactivate = vmx_fpu_deactivate,
7620
7621         .tlb_flush = vmx_flush_tlb,
7622
7623         .run = vmx_vcpu_run,
7624         .handle_exit = vmx_handle_exit,
7625         .skip_emulated_instruction = skip_emulated_instruction,
7626         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7627         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7628         .patch_hypercall = vmx_patch_hypercall,
7629         .set_irq = vmx_inject_irq,
7630         .set_nmi = vmx_inject_nmi,
7631         .queue_exception = vmx_queue_exception,
7632         .cancel_injection = vmx_cancel_injection,
7633         .interrupt_allowed = vmx_interrupt_allowed,
7634         .nmi_allowed = vmx_nmi_allowed,
7635         .get_nmi_mask = vmx_get_nmi_mask,
7636         .set_nmi_mask = vmx_set_nmi_mask,
7637         .enable_nmi_window = enable_nmi_window,
7638         .enable_irq_window = enable_irq_window,
7639         .update_cr8_intercept = update_cr8_intercept,
7640         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
7641         .vm_has_apicv = vmx_vm_has_apicv,
7642         .load_eoi_exitmap = vmx_load_eoi_exitmap,
7643         .hwapic_irr_update = vmx_hwapic_irr_update,
7644         .hwapic_isr_update = vmx_hwapic_isr_update,
7645
7646         .set_tss_addr = vmx_set_tss_addr,
7647         .get_tdp_level = get_ept_level,
7648         .get_mt_mask = vmx_get_mt_mask,
7649
7650         .get_exit_info = vmx_get_exit_info,
7651
7652         .get_lpage_level = vmx_get_lpage_level,
7653
7654         .cpuid_update = vmx_cpuid_update,
7655
7656         .rdtscp_supported = vmx_rdtscp_supported,
7657         .invpcid_supported = vmx_invpcid_supported,
7658
7659         .set_supported_cpuid = vmx_set_supported_cpuid,
7660
7661         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7662
7663         .set_tsc_khz = vmx_set_tsc_khz,
7664         .read_tsc_offset = vmx_read_tsc_offset,
7665         .write_tsc_offset = vmx_write_tsc_offset,
7666         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7667         .compute_tsc_offset = vmx_compute_tsc_offset,
7668         .read_l1_tsc = vmx_read_l1_tsc,
7669
7670         .set_tdp_cr3 = vmx_set_cr3,
7671
7672         .check_intercept = vmx_check_intercept,
7673 };
7674
7675 static int __init vmx_init(void)
7676 {
7677         int r, i, msr;
7678
7679         rdmsrl_safe(MSR_EFER, &host_efer);
7680
7681         for (i = 0; i < NR_VMX_MSR; ++i)
7682                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7683
7684         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7685         if (!vmx_io_bitmap_a)
7686                 return -ENOMEM;
7687
7688         r = -ENOMEM;
7689
7690         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7691         if (!vmx_io_bitmap_b)
7692                 goto out;
7693
7694         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7695         if (!vmx_msr_bitmap_legacy)
7696                 goto out1;
7697
7698         vmx_msr_bitmap_legacy_x2apic =
7699                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7700         if (!vmx_msr_bitmap_legacy_x2apic)
7701                 goto out2;
7702
7703         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7704         if (!vmx_msr_bitmap_longmode)
7705                 goto out3;
7706
7707         vmx_msr_bitmap_longmode_x2apic =
7708                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7709         if (!vmx_msr_bitmap_longmode_x2apic)
7710                 goto out4;
7711
7712         /*
7713          * Allow direct access to the PC debug port (it is often used for I/O
7714          * delays, but the vmexits simply slow things down).
7715          */
7716         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7717         clear_bit(0x80, vmx_io_bitmap_a);
7718
7719         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7720
7721         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7722         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7723
7724         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7725
7726         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7727                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7728         if (r)
7729                 goto out3;
7730
7731 #ifdef CONFIG_KEXEC
7732         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7733                            crash_vmclear_local_loaded_vmcss);
7734 #endif
7735
7736         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7737         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7738         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7739         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7740         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7741         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7742         memcpy(vmx_msr_bitmap_legacy_x2apic,
7743                         vmx_msr_bitmap_legacy, PAGE_SIZE);
7744         memcpy(vmx_msr_bitmap_longmode_x2apic,
7745                         vmx_msr_bitmap_longmode, PAGE_SIZE);
7746
7747         if (enable_apicv_reg_vid) {
7748                 for (msr = 0x800; msr <= 0x8ff; msr++)
7749                         vmx_disable_intercept_msr_read_x2apic(msr);
7750
7751                 /* According SDM, in x2apic mode, the whole id reg is used.
7752                  * But in KVM, it only use the highest eight bits. Need to
7753                  * intercept it */
7754                 vmx_enable_intercept_msr_read_x2apic(0x802);
7755                 /* TMCCT */
7756                 vmx_enable_intercept_msr_read_x2apic(0x839);
7757                 /* TPR */
7758                 vmx_disable_intercept_msr_write_x2apic(0x808);
7759                 /* EOI */
7760                 vmx_disable_intercept_msr_write_x2apic(0x80b);
7761                 /* SELF-IPI */
7762                 vmx_disable_intercept_msr_write_x2apic(0x83f);
7763         }
7764
7765         if (enable_ept) {
7766                 kvm_mmu_set_mask_ptes(0ull,
7767                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7768                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7769                         0ull, VMX_EPT_EXECUTABLE_MASK);
7770                 ept_set_mmio_spte_mask();
7771                 kvm_enable_tdp();
7772         } else
7773                 kvm_disable_tdp();
7774
7775         return 0;
7776
7777 out4:
7778         free_page((unsigned long)vmx_msr_bitmap_longmode);
7779 out3:
7780         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7781 out2:
7782         free_page((unsigned long)vmx_msr_bitmap_legacy);
7783 out1:
7784         free_page((unsigned long)vmx_io_bitmap_b);
7785 out:
7786         free_page((unsigned long)vmx_io_bitmap_a);
7787         return r;
7788 }
7789
7790 static void __exit vmx_exit(void)
7791 {
7792         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7793         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
7794         free_page((unsigned long)vmx_msr_bitmap_legacy);
7795         free_page((unsigned long)vmx_msr_bitmap_longmode);
7796         free_page((unsigned long)vmx_io_bitmap_b);
7797         free_page((unsigned long)vmx_io_bitmap_a);
7798
7799 #ifdef CONFIG_KEXEC
7800         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7801         synchronize_rcu();
7802 #endif
7803
7804         kvm_exit();
7805 }
7806
7807 module_init(vmx_init)
7808 module_exit(vmx_exit)