2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/trace_events.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
42 #include <asm/virtext.h>
44 #include <asm/fpu/internal.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
49 #include <asm/irq_remapping.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
55 #define __ex_clear(x, reg) \
56 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
58 MODULE_AUTHOR("Qumranet");
59 MODULE_LICENSE("GPL");
61 static const struct x86_cpu_id vmx_cpu_id[] = {
62 X86_FEATURE_MATCH(X86_FEATURE_VMX),
65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
67 static bool __read_mostly enable_vpid = 1;
68 module_param_named(vpid, enable_vpid, bool, 0444);
70 static bool __read_mostly flexpriority_enabled = 1;
71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
73 static bool __read_mostly enable_ept = 1;
74 module_param_named(ept, enable_ept, bool, S_IRUGO);
76 static bool __read_mostly enable_unrestricted_guest = 1;
77 module_param_named(unrestricted_guest,
78 enable_unrestricted_guest, bool, S_IRUGO);
80 static bool __read_mostly enable_ept_ad_bits = 1;
81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
83 static bool __read_mostly emulate_invalid_guest_state = true;
84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
86 static bool __read_mostly vmm_exclusive = 1;
87 module_param(vmm_exclusive, bool, S_IRUGO);
89 static bool __read_mostly fasteoi = 1;
90 module_param(fasteoi, bool, S_IRUGO);
92 static bool __read_mostly enable_apicv = 1;
93 module_param(enable_apicv, bool, S_IRUGO);
95 static bool __read_mostly enable_shadow_vmcs = 1;
96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested = 0;
103 module_param(nested, bool, S_IRUGO);
105 static u64 __read_mostly host_xss;
107 static bool __read_mostly enable_pml = 1;
108 module_param_named(pml, enable_pml, bool, S_IRUGO);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
114 #define KVM_VM_CR0_ALWAYS_ON \
115 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
116 #define KVM_CR4_GUEST_OWNED_BITS \
117 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
118 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
128 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
129 * ple_gap: upper bound on the amount of time between two successive
130 * executions of PAUSE in a loop. Also indicate if ple enabled.
131 * According to test, this time is usually smaller than 128 cycles.
132 * ple_window: upper bound on the amount of time a guest is allowed to execute
133 * in a PAUSE loop. Tests indicate that most spinlocks are held for
134 * less than 2^12 cycles
135 * Time is measured based on a counter that runs at the same rate as the TSC,
136 * refer SDM volume 3b section 21.6.13 & 22.1.3.
138 #define KVM_VMX_DEFAULT_PLE_GAP 128
139 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
143 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
146 module_param(ple_gap, int, S_IRUGO);
148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
149 module_param(ple_window, int, S_IRUGO);
151 /* Default doubles per-vcpu window every exit. */
152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
153 module_param(ple_window_grow, int, S_IRUGO);
155 /* Default resets per-vcpu window every exit to ple_window. */
156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
157 module_param(ple_window_shrink, int, S_IRUGO);
159 /* Default is to compute the maximum so we can never overflow. */
160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
161 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
162 module_param(ple_window_max, int, S_IRUGO);
164 extern const ulong vmx_return;
166 #define NR_AUTOLOAD_MSRS 8
167 #define VMCS02_POOL_SIZE 1
176 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
177 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
178 * loaded on this CPU (so we can clear them if the CPU goes down).
184 struct list_head loaded_vmcss_on_cpu_link;
187 struct shared_msr_entry {
194 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
195 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
196 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
197 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
198 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
199 * More than one of these structures may exist, if L1 runs multiple L2 guests.
200 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
201 * underlying hardware which will be used to run L2.
202 * This structure is packed to ensure that its layout is identical across
203 * machines (necessary for live migration).
204 * If there are changes in this struct, VMCS12_REVISION must be changed.
206 typedef u64 natural_width;
207 struct __packed vmcs12 {
208 /* According to the Intel spec, a VMCS region must start with the
209 * following two fields. Then follow implementation-specific data.
214 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
215 u32 padding[7]; /* room for future expansion */
220 u64 vm_exit_msr_store_addr;
221 u64 vm_exit_msr_load_addr;
222 u64 vm_entry_msr_load_addr;
224 u64 virtual_apic_page_addr;
225 u64 apic_access_addr;
226 u64 posted_intr_desc_addr;
228 u64 eoi_exit_bitmap0;
229 u64 eoi_exit_bitmap1;
230 u64 eoi_exit_bitmap2;
231 u64 eoi_exit_bitmap3;
233 u64 guest_physical_address;
234 u64 vmcs_link_pointer;
235 u64 guest_ia32_debugctl;
238 u64 guest_ia32_perf_global_ctrl;
246 u64 host_ia32_perf_global_ctrl;
247 u64 padding64[8]; /* room for future expansion */
249 * To allow migration of L1 (complete with its L2 guests) between
250 * machines of different natural widths (32 or 64 bit), we cannot have
251 * unsigned long fields with no explict size. We use u64 (aliased
252 * natural_width) instead. Luckily, x86 is little-endian.
254 natural_width cr0_guest_host_mask;
255 natural_width cr4_guest_host_mask;
256 natural_width cr0_read_shadow;
257 natural_width cr4_read_shadow;
258 natural_width cr3_target_value0;
259 natural_width cr3_target_value1;
260 natural_width cr3_target_value2;
261 natural_width cr3_target_value3;
262 natural_width exit_qualification;
263 natural_width guest_linear_address;
264 natural_width guest_cr0;
265 natural_width guest_cr3;
266 natural_width guest_cr4;
267 natural_width guest_es_base;
268 natural_width guest_cs_base;
269 natural_width guest_ss_base;
270 natural_width guest_ds_base;
271 natural_width guest_fs_base;
272 natural_width guest_gs_base;
273 natural_width guest_ldtr_base;
274 natural_width guest_tr_base;
275 natural_width guest_gdtr_base;
276 natural_width guest_idtr_base;
277 natural_width guest_dr7;
278 natural_width guest_rsp;
279 natural_width guest_rip;
280 natural_width guest_rflags;
281 natural_width guest_pending_dbg_exceptions;
282 natural_width guest_sysenter_esp;
283 natural_width guest_sysenter_eip;
284 natural_width host_cr0;
285 natural_width host_cr3;
286 natural_width host_cr4;
287 natural_width host_fs_base;
288 natural_width host_gs_base;
289 natural_width host_tr_base;
290 natural_width host_gdtr_base;
291 natural_width host_idtr_base;
292 natural_width host_ia32_sysenter_esp;
293 natural_width host_ia32_sysenter_eip;
294 natural_width host_rsp;
295 natural_width host_rip;
296 natural_width paddingl[8]; /* room for future expansion */
297 u32 pin_based_vm_exec_control;
298 u32 cpu_based_vm_exec_control;
299 u32 exception_bitmap;
300 u32 page_fault_error_code_mask;
301 u32 page_fault_error_code_match;
302 u32 cr3_target_count;
303 u32 vm_exit_controls;
304 u32 vm_exit_msr_store_count;
305 u32 vm_exit_msr_load_count;
306 u32 vm_entry_controls;
307 u32 vm_entry_msr_load_count;
308 u32 vm_entry_intr_info_field;
309 u32 vm_entry_exception_error_code;
310 u32 vm_entry_instruction_len;
312 u32 secondary_vm_exec_control;
313 u32 vm_instruction_error;
315 u32 vm_exit_intr_info;
316 u32 vm_exit_intr_error_code;
317 u32 idt_vectoring_info_field;
318 u32 idt_vectoring_error_code;
319 u32 vm_exit_instruction_len;
320 u32 vmx_instruction_info;
327 u32 guest_ldtr_limit;
329 u32 guest_gdtr_limit;
330 u32 guest_idtr_limit;
331 u32 guest_es_ar_bytes;
332 u32 guest_cs_ar_bytes;
333 u32 guest_ss_ar_bytes;
334 u32 guest_ds_ar_bytes;
335 u32 guest_fs_ar_bytes;
336 u32 guest_gs_ar_bytes;
337 u32 guest_ldtr_ar_bytes;
338 u32 guest_tr_ar_bytes;
339 u32 guest_interruptibility_info;
340 u32 guest_activity_state;
341 u32 guest_sysenter_cs;
342 u32 host_ia32_sysenter_cs;
343 u32 vmx_preemption_timer_value;
344 u32 padding32[7]; /* room for future expansion */
345 u16 virtual_processor_id;
347 u16 guest_es_selector;
348 u16 guest_cs_selector;
349 u16 guest_ss_selector;
350 u16 guest_ds_selector;
351 u16 guest_fs_selector;
352 u16 guest_gs_selector;
353 u16 guest_ldtr_selector;
354 u16 guest_tr_selector;
355 u16 guest_intr_status;
356 u16 host_es_selector;
357 u16 host_cs_selector;
358 u16 host_ss_selector;
359 u16 host_ds_selector;
360 u16 host_fs_selector;
361 u16 host_gs_selector;
362 u16 host_tr_selector;
366 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
367 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
368 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
370 #define VMCS12_REVISION 0x11e57ed0
373 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
374 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
375 * current implementation, 4K are reserved to avoid future complications.
377 #define VMCS12_SIZE 0x1000
379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
381 struct list_head list;
383 struct loaded_vmcs vmcs02;
387 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
388 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
391 /* Has the level1 guest done vmxon? */
395 /* The guest-physical address of the current VMCS L1 keeps for L2 */
397 /* The host-usable pointer to the above */
398 struct page *current_vmcs12_page;
399 struct vmcs12 *current_vmcs12;
400 struct vmcs *current_shadow_vmcs;
402 * Indicates if the shadow vmcs must be updated with the
403 * data hold by vmcs12
405 bool sync_shadow_vmcs;
407 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
408 struct list_head vmcs02_pool;
410 u64 vmcs01_tsc_offset;
411 /* L2 must run next, and mustn't decide to exit to L1. */
412 bool nested_run_pending;
414 * Guest pages referred to in vmcs02 with host-physical pointers, so
415 * we must keep them pinned while L2 runs.
417 struct page *apic_access_page;
418 struct page *virtual_apic_page;
419 struct page *pi_desc_page;
420 struct pi_desc *pi_desc;
423 u64 msr_ia32_feature_control;
425 struct hrtimer preemption_timer;
426 bool preemption_timer_expired;
428 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
434 u32 nested_vmx_procbased_ctls_low;
435 u32 nested_vmx_procbased_ctls_high;
436 u32 nested_vmx_true_procbased_ctls_low;
437 u32 nested_vmx_secondary_ctls_low;
438 u32 nested_vmx_secondary_ctls_high;
439 u32 nested_vmx_pinbased_ctls_low;
440 u32 nested_vmx_pinbased_ctls_high;
441 u32 nested_vmx_exit_ctls_low;
442 u32 nested_vmx_exit_ctls_high;
443 u32 nested_vmx_true_exit_ctls_low;
444 u32 nested_vmx_entry_ctls_low;
445 u32 nested_vmx_entry_ctls_high;
446 u32 nested_vmx_true_entry_ctls_low;
447 u32 nested_vmx_misc_low;
448 u32 nested_vmx_misc_high;
449 u32 nested_vmx_ept_caps;
450 u32 nested_vmx_vpid_caps;
453 #define POSTED_INTR_ON 0
454 #define POSTED_INTR_SN 1
456 /* Posted-Interrupt Descriptor */
458 u32 pir[8]; /* Posted interrupt requested */
461 /* bit 256 - Outstanding Notification */
463 /* bit 257 - Suppress Notification */
465 /* bit 271:258 - Reserved */
467 /* bit 279:272 - Notification Vector */
469 /* bit 287:280 - Reserved */
471 /* bit 319:288 - Notification Destination */
479 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
481 return test_and_set_bit(POSTED_INTR_ON,
482 (unsigned long *)&pi_desc->control);
485 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
487 return test_and_clear_bit(POSTED_INTR_ON,
488 (unsigned long *)&pi_desc->control);
491 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
493 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
496 static inline void pi_clear_sn(struct pi_desc *pi_desc)
498 return clear_bit(POSTED_INTR_SN,
499 (unsigned long *)&pi_desc->control);
502 static inline void pi_set_sn(struct pi_desc *pi_desc)
504 return set_bit(POSTED_INTR_SN,
505 (unsigned long *)&pi_desc->control);
508 static inline int pi_test_on(struct pi_desc *pi_desc)
510 return test_bit(POSTED_INTR_ON,
511 (unsigned long *)&pi_desc->control);
514 static inline int pi_test_sn(struct pi_desc *pi_desc)
516 return test_bit(POSTED_INTR_SN,
517 (unsigned long *)&pi_desc->control);
521 struct kvm_vcpu vcpu;
522 unsigned long host_rsp;
524 bool nmi_known_unmasked;
526 u32 idt_vectoring_info;
528 struct shared_msr_entry *guest_msrs;
531 unsigned long host_idt_base;
533 u64 msr_host_kernel_gs_base;
534 u64 msr_guest_kernel_gs_base;
536 u32 vm_entry_controls_shadow;
537 u32 vm_exit_controls_shadow;
539 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
540 * non-nested (L1) guest, it always points to vmcs01. For a nested
541 * guest (L2), it points to a different VMCS.
543 struct loaded_vmcs vmcs01;
544 struct loaded_vmcs *loaded_vmcs;
545 bool __launched; /* temporary, used in vmx_vcpu_run */
546 struct msr_autoload {
548 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
549 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
553 u16 fs_sel, gs_sel, ldt_sel;
557 int gs_ldt_reload_needed;
558 int fs_reload_needed;
559 u64 msr_host_bndcfgs;
560 unsigned long vmcs_host_cr4; /* May not match real cr4 */
565 struct kvm_segment segs[8];
568 u32 bitmask; /* 4 bits per segment (1 bit per field) */
569 struct kvm_save_segment {
577 bool emulation_required;
579 /* Support for vnmi-less CPUs */
580 int soft_vnmi_blocked;
582 s64 vnmi_blocked_time;
585 /* Posted interrupt descriptor */
586 struct pi_desc pi_desc;
588 /* Support for a guest hypervisor (nested VMX) */
589 struct nested_vmx nested;
591 /* Dynamic PLE window. */
593 bool ple_window_dirty;
595 /* Support for PML */
596 #define PML_ENTITY_NUM 512
600 enum segment_cache_field {
609 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
611 return container_of(vcpu, struct vcpu_vmx, vcpu);
614 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
616 return &(to_vmx(vcpu)->pi_desc);
619 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
620 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
621 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
622 [number##_HIGH] = VMCS12_OFFSET(name)+4
625 static unsigned long shadow_read_only_fields[] = {
627 * We do NOT shadow fields that are modified when L0
628 * traps and emulates any vmx instruction (e.g. VMPTRLD,
629 * VMXON...) executed by L1.
630 * For example, VM_INSTRUCTION_ERROR is read
631 * by L1 if a vmx instruction fails (part of the error path).
632 * Note the code assumes this logic. If for some reason
633 * we start shadowing these fields then we need to
634 * force a shadow sync when L0 emulates vmx instructions
635 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
636 * by nested_vmx_failValid)
640 VM_EXIT_INSTRUCTION_LEN,
641 IDT_VECTORING_INFO_FIELD,
642 IDT_VECTORING_ERROR_CODE,
643 VM_EXIT_INTR_ERROR_CODE,
645 GUEST_LINEAR_ADDRESS,
646 GUEST_PHYSICAL_ADDRESS
648 static int max_shadow_read_only_fields =
649 ARRAY_SIZE(shadow_read_only_fields);
651 static unsigned long shadow_read_write_fields[] = {
658 GUEST_INTERRUPTIBILITY_INFO,
671 CPU_BASED_VM_EXEC_CONTROL,
672 VM_ENTRY_EXCEPTION_ERROR_CODE,
673 VM_ENTRY_INTR_INFO_FIELD,
674 VM_ENTRY_INSTRUCTION_LEN,
675 VM_ENTRY_EXCEPTION_ERROR_CODE,
681 static int max_shadow_read_write_fields =
682 ARRAY_SIZE(shadow_read_write_fields);
684 static const unsigned short vmcs_field_to_offset_table[] = {
685 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
686 FIELD(POSTED_INTR_NV, posted_intr_nv),
687 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
688 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
689 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
690 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
691 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
692 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
693 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
694 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
695 FIELD(GUEST_INTR_STATUS, guest_intr_status),
696 FIELD(HOST_ES_SELECTOR, host_es_selector),
697 FIELD(HOST_CS_SELECTOR, host_cs_selector),
698 FIELD(HOST_SS_SELECTOR, host_ss_selector),
699 FIELD(HOST_DS_SELECTOR, host_ds_selector),
700 FIELD(HOST_FS_SELECTOR, host_fs_selector),
701 FIELD(HOST_GS_SELECTOR, host_gs_selector),
702 FIELD(HOST_TR_SELECTOR, host_tr_selector),
703 FIELD64(IO_BITMAP_A, io_bitmap_a),
704 FIELD64(IO_BITMAP_B, io_bitmap_b),
705 FIELD64(MSR_BITMAP, msr_bitmap),
706 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
707 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
708 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
709 FIELD64(TSC_OFFSET, tsc_offset),
710 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
711 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
712 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
713 FIELD64(EPT_POINTER, ept_pointer),
714 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
715 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
716 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
717 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
718 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
719 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
720 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
721 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
722 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
723 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
724 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
725 FIELD64(GUEST_PDPTR0, guest_pdptr0),
726 FIELD64(GUEST_PDPTR1, guest_pdptr1),
727 FIELD64(GUEST_PDPTR2, guest_pdptr2),
728 FIELD64(GUEST_PDPTR3, guest_pdptr3),
729 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
730 FIELD64(HOST_IA32_PAT, host_ia32_pat),
731 FIELD64(HOST_IA32_EFER, host_ia32_efer),
732 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
733 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
734 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
735 FIELD(EXCEPTION_BITMAP, exception_bitmap),
736 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
737 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
738 FIELD(CR3_TARGET_COUNT, cr3_target_count),
739 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
740 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
741 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
742 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
743 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
744 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
745 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
746 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
747 FIELD(TPR_THRESHOLD, tpr_threshold),
748 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
749 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
750 FIELD(VM_EXIT_REASON, vm_exit_reason),
751 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
752 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
753 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
754 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
755 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
756 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
757 FIELD(GUEST_ES_LIMIT, guest_es_limit),
758 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
759 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
760 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
761 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
762 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
763 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
764 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
765 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
766 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
767 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
768 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
769 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
770 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
771 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
772 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
773 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
774 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
775 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
776 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
777 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
778 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
779 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
780 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
781 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
782 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
783 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
784 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
785 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
786 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
787 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
788 FIELD(EXIT_QUALIFICATION, exit_qualification),
789 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
790 FIELD(GUEST_CR0, guest_cr0),
791 FIELD(GUEST_CR3, guest_cr3),
792 FIELD(GUEST_CR4, guest_cr4),
793 FIELD(GUEST_ES_BASE, guest_es_base),
794 FIELD(GUEST_CS_BASE, guest_cs_base),
795 FIELD(GUEST_SS_BASE, guest_ss_base),
796 FIELD(GUEST_DS_BASE, guest_ds_base),
797 FIELD(GUEST_FS_BASE, guest_fs_base),
798 FIELD(GUEST_GS_BASE, guest_gs_base),
799 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
800 FIELD(GUEST_TR_BASE, guest_tr_base),
801 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
802 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
803 FIELD(GUEST_DR7, guest_dr7),
804 FIELD(GUEST_RSP, guest_rsp),
805 FIELD(GUEST_RIP, guest_rip),
806 FIELD(GUEST_RFLAGS, guest_rflags),
807 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
808 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
809 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
810 FIELD(HOST_CR0, host_cr0),
811 FIELD(HOST_CR3, host_cr3),
812 FIELD(HOST_CR4, host_cr4),
813 FIELD(HOST_FS_BASE, host_fs_base),
814 FIELD(HOST_GS_BASE, host_gs_base),
815 FIELD(HOST_TR_BASE, host_tr_base),
816 FIELD(HOST_GDTR_BASE, host_gdtr_base),
817 FIELD(HOST_IDTR_BASE, host_idtr_base),
818 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
819 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
820 FIELD(HOST_RSP, host_rsp),
821 FIELD(HOST_RIP, host_rip),
824 static inline short vmcs_field_to_offset(unsigned long field)
826 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
828 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
829 vmcs_field_to_offset_table[field] == 0)
832 return vmcs_field_to_offset_table[field];
835 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
837 return to_vmx(vcpu)->nested.current_vmcs12;
840 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
842 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
843 if (is_error_page(page))
849 static void nested_release_page(struct page *page)
851 kvm_release_page_dirty(page);
854 static void nested_release_page_clean(struct page *page)
856 kvm_release_page_clean(page);
859 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
860 static u64 construct_eptp(unsigned long root_hpa);
861 static void kvm_cpu_vmxon(u64 addr);
862 static void kvm_cpu_vmxoff(void);
863 static bool vmx_mpx_supported(void);
864 static bool vmx_xsaves_supported(void);
865 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
866 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
867 static void vmx_set_segment(struct kvm_vcpu *vcpu,
868 struct kvm_segment *var, int seg);
869 static void vmx_get_segment(struct kvm_vcpu *vcpu,
870 struct kvm_segment *var, int seg);
871 static bool guest_state_valid(struct kvm_vcpu *vcpu);
872 static u32 vmx_segment_access_rights(struct kvm_segment *var);
873 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
874 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
875 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
876 static int alloc_identity_pagetable(struct kvm *kvm);
878 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
879 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
881 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
882 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
884 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
885 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
888 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
889 * can find which vCPU should be waken up.
891 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
892 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
894 static unsigned long *vmx_io_bitmap_a;
895 static unsigned long *vmx_io_bitmap_b;
896 static unsigned long *vmx_msr_bitmap_legacy;
897 static unsigned long *vmx_msr_bitmap_longmode;
898 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
899 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
900 static unsigned long *vmx_msr_bitmap_nested;
901 static unsigned long *vmx_vmread_bitmap;
902 static unsigned long *vmx_vmwrite_bitmap;
904 static bool cpu_has_load_ia32_efer;
905 static bool cpu_has_load_perf_global_ctrl;
907 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
908 static DEFINE_SPINLOCK(vmx_vpid_lock);
910 static struct vmcs_config {
914 u32 pin_based_exec_ctrl;
915 u32 cpu_based_exec_ctrl;
916 u32 cpu_based_2nd_exec_ctrl;
921 static struct vmx_capability {
926 #define VMX_SEGMENT_FIELD(seg) \
927 [VCPU_SREG_##seg] = { \
928 .selector = GUEST_##seg##_SELECTOR, \
929 .base = GUEST_##seg##_BASE, \
930 .limit = GUEST_##seg##_LIMIT, \
931 .ar_bytes = GUEST_##seg##_AR_BYTES, \
934 static const struct kvm_vmx_segment_field {
939 } kvm_vmx_segment_fields[] = {
940 VMX_SEGMENT_FIELD(CS),
941 VMX_SEGMENT_FIELD(DS),
942 VMX_SEGMENT_FIELD(ES),
943 VMX_SEGMENT_FIELD(FS),
944 VMX_SEGMENT_FIELD(GS),
945 VMX_SEGMENT_FIELD(SS),
946 VMX_SEGMENT_FIELD(TR),
947 VMX_SEGMENT_FIELD(LDTR),
950 static u64 host_efer;
952 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
955 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
956 * away by decrementing the array size.
958 static const u32 vmx_msr_index[] = {
960 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
962 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
965 static inline bool is_page_fault(u32 intr_info)
967 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
968 INTR_INFO_VALID_MASK)) ==
969 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
972 static inline bool is_no_device(u32 intr_info)
974 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
975 INTR_INFO_VALID_MASK)) ==
976 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
979 static inline bool is_invalid_opcode(u32 intr_info)
981 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
982 INTR_INFO_VALID_MASK)) ==
983 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
986 static inline bool is_external_interrupt(u32 intr_info)
988 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
989 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
992 static inline bool is_machine_check(u32 intr_info)
994 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
995 INTR_INFO_VALID_MASK)) ==
996 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
999 static inline bool cpu_has_vmx_msr_bitmap(void)
1001 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1004 static inline bool cpu_has_vmx_tpr_shadow(void)
1006 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1009 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1011 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1014 static inline bool cpu_has_secondary_exec_ctrls(void)
1016 return vmcs_config.cpu_based_exec_ctrl &
1017 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1020 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1026 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1028 return vmcs_config.cpu_based_2nd_exec_ctrl &
1029 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1032 static inline bool cpu_has_vmx_apic_register_virt(void)
1034 return vmcs_config.cpu_based_2nd_exec_ctrl &
1035 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1038 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1040 return vmcs_config.cpu_based_2nd_exec_ctrl &
1041 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1044 static inline bool cpu_has_vmx_posted_intr(void)
1046 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1047 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1050 static inline bool cpu_has_vmx_apicv(void)
1052 return cpu_has_vmx_apic_register_virt() &&
1053 cpu_has_vmx_virtual_intr_delivery() &&
1054 cpu_has_vmx_posted_intr();
1057 static inline bool cpu_has_vmx_flexpriority(void)
1059 return cpu_has_vmx_tpr_shadow() &&
1060 cpu_has_vmx_virtualize_apic_accesses();
1063 static inline bool cpu_has_vmx_ept_execute_only(void)
1065 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1068 static inline bool cpu_has_vmx_ept_2m_page(void)
1070 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1073 static inline bool cpu_has_vmx_ept_1g_page(void)
1075 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1078 static inline bool cpu_has_vmx_ept_4levels(void)
1080 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1083 static inline bool cpu_has_vmx_ept_ad_bits(void)
1085 return vmx_capability.ept & VMX_EPT_AD_BIT;
1088 static inline bool cpu_has_vmx_invept_context(void)
1090 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1093 static inline bool cpu_has_vmx_invept_global(void)
1095 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1098 static inline bool cpu_has_vmx_invvpid_single(void)
1100 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1103 static inline bool cpu_has_vmx_invvpid_global(void)
1105 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1108 static inline bool cpu_has_vmx_ept(void)
1110 return vmcs_config.cpu_based_2nd_exec_ctrl &
1111 SECONDARY_EXEC_ENABLE_EPT;
1114 static inline bool cpu_has_vmx_unrestricted_guest(void)
1116 return vmcs_config.cpu_based_2nd_exec_ctrl &
1117 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1120 static inline bool cpu_has_vmx_ple(void)
1122 return vmcs_config.cpu_based_2nd_exec_ctrl &
1123 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1126 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1128 return flexpriority_enabled && lapic_in_kernel(vcpu);
1131 static inline bool cpu_has_vmx_vpid(void)
1133 return vmcs_config.cpu_based_2nd_exec_ctrl &
1134 SECONDARY_EXEC_ENABLE_VPID;
1137 static inline bool cpu_has_vmx_rdtscp(void)
1139 return vmcs_config.cpu_based_2nd_exec_ctrl &
1140 SECONDARY_EXEC_RDTSCP;
1143 static inline bool cpu_has_vmx_invpcid(void)
1145 return vmcs_config.cpu_based_2nd_exec_ctrl &
1146 SECONDARY_EXEC_ENABLE_INVPCID;
1149 static inline bool cpu_has_virtual_nmis(void)
1151 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1154 static inline bool cpu_has_vmx_wbinvd_exit(void)
1156 return vmcs_config.cpu_based_2nd_exec_ctrl &
1157 SECONDARY_EXEC_WBINVD_EXITING;
1160 static inline bool cpu_has_vmx_shadow_vmcs(void)
1163 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1164 /* check if the cpu supports writing r/o exit information fields */
1165 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1168 return vmcs_config.cpu_based_2nd_exec_ctrl &
1169 SECONDARY_EXEC_SHADOW_VMCS;
1172 static inline bool cpu_has_vmx_pml(void)
1174 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1177 static inline bool cpu_has_vmx_tsc_scaling(void)
1179 return vmcs_config.cpu_based_2nd_exec_ctrl &
1180 SECONDARY_EXEC_TSC_SCALING;
1183 static inline bool report_flexpriority(void)
1185 return flexpriority_enabled;
1188 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1190 return vmcs12->cpu_based_vm_exec_control & bit;
1193 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1195 return (vmcs12->cpu_based_vm_exec_control &
1196 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1197 (vmcs12->secondary_vm_exec_control & bit);
1200 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1202 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1205 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1207 return vmcs12->pin_based_vm_exec_control &
1208 PIN_BASED_VMX_PREEMPTION_TIMER;
1211 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1213 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1216 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1218 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1219 vmx_xsaves_supported();
1222 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1224 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1227 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1229 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1232 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1234 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1237 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1239 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1242 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1244 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1247 static inline bool is_exception(u32 intr_info)
1249 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1250 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1253 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1255 unsigned long exit_qualification);
1256 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1257 struct vmcs12 *vmcs12,
1258 u32 reason, unsigned long qualification);
1260 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1264 for (i = 0; i < vmx->nmsrs; ++i)
1265 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1270 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1276 } operand = { vpid, 0, gva };
1278 asm volatile (__ex(ASM_VMX_INVVPID)
1279 /* CF==1 or ZF==1 --> rc = -1 */
1280 "; ja 1f ; ud2 ; 1:"
1281 : : "a"(&operand), "c"(ext) : "cc", "memory");
1284 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1288 } operand = {eptp, gpa};
1290 asm volatile (__ex(ASM_VMX_INVEPT)
1291 /* CF==1 or ZF==1 --> rc = -1 */
1292 "; ja 1f ; ud2 ; 1:\n"
1293 : : "a" (&operand), "c" (ext) : "cc", "memory");
1296 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1300 i = __find_msr_index(vmx, msr);
1302 return &vmx->guest_msrs[i];
1306 static void vmcs_clear(struct vmcs *vmcs)
1308 u64 phys_addr = __pa(vmcs);
1311 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1312 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1315 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1319 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1321 vmcs_clear(loaded_vmcs->vmcs);
1322 loaded_vmcs->cpu = -1;
1323 loaded_vmcs->launched = 0;
1326 static void vmcs_load(struct vmcs *vmcs)
1328 u64 phys_addr = __pa(vmcs);
1331 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1332 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1335 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1339 #ifdef CONFIG_KEXEC_CORE
1341 * This bitmap is used to indicate whether the vmclear
1342 * operation is enabled on all cpus. All disabled by
1345 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1347 static inline void crash_enable_local_vmclear(int cpu)
1349 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1352 static inline void crash_disable_local_vmclear(int cpu)
1354 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1357 static inline int crash_local_vmclear_enabled(int cpu)
1359 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1362 static void crash_vmclear_local_loaded_vmcss(void)
1364 int cpu = raw_smp_processor_id();
1365 struct loaded_vmcs *v;
1367 if (!crash_local_vmclear_enabled(cpu))
1370 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1371 loaded_vmcss_on_cpu_link)
1372 vmcs_clear(v->vmcs);
1375 static inline void crash_enable_local_vmclear(int cpu) { }
1376 static inline void crash_disable_local_vmclear(int cpu) { }
1377 #endif /* CONFIG_KEXEC_CORE */
1379 static void __loaded_vmcs_clear(void *arg)
1381 struct loaded_vmcs *loaded_vmcs = arg;
1382 int cpu = raw_smp_processor_id();
1384 if (loaded_vmcs->cpu != cpu)
1385 return; /* vcpu migration can race with cpu offline */
1386 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1387 per_cpu(current_vmcs, cpu) = NULL;
1388 crash_disable_local_vmclear(cpu);
1389 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1392 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1393 * is before setting loaded_vmcs->vcpu to -1 which is done in
1394 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1395 * then adds the vmcs into percpu list before it is deleted.
1399 loaded_vmcs_init(loaded_vmcs);
1400 crash_enable_local_vmclear(cpu);
1403 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1405 int cpu = loaded_vmcs->cpu;
1408 smp_call_function_single(cpu,
1409 __loaded_vmcs_clear, loaded_vmcs, 1);
1412 static inline void vpid_sync_vcpu_single(int vpid)
1417 if (cpu_has_vmx_invvpid_single())
1418 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1421 static inline void vpid_sync_vcpu_global(void)
1423 if (cpu_has_vmx_invvpid_global())
1424 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1427 static inline void vpid_sync_context(int vpid)
1429 if (cpu_has_vmx_invvpid_single())
1430 vpid_sync_vcpu_single(vpid);
1432 vpid_sync_vcpu_global();
1435 static inline void ept_sync_global(void)
1437 if (cpu_has_vmx_invept_global())
1438 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1441 static inline void ept_sync_context(u64 eptp)
1444 if (cpu_has_vmx_invept_context())
1445 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1451 static __always_inline unsigned long vmcs_readl(unsigned long field)
1453 unsigned long value;
1455 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1456 : "=a"(value) : "d"(field) : "cc");
1460 static __always_inline u16 vmcs_read16(unsigned long field)
1462 return vmcs_readl(field);
1465 static __always_inline u32 vmcs_read32(unsigned long field)
1467 return vmcs_readl(field);
1470 static __always_inline u64 vmcs_read64(unsigned long field)
1472 #ifdef CONFIG_X86_64
1473 return vmcs_readl(field);
1475 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1479 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1481 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1482 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1486 static void vmcs_writel(unsigned long field, unsigned long value)
1490 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1491 : "=q"(error) : "a"(value), "d"(field) : "cc");
1492 if (unlikely(error))
1493 vmwrite_error(field, value);
1496 static void vmcs_write16(unsigned long field, u16 value)
1498 vmcs_writel(field, value);
1501 static void vmcs_write32(unsigned long field, u32 value)
1503 vmcs_writel(field, value);
1506 static void vmcs_write64(unsigned long field, u64 value)
1508 vmcs_writel(field, value);
1509 #ifndef CONFIG_X86_64
1511 vmcs_writel(field+1, value >> 32);
1515 static void vmcs_clear_bits(unsigned long field, u32 mask)
1517 vmcs_writel(field, vmcs_readl(field) & ~mask);
1520 static void vmcs_set_bits(unsigned long field, u32 mask)
1522 vmcs_writel(field, vmcs_readl(field) | mask);
1525 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1527 vmcs_write32(VM_ENTRY_CONTROLS, val);
1528 vmx->vm_entry_controls_shadow = val;
1531 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1533 if (vmx->vm_entry_controls_shadow != val)
1534 vm_entry_controls_init(vmx, val);
1537 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1539 return vmx->vm_entry_controls_shadow;
1543 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1545 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1548 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1550 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1553 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1555 vmcs_write32(VM_EXIT_CONTROLS, val);
1556 vmx->vm_exit_controls_shadow = val;
1559 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1561 if (vmx->vm_exit_controls_shadow != val)
1562 vm_exit_controls_init(vmx, val);
1565 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1567 return vmx->vm_exit_controls_shadow;
1571 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1573 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1576 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1578 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1581 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1583 vmx->segment_cache.bitmask = 0;
1586 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1590 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1592 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1593 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1594 vmx->segment_cache.bitmask = 0;
1596 ret = vmx->segment_cache.bitmask & mask;
1597 vmx->segment_cache.bitmask |= mask;
1601 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1603 u16 *p = &vmx->segment_cache.seg[seg].selector;
1605 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1606 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1610 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1612 ulong *p = &vmx->segment_cache.seg[seg].base;
1614 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1615 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1619 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1621 u32 *p = &vmx->segment_cache.seg[seg].limit;
1623 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1624 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1628 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1630 u32 *p = &vmx->segment_cache.seg[seg].ar;
1632 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1633 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1637 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1641 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1642 (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1643 if ((vcpu->guest_debug &
1644 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1645 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1646 eb |= 1u << BP_VECTOR;
1647 if (to_vmx(vcpu)->rmode.vm86_active)
1650 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1651 if (vcpu->fpu_active)
1652 eb &= ~(1u << NM_VECTOR);
1654 /* When we are running a nested L2 guest and L1 specified for it a
1655 * certain exception bitmap, we must trap the same exceptions and pass
1656 * them to L1. When running L2, we will only handle the exceptions
1657 * specified above if L1 did not want them.
1659 if (is_guest_mode(vcpu))
1660 eb |= get_vmcs12(vcpu)->exception_bitmap;
1662 vmcs_write32(EXCEPTION_BITMAP, eb);
1665 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1666 unsigned long entry, unsigned long exit)
1668 vm_entry_controls_clearbit(vmx, entry);
1669 vm_exit_controls_clearbit(vmx, exit);
1672 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1675 struct msr_autoload *m = &vmx->msr_autoload;
1679 if (cpu_has_load_ia32_efer) {
1680 clear_atomic_switch_msr_special(vmx,
1681 VM_ENTRY_LOAD_IA32_EFER,
1682 VM_EXIT_LOAD_IA32_EFER);
1686 case MSR_CORE_PERF_GLOBAL_CTRL:
1687 if (cpu_has_load_perf_global_ctrl) {
1688 clear_atomic_switch_msr_special(vmx,
1689 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1690 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1696 for (i = 0; i < m->nr; ++i)
1697 if (m->guest[i].index == msr)
1703 m->guest[i] = m->guest[m->nr];
1704 m->host[i] = m->host[m->nr];
1705 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1706 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1709 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1710 unsigned long entry, unsigned long exit,
1711 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1712 u64 guest_val, u64 host_val)
1714 vmcs_write64(guest_val_vmcs, guest_val);
1715 vmcs_write64(host_val_vmcs, host_val);
1716 vm_entry_controls_setbit(vmx, entry);
1717 vm_exit_controls_setbit(vmx, exit);
1720 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1721 u64 guest_val, u64 host_val)
1724 struct msr_autoload *m = &vmx->msr_autoload;
1728 if (cpu_has_load_ia32_efer) {
1729 add_atomic_switch_msr_special(vmx,
1730 VM_ENTRY_LOAD_IA32_EFER,
1731 VM_EXIT_LOAD_IA32_EFER,
1734 guest_val, host_val);
1738 case MSR_CORE_PERF_GLOBAL_CTRL:
1739 if (cpu_has_load_perf_global_ctrl) {
1740 add_atomic_switch_msr_special(vmx,
1741 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1742 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1743 GUEST_IA32_PERF_GLOBAL_CTRL,
1744 HOST_IA32_PERF_GLOBAL_CTRL,
1745 guest_val, host_val);
1751 for (i = 0; i < m->nr; ++i)
1752 if (m->guest[i].index == msr)
1755 if (i == NR_AUTOLOAD_MSRS) {
1756 printk_once(KERN_WARNING "Not enough msr switch entries. "
1757 "Can't add msr %x\n", msr);
1759 } else if (i == m->nr) {
1761 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1762 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1765 m->guest[i].index = msr;
1766 m->guest[i].value = guest_val;
1767 m->host[i].index = msr;
1768 m->host[i].value = host_val;
1771 static void reload_tss(void)
1774 * VT restores TR but not its size. Useless.
1776 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1777 struct desc_struct *descs;
1779 descs = (void *)gdt->address;
1780 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1784 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1789 guest_efer = vmx->vcpu.arch.efer;
1792 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1795 ignore_bits = EFER_NX | EFER_SCE;
1796 #ifdef CONFIG_X86_64
1797 ignore_bits |= EFER_LMA | EFER_LME;
1798 /* SCE is meaningful only in long mode on Intel */
1799 if (guest_efer & EFER_LMA)
1800 ignore_bits &= ~(u64)EFER_SCE;
1802 guest_efer &= ~ignore_bits;
1803 guest_efer |= host_efer & ignore_bits;
1804 vmx->guest_msrs[efer_offset].data = guest_efer;
1805 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1807 clear_atomic_switch_msr(vmx, MSR_EFER);
1810 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1811 * On CPUs that support "load IA32_EFER", always switch EFER
1812 * atomically, since it's faster than switching it manually.
1814 if (cpu_has_load_ia32_efer ||
1815 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1816 guest_efer = vmx->vcpu.arch.efer;
1817 if (!(guest_efer & EFER_LMA))
1818 guest_efer &= ~EFER_LME;
1819 if (guest_efer != host_efer)
1820 add_atomic_switch_msr(vmx, MSR_EFER,
1821 guest_efer, host_efer);
1828 static unsigned long segment_base(u16 selector)
1830 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1831 struct desc_struct *d;
1832 unsigned long table_base;
1835 if (!(selector & ~3))
1838 table_base = gdt->address;
1840 if (selector & 4) { /* from ldt */
1841 u16 ldt_selector = kvm_read_ldt();
1843 if (!(ldt_selector & ~3))
1846 table_base = segment_base(ldt_selector);
1848 d = (struct desc_struct *)(table_base + (selector & ~7));
1849 v = get_desc_base(d);
1850 #ifdef CONFIG_X86_64
1851 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1852 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1857 static inline unsigned long kvm_read_tr_base(void)
1860 asm("str %0" : "=g"(tr));
1861 return segment_base(tr);
1864 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1866 struct vcpu_vmx *vmx = to_vmx(vcpu);
1869 if (vmx->host_state.loaded)
1872 vmx->host_state.loaded = 1;
1874 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1875 * allow segment selectors with cpl > 0 or ti == 1.
1877 vmx->host_state.ldt_sel = kvm_read_ldt();
1878 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1879 savesegment(fs, vmx->host_state.fs_sel);
1880 if (!(vmx->host_state.fs_sel & 7)) {
1881 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1882 vmx->host_state.fs_reload_needed = 0;
1884 vmcs_write16(HOST_FS_SELECTOR, 0);
1885 vmx->host_state.fs_reload_needed = 1;
1887 savesegment(gs, vmx->host_state.gs_sel);
1888 if (!(vmx->host_state.gs_sel & 7))
1889 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1891 vmcs_write16(HOST_GS_SELECTOR, 0);
1892 vmx->host_state.gs_ldt_reload_needed = 1;
1895 #ifdef CONFIG_X86_64
1896 savesegment(ds, vmx->host_state.ds_sel);
1897 savesegment(es, vmx->host_state.es_sel);
1900 #ifdef CONFIG_X86_64
1901 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1902 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1904 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1905 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1908 #ifdef CONFIG_X86_64
1909 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1910 if (is_long_mode(&vmx->vcpu))
1911 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1913 if (boot_cpu_has(X86_FEATURE_MPX))
1914 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1915 for (i = 0; i < vmx->save_nmsrs; ++i)
1916 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1917 vmx->guest_msrs[i].data,
1918 vmx->guest_msrs[i].mask);
1921 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1923 if (!vmx->host_state.loaded)
1926 ++vmx->vcpu.stat.host_state_reload;
1927 vmx->host_state.loaded = 0;
1928 #ifdef CONFIG_X86_64
1929 if (is_long_mode(&vmx->vcpu))
1930 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1932 if (vmx->host_state.gs_ldt_reload_needed) {
1933 kvm_load_ldt(vmx->host_state.ldt_sel);
1934 #ifdef CONFIG_X86_64
1935 load_gs_index(vmx->host_state.gs_sel);
1937 loadsegment(gs, vmx->host_state.gs_sel);
1940 if (vmx->host_state.fs_reload_needed)
1941 loadsegment(fs, vmx->host_state.fs_sel);
1942 #ifdef CONFIG_X86_64
1943 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1944 loadsegment(ds, vmx->host_state.ds_sel);
1945 loadsegment(es, vmx->host_state.es_sel);
1949 #ifdef CONFIG_X86_64
1950 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1952 if (vmx->host_state.msr_host_bndcfgs)
1953 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1955 * If the FPU is not active (through the host task or
1956 * the guest vcpu), then restore the cr0.TS bit.
1958 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1960 load_gdt(this_cpu_ptr(&host_gdt));
1963 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1966 __vmx_load_host_state(vmx);
1970 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1972 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1973 struct pi_desc old, new;
1976 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1977 !irq_remapping_cap(IRQ_POSTING_CAP))
1981 old.control = new.control = pi_desc->control;
1984 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1985 * are two possible cases:
1986 * 1. After running 'pre_block', context switch
1987 * happened. For this case, 'sn' was set in
1988 * vmx_vcpu_put(), so we need to clear it here.
1989 * 2. After running 'pre_block', we were blocked,
1990 * and woken up by some other guy. For this case,
1991 * we don't need to do anything, 'pi_post_block'
1992 * will do everything for us. However, we cannot
1993 * check whether it is case #1 or case #2 here
1994 * (maybe, not needed), so we also clear sn here,
1995 * I think it is not a big deal.
1997 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
1998 if (vcpu->cpu != cpu) {
1999 dest = cpu_physical_id(cpu);
2001 if (x2apic_enabled())
2004 new.ndst = (dest << 8) & 0xFF00;
2007 /* set 'NV' to 'notification vector' */
2008 new.nv = POSTED_INTR_VECTOR;
2011 /* Allow posting non-urgent interrupts */
2013 } while (cmpxchg(&pi_desc->control, old.control,
2014 new.control) != old.control);
2017 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2018 * vcpu mutex is already taken.
2020 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2022 struct vcpu_vmx *vmx = to_vmx(vcpu);
2023 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2026 kvm_cpu_vmxon(phys_addr);
2027 else if (vmx->loaded_vmcs->cpu != cpu)
2028 loaded_vmcs_clear(vmx->loaded_vmcs);
2030 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2031 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2032 vmcs_load(vmx->loaded_vmcs->vmcs);
2035 if (vmx->loaded_vmcs->cpu != cpu) {
2036 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2037 unsigned long sysenter_esp;
2039 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2040 local_irq_disable();
2041 crash_disable_local_vmclear(cpu);
2044 * Read loaded_vmcs->cpu should be before fetching
2045 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2046 * See the comments in __loaded_vmcs_clear().
2050 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2051 &per_cpu(loaded_vmcss_on_cpu, cpu));
2052 crash_enable_local_vmclear(cpu);
2056 * Linux uses per-cpu TSS and GDT, so set these when switching
2059 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2060 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
2062 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2063 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2065 /* Setup TSC multiplier */
2066 if (cpu_has_vmx_tsc_scaling())
2067 vmcs_write64(TSC_MULTIPLIER,
2068 vcpu->arch.tsc_scaling_ratio);
2070 vmx->loaded_vmcs->cpu = cpu;
2073 vmx_vcpu_pi_load(vcpu, cpu);
2076 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2078 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2080 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2081 !irq_remapping_cap(IRQ_POSTING_CAP))
2084 /* Set SN when the vCPU is preempted */
2085 if (vcpu->preempted)
2089 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2091 vmx_vcpu_pi_put(vcpu);
2093 __vmx_load_host_state(to_vmx(vcpu));
2094 if (!vmm_exclusive) {
2095 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2101 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2105 if (vcpu->fpu_active)
2107 vcpu->fpu_active = 1;
2108 cr0 = vmcs_readl(GUEST_CR0);
2109 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2110 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2111 vmcs_writel(GUEST_CR0, cr0);
2112 update_exception_bitmap(vcpu);
2113 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2114 if (is_guest_mode(vcpu))
2115 vcpu->arch.cr0_guest_owned_bits &=
2116 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2117 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2120 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2123 * Return the cr0 value that a nested guest would read. This is a combination
2124 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2125 * its hypervisor (cr0_read_shadow).
2127 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2129 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2130 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2132 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2134 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2135 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2138 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2140 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2141 * set this *before* calling this function.
2143 vmx_decache_cr0_guest_bits(vcpu);
2144 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2145 update_exception_bitmap(vcpu);
2146 vcpu->arch.cr0_guest_owned_bits = 0;
2147 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2148 if (is_guest_mode(vcpu)) {
2150 * L1's specified read shadow might not contain the TS bit,
2151 * so now that we turned on shadowing of this bit, we need to
2152 * set this bit of the shadow. Like in nested_vmx_run we need
2153 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2154 * up-to-date here because we just decached cr0.TS (and we'll
2155 * only update vmcs12->guest_cr0 on nested exit).
2157 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2158 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2159 (vcpu->arch.cr0 & X86_CR0_TS);
2160 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2162 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2165 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2167 unsigned long rflags, save_rflags;
2169 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2170 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2171 rflags = vmcs_readl(GUEST_RFLAGS);
2172 if (to_vmx(vcpu)->rmode.vm86_active) {
2173 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2174 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2175 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2177 to_vmx(vcpu)->rflags = rflags;
2179 return to_vmx(vcpu)->rflags;
2182 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2184 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2185 to_vmx(vcpu)->rflags = rflags;
2186 if (to_vmx(vcpu)->rmode.vm86_active) {
2187 to_vmx(vcpu)->rmode.save_rflags = rflags;
2188 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2190 vmcs_writel(GUEST_RFLAGS, rflags);
2193 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2195 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2198 if (interruptibility & GUEST_INTR_STATE_STI)
2199 ret |= KVM_X86_SHADOW_INT_STI;
2200 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2201 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2206 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2208 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2209 u32 interruptibility = interruptibility_old;
2211 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2213 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2214 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2215 else if (mask & KVM_X86_SHADOW_INT_STI)
2216 interruptibility |= GUEST_INTR_STATE_STI;
2218 if ((interruptibility != interruptibility_old))
2219 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2222 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2226 rip = kvm_rip_read(vcpu);
2227 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2228 kvm_rip_write(vcpu, rip);
2230 /* skipping an emulated instruction also counts */
2231 vmx_set_interrupt_shadow(vcpu, 0);
2235 * KVM wants to inject page-faults which it got to the guest. This function
2236 * checks whether in a nested guest, we need to inject them to L1 or L2.
2238 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2240 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2242 if (!(vmcs12->exception_bitmap & (1u << nr)))
2245 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2246 vmcs_read32(VM_EXIT_INTR_INFO),
2247 vmcs_readl(EXIT_QUALIFICATION));
2251 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2252 bool has_error_code, u32 error_code,
2255 struct vcpu_vmx *vmx = to_vmx(vcpu);
2256 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2258 if (!reinject && is_guest_mode(vcpu) &&
2259 nested_vmx_check_exception(vcpu, nr))
2262 if (has_error_code) {
2263 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2264 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2267 if (vmx->rmode.vm86_active) {
2269 if (kvm_exception_is_soft(nr))
2270 inc_eip = vcpu->arch.event_exit_inst_len;
2271 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2272 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2276 if (kvm_exception_is_soft(nr)) {
2277 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2278 vmx->vcpu.arch.event_exit_inst_len);
2279 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2281 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2283 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2286 static bool vmx_rdtscp_supported(void)
2288 return cpu_has_vmx_rdtscp();
2291 static bool vmx_invpcid_supported(void)
2293 return cpu_has_vmx_invpcid() && enable_ept;
2297 * Swap MSR entry in host/guest MSR entry array.
2299 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2301 struct shared_msr_entry tmp;
2303 tmp = vmx->guest_msrs[to];
2304 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2305 vmx->guest_msrs[from] = tmp;
2308 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2310 unsigned long *msr_bitmap;
2312 if (is_guest_mode(vcpu))
2313 msr_bitmap = vmx_msr_bitmap_nested;
2314 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2315 if (is_long_mode(vcpu))
2316 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2318 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2320 if (is_long_mode(vcpu))
2321 msr_bitmap = vmx_msr_bitmap_longmode;
2323 msr_bitmap = vmx_msr_bitmap_legacy;
2326 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2330 * Set up the vmcs to automatically save and restore system
2331 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2332 * mode, as fiddling with msrs is very expensive.
2334 static void setup_msrs(struct vcpu_vmx *vmx)
2336 int save_nmsrs, index;
2339 #ifdef CONFIG_X86_64
2340 if (is_long_mode(&vmx->vcpu)) {
2341 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2343 move_msr_up(vmx, index, save_nmsrs++);
2344 index = __find_msr_index(vmx, MSR_LSTAR);
2346 move_msr_up(vmx, index, save_nmsrs++);
2347 index = __find_msr_index(vmx, MSR_CSTAR);
2349 move_msr_up(vmx, index, save_nmsrs++);
2350 index = __find_msr_index(vmx, MSR_TSC_AUX);
2351 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2352 move_msr_up(vmx, index, save_nmsrs++);
2354 * MSR_STAR is only needed on long mode guests, and only
2355 * if efer.sce is enabled.
2357 index = __find_msr_index(vmx, MSR_STAR);
2358 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2359 move_msr_up(vmx, index, save_nmsrs++);
2362 index = __find_msr_index(vmx, MSR_EFER);
2363 if (index >= 0 && update_transition_efer(vmx, index))
2364 move_msr_up(vmx, index, save_nmsrs++);
2366 vmx->save_nmsrs = save_nmsrs;
2368 if (cpu_has_vmx_msr_bitmap())
2369 vmx_set_msr_bitmap(&vmx->vcpu);
2373 * reads and returns guest's timestamp counter "register"
2374 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2375 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2377 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2379 u64 host_tsc, tsc_offset;
2382 tsc_offset = vmcs_read64(TSC_OFFSET);
2383 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2387 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2388 * counter, even if a nested guest (L2) is currently running.
2390 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2394 tsc_offset = is_guest_mode(vcpu) ?
2395 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2396 vmcs_read64(TSC_OFFSET);
2397 return host_tsc + tsc_offset;
2400 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2402 return vmcs_read64(TSC_OFFSET);
2406 * writes 'offset' into guest's timestamp counter offset register
2408 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2410 if (is_guest_mode(vcpu)) {
2412 * We're here if L1 chose not to trap WRMSR to TSC. According
2413 * to the spec, this should set L1's TSC; The offset that L1
2414 * set for L2 remains unchanged, and still needs to be added
2415 * to the newly set TSC to get L2's TSC.
2417 struct vmcs12 *vmcs12;
2418 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2419 /* recalculate vmcs02.TSC_OFFSET: */
2420 vmcs12 = get_vmcs12(vcpu);
2421 vmcs_write64(TSC_OFFSET, offset +
2422 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2423 vmcs12->tsc_offset : 0));
2425 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2426 vmcs_read64(TSC_OFFSET), offset);
2427 vmcs_write64(TSC_OFFSET, offset);
2431 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2433 u64 offset = vmcs_read64(TSC_OFFSET);
2435 vmcs_write64(TSC_OFFSET, offset + adjustment);
2436 if (is_guest_mode(vcpu)) {
2437 /* Even when running L2, the adjustment needs to apply to L1 */
2438 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2440 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2441 offset + adjustment);
2444 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2446 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2447 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2451 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2452 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2453 * all guests if the "nested" module option is off, and can also be disabled
2454 * for a single guest by disabling its VMX cpuid bit.
2456 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2458 return nested && guest_cpuid_has_vmx(vcpu);
2462 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2463 * returned for the various VMX controls MSRs when nested VMX is enabled.
2464 * The same values should also be used to verify that vmcs12 control fields are
2465 * valid during nested entry from L1 to L2.
2466 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2467 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2468 * bit in the high half is on if the corresponding bit in the control field
2469 * may be on. See also vmx_control_verify().
2471 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2474 * Note that as a general rule, the high half of the MSRs (bits in
2475 * the control fields which may be 1) should be initialized by the
2476 * intersection of the underlying hardware's MSR (i.e., features which
2477 * can be supported) and the list of features we want to expose -
2478 * because they are known to be properly supported in our code.
2479 * Also, usually, the low half of the MSRs (bits which must be 1) can
2480 * be set to 0, meaning that L1 may turn off any of these bits. The
2481 * reason is that if one of these bits is necessary, it will appear
2482 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2483 * fields of vmcs01 and vmcs02, will turn these bits off - and
2484 * nested_vmx_exit_handled() will not pass related exits to L1.
2485 * These rules have exceptions below.
2488 /* pin-based controls */
2489 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2490 vmx->nested.nested_vmx_pinbased_ctls_low,
2491 vmx->nested.nested_vmx_pinbased_ctls_high);
2492 vmx->nested.nested_vmx_pinbased_ctls_low |=
2493 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2494 vmx->nested.nested_vmx_pinbased_ctls_high &=
2495 PIN_BASED_EXT_INTR_MASK |
2496 PIN_BASED_NMI_EXITING |
2497 PIN_BASED_VIRTUAL_NMIS;
2498 vmx->nested.nested_vmx_pinbased_ctls_high |=
2499 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2500 PIN_BASED_VMX_PREEMPTION_TIMER;
2501 if (vmx_cpu_uses_apicv(&vmx->vcpu))
2502 vmx->nested.nested_vmx_pinbased_ctls_high |=
2503 PIN_BASED_POSTED_INTR;
2506 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2507 vmx->nested.nested_vmx_exit_ctls_low,
2508 vmx->nested.nested_vmx_exit_ctls_high);
2509 vmx->nested.nested_vmx_exit_ctls_low =
2510 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2512 vmx->nested.nested_vmx_exit_ctls_high &=
2513 #ifdef CONFIG_X86_64
2514 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2516 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2517 vmx->nested.nested_vmx_exit_ctls_high |=
2518 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2519 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2520 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2522 if (vmx_mpx_supported())
2523 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2525 /* We support free control of debug control saving. */
2526 vmx->nested.nested_vmx_true_exit_ctls_low =
2527 vmx->nested.nested_vmx_exit_ctls_low &
2528 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2530 /* entry controls */
2531 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2532 vmx->nested.nested_vmx_entry_ctls_low,
2533 vmx->nested.nested_vmx_entry_ctls_high);
2534 vmx->nested.nested_vmx_entry_ctls_low =
2535 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2536 vmx->nested.nested_vmx_entry_ctls_high &=
2537 #ifdef CONFIG_X86_64
2538 VM_ENTRY_IA32E_MODE |
2540 VM_ENTRY_LOAD_IA32_PAT;
2541 vmx->nested.nested_vmx_entry_ctls_high |=
2542 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2543 if (vmx_mpx_supported())
2544 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2546 /* We support free control of debug control loading. */
2547 vmx->nested.nested_vmx_true_entry_ctls_low =
2548 vmx->nested.nested_vmx_entry_ctls_low &
2549 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2551 /* cpu-based controls */
2552 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2553 vmx->nested.nested_vmx_procbased_ctls_low,
2554 vmx->nested.nested_vmx_procbased_ctls_high);
2555 vmx->nested.nested_vmx_procbased_ctls_low =
2556 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2557 vmx->nested.nested_vmx_procbased_ctls_high &=
2558 CPU_BASED_VIRTUAL_INTR_PENDING |
2559 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2560 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2561 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2562 CPU_BASED_CR3_STORE_EXITING |
2563 #ifdef CONFIG_X86_64
2564 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2566 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2567 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2568 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2569 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2570 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2572 * We can allow some features even when not supported by the
2573 * hardware. For example, L1 can specify an MSR bitmap - and we
2574 * can use it to avoid exits to L1 - even when L0 runs L2
2575 * without MSR bitmaps.
2577 vmx->nested.nested_vmx_procbased_ctls_high |=
2578 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2579 CPU_BASED_USE_MSR_BITMAPS;
2581 /* We support free control of CR3 access interception. */
2582 vmx->nested.nested_vmx_true_procbased_ctls_low =
2583 vmx->nested.nested_vmx_procbased_ctls_low &
2584 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2586 /* secondary cpu-based controls */
2587 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2588 vmx->nested.nested_vmx_secondary_ctls_low,
2589 vmx->nested.nested_vmx_secondary_ctls_high);
2590 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2591 vmx->nested.nested_vmx_secondary_ctls_high &=
2592 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2593 SECONDARY_EXEC_RDTSCP |
2594 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2595 SECONDARY_EXEC_ENABLE_VPID |
2596 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2597 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2598 SECONDARY_EXEC_WBINVD_EXITING |
2599 SECONDARY_EXEC_XSAVES |
2600 SECONDARY_EXEC_PCOMMIT;
2603 /* nested EPT: emulate EPT also to L1 */
2604 vmx->nested.nested_vmx_secondary_ctls_high |=
2605 SECONDARY_EXEC_ENABLE_EPT;
2606 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2607 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2609 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2611 * For nested guests, we don't do anything specific
2612 * for single context invalidation. Hence, only advertise
2613 * support for global context invalidation.
2615 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2617 vmx->nested.nested_vmx_ept_caps = 0;
2620 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2621 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2623 vmx->nested.nested_vmx_vpid_caps = 0;
2625 if (enable_unrestricted_guest)
2626 vmx->nested.nested_vmx_secondary_ctls_high |=
2627 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2629 /* miscellaneous data */
2630 rdmsr(MSR_IA32_VMX_MISC,
2631 vmx->nested.nested_vmx_misc_low,
2632 vmx->nested.nested_vmx_misc_high);
2633 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2634 vmx->nested.nested_vmx_misc_low |=
2635 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2636 VMX_MISC_ACTIVITY_HLT;
2637 vmx->nested.nested_vmx_misc_high = 0;
2640 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2643 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2645 return ((control & high) | low) == control;
2648 static inline u64 vmx_control_msr(u32 low, u32 high)
2650 return low | ((u64)high << 32);
2653 /* Returns 0 on success, non-0 otherwise. */
2654 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2656 struct vcpu_vmx *vmx = to_vmx(vcpu);
2658 switch (msr_index) {
2659 case MSR_IA32_VMX_BASIC:
2661 * This MSR reports some information about VMX support. We
2662 * should return information about the VMX we emulate for the
2663 * guest, and the VMCS structure we give it - not about the
2664 * VMX support of the underlying hardware.
2666 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2667 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2668 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2670 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2671 case MSR_IA32_VMX_PINBASED_CTLS:
2672 *pdata = vmx_control_msr(
2673 vmx->nested.nested_vmx_pinbased_ctls_low,
2674 vmx->nested.nested_vmx_pinbased_ctls_high);
2676 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2677 *pdata = vmx_control_msr(
2678 vmx->nested.nested_vmx_true_procbased_ctls_low,
2679 vmx->nested.nested_vmx_procbased_ctls_high);
2681 case MSR_IA32_VMX_PROCBASED_CTLS:
2682 *pdata = vmx_control_msr(
2683 vmx->nested.nested_vmx_procbased_ctls_low,
2684 vmx->nested.nested_vmx_procbased_ctls_high);
2686 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2687 *pdata = vmx_control_msr(
2688 vmx->nested.nested_vmx_true_exit_ctls_low,
2689 vmx->nested.nested_vmx_exit_ctls_high);
2691 case MSR_IA32_VMX_EXIT_CTLS:
2692 *pdata = vmx_control_msr(
2693 vmx->nested.nested_vmx_exit_ctls_low,
2694 vmx->nested.nested_vmx_exit_ctls_high);
2696 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2697 *pdata = vmx_control_msr(
2698 vmx->nested.nested_vmx_true_entry_ctls_low,
2699 vmx->nested.nested_vmx_entry_ctls_high);
2701 case MSR_IA32_VMX_ENTRY_CTLS:
2702 *pdata = vmx_control_msr(
2703 vmx->nested.nested_vmx_entry_ctls_low,
2704 vmx->nested.nested_vmx_entry_ctls_high);
2706 case MSR_IA32_VMX_MISC:
2707 *pdata = vmx_control_msr(
2708 vmx->nested.nested_vmx_misc_low,
2709 vmx->nested.nested_vmx_misc_high);
2712 * These MSRs specify bits which the guest must keep fixed (on or off)
2713 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2714 * We picked the standard core2 setting.
2716 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2717 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2718 case MSR_IA32_VMX_CR0_FIXED0:
2719 *pdata = VMXON_CR0_ALWAYSON;
2721 case MSR_IA32_VMX_CR0_FIXED1:
2724 case MSR_IA32_VMX_CR4_FIXED0:
2725 *pdata = VMXON_CR4_ALWAYSON;
2727 case MSR_IA32_VMX_CR4_FIXED1:
2730 case MSR_IA32_VMX_VMCS_ENUM:
2731 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2733 case MSR_IA32_VMX_PROCBASED_CTLS2:
2734 *pdata = vmx_control_msr(
2735 vmx->nested.nested_vmx_secondary_ctls_low,
2736 vmx->nested.nested_vmx_secondary_ctls_high);
2738 case MSR_IA32_VMX_EPT_VPID_CAP:
2739 /* Currently, no nested vpid support */
2740 *pdata = vmx->nested.nested_vmx_ept_caps |
2741 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2751 * Reads an msr value (of 'msr_index') into 'pdata'.
2752 * Returns 0 on success, non-0 otherwise.
2753 * Assumes vcpu_load() was already called.
2755 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2757 struct shared_msr_entry *msr;
2759 switch (msr_info->index) {
2760 #ifdef CONFIG_X86_64
2762 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2765 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2767 case MSR_KERNEL_GS_BASE:
2768 vmx_load_host_state(to_vmx(vcpu));
2769 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2773 return kvm_get_msr_common(vcpu, msr_info);
2775 msr_info->data = guest_read_tsc(vcpu);
2777 case MSR_IA32_SYSENTER_CS:
2778 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2780 case MSR_IA32_SYSENTER_EIP:
2781 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2783 case MSR_IA32_SYSENTER_ESP:
2784 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2786 case MSR_IA32_BNDCFGS:
2787 if (!vmx_mpx_supported())
2789 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2791 case MSR_IA32_FEATURE_CONTROL:
2792 if (!nested_vmx_allowed(vcpu))
2794 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2796 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2797 if (!nested_vmx_allowed(vcpu))
2799 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2801 if (!vmx_xsaves_supported())
2803 msr_info->data = vcpu->arch.ia32_xss;
2806 if (!guest_cpuid_has_rdtscp(vcpu))
2808 /* Otherwise falls through */
2810 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2812 msr_info->data = msr->data;
2815 return kvm_get_msr_common(vcpu, msr_info);
2821 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2824 * Writes msr value into into the appropriate "register".
2825 * Returns 0 on success, non-0 otherwise.
2826 * Assumes vcpu_load() was already called.
2828 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2830 struct vcpu_vmx *vmx = to_vmx(vcpu);
2831 struct shared_msr_entry *msr;
2833 u32 msr_index = msr_info->index;
2834 u64 data = msr_info->data;
2836 switch (msr_index) {
2838 ret = kvm_set_msr_common(vcpu, msr_info);
2840 #ifdef CONFIG_X86_64
2842 vmx_segment_cache_clear(vmx);
2843 vmcs_writel(GUEST_FS_BASE, data);
2846 vmx_segment_cache_clear(vmx);
2847 vmcs_writel(GUEST_GS_BASE, data);
2849 case MSR_KERNEL_GS_BASE:
2850 vmx_load_host_state(vmx);
2851 vmx->msr_guest_kernel_gs_base = data;
2854 case MSR_IA32_SYSENTER_CS:
2855 vmcs_write32(GUEST_SYSENTER_CS, data);
2857 case MSR_IA32_SYSENTER_EIP:
2858 vmcs_writel(GUEST_SYSENTER_EIP, data);
2860 case MSR_IA32_SYSENTER_ESP:
2861 vmcs_writel(GUEST_SYSENTER_ESP, data);
2863 case MSR_IA32_BNDCFGS:
2864 if (!vmx_mpx_supported())
2866 vmcs_write64(GUEST_BNDCFGS, data);
2869 kvm_write_tsc(vcpu, msr_info);
2871 case MSR_IA32_CR_PAT:
2872 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2873 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2875 vmcs_write64(GUEST_IA32_PAT, data);
2876 vcpu->arch.pat = data;
2879 ret = kvm_set_msr_common(vcpu, msr_info);
2881 case MSR_IA32_TSC_ADJUST:
2882 ret = kvm_set_msr_common(vcpu, msr_info);
2884 case MSR_IA32_FEATURE_CONTROL:
2885 if (!nested_vmx_allowed(vcpu) ||
2886 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2887 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2889 vmx->nested.msr_ia32_feature_control = data;
2890 if (msr_info->host_initiated && data == 0)
2891 vmx_leave_nested(vcpu);
2893 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2894 return 1; /* they are read-only */
2896 if (!vmx_xsaves_supported())
2899 * The only supported bit as of Skylake is bit 8, but
2900 * it is not supported on KVM.
2904 vcpu->arch.ia32_xss = data;
2905 if (vcpu->arch.ia32_xss != host_xss)
2906 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2907 vcpu->arch.ia32_xss, host_xss);
2909 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2912 if (!guest_cpuid_has_rdtscp(vcpu))
2914 /* Check reserved bit, higher 32 bits should be zero */
2915 if ((data >> 32) != 0)
2917 /* Otherwise falls through */
2919 msr = find_msr_entry(vmx, msr_index);
2921 u64 old_msr_data = msr->data;
2923 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2925 ret = kvm_set_shared_msr(msr->index, msr->data,
2929 msr->data = old_msr_data;
2933 ret = kvm_set_msr_common(vcpu, msr_info);
2939 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2941 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2944 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2947 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2949 case VCPU_EXREG_PDPTR:
2951 ept_save_pdptrs(vcpu);
2958 static __init int cpu_has_kvm_support(void)
2960 return cpu_has_vmx();
2963 static __init int vmx_disabled_by_bios(void)
2967 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2968 if (msr & FEATURE_CONTROL_LOCKED) {
2969 /* launched w/ TXT and VMX disabled */
2970 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2973 /* launched w/o TXT and VMX only enabled w/ TXT */
2974 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2975 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2976 && !tboot_enabled()) {
2977 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2978 "activate TXT before enabling KVM\n");
2981 /* launched w/o TXT and VMX disabled */
2982 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2983 && !tboot_enabled())
2990 static void kvm_cpu_vmxon(u64 addr)
2992 asm volatile (ASM_VMX_VMXON_RAX
2993 : : "a"(&addr), "m"(addr)
2997 static int hardware_enable(void)
2999 int cpu = raw_smp_processor_id();
3000 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3003 if (cr4_read_shadow() & X86_CR4_VMXE)
3006 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3007 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3008 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3011 * Now we can enable the vmclear operation in kdump
3012 * since the loaded_vmcss_on_cpu list on this cpu
3013 * has been initialized.
3015 * Though the cpu is not in VMX operation now, there
3016 * is no problem to enable the vmclear operation
3017 * for the loaded_vmcss_on_cpu list is empty!
3019 crash_enable_local_vmclear(cpu);
3021 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3023 test_bits = FEATURE_CONTROL_LOCKED;
3024 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3025 if (tboot_enabled())
3026 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3028 if ((old & test_bits) != test_bits) {
3029 /* enable and lock */
3030 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3032 cr4_set_bits(X86_CR4_VMXE);
3034 if (vmm_exclusive) {
3035 kvm_cpu_vmxon(phys_addr);
3039 native_store_gdt(this_cpu_ptr(&host_gdt));
3044 static void vmclear_local_loaded_vmcss(void)
3046 int cpu = raw_smp_processor_id();
3047 struct loaded_vmcs *v, *n;
3049 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3050 loaded_vmcss_on_cpu_link)
3051 __loaded_vmcs_clear(v);
3055 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3058 static void kvm_cpu_vmxoff(void)
3060 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3063 static void hardware_disable(void)
3065 if (vmm_exclusive) {
3066 vmclear_local_loaded_vmcss();
3069 cr4_clear_bits(X86_CR4_VMXE);
3072 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3073 u32 msr, u32 *result)
3075 u32 vmx_msr_low, vmx_msr_high;
3076 u32 ctl = ctl_min | ctl_opt;
3078 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3080 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3081 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3083 /* Ensure minimum (required) set of control bits are supported. */
3091 static __init bool allow_1_setting(u32 msr, u32 ctl)
3093 u32 vmx_msr_low, vmx_msr_high;
3095 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3096 return vmx_msr_high & ctl;
3099 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3101 u32 vmx_msr_low, vmx_msr_high;
3102 u32 min, opt, min2, opt2;
3103 u32 _pin_based_exec_control = 0;
3104 u32 _cpu_based_exec_control = 0;
3105 u32 _cpu_based_2nd_exec_control = 0;
3106 u32 _vmexit_control = 0;
3107 u32 _vmentry_control = 0;
3109 min = CPU_BASED_HLT_EXITING |
3110 #ifdef CONFIG_X86_64
3111 CPU_BASED_CR8_LOAD_EXITING |
3112 CPU_BASED_CR8_STORE_EXITING |
3114 CPU_BASED_CR3_LOAD_EXITING |
3115 CPU_BASED_CR3_STORE_EXITING |
3116 CPU_BASED_USE_IO_BITMAPS |
3117 CPU_BASED_MOV_DR_EXITING |
3118 CPU_BASED_USE_TSC_OFFSETING |
3119 CPU_BASED_MWAIT_EXITING |
3120 CPU_BASED_MONITOR_EXITING |
3121 CPU_BASED_INVLPG_EXITING |
3122 CPU_BASED_RDPMC_EXITING;
3124 opt = CPU_BASED_TPR_SHADOW |
3125 CPU_BASED_USE_MSR_BITMAPS |
3126 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3127 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3128 &_cpu_based_exec_control) < 0)
3130 #ifdef CONFIG_X86_64
3131 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3132 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3133 ~CPU_BASED_CR8_STORE_EXITING;
3135 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3137 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3138 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3139 SECONDARY_EXEC_WBINVD_EXITING |
3140 SECONDARY_EXEC_ENABLE_VPID |
3141 SECONDARY_EXEC_ENABLE_EPT |
3142 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3143 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3144 SECONDARY_EXEC_RDTSCP |
3145 SECONDARY_EXEC_ENABLE_INVPCID |
3146 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3147 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3148 SECONDARY_EXEC_SHADOW_VMCS |
3149 SECONDARY_EXEC_XSAVES |
3150 SECONDARY_EXEC_ENABLE_PML |
3151 SECONDARY_EXEC_PCOMMIT |
3152 SECONDARY_EXEC_TSC_SCALING;
3153 if (adjust_vmx_controls(min2, opt2,
3154 MSR_IA32_VMX_PROCBASED_CTLS2,
3155 &_cpu_based_2nd_exec_control) < 0)
3158 #ifndef CONFIG_X86_64
3159 if (!(_cpu_based_2nd_exec_control &
3160 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3161 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3164 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3165 _cpu_based_2nd_exec_control &= ~(
3166 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3167 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3168 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3170 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3171 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3173 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3174 CPU_BASED_CR3_STORE_EXITING |
3175 CPU_BASED_INVLPG_EXITING);
3176 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3177 vmx_capability.ept, vmx_capability.vpid);
3180 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3181 #ifdef CONFIG_X86_64
3182 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3184 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3185 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3186 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3187 &_vmexit_control) < 0)
3190 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3191 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3192 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3193 &_pin_based_exec_control) < 0)
3196 if (!(_cpu_based_2nd_exec_control &
3197 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3198 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3199 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3201 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3202 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3203 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3204 &_vmentry_control) < 0)
3207 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3209 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3210 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3213 #ifdef CONFIG_X86_64
3214 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3215 if (vmx_msr_high & (1u<<16))
3219 /* Require Write-Back (WB) memory type for VMCS accesses. */
3220 if (((vmx_msr_high >> 18) & 15) != 6)
3223 vmcs_conf->size = vmx_msr_high & 0x1fff;
3224 vmcs_conf->order = get_order(vmcs_config.size);
3225 vmcs_conf->revision_id = vmx_msr_low;
3227 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3228 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3229 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3230 vmcs_conf->vmexit_ctrl = _vmexit_control;
3231 vmcs_conf->vmentry_ctrl = _vmentry_control;
3233 cpu_has_load_ia32_efer =
3234 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3235 VM_ENTRY_LOAD_IA32_EFER)
3236 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3237 VM_EXIT_LOAD_IA32_EFER);
3239 cpu_has_load_perf_global_ctrl =
3240 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3241 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3242 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3243 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3246 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3247 * but due to arrata below it can't be used. Workaround is to use
3248 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3250 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3255 * BC86,AAY89,BD102 (model 44)
3259 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3260 switch (boot_cpu_data.x86_model) {
3266 cpu_has_load_perf_global_ctrl = false;
3267 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3268 "does not work properly. Using workaround\n");
3276 rdmsrl(MSR_IA32_XSS, host_xss);
3281 static struct vmcs *alloc_vmcs_cpu(int cpu)
3283 int node = cpu_to_node(cpu);
3287 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3290 vmcs = page_address(pages);
3291 memset(vmcs, 0, vmcs_config.size);
3292 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3296 static struct vmcs *alloc_vmcs(void)
3298 return alloc_vmcs_cpu(raw_smp_processor_id());
3301 static void free_vmcs(struct vmcs *vmcs)
3303 free_pages((unsigned long)vmcs, vmcs_config.order);
3307 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3309 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3311 if (!loaded_vmcs->vmcs)
3313 loaded_vmcs_clear(loaded_vmcs);
3314 free_vmcs(loaded_vmcs->vmcs);
3315 loaded_vmcs->vmcs = NULL;
3318 static void free_kvm_area(void)
3322 for_each_possible_cpu(cpu) {
3323 free_vmcs(per_cpu(vmxarea, cpu));
3324 per_cpu(vmxarea, cpu) = NULL;
3328 static void init_vmcs_shadow_fields(void)
3332 /* No checks for read only fields yet */
3334 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3335 switch (shadow_read_write_fields[i]) {
3337 if (!vmx_mpx_supported())
3345 shadow_read_write_fields[j] =
3346 shadow_read_write_fields[i];
3349 max_shadow_read_write_fields = j;
3351 /* shadowed fields guest access without vmexit */
3352 for (i = 0; i < max_shadow_read_write_fields; i++) {
3353 clear_bit(shadow_read_write_fields[i],
3354 vmx_vmwrite_bitmap);
3355 clear_bit(shadow_read_write_fields[i],
3358 for (i = 0; i < max_shadow_read_only_fields; i++)
3359 clear_bit(shadow_read_only_fields[i],
3363 static __init int alloc_kvm_area(void)
3367 for_each_possible_cpu(cpu) {
3370 vmcs = alloc_vmcs_cpu(cpu);
3376 per_cpu(vmxarea, cpu) = vmcs;
3381 static bool emulation_required(struct kvm_vcpu *vcpu)
3383 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3386 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3387 struct kvm_segment *save)
3389 if (!emulate_invalid_guest_state) {
3391 * CS and SS RPL should be equal during guest entry according
3392 * to VMX spec, but in reality it is not always so. Since vcpu
3393 * is in the middle of the transition from real mode to
3394 * protected mode it is safe to assume that RPL 0 is a good
3397 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3398 save->selector &= ~SEGMENT_RPL_MASK;
3399 save->dpl = save->selector & SEGMENT_RPL_MASK;
3402 vmx_set_segment(vcpu, save, seg);
3405 static void enter_pmode(struct kvm_vcpu *vcpu)
3407 unsigned long flags;
3408 struct vcpu_vmx *vmx = to_vmx(vcpu);
3411 * Update real mode segment cache. It may be not up-to-date if sement
3412 * register was written while vcpu was in a guest mode.
3414 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3415 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3416 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3417 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3418 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3419 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3421 vmx->rmode.vm86_active = 0;
3423 vmx_segment_cache_clear(vmx);
3425 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3427 flags = vmcs_readl(GUEST_RFLAGS);
3428 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3429 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3430 vmcs_writel(GUEST_RFLAGS, flags);
3432 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3433 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3435 update_exception_bitmap(vcpu);
3437 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3438 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3439 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3440 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3441 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3442 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3445 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3447 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3448 struct kvm_segment var = *save;
3451 if (seg == VCPU_SREG_CS)
3454 if (!emulate_invalid_guest_state) {
3455 var.selector = var.base >> 4;
3456 var.base = var.base & 0xffff0;
3466 if (save->base & 0xf)
3467 printk_once(KERN_WARNING "kvm: segment base is not "
3468 "paragraph aligned when entering "
3469 "protected mode (seg=%d)", seg);
3472 vmcs_write16(sf->selector, var.selector);
3473 vmcs_write32(sf->base, var.base);
3474 vmcs_write32(sf->limit, var.limit);
3475 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3478 static void enter_rmode(struct kvm_vcpu *vcpu)
3480 unsigned long flags;
3481 struct vcpu_vmx *vmx = to_vmx(vcpu);
3483 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3484 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3485 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3486 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3487 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3488 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3489 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3491 vmx->rmode.vm86_active = 1;
3494 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3495 * vcpu. Warn the user that an update is overdue.
3497 if (!vcpu->kvm->arch.tss_addr)
3498 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3499 "called before entering vcpu\n");
3501 vmx_segment_cache_clear(vmx);
3503 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3504 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3505 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3507 flags = vmcs_readl(GUEST_RFLAGS);
3508 vmx->rmode.save_rflags = flags;
3510 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3512 vmcs_writel(GUEST_RFLAGS, flags);
3513 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3514 update_exception_bitmap(vcpu);
3516 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3517 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3518 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3519 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3520 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3521 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3523 kvm_mmu_reset_context(vcpu);
3526 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3528 struct vcpu_vmx *vmx = to_vmx(vcpu);
3529 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3535 * Force kernel_gs_base reloading before EFER changes, as control
3536 * of this msr depends on is_long_mode().
3538 vmx_load_host_state(to_vmx(vcpu));
3539 vcpu->arch.efer = efer;
3540 if (efer & EFER_LMA) {
3541 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3544 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3546 msr->data = efer & ~EFER_LME;
3551 #ifdef CONFIG_X86_64
3553 static void enter_lmode(struct kvm_vcpu *vcpu)
3557 vmx_segment_cache_clear(to_vmx(vcpu));
3559 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3560 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3561 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3563 vmcs_write32(GUEST_TR_AR_BYTES,
3564 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3565 | VMX_AR_TYPE_BUSY_64_TSS);
3567 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3570 static void exit_lmode(struct kvm_vcpu *vcpu)
3572 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3573 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3578 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3580 vpid_sync_context(vpid);
3582 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3584 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3588 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3590 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3593 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3595 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3597 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3598 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3601 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3603 if (enable_ept && is_paging(vcpu))
3604 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3605 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3608 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3610 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3612 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3613 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3616 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3618 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3620 if (!test_bit(VCPU_EXREG_PDPTR,
3621 (unsigned long *)&vcpu->arch.regs_dirty))
3624 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3625 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3626 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3627 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3628 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3632 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3634 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3636 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3637 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3638 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3639 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3640 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3643 __set_bit(VCPU_EXREG_PDPTR,
3644 (unsigned long *)&vcpu->arch.regs_avail);
3645 __set_bit(VCPU_EXREG_PDPTR,
3646 (unsigned long *)&vcpu->arch.regs_dirty);
3649 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3651 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3653 struct kvm_vcpu *vcpu)
3655 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3656 vmx_decache_cr3(vcpu);
3657 if (!(cr0 & X86_CR0_PG)) {
3658 /* From paging/starting to nonpaging */
3659 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3660 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3661 (CPU_BASED_CR3_LOAD_EXITING |
3662 CPU_BASED_CR3_STORE_EXITING));
3663 vcpu->arch.cr0 = cr0;
3664 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3665 } else if (!is_paging(vcpu)) {
3666 /* From nonpaging to paging */
3667 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3668 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3669 ~(CPU_BASED_CR3_LOAD_EXITING |
3670 CPU_BASED_CR3_STORE_EXITING));
3671 vcpu->arch.cr0 = cr0;
3672 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3675 if (!(cr0 & X86_CR0_WP))
3676 *hw_cr0 &= ~X86_CR0_WP;
3679 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3681 struct vcpu_vmx *vmx = to_vmx(vcpu);
3682 unsigned long hw_cr0;
3684 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3685 if (enable_unrestricted_guest)
3686 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3688 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3690 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3693 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3697 #ifdef CONFIG_X86_64
3698 if (vcpu->arch.efer & EFER_LME) {
3699 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3701 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3707 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3709 if (!vcpu->fpu_active)
3710 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3712 vmcs_writel(CR0_READ_SHADOW, cr0);
3713 vmcs_writel(GUEST_CR0, hw_cr0);
3714 vcpu->arch.cr0 = cr0;
3716 /* depends on vcpu->arch.cr0 to be set to a new value */
3717 vmx->emulation_required = emulation_required(vcpu);
3720 static u64 construct_eptp(unsigned long root_hpa)
3724 /* TODO write the value reading from MSR */
3725 eptp = VMX_EPT_DEFAULT_MT |
3726 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3727 if (enable_ept_ad_bits)
3728 eptp |= VMX_EPT_AD_ENABLE_BIT;
3729 eptp |= (root_hpa & PAGE_MASK);
3734 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3736 unsigned long guest_cr3;
3741 eptp = construct_eptp(cr3);
3742 vmcs_write64(EPT_POINTER, eptp);
3743 if (is_paging(vcpu) || is_guest_mode(vcpu))
3744 guest_cr3 = kvm_read_cr3(vcpu);
3746 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3747 ept_load_pdptrs(vcpu);
3750 vmx_flush_tlb(vcpu);
3751 vmcs_writel(GUEST_CR3, guest_cr3);
3754 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3757 * Pass through host's Machine Check Enable value to hw_cr4, which
3758 * is in force while we are in guest mode. Do not let guests control
3759 * this bit, even if host CR4.MCE == 0.
3761 unsigned long hw_cr4 =
3762 (cr4_read_shadow() & X86_CR4_MCE) |
3763 (cr4 & ~X86_CR4_MCE) |
3764 (to_vmx(vcpu)->rmode.vm86_active ?
3765 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3767 if (cr4 & X86_CR4_VMXE) {
3769 * To use VMXON (and later other VMX instructions), a guest
3770 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3771 * So basically the check on whether to allow nested VMX
3774 if (!nested_vmx_allowed(vcpu))
3777 if (to_vmx(vcpu)->nested.vmxon &&
3778 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3781 vcpu->arch.cr4 = cr4;
3783 if (!is_paging(vcpu)) {
3784 hw_cr4 &= ~X86_CR4_PAE;
3785 hw_cr4 |= X86_CR4_PSE;
3786 } else if (!(cr4 & X86_CR4_PAE)) {
3787 hw_cr4 &= ~X86_CR4_PAE;
3791 if (!enable_unrestricted_guest && !is_paging(vcpu))
3793 * SMEP/SMAP is disabled if CPU is in non-paging mode in
3794 * hardware. However KVM always uses paging mode without
3795 * unrestricted guest.
3796 * To emulate this behavior, SMEP/SMAP needs to be manually
3797 * disabled when guest switches to non-paging mode.
3799 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3801 vmcs_writel(CR4_READ_SHADOW, cr4);
3802 vmcs_writel(GUEST_CR4, hw_cr4);
3806 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3807 struct kvm_segment *var, int seg)
3809 struct vcpu_vmx *vmx = to_vmx(vcpu);
3812 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3813 *var = vmx->rmode.segs[seg];
3814 if (seg == VCPU_SREG_TR
3815 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3817 var->base = vmx_read_guest_seg_base(vmx, seg);
3818 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3821 var->base = vmx_read_guest_seg_base(vmx, seg);
3822 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3823 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3824 ar = vmx_read_guest_seg_ar(vmx, seg);
3825 var->unusable = (ar >> 16) & 1;
3826 var->type = ar & 15;
3827 var->s = (ar >> 4) & 1;
3828 var->dpl = (ar >> 5) & 3;
3830 * Some userspaces do not preserve unusable property. Since usable
3831 * segment has to be present according to VMX spec we can use present
3832 * property to amend userspace bug by making unusable segment always
3833 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3834 * segment as unusable.
3836 var->present = !var->unusable;
3837 var->avl = (ar >> 12) & 1;
3838 var->l = (ar >> 13) & 1;
3839 var->db = (ar >> 14) & 1;
3840 var->g = (ar >> 15) & 1;
3843 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3845 struct kvm_segment s;
3847 if (to_vmx(vcpu)->rmode.vm86_active) {
3848 vmx_get_segment(vcpu, &s, seg);
3851 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3854 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3856 struct vcpu_vmx *vmx = to_vmx(vcpu);
3858 if (unlikely(vmx->rmode.vm86_active))
3861 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3862 return VMX_AR_DPL(ar);
3866 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3870 if (var->unusable || !var->present)
3873 ar = var->type & 15;
3874 ar |= (var->s & 1) << 4;
3875 ar |= (var->dpl & 3) << 5;
3876 ar |= (var->present & 1) << 7;
3877 ar |= (var->avl & 1) << 12;
3878 ar |= (var->l & 1) << 13;
3879 ar |= (var->db & 1) << 14;
3880 ar |= (var->g & 1) << 15;
3886 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3887 struct kvm_segment *var, int seg)
3889 struct vcpu_vmx *vmx = to_vmx(vcpu);
3890 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3892 vmx_segment_cache_clear(vmx);
3894 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3895 vmx->rmode.segs[seg] = *var;
3896 if (seg == VCPU_SREG_TR)
3897 vmcs_write16(sf->selector, var->selector);
3899 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3903 vmcs_writel(sf->base, var->base);
3904 vmcs_write32(sf->limit, var->limit);
3905 vmcs_write16(sf->selector, var->selector);
3908 * Fix the "Accessed" bit in AR field of segment registers for older
3910 * IA32 arch specifies that at the time of processor reset the
3911 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3912 * is setting it to 0 in the userland code. This causes invalid guest
3913 * state vmexit when "unrestricted guest" mode is turned on.
3914 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3915 * tree. Newer qemu binaries with that qemu fix would not need this
3918 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3919 var->type |= 0x1; /* Accessed */
3921 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3924 vmx->emulation_required = emulation_required(vcpu);
3927 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3929 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3931 *db = (ar >> 14) & 1;
3932 *l = (ar >> 13) & 1;
3935 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3937 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3938 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3941 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3943 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3944 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3947 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3949 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3950 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3953 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3955 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3956 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3959 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3961 struct kvm_segment var;
3964 vmx_get_segment(vcpu, &var, seg);
3966 if (seg == VCPU_SREG_CS)
3968 ar = vmx_segment_access_rights(&var);
3970 if (var.base != (var.selector << 4))
3972 if (var.limit != 0xffff)
3980 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3982 struct kvm_segment cs;
3983 unsigned int cs_rpl;
3985 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3986 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3990 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3994 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3995 if (cs.dpl > cs_rpl)
3998 if (cs.dpl != cs_rpl)
4004 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4008 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4010 struct kvm_segment ss;
4011 unsigned int ss_rpl;
4013 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4014 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4018 if (ss.type != 3 && ss.type != 7)
4022 if (ss.dpl != ss_rpl) /* DPL != RPL */
4030 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4032 struct kvm_segment var;
4035 vmx_get_segment(vcpu, &var, seg);
4036 rpl = var.selector & SEGMENT_RPL_MASK;
4044 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4045 if (var.dpl < rpl) /* DPL < RPL */
4049 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4055 static bool tr_valid(struct kvm_vcpu *vcpu)
4057 struct kvm_segment tr;
4059 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4063 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4065 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4073 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4075 struct kvm_segment ldtr;
4077 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4081 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4091 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4093 struct kvm_segment cs, ss;
4095 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4096 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4098 return ((cs.selector & SEGMENT_RPL_MASK) ==
4099 (ss.selector & SEGMENT_RPL_MASK));
4103 * Check if guest state is valid. Returns true if valid, false if
4105 * We assume that registers are always usable
4107 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4109 if (enable_unrestricted_guest)
4112 /* real mode guest state checks */
4113 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4114 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4116 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4118 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4120 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4122 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4124 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4127 /* protected mode guest state checks */
4128 if (!cs_ss_rpl_check(vcpu))
4130 if (!code_segment_valid(vcpu))
4132 if (!stack_segment_valid(vcpu))
4134 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4136 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4138 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4140 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4142 if (!tr_valid(vcpu))
4144 if (!ldtr_valid(vcpu))
4148 * - Add checks on RIP
4149 * - Add checks on RFLAGS
4155 static int init_rmode_tss(struct kvm *kvm)
4161 idx = srcu_read_lock(&kvm->srcu);
4162 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4163 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4166 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4167 r = kvm_write_guest_page(kvm, fn++, &data,
4168 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4171 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4174 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4178 r = kvm_write_guest_page(kvm, fn, &data,
4179 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4182 srcu_read_unlock(&kvm->srcu, idx);
4186 static int init_rmode_identity_map(struct kvm *kvm)
4189 pfn_t identity_map_pfn;
4195 /* Protect kvm->arch.ept_identity_pagetable_done. */
4196 mutex_lock(&kvm->slots_lock);
4198 if (likely(kvm->arch.ept_identity_pagetable_done))
4201 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4203 r = alloc_identity_pagetable(kvm);
4207 idx = srcu_read_lock(&kvm->srcu);
4208 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4211 /* Set up identity-mapping pagetable for EPT in real mode */
4212 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4213 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4214 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4215 r = kvm_write_guest_page(kvm, identity_map_pfn,
4216 &tmp, i * sizeof(tmp), sizeof(tmp));
4220 kvm->arch.ept_identity_pagetable_done = true;
4223 srcu_read_unlock(&kvm->srcu, idx);
4226 mutex_unlock(&kvm->slots_lock);
4230 static void seg_setup(int seg)
4232 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4235 vmcs_write16(sf->selector, 0);
4236 vmcs_writel(sf->base, 0);
4237 vmcs_write32(sf->limit, 0xffff);
4239 if (seg == VCPU_SREG_CS)
4240 ar |= 0x08; /* code segment */
4242 vmcs_write32(sf->ar_bytes, ar);
4245 static int alloc_apic_access_page(struct kvm *kvm)
4250 mutex_lock(&kvm->slots_lock);
4251 if (kvm->arch.apic_access_page_done)
4253 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4254 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4258 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4259 if (is_error_page(page)) {
4265 * Do not pin the page in memory, so that memory hot-unplug
4266 * is able to migrate it.
4269 kvm->arch.apic_access_page_done = true;
4271 mutex_unlock(&kvm->slots_lock);
4275 static int alloc_identity_pagetable(struct kvm *kvm)
4277 /* Called with kvm->slots_lock held. */
4281 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4283 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4284 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4289 static int allocate_vpid(void)
4295 spin_lock(&vmx_vpid_lock);
4296 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4297 if (vpid < VMX_NR_VPIDS)
4298 __set_bit(vpid, vmx_vpid_bitmap);
4301 spin_unlock(&vmx_vpid_lock);
4305 static void free_vpid(int vpid)
4307 if (!enable_vpid || vpid == 0)
4309 spin_lock(&vmx_vpid_lock);
4310 __clear_bit(vpid, vmx_vpid_bitmap);
4311 spin_unlock(&vmx_vpid_lock);
4314 #define MSR_TYPE_R 1
4315 #define MSR_TYPE_W 2
4316 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4319 int f = sizeof(unsigned long);
4321 if (!cpu_has_vmx_msr_bitmap())
4325 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4326 * have the write-low and read-high bitmap offsets the wrong way round.
4327 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4329 if (msr <= 0x1fff) {
4330 if (type & MSR_TYPE_R)
4332 __clear_bit(msr, msr_bitmap + 0x000 / f);
4334 if (type & MSR_TYPE_W)
4336 __clear_bit(msr, msr_bitmap + 0x800 / f);
4338 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4340 if (type & MSR_TYPE_R)
4342 __clear_bit(msr, msr_bitmap + 0x400 / f);
4344 if (type & MSR_TYPE_W)
4346 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4351 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4354 int f = sizeof(unsigned long);
4356 if (!cpu_has_vmx_msr_bitmap())
4360 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4361 * have the write-low and read-high bitmap offsets the wrong way round.
4362 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4364 if (msr <= 0x1fff) {
4365 if (type & MSR_TYPE_R)
4367 __set_bit(msr, msr_bitmap + 0x000 / f);
4369 if (type & MSR_TYPE_W)
4371 __set_bit(msr, msr_bitmap + 0x800 / f);
4373 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4375 if (type & MSR_TYPE_R)
4377 __set_bit(msr, msr_bitmap + 0x400 / f);
4379 if (type & MSR_TYPE_W)
4381 __set_bit(msr, msr_bitmap + 0xc00 / f);
4387 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4388 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4390 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4391 unsigned long *msr_bitmap_nested,
4394 int f = sizeof(unsigned long);
4396 if (!cpu_has_vmx_msr_bitmap()) {
4402 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4403 * have the write-low and read-high bitmap offsets the wrong way round.
4404 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4406 if (msr <= 0x1fff) {
4407 if (type & MSR_TYPE_R &&
4408 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4410 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4412 if (type & MSR_TYPE_W &&
4413 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4415 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4417 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4419 if (type & MSR_TYPE_R &&
4420 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4422 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4424 if (type & MSR_TYPE_W &&
4425 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4427 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4432 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4435 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4436 msr, MSR_TYPE_R | MSR_TYPE_W);
4437 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4438 msr, MSR_TYPE_R | MSR_TYPE_W);
4441 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4443 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4445 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4449 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4451 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4453 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4457 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4459 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4461 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4465 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4467 return enable_apicv && lapic_in_kernel(vcpu);
4470 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4472 struct vcpu_vmx *vmx = to_vmx(vcpu);
4477 if (vmx->nested.pi_desc &&
4478 vmx->nested.pi_pending) {
4479 vmx->nested.pi_pending = false;
4480 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4483 max_irr = find_last_bit(
4484 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4489 vapic_page = kmap(vmx->nested.virtual_apic_page);
4494 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4495 kunmap(vmx->nested.virtual_apic_page);
4497 status = vmcs_read16(GUEST_INTR_STATUS);
4498 if ((u8)max_irr > ((u8)status & 0xff)) {
4500 status |= (u8)max_irr;
4501 vmcs_write16(GUEST_INTR_STATUS, status);
4507 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4510 if (vcpu->mode == IN_GUEST_MODE) {
4511 struct vcpu_vmx *vmx = to_vmx(vcpu);
4514 * Currently, we don't support urgent interrupt,
4515 * all interrupts are recognized as non-urgent
4516 * interrupt, so we cannot post interrupts when
4519 * If the vcpu is in guest mode, it means it is
4520 * running instead of being scheduled out and
4521 * waiting in the run queue, and that's the only
4522 * case when 'SN' is set currently, warning if
4525 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4527 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4528 POSTED_INTR_VECTOR);
4535 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4538 struct vcpu_vmx *vmx = to_vmx(vcpu);
4540 if (is_guest_mode(vcpu) &&
4541 vector == vmx->nested.posted_intr_nv) {
4542 /* the PIR and ON have been set by L1. */
4543 kvm_vcpu_trigger_posted_interrupt(vcpu);
4545 * If a posted intr is not recognized by hardware,
4546 * we will accomplish it in the next vmentry.
4548 vmx->nested.pi_pending = true;
4549 kvm_make_request(KVM_REQ_EVENT, vcpu);
4555 * Send interrupt to vcpu via posted interrupt way.
4556 * 1. If target vcpu is running(non-root mode), send posted interrupt
4557 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4558 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4559 * interrupt from PIR in next vmentry.
4561 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4563 struct vcpu_vmx *vmx = to_vmx(vcpu);
4566 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4570 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4573 r = pi_test_and_set_on(&vmx->pi_desc);
4574 kvm_make_request(KVM_REQ_EVENT, vcpu);
4575 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4576 kvm_vcpu_kick(vcpu);
4579 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4581 struct vcpu_vmx *vmx = to_vmx(vcpu);
4583 if (!pi_test_and_clear_on(&vmx->pi_desc))
4586 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4589 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4595 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4596 * will not change in the lifetime of the guest.
4597 * Note that host-state that does change is set elsewhere. E.g., host-state
4598 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4600 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4607 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4608 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4610 /* Save the most likely value for this task's CR4 in the VMCS. */
4611 cr4 = cr4_read_shadow();
4612 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4613 vmx->host_state.vmcs_host_cr4 = cr4;
4615 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4616 #ifdef CONFIG_X86_64
4618 * Load null selectors, so we can avoid reloading them in
4619 * __vmx_load_host_state(), in case userspace uses the null selectors
4620 * too (the expected case).
4622 vmcs_write16(HOST_DS_SELECTOR, 0);
4623 vmcs_write16(HOST_ES_SELECTOR, 0);
4625 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4626 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4628 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4629 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4631 native_store_idt(&dt);
4632 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4633 vmx->host_idt_base = dt.address;
4635 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4637 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4638 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4639 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4640 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4642 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4643 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4644 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4648 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4650 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4652 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4653 if (is_guest_mode(&vmx->vcpu))
4654 vmx->vcpu.arch.cr4_guest_owned_bits &=
4655 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4656 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4659 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4661 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4663 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4664 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4665 return pin_based_exec_ctrl;
4668 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4670 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4672 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4673 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4675 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4676 exec_control &= ~CPU_BASED_TPR_SHADOW;
4677 #ifdef CONFIG_X86_64
4678 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4679 CPU_BASED_CR8_LOAD_EXITING;
4683 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4684 CPU_BASED_CR3_LOAD_EXITING |
4685 CPU_BASED_INVLPG_EXITING;
4686 return exec_control;
4689 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4691 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4692 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4693 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4695 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4697 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4698 enable_unrestricted_guest = 0;
4699 /* Enable INVPCID for non-ept guests may cause performance regression. */
4700 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4702 if (!enable_unrestricted_guest)
4703 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4705 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4706 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4707 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4708 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4709 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4710 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4712 We can NOT enable shadow_vmcs here because we don't have yet
4715 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4718 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4720 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4721 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4723 return exec_control;
4726 static void ept_set_mmio_spte_mask(void)
4729 * EPT Misconfigurations can be generated if the value of bits 2:0
4730 * of an EPT paging-structure entry is 110b (write/execute).
4731 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4734 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4737 #define VMX_XSS_EXIT_BITMAP 0
4739 * Sets up the vmcs for emulated real mode.
4741 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4743 #ifdef CONFIG_X86_64
4749 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4750 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4752 if (enable_shadow_vmcs) {
4753 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4754 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4756 if (cpu_has_vmx_msr_bitmap())
4757 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4759 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4762 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4764 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4766 if (cpu_has_secondary_exec_ctrls())
4767 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4768 vmx_secondary_exec_control(vmx));
4770 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4771 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4772 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4773 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4774 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4776 vmcs_write16(GUEST_INTR_STATUS, 0);
4778 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4779 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4783 vmcs_write32(PLE_GAP, ple_gap);
4784 vmx->ple_window = ple_window;
4785 vmx->ple_window_dirty = true;
4788 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4789 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4790 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4792 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4793 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4794 vmx_set_constant_host_state(vmx);
4795 #ifdef CONFIG_X86_64
4796 rdmsrl(MSR_FS_BASE, a);
4797 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4798 rdmsrl(MSR_GS_BASE, a);
4799 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4801 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4802 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4805 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4806 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4807 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4808 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4809 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4811 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4812 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4814 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4815 u32 index = vmx_msr_index[i];
4816 u32 data_low, data_high;
4819 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4821 if (wrmsr_safe(index, data_low, data_high) < 0)
4823 vmx->guest_msrs[j].index = i;
4824 vmx->guest_msrs[j].data = 0;
4825 vmx->guest_msrs[j].mask = -1ull;
4830 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4832 /* 22.2.1, 20.8.1 */
4833 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4835 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4836 set_cr4_guest_host_mask(vmx);
4838 if (vmx_xsaves_supported())
4839 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4844 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4846 struct vcpu_vmx *vmx = to_vmx(vcpu);
4847 struct msr_data apic_base_msr;
4850 vmx->rmode.vm86_active = 0;
4852 vmx->soft_vnmi_blocked = 0;
4854 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4855 kvm_set_cr8(vcpu, 0);
4858 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4859 MSR_IA32_APICBASE_ENABLE;
4860 if (kvm_vcpu_is_reset_bsp(vcpu))
4861 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4862 apic_base_msr.host_initiated = true;
4863 kvm_set_apic_base(vcpu, &apic_base_msr);
4866 vmx_segment_cache_clear(vmx);
4868 seg_setup(VCPU_SREG_CS);
4869 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4870 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4872 seg_setup(VCPU_SREG_DS);
4873 seg_setup(VCPU_SREG_ES);
4874 seg_setup(VCPU_SREG_FS);
4875 seg_setup(VCPU_SREG_GS);
4876 seg_setup(VCPU_SREG_SS);
4878 vmcs_write16(GUEST_TR_SELECTOR, 0);
4879 vmcs_writel(GUEST_TR_BASE, 0);
4880 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4881 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4883 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4884 vmcs_writel(GUEST_LDTR_BASE, 0);
4885 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4886 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4889 vmcs_write32(GUEST_SYSENTER_CS, 0);
4890 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4891 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4892 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4895 vmcs_writel(GUEST_RFLAGS, 0x02);
4896 kvm_rip_write(vcpu, 0xfff0);
4898 vmcs_writel(GUEST_GDTR_BASE, 0);
4899 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4901 vmcs_writel(GUEST_IDTR_BASE, 0);
4902 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4904 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4905 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4906 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4910 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4912 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4913 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4914 if (cpu_need_tpr_shadow(vcpu))
4915 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4916 __pa(vcpu->arch.apic->regs));
4917 vmcs_write32(TPR_THRESHOLD, 0);
4920 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4922 if (vmx_cpu_uses_apicv(vcpu))
4923 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4926 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4928 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4929 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4930 vmx->vcpu.arch.cr0 = cr0;
4931 vmx_set_cr4(vcpu, 0);
4932 vmx_set_efer(vcpu, 0);
4933 vmx_fpu_activate(vcpu);
4934 update_exception_bitmap(vcpu);
4936 vpid_sync_context(vmx->vpid);
4940 * In nested virtualization, check if L1 asked to exit on external interrupts.
4941 * For most existing hypervisors, this will always return true.
4943 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4945 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4946 PIN_BASED_EXT_INTR_MASK;
4950 * In nested virtualization, check if L1 has set
4951 * VM_EXIT_ACK_INTR_ON_EXIT
4953 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4955 return get_vmcs12(vcpu)->vm_exit_controls &
4956 VM_EXIT_ACK_INTR_ON_EXIT;
4959 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4961 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4962 PIN_BASED_NMI_EXITING;
4965 static void enable_irq_window(struct kvm_vcpu *vcpu)
4967 u32 cpu_based_vm_exec_control;
4969 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4970 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4971 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4974 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4976 u32 cpu_based_vm_exec_control;
4978 if (!cpu_has_virtual_nmis() ||
4979 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4980 enable_irq_window(vcpu);
4984 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4985 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4986 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4989 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4991 struct vcpu_vmx *vmx = to_vmx(vcpu);
4993 int irq = vcpu->arch.interrupt.nr;
4995 trace_kvm_inj_virq(irq);
4997 ++vcpu->stat.irq_injections;
4998 if (vmx->rmode.vm86_active) {
5000 if (vcpu->arch.interrupt.soft)
5001 inc_eip = vcpu->arch.event_exit_inst_len;
5002 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5003 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5006 intr = irq | INTR_INFO_VALID_MASK;
5007 if (vcpu->arch.interrupt.soft) {
5008 intr |= INTR_TYPE_SOFT_INTR;
5009 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5010 vmx->vcpu.arch.event_exit_inst_len);
5012 intr |= INTR_TYPE_EXT_INTR;
5013 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5016 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5018 struct vcpu_vmx *vmx = to_vmx(vcpu);
5020 if (is_guest_mode(vcpu))
5023 if (!cpu_has_virtual_nmis()) {
5025 * Tracking the NMI-blocked state in software is built upon
5026 * finding the next open IRQ window. This, in turn, depends on
5027 * well-behaving guests: They have to keep IRQs disabled at
5028 * least as long as the NMI handler runs. Otherwise we may
5029 * cause NMI nesting, maybe breaking the guest. But as this is
5030 * highly unlikely, we can live with the residual risk.
5032 vmx->soft_vnmi_blocked = 1;
5033 vmx->vnmi_blocked_time = 0;
5036 ++vcpu->stat.nmi_injections;
5037 vmx->nmi_known_unmasked = false;
5038 if (vmx->rmode.vm86_active) {
5039 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5040 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5043 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5044 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5047 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5049 if (!cpu_has_virtual_nmis())
5050 return to_vmx(vcpu)->soft_vnmi_blocked;
5051 if (to_vmx(vcpu)->nmi_known_unmasked)
5053 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5056 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5058 struct vcpu_vmx *vmx = to_vmx(vcpu);
5060 if (!cpu_has_virtual_nmis()) {
5061 if (vmx->soft_vnmi_blocked != masked) {
5062 vmx->soft_vnmi_blocked = masked;
5063 vmx->vnmi_blocked_time = 0;
5066 vmx->nmi_known_unmasked = !masked;
5068 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5069 GUEST_INTR_STATE_NMI);
5071 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5072 GUEST_INTR_STATE_NMI);
5076 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5078 if (to_vmx(vcpu)->nested.nested_run_pending)
5081 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5084 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5085 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5086 | GUEST_INTR_STATE_NMI));
5089 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5091 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5092 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5093 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5094 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5097 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5101 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5105 kvm->arch.tss_addr = addr;
5106 return init_rmode_tss(kvm);
5109 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5114 * Update instruction length as we may reinject the exception
5115 * from user space while in guest debugging mode.
5117 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5118 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5119 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5123 if (vcpu->guest_debug &
5124 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5141 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5142 int vec, u32 err_code)
5145 * Instruction with address size override prefix opcode 0x67
5146 * Cause the #SS fault with 0 error code in VM86 mode.
5148 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5149 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5150 if (vcpu->arch.halt_request) {
5151 vcpu->arch.halt_request = 0;
5152 return kvm_vcpu_halt(vcpu);
5160 * Forward all other exceptions that are valid in real mode.
5161 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5162 * the required debugging infrastructure rework.
5164 kvm_queue_exception(vcpu, vec);
5169 * Trigger machine check on the host. We assume all the MSRs are already set up
5170 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5171 * We pass a fake environment to the machine check handler because we want
5172 * the guest to be always treated like user space, no matter what context
5173 * it used internally.
5175 static void kvm_machine_check(void)
5177 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5178 struct pt_regs regs = {
5179 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5180 .flags = X86_EFLAGS_IF,
5183 do_machine_check(®s, 0);
5187 static int handle_machine_check(struct kvm_vcpu *vcpu)
5189 /* already handled by vcpu_run */
5193 static int handle_exception(struct kvm_vcpu *vcpu)
5195 struct vcpu_vmx *vmx = to_vmx(vcpu);
5196 struct kvm_run *kvm_run = vcpu->run;
5197 u32 intr_info, ex_no, error_code;
5198 unsigned long cr2, rip, dr6;
5200 enum emulation_result er;
5202 vect_info = vmx->idt_vectoring_info;
5203 intr_info = vmx->exit_intr_info;
5205 if (is_machine_check(intr_info))
5206 return handle_machine_check(vcpu);
5208 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5209 return 1; /* already handled by vmx_vcpu_run() */
5211 if (is_no_device(intr_info)) {
5212 vmx_fpu_activate(vcpu);
5216 if (is_invalid_opcode(intr_info)) {
5217 if (is_guest_mode(vcpu)) {
5218 kvm_queue_exception(vcpu, UD_VECTOR);
5221 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5222 if (er != EMULATE_DONE)
5223 kvm_queue_exception(vcpu, UD_VECTOR);
5228 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5229 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5232 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5233 * MMIO, it is better to report an internal error.
5234 * See the comments in vmx_handle_exit.
5236 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5237 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5238 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5239 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5240 vcpu->run->internal.ndata = 3;
5241 vcpu->run->internal.data[0] = vect_info;
5242 vcpu->run->internal.data[1] = intr_info;
5243 vcpu->run->internal.data[2] = error_code;
5247 if (is_page_fault(intr_info)) {
5248 /* EPT won't cause page fault directly */
5250 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5251 trace_kvm_page_fault(cr2, error_code);
5253 if (kvm_event_needs_reinjection(vcpu))
5254 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5255 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5258 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5260 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5261 return handle_rmode_exception(vcpu, ex_no, error_code);
5265 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5268 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5269 if (!(vcpu->guest_debug &
5270 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5271 vcpu->arch.dr6 &= ~15;
5272 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5273 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5274 skip_emulated_instruction(vcpu);
5276 kvm_queue_exception(vcpu, DB_VECTOR);
5279 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5280 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5284 * Update instruction length as we may reinject #BP from
5285 * user space while in guest debugging mode. Reading it for
5286 * #DB as well causes no harm, it is not used in that case.
5288 vmx->vcpu.arch.event_exit_inst_len =
5289 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5290 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5291 rip = kvm_rip_read(vcpu);
5292 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5293 kvm_run->debug.arch.exception = ex_no;
5296 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5297 kvm_run->ex.exception = ex_no;
5298 kvm_run->ex.error_code = error_code;
5304 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5306 ++vcpu->stat.irq_exits;
5310 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5312 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5316 static int handle_io(struct kvm_vcpu *vcpu)
5318 unsigned long exit_qualification;
5319 int size, in, string;
5322 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5323 string = (exit_qualification & 16) != 0;
5324 in = (exit_qualification & 8) != 0;
5326 ++vcpu->stat.io_exits;
5329 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5331 port = exit_qualification >> 16;
5332 size = (exit_qualification & 7) + 1;
5333 skip_emulated_instruction(vcpu);
5335 return kvm_fast_pio_out(vcpu, size, port);
5339 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5342 * Patch in the VMCALL instruction:
5344 hypercall[0] = 0x0f;
5345 hypercall[1] = 0x01;
5346 hypercall[2] = 0xc1;
5349 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5351 unsigned long always_on = VMXON_CR0_ALWAYSON;
5352 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5354 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5355 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5356 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5357 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5358 return (val & always_on) == always_on;
5361 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5362 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5364 if (is_guest_mode(vcpu)) {
5365 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5366 unsigned long orig_val = val;
5369 * We get here when L2 changed cr0 in a way that did not change
5370 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5371 * but did change L0 shadowed bits. So we first calculate the
5372 * effective cr0 value that L1 would like to write into the
5373 * hardware. It consists of the L2-owned bits from the new
5374 * value combined with the L1-owned bits from L1's guest_cr0.
5376 val = (val & ~vmcs12->cr0_guest_host_mask) |
5377 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5379 if (!nested_cr0_valid(vcpu, val))
5382 if (kvm_set_cr0(vcpu, val))
5384 vmcs_writel(CR0_READ_SHADOW, orig_val);
5387 if (to_vmx(vcpu)->nested.vmxon &&
5388 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5390 return kvm_set_cr0(vcpu, val);
5394 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5396 if (is_guest_mode(vcpu)) {
5397 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5398 unsigned long orig_val = val;
5400 /* analogously to handle_set_cr0 */
5401 val = (val & ~vmcs12->cr4_guest_host_mask) |
5402 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5403 if (kvm_set_cr4(vcpu, val))
5405 vmcs_writel(CR4_READ_SHADOW, orig_val);
5408 return kvm_set_cr4(vcpu, val);
5411 /* called to set cr0 as approriate for clts instruction exit. */
5412 static void handle_clts(struct kvm_vcpu *vcpu)
5414 if (is_guest_mode(vcpu)) {
5416 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5417 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5418 * just pretend it's off (also in arch.cr0 for fpu_activate).
5420 vmcs_writel(CR0_READ_SHADOW,
5421 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5422 vcpu->arch.cr0 &= ~X86_CR0_TS;
5424 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5427 static int handle_cr(struct kvm_vcpu *vcpu)
5429 unsigned long exit_qualification, val;
5434 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5435 cr = exit_qualification & 15;
5436 reg = (exit_qualification >> 8) & 15;
5437 switch ((exit_qualification >> 4) & 3) {
5438 case 0: /* mov to cr */
5439 val = kvm_register_readl(vcpu, reg);
5440 trace_kvm_cr_write(cr, val);
5443 err = handle_set_cr0(vcpu, val);
5444 kvm_complete_insn_gp(vcpu, err);
5447 err = kvm_set_cr3(vcpu, val);
5448 kvm_complete_insn_gp(vcpu, err);
5451 err = handle_set_cr4(vcpu, val);
5452 kvm_complete_insn_gp(vcpu, err);
5455 u8 cr8_prev = kvm_get_cr8(vcpu);
5457 err = kvm_set_cr8(vcpu, cr8);
5458 kvm_complete_insn_gp(vcpu, err);
5459 if (lapic_in_kernel(vcpu))
5461 if (cr8_prev <= cr8)
5463 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5470 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5471 skip_emulated_instruction(vcpu);
5472 vmx_fpu_activate(vcpu);
5474 case 1: /*mov from cr*/
5477 val = kvm_read_cr3(vcpu);
5478 kvm_register_write(vcpu, reg, val);
5479 trace_kvm_cr_read(cr, val);
5480 skip_emulated_instruction(vcpu);
5483 val = kvm_get_cr8(vcpu);
5484 kvm_register_write(vcpu, reg, val);
5485 trace_kvm_cr_read(cr, val);
5486 skip_emulated_instruction(vcpu);
5491 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5492 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5493 kvm_lmsw(vcpu, val);
5495 skip_emulated_instruction(vcpu);
5500 vcpu->run->exit_reason = 0;
5501 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5502 (int)(exit_qualification >> 4) & 3, cr);
5506 static int handle_dr(struct kvm_vcpu *vcpu)
5508 unsigned long exit_qualification;
5511 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5512 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5514 /* First, if DR does not exist, trigger UD */
5515 if (!kvm_require_dr(vcpu, dr))
5518 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5519 if (!kvm_require_cpl(vcpu, 0))
5521 dr7 = vmcs_readl(GUEST_DR7);
5524 * As the vm-exit takes precedence over the debug trap, we
5525 * need to emulate the latter, either for the host or the
5526 * guest debugging itself.
5528 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5529 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5530 vcpu->run->debug.arch.dr7 = dr7;
5531 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5532 vcpu->run->debug.arch.exception = DB_VECTOR;
5533 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5536 vcpu->arch.dr6 &= ~15;
5537 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5538 kvm_queue_exception(vcpu, DB_VECTOR);
5543 if (vcpu->guest_debug == 0) {
5544 u32 cpu_based_vm_exec_control;
5546 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5547 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5548 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5551 * No more DR vmexits; force a reload of the debug registers
5552 * and reenter on this instruction. The next vmexit will
5553 * retrieve the full state of the debug registers.
5555 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5559 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5560 if (exit_qualification & TYPE_MOV_FROM_DR) {
5563 if (kvm_get_dr(vcpu, dr, &val))
5565 kvm_register_write(vcpu, reg, val);
5567 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5570 skip_emulated_instruction(vcpu);
5574 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5576 return vcpu->arch.dr6;
5579 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5583 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5585 u32 cpu_based_vm_exec_control;
5587 get_debugreg(vcpu->arch.db[0], 0);
5588 get_debugreg(vcpu->arch.db[1], 1);
5589 get_debugreg(vcpu->arch.db[2], 2);
5590 get_debugreg(vcpu->arch.db[3], 3);
5591 get_debugreg(vcpu->arch.dr6, 6);
5592 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5594 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5596 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5597 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5598 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5601 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5603 vmcs_writel(GUEST_DR7, val);
5606 static int handle_cpuid(struct kvm_vcpu *vcpu)
5608 kvm_emulate_cpuid(vcpu);
5612 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5614 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5615 struct msr_data msr_info;
5617 msr_info.index = ecx;
5618 msr_info.host_initiated = false;
5619 if (vmx_get_msr(vcpu, &msr_info)) {
5620 trace_kvm_msr_read_ex(ecx);
5621 kvm_inject_gp(vcpu, 0);
5625 trace_kvm_msr_read(ecx, msr_info.data);
5627 /* FIXME: handling of bits 32:63 of rax, rdx */
5628 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5629 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5630 skip_emulated_instruction(vcpu);
5634 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5636 struct msr_data msr;
5637 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5638 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5639 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5643 msr.host_initiated = false;
5644 if (kvm_set_msr(vcpu, &msr) != 0) {
5645 trace_kvm_msr_write_ex(ecx, data);
5646 kvm_inject_gp(vcpu, 0);
5650 trace_kvm_msr_write(ecx, data);
5651 skip_emulated_instruction(vcpu);
5655 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5657 kvm_make_request(KVM_REQ_EVENT, vcpu);
5661 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5663 u32 cpu_based_vm_exec_control;
5665 /* clear pending irq */
5666 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5667 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5668 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5670 kvm_make_request(KVM_REQ_EVENT, vcpu);
5672 ++vcpu->stat.irq_window_exits;
5676 static int handle_halt(struct kvm_vcpu *vcpu)
5678 return kvm_emulate_halt(vcpu);
5681 static int handle_vmcall(struct kvm_vcpu *vcpu)
5683 kvm_emulate_hypercall(vcpu);
5687 static int handle_invd(struct kvm_vcpu *vcpu)
5689 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5692 static int handle_invlpg(struct kvm_vcpu *vcpu)
5694 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5696 kvm_mmu_invlpg(vcpu, exit_qualification);
5697 skip_emulated_instruction(vcpu);
5701 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5705 err = kvm_rdpmc(vcpu);
5706 kvm_complete_insn_gp(vcpu, err);
5711 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5713 kvm_emulate_wbinvd(vcpu);
5717 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5719 u64 new_bv = kvm_read_edx_eax(vcpu);
5720 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5722 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5723 skip_emulated_instruction(vcpu);
5727 static int handle_xsaves(struct kvm_vcpu *vcpu)
5729 skip_emulated_instruction(vcpu);
5730 WARN(1, "this should never happen\n");
5734 static int handle_xrstors(struct kvm_vcpu *vcpu)
5736 skip_emulated_instruction(vcpu);
5737 WARN(1, "this should never happen\n");
5741 static int handle_apic_access(struct kvm_vcpu *vcpu)
5743 if (likely(fasteoi)) {
5744 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5745 int access_type, offset;
5747 access_type = exit_qualification & APIC_ACCESS_TYPE;
5748 offset = exit_qualification & APIC_ACCESS_OFFSET;
5750 * Sane guest uses MOV to write EOI, with written value
5751 * not cared. So make a short-circuit here by avoiding
5752 * heavy instruction emulation.
5754 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5755 (offset == APIC_EOI)) {
5756 kvm_lapic_set_eoi(vcpu);
5757 skip_emulated_instruction(vcpu);
5761 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5764 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5766 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5767 int vector = exit_qualification & 0xff;
5769 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5770 kvm_apic_set_eoi_accelerated(vcpu, vector);
5774 static int handle_apic_write(struct kvm_vcpu *vcpu)
5776 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5777 u32 offset = exit_qualification & 0xfff;
5779 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5780 kvm_apic_write_nodecode(vcpu, offset);
5784 static int handle_task_switch(struct kvm_vcpu *vcpu)
5786 struct vcpu_vmx *vmx = to_vmx(vcpu);
5787 unsigned long exit_qualification;
5788 bool has_error_code = false;
5791 int reason, type, idt_v, idt_index;
5793 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5794 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5795 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5797 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5799 reason = (u32)exit_qualification >> 30;
5800 if (reason == TASK_SWITCH_GATE && idt_v) {
5802 case INTR_TYPE_NMI_INTR:
5803 vcpu->arch.nmi_injected = false;
5804 vmx_set_nmi_mask(vcpu, true);
5806 case INTR_TYPE_EXT_INTR:
5807 case INTR_TYPE_SOFT_INTR:
5808 kvm_clear_interrupt_queue(vcpu);
5810 case INTR_TYPE_HARD_EXCEPTION:
5811 if (vmx->idt_vectoring_info &
5812 VECTORING_INFO_DELIVER_CODE_MASK) {
5813 has_error_code = true;
5815 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5818 case INTR_TYPE_SOFT_EXCEPTION:
5819 kvm_clear_exception_queue(vcpu);
5825 tss_selector = exit_qualification;
5827 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5828 type != INTR_TYPE_EXT_INTR &&
5829 type != INTR_TYPE_NMI_INTR))
5830 skip_emulated_instruction(vcpu);
5832 if (kvm_task_switch(vcpu, tss_selector,
5833 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5834 has_error_code, error_code) == EMULATE_FAIL) {
5835 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5836 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5837 vcpu->run->internal.ndata = 0;
5842 * TODO: What about debug traps on tss switch?
5843 * Are we supposed to inject them and update dr6?
5849 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5851 unsigned long exit_qualification;
5856 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5858 gla_validity = (exit_qualification >> 7) & 0x3;
5859 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5860 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5861 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5862 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5863 vmcs_readl(GUEST_LINEAR_ADDRESS));
5864 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5865 (long unsigned int)exit_qualification);
5866 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5867 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5872 * EPT violation happened while executing iret from NMI,
5873 * "blocked by NMI" bit has to be set before next VM entry.
5874 * There are errata that may cause this bit to not be set:
5877 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5878 cpu_has_virtual_nmis() &&
5879 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5880 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5882 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5883 trace_kvm_page_fault(gpa, exit_qualification);
5885 /* It is a write fault? */
5886 error_code = exit_qualification & PFERR_WRITE_MASK;
5887 /* It is a fetch fault? */
5888 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5889 /* ept page table is present? */
5890 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5892 vcpu->arch.exit_qualification = exit_qualification;
5894 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5897 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5902 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5903 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5904 skip_emulated_instruction(vcpu);
5905 trace_kvm_fast_mmio(gpa);
5909 ret = handle_mmio_page_fault(vcpu, gpa, true);
5910 if (likely(ret == RET_MMIO_PF_EMULATE))
5911 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5914 if (unlikely(ret == RET_MMIO_PF_INVALID))
5915 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5917 if (unlikely(ret == RET_MMIO_PF_RETRY))
5920 /* It is the real ept misconfig */
5923 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5924 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5929 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5931 u32 cpu_based_vm_exec_control;
5933 /* clear pending NMI */
5934 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5935 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5936 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5937 ++vcpu->stat.nmi_window_exits;
5938 kvm_make_request(KVM_REQ_EVENT, vcpu);
5943 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5945 struct vcpu_vmx *vmx = to_vmx(vcpu);
5946 enum emulation_result err = EMULATE_DONE;
5949 bool intr_window_requested;
5950 unsigned count = 130;
5952 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5953 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5955 while (vmx->emulation_required && count-- != 0) {
5956 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5957 return handle_interrupt_window(&vmx->vcpu);
5959 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5962 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5964 if (err == EMULATE_USER_EXIT) {
5965 ++vcpu->stat.mmio_exits;
5970 if (err != EMULATE_DONE) {
5971 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5972 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5973 vcpu->run->internal.ndata = 0;
5977 if (vcpu->arch.halt_request) {
5978 vcpu->arch.halt_request = 0;
5979 ret = kvm_vcpu_halt(vcpu);
5983 if (signal_pending(current))
5993 static int __grow_ple_window(int val)
5995 if (ple_window_grow < 1)
5998 val = min(val, ple_window_actual_max);
6000 if (ple_window_grow < ple_window)
6001 val *= ple_window_grow;
6003 val += ple_window_grow;
6008 static int __shrink_ple_window(int val, int modifier, int minimum)
6013 if (modifier < ple_window)
6018 return max(val, minimum);
6021 static void grow_ple_window(struct kvm_vcpu *vcpu)
6023 struct vcpu_vmx *vmx = to_vmx(vcpu);
6024 int old = vmx->ple_window;
6026 vmx->ple_window = __grow_ple_window(old);
6028 if (vmx->ple_window != old)
6029 vmx->ple_window_dirty = true;
6031 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6034 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6036 struct vcpu_vmx *vmx = to_vmx(vcpu);
6037 int old = vmx->ple_window;
6039 vmx->ple_window = __shrink_ple_window(old,
6040 ple_window_shrink, ple_window);
6042 if (vmx->ple_window != old)
6043 vmx->ple_window_dirty = true;
6045 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6049 * ple_window_actual_max is computed to be one grow_ple_window() below
6050 * ple_window_max. (See __grow_ple_window for the reason.)
6051 * This prevents overflows, because ple_window_max is int.
6052 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6054 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6056 static void update_ple_window_actual_max(void)
6058 ple_window_actual_max =
6059 __shrink_ple_window(max(ple_window_max, ple_window),
6060 ple_window_grow, INT_MIN);
6064 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6066 static void wakeup_handler(void)
6068 struct kvm_vcpu *vcpu;
6069 int cpu = smp_processor_id();
6071 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6072 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6073 blocked_vcpu_list) {
6074 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6076 if (pi_test_on(pi_desc) == 1)
6077 kvm_vcpu_kick(vcpu);
6079 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6082 static __init int hardware_setup(void)
6084 int r = -ENOMEM, i, msr;
6086 rdmsrl_safe(MSR_EFER, &host_efer);
6088 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6089 kvm_define_shared_msr(i, vmx_msr_index[i]);
6091 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6092 if (!vmx_io_bitmap_a)
6095 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6096 if (!vmx_io_bitmap_b)
6099 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6100 if (!vmx_msr_bitmap_legacy)
6103 vmx_msr_bitmap_legacy_x2apic =
6104 (unsigned long *)__get_free_page(GFP_KERNEL);
6105 if (!vmx_msr_bitmap_legacy_x2apic)
6108 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6109 if (!vmx_msr_bitmap_longmode)
6112 vmx_msr_bitmap_longmode_x2apic =
6113 (unsigned long *)__get_free_page(GFP_KERNEL);
6114 if (!vmx_msr_bitmap_longmode_x2apic)
6118 vmx_msr_bitmap_nested =
6119 (unsigned long *)__get_free_page(GFP_KERNEL);
6120 if (!vmx_msr_bitmap_nested)
6124 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6125 if (!vmx_vmread_bitmap)
6128 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6129 if (!vmx_vmwrite_bitmap)
6132 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6133 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6136 * Allow direct access to the PC debug port (it is often used for I/O
6137 * delays, but the vmexits simply slow things down).
6139 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6140 clear_bit(0x80, vmx_io_bitmap_a);
6142 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6144 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6145 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6147 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6149 if (setup_vmcs_config(&vmcs_config) < 0) {
6154 if (boot_cpu_has(X86_FEATURE_NX))
6155 kvm_enable_efer_bits(EFER_NX);
6157 if (!cpu_has_vmx_vpid())
6159 if (!cpu_has_vmx_shadow_vmcs())
6160 enable_shadow_vmcs = 0;
6161 if (enable_shadow_vmcs)
6162 init_vmcs_shadow_fields();
6164 if (!cpu_has_vmx_ept() ||
6165 !cpu_has_vmx_ept_4levels()) {
6167 enable_unrestricted_guest = 0;
6168 enable_ept_ad_bits = 0;
6171 if (!cpu_has_vmx_ept_ad_bits())
6172 enable_ept_ad_bits = 0;
6174 if (!cpu_has_vmx_unrestricted_guest())
6175 enable_unrestricted_guest = 0;
6177 if (!cpu_has_vmx_flexpriority())
6178 flexpriority_enabled = 0;
6181 * set_apic_access_page_addr() is used to reload apic access
6182 * page upon invalidation. No need to do anything if not
6183 * using the APIC_ACCESS_ADDR VMCS field.
6185 if (!flexpriority_enabled)
6186 kvm_x86_ops->set_apic_access_page_addr = NULL;
6188 if (!cpu_has_vmx_tpr_shadow())
6189 kvm_x86_ops->update_cr8_intercept = NULL;
6191 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6192 kvm_disable_largepages();
6194 if (!cpu_has_vmx_ple())
6197 if (!cpu_has_vmx_apicv())
6200 if (cpu_has_vmx_tsc_scaling()) {
6201 kvm_has_tsc_control = true;
6202 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6203 kvm_tsc_scaling_ratio_frac_bits = 48;
6207 kvm_x86_ops->update_cr8_intercept = NULL;
6209 kvm_x86_ops->hwapic_irr_update = NULL;
6210 kvm_x86_ops->hwapic_isr_update = NULL;
6211 kvm_x86_ops->deliver_posted_interrupt = NULL;
6212 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6215 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6216 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6217 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6218 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6219 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6220 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6221 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6223 memcpy(vmx_msr_bitmap_legacy_x2apic,
6224 vmx_msr_bitmap_legacy, PAGE_SIZE);
6225 memcpy(vmx_msr_bitmap_longmode_x2apic,
6226 vmx_msr_bitmap_longmode, PAGE_SIZE);
6228 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6231 for (msr = 0x800; msr <= 0x8ff; msr++)
6232 vmx_disable_intercept_msr_read_x2apic(msr);
6234 /* According SDM, in x2apic mode, the whole id reg is used.
6235 * But in KVM, it only use the highest eight bits. Need to
6237 vmx_enable_intercept_msr_read_x2apic(0x802);
6239 vmx_enable_intercept_msr_read_x2apic(0x839);
6241 vmx_disable_intercept_msr_write_x2apic(0x808);
6243 vmx_disable_intercept_msr_write_x2apic(0x80b);
6245 vmx_disable_intercept_msr_write_x2apic(0x83f);
6249 kvm_mmu_set_mask_ptes(0ull,
6250 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6251 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6252 0ull, VMX_EPT_EXECUTABLE_MASK);
6253 ept_set_mmio_spte_mask();
6258 update_ple_window_actual_max();
6261 * Only enable PML when hardware supports PML feature, and both EPT
6262 * and EPT A/D bit features are enabled -- PML depends on them to work.
6264 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6268 kvm_x86_ops->slot_enable_log_dirty = NULL;
6269 kvm_x86_ops->slot_disable_log_dirty = NULL;
6270 kvm_x86_ops->flush_log_dirty = NULL;
6271 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6274 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6276 return alloc_kvm_area();
6279 free_page((unsigned long)vmx_vmwrite_bitmap);
6281 free_page((unsigned long)vmx_vmread_bitmap);
6284 free_page((unsigned long)vmx_msr_bitmap_nested);
6286 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6288 free_page((unsigned long)vmx_msr_bitmap_longmode);
6290 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6292 free_page((unsigned long)vmx_msr_bitmap_legacy);
6294 free_page((unsigned long)vmx_io_bitmap_b);
6296 free_page((unsigned long)vmx_io_bitmap_a);
6301 static __exit void hardware_unsetup(void)
6303 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6304 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6305 free_page((unsigned long)vmx_msr_bitmap_legacy);
6306 free_page((unsigned long)vmx_msr_bitmap_longmode);
6307 free_page((unsigned long)vmx_io_bitmap_b);
6308 free_page((unsigned long)vmx_io_bitmap_a);
6309 free_page((unsigned long)vmx_vmwrite_bitmap);
6310 free_page((unsigned long)vmx_vmread_bitmap);
6312 free_page((unsigned long)vmx_msr_bitmap_nested);
6318 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6319 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6321 static int handle_pause(struct kvm_vcpu *vcpu)
6324 grow_ple_window(vcpu);
6326 skip_emulated_instruction(vcpu);
6327 kvm_vcpu_on_spin(vcpu);
6332 static int handle_nop(struct kvm_vcpu *vcpu)
6334 skip_emulated_instruction(vcpu);
6338 static int handle_mwait(struct kvm_vcpu *vcpu)
6340 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6341 return handle_nop(vcpu);
6344 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6349 static int handle_monitor(struct kvm_vcpu *vcpu)
6351 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6352 return handle_nop(vcpu);
6356 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6357 * We could reuse a single VMCS for all the L2 guests, but we also want the
6358 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6359 * allows keeping them loaded on the processor, and in the future will allow
6360 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6361 * every entry if they never change.
6362 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6363 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6365 * The following functions allocate and free a vmcs02 in this pool.
6368 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6369 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6371 struct vmcs02_list *item;
6372 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6373 if (item->vmptr == vmx->nested.current_vmptr) {
6374 list_move(&item->list, &vmx->nested.vmcs02_pool);
6375 return &item->vmcs02;
6378 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6379 /* Recycle the least recently used VMCS. */
6380 item = list_entry(vmx->nested.vmcs02_pool.prev,
6381 struct vmcs02_list, list);
6382 item->vmptr = vmx->nested.current_vmptr;
6383 list_move(&item->list, &vmx->nested.vmcs02_pool);
6384 return &item->vmcs02;
6387 /* Create a new VMCS */
6388 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6391 item->vmcs02.vmcs = alloc_vmcs();
6392 if (!item->vmcs02.vmcs) {
6396 loaded_vmcs_init(&item->vmcs02);
6397 item->vmptr = vmx->nested.current_vmptr;
6398 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6399 vmx->nested.vmcs02_num++;
6400 return &item->vmcs02;
6403 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6404 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6406 struct vmcs02_list *item;
6407 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6408 if (item->vmptr == vmptr) {
6409 free_loaded_vmcs(&item->vmcs02);
6410 list_del(&item->list);
6412 vmx->nested.vmcs02_num--;
6418 * Free all VMCSs saved for this vcpu, except the one pointed by
6419 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6420 * must be &vmx->vmcs01.
6422 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6424 struct vmcs02_list *item, *n;
6426 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6427 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6429 * Something will leak if the above WARN triggers. Better than
6432 if (vmx->loaded_vmcs == &item->vmcs02)
6435 free_loaded_vmcs(&item->vmcs02);
6436 list_del(&item->list);
6438 vmx->nested.vmcs02_num--;
6443 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6444 * set the success or error code of an emulated VMX instruction, as specified
6445 * by Vol 2B, VMX Instruction Reference, "Conventions".
6447 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6449 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6450 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6451 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6454 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6456 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6457 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6458 X86_EFLAGS_SF | X86_EFLAGS_OF))
6462 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6463 u32 vm_instruction_error)
6465 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6467 * failValid writes the error number to the current VMCS, which
6468 * can't be done there isn't a current VMCS.
6470 nested_vmx_failInvalid(vcpu);
6473 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6474 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6475 X86_EFLAGS_SF | X86_EFLAGS_OF))
6477 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6479 * We don't need to force a shadow sync because
6480 * VM_INSTRUCTION_ERROR is not shadowed
6484 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6486 /* TODO: not to reset guest simply here. */
6487 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6488 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6491 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6493 struct vcpu_vmx *vmx =
6494 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6496 vmx->nested.preemption_timer_expired = true;
6497 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6498 kvm_vcpu_kick(&vmx->vcpu);
6500 return HRTIMER_NORESTART;
6504 * Decode the memory-address operand of a vmx instruction, as recorded on an
6505 * exit caused by such an instruction (run by a guest hypervisor).
6506 * On success, returns 0. When the operand is invalid, returns 1 and throws
6509 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6510 unsigned long exit_qualification,
6511 u32 vmx_instruction_info, bool wr, gva_t *ret)
6515 struct kvm_segment s;
6518 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6519 * Execution", on an exit, vmx_instruction_info holds most of the
6520 * addressing components of the operand. Only the displacement part
6521 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6522 * For how an actual address is calculated from all these components,
6523 * refer to Vol. 1, "Operand Addressing".
6525 int scaling = vmx_instruction_info & 3;
6526 int addr_size = (vmx_instruction_info >> 7) & 7;
6527 bool is_reg = vmx_instruction_info & (1u << 10);
6528 int seg_reg = (vmx_instruction_info >> 15) & 7;
6529 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6530 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6531 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6532 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6535 kvm_queue_exception(vcpu, UD_VECTOR);
6539 /* Addr = segment_base + offset */
6540 /* offset = base + [index * scale] + displacement */
6541 off = exit_qualification; /* holds the displacement */
6543 off += kvm_register_read(vcpu, base_reg);
6545 off += kvm_register_read(vcpu, index_reg)<<scaling;
6546 vmx_get_segment(vcpu, &s, seg_reg);
6547 *ret = s.base + off;
6549 if (addr_size == 1) /* 32 bit */
6552 /* Checks for #GP/#SS exceptions. */
6554 if (is_protmode(vcpu)) {
6555 /* Protected mode: apply checks for segment validity in the
6557 * - segment type check (#GP(0) may be thrown)
6558 * - usability check (#GP(0)/#SS(0))
6559 * - limit check (#GP(0)/#SS(0))
6562 /* #GP(0) if the destination operand is located in a
6563 * read-only data segment or any code segment.
6565 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6567 /* #GP(0) if the source operand is located in an
6568 * execute-only code segment
6570 exn = ((s.type & 0xa) == 8);
6573 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6576 if (is_long_mode(vcpu)) {
6577 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6578 * non-canonical form. This is an only check for long mode.
6580 exn = is_noncanonical_address(*ret);
6581 } else if (is_protmode(vcpu)) {
6582 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6584 exn = (s.unusable != 0);
6585 /* Protected mode: #GP(0)/#SS(0) if the memory
6586 * operand is outside the segment limit.
6588 exn = exn || (off + sizeof(u64) > s.limit);
6591 kvm_queue_exception_e(vcpu,
6592 seg_reg == VCPU_SREG_SS ?
6593 SS_VECTOR : GP_VECTOR,
6602 * This function performs the various checks including
6603 * - if it's 4KB aligned
6604 * - No bits beyond the physical address width are set
6605 * - Returns 0 on success or else 1
6606 * (Intel SDM Section 30.3)
6608 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6613 struct x86_exception e;
6615 struct vcpu_vmx *vmx = to_vmx(vcpu);
6616 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6618 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6619 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6622 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6623 sizeof(vmptr), &e)) {
6624 kvm_inject_page_fault(vcpu, &e);
6628 switch (exit_reason) {
6629 case EXIT_REASON_VMON:
6632 * The first 4 bytes of VMXON region contain the supported
6633 * VMCS revision identifier
6635 * Note - IA32_VMX_BASIC[48] will never be 1
6636 * for the nested case;
6637 * which replaces physical address width with 32
6640 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6641 nested_vmx_failInvalid(vcpu);
6642 skip_emulated_instruction(vcpu);
6646 page = nested_get_page(vcpu, vmptr);
6648 *(u32 *)kmap(page) != VMCS12_REVISION) {
6649 nested_vmx_failInvalid(vcpu);
6651 skip_emulated_instruction(vcpu);
6655 vmx->nested.vmxon_ptr = vmptr;
6657 case EXIT_REASON_VMCLEAR:
6658 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6659 nested_vmx_failValid(vcpu,
6660 VMXERR_VMCLEAR_INVALID_ADDRESS);
6661 skip_emulated_instruction(vcpu);
6665 if (vmptr == vmx->nested.vmxon_ptr) {
6666 nested_vmx_failValid(vcpu,
6667 VMXERR_VMCLEAR_VMXON_POINTER);
6668 skip_emulated_instruction(vcpu);
6672 case EXIT_REASON_VMPTRLD:
6673 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6674 nested_vmx_failValid(vcpu,
6675 VMXERR_VMPTRLD_INVALID_ADDRESS);
6676 skip_emulated_instruction(vcpu);
6680 if (vmptr == vmx->nested.vmxon_ptr) {
6681 nested_vmx_failValid(vcpu,
6682 VMXERR_VMCLEAR_VMXON_POINTER);
6683 skip_emulated_instruction(vcpu);
6688 return 1; /* shouldn't happen */
6697 * Emulate the VMXON instruction.
6698 * Currently, we just remember that VMX is active, and do not save or even
6699 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6700 * do not currently need to store anything in that guest-allocated memory
6701 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6702 * argument is different from the VMXON pointer (which the spec says they do).
6704 static int handle_vmon(struct kvm_vcpu *vcpu)
6706 struct kvm_segment cs;
6707 struct vcpu_vmx *vmx = to_vmx(vcpu);
6708 struct vmcs *shadow_vmcs;
6709 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6710 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6712 /* The Intel VMX Instruction Reference lists a bunch of bits that
6713 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6714 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6715 * Otherwise, we should fail with #UD. We test these now:
6717 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6718 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6719 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6720 kvm_queue_exception(vcpu, UD_VECTOR);
6724 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6725 if (is_long_mode(vcpu) && !cs.l) {
6726 kvm_queue_exception(vcpu, UD_VECTOR);
6730 if (vmx_get_cpl(vcpu)) {
6731 kvm_inject_gp(vcpu, 0);
6735 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6738 if (vmx->nested.vmxon) {
6739 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6740 skip_emulated_instruction(vcpu);
6744 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6745 != VMXON_NEEDED_FEATURES) {
6746 kvm_inject_gp(vcpu, 0);
6750 if (enable_shadow_vmcs) {
6751 shadow_vmcs = alloc_vmcs();
6754 /* mark vmcs as shadow */
6755 shadow_vmcs->revision_id |= (1u << 31);
6756 /* init shadow vmcs */
6757 vmcs_clear(shadow_vmcs);
6758 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6761 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6762 vmx->nested.vmcs02_num = 0;
6764 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6766 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6768 vmx->nested.vmxon = true;
6770 skip_emulated_instruction(vcpu);
6771 nested_vmx_succeed(vcpu);
6776 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6777 * for running VMX instructions (except VMXON, whose prerequisites are
6778 * slightly different). It also specifies what exception to inject otherwise.
6780 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6782 struct kvm_segment cs;
6783 struct vcpu_vmx *vmx = to_vmx(vcpu);
6785 if (!vmx->nested.vmxon) {
6786 kvm_queue_exception(vcpu, UD_VECTOR);
6790 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6791 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6792 (is_long_mode(vcpu) && !cs.l)) {
6793 kvm_queue_exception(vcpu, UD_VECTOR);
6797 if (vmx_get_cpl(vcpu)) {
6798 kvm_inject_gp(vcpu, 0);
6805 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6807 if (vmx->nested.current_vmptr == -1ull)
6810 /* current_vmptr and current_vmcs12 are always set/reset together */
6811 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6814 if (enable_shadow_vmcs) {
6815 /* copy to memory all shadowed fields in case
6816 they were modified */
6817 copy_shadow_to_vmcs12(vmx);
6818 vmx->nested.sync_shadow_vmcs = false;
6819 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6820 SECONDARY_EXEC_SHADOW_VMCS);
6821 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6823 vmx->nested.posted_intr_nv = -1;
6824 kunmap(vmx->nested.current_vmcs12_page);
6825 nested_release_page(vmx->nested.current_vmcs12_page);
6826 vmx->nested.current_vmptr = -1ull;
6827 vmx->nested.current_vmcs12 = NULL;
6831 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6832 * just stops using VMX.
6834 static void free_nested(struct vcpu_vmx *vmx)
6836 if (!vmx->nested.vmxon)
6839 vmx->nested.vmxon = false;
6840 free_vpid(vmx->nested.vpid02);
6841 nested_release_vmcs12(vmx);
6842 if (enable_shadow_vmcs)
6843 free_vmcs(vmx->nested.current_shadow_vmcs);
6844 /* Unpin physical memory we referred to in current vmcs02 */
6845 if (vmx->nested.apic_access_page) {
6846 nested_release_page(vmx->nested.apic_access_page);
6847 vmx->nested.apic_access_page = NULL;
6849 if (vmx->nested.virtual_apic_page) {
6850 nested_release_page(vmx->nested.virtual_apic_page);
6851 vmx->nested.virtual_apic_page = NULL;
6853 if (vmx->nested.pi_desc_page) {
6854 kunmap(vmx->nested.pi_desc_page);
6855 nested_release_page(vmx->nested.pi_desc_page);
6856 vmx->nested.pi_desc_page = NULL;
6857 vmx->nested.pi_desc = NULL;
6860 nested_free_all_saved_vmcss(vmx);
6863 /* Emulate the VMXOFF instruction */
6864 static int handle_vmoff(struct kvm_vcpu *vcpu)
6866 if (!nested_vmx_check_permission(vcpu))
6868 free_nested(to_vmx(vcpu));
6869 skip_emulated_instruction(vcpu);
6870 nested_vmx_succeed(vcpu);
6874 /* Emulate the VMCLEAR instruction */
6875 static int handle_vmclear(struct kvm_vcpu *vcpu)
6877 struct vcpu_vmx *vmx = to_vmx(vcpu);
6879 struct vmcs12 *vmcs12;
6882 if (!nested_vmx_check_permission(vcpu))
6885 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6888 if (vmptr == vmx->nested.current_vmptr)
6889 nested_release_vmcs12(vmx);
6891 page = nested_get_page(vcpu, vmptr);
6894 * For accurate processor emulation, VMCLEAR beyond available
6895 * physical memory should do nothing at all. However, it is
6896 * possible that a nested vmx bug, not a guest hypervisor bug,
6897 * resulted in this case, so let's shut down before doing any
6900 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6903 vmcs12 = kmap(page);
6904 vmcs12->launch_state = 0;
6906 nested_release_page(page);
6908 nested_free_vmcs02(vmx, vmptr);
6910 skip_emulated_instruction(vcpu);
6911 nested_vmx_succeed(vcpu);
6915 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6917 /* Emulate the VMLAUNCH instruction */
6918 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6920 return nested_vmx_run(vcpu, true);
6923 /* Emulate the VMRESUME instruction */
6924 static int handle_vmresume(struct kvm_vcpu *vcpu)
6927 return nested_vmx_run(vcpu, false);
6930 enum vmcs_field_type {
6931 VMCS_FIELD_TYPE_U16 = 0,
6932 VMCS_FIELD_TYPE_U64 = 1,
6933 VMCS_FIELD_TYPE_U32 = 2,
6934 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6937 static inline int vmcs_field_type(unsigned long field)
6939 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6940 return VMCS_FIELD_TYPE_U32;
6941 return (field >> 13) & 0x3 ;
6944 static inline int vmcs_field_readonly(unsigned long field)
6946 return (((field >> 10) & 0x3) == 1);
6950 * Read a vmcs12 field. Since these can have varying lengths and we return
6951 * one type, we chose the biggest type (u64) and zero-extend the return value
6952 * to that size. Note that the caller, handle_vmread, might need to use only
6953 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6954 * 64-bit fields are to be returned).
6956 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6957 unsigned long field, u64 *ret)
6959 short offset = vmcs_field_to_offset(field);
6965 p = ((char *)(get_vmcs12(vcpu))) + offset;
6967 switch (vmcs_field_type(field)) {
6968 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6969 *ret = *((natural_width *)p);
6971 case VMCS_FIELD_TYPE_U16:
6974 case VMCS_FIELD_TYPE_U32:
6977 case VMCS_FIELD_TYPE_U64:
6987 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6988 unsigned long field, u64 field_value){
6989 short offset = vmcs_field_to_offset(field);
6990 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6994 switch (vmcs_field_type(field)) {
6995 case VMCS_FIELD_TYPE_U16:
6996 *(u16 *)p = field_value;
6998 case VMCS_FIELD_TYPE_U32:
6999 *(u32 *)p = field_value;
7001 case VMCS_FIELD_TYPE_U64:
7002 *(u64 *)p = field_value;
7004 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7005 *(natural_width *)p = field_value;
7014 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7017 unsigned long field;
7019 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7020 const unsigned long *fields = shadow_read_write_fields;
7021 const int num_fields = max_shadow_read_write_fields;
7025 vmcs_load(shadow_vmcs);
7027 for (i = 0; i < num_fields; i++) {
7029 switch (vmcs_field_type(field)) {
7030 case VMCS_FIELD_TYPE_U16:
7031 field_value = vmcs_read16(field);
7033 case VMCS_FIELD_TYPE_U32:
7034 field_value = vmcs_read32(field);
7036 case VMCS_FIELD_TYPE_U64:
7037 field_value = vmcs_read64(field);
7039 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7040 field_value = vmcs_readl(field);
7046 vmcs12_write_any(&vmx->vcpu, field, field_value);
7049 vmcs_clear(shadow_vmcs);
7050 vmcs_load(vmx->loaded_vmcs->vmcs);
7055 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7057 const unsigned long *fields[] = {
7058 shadow_read_write_fields,
7059 shadow_read_only_fields
7061 const int max_fields[] = {
7062 max_shadow_read_write_fields,
7063 max_shadow_read_only_fields
7066 unsigned long field;
7067 u64 field_value = 0;
7068 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7070 vmcs_load(shadow_vmcs);
7072 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7073 for (i = 0; i < max_fields[q]; i++) {
7074 field = fields[q][i];
7075 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7077 switch (vmcs_field_type(field)) {
7078 case VMCS_FIELD_TYPE_U16:
7079 vmcs_write16(field, (u16)field_value);
7081 case VMCS_FIELD_TYPE_U32:
7082 vmcs_write32(field, (u32)field_value);
7084 case VMCS_FIELD_TYPE_U64:
7085 vmcs_write64(field, (u64)field_value);
7087 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7088 vmcs_writel(field, (long)field_value);
7097 vmcs_clear(shadow_vmcs);
7098 vmcs_load(vmx->loaded_vmcs->vmcs);
7102 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7103 * used before) all generate the same failure when it is missing.
7105 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7107 struct vcpu_vmx *vmx = to_vmx(vcpu);
7108 if (vmx->nested.current_vmptr == -1ull) {
7109 nested_vmx_failInvalid(vcpu);
7110 skip_emulated_instruction(vcpu);
7116 static int handle_vmread(struct kvm_vcpu *vcpu)
7118 unsigned long field;
7120 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7121 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7124 if (!nested_vmx_check_permission(vcpu) ||
7125 !nested_vmx_check_vmcs12(vcpu))
7128 /* Decode instruction info and find the field to read */
7129 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7130 /* Read the field, zero-extended to a u64 field_value */
7131 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7132 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7133 skip_emulated_instruction(vcpu);
7137 * Now copy part of this value to register or memory, as requested.
7138 * Note that the number of bits actually copied is 32 or 64 depending
7139 * on the guest's mode (32 or 64 bit), not on the given field's length.
7141 if (vmx_instruction_info & (1u << 10)) {
7142 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7145 if (get_vmx_mem_address(vcpu, exit_qualification,
7146 vmx_instruction_info, true, &gva))
7148 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7149 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7150 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7153 nested_vmx_succeed(vcpu);
7154 skip_emulated_instruction(vcpu);
7159 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7161 unsigned long field;
7163 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7164 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7165 /* The value to write might be 32 or 64 bits, depending on L1's long
7166 * mode, and eventually we need to write that into a field of several
7167 * possible lengths. The code below first zero-extends the value to 64
7168 * bit (field_value), and then copies only the approriate number of
7169 * bits into the vmcs12 field.
7171 u64 field_value = 0;
7172 struct x86_exception e;
7174 if (!nested_vmx_check_permission(vcpu) ||
7175 !nested_vmx_check_vmcs12(vcpu))
7178 if (vmx_instruction_info & (1u << 10))
7179 field_value = kvm_register_readl(vcpu,
7180 (((vmx_instruction_info) >> 3) & 0xf));
7182 if (get_vmx_mem_address(vcpu, exit_qualification,
7183 vmx_instruction_info, false, &gva))
7185 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7186 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7187 kvm_inject_page_fault(vcpu, &e);
7193 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7194 if (vmcs_field_readonly(field)) {
7195 nested_vmx_failValid(vcpu,
7196 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7197 skip_emulated_instruction(vcpu);
7201 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7202 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7203 skip_emulated_instruction(vcpu);
7207 nested_vmx_succeed(vcpu);
7208 skip_emulated_instruction(vcpu);
7212 /* Emulate the VMPTRLD instruction */
7213 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7215 struct vcpu_vmx *vmx = to_vmx(vcpu);
7218 if (!nested_vmx_check_permission(vcpu))
7221 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7224 if (vmx->nested.current_vmptr != vmptr) {
7225 struct vmcs12 *new_vmcs12;
7227 page = nested_get_page(vcpu, vmptr);
7229 nested_vmx_failInvalid(vcpu);
7230 skip_emulated_instruction(vcpu);
7233 new_vmcs12 = kmap(page);
7234 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7236 nested_release_page_clean(page);
7237 nested_vmx_failValid(vcpu,
7238 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7239 skip_emulated_instruction(vcpu);
7243 nested_release_vmcs12(vmx);
7244 vmx->nested.current_vmptr = vmptr;
7245 vmx->nested.current_vmcs12 = new_vmcs12;
7246 vmx->nested.current_vmcs12_page = page;
7247 if (enable_shadow_vmcs) {
7248 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7249 SECONDARY_EXEC_SHADOW_VMCS);
7250 vmcs_write64(VMCS_LINK_POINTER,
7251 __pa(vmx->nested.current_shadow_vmcs));
7252 vmx->nested.sync_shadow_vmcs = true;
7256 nested_vmx_succeed(vcpu);
7257 skip_emulated_instruction(vcpu);
7261 /* Emulate the VMPTRST instruction */
7262 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7264 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7265 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7267 struct x86_exception e;
7269 if (!nested_vmx_check_permission(vcpu))
7272 if (get_vmx_mem_address(vcpu, exit_qualification,
7273 vmx_instruction_info, true, &vmcs_gva))
7275 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7276 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7277 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7279 kvm_inject_page_fault(vcpu, &e);
7282 nested_vmx_succeed(vcpu);
7283 skip_emulated_instruction(vcpu);
7287 /* Emulate the INVEPT instruction */
7288 static int handle_invept(struct kvm_vcpu *vcpu)
7290 struct vcpu_vmx *vmx = to_vmx(vcpu);
7291 u32 vmx_instruction_info, types;
7294 struct x86_exception e;
7299 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7300 SECONDARY_EXEC_ENABLE_EPT) ||
7301 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7302 kvm_queue_exception(vcpu, UD_VECTOR);
7306 if (!nested_vmx_check_permission(vcpu))
7309 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7310 kvm_queue_exception(vcpu, UD_VECTOR);
7314 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7315 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7317 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7319 if (!(types & (1UL << type))) {
7320 nested_vmx_failValid(vcpu,
7321 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7325 /* According to the Intel VMX instruction reference, the memory
7326 * operand is read even if it isn't needed (e.g., for type==global)
7328 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7329 vmx_instruction_info, false, &gva))
7331 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7332 sizeof(operand), &e)) {
7333 kvm_inject_page_fault(vcpu, &e);
7338 case VMX_EPT_EXTENT_GLOBAL:
7339 kvm_mmu_sync_roots(vcpu);
7340 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7341 nested_vmx_succeed(vcpu);
7344 /* Trap single context invalidation invept calls */
7349 skip_emulated_instruction(vcpu);
7353 static int handle_invvpid(struct kvm_vcpu *vcpu)
7355 struct vcpu_vmx *vmx = to_vmx(vcpu);
7356 u32 vmx_instruction_info;
7357 unsigned long type, types;
7359 struct x86_exception e;
7362 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7363 SECONDARY_EXEC_ENABLE_VPID) ||
7364 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7365 kvm_queue_exception(vcpu, UD_VECTOR);
7369 if (!nested_vmx_check_permission(vcpu))
7372 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7373 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7375 types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7377 if (!(types & (1UL << type))) {
7378 nested_vmx_failValid(vcpu,
7379 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7383 /* according to the intel vmx instruction reference, the memory
7384 * operand is read even if it isn't needed (e.g., for type==global)
7386 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7387 vmx_instruction_info, false, &gva))
7389 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7391 kvm_inject_page_fault(vcpu, &e);
7396 case VMX_VPID_EXTENT_ALL_CONTEXT:
7397 if (get_vmcs12(vcpu)->virtual_processor_id == 0) {
7398 nested_vmx_failValid(vcpu,
7399 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7402 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7403 nested_vmx_succeed(vcpu);
7406 /* Trap single context invalidation invvpid calls */
7411 skip_emulated_instruction(vcpu);
7415 static int handle_pml_full(struct kvm_vcpu *vcpu)
7417 unsigned long exit_qualification;
7419 trace_kvm_pml_full(vcpu->vcpu_id);
7421 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7424 * PML buffer FULL happened while executing iret from NMI,
7425 * "blocked by NMI" bit has to be set before next VM entry.
7427 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7428 cpu_has_virtual_nmis() &&
7429 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7430 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7431 GUEST_INTR_STATE_NMI);
7434 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7435 * here.., and there's no userspace involvement needed for PML.
7440 static int handle_pcommit(struct kvm_vcpu *vcpu)
7442 /* we never catch pcommit instruct for L1 guest. */
7448 * The exit handlers return 1 if the exit was handled fully and guest execution
7449 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7450 * to be done to userspace and return 0.
7452 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7453 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7454 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7455 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7456 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7457 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7458 [EXIT_REASON_CR_ACCESS] = handle_cr,
7459 [EXIT_REASON_DR_ACCESS] = handle_dr,
7460 [EXIT_REASON_CPUID] = handle_cpuid,
7461 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7462 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7463 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7464 [EXIT_REASON_HLT] = handle_halt,
7465 [EXIT_REASON_INVD] = handle_invd,
7466 [EXIT_REASON_INVLPG] = handle_invlpg,
7467 [EXIT_REASON_RDPMC] = handle_rdpmc,
7468 [EXIT_REASON_VMCALL] = handle_vmcall,
7469 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7470 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7471 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7472 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7473 [EXIT_REASON_VMREAD] = handle_vmread,
7474 [EXIT_REASON_VMRESUME] = handle_vmresume,
7475 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7476 [EXIT_REASON_VMOFF] = handle_vmoff,
7477 [EXIT_REASON_VMON] = handle_vmon,
7478 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7479 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7480 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7481 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7482 [EXIT_REASON_WBINVD] = handle_wbinvd,
7483 [EXIT_REASON_XSETBV] = handle_xsetbv,
7484 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7485 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7486 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7487 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7488 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7489 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7490 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7491 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7492 [EXIT_REASON_INVEPT] = handle_invept,
7493 [EXIT_REASON_INVVPID] = handle_invvpid,
7494 [EXIT_REASON_XSAVES] = handle_xsaves,
7495 [EXIT_REASON_XRSTORS] = handle_xrstors,
7496 [EXIT_REASON_PML_FULL] = handle_pml_full,
7497 [EXIT_REASON_PCOMMIT] = handle_pcommit,
7500 static const int kvm_vmx_max_exit_handlers =
7501 ARRAY_SIZE(kvm_vmx_exit_handlers);
7503 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7504 struct vmcs12 *vmcs12)
7506 unsigned long exit_qualification;
7507 gpa_t bitmap, last_bitmap;
7512 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7513 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7515 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7517 port = exit_qualification >> 16;
7518 size = (exit_qualification & 7) + 1;
7520 last_bitmap = (gpa_t)-1;
7525 bitmap = vmcs12->io_bitmap_a;
7526 else if (port < 0x10000)
7527 bitmap = vmcs12->io_bitmap_b;
7530 bitmap += (port & 0x7fff) / 8;
7532 if (last_bitmap != bitmap)
7533 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7535 if (b & (1 << (port & 7)))
7540 last_bitmap = bitmap;
7547 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7548 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7549 * disinterest in the current event (read or write a specific MSR) by using an
7550 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7552 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7553 struct vmcs12 *vmcs12, u32 exit_reason)
7555 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7558 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7562 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7563 * for the four combinations of read/write and low/high MSR numbers.
7564 * First we need to figure out which of the four to use:
7566 bitmap = vmcs12->msr_bitmap;
7567 if (exit_reason == EXIT_REASON_MSR_WRITE)
7569 if (msr_index >= 0xc0000000) {
7570 msr_index -= 0xc0000000;
7574 /* Then read the msr_index'th bit from this bitmap: */
7575 if (msr_index < 1024*8) {
7577 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7579 return 1 & (b >> (msr_index & 7));
7581 return true; /* let L1 handle the wrong parameter */
7585 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7586 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7587 * intercept (via guest_host_mask etc.) the current event.
7589 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7590 struct vmcs12 *vmcs12)
7592 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7593 int cr = exit_qualification & 15;
7594 int reg = (exit_qualification >> 8) & 15;
7595 unsigned long val = kvm_register_readl(vcpu, reg);
7597 switch ((exit_qualification >> 4) & 3) {
7598 case 0: /* mov to cr */
7601 if (vmcs12->cr0_guest_host_mask &
7602 (val ^ vmcs12->cr0_read_shadow))
7606 if ((vmcs12->cr3_target_count >= 1 &&
7607 vmcs12->cr3_target_value0 == val) ||
7608 (vmcs12->cr3_target_count >= 2 &&
7609 vmcs12->cr3_target_value1 == val) ||
7610 (vmcs12->cr3_target_count >= 3 &&
7611 vmcs12->cr3_target_value2 == val) ||
7612 (vmcs12->cr3_target_count >= 4 &&
7613 vmcs12->cr3_target_value3 == val))
7615 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7619 if (vmcs12->cr4_guest_host_mask &
7620 (vmcs12->cr4_read_shadow ^ val))
7624 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7630 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7631 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7634 case 1: /* mov from cr */
7637 if (vmcs12->cpu_based_vm_exec_control &
7638 CPU_BASED_CR3_STORE_EXITING)
7642 if (vmcs12->cpu_based_vm_exec_control &
7643 CPU_BASED_CR8_STORE_EXITING)
7650 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7651 * cr0. Other attempted changes are ignored, with no exit.
7653 if (vmcs12->cr0_guest_host_mask & 0xe &
7654 (val ^ vmcs12->cr0_read_shadow))
7656 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7657 !(vmcs12->cr0_read_shadow & 0x1) &&
7666 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7667 * should handle it ourselves in L0 (and then continue L2). Only call this
7668 * when in is_guest_mode (L2).
7670 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7672 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7673 struct vcpu_vmx *vmx = to_vmx(vcpu);
7674 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7675 u32 exit_reason = vmx->exit_reason;
7677 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7678 vmcs_readl(EXIT_QUALIFICATION),
7679 vmx->idt_vectoring_info,
7681 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7684 if (vmx->nested.nested_run_pending)
7687 if (unlikely(vmx->fail)) {
7688 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7689 vmcs_read32(VM_INSTRUCTION_ERROR));
7693 switch (exit_reason) {
7694 case EXIT_REASON_EXCEPTION_NMI:
7695 if (!is_exception(intr_info))
7697 else if (is_page_fault(intr_info))
7699 else if (is_no_device(intr_info) &&
7700 !(vmcs12->guest_cr0 & X86_CR0_TS))
7702 return vmcs12->exception_bitmap &
7703 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7704 case EXIT_REASON_EXTERNAL_INTERRUPT:
7706 case EXIT_REASON_TRIPLE_FAULT:
7708 case EXIT_REASON_PENDING_INTERRUPT:
7709 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7710 case EXIT_REASON_NMI_WINDOW:
7711 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7712 case EXIT_REASON_TASK_SWITCH:
7714 case EXIT_REASON_CPUID:
7715 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7718 case EXIT_REASON_HLT:
7719 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7720 case EXIT_REASON_INVD:
7722 case EXIT_REASON_INVLPG:
7723 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7724 case EXIT_REASON_RDPMC:
7725 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7726 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7727 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7728 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7729 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7730 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7731 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7732 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7733 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7735 * VMX instructions trap unconditionally. This allows L1 to
7736 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7739 case EXIT_REASON_CR_ACCESS:
7740 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7741 case EXIT_REASON_DR_ACCESS:
7742 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7743 case EXIT_REASON_IO_INSTRUCTION:
7744 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7745 case EXIT_REASON_MSR_READ:
7746 case EXIT_REASON_MSR_WRITE:
7747 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7748 case EXIT_REASON_INVALID_STATE:
7750 case EXIT_REASON_MWAIT_INSTRUCTION:
7751 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7752 case EXIT_REASON_MONITOR_TRAP_FLAG:
7753 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7754 case EXIT_REASON_MONITOR_INSTRUCTION:
7755 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7756 case EXIT_REASON_PAUSE_INSTRUCTION:
7757 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7758 nested_cpu_has2(vmcs12,
7759 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7760 case EXIT_REASON_MCE_DURING_VMENTRY:
7762 case EXIT_REASON_TPR_BELOW_THRESHOLD:
7763 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7764 case EXIT_REASON_APIC_ACCESS:
7765 return nested_cpu_has2(vmcs12,
7766 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7767 case EXIT_REASON_APIC_WRITE:
7768 case EXIT_REASON_EOI_INDUCED:
7769 /* apic_write and eoi_induced should exit unconditionally. */
7771 case EXIT_REASON_EPT_VIOLATION:
7773 * L0 always deals with the EPT violation. If nested EPT is
7774 * used, and the nested mmu code discovers that the address is
7775 * missing in the guest EPT table (EPT12), the EPT violation
7776 * will be injected with nested_ept_inject_page_fault()
7779 case EXIT_REASON_EPT_MISCONFIG:
7781 * L2 never uses directly L1's EPT, but rather L0's own EPT
7782 * table (shadow on EPT) or a merged EPT table that L0 built
7783 * (EPT on EPT). So any problems with the structure of the
7784 * table is L0's fault.
7787 case EXIT_REASON_WBINVD:
7788 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7789 case EXIT_REASON_XSETBV:
7791 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7793 * This should never happen, since it is not possible to
7794 * set XSS to a non-zero value---neither in L1 nor in L2.
7795 * If if it were, XSS would have to be checked against
7796 * the XSS exit bitmap in vmcs12.
7798 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7799 case EXIT_REASON_PCOMMIT:
7800 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7806 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7808 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7809 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7812 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7814 struct page *pml_pg;
7816 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7820 vmx->pml_pg = pml_pg;
7822 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7823 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7828 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7831 __free_page(vmx->pml_pg);
7836 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7838 struct vcpu_vmx *vmx = to_vmx(vcpu);
7842 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7844 /* Do nothing if PML buffer is empty */
7845 if (pml_idx == (PML_ENTITY_NUM - 1))
7848 /* PML index always points to next available PML buffer entity */
7849 if (pml_idx >= PML_ENTITY_NUM)
7854 pml_buf = page_address(vmx->pml_pg);
7855 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7858 gpa = pml_buf[pml_idx];
7859 WARN_ON(gpa & (PAGE_SIZE - 1));
7860 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7863 /* reset PML index */
7864 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7868 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7869 * Called before reporting dirty_bitmap to userspace.
7871 static void kvm_flush_pml_buffers(struct kvm *kvm)
7874 struct kvm_vcpu *vcpu;
7876 * We only need to kick vcpu out of guest mode here, as PML buffer
7877 * is flushed at beginning of all VMEXITs, and it's obvious that only
7878 * vcpus running in guest are possible to have unflushed GPAs in PML
7881 kvm_for_each_vcpu(i, vcpu, kvm)
7882 kvm_vcpu_kick(vcpu);
7885 static void vmx_dump_sel(char *name, uint32_t sel)
7887 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7888 name, vmcs_read32(sel),
7889 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7890 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7891 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7894 static void vmx_dump_dtsel(char *name, uint32_t limit)
7896 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7897 name, vmcs_read32(limit),
7898 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7901 static void dump_vmcs(void)
7903 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7904 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7905 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7906 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7907 u32 secondary_exec_control = 0;
7908 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7909 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7912 if (cpu_has_secondary_exec_ctrls())
7913 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7915 pr_err("*** Guest State ***\n");
7916 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7917 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7918 vmcs_readl(CR0_GUEST_HOST_MASK));
7919 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7920 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7921 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7922 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7923 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7925 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7926 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7927 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7928 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7930 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7931 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7932 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7933 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7934 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7935 vmcs_readl(GUEST_SYSENTER_ESP),
7936 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7937 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7938 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7939 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7940 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7941 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7942 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7943 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7944 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7945 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7946 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7947 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7948 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7949 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7950 efer, vmcs_readl(GUEST_IA32_PAT));
7951 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7952 vmcs_readl(GUEST_IA32_DEBUGCTL),
7953 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7954 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7955 pr_err("PerfGlobCtl = 0x%016lx\n",
7956 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7957 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7958 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7959 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7960 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7961 vmcs_read32(GUEST_ACTIVITY_STATE));
7962 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7963 pr_err("InterruptStatus = %04x\n",
7964 vmcs_read16(GUEST_INTR_STATUS));
7966 pr_err("*** Host State ***\n");
7967 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7968 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7969 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7970 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7971 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7972 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7973 vmcs_read16(HOST_TR_SELECTOR));
7974 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7975 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7976 vmcs_readl(HOST_TR_BASE));
7977 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7978 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7979 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7980 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7981 vmcs_readl(HOST_CR4));
7982 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7983 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7984 vmcs_read32(HOST_IA32_SYSENTER_CS),
7985 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7986 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7987 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7988 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7989 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7990 pr_err("PerfGlobCtl = 0x%016lx\n",
7991 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7993 pr_err("*** Control State ***\n");
7994 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7995 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7996 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7997 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7998 vmcs_read32(EXCEPTION_BITMAP),
7999 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8000 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8001 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8002 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8003 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8004 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8005 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8006 vmcs_read32(VM_EXIT_INTR_INFO),
8007 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8008 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8009 pr_err(" reason=%08x qualification=%016lx\n",
8010 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8011 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8012 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8013 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8014 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8015 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8016 pr_err("TSC Multiplier = 0x%016lx\n",
8017 vmcs_readl(TSC_MULTIPLIER));
8018 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8019 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8020 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8021 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8022 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8023 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8024 n = vmcs_read32(CR3_TARGET_COUNT);
8025 for (i = 0; i + 1 < n; i += 4)
8026 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8027 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8028 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8030 pr_err("CR3 target%u=%016lx\n",
8031 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8032 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8033 pr_err("PLE Gap=%08x Window=%08x\n",
8034 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8035 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8036 pr_err("Virtual processor ID = 0x%04x\n",
8037 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8041 * The guest has exited. See if we can fix it or if we need userspace
8044 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8046 struct vcpu_vmx *vmx = to_vmx(vcpu);
8047 u32 exit_reason = vmx->exit_reason;
8048 u32 vectoring_info = vmx->idt_vectoring_info;
8051 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8052 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8053 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8054 * mode as if vcpus is in root mode, the PML buffer must has been
8058 vmx_flush_pml_buffer(vcpu);
8060 /* If guest state is invalid, start emulating */
8061 if (vmx->emulation_required)
8062 return handle_invalid_guest_state(vcpu);
8064 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8065 nested_vmx_vmexit(vcpu, exit_reason,
8066 vmcs_read32(VM_EXIT_INTR_INFO),
8067 vmcs_readl(EXIT_QUALIFICATION));
8071 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8073 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8074 vcpu->run->fail_entry.hardware_entry_failure_reason
8079 if (unlikely(vmx->fail)) {
8080 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8081 vcpu->run->fail_entry.hardware_entry_failure_reason
8082 = vmcs_read32(VM_INSTRUCTION_ERROR);
8088 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8089 * delivery event since it indicates guest is accessing MMIO.
8090 * The vm-exit can be triggered again after return to guest that
8091 * will cause infinite loop.
8093 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8094 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8095 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8096 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8097 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8098 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8099 vcpu->run->internal.ndata = 2;
8100 vcpu->run->internal.data[0] = vectoring_info;
8101 vcpu->run->internal.data[1] = exit_reason;
8105 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8106 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8107 get_vmcs12(vcpu))))) {
8108 if (vmx_interrupt_allowed(vcpu)) {
8109 vmx->soft_vnmi_blocked = 0;
8110 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8111 vcpu->arch.nmi_pending) {
8113 * This CPU don't support us in finding the end of an
8114 * NMI-blocked window if the guest runs with IRQs
8115 * disabled. So we pull the trigger after 1 s of
8116 * futile waiting, but inform the user about this.
8118 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8119 "state on VCPU %d after 1 s timeout\n",
8120 __func__, vcpu->vcpu_id);
8121 vmx->soft_vnmi_blocked = 0;
8125 if (exit_reason < kvm_vmx_max_exit_handlers
8126 && kvm_vmx_exit_handlers[exit_reason])
8127 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8129 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8130 kvm_queue_exception(vcpu, UD_VECTOR);
8135 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8137 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8139 if (is_guest_mode(vcpu) &&
8140 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8143 if (irr == -1 || tpr < irr) {
8144 vmcs_write32(TPR_THRESHOLD, 0);
8148 vmcs_write32(TPR_THRESHOLD, irr);
8151 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8153 u32 sec_exec_control;
8156 * There is not point to enable virtualize x2apic without enable
8159 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8160 !vmx_cpu_uses_apicv(vcpu))
8163 if (!cpu_need_tpr_shadow(vcpu))
8166 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8169 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8170 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8172 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8173 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8175 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8177 vmx_set_msr_bitmap(vcpu);
8180 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8182 struct vcpu_vmx *vmx = to_vmx(vcpu);
8185 * Currently we do not handle the nested case where L2 has an
8186 * APIC access page of its own; that page is still pinned.
8187 * Hence, we skip the case where the VCPU is in guest mode _and_
8188 * L1 prepared an APIC access page for L2.
8190 * For the case where L1 and L2 share the same APIC access page
8191 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8192 * in the vmcs12), this function will only update either the vmcs01
8193 * or the vmcs02. If the former, the vmcs02 will be updated by
8194 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8195 * the next L2->L1 exit.
8197 if (!is_guest_mode(vcpu) ||
8198 !nested_cpu_has2(vmx->nested.current_vmcs12,
8199 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8200 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8203 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8211 status = vmcs_read16(GUEST_INTR_STATUS);
8216 vmcs_write16(GUEST_INTR_STATUS, status);
8220 static void vmx_set_rvi(int vector)
8228 status = vmcs_read16(GUEST_INTR_STATUS);
8229 old = (u8)status & 0xff;
8230 if ((u8)vector != old) {
8232 status |= (u8)vector;
8233 vmcs_write16(GUEST_INTR_STATUS, status);
8237 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8239 if (!is_guest_mode(vcpu)) {
8240 vmx_set_rvi(max_irr);
8248 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8251 if (nested_exit_on_intr(vcpu))
8255 * Else, fall back to pre-APICv interrupt injection since L2
8256 * is run without virtual interrupt delivery.
8258 if (!kvm_event_needs_reinjection(vcpu) &&
8259 vmx_interrupt_allowed(vcpu)) {
8260 kvm_queue_interrupt(vcpu, max_irr, false);
8261 vmx_inject_irq(vcpu);
8265 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8267 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8268 if (!vmx_cpu_uses_apicv(vcpu))
8271 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8272 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8273 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8274 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8277 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8281 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8282 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8285 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8286 exit_intr_info = vmx->exit_intr_info;
8288 /* Handle machine checks before interrupts are enabled */
8289 if (is_machine_check(exit_intr_info))
8290 kvm_machine_check();
8292 /* We need to handle NMIs before interrupts are enabled */
8293 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8294 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8295 kvm_before_handle_nmi(&vmx->vcpu);
8297 kvm_after_handle_nmi(&vmx->vcpu);
8301 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8303 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8306 * If external interrupt exists, IF bit is set in rflags/eflags on the
8307 * interrupt stack frame, and interrupt will be enabled on a return
8308 * from interrupt handler.
8310 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8311 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8312 unsigned int vector;
8313 unsigned long entry;
8315 struct vcpu_vmx *vmx = to_vmx(vcpu);
8316 #ifdef CONFIG_X86_64
8320 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8321 desc = (gate_desc *)vmx->host_idt_base + vector;
8322 entry = gate_offset(*desc);
8324 #ifdef CONFIG_X86_64
8325 "mov %%" _ASM_SP ", %[sp]\n\t"
8326 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8331 "orl $0x200, (%%" _ASM_SP ")\n\t"
8332 __ASM_SIZE(push) " $%c[cs]\n\t"
8333 "call *%[entry]\n\t"
8335 #ifdef CONFIG_X86_64
8340 [ss]"i"(__KERNEL_DS),
8341 [cs]"i"(__KERNEL_CS)
8347 static bool vmx_has_high_real_mode_segbase(void)
8349 return enable_unrestricted_guest || emulate_invalid_guest_state;
8352 static bool vmx_mpx_supported(void)
8354 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8355 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8358 static bool vmx_xsaves_supported(void)
8360 return vmcs_config.cpu_based_2nd_exec_ctrl &
8361 SECONDARY_EXEC_XSAVES;
8364 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8369 bool idtv_info_valid;
8371 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8373 if (cpu_has_virtual_nmis()) {
8374 if (vmx->nmi_known_unmasked)
8377 * Can't use vmx->exit_intr_info since we're not sure what
8378 * the exit reason is.
8380 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8381 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8382 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8384 * SDM 3: 27.7.1.2 (September 2008)
8385 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8386 * a guest IRET fault.
8387 * SDM 3: 23.2.2 (September 2008)
8388 * Bit 12 is undefined in any of the following cases:
8389 * If the VM exit sets the valid bit in the IDT-vectoring
8390 * information field.
8391 * If the VM exit is due to a double fault.
8393 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8394 vector != DF_VECTOR && !idtv_info_valid)
8395 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8396 GUEST_INTR_STATE_NMI);
8398 vmx->nmi_known_unmasked =
8399 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8400 & GUEST_INTR_STATE_NMI);
8401 } else if (unlikely(vmx->soft_vnmi_blocked))
8402 vmx->vnmi_blocked_time +=
8403 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8406 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8407 u32 idt_vectoring_info,
8408 int instr_len_field,
8409 int error_code_field)
8413 bool idtv_info_valid;
8415 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8417 vcpu->arch.nmi_injected = false;
8418 kvm_clear_exception_queue(vcpu);
8419 kvm_clear_interrupt_queue(vcpu);
8421 if (!idtv_info_valid)
8424 kvm_make_request(KVM_REQ_EVENT, vcpu);
8426 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8427 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8430 case INTR_TYPE_NMI_INTR:
8431 vcpu->arch.nmi_injected = true;
8433 * SDM 3: 27.7.1.2 (September 2008)
8434 * Clear bit "block by NMI" before VM entry if a NMI
8437 vmx_set_nmi_mask(vcpu, false);
8439 case INTR_TYPE_SOFT_EXCEPTION:
8440 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8442 case INTR_TYPE_HARD_EXCEPTION:
8443 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8444 u32 err = vmcs_read32(error_code_field);
8445 kvm_requeue_exception_e(vcpu, vector, err);
8447 kvm_requeue_exception(vcpu, vector);
8449 case INTR_TYPE_SOFT_INTR:
8450 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8452 case INTR_TYPE_EXT_INTR:
8453 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8460 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8462 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8463 VM_EXIT_INSTRUCTION_LEN,
8464 IDT_VECTORING_ERROR_CODE);
8467 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8469 __vmx_complete_interrupts(vcpu,
8470 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8471 VM_ENTRY_INSTRUCTION_LEN,
8472 VM_ENTRY_EXCEPTION_ERROR_CODE);
8474 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8477 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8480 struct perf_guest_switch_msr *msrs;
8482 msrs = perf_guest_get_msrs(&nr_msrs);
8487 for (i = 0; i < nr_msrs; i++)
8488 if (msrs[i].host == msrs[i].guest)
8489 clear_atomic_switch_msr(vmx, msrs[i].msr);
8491 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8495 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8497 struct vcpu_vmx *vmx = to_vmx(vcpu);
8498 unsigned long debugctlmsr, cr4;
8500 /* Record the guest's net vcpu time for enforced NMI injections. */
8501 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8502 vmx->entry_time = ktime_get();
8504 /* Don't enter VMX if guest state is invalid, let the exit handler
8505 start emulation until we arrive back to a valid state */
8506 if (vmx->emulation_required)
8509 if (vmx->ple_window_dirty) {
8510 vmx->ple_window_dirty = false;
8511 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8514 if (vmx->nested.sync_shadow_vmcs) {
8515 copy_vmcs12_to_shadow(vmx);
8516 vmx->nested.sync_shadow_vmcs = false;
8519 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8520 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8521 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8522 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8524 cr4 = cr4_read_shadow();
8525 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8526 vmcs_writel(HOST_CR4, cr4);
8527 vmx->host_state.vmcs_host_cr4 = cr4;
8530 /* When single-stepping over STI and MOV SS, we must clear the
8531 * corresponding interruptibility bits in the guest state. Otherwise
8532 * vmentry fails as it then expects bit 14 (BS) in pending debug
8533 * exceptions being set, but that's not correct for the guest debugging
8535 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8536 vmx_set_interrupt_shadow(vcpu, 0);
8538 atomic_switch_perf_msrs(vmx);
8539 debugctlmsr = get_debugctlmsr();
8541 vmx->__launched = vmx->loaded_vmcs->launched;
8543 /* Store host registers */
8544 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8545 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8546 "push %%" _ASM_CX " \n\t"
8547 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8549 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8550 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8552 /* Reload cr2 if changed */
8553 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8554 "mov %%cr2, %%" _ASM_DX " \n\t"
8555 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8557 "mov %%" _ASM_AX", %%cr2 \n\t"
8559 /* Check if vmlaunch of vmresume is needed */
8560 "cmpl $0, %c[launched](%0) \n\t"
8561 /* Load guest registers. Don't clobber flags. */
8562 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8563 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8564 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8565 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8566 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8567 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8568 #ifdef CONFIG_X86_64
8569 "mov %c[r8](%0), %%r8 \n\t"
8570 "mov %c[r9](%0), %%r9 \n\t"
8571 "mov %c[r10](%0), %%r10 \n\t"
8572 "mov %c[r11](%0), %%r11 \n\t"
8573 "mov %c[r12](%0), %%r12 \n\t"
8574 "mov %c[r13](%0), %%r13 \n\t"
8575 "mov %c[r14](%0), %%r14 \n\t"
8576 "mov %c[r15](%0), %%r15 \n\t"
8578 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8580 /* Enter guest mode */
8582 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8584 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8586 /* Save guest registers, load host registers, keep flags */
8587 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8589 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8590 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8591 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8592 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8593 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8594 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8595 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8596 #ifdef CONFIG_X86_64
8597 "mov %%r8, %c[r8](%0) \n\t"
8598 "mov %%r9, %c[r9](%0) \n\t"
8599 "mov %%r10, %c[r10](%0) \n\t"
8600 "mov %%r11, %c[r11](%0) \n\t"
8601 "mov %%r12, %c[r12](%0) \n\t"
8602 "mov %%r13, %c[r13](%0) \n\t"
8603 "mov %%r14, %c[r14](%0) \n\t"
8604 "mov %%r15, %c[r15](%0) \n\t"
8606 "mov %%cr2, %%" _ASM_AX " \n\t"
8607 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8609 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8610 "setbe %c[fail](%0) \n\t"
8611 ".pushsection .rodata \n\t"
8612 ".global vmx_return \n\t"
8613 "vmx_return: " _ASM_PTR " 2b \n\t"
8615 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8616 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8617 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8618 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8619 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8620 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8621 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8622 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8623 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8624 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8625 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8626 #ifdef CONFIG_X86_64
8627 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8628 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8629 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8630 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8631 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8632 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8633 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8634 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8636 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8637 [wordsize]"i"(sizeof(ulong))
8639 #ifdef CONFIG_X86_64
8640 , "rax", "rbx", "rdi", "rsi"
8641 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8643 , "eax", "ebx", "edi", "esi"
8647 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8649 update_debugctlmsr(debugctlmsr);
8651 #ifndef CONFIG_X86_64
8653 * The sysexit path does not restore ds/es, so we must set them to
8654 * a reasonable value ourselves.
8656 * We can't defer this to vmx_load_host_state() since that function
8657 * may be executed in interrupt context, which saves and restore segments
8658 * around it, nullifying its effect.
8660 loadsegment(ds, __USER_DS);
8661 loadsegment(es, __USER_DS);
8664 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8665 | (1 << VCPU_EXREG_RFLAGS)
8666 | (1 << VCPU_EXREG_PDPTR)
8667 | (1 << VCPU_EXREG_SEGMENTS)
8668 | (1 << VCPU_EXREG_CR3));
8669 vcpu->arch.regs_dirty = 0;
8671 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8673 vmx->loaded_vmcs->launched = 1;
8675 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8676 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8679 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8680 * we did not inject a still-pending event to L1 now because of
8681 * nested_run_pending, we need to re-enable this bit.
8683 if (vmx->nested.nested_run_pending)
8684 kvm_make_request(KVM_REQ_EVENT, vcpu);
8686 vmx->nested.nested_run_pending = 0;
8688 vmx_complete_atomic_exit(vmx);
8689 vmx_recover_nmi_blocking(vmx);
8690 vmx_complete_interrupts(vmx);
8693 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8695 struct vcpu_vmx *vmx = to_vmx(vcpu);
8698 if (vmx->loaded_vmcs == &vmx->vmcs01)
8702 vmx->loaded_vmcs = &vmx->vmcs01;
8704 vmx_vcpu_load(vcpu, cpu);
8709 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8711 struct vcpu_vmx *vmx = to_vmx(vcpu);
8714 vmx_destroy_pml_buffer(vmx);
8715 free_vpid(vmx->vpid);
8716 leave_guest_mode(vcpu);
8717 vmx_load_vmcs01(vcpu);
8719 free_loaded_vmcs(vmx->loaded_vmcs);
8720 kfree(vmx->guest_msrs);
8721 kvm_vcpu_uninit(vcpu);
8722 kmem_cache_free(kvm_vcpu_cache, vmx);
8725 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8728 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8732 return ERR_PTR(-ENOMEM);
8734 vmx->vpid = allocate_vpid();
8736 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8740 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8741 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8745 if (!vmx->guest_msrs) {
8749 vmx->loaded_vmcs = &vmx->vmcs01;
8750 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8751 if (!vmx->loaded_vmcs->vmcs)
8754 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8755 loaded_vmcs_init(vmx->loaded_vmcs);
8760 vmx_vcpu_load(&vmx->vcpu, cpu);
8761 vmx->vcpu.cpu = cpu;
8762 err = vmx_vcpu_setup(vmx);
8763 vmx_vcpu_put(&vmx->vcpu);
8767 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8768 err = alloc_apic_access_page(kvm);
8774 if (!kvm->arch.ept_identity_map_addr)
8775 kvm->arch.ept_identity_map_addr =
8776 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8777 err = init_rmode_identity_map(kvm);
8783 nested_vmx_setup_ctls_msrs(vmx);
8784 vmx->nested.vpid02 = allocate_vpid();
8787 vmx->nested.posted_intr_nv = -1;
8788 vmx->nested.current_vmptr = -1ull;
8789 vmx->nested.current_vmcs12 = NULL;
8792 * If PML is turned on, failure on enabling PML just results in failure
8793 * of creating the vcpu, therefore we can simplify PML logic (by
8794 * avoiding dealing with cases, such as enabling PML partially on vcpus
8795 * for the guest, etc.
8798 err = vmx_create_pml_buffer(vmx);
8806 free_vpid(vmx->nested.vpid02);
8807 free_loaded_vmcs(vmx->loaded_vmcs);
8809 kfree(vmx->guest_msrs);
8811 kvm_vcpu_uninit(&vmx->vcpu);
8813 free_vpid(vmx->vpid);
8814 kmem_cache_free(kvm_vcpu_cache, vmx);
8815 return ERR_PTR(err);
8818 static void __init vmx_check_processor_compat(void *rtn)
8820 struct vmcs_config vmcs_conf;
8823 if (setup_vmcs_config(&vmcs_conf) < 0)
8825 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8826 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8827 smp_processor_id());
8832 static int get_ept_level(void)
8834 return VMX_EPT_DEFAULT_GAW + 1;
8837 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8842 /* For VT-d and EPT combination
8843 * 1. MMIO: always map as UC
8845 * a. VT-d without snooping control feature: can't guarantee the
8846 * result, try to trust guest.
8847 * b. VT-d with snooping control feature: snooping control feature of
8848 * VT-d engine can guarantee the cache correctness. Just set it
8849 * to WB to keep consistent with host. So the same as item 3.
8850 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8851 * consistent with host MTRR
8854 cache = MTRR_TYPE_UNCACHABLE;
8858 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8859 ipat = VMX_EPT_IPAT_BIT;
8860 cache = MTRR_TYPE_WRBACK;
8864 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8865 ipat = VMX_EPT_IPAT_BIT;
8866 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8867 cache = MTRR_TYPE_WRBACK;
8869 cache = MTRR_TYPE_UNCACHABLE;
8873 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8876 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8879 static int vmx_get_lpage_level(void)
8881 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8882 return PT_DIRECTORY_LEVEL;
8884 /* For shadow and EPT supported 1GB page */
8885 return PT_PDPE_LEVEL;
8888 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8891 * These bits in the secondary execution controls field
8892 * are dynamic, the others are mostly based on the hypervisor
8893 * architecture and the guest's CPUID. Do not touch the
8897 SECONDARY_EXEC_SHADOW_VMCS |
8898 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8899 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8901 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8903 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8904 (new_ctl & ~mask) | (cur_ctl & mask));
8907 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8909 struct kvm_cpuid_entry2 *best;
8910 struct vcpu_vmx *vmx = to_vmx(vcpu);
8911 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8913 if (vmx_rdtscp_supported()) {
8914 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8915 if (!rdtscp_enabled)
8916 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8920 vmx->nested.nested_vmx_secondary_ctls_high |=
8921 SECONDARY_EXEC_RDTSCP;
8923 vmx->nested.nested_vmx_secondary_ctls_high &=
8924 ~SECONDARY_EXEC_RDTSCP;
8928 /* Exposing INVPCID only when PCID is exposed */
8929 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8930 if (vmx_invpcid_supported() &&
8931 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8932 !guest_cpuid_has_pcid(vcpu))) {
8933 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8936 best->ebx &= ~bit(X86_FEATURE_INVPCID);
8939 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8941 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8942 if (guest_cpuid_has_pcommit(vcpu))
8943 vmx->nested.nested_vmx_secondary_ctls_high |=
8944 SECONDARY_EXEC_PCOMMIT;
8946 vmx->nested.nested_vmx_secondary_ctls_high &=
8947 ~SECONDARY_EXEC_PCOMMIT;
8951 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8953 if (func == 1 && nested)
8954 entry->ecx |= bit(X86_FEATURE_VMX);
8957 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8958 struct x86_exception *fault)
8960 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8963 if (fault->error_code & PFERR_RSVD_MASK)
8964 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8966 exit_reason = EXIT_REASON_EPT_VIOLATION;
8967 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8968 vmcs12->guest_physical_address = fault->address;
8971 /* Callbacks for nested_ept_init_mmu_context: */
8973 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8975 /* return the page table to be shadowed - in our case, EPT12 */
8976 return get_vmcs12(vcpu)->ept_pointer;
8979 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8981 WARN_ON(mmu_is_nested(vcpu));
8982 kvm_init_shadow_ept_mmu(vcpu,
8983 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8984 VMX_EPT_EXECUTE_ONLY_BIT);
8985 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8986 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8987 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8989 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
8992 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8994 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8997 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9000 bool inequality, bit;
9002 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9004 (error_code & vmcs12->page_fault_error_code_mask) !=
9005 vmcs12->page_fault_error_code_match;
9006 return inequality ^ bit;
9009 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9010 struct x86_exception *fault)
9012 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9014 WARN_ON(!is_guest_mode(vcpu));
9016 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9017 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9018 vmcs_read32(VM_EXIT_INTR_INFO),
9019 vmcs_readl(EXIT_QUALIFICATION));
9021 kvm_inject_page_fault(vcpu, fault);
9024 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9025 struct vmcs12 *vmcs12)
9027 struct vcpu_vmx *vmx = to_vmx(vcpu);
9028 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9030 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9031 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9032 vmcs12->apic_access_addr >> maxphyaddr)
9036 * Translate L1 physical address to host physical
9037 * address for vmcs02. Keep the page pinned, so this
9038 * physical address remains valid. We keep a reference
9039 * to it so we can release it later.
9041 if (vmx->nested.apic_access_page) /* shouldn't happen */
9042 nested_release_page(vmx->nested.apic_access_page);
9043 vmx->nested.apic_access_page =
9044 nested_get_page(vcpu, vmcs12->apic_access_addr);
9047 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9048 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9049 vmcs12->virtual_apic_page_addr >> maxphyaddr)
9052 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9053 nested_release_page(vmx->nested.virtual_apic_page);
9054 vmx->nested.virtual_apic_page =
9055 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9058 * Failing the vm entry is _not_ what the processor does
9059 * but it's basically the only possibility we have.
9060 * We could still enter the guest if CR8 load exits are
9061 * enabled, CR8 store exits are enabled, and virtualize APIC
9062 * access is disabled; in this case the processor would never
9063 * use the TPR shadow and we could simply clear the bit from
9064 * the execution control. But such a configuration is useless,
9065 * so let's keep the code simple.
9067 if (!vmx->nested.virtual_apic_page)
9071 if (nested_cpu_has_posted_intr(vmcs12)) {
9072 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9073 vmcs12->posted_intr_desc_addr >> maxphyaddr)
9076 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9077 kunmap(vmx->nested.pi_desc_page);
9078 nested_release_page(vmx->nested.pi_desc_page);
9080 vmx->nested.pi_desc_page =
9081 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9082 if (!vmx->nested.pi_desc_page)
9085 vmx->nested.pi_desc =
9086 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9087 if (!vmx->nested.pi_desc) {
9088 nested_release_page_clean(vmx->nested.pi_desc_page);
9091 vmx->nested.pi_desc =
9092 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9093 (unsigned long)(vmcs12->posted_intr_desc_addr &
9100 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9102 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9103 struct vcpu_vmx *vmx = to_vmx(vcpu);
9105 if (vcpu->arch.virtual_tsc_khz == 0)
9108 /* Make sure short timeouts reliably trigger an immediate vmexit.
9109 * hrtimer_start does not guarantee this. */
9110 if (preemption_timeout <= 1) {
9111 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9115 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9116 preemption_timeout *= 1000000;
9117 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9118 hrtimer_start(&vmx->nested.preemption_timer,
9119 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9122 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9123 struct vmcs12 *vmcs12)
9128 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9131 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9135 maxphyaddr = cpuid_maxphyaddr(vcpu);
9137 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9138 ((addr + PAGE_SIZE) >> maxphyaddr))
9145 * Merge L0's and L1's MSR bitmap, return false to indicate that
9146 * we do not use the hardware.
9148 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9149 struct vmcs12 *vmcs12)
9153 unsigned long *msr_bitmap;
9155 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9158 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9163 msr_bitmap = (unsigned long *)kmap(page);
9165 nested_release_page_clean(page);
9170 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9171 if (nested_cpu_has_apic_reg_virt(vmcs12))
9172 for (msr = 0x800; msr <= 0x8ff; msr++)
9173 nested_vmx_disable_intercept_for_msr(
9175 vmx_msr_bitmap_nested,
9177 /* TPR is allowed */
9178 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9179 vmx_msr_bitmap_nested,
9180 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9181 MSR_TYPE_R | MSR_TYPE_W);
9182 if (nested_cpu_has_vid(vmcs12)) {
9183 /* EOI and self-IPI are allowed */
9184 nested_vmx_disable_intercept_for_msr(
9186 vmx_msr_bitmap_nested,
9187 APIC_BASE_MSR + (APIC_EOI >> 4),
9189 nested_vmx_disable_intercept_for_msr(
9191 vmx_msr_bitmap_nested,
9192 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9197 * Enable reading intercept of all the x2apic
9198 * MSRs. We should not rely on vmcs12 to do any
9199 * optimizations here, it may have been modified
9202 for (msr = 0x800; msr <= 0x8ff; msr++)
9203 __vmx_enable_intercept_for_msr(
9204 vmx_msr_bitmap_nested,
9208 __vmx_enable_intercept_for_msr(
9209 vmx_msr_bitmap_nested,
9210 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9212 __vmx_enable_intercept_for_msr(
9213 vmx_msr_bitmap_nested,
9214 APIC_BASE_MSR + (APIC_EOI >> 4),
9216 __vmx_enable_intercept_for_msr(
9217 vmx_msr_bitmap_nested,
9218 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9222 nested_release_page_clean(page);
9227 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9228 struct vmcs12 *vmcs12)
9230 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9231 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9232 !nested_cpu_has_vid(vmcs12) &&
9233 !nested_cpu_has_posted_intr(vmcs12))
9237 * If virtualize x2apic mode is enabled,
9238 * virtualize apic access must be disabled.
9240 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9241 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9245 * If virtual interrupt delivery is enabled,
9246 * we must exit on external interrupts.
9248 if (nested_cpu_has_vid(vmcs12) &&
9249 !nested_exit_on_intr(vcpu))
9253 * bits 15:8 should be zero in posted_intr_nv,
9254 * the descriptor address has been already checked
9255 * in nested_get_vmcs12_pages.
9257 if (nested_cpu_has_posted_intr(vmcs12) &&
9258 (!nested_cpu_has_vid(vmcs12) ||
9259 !nested_exit_intr_ack_set(vcpu) ||
9260 vmcs12->posted_intr_nv & 0xff00))
9263 /* tpr shadow is needed by all apicv features. */
9264 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9270 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9271 unsigned long count_field,
9272 unsigned long addr_field)
9277 if (vmcs12_read_any(vcpu, count_field, &count) ||
9278 vmcs12_read_any(vcpu, addr_field, &addr)) {
9284 maxphyaddr = cpuid_maxphyaddr(vcpu);
9285 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9286 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9287 pr_warn_ratelimited(
9288 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9289 addr_field, maxphyaddr, count, addr);
9295 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9296 struct vmcs12 *vmcs12)
9298 if (vmcs12->vm_exit_msr_load_count == 0 &&
9299 vmcs12->vm_exit_msr_store_count == 0 &&
9300 vmcs12->vm_entry_msr_load_count == 0)
9301 return 0; /* Fast path */
9302 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9303 VM_EXIT_MSR_LOAD_ADDR) ||
9304 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9305 VM_EXIT_MSR_STORE_ADDR) ||
9306 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9307 VM_ENTRY_MSR_LOAD_ADDR))
9312 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9313 struct vmx_msr_entry *e)
9315 /* x2APIC MSR accesses are not allowed */
9316 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9318 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9319 e->index == MSR_IA32_UCODE_REV)
9321 if (e->reserved != 0)
9326 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9327 struct vmx_msr_entry *e)
9329 if (e->index == MSR_FS_BASE ||
9330 e->index == MSR_GS_BASE ||
9331 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9332 nested_vmx_msr_check_common(vcpu, e))
9337 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9338 struct vmx_msr_entry *e)
9340 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9341 nested_vmx_msr_check_common(vcpu, e))
9347 * Load guest's/host's msr at nested entry/exit.
9348 * return 0 for success, entry index for failure.
9350 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9353 struct vmx_msr_entry e;
9354 struct msr_data msr;
9356 msr.host_initiated = false;
9357 for (i = 0; i < count; i++) {
9358 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9360 pr_warn_ratelimited(
9361 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9362 __func__, i, gpa + i * sizeof(e));
9365 if (nested_vmx_load_msr_check(vcpu, &e)) {
9366 pr_warn_ratelimited(
9367 "%s check failed (%u, 0x%x, 0x%x)\n",
9368 __func__, i, e.index, e.reserved);
9371 msr.index = e.index;
9373 if (kvm_set_msr(vcpu, &msr)) {
9374 pr_warn_ratelimited(
9375 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9376 __func__, i, e.index, e.value);
9385 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9388 struct vmx_msr_entry e;
9390 for (i = 0; i < count; i++) {
9391 struct msr_data msr_info;
9392 if (kvm_vcpu_read_guest(vcpu,
9393 gpa + i * sizeof(e),
9394 &e, 2 * sizeof(u32))) {
9395 pr_warn_ratelimited(
9396 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9397 __func__, i, gpa + i * sizeof(e));
9400 if (nested_vmx_store_msr_check(vcpu, &e)) {
9401 pr_warn_ratelimited(
9402 "%s check failed (%u, 0x%x, 0x%x)\n",
9403 __func__, i, e.index, e.reserved);
9406 msr_info.host_initiated = false;
9407 msr_info.index = e.index;
9408 if (kvm_get_msr(vcpu, &msr_info)) {
9409 pr_warn_ratelimited(
9410 "%s cannot read MSR (%u, 0x%x)\n",
9411 __func__, i, e.index);
9414 if (kvm_vcpu_write_guest(vcpu,
9415 gpa + i * sizeof(e) +
9416 offsetof(struct vmx_msr_entry, value),
9417 &msr_info.data, sizeof(msr_info.data))) {
9418 pr_warn_ratelimited(
9419 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9420 __func__, i, e.index, msr_info.data);
9428 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9429 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9430 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9431 * guest in a way that will both be appropriate to L1's requests, and our
9432 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9433 * function also has additional necessary side-effects, like setting various
9434 * vcpu->arch fields.
9436 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9438 struct vcpu_vmx *vmx = to_vmx(vcpu);
9441 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9442 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9443 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9444 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9445 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9446 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9447 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9448 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9449 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9450 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9451 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9452 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9453 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9454 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9455 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9456 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9457 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9458 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9459 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9460 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9461 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9462 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9463 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9464 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9465 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9466 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9467 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9468 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9469 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9470 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9471 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9472 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9473 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9474 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9475 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9476 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9478 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9479 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9480 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9482 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9483 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9485 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9486 vmcs12->vm_entry_intr_info_field);
9487 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9488 vmcs12->vm_entry_exception_error_code);
9489 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9490 vmcs12->vm_entry_instruction_len);
9491 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9492 vmcs12->guest_interruptibility_info);
9493 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9494 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9495 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9496 vmcs12->guest_pending_dbg_exceptions);
9497 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9498 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9500 if (nested_cpu_has_xsaves(vmcs12))
9501 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9502 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9504 exec_control = vmcs12->pin_based_vm_exec_control;
9505 exec_control |= vmcs_config.pin_based_exec_ctrl;
9506 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9508 if (nested_cpu_has_posted_intr(vmcs12)) {
9510 * Note that we use L0's vector here and in
9511 * vmx_deliver_nested_posted_interrupt.
9513 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9514 vmx->nested.pi_pending = false;
9515 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9516 vmcs_write64(POSTED_INTR_DESC_ADDR,
9517 page_to_phys(vmx->nested.pi_desc_page) +
9518 (unsigned long)(vmcs12->posted_intr_desc_addr &
9521 exec_control &= ~PIN_BASED_POSTED_INTR;
9523 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9525 vmx->nested.preemption_timer_expired = false;
9526 if (nested_cpu_has_preemption_timer(vmcs12))
9527 vmx_start_preemption_timer(vcpu);
9530 * Whether page-faults are trapped is determined by a combination of
9531 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9532 * If enable_ept, L0 doesn't care about page faults and we should
9533 * set all of these to L1's desires. However, if !enable_ept, L0 does
9534 * care about (at least some) page faults, and because it is not easy
9535 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9536 * to exit on each and every L2 page fault. This is done by setting
9537 * MASK=MATCH=0 and (see below) EB.PF=1.
9538 * Note that below we don't need special code to set EB.PF beyond the
9539 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9540 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9541 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9543 * A problem with this approach (when !enable_ept) is that L1 may be
9544 * injected with more page faults than it asked for. This could have
9545 * caused problems, but in practice existing hypervisors don't care.
9546 * To fix this, we will need to emulate the PFEC checking (on the L1
9547 * page tables), using walk_addr(), when injecting PFs to L1.
9549 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9550 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9551 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9552 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9554 if (cpu_has_secondary_exec_ctrls()) {
9555 exec_control = vmx_secondary_exec_control(vmx);
9557 /* Take the following fields only from vmcs12 */
9558 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9559 SECONDARY_EXEC_RDTSCP |
9560 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9561 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9562 SECONDARY_EXEC_PCOMMIT);
9563 if (nested_cpu_has(vmcs12,
9564 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9565 exec_control |= vmcs12->secondary_vm_exec_control;
9567 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9569 * If translation failed, no matter: This feature asks
9570 * to exit when accessing the given address, and if it
9571 * can never be accessed, this feature won't do
9574 if (!vmx->nested.apic_access_page)
9576 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9578 vmcs_write64(APIC_ACCESS_ADDR,
9579 page_to_phys(vmx->nested.apic_access_page));
9580 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9581 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9583 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9584 kvm_vcpu_reload_apic_access_page(vcpu);
9587 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9588 vmcs_write64(EOI_EXIT_BITMAP0,
9589 vmcs12->eoi_exit_bitmap0);
9590 vmcs_write64(EOI_EXIT_BITMAP1,
9591 vmcs12->eoi_exit_bitmap1);
9592 vmcs_write64(EOI_EXIT_BITMAP2,
9593 vmcs12->eoi_exit_bitmap2);
9594 vmcs_write64(EOI_EXIT_BITMAP3,
9595 vmcs12->eoi_exit_bitmap3);
9596 vmcs_write16(GUEST_INTR_STATUS,
9597 vmcs12->guest_intr_status);
9600 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9605 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9606 * Some constant fields are set here by vmx_set_constant_host_state().
9607 * Other fields are different per CPU, and will be set later when
9608 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9610 vmx_set_constant_host_state(vmx);
9613 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9614 * entry, but only if the current (host) sp changed from the value
9615 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9616 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9617 * here we just force the write to happen on entry.
9621 exec_control = vmx_exec_control(vmx); /* L0's desires */
9622 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9623 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9624 exec_control &= ~CPU_BASED_TPR_SHADOW;
9625 exec_control |= vmcs12->cpu_based_vm_exec_control;
9627 if (exec_control & CPU_BASED_TPR_SHADOW) {
9628 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9629 page_to_phys(vmx->nested.virtual_apic_page));
9630 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9633 if (cpu_has_vmx_msr_bitmap() &&
9634 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9635 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9636 /* MSR_BITMAP will be set by following vmx_set_efer. */
9638 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9641 * Merging of IO bitmap not currently supported.
9642 * Rather, exit every time.
9644 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9645 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9647 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9649 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9650 * bitwise-or of what L1 wants to trap for L2, and what we want to
9651 * trap. Note that CR0.TS also needs updating - we do this later.
9653 update_exception_bitmap(vcpu);
9654 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9655 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9657 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9658 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9659 * bits are further modified by vmx_set_efer() below.
9661 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9663 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9664 * emulated by vmx_set_efer(), below.
9666 vm_entry_controls_init(vmx,
9667 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9668 ~VM_ENTRY_IA32E_MODE) |
9669 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9671 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9672 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9673 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9674 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9675 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9678 set_cr4_guest_host_mask(vmx);
9680 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9681 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9683 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9684 vmcs_write64(TSC_OFFSET,
9685 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9687 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9691 * There is no direct mapping between vpid02 and vpid12, the
9692 * vpid02 is per-vCPU for L0 and reused while the value of
9693 * vpid12 is changed w/ one invvpid during nested vmentry.
9694 * The vpid12 is allocated by L1 for L2, so it will not
9695 * influence global bitmap(for vpid01 and vpid02 allocation)
9696 * even if spawn a lot of nested vCPUs.
9698 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9699 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9700 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9701 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9702 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9705 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9706 vmx_flush_tlb(vcpu);
9711 if (nested_cpu_has_ept(vmcs12)) {
9712 kvm_mmu_unload(vcpu);
9713 nested_ept_init_mmu_context(vcpu);
9716 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9717 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9718 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9719 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9721 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9722 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9723 vmx_set_efer(vcpu, vcpu->arch.efer);
9726 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9727 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9728 * The CR0_READ_SHADOW is what L2 should have expected to read given
9729 * the specifications by L1; It's not enough to take
9730 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9731 * have more bits than L1 expected.
9733 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9734 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9736 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9737 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9739 /* shadow page tables on either EPT or shadow page tables */
9740 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9741 kvm_mmu_reset_context(vcpu);
9744 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9747 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9750 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9751 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9752 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9753 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9756 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9757 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9761 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9762 * for running an L2 nested guest.
9764 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9766 struct vmcs12 *vmcs12;
9767 struct vcpu_vmx *vmx = to_vmx(vcpu);
9769 struct loaded_vmcs *vmcs02;
9773 if (!nested_vmx_check_permission(vcpu) ||
9774 !nested_vmx_check_vmcs12(vcpu))
9777 skip_emulated_instruction(vcpu);
9778 vmcs12 = get_vmcs12(vcpu);
9780 if (enable_shadow_vmcs)
9781 copy_shadow_to_vmcs12(vmx);
9784 * The nested entry process starts with enforcing various prerequisites
9785 * on vmcs12 as required by the Intel SDM, and act appropriately when
9786 * they fail: As the SDM explains, some conditions should cause the
9787 * instruction to fail, while others will cause the instruction to seem
9788 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9789 * To speed up the normal (success) code path, we should avoid checking
9790 * for misconfigurations which will anyway be caught by the processor
9791 * when using the merged vmcs02.
9793 if (vmcs12->launch_state == launch) {
9794 nested_vmx_failValid(vcpu,
9795 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9796 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9800 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9801 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9802 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9806 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9807 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9811 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9812 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9816 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9817 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9821 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9822 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9826 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9827 vmx->nested.nested_vmx_true_procbased_ctls_low,
9828 vmx->nested.nested_vmx_procbased_ctls_high) ||
9829 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9830 vmx->nested.nested_vmx_secondary_ctls_low,
9831 vmx->nested.nested_vmx_secondary_ctls_high) ||
9832 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9833 vmx->nested.nested_vmx_pinbased_ctls_low,
9834 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9835 !vmx_control_verify(vmcs12->vm_exit_controls,
9836 vmx->nested.nested_vmx_true_exit_ctls_low,
9837 vmx->nested.nested_vmx_exit_ctls_high) ||
9838 !vmx_control_verify(vmcs12->vm_entry_controls,
9839 vmx->nested.nested_vmx_true_entry_ctls_low,
9840 vmx->nested.nested_vmx_entry_ctls_high))
9842 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9846 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9847 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9848 nested_vmx_failValid(vcpu,
9849 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9853 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9854 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9855 nested_vmx_entry_failure(vcpu, vmcs12,
9856 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9859 if (vmcs12->vmcs_link_pointer != -1ull) {
9860 nested_vmx_entry_failure(vcpu, vmcs12,
9861 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9866 * If the load IA32_EFER VM-entry control is 1, the following checks
9867 * are performed on the field for the IA32_EFER MSR:
9868 * - Bits reserved in the IA32_EFER MSR must be 0.
9869 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9870 * the IA-32e mode guest VM-exit control. It must also be identical
9871 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9874 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9875 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9876 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9877 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9878 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9879 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9880 nested_vmx_entry_failure(vcpu, vmcs12,
9881 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9887 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9888 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9889 * the values of the LMA and LME bits in the field must each be that of
9890 * the host address-space size VM-exit control.
9892 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9893 ia32e = (vmcs12->vm_exit_controls &
9894 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9895 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9896 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9897 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9898 nested_vmx_entry_failure(vcpu, vmcs12,
9899 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9905 * We're finally done with prerequisite checking, and can start with
9909 vmcs02 = nested_get_current_vmcs02(vmx);
9913 enter_guest_mode(vcpu);
9915 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9917 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9918 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9921 vmx->loaded_vmcs = vmcs02;
9923 vmx_vcpu_load(vcpu, cpu);
9927 vmx_segment_cache_clear(vmx);
9929 prepare_vmcs02(vcpu, vmcs12);
9931 msr_entry_idx = nested_vmx_load_msr(vcpu,
9932 vmcs12->vm_entry_msr_load_addr,
9933 vmcs12->vm_entry_msr_load_count);
9934 if (msr_entry_idx) {
9935 leave_guest_mode(vcpu);
9936 vmx_load_vmcs01(vcpu);
9937 nested_vmx_entry_failure(vcpu, vmcs12,
9938 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9942 vmcs12->launch_state = 1;
9944 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9945 return kvm_vcpu_halt(vcpu);
9947 vmx->nested.nested_run_pending = 1;
9950 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9951 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9952 * returned as far as L1 is concerned. It will only return (and set
9953 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9959 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9960 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9961 * This function returns the new value we should put in vmcs12.guest_cr0.
9962 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9963 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9964 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9965 * didn't trap the bit, because if L1 did, so would L0).
9966 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9967 * been modified by L2, and L1 knows it. So just leave the old value of
9968 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9969 * isn't relevant, because if L0 traps this bit it can set it to anything.
9970 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9971 * changed these bits, and therefore they need to be updated, but L0
9972 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9973 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9975 static inline unsigned long
9976 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9979 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9980 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9981 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9982 vcpu->arch.cr0_guest_owned_bits));
9985 static inline unsigned long
9986 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9989 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9990 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9991 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9992 vcpu->arch.cr4_guest_owned_bits));
9995 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9996 struct vmcs12 *vmcs12)
10001 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10002 nr = vcpu->arch.exception.nr;
10003 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10005 if (kvm_exception_is_soft(nr)) {
10006 vmcs12->vm_exit_instruction_len =
10007 vcpu->arch.event_exit_inst_len;
10008 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10010 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10012 if (vcpu->arch.exception.has_error_code) {
10013 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10014 vmcs12->idt_vectoring_error_code =
10015 vcpu->arch.exception.error_code;
10018 vmcs12->idt_vectoring_info_field = idt_vectoring;
10019 } else if (vcpu->arch.nmi_injected) {
10020 vmcs12->idt_vectoring_info_field =
10021 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10022 } else if (vcpu->arch.interrupt.pending) {
10023 nr = vcpu->arch.interrupt.nr;
10024 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10026 if (vcpu->arch.interrupt.soft) {
10027 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10028 vmcs12->vm_entry_instruction_len =
10029 vcpu->arch.event_exit_inst_len;
10031 idt_vectoring |= INTR_TYPE_EXT_INTR;
10033 vmcs12->idt_vectoring_info_field = idt_vectoring;
10037 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10039 struct vcpu_vmx *vmx = to_vmx(vcpu);
10041 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10042 vmx->nested.preemption_timer_expired) {
10043 if (vmx->nested.nested_run_pending)
10045 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10049 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10050 if (vmx->nested.nested_run_pending ||
10051 vcpu->arch.interrupt.pending)
10053 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10054 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10055 INTR_INFO_VALID_MASK, 0);
10057 * The NMI-triggered VM exit counts as injection:
10058 * clear this one and block further NMIs.
10060 vcpu->arch.nmi_pending = 0;
10061 vmx_set_nmi_mask(vcpu, true);
10065 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10066 nested_exit_on_intr(vcpu)) {
10067 if (vmx->nested.nested_run_pending)
10069 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10073 return vmx_complete_nested_posted_interrupt(vcpu);
10076 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10078 ktime_t remaining =
10079 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10082 if (ktime_to_ns(remaining) <= 0)
10085 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10086 do_div(value, 1000000);
10087 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10091 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10092 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10093 * and this function updates it to reflect the changes to the guest state while
10094 * L2 was running (and perhaps made some exits which were handled directly by L0
10095 * without going back to L1), and to reflect the exit reason.
10096 * Note that we do not have to copy here all VMCS fields, just those that
10097 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10098 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10099 * which already writes to vmcs12 directly.
10101 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10102 u32 exit_reason, u32 exit_intr_info,
10103 unsigned long exit_qualification)
10105 /* update guest state fields: */
10106 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10107 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10109 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10110 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10111 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10113 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10114 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10115 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10116 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10117 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10118 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10119 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10120 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10121 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10122 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10123 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10124 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10125 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10126 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10127 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10128 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10129 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10130 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10131 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10132 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10133 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10134 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10135 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10136 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10137 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10138 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10139 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10140 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10141 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10142 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10143 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10144 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10145 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10146 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10147 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10148 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10150 vmcs12->guest_interruptibility_info =
10151 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10152 vmcs12->guest_pending_dbg_exceptions =
10153 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10154 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10155 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10157 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10159 if (nested_cpu_has_preemption_timer(vmcs12)) {
10160 if (vmcs12->vm_exit_controls &
10161 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10162 vmcs12->vmx_preemption_timer_value =
10163 vmx_get_preemption_timer_value(vcpu);
10164 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10168 * In some cases (usually, nested EPT), L2 is allowed to change its
10169 * own CR3 without exiting. If it has changed it, we must keep it.
10170 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10171 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10173 * Additionally, restore L2's PDPTR to vmcs12.
10176 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10177 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10178 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10179 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10180 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10183 if (nested_cpu_has_vid(vmcs12))
10184 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10186 vmcs12->vm_entry_controls =
10187 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10188 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10190 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10191 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10192 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10195 /* TODO: These cannot have changed unless we have MSR bitmaps and
10196 * the relevant bit asks not to trap the change */
10197 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10198 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10199 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10200 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10201 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10202 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10203 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10204 if (vmx_mpx_supported())
10205 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10206 if (nested_cpu_has_xsaves(vmcs12))
10207 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10209 /* update exit information fields: */
10211 vmcs12->vm_exit_reason = exit_reason;
10212 vmcs12->exit_qualification = exit_qualification;
10214 vmcs12->vm_exit_intr_info = exit_intr_info;
10215 if ((vmcs12->vm_exit_intr_info &
10216 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10217 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10218 vmcs12->vm_exit_intr_error_code =
10219 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10220 vmcs12->idt_vectoring_info_field = 0;
10221 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10222 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10224 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10225 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10226 * instead of reading the real value. */
10227 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10230 * Transfer the event that L0 or L1 may wanted to inject into
10231 * L2 to IDT_VECTORING_INFO_FIELD.
10233 vmcs12_save_pending_event(vcpu, vmcs12);
10237 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10238 * preserved above and would only end up incorrectly in L1.
10240 vcpu->arch.nmi_injected = false;
10241 kvm_clear_exception_queue(vcpu);
10242 kvm_clear_interrupt_queue(vcpu);
10246 * A part of what we need to when the nested L2 guest exits and we want to
10247 * run its L1 parent, is to reset L1's guest state to the host state specified
10249 * This function is to be called not only on normal nested exit, but also on
10250 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10251 * Failures During or After Loading Guest State").
10252 * This function should be called when the active VMCS is L1's (vmcs01).
10254 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10255 struct vmcs12 *vmcs12)
10257 struct kvm_segment seg;
10259 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10260 vcpu->arch.efer = vmcs12->host_ia32_efer;
10261 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10262 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10264 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10265 vmx_set_efer(vcpu, vcpu->arch.efer);
10267 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10268 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10269 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10271 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10272 * actually changed, because it depends on the current state of
10273 * fpu_active (which may have changed).
10274 * Note that vmx_set_cr0 refers to efer set above.
10276 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10278 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10279 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10280 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10282 update_exception_bitmap(vcpu);
10283 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10284 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10287 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10288 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10290 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10291 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10293 nested_ept_uninit_mmu_context(vcpu);
10295 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10296 kvm_mmu_reset_context(vcpu);
10299 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10303 * Trivially support vpid by letting L2s share their parent
10304 * L1's vpid. TODO: move to a more elaborate solution, giving
10305 * each L2 its own vpid and exposing the vpid feature to L1.
10307 vmx_flush_tlb(vcpu);
10311 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10312 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10313 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10314 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10315 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10317 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10318 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10319 vmcs_write64(GUEST_BNDCFGS, 0);
10321 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10322 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10323 vcpu->arch.pat = vmcs12->host_ia32_pat;
10325 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10326 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10327 vmcs12->host_ia32_perf_global_ctrl);
10329 /* Set L1 segment info according to Intel SDM
10330 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10331 seg = (struct kvm_segment) {
10333 .limit = 0xFFFFFFFF,
10334 .selector = vmcs12->host_cs_selector,
10340 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10344 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10345 seg = (struct kvm_segment) {
10347 .limit = 0xFFFFFFFF,
10354 seg.selector = vmcs12->host_ds_selector;
10355 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10356 seg.selector = vmcs12->host_es_selector;
10357 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10358 seg.selector = vmcs12->host_ss_selector;
10359 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10360 seg.selector = vmcs12->host_fs_selector;
10361 seg.base = vmcs12->host_fs_base;
10362 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10363 seg.selector = vmcs12->host_gs_selector;
10364 seg.base = vmcs12->host_gs_base;
10365 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10366 seg = (struct kvm_segment) {
10367 .base = vmcs12->host_tr_base,
10369 .selector = vmcs12->host_tr_selector,
10373 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10375 kvm_set_dr(vcpu, 7, 0x400);
10376 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10378 if (cpu_has_vmx_msr_bitmap())
10379 vmx_set_msr_bitmap(vcpu);
10381 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10382 vmcs12->vm_exit_msr_load_count))
10383 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10387 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10388 * and modify vmcs12 to make it see what it would expect to see there if
10389 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10391 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10392 u32 exit_intr_info,
10393 unsigned long exit_qualification)
10395 struct vcpu_vmx *vmx = to_vmx(vcpu);
10396 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10398 /* trying to cancel vmlaunch/vmresume is a bug */
10399 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10401 leave_guest_mode(vcpu);
10402 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10403 exit_qualification);
10405 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10406 vmcs12->vm_exit_msr_store_count))
10407 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10409 vmx_load_vmcs01(vcpu);
10411 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10412 && nested_exit_intr_ack_set(vcpu)) {
10413 int irq = kvm_cpu_get_interrupt(vcpu);
10415 vmcs12->vm_exit_intr_info = irq |
10416 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10419 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10420 vmcs12->exit_qualification,
10421 vmcs12->idt_vectoring_info_field,
10422 vmcs12->vm_exit_intr_info,
10423 vmcs12->vm_exit_intr_error_code,
10426 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10427 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10428 vmx_segment_cache_clear(vmx);
10430 /* if no vmcs02 cache requested, remove the one we used */
10431 if (VMCS02_POOL_SIZE == 0)
10432 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10434 load_vmcs12_host_state(vcpu, vmcs12);
10436 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10437 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10439 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10442 /* Unpin physical memory we referred to in vmcs02 */
10443 if (vmx->nested.apic_access_page) {
10444 nested_release_page(vmx->nested.apic_access_page);
10445 vmx->nested.apic_access_page = NULL;
10447 if (vmx->nested.virtual_apic_page) {
10448 nested_release_page(vmx->nested.virtual_apic_page);
10449 vmx->nested.virtual_apic_page = NULL;
10451 if (vmx->nested.pi_desc_page) {
10452 kunmap(vmx->nested.pi_desc_page);
10453 nested_release_page(vmx->nested.pi_desc_page);
10454 vmx->nested.pi_desc_page = NULL;
10455 vmx->nested.pi_desc = NULL;
10459 * We are now running in L2, mmu_notifier will force to reload the
10460 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10462 kvm_vcpu_reload_apic_access_page(vcpu);
10465 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10466 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10467 * success or failure flag accordingly.
10469 if (unlikely(vmx->fail)) {
10471 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10473 nested_vmx_succeed(vcpu);
10474 if (enable_shadow_vmcs)
10475 vmx->nested.sync_shadow_vmcs = true;
10477 /* in case we halted in L2 */
10478 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10482 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10484 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10486 if (is_guest_mode(vcpu))
10487 nested_vmx_vmexit(vcpu, -1, 0, 0);
10488 free_nested(to_vmx(vcpu));
10492 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10493 * 23.7 "VM-entry failures during or after loading guest state" (this also
10494 * lists the acceptable exit-reason and exit-qualification parameters).
10495 * It should only be called before L2 actually succeeded to run, and when
10496 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10498 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10499 struct vmcs12 *vmcs12,
10500 u32 reason, unsigned long qualification)
10502 load_vmcs12_host_state(vcpu, vmcs12);
10503 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10504 vmcs12->exit_qualification = qualification;
10505 nested_vmx_succeed(vcpu);
10506 if (enable_shadow_vmcs)
10507 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10510 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10511 struct x86_instruction_info *info,
10512 enum x86_intercept_stage stage)
10514 return X86EMUL_CONTINUE;
10517 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10520 shrink_ple_window(vcpu);
10523 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10524 struct kvm_memory_slot *slot)
10526 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10527 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10530 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10531 struct kvm_memory_slot *slot)
10533 kvm_mmu_slot_set_dirty(kvm, slot);
10536 static void vmx_flush_log_dirty(struct kvm *kvm)
10538 kvm_flush_pml_buffers(kvm);
10541 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10542 struct kvm_memory_slot *memslot,
10543 gfn_t offset, unsigned long mask)
10545 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10549 * This routine does the following things for vCPU which is going
10550 * to be blocked if VT-d PI is enabled.
10551 * - Store the vCPU to the wakeup list, so when interrupts happen
10552 * we can find the right vCPU to wake up.
10553 * - Change the Posted-interrupt descriptor as below:
10554 * 'NDST' <-- vcpu->pre_pcpu
10555 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10556 * - If 'ON' is set during this process, which means at least one
10557 * interrupt is posted for this vCPU, we cannot block it, in
10558 * this case, return 1, otherwise, return 0.
10561 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10563 unsigned long flags;
10565 struct pi_desc old, new;
10566 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10568 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10569 !irq_remapping_cap(IRQ_POSTING_CAP))
10572 vcpu->pre_pcpu = vcpu->cpu;
10573 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10574 vcpu->pre_pcpu), flags);
10575 list_add_tail(&vcpu->blocked_vcpu_list,
10576 &per_cpu(blocked_vcpu_on_cpu,
10578 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10579 vcpu->pre_pcpu), flags);
10582 old.control = new.control = pi_desc->control;
10585 * We should not block the vCPU if
10586 * an interrupt is posted for it.
10588 if (pi_test_on(pi_desc) == 1) {
10589 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10590 vcpu->pre_pcpu), flags);
10591 list_del(&vcpu->blocked_vcpu_list);
10592 spin_unlock_irqrestore(
10593 &per_cpu(blocked_vcpu_on_cpu_lock,
10594 vcpu->pre_pcpu), flags);
10595 vcpu->pre_pcpu = -1;
10600 WARN((pi_desc->sn == 1),
10601 "Warning: SN field of posted-interrupts "
10602 "is set before blocking\n");
10605 * Since vCPU can be preempted during this process,
10606 * vcpu->cpu could be different with pre_pcpu, we
10607 * need to set pre_pcpu as the destination of wakeup
10608 * notification event, then we can find the right vCPU
10609 * to wakeup in wakeup handler if interrupts happen
10610 * when the vCPU is in blocked state.
10612 dest = cpu_physical_id(vcpu->pre_pcpu);
10614 if (x2apic_enabled())
10617 new.ndst = (dest << 8) & 0xFF00;
10619 /* set 'NV' to 'wakeup vector' */
10620 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10621 } while (cmpxchg(&pi_desc->control, old.control,
10622 new.control) != old.control);
10627 static void vmx_post_block(struct kvm_vcpu *vcpu)
10629 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10630 struct pi_desc old, new;
10632 unsigned long flags;
10634 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10635 !irq_remapping_cap(IRQ_POSTING_CAP))
10639 old.control = new.control = pi_desc->control;
10641 dest = cpu_physical_id(vcpu->cpu);
10643 if (x2apic_enabled())
10646 new.ndst = (dest << 8) & 0xFF00;
10648 /* Allow posting non-urgent interrupts */
10651 /* set 'NV' to 'notification vector' */
10652 new.nv = POSTED_INTR_VECTOR;
10653 } while (cmpxchg(&pi_desc->control, old.control,
10654 new.control) != old.control);
10656 if(vcpu->pre_pcpu != -1) {
10658 &per_cpu(blocked_vcpu_on_cpu_lock,
10659 vcpu->pre_pcpu), flags);
10660 list_del(&vcpu->blocked_vcpu_list);
10661 spin_unlock_irqrestore(
10662 &per_cpu(blocked_vcpu_on_cpu_lock,
10663 vcpu->pre_pcpu), flags);
10664 vcpu->pre_pcpu = -1;
10669 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10672 * @host_irq: host irq of the interrupt
10673 * @guest_irq: gsi of the interrupt
10674 * @set: set or unset PI
10675 * returns 0 on success, < 0 on failure
10677 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10678 uint32_t guest_irq, bool set)
10680 struct kvm_kernel_irq_routing_entry *e;
10681 struct kvm_irq_routing_table *irq_rt;
10682 struct kvm_lapic_irq irq;
10683 struct kvm_vcpu *vcpu;
10684 struct vcpu_data vcpu_info;
10685 int idx, ret = -EINVAL;
10687 if (!kvm_arch_has_assigned_device(kvm) ||
10688 !irq_remapping_cap(IRQ_POSTING_CAP))
10691 idx = srcu_read_lock(&kvm->irq_srcu);
10692 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10693 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10695 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10696 if (e->type != KVM_IRQ_ROUTING_MSI)
10699 * VT-d PI cannot support posting multicast/broadcast
10700 * interrupts to a vCPU, we still use interrupt remapping
10701 * for these kind of interrupts.
10703 * For lowest-priority interrupts, we only support
10704 * those with single CPU as the destination, e.g. user
10705 * configures the interrupts via /proc/irq or uses
10706 * irqbalance to make the interrupts single-CPU.
10708 * We will support full lowest-priority interrupt later.
10711 kvm_set_msi_irq(e, &irq);
10712 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10715 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10716 vcpu_info.vector = irq.vector;
10718 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10719 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10722 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10724 /* suppress notification event before unposting */
10725 pi_set_sn(vcpu_to_pi_desc(vcpu));
10726 ret = irq_set_vcpu_affinity(host_irq, NULL);
10727 pi_clear_sn(vcpu_to_pi_desc(vcpu));
10731 printk(KERN_INFO "%s: failed to update PI IRTE\n",
10739 srcu_read_unlock(&kvm->irq_srcu, idx);
10743 static struct kvm_x86_ops vmx_x86_ops = {
10744 .cpu_has_kvm_support = cpu_has_kvm_support,
10745 .disabled_by_bios = vmx_disabled_by_bios,
10746 .hardware_setup = hardware_setup,
10747 .hardware_unsetup = hardware_unsetup,
10748 .check_processor_compatibility = vmx_check_processor_compat,
10749 .hardware_enable = hardware_enable,
10750 .hardware_disable = hardware_disable,
10751 .cpu_has_accelerated_tpr = report_flexpriority,
10752 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10754 .vcpu_create = vmx_create_vcpu,
10755 .vcpu_free = vmx_free_vcpu,
10756 .vcpu_reset = vmx_vcpu_reset,
10758 .prepare_guest_switch = vmx_save_host_state,
10759 .vcpu_load = vmx_vcpu_load,
10760 .vcpu_put = vmx_vcpu_put,
10762 .update_db_bp_intercept = update_exception_bitmap,
10763 .get_msr = vmx_get_msr,
10764 .set_msr = vmx_set_msr,
10765 .get_segment_base = vmx_get_segment_base,
10766 .get_segment = vmx_get_segment,
10767 .set_segment = vmx_set_segment,
10768 .get_cpl = vmx_get_cpl,
10769 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10770 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10771 .decache_cr3 = vmx_decache_cr3,
10772 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10773 .set_cr0 = vmx_set_cr0,
10774 .set_cr3 = vmx_set_cr3,
10775 .set_cr4 = vmx_set_cr4,
10776 .set_efer = vmx_set_efer,
10777 .get_idt = vmx_get_idt,
10778 .set_idt = vmx_set_idt,
10779 .get_gdt = vmx_get_gdt,
10780 .set_gdt = vmx_set_gdt,
10781 .get_dr6 = vmx_get_dr6,
10782 .set_dr6 = vmx_set_dr6,
10783 .set_dr7 = vmx_set_dr7,
10784 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10785 .cache_reg = vmx_cache_reg,
10786 .get_rflags = vmx_get_rflags,
10787 .set_rflags = vmx_set_rflags,
10788 .fpu_activate = vmx_fpu_activate,
10789 .fpu_deactivate = vmx_fpu_deactivate,
10791 .tlb_flush = vmx_flush_tlb,
10793 .run = vmx_vcpu_run,
10794 .handle_exit = vmx_handle_exit,
10795 .skip_emulated_instruction = skip_emulated_instruction,
10796 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10797 .get_interrupt_shadow = vmx_get_interrupt_shadow,
10798 .patch_hypercall = vmx_patch_hypercall,
10799 .set_irq = vmx_inject_irq,
10800 .set_nmi = vmx_inject_nmi,
10801 .queue_exception = vmx_queue_exception,
10802 .cancel_injection = vmx_cancel_injection,
10803 .interrupt_allowed = vmx_interrupt_allowed,
10804 .nmi_allowed = vmx_nmi_allowed,
10805 .get_nmi_mask = vmx_get_nmi_mask,
10806 .set_nmi_mask = vmx_set_nmi_mask,
10807 .enable_nmi_window = enable_nmi_window,
10808 .enable_irq_window = enable_irq_window,
10809 .update_cr8_intercept = update_cr8_intercept,
10810 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10811 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10812 .cpu_uses_apicv = vmx_cpu_uses_apicv,
10813 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10814 .hwapic_irr_update = vmx_hwapic_irr_update,
10815 .hwapic_isr_update = vmx_hwapic_isr_update,
10816 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10817 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10819 .set_tss_addr = vmx_set_tss_addr,
10820 .get_tdp_level = get_ept_level,
10821 .get_mt_mask = vmx_get_mt_mask,
10823 .get_exit_info = vmx_get_exit_info,
10825 .get_lpage_level = vmx_get_lpage_level,
10827 .cpuid_update = vmx_cpuid_update,
10829 .rdtscp_supported = vmx_rdtscp_supported,
10830 .invpcid_supported = vmx_invpcid_supported,
10832 .set_supported_cpuid = vmx_set_supported_cpuid,
10834 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10836 .read_tsc_offset = vmx_read_tsc_offset,
10837 .write_tsc_offset = vmx_write_tsc_offset,
10838 .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10839 .read_l1_tsc = vmx_read_l1_tsc,
10841 .set_tdp_cr3 = vmx_set_cr3,
10843 .check_intercept = vmx_check_intercept,
10844 .handle_external_intr = vmx_handle_external_intr,
10845 .mpx_supported = vmx_mpx_supported,
10846 .xsaves_supported = vmx_xsaves_supported,
10848 .check_nested_events = vmx_check_nested_events,
10850 .sched_in = vmx_sched_in,
10852 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10853 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10854 .flush_log_dirty = vmx_flush_log_dirty,
10855 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10857 .pre_block = vmx_pre_block,
10858 .post_block = vmx_post_block,
10860 .pmu_ops = &intel_pmu_ops,
10862 .update_pi_irte = vmx_update_pi_irte,
10865 static int __init vmx_init(void)
10867 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10868 __alignof__(struct vcpu_vmx), THIS_MODULE);
10872 #ifdef CONFIG_KEXEC_CORE
10873 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10874 crash_vmclear_local_loaded_vmcss);
10880 static void __exit vmx_exit(void)
10882 #ifdef CONFIG_KEXEC_CORE
10883 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10890 module_init(vmx_init)
10891 module_exit(vmx_exit)