arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/trace_events.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/cpu.h>
  39 #include <asm/io.h>
  40 #include <asm/desc.h>
  41 #include <asm/vmx.h>
  42 #include <asm/virtext.h>
  43 #include <asm/mce.h>
  44 #include <asm/fpu/internal.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49 #include <asm/irq_remapping.h>
  50
  51 #include "trace.h"
  52 #include "pmu.h"
  53
  54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  55 #define __ex_clear(x, reg) \
  56         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  57
  58 MODULE_AUTHOR("Qumranet");
  59 MODULE_LICENSE("GPL");
  60
  61 static const struct x86_cpu_id vmx_cpu_id[] = {
  62         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  63         {}
  64 };
  65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  66
  67 static bool __read_mostly enable_vpid = 1;
  68 module_param_named(vpid, enable_vpid, bool, 0444);
  69
  70 static bool __read_mostly flexpriority_enabled = 1;
  71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_ept = 1;
  74 module_param_named(ept, enable_ept, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_unrestricted_guest = 1;
  77 module_param_named(unrestricted_guest,
  78                         enable_unrestricted_guest, bool, S_IRUGO);
  79
  80 static bool __read_mostly enable_ept_ad_bits = 1;
  81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  82
  83 static bool __read_mostly emulate_invalid_guest_state = true;
  84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  85
  86 static bool __read_mostly vmm_exclusive = 1;
  87 module_param(vmm_exclusive, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 114 #define KVM_VM_CR0_ALWAYS_ON                                            \
 115         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 116 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 117         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 118          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 119
 120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 122
 123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 124
 125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 126
 127 /*
 128  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 129  * ple_gap:    upper bound on the amount of time between two successive
 130  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 131  *             According to test, this time is usually smaller than 128 cycles.
 132  * ple_window: upper bound on the amount of time a guest is allowed to execute
 133  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 134  *             less than 2^12 cycles
 135  * Time is measured based on a counter that runs at the same rate as the TSC,
 136  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 137  */
 138 #define KVM_VMX_DEFAULT_PLE_GAP           128
 139 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 143                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 144
 145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 146 module_param(ple_gap, int, S_IRUGO);
 147
 148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 149 module_param(ple_window, int, S_IRUGO);
 150
 151 /* Default doubles per-vcpu window every exit. */
 152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 153 module_param(ple_window_grow, int, S_IRUGO);
 154
 155 /* Default resets per-vcpu window every exit to ple_window. */
 156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 157 module_param(ple_window_shrink, int, S_IRUGO);
 158
 159 /* Default is to compute the maximum so we can never overflow. */
 160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 161 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 module_param(ple_window_max, int, S_IRUGO);
 163
 164 extern const ulong vmx_return;
 165
 166 #define NR_AUTOLOAD_MSRS 8
 167 #define VMCS02_POOL_SIZE 1
 168
 169 struct vmcs {
 170         u32 revision_id;
 171         u32 abort;
 172         char data[0];
 173 };
 174
 175 /*
 176  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 177  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 178  * loaded on this CPU (so we can clear them if the CPU goes down).
 179  */
 180 struct loaded_vmcs {
 181         struct vmcs *vmcs;
 182         int cpu;
 183         int launched;
 184         struct list_head loaded_vmcss_on_cpu_link;
 185 };
 186
 187 struct shared_msr_entry {
 188         unsigned index;
 189         u64 data;
 190         u64 mask;
 191 };
 192
 193 /*
 194  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 195  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 196  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 197  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 198  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 199  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 200  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 201  * underlying hardware which will be used to run L2.
 202  * This structure is packed to ensure that its layout is identical across
 203  * machines (necessary for live migration).
 204  * If there are changes in this struct, VMCS12_REVISION must be changed.
 205  */
 206 typedef u64 natural_width;
 207 struct __packed vmcs12 {
 208         /* According to the Intel spec, a VMCS region must start with the
 209          * following two fields. Then follow implementation-specific data.
 210          */
 211         u32 revision_id;
 212         u32 abort;
 213
 214         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 215         u32 padding[7]; /* room for future expansion */
 216
 217         u64 io_bitmap_a;
 218         u64 io_bitmap_b;
 219         u64 msr_bitmap;
 220         u64 vm_exit_msr_store_addr;
 221         u64 vm_exit_msr_load_addr;
 222         u64 vm_entry_msr_load_addr;
 223         u64 tsc_offset;
 224         u64 virtual_apic_page_addr;
 225         u64 apic_access_addr;
 226         u64 posted_intr_desc_addr;
 227         u64 ept_pointer;
 228         u64 eoi_exit_bitmap0;
 229         u64 eoi_exit_bitmap1;
 230         u64 eoi_exit_bitmap2;
 231         u64 eoi_exit_bitmap3;
 232         u64 xss_exit_bitmap;
 233         u64 guest_physical_address;
 234         u64 vmcs_link_pointer;
 235         u64 guest_ia32_debugctl;
 236         u64 guest_ia32_pat;
 237         u64 guest_ia32_efer;
 238         u64 guest_ia32_perf_global_ctrl;
 239         u64 guest_pdptr0;
 240         u64 guest_pdptr1;
 241         u64 guest_pdptr2;
 242         u64 guest_pdptr3;
 243         u64 guest_bndcfgs;
 244         u64 host_ia32_pat;
 245         u64 host_ia32_efer;
 246         u64 host_ia32_perf_global_ctrl;
 247         u64 padding64[8]; /* room for future expansion */
 248         /*
 249          * To allow migration of L1 (complete with its L2 guests) between
 250          * machines of different natural widths (32 or 64 bit), we cannot have
 251          * unsigned long fields with no explict size. We use u64 (aliased
 252          * natural_width) instead. Luckily, x86 is little-endian.
 253          */
 254         natural_width cr0_guest_host_mask;
 255         natural_width cr4_guest_host_mask;
 256         natural_width cr0_read_shadow;
 257         natural_width cr4_read_shadow;
 258         natural_width cr3_target_value0;
 259         natural_width cr3_target_value1;
 260         natural_width cr3_target_value2;
 261         natural_width cr3_target_value3;
 262         natural_width exit_qualification;
 263         natural_width guest_linear_address;
 264         natural_width guest_cr0;
 265         natural_width guest_cr3;
 266         natural_width guest_cr4;
 267         natural_width guest_es_base;
 268         natural_width guest_cs_base;
 269         natural_width guest_ss_base;
 270         natural_width guest_ds_base;
 271         natural_width guest_fs_base;
 272         natural_width guest_gs_base;
 273         natural_width guest_ldtr_base;
 274         natural_width guest_tr_base;
 275         natural_width guest_gdtr_base;
 276         natural_width guest_idtr_base;
 277         natural_width guest_dr7;
 278         natural_width guest_rsp;
 279         natural_width guest_rip;
 280         natural_width guest_rflags;
 281         natural_width guest_pending_dbg_exceptions;
 282         natural_width guest_sysenter_esp;
 283         natural_width guest_sysenter_eip;
 284         natural_width host_cr0;
 285         natural_width host_cr3;
 286         natural_width host_cr4;
 287         natural_width host_fs_base;
 288         natural_width host_gs_base;
 289         natural_width host_tr_base;
 290         natural_width host_gdtr_base;
 291         natural_width host_idtr_base;
 292         natural_width host_ia32_sysenter_esp;
 293         natural_width host_ia32_sysenter_eip;
 294         natural_width host_rsp;
 295         natural_width host_rip;
 296         natural_width paddingl[8]; /* room for future expansion */
 297         u32 pin_based_vm_exec_control;
 298         u32 cpu_based_vm_exec_control;
 299         u32 exception_bitmap;
 300         u32 page_fault_error_code_mask;
 301         u32 page_fault_error_code_match;
 302         u32 cr3_target_count;
 303         u32 vm_exit_controls;
 304         u32 vm_exit_msr_store_count;
 305         u32 vm_exit_msr_load_count;
 306         u32 vm_entry_controls;
 307         u32 vm_entry_msr_load_count;
 308         u32 vm_entry_intr_info_field;
 309         u32 vm_entry_exception_error_code;
 310         u32 vm_entry_instruction_len;
 311         u32 tpr_threshold;
 312         u32 secondary_vm_exec_control;
 313         u32 vm_instruction_error;
 314         u32 vm_exit_reason;
 315         u32 vm_exit_intr_info;
 316         u32 vm_exit_intr_error_code;
 317         u32 idt_vectoring_info_field;
 318         u32 idt_vectoring_error_code;
 319         u32 vm_exit_instruction_len;
 320         u32 vmx_instruction_info;
 321         u32 guest_es_limit;
 322         u32 guest_cs_limit;
 323         u32 guest_ss_limit;
 324         u32 guest_ds_limit;
 325         u32 guest_fs_limit;
 326         u32 guest_gs_limit;
 327         u32 guest_ldtr_limit;
 328         u32 guest_tr_limit;
 329         u32 guest_gdtr_limit;
 330         u32 guest_idtr_limit;
 331         u32 guest_es_ar_bytes;
 332         u32 guest_cs_ar_bytes;
 333         u32 guest_ss_ar_bytes;
 334         u32 guest_ds_ar_bytes;
 335         u32 guest_fs_ar_bytes;
 336         u32 guest_gs_ar_bytes;
 337         u32 guest_ldtr_ar_bytes;
 338         u32 guest_tr_ar_bytes;
 339         u32 guest_interruptibility_info;
 340         u32 guest_activity_state;
 341         u32 guest_sysenter_cs;
 342         u32 host_ia32_sysenter_cs;
 343         u32 vmx_preemption_timer_value;
 344         u32 padding32[7]; /* room for future expansion */
 345         u16 virtual_processor_id;
 346         u16 posted_intr_nv;
 347         u16 guest_es_selector;
 348         u16 guest_cs_selector;
 349         u16 guest_ss_selector;
 350         u16 guest_ds_selector;
 351         u16 guest_fs_selector;
 352         u16 guest_gs_selector;
 353         u16 guest_ldtr_selector;
 354         u16 guest_tr_selector;
 355         u16 guest_intr_status;
 356         u16 host_es_selector;
 357         u16 host_cs_selector;
 358         u16 host_ss_selector;
 359         u16 host_ds_selector;
 360         u16 host_fs_selector;
 361         u16 host_gs_selector;
 362         u16 host_tr_selector;
 363 };
 364
 365 /*
 366  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 367  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 368  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 369  */
 370 #define VMCS12_REVISION 0x11e57ed0
 371
 372 /*
 373  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 374  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 375  * current implementation, 4K are reserved to avoid future complications.
 376  */
 377 #define VMCS12_SIZE 0x1000
 378
 379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 380 struct vmcs02_list {
 381         struct list_head list;
 382         gpa_t vmptr;
 383         struct loaded_vmcs vmcs02;
 384 };
 385
 386 /*
 387  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 388  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 389  */
 390 struct nested_vmx {
 391         /* Has the level1 guest done vmxon? */
 392         bool vmxon;
 393         gpa_t vmxon_ptr;
 394
 395         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 396         gpa_t current_vmptr;
 397         /* The host-usable pointer to the above */
 398         struct page *current_vmcs12_page;
 399         struct vmcs12 *current_vmcs12;
 400         struct vmcs *current_shadow_vmcs;
 401         /*
 402          * Indicates if the shadow vmcs must be updated with the
 403          * data hold by vmcs12
 404          */
 405         bool sync_shadow_vmcs;
 406
 407         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 408         struct list_head vmcs02_pool;
 409         int vmcs02_num;
 410         u64 vmcs01_tsc_offset;
 411         /* L2 must run next, and mustn't decide to exit to L1. */
 412         bool nested_run_pending;
 413         /*
 414          * Guest pages referred to in vmcs02 with host-physical pointers, so
 415          * we must keep them pinned while L2 runs.
 416          */
 417         struct page *apic_access_page;
 418         struct page *virtual_apic_page;
 419         struct page *pi_desc_page;
 420         struct pi_desc *pi_desc;
 421         bool pi_pending;
 422         u16 posted_intr_nv;
 423         u64 msr_ia32_feature_control;
 424
 425         struct hrtimer preemption_timer;
 426         bool preemption_timer_expired;
 427
 428         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 429         u64 vmcs01_debugctl;
 430
 431         u16 vpid02;
 432         u16 last_vpid;
 433
 434         u32 nested_vmx_procbased_ctls_low;
 435         u32 nested_vmx_procbased_ctls_high;
 436         u32 nested_vmx_true_procbased_ctls_low;
 437         u32 nested_vmx_secondary_ctls_low;
 438         u32 nested_vmx_secondary_ctls_high;
 439         u32 nested_vmx_pinbased_ctls_low;
 440         u32 nested_vmx_pinbased_ctls_high;
 441         u32 nested_vmx_exit_ctls_low;
 442         u32 nested_vmx_exit_ctls_high;
 443         u32 nested_vmx_true_exit_ctls_low;
 444         u32 nested_vmx_entry_ctls_low;
 445         u32 nested_vmx_entry_ctls_high;
 446         u32 nested_vmx_true_entry_ctls_low;
 447         u32 nested_vmx_misc_low;
 448         u32 nested_vmx_misc_high;
 449         u32 nested_vmx_ept_caps;
 450         u32 nested_vmx_vpid_caps;
 451 };
 452
 453 #define POSTED_INTR_ON  0
 454 #define POSTED_INTR_SN  1
 455
 456 /* Posted-Interrupt Descriptor */
 457 struct pi_desc {
 458         u32 pir[8];     /* Posted interrupt requested */
 459         union {
 460                 struct {
 461                                 /* bit 256 - Outstanding Notification */
 462                         u16     on      : 1,
 463                                 /* bit 257 - Suppress Notification */
 464                                 sn      : 1,
 465                                 /* bit 271:258 - Reserved */
 466                                 rsvd_1  : 14;
 467                                 /* bit 279:272 - Notification Vector */
 468                         u8      nv;
 469                                 /* bit 287:280 - Reserved */
 470                         u8      rsvd_2;
 471                                 /* bit 319:288 - Notification Destination */
 472                         u32     ndst;
 473                 };
 474                 u64 control;
 475         };
 476         u32 rsvd[6];
 477 } __aligned(64);
 478
 479 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 480 {
 481         return test_and_set_bit(POSTED_INTR_ON,
 482                         (unsigned long *)&pi_desc->control);
 483 }
 484
 485 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 486 {
 487         return test_and_clear_bit(POSTED_INTR_ON,
 488                         (unsigned long *)&pi_desc->control);
 489 }
 490
 491 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 492 {
 493         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 494 }
 495
 496 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 497 {
 498         return clear_bit(POSTED_INTR_SN,
 499                         (unsigned long *)&pi_desc->control);
 500 }
 501
 502 static inline void pi_set_sn(struct pi_desc *pi_desc)
 503 {
 504         return set_bit(POSTED_INTR_SN,
 505                         (unsigned long *)&pi_desc->control);
 506 }
 507
 508 static inline int pi_test_on(struct pi_desc *pi_desc)
 509 {
 510         return test_bit(POSTED_INTR_ON,
 511                         (unsigned long *)&pi_desc->control);
 512 }
 513
 514 static inline int pi_test_sn(struct pi_desc *pi_desc)
 515 {
 516         return test_bit(POSTED_INTR_SN,
 517                         (unsigned long *)&pi_desc->control);
 518 }
 519
 520 struct vcpu_vmx {
 521         struct kvm_vcpu       vcpu;
 522         unsigned long         host_rsp;
 523         u8                    fail;
 524         bool                  nmi_known_unmasked;
 525         u32                   exit_intr_info;
 526         u32                   idt_vectoring_info;
 527         ulong                 rflags;
 528         struct shared_msr_entry *guest_msrs;
 529         int                   nmsrs;
 530         int                   save_nmsrs;
 531         unsigned long         host_idt_base;
 532 #ifdef CONFIG_X86_64
 533         u64                   msr_host_kernel_gs_base;
 534         u64                   msr_guest_kernel_gs_base;
 535 #endif
 536         u32 vm_entry_controls_shadow;
 537         u32 vm_exit_controls_shadow;
 538         /*
 539          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 540          * non-nested (L1) guest, it always points to vmcs01. For a nested
 541          * guest (L2), it points to a different VMCS.
 542          */
 543         struct loaded_vmcs    vmcs01;
 544         struct loaded_vmcs   *loaded_vmcs;
 545         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 546         struct msr_autoload {
 547                 unsigned nr;
 548                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 549                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 550         } msr_autoload;
 551         struct {
 552                 int           loaded;
 553                 u16           fs_sel, gs_sel, ldt_sel;
 554 #ifdef CONFIG_X86_64
 555                 u16           ds_sel, es_sel;
 556 #endif
 557                 int           gs_ldt_reload_needed;
 558                 int           fs_reload_needed;
 559                 u64           msr_host_bndcfgs;
 560                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 561         } host_state;
 562         struct {
 563                 int vm86_active;
 564                 ulong save_rflags;
 565                 struct kvm_segment segs[8];
 566         } rmode;
 567         struct {
 568                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 569                 struct kvm_save_segment {
 570                         u16 selector;
 571                         unsigned long base;
 572                         u32 limit;
 573                         u32 ar;
 574                 } seg[8];
 575         } segment_cache;
 576         int vpid;
 577         bool emulation_required;
 578
 579         /* Support for vnmi-less CPUs */
 580         int soft_vnmi_blocked;
 581         ktime_t entry_time;
 582         s64 vnmi_blocked_time;
 583         u32 exit_reason;
 584
 585         /* Posted interrupt descriptor */
 586         struct pi_desc pi_desc;
 587
 588         /* Support for a guest hypervisor (nested VMX) */
 589         struct nested_vmx nested;
 590
 591         /* Dynamic PLE window. */
 592         int ple_window;
 593         bool ple_window_dirty;
 594
 595         /* Support for PML */
 596 #define PML_ENTITY_NUM          512
 597         struct page *pml_pg;
 598
 599         u64 current_tsc_ratio;
 600 };
 601
 602 enum segment_cache_field {
 603         SEG_FIELD_SEL = 0,
 604         SEG_FIELD_BASE = 1,
 605         SEG_FIELD_LIMIT = 2,
 606         SEG_FIELD_AR = 3,
 607
 608         SEG_FIELD_NR = 4
 609 };
 610
 611 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 612 {
 613         return container_of(vcpu, struct vcpu_vmx, vcpu);
 614 }
 615
 616 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 617 {
 618         return &(to_vmx(vcpu)->pi_desc);
 619 }
 620
 621 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 622 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 623 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 624                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 625
 626
 627 static unsigned long shadow_read_only_fields[] = {
 628         /*
 629          * We do NOT shadow fields that are modified when L0
 630          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 631          * VMXON...) executed by L1.
 632          * For example, VM_INSTRUCTION_ERROR is read
 633          * by L1 if a vmx instruction fails (part of the error path).
 634          * Note the code assumes this logic. If for some reason
 635          * we start shadowing these fields then we need to
 636          * force a shadow sync when L0 emulates vmx instructions
 637          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 638          * by nested_vmx_failValid)
 639          */
 640         VM_EXIT_REASON,
 641         VM_EXIT_INTR_INFO,
 642         VM_EXIT_INSTRUCTION_LEN,
 643         IDT_VECTORING_INFO_FIELD,
 644         IDT_VECTORING_ERROR_CODE,
 645         VM_EXIT_INTR_ERROR_CODE,
 646         EXIT_QUALIFICATION,
 647         GUEST_LINEAR_ADDRESS,
 648         GUEST_PHYSICAL_ADDRESS
 649 };
 650 static int max_shadow_read_only_fields =
 651         ARRAY_SIZE(shadow_read_only_fields);
 652
 653 static unsigned long shadow_read_write_fields[] = {
 654         TPR_THRESHOLD,
 655         GUEST_RIP,
 656         GUEST_RSP,
 657         GUEST_CR0,
 658         GUEST_CR3,
 659         GUEST_CR4,
 660         GUEST_INTERRUPTIBILITY_INFO,
 661         GUEST_RFLAGS,
 662         GUEST_CS_SELECTOR,
 663         GUEST_CS_AR_BYTES,
 664         GUEST_CS_LIMIT,
 665         GUEST_CS_BASE,
 666         GUEST_ES_BASE,
 667         GUEST_BNDCFGS,
 668         CR0_GUEST_HOST_MASK,
 669         CR0_READ_SHADOW,
 670         CR4_READ_SHADOW,
 671         TSC_OFFSET,
 672         EXCEPTION_BITMAP,
 673         CPU_BASED_VM_EXEC_CONTROL,
 674         VM_ENTRY_EXCEPTION_ERROR_CODE,
 675         VM_ENTRY_INTR_INFO_FIELD,
 676         VM_ENTRY_INSTRUCTION_LEN,
 677         VM_ENTRY_EXCEPTION_ERROR_CODE,
 678         HOST_FS_BASE,
 679         HOST_GS_BASE,
 680         HOST_FS_SELECTOR,
 681         HOST_GS_SELECTOR
 682 };
 683 static int max_shadow_read_write_fields =
 684         ARRAY_SIZE(shadow_read_write_fields);
 685
 686 static const unsigned short vmcs_field_to_offset_table[] = {
 687         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 688         FIELD(POSTED_INTR_NV, posted_intr_nv),
 689         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 690         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 691         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 692         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 693         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 694         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 695         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 696         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 697         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 698         FIELD(HOST_ES_SELECTOR, host_es_selector),
 699         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 700         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 701         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 702         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 703         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 704         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 705         FIELD64(IO_BITMAP_A, io_bitmap_a),
 706         FIELD64(IO_BITMAP_B, io_bitmap_b),
 707         FIELD64(MSR_BITMAP, msr_bitmap),
 708         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 709         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 710         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 711         FIELD64(TSC_OFFSET, tsc_offset),
 712         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 713         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 714         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 715         FIELD64(EPT_POINTER, ept_pointer),
 716         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 717         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 718         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 719         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 720         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 721         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 722         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 723         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 724         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 725         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 726         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 727         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 728         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 729         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 730         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 731         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 732         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 733         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 734         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 735         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 736         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 737         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 738         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 739         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 740         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 741         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 742         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 743         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 744         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 745         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 746         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 747         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 748         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 749         FIELD(TPR_THRESHOLD, tpr_threshold),
 750         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 751         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 752         FIELD(VM_EXIT_REASON, vm_exit_reason),
 753         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 754         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 755         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 756         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 757         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 758         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 759         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 760         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 761         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 762         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 763         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 764         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 765         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 766         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 767         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 768         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 769         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 770         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 771         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 772         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 773         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 774         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 775         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 776         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 777         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 778         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 779         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 780         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 781         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 782         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 783         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 784         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 785         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 786         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 787         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 788         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 789         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 790         FIELD(EXIT_QUALIFICATION, exit_qualification),
 791         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 792         FIELD(GUEST_CR0, guest_cr0),
 793         FIELD(GUEST_CR3, guest_cr3),
 794         FIELD(GUEST_CR4, guest_cr4),
 795         FIELD(GUEST_ES_BASE, guest_es_base),
 796         FIELD(GUEST_CS_BASE, guest_cs_base),
 797         FIELD(GUEST_SS_BASE, guest_ss_base),
 798         FIELD(GUEST_DS_BASE, guest_ds_base),
 799         FIELD(GUEST_FS_BASE, guest_fs_base),
 800         FIELD(GUEST_GS_BASE, guest_gs_base),
 801         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 802         FIELD(GUEST_TR_BASE, guest_tr_base),
 803         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 804         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 805         FIELD(GUEST_DR7, guest_dr7),
 806         FIELD(GUEST_RSP, guest_rsp),
 807         FIELD(GUEST_RIP, guest_rip),
 808         FIELD(GUEST_RFLAGS, guest_rflags),
 809         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 810         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 811         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 812         FIELD(HOST_CR0, host_cr0),
 813         FIELD(HOST_CR3, host_cr3),
 814         FIELD(HOST_CR4, host_cr4),
 815         FIELD(HOST_FS_BASE, host_fs_base),
 816         FIELD(HOST_GS_BASE, host_gs_base),
 817         FIELD(HOST_TR_BASE, host_tr_base),
 818         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 819         FIELD(HOST_IDTR_BASE, host_idtr_base),
 820         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 821         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 822         FIELD(HOST_RSP, host_rsp),
 823         FIELD(HOST_RIP, host_rip),
 824 };
 825
 826 static inline short vmcs_field_to_offset(unsigned long field)
 827 {
 828         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 829
 830         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 831             vmcs_field_to_offset_table[field] == 0)
 832                 return -ENOENT;
 833
 834         return vmcs_field_to_offset_table[field];
 835 }
 836
 837 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 838 {
 839         return to_vmx(vcpu)->nested.current_vmcs12;
 840 }
 841
 842 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 843 {
 844         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 845         if (is_error_page(page))
 846                 return NULL;
 847
 848         return page;
 849 }
 850
 851 static void nested_release_page(struct page *page)
 852 {
 853         kvm_release_page_dirty(page);
 854 }
 855
 856 static void nested_release_page_clean(struct page *page)
 857 {
 858         kvm_release_page_clean(page);
 859 }
 860
 861 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 862 static u64 construct_eptp(unsigned long root_hpa);
 863 static void kvm_cpu_vmxon(u64 addr);
 864 static void kvm_cpu_vmxoff(void);
 865 static bool vmx_mpx_supported(void);
 866 static bool vmx_xsaves_supported(void);
 867 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
 868 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 869 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg);
 871 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 872                             struct kvm_segment *var, int seg);
 873 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 874 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 875 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 876 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 877 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 878 static int alloc_identity_pagetable(struct kvm *kvm);
 879
 880 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 881 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 882 /*
 883  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 884  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 885  */
 886 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 887 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 888
 889 /*
 890  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 891  * can find which vCPU should be waken up.
 892  */
 893 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 894 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 895
 896 static unsigned long *vmx_io_bitmap_a;
 897 static unsigned long *vmx_io_bitmap_b;
 898 static unsigned long *vmx_msr_bitmap_legacy;
 899 static unsigned long *vmx_msr_bitmap_longmode;
 900 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 901 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 902 static unsigned long *vmx_msr_bitmap_nested;
 903 static unsigned long *vmx_vmread_bitmap;
 904 static unsigned long *vmx_vmwrite_bitmap;
 905
 906 static bool cpu_has_load_ia32_efer;
 907 static bool cpu_has_load_perf_global_ctrl;
 908
 909 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 910 static DEFINE_SPINLOCK(vmx_vpid_lock);
 911
 912 static struct vmcs_config {
 913         int size;
 914         int order;
 915         u32 revision_id;
 916         u32 pin_based_exec_ctrl;
 917         u32 cpu_based_exec_ctrl;
 918         u32 cpu_based_2nd_exec_ctrl;
 919         u32 vmexit_ctrl;
 920         u32 vmentry_ctrl;
 921 } vmcs_config;
 922
 923 static struct vmx_capability {
 924         u32 ept;
 925         u32 vpid;
 926 } vmx_capability;
 927
 928 #define VMX_SEGMENT_FIELD(seg)                                  \
 929         [VCPU_SREG_##seg] = {                                   \
 930                 .selector = GUEST_##seg##_SELECTOR,             \
 931                 .base = GUEST_##seg##_BASE,                     \
 932                 .limit = GUEST_##seg##_LIMIT,                   \
 933                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 934         }
 935
 936 static const struct kvm_vmx_segment_field {
 937         unsigned selector;
 938         unsigned base;
 939         unsigned limit;
 940         unsigned ar_bytes;
 941 } kvm_vmx_segment_fields[] = {
 942         VMX_SEGMENT_FIELD(CS),
 943         VMX_SEGMENT_FIELD(DS),
 944         VMX_SEGMENT_FIELD(ES),
 945         VMX_SEGMENT_FIELD(FS),
 946         VMX_SEGMENT_FIELD(GS),
 947         VMX_SEGMENT_FIELD(SS),
 948         VMX_SEGMENT_FIELD(TR),
 949         VMX_SEGMENT_FIELD(LDTR),
 950 };
 951
 952 static u64 host_efer;
 953
 954 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 955
 956 /*
 957  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 958  * away by decrementing the array size.
 959  */
 960 static const u32 vmx_msr_index[] = {
 961 #ifdef CONFIG_X86_64
 962         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 963 #endif
 964         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 965 };
 966
 967 static inline bool is_page_fault(u32 intr_info)
 968 {
 969         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 970                              INTR_INFO_VALID_MASK)) ==
 971                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 972 }
 973
 974 static inline bool is_no_device(u32 intr_info)
 975 {
 976         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 977                              INTR_INFO_VALID_MASK)) ==
 978                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 979 }
 980
 981 static inline bool is_invalid_opcode(u32 intr_info)
 982 {
 983         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 984                              INTR_INFO_VALID_MASK)) ==
 985                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 986 }
 987
 988 static inline bool is_external_interrupt(u32 intr_info)
 989 {
 990         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 991                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 992 }
 993
 994 static inline bool is_machine_check(u32 intr_info)
 995 {
 996         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 997                              INTR_INFO_VALID_MASK)) ==
 998                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 999 }
1000
1001 static inline bool cpu_has_vmx_msr_bitmap(void)
1002 {
1003         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1004 }
1005
1006 static inline bool cpu_has_vmx_tpr_shadow(void)
1007 {
1008         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1009 }
1010
1011 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1012 {
1013         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1014 }
1015
1016 static inline bool cpu_has_secondary_exec_ctrls(void)
1017 {
1018         return vmcs_config.cpu_based_exec_ctrl &
1019                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1020 }
1021
1022 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1023 {
1024         return vmcs_config.cpu_based_2nd_exec_ctrl &
1025                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1026 }
1027
1028 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1029 {
1030         return vmcs_config.cpu_based_2nd_exec_ctrl &
1031                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1032 }
1033
1034 static inline bool cpu_has_vmx_apic_register_virt(void)
1035 {
1036         return vmcs_config.cpu_based_2nd_exec_ctrl &
1037                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1038 }
1039
1040 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1041 {
1042         return vmcs_config.cpu_based_2nd_exec_ctrl &
1043                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1044 }
1045
1046 static inline bool cpu_has_vmx_posted_intr(void)
1047 {
1048         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1049                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1050 }
1051
1052 static inline bool cpu_has_vmx_apicv(void)
1053 {
1054         return cpu_has_vmx_apic_register_virt() &&
1055                 cpu_has_vmx_virtual_intr_delivery() &&
1056                 cpu_has_vmx_posted_intr();
1057 }
1058
1059 static inline bool cpu_has_vmx_flexpriority(void)
1060 {
1061         return cpu_has_vmx_tpr_shadow() &&
1062                 cpu_has_vmx_virtualize_apic_accesses();
1063 }
1064
1065 static inline bool cpu_has_vmx_ept_execute_only(void)
1066 {
1067         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1068 }
1069
1070 static inline bool cpu_has_vmx_ept_2m_page(void)
1071 {
1072         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1073 }
1074
1075 static inline bool cpu_has_vmx_ept_1g_page(void)
1076 {
1077         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1078 }
1079
1080 static inline bool cpu_has_vmx_ept_4levels(void)
1081 {
1082         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1083 }
1084
1085 static inline bool cpu_has_vmx_ept_ad_bits(void)
1086 {
1087         return vmx_capability.ept & VMX_EPT_AD_BIT;
1088 }
1089
1090 static inline bool cpu_has_vmx_invept_context(void)
1091 {
1092         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1093 }
1094
1095 static inline bool cpu_has_vmx_invept_global(void)
1096 {
1097         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1098 }
1099
1100 static inline bool cpu_has_vmx_invvpid_single(void)
1101 {
1102         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1103 }
1104
1105 static inline bool cpu_has_vmx_invvpid_global(void)
1106 {
1107         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1108 }
1109
1110 static inline bool cpu_has_vmx_ept(void)
1111 {
1112         return vmcs_config.cpu_based_2nd_exec_ctrl &
1113                 SECONDARY_EXEC_ENABLE_EPT;
1114 }
1115
1116 static inline bool cpu_has_vmx_unrestricted_guest(void)
1117 {
1118         return vmcs_config.cpu_based_2nd_exec_ctrl &
1119                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1120 }
1121
1122 static inline bool cpu_has_vmx_ple(void)
1123 {
1124         return vmcs_config.cpu_based_2nd_exec_ctrl &
1125                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1126 }
1127
1128 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1129 {
1130         return flexpriority_enabled && lapic_in_kernel(vcpu);
1131 }
1132
1133 static inline bool cpu_has_vmx_vpid(void)
1134 {
1135         return vmcs_config.cpu_based_2nd_exec_ctrl &
1136                 SECONDARY_EXEC_ENABLE_VPID;
1137 }
1138
1139 static inline bool cpu_has_vmx_rdtscp(void)
1140 {
1141         return vmcs_config.cpu_based_2nd_exec_ctrl &
1142                 SECONDARY_EXEC_RDTSCP;
1143 }
1144
1145 static inline bool cpu_has_vmx_invpcid(void)
1146 {
1147         return vmcs_config.cpu_based_2nd_exec_ctrl &
1148                 SECONDARY_EXEC_ENABLE_INVPCID;
1149 }
1150
1151 static inline bool cpu_has_virtual_nmis(void)
1152 {
1153         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1154 }
1155
1156 static inline bool cpu_has_vmx_wbinvd_exit(void)
1157 {
1158         return vmcs_config.cpu_based_2nd_exec_ctrl &
1159                 SECONDARY_EXEC_WBINVD_EXITING;
1160 }
1161
1162 static inline bool cpu_has_vmx_shadow_vmcs(void)
1163 {
1164         u64 vmx_msr;
1165         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1166         /* check if the cpu supports writing r/o exit information fields */
1167         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1168                 return false;
1169
1170         return vmcs_config.cpu_based_2nd_exec_ctrl &
1171                 SECONDARY_EXEC_SHADOW_VMCS;
1172 }
1173
1174 static inline bool cpu_has_vmx_pml(void)
1175 {
1176         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1177 }
1178
1179 static inline bool cpu_has_vmx_tsc_scaling(void)
1180 {
1181         return vmcs_config.cpu_based_2nd_exec_ctrl &
1182                 SECONDARY_EXEC_TSC_SCALING;
1183 }
1184
1185 static inline bool report_flexpriority(void)
1186 {
1187         return flexpriority_enabled;
1188 }
1189
1190 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1191 {
1192         return vmcs12->cpu_based_vm_exec_control & bit;
1193 }
1194
1195 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1196 {
1197         return (vmcs12->cpu_based_vm_exec_control &
1198                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1199                 (vmcs12->secondary_vm_exec_control & bit);
1200 }
1201
1202 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1203 {
1204         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1205 }
1206
1207 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1208 {
1209         return vmcs12->pin_based_vm_exec_control &
1210                 PIN_BASED_VMX_PREEMPTION_TIMER;
1211 }
1212
1213 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1214 {
1215         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1216 }
1217
1218 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1219 {
1220         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1221                 vmx_xsaves_supported();
1222 }
1223
1224 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1225 {
1226         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1227 }
1228
1229 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1230 {
1231         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1232 }
1233
1234 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1235 {
1236         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1237 }
1238
1239 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1240 {
1241         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1242 }
1243
1244 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1245 {
1246         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1247 }
1248
1249 static inline bool is_exception(u32 intr_info)
1250 {
1251         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1252                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1253 }
1254
1255 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1256                               u32 exit_intr_info,
1257                               unsigned long exit_qualification);
1258 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1259                         struct vmcs12 *vmcs12,
1260                         u32 reason, unsigned long qualification);
1261
1262 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1263 {
1264         int i;
1265
1266         for (i = 0; i < vmx->nmsrs; ++i)
1267                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1268                         return i;
1269         return -1;
1270 }
1271
1272 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1273 {
1274     struct {
1275         u64 vpid : 16;
1276         u64 rsvd : 48;
1277         u64 gva;
1278     } operand = { vpid, 0, gva };
1279
1280     asm volatile (__ex(ASM_VMX_INVVPID)
1281                   /* CF==1 or ZF==1 --> rc = -1 */
1282                   "; ja 1f ; ud2 ; 1:"
1283                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1284 }
1285
1286 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1287 {
1288         struct {
1289                 u64 eptp, gpa;
1290         } operand = {eptp, gpa};
1291
1292         asm volatile (__ex(ASM_VMX_INVEPT)
1293                         /* CF==1 or ZF==1 --> rc = -1 */
1294                         "; ja 1f ; ud2 ; 1:\n"
1295                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1296 }
1297
1298 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1299 {
1300         int i;
1301
1302         i = __find_msr_index(vmx, msr);
1303         if (i >= 0)
1304                 return &vmx->guest_msrs[i];
1305         return NULL;
1306 }
1307
1308 static void vmcs_clear(struct vmcs *vmcs)
1309 {
1310         u64 phys_addr = __pa(vmcs);
1311         u8 error;
1312
1313         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1314                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1315                       : "cc", "memory");
1316         if (error)
1317                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1318                        vmcs, phys_addr);
1319 }
1320
1321 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1322 {
1323         vmcs_clear(loaded_vmcs->vmcs);
1324         loaded_vmcs->cpu = -1;
1325         loaded_vmcs->launched = 0;
1326 }
1327
1328 static void vmcs_load(struct vmcs *vmcs)
1329 {
1330         u64 phys_addr = __pa(vmcs);
1331         u8 error;
1332
1333         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1334                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1335                         : "cc", "memory");
1336         if (error)
1337                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1338                        vmcs, phys_addr);
1339 }
1340
1341 #ifdef CONFIG_KEXEC_CORE
1342 /*
1343  * This bitmap is used to indicate whether the vmclear
1344  * operation is enabled on all cpus. All disabled by
1345  * default.
1346  */
1347 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1348
1349 static inline void crash_enable_local_vmclear(int cpu)
1350 {
1351         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1352 }
1353
1354 static inline void crash_disable_local_vmclear(int cpu)
1355 {
1356         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1357 }
1358
1359 static inline int crash_local_vmclear_enabled(int cpu)
1360 {
1361         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1362 }
1363
1364 static void crash_vmclear_local_loaded_vmcss(void)
1365 {
1366         int cpu = raw_smp_processor_id();
1367         struct loaded_vmcs *v;
1368
1369         if (!crash_local_vmclear_enabled(cpu))
1370                 return;
1371
1372         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1373                             loaded_vmcss_on_cpu_link)
1374                 vmcs_clear(v->vmcs);
1375 }
1376 #else
1377 static inline void crash_enable_local_vmclear(int cpu) { }
1378 static inline void crash_disable_local_vmclear(int cpu) { }
1379 #endif /* CONFIG_KEXEC_CORE */
1380
1381 static void __loaded_vmcs_clear(void *arg)
1382 {
1383         struct loaded_vmcs *loaded_vmcs = arg;
1384         int cpu = raw_smp_processor_id();
1385
1386         if (loaded_vmcs->cpu != cpu)
1387                 return; /* vcpu migration can race with cpu offline */
1388         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1389                 per_cpu(current_vmcs, cpu) = NULL;
1390         crash_disable_local_vmclear(cpu);
1391         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1392
1393         /*
1394          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1395          * is before setting loaded_vmcs->vcpu to -1 which is done in
1396          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1397          * then adds the vmcs into percpu list before it is deleted.
1398          */
1399         smp_wmb();
1400
1401         loaded_vmcs_init(loaded_vmcs);
1402         crash_enable_local_vmclear(cpu);
1403 }
1404
1405 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1406 {
1407         int cpu = loaded_vmcs->cpu;
1408
1409         if (cpu != -1)
1410                 smp_call_function_single(cpu,
1411                          __loaded_vmcs_clear, loaded_vmcs, 1);
1412 }
1413
1414 static inline void vpid_sync_vcpu_single(int vpid)
1415 {
1416         if (vpid == 0)
1417                 return;
1418
1419         if (cpu_has_vmx_invvpid_single())
1420                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1421 }
1422
1423 static inline void vpid_sync_vcpu_global(void)
1424 {
1425         if (cpu_has_vmx_invvpid_global())
1426                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1427 }
1428
1429 static inline void vpid_sync_context(int vpid)
1430 {
1431         if (cpu_has_vmx_invvpid_single())
1432                 vpid_sync_vcpu_single(vpid);
1433         else
1434                 vpid_sync_vcpu_global();
1435 }
1436
1437 static inline void ept_sync_global(void)
1438 {
1439         if (cpu_has_vmx_invept_global())
1440                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1441 }
1442
1443 static inline void ept_sync_context(u64 eptp)
1444 {
1445         if (enable_ept) {
1446                 if (cpu_has_vmx_invept_context())
1447                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1448                 else
1449                         ept_sync_global();
1450         }
1451 }
1452
1453 static __always_inline unsigned long vmcs_readl(unsigned long field)
1454 {
1455         unsigned long value;
1456
1457         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1458                       : "=a"(value) : "d"(field) : "cc");
1459         return value;
1460 }
1461
1462 static __always_inline u16 vmcs_read16(unsigned long field)
1463 {
1464         return vmcs_readl(field);
1465 }
1466
1467 static __always_inline u32 vmcs_read32(unsigned long field)
1468 {
1469         return vmcs_readl(field);
1470 }
1471
1472 static __always_inline u64 vmcs_read64(unsigned long field)
1473 {
1474 #ifdef CONFIG_X86_64
1475         return vmcs_readl(field);
1476 #else
1477         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1478 #endif
1479 }
1480
1481 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1482 {
1483         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1484                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1485         dump_stack();
1486 }
1487
1488 static void vmcs_writel(unsigned long field, unsigned long value)
1489 {
1490         u8 error;
1491
1492         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1493                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1494         if (unlikely(error))
1495                 vmwrite_error(field, value);
1496 }
1497
1498 static void vmcs_write16(unsigned long field, u16 value)
1499 {
1500         vmcs_writel(field, value);
1501 }
1502
1503 static void vmcs_write32(unsigned long field, u32 value)
1504 {
1505         vmcs_writel(field, value);
1506 }
1507
1508 static void vmcs_write64(unsigned long field, u64 value)
1509 {
1510         vmcs_writel(field, value);
1511 #ifndef CONFIG_X86_64
1512         asm volatile ("");
1513         vmcs_writel(field+1, value >> 32);
1514 #endif
1515 }
1516
1517 static void vmcs_clear_bits(unsigned long field, u32 mask)
1518 {
1519         vmcs_writel(field, vmcs_readl(field) & ~mask);
1520 }
1521
1522 static void vmcs_set_bits(unsigned long field, u32 mask)
1523 {
1524         vmcs_writel(field, vmcs_readl(field) | mask);
1525 }
1526
1527 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1528 {
1529         vmcs_write32(VM_ENTRY_CONTROLS, val);
1530         vmx->vm_entry_controls_shadow = val;
1531 }
1532
1533 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1534 {
1535         if (vmx->vm_entry_controls_shadow != val)
1536                 vm_entry_controls_init(vmx, val);
1537 }
1538
1539 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1540 {
1541         return vmx->vm_entry_controls_shadow;
1542 }
1543
1544
1545 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1546 {
1547         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1548 }
1549
1550 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1551 {
1552         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1553 }
1554
1555 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1556 {
1557         vmcs_write32(VM_EXIT_CONTROLS, val);
1558         vmx->vm_exit_controls_shadow = val;
1559 }
1560
1561 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1562 {
1563         if (vmx->vm_exit_controls_shadow != val)
1564                 vm_exit_controls_init(vmx, val);
1565 }
1566
1567 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1568 {
1569         return vmx->vm_exit_controls_shadow;
1570 }
1571
1572
1573 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1574 {
1575         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1576 }
1577
1578 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1579 {
1580         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1581 }
1582
1583 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1584 {
1585         vmx->segment_cache.bitmask = 0;
1586 }
1587
1588 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1589                                        unsigned field)
1590 {
1591         bool ret;
1592         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1593
1594         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1595                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1596                 vmx->segment_cache.bitmask = 0;
1597         }
1598         ret = vmx->segment_cache.bitmask & mask;
1599         vmx->segment_cache.bitmask |= mask;
1600         return ret;
1601 }
1602
1603 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1604 {
1605         u16 *p = &vmx->segment_cache.seg[seg].selector;
1606
1607         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1608                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1609         return *p;
1610 }
1611
1612 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1613 {
1614         ulong *p = &vmx->segment_cache.seg[seg].base;
1615
1616         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1617                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1618         return *p;
1619 }
1620
1621 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1622 {
1623         u32 *p = &vmx->segment_cache.seg[seg].limit;
1624
1625         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1626                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1627         return *p;
1628 }
1629
1630 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1631 {
1632         u32 *p = &vmx->segment_cache.seg[seg].ar;
1633
1634         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1635                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1636         return *p;
1637 }
1638
1639 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1640 {
1641         u32 eb;
1642
1643         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1644              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1645         if ((vcpu->guest_debug &
1646              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1647             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1648                 eb |= 1u << BP_VECTOR;
1649         if (to_vmx(vcpu)->rmode.vm86_active)
1650                 eb = ~0;
1651         if (enable_ept)
1652                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1653         if (vcpu->fpu_active)
1654                 eb &= ~(1u << NM_VECTOR);
1655
1656         /* When we are running a nested L2 guest and L1 specified for it a
1657          * certain exception bitmap, we must trap the same exceptions and pass
1658          * them to L1. When running L2, we will only handle the exceptions
1659          * specified above if L1 did not want them.
1660          */
1661         if (is_guest_mode(vcpu))
1662                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1663
1664         vmcs_write32(EXCEPTION_BITMAP, eb);
1665 }
1666
1667 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1668                 unsigned long entry, unsigned long exit)
1669 {
1670         vm_entry_controls_clearbit(vmx, entry);
1671         vm_exit_controls_clearbit(vmx, exit);
1672 }
1673
1674 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1675 {
1676         unsigned i;
1677         struct msr_autoload *m = &vmx->msr_autoload;
1678
1679         switch (msr) {
1680         case MSR_EFER:
1681                 if (cpu_has_load_ia32_efer) {
1682                         clear_atomic_switch_msr_special(vmx,
1683                                         VM_ENTRY_LOAD_IA32_EFER,
1684                                         VM_EXIT_LOAD_IA32_EFER);
1685                         return;
1686                 }
1687                 break;
1688         case MSR_CORE_PERF_GLOBAL_CTRL:
1689                 if (cpu_has_load_perf_global_ctrl) {
1690                         clear_atomic_switch_msr_special(vmx,
1691                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1692                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1693                         return;
1694                 }
1695                 break;
1696         }
1697
1698         for (i = 0; i < m->nr; ++i)
1699                 if (m->guest[i].index == msr)
1700                         break;
1701
1702         if (i == m->nr)
1703                 return;
1704         --m->nr;
1705         m->guest[i] = m->guest[m->nr];
1706         m->host[i] = m->host[m->nr];
1707         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1708         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1709 }
1710
1711 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1712                 unsigned long entry, unsigned long exit,
1713                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1714                 u64 guest_val, u64 host_val)
1715 {
1716         vmcs_write64(guest_val_vmcs, guest_val);
1717         vmcs_write64(host_val_vmcs, host_val);
1718         vm_entry_controls_setbit(vmx, entry);
1719         vm_exit_controls_setbit(vmx, exit);
1720 }
1721
1722 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1723                                   u64 guest_val, u64 host_val)
1724 {
1725         unsigned i;
1726         struct msr_autoload *m = &vmx->msr_autoload;
1727
1728         switch (msr) {
1729         case MSR_EFER:
1730                 if (cpu_has_load_ia32_efer) {
1731                         add_atomic_switch_msr_special(vmx,
1732                                         VM_ENTRY_LOAD_IA32_EFER,
1733                                         VM_EXIT_LOAD_IA32_EFER,
1734                                         GUEST_IA32_EFER,
1735                                         HOST_IA32_EFER,
1736                                         guest_val, host_val);
1737                         return;
1738                 }
1739                 break;
1740         case MSR_CORE_PERF_GLOBAL_CTRL:
1741                 if (cpu_has_load_perf_global_ctrl) {
1742                         add_atomic_switch_msr_special(vmx,
1743                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1744                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1745                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1746                                         HOST_IA32_PERF_GLOBAL_CTRL,
1747                                         guest_val, host_val);
1748                         return;
1749                 }
1750                 break;
1751         }
1752
1753         for (i = 0; i < m->nr; ++i)
1754                 if (m->guest[i].index == msr)
1755                         break;
1756
1757         if (i == NR_AUTOLOAD_MSRS) {
1758                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1759                                 "Can't add msr %x\n", msr);
1760                 return;
1761         } else if (i == m->nr) {
1762                 ++m->nr;
1763                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1764                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1765         }
1766
1767         m->guest[i].index = msr;
1768         m->guest[i].value = guest_val;
1769         m->host[i].index = msr;
1770         m->host[i].value = host_val;
1771 }
1772
1773 static void reload_tss(void)
1774 {
1775         /*
1776          * VT restores TR but not its size.  Useless.
1777          */
1778         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1779         struct desc_struct *descs;
1780
1781         descs = (void *)gdt->address;
1782         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1783         load_TR_desc();
1784 }
1785
1786 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1787 {
1788         u64 guest_efer;
1789         u64 ignore_bits;
1790
1791         guest_efer = vmx->vcpu.arch.efer;
1792
1793         /*
1794          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1795          * outside long mode
1796          */
1797         ignore_bits = EFER_NX | EFER_SCE;
1798 #ifdef CONFIG_X86_64
1799         ignore_bits |= EFER_LMA | EFER_LME;
1800         /* SCE is meaningful only in long mode on Intel */
1801         if (guest_efer & EFER_LMA)
1802                 ignore_bits &= ~(u64)EFER_SCE;
1803 #endif
1804         guest_efer &= ~ignore_bits;
1805         guest_efer |= host_efer & ignore_bits;
1806         vmx->guest_msrs[efer_offset].data = guest_efer;
1807         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1808
1809         clear_atomic_switch_msr(vmx, MSR_EFER);
1810
1811         /*
1812          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1813          * On CPUs that support "load IA32_EFER", always switch EFER
1814          * atomically, since it's faster than switching it manually.
1815          */
1816         if (cpu_has_load_ia32_efer ||
1817             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1818                 guest_efer = vmx->vcpu.arch.efer;
1819                 if (!(guest_efer & EFER_LMA))
1820                         guest_efer &= ~EFER_LME;
1821                 if (guest_efer != host_efer)
1822                         add_atomic_switch_msr(vmx, MSR_EFER,
1823                                               guest_efer, host_efer);
1824                 return false;
1825         }
1826
1827         return true;
1828 }
1829
1830 static unsigned long segment_base(u16 selector)
1831 {
1832         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1833         struct desc_struct *d;
1834         unsigned long table_base;
1835         unsigned long v;
1836
1837         if (!(selector & ~3))
1838                 return 0;
1839
1840         table_base = gdt->address;
1841
1842         if (selector & 4) {           /* from ldt */
1843                 u16 ldt_selector = kvm_read_ldt();
1844
1845                 if (!(ldt_selector & ~3))
1846                         return 0;
1847
1848                 table_base = segment_base(ldt_selector);
1849         }
1850         d = (struct desc_struct *)(table_base + (selector & ~7));
1851         v = get_desc_base(d);
1852 #ifdef CONFIG_X86_64
1853        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1854                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1855 #endif
1856         return v;
1857 }
1858
1859 static inline unsigned long kvm_read_tr_base(void)
1860 {
1861         u16 tr;
1862         asm("str %0" : "=g"(tr));
1863         return segment_base(tr);
1864 }
1865
1866 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1867 {
1868         struct vcpu_vmx *vmx = to_vmx(vcpu);
1869         int i;
1870
1871         if (vmx->host_state.loaded)
1872                 return;
1873
1874         vmx->host_state.loaded = 1;
1875         /*
1876          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1877          * allow segment selectors with cpl > 0 or ti == 1.
1878          */
1879         vmx->host_state.ldt_sel = kvm_read_ldt();
1880         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1881         savesegment(fs, vmx->host_state.fs_sel);
1882         if (!(vmx->host_state.fs_sel & 7)) {
1883                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1884                 vmx->host_state.fs_reload_needed = 0;
1885         } else {
1886                 vmcs_write16(HOST_FS_SELECTOR, 0);
1887                 vmx->host_state.fs_reload_needed = 1;
1888         }
1889         savesegment(gs, vmx->host_state.gs_sel);
1890         if (!(vmx->host_state.gs_sel & 7))
1891                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1892         else {
1893                 vmcs_write16(HOST_GS_SELECTOR, 0);
1894                 vmx->host_state.gs_ldt_reload_needed = 1;
1895         }
1896
1897 #ifdef CONFIG_X86_64
1898         savesegment(ds, vmx->host_state.ds_sel);
1899         savesegment(es, vmx->host_state.es_sel);
1900 #endif
1901
1902 #ifdef CONFIG_X86_64
1903         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1904         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1905 #else
1906         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1907         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1908 #endif
1909
1910 #ifdef CONFIG_X86_64
1911         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1912         if (is_long_mode(&vmx->vcpu))
1913                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1914 #endif
1915         if (boot_cpu_has(X86_FEATURE_MPX))
1916                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1917         for (i = 0; i < vmx->save_nmsrs; ++i)
1918                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1919                                    vmx->guest_msrs[i].data,
1920                                    vmx->guest_msrs[i].mask);
1921 }
1922
1923 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1924 {
1925         if (!vmx->host_state.loaded)
1926                 return;
1927
1928         ++vmx->vcpu.stat.host_state_reload;
1929         vmx->host_state.loaded = 0;
1930 #ifdef CONFIG_X86_64
1931         if (is_long_mode(&vmx->vcpu))
1932                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1933 #endif
1934         if (vmx->host_state.gs_ldt_reload_needed) {
1935                 kvm_load_ldt(vmx->host_state.ldt_sel);
1936 #ifdef CONFIG_X86_64
1937                 load_gs_index(vmx->host_state.gs_sel);
1938 #else
1939                 loadsegment(gs, vmx->host_state.gs_sel);
1940 #endif
1941         }
1942         if (vmx->host_state.fs_reload_needed)
1943                 loadsegment(fs, vmx->host_state.fs_sel);
1944 #ifdef CONFIG_X86_64
1945         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1946                 loadsegment(ds, vmx->host_state.ds_sel);
1947                 loadsegment(es, vmx->host_state.es_sel);
1948         }
1949 #endif
1950         reload_tss();
1951 #ifdef CONFIG_X86_64
1952         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1953 #endif
1954         if (vmx->host_state.msr_host_bndcfgs)
1955                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1956         /*
1957          * If the FPU is not active (through the host task or
1958          * the guest vcpu), then restore the cr0.TS bit.
1959          */
1960         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1961                 stts();
1962         load_gdt(this_cpu_ptr(&host_gdt));
1963 }
1964
1965 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1966 {
1967         preempt_disable();
1968         __vmx_load_host_state(vmx);
1969         preempt_enable();
1970 }
1971
1972 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1973 {
1974         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1975         struct pi_desc old, new;
1976         unsigned int dest;
1977
1978         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1979                 !irq_remapping_cap(IRQ_POSTING_CAP))
1980                 return;
1981
1982         do {
1983                 old.control = new.control = pi_desc->control;
1984
1985                 /*
1986                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1987                  * are two possible cases:
1988                  * 1. After running 'pre_block', context switch
1989                  *    happened. For this case, 'sn' was set in
1990                  *    vmx_vcpu_put(), so we need to clear it here.
1991                  * 2. After running 'pre_block', we were blocked,
1992                  *    and woken up by some other guy. For this case,
1993                  *    we don't need to do anything, 'pi_post_block'
1994                  *    will do everything for us. However, we cannot
1995                  *    check whether it is case #1 or case #2 here
1996                  *    (maybe, not needed), so we also clear sn here,
1997                  *    I think it is not a big deal.
1998                  */
1999                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2000                         if (vcpu->cpu != cpu) {
2001                                 dest = cpu_physical_id(cpu);
2002
2003                                 if (x2apic_enabled())
2004                                         new.ndst = dest;
2005                                 else
2006                                         new.ndst = (dest << 8) & 0xFF00;
2007                         }
2008
2009                         /* set 'NV' to 'notification vector' */
2010                         new.nv = POSTED_INTR_VECTOR;
2011                 }
2012
2013                 /* Allow posting non-urgent interrupts */
2014                 new.sn = 0;
2015         } while (cmpxchg(&pi_desc->control, old.control,
2016                         new.control) != old.control);
2017 }
2018 /*
2019  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2020  * vcpu mutex is already taken.
2021  */
2022 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2023 {
2024         struct vcpu_vmx *vmx = to_vmx(vcpu);
2025         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2026
2027         if (!vmm_exclusive)
2028                 kvm_cpu_vmxon(phys_addr);
2029         else if (vmx->loaded_vmcs->cpu != cpu)
2030                 loaded_vmcs_clear(vmx->loaded_vmcs);
2031
2032         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2033                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2034                 vmcs_load(vmx->loaded_vmcs->vmcs);
2035         }
2036
2037         if (vmx->loaded_vmcs->cpu != cpu) {
2038                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2039                 unsigned long sysenter_esp;
2040
2041                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2042                 local_irq_disable();
2043                 crash_disable_local_vmclear(cpu);
2044
2045                 /*
2046                  * Read loaded_vmcs->cpu should be before fetching
2047                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2048                  * See the comments in __loaded_vmcs_clear().
2049                  */
2050                 smp_rmb();
2051
2052                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2053                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2054                 crash_enable_local_vmclear(cpu);
2055                 local_irq_enable();
2056
2057                 /*
2058                  * Linux uses per-cpu TSS and GDT, so set these when switching
2059                  * processors.
2060                  */
2061                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2062                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2063
2064                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2065                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2066
2067                 vmx->loaded_vmcs->cpu = cpu;
2068         }
2069
2070         /* Setup TSC multiplier */
2071         if (kvm_has_tsc_control &&
2072             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2073                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2074                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2075         }
2076
2077         vmx_vcpu_pi_load(vcpu, cpu);
2078 }
2079
2080 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2081 {
2082         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2083
2084         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2085                 !irq_remapping_cap(IRQ_POSTING_CAP))
2086                 return;
2087
2088         /* Set SN when the vCPU is preempted */
2089         if (vcpu->preempted)
2090                 pi_set_sn(pi_desc);
2091 }
2092
2093 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2094 {
2095         vmx_vcpu_pi_put(vcpu);
2096
2097         __vmx_load_host_state(to_vmx(vcpu));
2098         if (!vmm_exclusive) {
2099                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2100                 vcpu->cpu = -1;
2101                 kvm_cpu_vmxoff();
2102         }
2103 }
2104
2105 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2106 {
2107         ulong cr0;
2108
2109         if (vcpu->fpu_active)
2110                 return;
2111         vcpu->fpu_active = 1;
2112         cr0 = vmcs_readl(GUEST_CR0);
2113         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2114         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2115         vmcs_writel(GUEST_CR0, cr0);
2116         update_exception_bitmap(vcpu);
2117         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2118         if (is_guest_mode(vcpu))
2119                 vcpu->arch.cr0_guest_owned_bits &=
2120                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2121         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2122 }
2123
2124 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2125
2126 /*
2127  * Return the cr0 value that a nested guest would read. This is a combination
2128  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2129  * its hypervisor (cr0_read_shadow).
2130  */
2131 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2132 {
2133         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2134                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2135 }
2136 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2137 {
2138         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2139                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2140 }
2141
2142 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2143 {
2144         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2145          * set this *before* calling this function.
2146          */
2147         vmx_decache_cr0_guest_bits(vcpu);
2148         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2149         update_exception_bitmap(vcpu);
2150         vcpu->arch.cr0_guest_owned_bits = 0;
2151         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2152         if (is_guest_mode(vcpu)) {
2153                 /*
2154                  * L1's specified read shadow might not contain the TS bit,
2155                  * so now that we turned on shadowing of this bit, we need to
2156                  * set this bit of the shadow. Like in nested_vmx_run we need
2157                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2158                  * up-to-date here because we just decached cr0.TS (and we'll
2159                  * only update vmcs12->guest_cr0 on nested exit).
2160                  */
2161                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2162                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2163                         (vcpu->arch.cr0 & X86_CR0_TS);
2164                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2165         } else
2166                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2167 }
2168
2169 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2170 {
2171         unsigned long rflags, save_rflags;
2172
2173         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2174                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2175                 rflags = vmcs_readl(GUEST_RFLAGS);
2176                 if (to_vmx(vcpu)->rmode.vm86_active) {
2177                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2178                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2179                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2180                 }
2181                 to_vmx(vcpu)->rflags = rflags;
2182         }
2183         return to_vmx(vcpu)->rflags;
2184 }
2185
2186 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2187 {
2188         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2189         to_vmx(vcpu)->rflags = rflags;
2190         if (to_vmx(vcpu)->rmode.vm86_active) {
2191                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2192                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2193         }
2194         vmcs_writel(GUEST_RFLAGS, rflags);
2195 }
2196
2197 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2198 {
2199         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2200         int ret = 0;
2201
2202         if (interruptibility & GUEST_INTR_STATE_STI)
2203                 ret |= KVM_X86_SHADOW_INT_STI;
2204         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2205                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2206
2207         return ret;
2208 }
2209
2210 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2211 {
2212         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2213         u32 interruptibility = interruptibility_old;
2214
2215         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2216
2217         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2218                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2219         else if (mask & KVM_X86_SHADOW_INT_STI)
2220                 interruptibility |= GUEST_INTR_STATE_STI;
2221
2222         if ((interruptibility != interruptibility_old))
2223                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2224 }
2225
2226 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2227 {
2228         unsigned long rip;
2229
2230         rip = kvm_rip_read(vcpu);
2231         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2232         kvm_rip_write(vcpu, rip);
2233
2234         /* skipping an emulated instruction also counts */
2235         vmx_set_interrupt_shadow(vcpu, 0);
2236 }
2237
2238 /*
2239  * KVM wants to inject page-faults which it got to the guest. This function
2240  * checks whether in a nested guest, we need to inject them to L1 or L2.
2241  */
2242 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2243 {
2244         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2245
2246         if (!(vmcs12->exception_bitmap & (1u << nr)))
2247                 return 0;
2248
2249         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2250                           vmcs_read32(VM_EXIT_INTR_INFO),
2251                           vmcs_readl(EXIT_QUALIFICATION));
2252         return 1;
2253 }
2254
2255 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2256                                 bool has_error_code, u32 error_code,
2257                                 bool reinject)
2258 {
2259         struct vcpu_vmx *vmx = to_vmx(vcpu);
2260         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2261
2262         if (!reinject && is_guest_mode(vcpu) &&
2263             nested_vmx_check_exception(vcpu, nr))
2264                 return;
2265
2266         if (has_error_code) {
2267                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2268                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2269         }
2270
2271         if (vmx->rmode.vm86_active) {
2272                 int inc_eip = 0;
2273                 if (kvm_exception_is_soft(nr))
2274                         inc_eip = vcpu->arch.event_exit_inst_len;
2275                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2276                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2277                 return;
2278         }
2279
2280         if (kvm_exception_is_soft(nr)) {
2281                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2282                              vmx->vcpu.arch.event_exit_inst_len);
2283                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2284         } else
2285                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2286
2287         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2288 }
2289
2290 static bool vmx_rdtscp_supported(void)
2291 {
2292         return cpu_has_vmx_rdtscp();
2293 }
2294
2295 static bool vmx_invpcid_supported(void)
2296 {
2297         return cpu_has_vmx_invpcid() && enable_ept;
2298 }
2299
2300 /*
2301  * Swap MSR entry in host/guest MSR entry array.
2302  */
2303 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2304 {
2305         struct shared_msr_entry tmp;
2306
2307         tmp = vmx->guest_msrs[to];
2308         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2309         vmx->guest_msrs[from] = tmp;
2310 }
2311
2312 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2313 {
2314         unsigned long *msr_bitmap;
2315
2316         if (is_guest_mode(vcpu))
2317                 msr_bitmap = vmx_msr_bitmap_nested;
2318         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2319                 if (is_long_mode(vcpu))
2320                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2321                 else
2322                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2323         } else {
2324                 if (is_long_mode(vcpu))
2325                         msr_bitmap = vmx_msr_bitmap_longmode;
2326                 else
2327                         msr_bitmap = vmx_msr_bitmap_legacy;
2328         }
2329
2330         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2331 }
2332
2333 /*
2334  * Set up the vmcs to automatically save and restore system
2335  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2336  * mode, as fiddling with msrs is very expensive.
2337  */
2338 static void setup_msrs(struct vcpu_vmx *vmx)
2339 {
2340         int save_nmsrs, index;
2341
2342         save_nmsrs = 0;
2343 #ifdef CONFIG_X86_64
2344         if (is_long_mode(&vmx->vcpu)) {
2345                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2346                 if (index >= 0)
2347                         move_msr_up(vmx, index, save_nmsrs++);
2348                 index = __find_msr_index(vmx, MSR_LSTAR);
2349                 if (index >= 0)
2350                         move_msr_up(vmx, index, save_nmsrs++);
2351                 index = __find_msr_index(vmx, MSR_CSTAR);
2352                 if (index >= 0)
2353                         move_msr_up(vmx, index, save_nmsrs++);
2354                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2355                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2356                         move_msr_up(vmx, index, save_nmsrs++);
2357                 /*
2358                  * MSR_STAR is only needed on long mode guests, and only
2359                  * if efer.sce is enabled.
2360                  */
2361                 index = __find_msr_index(vmx, MSR_STAR);
2362                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2363                         move_msr_up(vmx, index, save_nmsrs++);
2364         }
2365 #endif
2366         index = __find_msr_index(vmx, MSR_EFER);
2367         if (index >= 0 && update_transition_efer(vmx, index))
2368                 move_msr_up(vmx, index, save_nmsrs++);
2369
2370         vmx->save_nmsrs = save_nmsrs;
2371
2372         if (cpu_has_vmx_msr_bitmap())
2373                 vmx_set_msr_bitmap(&vmx->vcpu);
2374 }
2375
2376 /*
2377  * reads and returns guest's timestamp counter "register"
2378  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2379  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2380  */
2381 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2382 {
2383         u64 host_tsc, tsc_offset;
2384
2385         host_tsc = rdtsc();
2386         tsc_offset = vmcs_read64(TSC_OFFSET);
2387         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2388 }
2389
2390 /*
2391  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2392  * counter, even if a nested guest (L2) is currently running.
2393  */
2394 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2395 {
2396         u64 tsc_offset;
2397
2398         tsc_offset = is_guest_mode(vcpu) ?
2399                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2400                 vmcs_read64(TSC_OFFSET);
2401         return host_tsc + tsc_offset;
2402 }
2403
2404 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2405 {
2406         return vmcs_read64(TSC_OFFSET);
2407 }
2408
2409 /*
2410  * writes 'offset' into guest's timestamp counter offset register
2411  */
2412 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2413 {
2414         if (is_guest_mode(vcpu)) {
2415                 /*
2416                  * We're here if L1 chose not to trap WRMSR to TSC. According
2417                  * to the spec, this should set L1's TSC; The offset that L1
2418                  * set for L2 remains unchanged, and still needs to be added
2419                  * to the newly set TSC to get L2's TSC.
2420                  */
2421                 struct vmcs12 *vmcs12;
2422                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2423                 /* recalculate vmcs02.TSC_OFFSET: */
2424                 vmcs12 = get_vmcs12(vcpu);
2425                 vmcs_write64(TSC_OFFSET, offset +
2426                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2427                          vmcs12->tsc_offset : 0));
2428         } else {
2429                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2430                                            vmcs_read64(TSC_OFFSET), offset);
2431                 vmcs_write64(TSC_OFFSET, offset);
2432         }
2433 }
2434
2435 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2436 {
2437         u64 offset = vmcs_read64(TSC_OFFSET);
2438
2439         vmcs_write64(TSC_OFFSET, offset + adjustment);
2440         if (is_guest_mode(vcpu)) {
2441                 /* Even when running L2, the adjustment needs to apply to L1 */
2442                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2443         } else
2444                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2445                                            offset + adjustment);
2446 }
2447
2448 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2449 {
2450         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2451         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2452 }
2453
2454 /*
2455  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2456  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2457  * all guests if the "nested" module option is off, and can also be disabled
2458  * for a single guest by disabling its VMX cpuid bit.
2459  */
2460 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2461 {
2462         return nested && guest_cpuid_has_vmx(vcpu);
2463 }
2464
2465 /*
2466  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2467  * returned for the various VMX controls MSRs when nested VMX is enabled.
2468  * The same values should also be used to verify that vmcs12 control fields are
2469  * valid during nested entry from L1 to L2.
2470  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2471  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2472  * bit in the high half is on if the corresponding bit in the control field
2473  * may be on. See also vmx_control_verify().
2474  */
2475 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2476 {
2477         /*
2478          * Note that as a general rule, the high half of the MSRs (bits in
2479          * the control fields which may be 1) should be initialized by the
2480          * intersection of the underlying hardware's MSR (i.e., features which
2481          * can be supported) and the list of features we want to expose -
2482          * because they are known to be properly supported in our code.
2483          * Also, usually, the low half of the MSRs (bits which must be 1) can
2484          * be set to 0, meaning that L1 may turn off any of these bits. The
2485          * reason is that if one of these bits is necessary, it will appear
2486          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2487          * fields of vmcs01 and vmcs02, will turn these bits off - and
2488          * nested_vmx_exit_handled() will not pass related exits to L1.
2489          * These rules have exceptions below.
2490          */
2491
2492         /* pin-based controls */
2493         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2494                 vmx->nested.nested_vmx_pinbased_ctls_low,
2495                 vmx->nested.nested_vmx_pinbased_ctls_high);
2496         vmx->nested.nested_vmx_pinbased_ctls_low |=
2497                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2498         vmx->nested.nested_vmx_pinbased_ctls_high &=
2499                 PIN_BASED_EXT_INTR_MASK |
2500                 PIN_BASED_NMI_EXITING |
2501                 PIN_BASED_VIRTUAL_NMIS;
2502         vmx->nested.nested_vmx_pinbased_ctls_high |=
2503                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2504                 PIN_BASED_VMX_PREEMPTION_TIMER;
2505         if (vmx_cpu_uses_apicv(&vmx->vcpu))
2506                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2507                         PIN_BASED_POSTED_INTR;
2508
2509         /* exit controls */
2510         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2511                 vmx->nested.nested_vmx_exit_ctls_low,
2512                 vmx->nested.nested_vmx_exit_ctls_high);
2513         vmx->nested.nested_vmx_exit_ctls_low =
2514                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2515
2516         vmx->nested.nested_vmx_exit_ctls_high &=
2517 #ifdef CONFIG_X86_64
2518                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2519 #endif
2520                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2521         vmx->nested.nested_vmx_exit_ctls_high |=
2522                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2523                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2524                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2525
2526         if (vmx_mpx_supported())
2527                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2528
2529         /* We support free control of debug control saving. */
2530         vmx->nested.nested_vmx_true_exit_ctls_low =
2531                 vmx->nested.nested_vmx_exit_ctls_low &
2532                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2533
2534         /* entry controls */
2535         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2536                 vmx->nested.nested_vmx_entry_ctls_low,
2537                 vmx->nested.nested_vmx_entry_ctls_high);
2538         vmx->nested.nested_vmx_entry_ctls_low =
2539                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2540         vmx->nested.nested_vmx_entry_ctls_high &=
2541 #ifdef CONFIG_X86_64
2542                 VM_ENTRY_IA32E_MODE |
2543 #endif
2544                 VM_ENTRY_LOAD_IA32_PAT;
2545         vmx->nested.nested_vmx_entry_ctls_high |=
2546                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2547         if (vmx_mpx_supported())
2548                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2549
2550         /* We support free control of debug control loading. */
2551         vmx->nested.nested_vmx_true_entry_ctls_low =
2552                 vmx->nested.nested_vmx_entry_ctls_low &
2553                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2554
2555         /* cpu-based controls */
2556         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2557                 vmx->nested.nested_vmx_procbased_ctls_low,
2558                 vmx->nested.nested_vmx_procbased_ctls_high);
2559         vmx->nested.nested_vmx_procbased_ctls_low =
2560                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2561         vmx->nested.nested_vmx_procbased_ctls_high &=
2562                 CPU_BASED_VIRTUAL_INTR_PENDING |
2563                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2564                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2565                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2566                 CPU_BASED_CR3_STORE_EXITING |
2567 #ifdef CONFIG_X86_64
2568                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2569 #endif
2570                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2571                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2572                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2573                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2574                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2575         /*
2576          * We can allow some features even when not supported by the
2577          * hardware. For example, L1 can specify an MSR bitmap - and we
2578          * can use it to avoid exits to L1 - even when L0 runs L2
2579          * without MSR bitmaps.
2580          */
2581         vmx->nested.nested_vmx_procbased_ctls_high |=
2582                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2583                 CPU_BASED_USE_MSR_BITMAPS;
2584
2585         /* We support free control of CR3 access interception. */
2586         vmx->nested.nested_vmx_true_procbased_ctls_low =
2587                 vmx->nested.nested_vmx_procbased_ctls_low &
2588                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2589
2590         /* secondary cpu-based controls */
2591         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2592                 vmx->nested.nested_vmx_secondary_ctls_low,
2593                 vmx->nested.nested_vmx_secondary_ctls_high);
2594         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2595         vmx->nested.nested_vmx_secondary_ctls_high &=
2596                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2597                 SECONDARY_EXEC_RDTSCP |
2598                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2599                 SECONDARY_EXEC_ENABLE_VPID |
2600                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2601                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2602                 SECONDARY_EXEC_WBINVD_EXITING |
2603                 SECONDARY_EXEC_XSAVES |
2604                 SECONDARY_EXEC_PCOMMIT;
2605
2606         if (enable_ept) {
2607                 /* nested EPT: emulate EPT also to L1 */
2608                 vmx->nested.nested_vmx_secondary_ctls_high |=
2609                         SECONDARY_EXEC_ENABLE_EPT;
2610                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2611                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2612                          VMX_EPT_INVEPT_BIT;
2613                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2614                 /*
2615                  * For nested guests, we don't do anything specific
2616                  * for single context invalidation. Hence, only advertise
2617                  * support for global context invalidation.
2618                  */
2619                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2620         } else
2621                 vmx->nested.nested_vmx_ept_caps = 0;
2622
2623         if (enable_vpid)
2624                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2625                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2626         else
2627                 vmx->nested.nested_vmx_vpid_caps = 0;
2628
2629         if (enable_unrestricted_guest)
2630                 vmx->nested.nested_vmx_secondary_ctls_high |=
2631                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2632
2633         /* miscellaneous data */
2634         rdmsr(MSR_IA32_VMX_MISC,
2635                 vmx->nested.nested_vmx_misc_low,
2636                 vmx->nested.nested_vmx_misc_high);
2637         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2638         vmx->nested.nested_vmx_misc_low |=
2639                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2640                 VMX_MISC_ACTIVITY_HLT;
2641         vmx->nested.nested_vmx_misc_high = 0;
2642 }
2643
2644 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2645 {
2646         /*
2647          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2648          */
2649         return ((control & high) | low) == control;
2650 }
2651
2652 static inline u64 vmx_control_msr(u32 low, u32 high)
2653 {
2654         return low | ((u64)high << 32);
2655 }
2656
2657 /* Returns 0 on success, non-0 otherwise. */
2658 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2659 {
2660         struct vcpu_vmx *vmx = to_vmx(vcpu);
2661
2662         switch (msr_index) {
2663         case MSR_IA32_VMX_BASIC:
2664                 /*
2665                  * This MSR reports some information about VMX support. We
2666                  * should return information about the VMX we emulate for the
2667                  * guest, and the VMCS structure we give it - not about the
2668                  * VMX support of the underlying hardware.
2669                  */
2670                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2671                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2672                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2673                 break;
2674         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2675         case MSR_IA32_VMX_PINBASED_CTLS:
2676                 *pdata = vmx_control_msr(
2677                         vmx->nested.nested_vmx_pinbased_ctls_low,
2678                         vmx->nested.nested_vmx_pinbased_ctls_high);
2679                 break;
2680         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2681                 *pdata = vmx_control_msr(
2682                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2683                         vmx->nested.nested_vmx_procbased_ctls_high);
2684                 break;
2685         case MSR_IA32_VMX_PROCBASED_CTLS:
2686                 *pdata = vmx_control_msr(
2687                         vmx->nested.nested_vmx_procbased_ctls_low,
2688                         vmx->nested.nested_vmx_procbased_ctls_high);
2689                 break;
2690         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2691                 *pdata = vmx_control_msr(
2692                         vmx->nested.nested_vmx_true_exit_ctls_low,
2693                         vmx->nested.nested_vmx_exit_ctls_high);
2694                 break;
2695         case MSR_IA32_VMX_EXIT_CTLS:
2696                 *pdata = vmx_control_msr(
2697                         vmx->nested.nested_vmx_exit_ctls_low,
2698                         vmx->nested.nested_vmx_exit_ctls_high);
2699                 break;
2700         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2701                 *pdata = vmx_control_msr(
2702                         vmx->nested.nested_vmx_true_entry_ctls_low,
2703                         vmx->nested.nested_vmx_entry_ctls_high);
2704                 break;
2705         case MSR_IA32_VMX_ENTRY_CTLS:
2706                 *pdata = vmx_control_msr(
2707                         vmx->nested.nested_vmx_entry_ctls_low,
2708                         vmx->nested.nested_vmx_entry_ctls_high);
2709                 break;
2710         case MSR_IA32_VMX_MISC:
2711                 *pdata = vmx_control_msr(
2712                         vmx->nested.nested_vmx_misc_low,
2713                         vmx->nested.nested_vmx_misc_high);
2714                 break;
2715         /*
2716          * These MSRs specify bits which the guest must keep fixed (on or off)
2717          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2718          * We picked the standard core2 setting.
2719          */
2720 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2721 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2722         case MSR_IA32_VMX_CR0_FIXED0:
2723                 *pdata = VMXON_CR0_ALWAYSON;
2724                 break;
2725         case MSR_IA32_VMX_CR0_FIXED1:
2726                 *pdata = -1ULL;
2727                 break;
2728         case MSR_IA32_VMX_CR4_FIXED0:
2729                 *pdata = VMXON_CR4_ALWAYSON;
2730                 break;
2731         case MSR_IA32_VMX_CR4_FIXED1:
2732                 *pdata = -1ULL;
2733                 break;
2734         case MSR_IA32_VMX_VMCS_ENUM:
2735                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2736                 break;
2737         case MSR_IA32_VMX_PROCBASED_CTLS2:
2738                 *pdata = vmx_control_msr(
2739                         vmx->nested.nested_vmx_secondary_ctls_low,
2740                         vmx->nested.nested_vmx_secondary_ctls_high);
2741                 break;
2742         case MSR_IA32_VMX_EPT_VPID_CAP:
2743                 /* Currently, no nested vpid support */
2744                 *pdata = vmx->nested.nested_vmx_ept_caps |
2745                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2746                 break;
2747         default:
2748                 return 1;
2749         }
2750
2751         return 0;
2752 }
2753
2754 /*
2755  * Reads an msr value (of 'msr_index') into 'pdata'.
2756  * Returns 0 on success, non-0 otherwise.
2757  * Assumes vcpu_load() was already called.
2758  */
2759 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2760 {
2761         struct shared_msr_entry *msr;
2762
2763         switch (msr_info->index) {
2764 #ifdef CONFIG_X86_64
2765         case MSR_FS_BASE:
2766                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2767                 break;
2768         case MSR_GS_BASE:
2769                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2770                 break;
2771         case MSR_KERNEL_GS_BASE:
2772                 vmx_load_host_state(to_vmx(vcpu));
2773                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2774                 break;
2775 #endif
2776         case MSR_EFER:
2777                 return kvm_get_msr_common(vcpu, msr_info);
2778         case MSR_IA32_TSC:
2779                 msr_info->data = guest_read_tsc(vcpu);
2780                 break;
2781         case MSR_IA32_SYSENTER_CS:
2782                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2783                 break;
2784         case MSR_IA32_SYSENTER_EIP:
2785                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2786                 break;
2787         case MSR_IA32_SYSENTER_ESP:
2788                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2789                 break;
2790         case MSR_IA32_BNDCFGS:
2791                 if (!vmx_mpx_supported())
2792                         return 1;
2793                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2794                 break;
2795         case MSR_IA32_FEATURE_CONTROL:
2796                 if (!nested_vmx_allowed(vcpu))
2797                         return 1;
2798                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2799                 break;
2800         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2801                 if (!nested_vmx_allowed(vcpu))
2802                         return 1;
2803                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2804         case MSR_IA32_XSS:
2805                 if (!vmx_xsaves_supported())
2806                         return 1;
2807                 msr_info->data = vcpu->arch.ia32_xss;
2808                 break;
2809         case MSR_TSC_AUX:
2810                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2811                         return 1;
2812                 /* Otherwise falls through */
2813         default:
2814                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2815                 if (msr) {
2816                         msr_info->data = msr->data;
2817                         break;
2818                 }
2819                 return kvm_get_msr_common(vcpu, msr_info);
2820         }
2821
2822         return 0;
2823 }
2824
2825 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2826
2827 /*
2828  * Writes msr value into into the appropriate "register".
2829  * Returns 0 on success, non-0 otherwise.
2830  * Assumes vcpu_load() was already called.
2831  */
2832 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2833 {
2834         struct vcpu_vmx *vmx = to_vmx(vcpu);
2835         struct shared_msr_entry *msr;
2836         int ret = 0;
2837         u32 msr_index = msr_info->index;
2838         u64 data = msr_info->data;
2839
2840         switch (msr_index) {
2841         case MSR_EFER:
2842                 ret = kvm_set_msr_common(vcpu, msr_info);
2843                 break;
2844 #ifdef CONFIG_X86_64
2845         case MSR_FS_BASE:
2846                 vmx_segment_cache_clear(vmx);
2847                 vmcs_writel(GUEST_FS_BASE, data);
2848                 break;
2849         case MSR_GS_BASE:
2850                 vmx_segment_cache_clear(vmx);
2851                 vmcs_writel(GUEST_GS_BASE, data);
2852                 break;
2853         case MSR_KERNEL_GS_BASE:
2854                 vmx_load_host_state(vmx);
2855                 vmx->msr_guest_kernel_gs_base = data;
2856                 break;
2857 #endif
2858         case MSR_IA32_SYSENTER_CS:
2859                 vmcs_write32(GUEST_SYSENTER_CS, data);
2860                 break;
2861         case MSR_IA32_SYSENTER_EIP:
2862                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2863                 break;
2864         case MSR_IA32_SYSENTER_ESP:
2865                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2866                 break;
2867         case MSR_IA32_BNDCFGS:
2868                 if (!vmx_mpx_supported())
2869                         return 1;
2870                 vmcs_write64(GUEST_BNDCFGS, data);
2871                 break;
2872         case MSR_IA32_TSC:
2873                 kvm_write_tsc(vcpu, msr_info);
2874                 break;
2875         case MSR_IA32_CR_PAT:
2876                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2877                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2878                                 return 1;
2879                         vmcs_write64(GUEST_IA32_PAT, data);
2880                         vcpu->arch.pat = data;
2881                         break;
2882                 }
2883                 ret = kvm_set_msr_common(vcpu, msr_info);
2884                 break;
2885         case MSR_IA32_TSC_ADJUST:
2886                 ret = kvm_set_msr_common(vcpu, msr_info);
2887                 break;
2888         case MSR_IA32_FEATURE_CONTROL:
2889                 if (!nested_vmx_allowed(vcpu) ||
2890                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2891                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2892                         return 1;
2893                 vmx->nested.msr_ia32_feature_control = data;
2894                 if (msr_info->host_initiated && data == 0)
2895                         vmx_leave_nested(vcpu);
2896                 break;
2897         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2898                 return 1; /* they are read-only */
2899         case MSR_IA32_XSS:
2900                 if (!vmx_xsaves_supported())
2901                         return 1;
2902                 /*
2903                  * The only supported bit as of Skylake is bit 8, but
2904                  * it is not supported on KVM.
2905                  */
2906                 if (data != 0)
2907                         return 1;
2908                 vcpu->arch.ia32_xss = data;
2909                 if (vcpu->arch.ia32_xss != host_xss)
2910                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2911                                 vcpu->arch.ia32_xss, host_xss);
2912                 else
2913                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2914                 break;
2915         case MSR_TSC_AUX:
2916                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2917                         return 1;
2918                 /* Check reserved bit, higher 32 bits should be zero */
2919                 if ((data >> 32) != 0)
2920                         return 1;
2921                 /* Otherwise falls through */
2922         default:
2923                 msr = find_msr_entry(vmx, msr_index);
2924                 if (msr) {
2925                         u64 old_msr_data = msr->data;
2926                         msr->data = data;
2927                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2928                                 preempt_disable();
2929                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2930                                                          msr->mask);
2931                                 preempt_enable();
2932                                 if (ret)
2933                                         msr->data = old_msr_data;
2934                         }
2935                         break;
2936                 }
2937                 ret = kvm_set_msr_common(vcpu, msr_info);
2938         }
2939
2940         return ret;
2941 }
2942
2943 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2944 {
2945         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2946         switch (reg) {
2947         case VCPU_REGS_RSP:
2948                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2949                 break;
2950         case VCPU_REGS_RIP:
2951                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2952                 break;
2953         case VCPU_EXREG_PDPTR:
2954                 if (enable_ept)
2955                         ept_save_pdptrs(vcpu);
2956                 break;
2957         default:
2958                 break;
2959         }
2960 }
2961
2962 static __init int cpu_has_kvm_support(void)
2963 {
2964         return cpu_has_vmx();
2965 }
2966
2967 static __init int vmx_disabled_by_bios(void)
2968 {
2969         u64 msr;
2970
2971         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2972         if (msr & FEATURE_CONTROL_LOCKED) {
2973                 /* launched w/ TXT and VMX disabled */
2974                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2975                         && tboot_enabled())
2976                         return 1;
2977                 /* launched w/o TXT and VMX only enabled w/ TXT */
2978                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2979                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2980                         && !tboot_enabled()) {
2981                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2982                                 "activate TXT before enabling KVM\n");
2983                         return 1;
2984                 }
2985                 /* launched w/o TXT and VMX disabled */
2986                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2987                         && !tboot_enabled())
2988                         return 1;
2989         }
2990
2991         return 0;
2992 }
2993
2994 static void kvm_cpu_vmxon(u64 addr)
2995 {
2996         asm volatile (ASM_VMX_VMXON_RAX
2997                         : : "a"(&addr), "m"(addr)
2998                         : "memory", "cc");
2999 }
3000
3001 static int hardware_enable(void)
3002 {
3003         int cpu = raw_smp_processor_id();
3004         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3005         u64 old, test_bits;
3006
3007         if (cr4_read_shadow() & X86_CR4_VMXE)
3008                 return -EBUSY;
3009
3010         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3011         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3012         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3013
3014         /*
3015          * Now we can enable the vmclear operation in kdump
3016          * since the loaded_vmcss_on_cpu list on this cpu
3017          * has been initialized.
3018          *
3019          * Though the cpu is not in VMX operation now, there
3020          * is no problem to enable the vmclear operation
3021          * for the loaded_vmcss_on_cpu list is empty!
3022          */
3023         crash_enable_local_vmclear(cpu);
3024
3025         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3026
3027         test_bits = FEATURE_CONTROL_LOCKED;
3028         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3029         if (tboot_enabled())
3030                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3031
3032         if ((old & test_bits) != test_bits) {
3033                 /* enable and lock */
3034                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3035         }
3036         cr4_set_bits(X86_CR4_VMXE);
3037
3038         if (vmm_exclusive) {
3039                 kvm_cpu_vmxon(phys_addr);
3040                 ept_sync_global();
3041         }
3042
3043         native_store_gdt(this_cpu_ptr(&host_gdt));
3044
3045         return 0;
3046 }
3047
3048 static void vmclear_local_loaded_vmcss(void)
3049 {
3050         int cpu = raw_smp_processor_id();
3051         struct loaded_vmcs *v, *n;
3052
3053         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3054                                  loaded_vmcss_on_cpu_link)
3055                 __loaded_vmcs_clear(v);
3056 }
3057
3058
3059 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3060  * tricks.
3061  */
3062 static void kvm_cpu_vmxoff(void)
3063 {
3064         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3065 }
3066
3067 static void hardware_disable(void)
3068 {
3069         if (vmm_exclusive) {
3070                 vmclear_local_loaded_vmcss();
3071                 kvm_cpu_vmxoff();
3072         }
3073         cr4_clear_bits(X86_CR4_VMXE);
3074 }
3075
3076 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3077                                       u32 msr, u32 *result)
3078 {
3079         u32 vmx_msr_low, vmx_msr_high;
3080         u32 ctl = ctl_min | ctl_opt;
3081
3082         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3083
3084         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3085         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3086
3087         /* Ensure minimum (required) set of control bits are supported. */
3088         if (ctl_min & ~ctl)
3089                 return -EIO;
3090
3091         *result = ctl;
3092         return 0;
3093 }
3094
3095 static __init bool allow_1_setting(u32 msr, u32 ctl)
3096 {
3097         u32 vmx_msr_low, vmx_msr_high;
3098
3099         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3100         return vmx_msr_high & ctl;
3101 }
3102
3103 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3104 {
3105         u32 vmx_msr_low, vmx_msr_high;
3106         u32 min, opt, min2, opt2;
3107         u32 _pin_based_exec_control = 0;
3108         u32 _cpu_based_exec_control = 0;
3109         u32 _cpu_based_2nd_exec_control = 0;
3110         u32 _vmexit_control = 0;
3111         u32 _vmentry_control = 0;
3112
3113         min = CPU_BASED_HLT_EXITING |
3114 #ifdef CONFIG_X86_64
3115               CPU_BASED_CR8_LOAD_EXITING |
3116               CPU_BASED_CR8_STORE_EXITING |
3117 #endif
3118               CPU_BASED_CR3_LOAD_EXITING |
3119               CPU_BASED_CR3_STORE_EXITING |
3120               CPU_BASED_USE_IO_BITMAPS |
3121               CPU_BASED_MOV_DR_EXITING |
3122               CPU_BASED_USE_TSC_OFFSETING |
3123               CPU_BASED_MWAIT_EXITING |
3124               CPU_BASED_MONITOR_EXITING |
3125               CPU_BASED_INVLPG_EXITING |
3126               CPU_BASED_RDPMC_EXITING;
3127
3128         opt = CPU_BASED_TPR_SHADOW |
3129               CPU_BASED_USE_MSR_BITMAPS |
3130               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3131         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3132                                 &_cpu_based_exec_control) < 0)
3133                 return -EIO;
3134 #ifdef CONFIG_X86_64
3135         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3136                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3137                                            ~CPU_BASED_CR8_STORE_EXITING;
3138 #endif
3139         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3140                 min2 = 0;
3141                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3142                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3143                         SECONDARY_EXEC_WBINVD_EXITING |
3144                         SECONDARY_EXEC_ENABLE_VPID |
3145                         SECONDARY_EXEC_ENABLE_EPT |
3146                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3147                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3148                         SECONDARY_EXEC_RDTSCP |
3149                         SECONDARY_EXEC_ENABLE_INVPCID |
3150                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3151                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3152                         SECONDARY_EXEC_SHADOW_VMCS |
3153                         SECONDARY_EXEC_XSAVES |
3154                         SECONDARY_EXEC_ENABLE_PML |
3155                         SECONDARY_EXEC_PCOMMIT |
3156                         SECONDARY_EXEC_TSC_SCALING;
3157                 if (adjust_vmx_controls(min2, opt2,
3158                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3159                                         &_cpu_based_2nd_exec_control) < 0)
3160                         return -EIO;
3161         }
3162 #ifndef CONFIG_X86_64
3163         if (!(_cpu_based_2nd_exec_control &
3164                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3165                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3166 #endif
3167
3168         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3169                 _cpu_based_2nd_exec_control &= ~(
3170                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3171                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3172                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3173
3174         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3175                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3176                    enabled */
3177                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3178                                              CPU_BASED_CR3_STORE_EXITING |
3179                                              CPU_BASED_INVLPG_EXITING);
3180                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3181                       vmx_capability.ept, vmx_capability.vpid);
3182         }
3183
3184         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3185 #ifdef CONFIG_X86_64
3186         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3187 #endif
3188         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3189                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3190         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3191                                 &_vmexit_control) < 0)
3192                 return -EIO;
3193
3194         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3195         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3196         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3197                                 &_pin_based_exec_control) < 0)
3198                 return -EIO;
3199
3200         if (!(_cpu_based_2nd_exec_control &
3201                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3202                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3203                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3204
3205         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3206         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3207         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3208                                 &_vmentry_control) < 0)
3209                 return -EIO;
3210
3211         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3212
3213         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3214         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3215                 return -EIO;
3216
3217 #ifdef CONFIG_X86_64
3218         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3219         if (vmx_msr_high & (1u<<16))
3220                 return -EIO;
3221 #endif
3222
3223         /* Require Write-Back (WB) memory type for VMCS accesses. */
3224         if (((vmx_msr_high >> 18) & 15) != 6)
3225                 return -EIO;
3226
3227         vmcs_conf->size = vmx_msr_high & 0x1fff;
3228         vmcs_conf->order = get_order(vmcs_config.size);
3229         vmcs_conf->revision_id = vmx_msr_low;
3230
3231         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3232         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3233         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3234         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3235         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3236
3237         cpu_has_load_ia32_efer =
3238                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3239                                 VM_ENTRY_LOAD_IA32_EFER)
3240                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3241                                    VM_EXIT_LOAD_IA32_EFER);
3242
3243         cpu_has_load_perf_global_ctrl =
3244                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3245                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3246                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3247                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3248
3249         /*
3250          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3251          * but due to arrata below it can't be used. Workaround is to use
3252          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3253          *
3254          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3255          *
3256          * AAK155             (model 26)
3257          * AAP115             (model 30)
3258          * AAT100             (model 37)
3259          * BC86,AAY89,BD102   (model 44)
3260          * BA97               (model 46)
3261          *
3262          */
3263         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3264                 switch (boot_cpu_data.x86_model) {
3265                 case 26:
3266                 case 30:
3267                 case 37:
3268                 case 44:
3269                 case 46:
3270                         cpu_has_load_perf_global_ctrl = false;
3271                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3272                                         "does not work properly. Using workaround\n");
3273                         break;
3274                 default:
3275                         break;
3276                 }
3277         }
3278
3279         if (cpu_has_xsaves)
3280                 rdmsrl(MSR_IA32_XSS, host_xss);
3281
3282         return 0;
3283 }
3284
3285 static struct vmcs *alloc_vmcs_cpu(int cpu)
3286 {
3287         int node = cpu_to_node(cpu);
3288         struct page *pages;
3289         struct vmcs *vmcs;
3290
3291         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3292         if (!pages)
3293                 return NULL;
3294         vmcs = page_address(pages);
3295         memset(vmcs, 0, vmcs_config.size);
3296         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3297         return vmcs;
3298 }
3299
3300 static struct vmcs *alloc_vmcs(void)
3301 {
3302         return alloc_vmcs_cpu(raw_smp_processor_id());
3303 }
3304
3305 static void free_vmcs(struct vmcs *vmcs)
3306 {
3307         free_pages((unsigned long)vmcs, vmcs_config.order);
3308 }
3309
3310 /*
3311  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3312  */
3313 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3314 {
3315         if (!loaded_vmcs->vmcs)
3316                 return;
3317         loaded_vmcs_clear(loaded_vmcs);
3318         free_vmcs(loaded_vmcs->vmcs);
3319         loaded_vmcs->vmcs = NULL;
3320 }
3321
3322 static void free_kvm_area(void)
3323 {
3324         int cpu;
3325
3326         for_each_possible_cpu(cpu) {
3327                 free_vmcs(per_cpu(vmxarea, cpu));
3328                 per_cpu(vmxarea, cpu) = NULL;
3329         }
3330 }
3331
3332 static void init_vmcs_shadow_fields(void)
3333 {
3334         int i, j;
3335
3336         /* No checks for read only fields yet */
3337
3338         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3339                 switch (shadow_read_write_fields[i]) {
3340                 case GUEST_BNDCFGS:
3341                         if (!vmx_mpx_supported())
3342                                 continue;
3343                         break;
3344                 default:
3345                         break;
3346                 }
3347
3348                 if (j < i)
3349                         shadow_read_write_fields[j] =
3350                                 shadow_read_write_fields[i];
3351                 j++;
3352         }
3353         max_shadow_read_write_fields = j;
3354
3355         /* shadowed fields guest access without vmexit */
3356         for (i = 0; i < max_shadow_read_write_fields; i++) {
3357                 clear_bit(shadow_read_write_fields[i],
3358                           vmx_vmwrite_bitmap);
3359                 clear_bit(shadow_read_write_fields[i],
3360                           vmx_vmread_bitmap);
3361         }
3362         for (i = 0; i < max_shadow_read_only_fields; i++)
3363                 clear_bit(shadow_read_only_fields[i],
3364                           vmx_vmread_bitmap);
3365 }
3366
3367 static __init int alloc_kvm_area(void)
3368 {
3369         int cpu;
3370
3371         for_each_possible_cpu(cpu) {
3372                 struct vmcs *vmcs;
3373
3374                 vmcs = alloc_vmcs_cpu(cpu);
3375                 if (!vmcs) {
3376                         free_kvm_area();
3377                         return -ENOMEM;
3378                 }
3379
3380                 per_cpu(vmxarea, cpu) = vmcs;
3381         }
3382         return 0;
3383 }
3384
3385 static bool emulation_required(struct kvm_vcpu *vcpu)
3386 {
3387         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3388 }
3389
3390 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3391                 struct kvm_segment *save)
3392 {
3393         if (!emulate_invalid_guest_state) {
3394                 /*
3395                  * CS and SS RPL should be equal during guest entry according
3396                  * to VMX spec, but in reality it is not always so. Since vcpu
3397                  * is in the middle of the transition from real mode to
3398                  * protected mode it is safe to assume that RPL 0 is a good
3399                  * default value.
3400                  */
3401                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3402                         save->selector &= ~SEGMENT_RPL_MASK;
3403                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3404                 save->s = 1;
3405         }
3406         vmx_set_segment(vcpu, save, seg);
3407 }
3408
3409 static void enter_pmode(struct kvm_vcpu *vcpu)
3410 {
3411         unsigned long flags;
3412         struct vcpu_vmx *vmx = to_vmx(vcpu);
3413
3414         /*
3415          * Update real mode segment cache. It may be not up-to-date if sement
3416          * register was written while vcpu was in a guest mode.
3417          */
3418         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3419         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3420         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3421         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3422         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3423         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3424
3425         vmx->rmode.vm86_active = 0;
3426
3427         vmx_segment_cache_clear(vmx);
3428
3429         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3430
3431         flags = vmcs_readl(GUEST_RFLAGS);
3432         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3433         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3434         vmcs_writel(GUEST_RFLAGS, flags);
3435
3436         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3437                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3438
3439         update_exception_bitmap(vcpu);
3440
3441         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3442         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3443         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3444         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3445         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3446         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3447 }
3448
3449 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3450 {
3451         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3452         struct kvm_segment var = *save;
3453
3454         var.dpl = 0x3;
3455         if (seg == VCPU_SREG_CS)
3456                 var.type = 0x3;
3457
3458         if (!emulate_invalid_guest_state) {
3459                 var.selector = var.base >> 4;
3460                 var.base = var.base & 0xffff0;
3461                 var.limit = 0xffff;
3462                 var.g = 0;
3463                 var.db = 0;
3464                 var.present = 1;
3465                 var.s = 1;
3466                 var.l = 0;
3467                 var.unusable = 0;
3468                 var.type = 0x3;
3469                 var.avl = 0;
3470                 if (save->base & 0xf)
3471                         printk_once(KERN_WARNING "kvm: segment base is not "
3472                                         "paragraph aligned when entering "
3473                                         "protected mode (seg=%d)", seg);
3474         }
3475
3476         vmcs_write16(sf->selector, var.selector);
3477         vmcs_write32(sf->base, var.base);
3478         vmcs_write32(sf->limit, var.limit);
3479         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3480 }
3481
3482 static void enter_rmode(struct kvm_vcpu *vcpu)
3483 {
3484         unsigned long flags;
3485         struct vcpu_vmx *vmx = to_vmx(vcpu);
3486
3487         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3488         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3489         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3490         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3491         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3492         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3493         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3494
3495         vmx->rmode.vm86_active = 1;
3496
3497         /*
3498          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3499          * vcpu. Warn the user that an update is overdue.
3500          */
3501         if (!vcpu->kvm->arch.tss_addr)
3502                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3503                              "called before entering vcpu\n");
3504
3505         vmx_segment_cache_clear(vmx);
3506
3507         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3508         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3509         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3510
3511         flags = vmcs_readl(GUEST_RFLAGS);
3512         vmx->rmode.save_rflags = flags;
3513
3514         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3515
3516         vmcs_writel(GUEST_RFLAGS, flags);
3517         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3518         update_exception_bitmap(vcpu);
3519
3520         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3521         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3522         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3523         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3524         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3525         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3526
3527         kvm_mmu_reset_context(vcpu);
3528 }
3529
3530 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3531 {
3532         struct vcpu_vmx *vmx = to_vmx(vcpu);
3533         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3534
3535         if (!msr)
3536                 return;
3537
3538         /*
3539          * Force kernel_gs_base reloading before EFER changes, as control
3540          * of this msr depends on is_long_mode().
3541          */
3542         vmx_load_host_state(to_vmx(vcpu));
3543         vcpu->arch.efer = efer;
3544         if (efer & EFER_LMA) {
3545                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3546                 msr->data = efer;
3547         } else {
3548                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3549
3550                 msr->data = efer & ~EFER_LME;
3551         }
3552         setup_msrs(vmx);
3553 }
3554
3555 #ifdef CONFIG_X86_64
3556
3557 static void enter_lmode(struct kvm_vcpu *vcpu)
3558 {
3559         u32 guest_tr_ar;
3560
3561         vmx_segment_cache_clear(to_vmx(vcpu));
3562
3563         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3564         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3565                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3566                                      __func__);
3567                 vmcs_write32(GUEST_TR_AR_BYTES,
3568                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3569                              | VMX_AR_TYPE_BUSY_64_TSS);
3570         }
3571         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3572 }
3573
3574 static void exit_lmode(struct kvm_vcpu *vcpu)
3575 {
3576         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3577         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3578 }
3579
3580 #endif
3581
3582 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3583 {
3584         vpid_sync_context(vpid);
3585         if (enable_ept) {
3586                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3587                         return;
3588                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3589         }
3590 }
3591
3592 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3593 {
3594         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3595 }
3596
3597 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3598 {
3599         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3600
3601         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3602         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3603 }
3604
3605 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3606 {
3607         if (enable_ept && is_paging(vcpu))
3608                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3609         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3610 }
3611
3612 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3613 {
3614         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3615
3616         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3617         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3618 }
3619
3620 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3621 {
3622         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3623
3624         if (!test_bit(VCPU_EXREG_PDPTR,
3625                       (unsigned long *)&vcpu->arch.regs_dirty))
3626                 return;
3627
3628         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3629                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3630                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3631                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3632                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3633         }
3634 }
3635
3636 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3637 {
3638         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3639
3640         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3641                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3642                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3643                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3644                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3645         }
3646
3647         __set_bit(VCPU_EXREG_PDPTR,
3648                   (unsigned long *)&vcpu->arch.regs_avail);
3649         __set_bit(VCPU_EXREG_PDPTR,
3650                   (unsigned long *)&vcpu->arch.regs_dirty);
3651 }
3652
3653 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3654
3655 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3656                                         unsigned long cr0,
3657                                         struct kvm_vcpu *vcpu)
3658 {
3659         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3660                 vmx_decache_cr3(vcpu);
3661         if (!(cr0 & X86_CR0_PG)) {
3662                 /* From paging/starting to nonpaging */
3663                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3664                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3665                              (CPU_BASED_CR3_LOAD_EXITING |
3666                               CPU_BASED_CR3_STORE_EXITING));
3667                 vcpu->arch.cr0 = cr0;
3668                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3669         } else if (!is_paging(vcpu)) {
3670                 /* From nonpaging to paging */
3671                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3672                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3673                              ~(CPU_BASED_CR3_LOAD_EXITING |
3674                                CPU_BASED_CR3_STORE_EXITING));
3675                 vcpu->arch.cr0 = cr0;
3676                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3677         }
3678
3679         if (!(cr0 & X86_CR0_WP))
3680                 *hw_cr0 &= ~X86_CR0_WP;
3681 }
3682
3683 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3684 {
3685         struct vcpu_vmx *vmx = to_vmx(vcpu);
3686         unsigned long hw_cr0;
3687
3688         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3689         if (enable_unrestricted_guest)
3690                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3691         else {
3692                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3693
3694                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3695                         enter_pmode(vcpu);
3696
3697                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3698                         enter_rmode(vcpu);
3699         }
3700
3701 #ifdef CONFIG_X86_64
3702         if (vcpu->arch.efer & EFER_LME) {
3703                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3704                         enter_lmode(vcpu);
3705                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3706                         exit_lmode(vcpu);
3707         }
3708 #endif
3709
3710         if (enable_ept)
3711                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3712
3713         if (!vcpu->fpu_active)
3714                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3715
3716         vmcs_writel(CR0_READ_SHADOW, cr0);
3717         vmcs_writel(GUEST_CR0, hw_cr0);
3718         vcpu->arch.cr0 = cr0;
3719
3720         /* depends on vcpu->arch.cr0 to be set to a new value */
3721         vmx->emulation_required = emulation_required(vcpu);
3722 }
3723
3724 static u64 construct_eptp(unsigned long root_hpa)
3725 {
3726         u64 eptp;
3727
3728         /* TODO write the value reading from MSR */
3729         eptp = VMX_EPT_DEFAULT_MT |
3730                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3731         if (enable_ept_ad_bits)
3732                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3733         eptp |= (root_hpa & PAGE_MASK);
3734
3735         return eptp;
3736 }
3737
3738 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3739 {
3740         unsigned long guest_cr3;
3741         u64 eptp;
3742
3743         guest_cr3 = cr3;
3744         if (enable_ept) {
3745                 eptp = construct_eptp(cr3);
3746                 vmcs_write64(EPT_POINTER, eptp);
3747                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3748                         guest_cr3 = kvm_read_cr3(vcpu);
3749                 else
3750                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3751                 ept_load_pdptrs(vcpu);
3752         }
3753
3754         vmx_flush_tlb(vcpu);
3755         vmcs_writel(GUEST_CR3, guest_cr3);
3756 }
3757
3758 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3759 {
3760         /*
3761          * Pass through host's Machine Check Enable value to hw_cr4, which
3762          * is in force while we are in guest mode.  Do not let guests control
3763          * this bit, even if host CR4.MCE == 0.
3764          */
3765         unsigned long hw_cr4 =
3766                 (cr4_read_shadow() & X86_CR4_MCE) |
3767                 (cr4 & ~X86_CR4_MCE) |
3768                 (to_vmx(vcpu)->rmode.vm86_active ?
3769                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3770
3771         if (cr4 & X86_CR4_VMXE) {
3772                 /*
3773                  * To use VMXON (and later other VMX instructions), a guest
3774                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3775                  * So basically the check on whether to allow nested VMX
3776                  * is here.
3777                  */
3778                 if (!nested_vmx_allowed(vcpu))
3779                         return 1;
3780         }
3781         if (to_vmx(vcpu)->nested.vmxon &&
3782             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3783                 return 1;
3784
3785         vcpu->arch.cr4 = cr4;
3786         if (enable_ept) {
3787                 if (!is_paging(vcpu)) {
3788                         hw_cr4 &= ~X86_CR4_PAE;
3789                         hw_cr4 |= X86_CR4_PSE;
3790                 } else if (!(cr4 & X86_CR4_PAE)) {
3791                         hw_cr4 &= ~X86_CR4_PAE;
3792                 }
3793         }
3794
3795         if (!enable_unrestricted_guest && !is_paging(vcpu))
3796                 /*
3797                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3798                  * hardware.  However KVM always uses paging mode without
3799                  * unrestricted guest.
3800                  * To emulate this behavior, SMEP/SMAP needs to be manually
3801                  * disabled when guest switches to non-paging mode.
3802                  */
3803                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3804
3805         vmcs_writel(CR4_READ_SHADOW, cr4);
3806         vmcs_writel(GUEST_CR4, hw_cr4);
3807         return 0;
3808 }
3809
3810 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3811                             struct kvm_segment *var, int seg)
3812 {
3813         struct vcpu_vmx *vmx = to_vmx(vcpu);
3814         u32 ar;
3815
3816         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3817                 *var = vmx->rmode.segs[seg];
3818                 if (seg == VCPU_SREG_TR
3819                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3820                         return;
3821                 var->base = vmx_read_guest_seg_base(vmx, seg);
3822                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3823                 return;
3824         }
3825         var->base = vmx_read_guest_seg_base(vmx, seg);
3826         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3827         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3828         ar = vmx_read_guest_seg_ar(vmx, seg);
3829         var->unusable = (ar >> 16) & 1;
3830         var->type = ar & 15;
3831         var->s = (ar >> 4) & 1;
3832         var->dpl = (ar >> 5) & 3;
3833         /*
3834          * Some userspaces do not preserve unusable property. Since usable
3835          * segment has to be present according to VMX spec we can use present
3836          * property to amend userspace bug by making unusable segment always
3837          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3838          * segment as unusable.
3839          */
3840         var->present = !var->unusable;
3841         var->avl = (ar >> 12) & 1;
3842         var->l = (ar >> 13) & 1;
3843         var->db = (ar >> 14) & 1;
3844         var->g = (ar >> 15) & 1;
3845 }
3846
3847 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3848 {
3849         struct kvm_segment s;
3850
3851         if (to_vmx(vcpu)->rmode.vm86_active) {
3852                 vmx_get_segment(vcpu, &s, seg);
3853                 return s.base;
3854         }
3855         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3856 }
3857
3858 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3859 {
3860         struct vcpu_vmx *vmx = to_vmx(vcpu);
3861
3862         if (unlikely(vmx->rmode.vm86_active))
3863                 return 0;
3864         else {
3865                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3866                 return VMX_AR_DPL(ar);
3867         }
3868 }
3869
3870 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3871 {
3872         u32 ar;
3873
3874         if (var->unusable || !var->present)
3875                 ar = 1 << 16;
3876         else {
3877                 ar = var->type & 15;
3878                 ar |= (var->s & 1) << 4;
3879                 ar |= (var->dpl & 3) << 5;
3880                 ar |= (var->present & 1) << 7;
3881                 ar |= (var->avl & 1) << 12;
3882                 ar |= (var->l & 1) << 13;
3883                 ar |= (var->db & 1) << 14;
3884                 ar |= (var->g & 1) << 15;
3885         }
3886
3887         return ar;
3888 }
3889
3890 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3891                             struct kvm_segment *var, int seg)
3892 {
3893         struct vcpu_vmx *vmx = to_vmx(vcpu);
3894         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3895
3896         vmx_segment_cache_clear(vmx);
3897
3898         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3899                 vmx->rmode.segs[seg] = *var;
3900                 if (seg == VCPU_SREG_TR)
3901                         vmcs_write16(sf->selector, var->selector);
3902                 else if (var->s)
3903                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3904                 goto out;
3905         }
3906
3907         vmcs_writel(sf->base, var->base);
3908         vmcs_write32(sf->limit, var->limit);
3909         vmcs_write16(sf->selector, var->selector);
3910
3911         /*
3912          *   Fix the "Accessed" bit in AR field of segment registers for older
3913          * qemu binaries.
3914          *   IA32 arch specifies that at the time of processor reset the
3915          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3916          * is setting it to 0 in the userland code. This causes invalid guest
3917          * state vmexit when "unrestricted guest" mode is turned on.
3918          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3919          * tree. Newer qemu binaries with that qemu fix would not need this
3920          * kvm hack.
3921          */
3922         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3923                 var->type |= 0x1; /* Accessed */
3924
3925         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3926
3927 out:
3928         vmx->emulation_required = emulation_required(vcpu);
3929 }
3930
3931 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3932 {
3933         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3934
3935         *db = (ar >> 14) & 1;
3936         *l = (ar >> 13) & 1;
3937 }
3938
3939 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3940 {
3941         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3942         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3943 }
3944
3945 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3946 {
3947         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3948         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3949 }
3950
3951 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3952 {
3953         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3954         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3955 }
3956
3957 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3958 {
3959         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3960         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3961 }
3962
3963 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3964 {
3965         struct kvm_segment var;
3966         u32 ar;
3967
3968         vmx_get_segment(vcpu, &var, seg);
3969         var.dpl = 0x3;
3970         if (seg == VCPU_SREG_CS)
3971                 var.type = 0x3;
3972         ar = vmx_segment_access_rights(&var);
3973
3974         if (var.base != (var.selector << 4))
3975                 return false;
3976         if (var.limit != 0xffff)
3977                 return false;
3978         if (ar != 0xf3)
3979                 return false;
3980
3981         return true;
3982 }
3983
3984 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3985 {
3986         struct kvm_segment cs;
3987         unsigned int cs_rpl;
3988
3989         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3990         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3991
3992         if (cs.unusable)
3993                 return false;
3994         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3995                 return false;
3996         if (!cs.s)
3997                 return false;
3998         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3999                 if (cs.dpl > cs_rpl)
4000                         return false;
4001         } else {
4002                 if (cs.dpl != cs_rpl)
4003                         return false;
4004         }
4005         if (!cs.present)
4006                 return false;
4007
4008         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4009         return true;
4010 }
4011
4012 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4013 {
4014         struct kvm_segment ss;
4015         unsigned int ss_rpl;
4016
4017         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4018         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4019
4020         if (ss.unusable)
4021                 return true;
4022         if (ss.type != 3 && ss.type != 7)
4023                 return false;
4024         if (!ss.s)
4025                 return false;
4026         if (ss.dpl != ss_rpl) /* DPL != RPL */
4027                 return false;
4028         if (!ss.present)
4029                 return false;
4030
4031         return true;
4032 }
4033
4034 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4035 {
4036         struct kvm_segment var;
4037         unsigned int rpl;
4038
4039         vmx_get_segment(vcpu, &var, seg);
4040         rpl = var.selector & SEGMENT_RPL_MASK;
4041
4042         if (var.unusable)
4043                 return true;
4044         if (!var.s)
4045                 return false;
4046         if (!var.present)
4047                 return false;
4048         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4049                 if (var.dpl < rpl) /* DPL < RPL */
4050                         return false;
4051         }
4052
4053         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4054          * rights flags
4055          */
4056         return true;
4057 }
4058
4059 static bool tr_valid(struct kvm_vcpu *vcpu)
4060 {
4061         struct kvm_segment tr;
4062
4063         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4064
4065         if (tr.unusable)
4066                 return false;
4067         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4068                 return false;
4069         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4070                 return false;
4071         if (!tr.present)
4072                 return false;
4073
4074         return true;
4075 }
4076
4077 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4078 {
4079         struct kvm_segment ldtr;
4080
4081         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4082
4083         if (ldtr.unusable)
4084                 return true;
4085         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4086                 return false;
4087         if (ldtr.type != 2)
4088                 return false;
4089         if (!ldtr.present)
4090                 return false;
4091
4092         return true;
4093 }
4094
4095 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4096 {
4097         struct kvm_segment cs, ss;
4098
4099         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4100         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4101
4102         return ((cs.selector & SEGMENT_RPL_MASK) ==
4103                  (ss.selector & SEGMENT_RPL_MASK));
4104 }
4105
4106 /*
4107  * Check if guest state is valid. Returns true if valid, false if
4108  * not.
4109  * We assume that registers are always usable
4110  */
4111 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4112 {
4113         if (enable_unrestricted_guest)
4114                 return true;
4115
4116         /* real mode guest state checks */
4117         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4118                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4119                         return false;
4120                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4121                         return false;
4122                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4123                         return false;
4124                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4125                         return false;
4126                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4127                         return false;
4128                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4129                         return false;
4130         } else {
4131         /* protected mode guest state checks */
4132                 if (!cs_ss_rpl_check(vcpu))
4133                         return false;
4134                 if (!code_segment_valid(vcpu))
4135                         return false;
4136                 if (!stack_segment_valid(vcpu))
4137                         return false;
4138                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4139                         return false;
4140                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4141                         return false;
4142                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4143                         return false;
4144                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4145                         return false;
4146                 if (!tr_valid(vcpu))
4147                         return false;
4148                 if (!ldtr_valid(vcpu))
4149                         return false;
4150         }
4151         /* TODO:
4152          * - Add checks on RIP
4153          * - Add checks on RFLAGS
4154          */
4155
4156         return true;
4157 }
4158
4159 static int init_rmode_tss(struct kvm *kvm)
4160 {
4161         gfn_t fn;
4162         u16 data = 0;
4163         int idx, r;
4164
4165         idx = srcu_read_lock(&kvm->srcu);
4166         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4167         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4168         if (r < 0)
4169                 goto out;
4170         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4171         r = kvm_write_guest_page(kvm, fn++, &data,
4172                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4173         if (r < 0)
4174                 goto out;
4175         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4176         if (r < 0)
4177                 goto out;
4178         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4179         if (r < 0)
4180                 goto out;
4181         data = ~0;
4182         r = kvm_write_guest_page(kvm, fn, &data,
4183                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4184                                  sizeof(u8));
4185 out:
4186         srcu_read_unlock(&kvm->srcu, idx);
4187         return r;
4188 }
4189
4190 static int init_rmode_identity_map(struct kvm *kvm)
4191 {
4192         int i, idx, r = 0;
4193         pfn_t identity_map_pfn;
4194         u32 tmp;
4195
4196         if (!enable_ept)
4197                 return 0;
4198
4199         /* Protect kvm->arch.ept_identity_pagetable_done. */
4200         mutex_lock(&kvm->slots_lock);
4201
4202         if (likely(kvm->arch.ept_identity_pagetable_done))
4203                 goto out2;
4204
4205         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4206
4207         r = alloc_identity_pagetable(kvm);
4208         if (r < 0)
4209                 goto out2;
4210
4211         idx = srcu_read_lock(&kvm->srcu);
4212         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4213         if (r < 0)
4214                 goto out;
4215         /* Set up identity-mapping pagetable for EPT in real mode */
4216         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4217                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4218                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4219                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4220                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4221                 if (r < 0)
4222                         goto out;
4223         }
4224         kvm->arch.ept_identity_pagetable_done = true;
4225
4226 out:
4227         srcu_read_unlock(&kvm->srcu, idx);
4228
4229 out2:
4230         mutex_unlock(&kvm->slots_lock);
4231         return r;
4232 }
4233
4234 static void seg_setup(int seg)
4235 {
4236         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4237         unsigned int ar;
4238
4239         vmcs_write16(sf->selector, 0);
4240         vmcs_writel(sf->base, 0);
4241         vmcs_write32(sf->limit, 0xffff);
4242         ar = 0x93;
4243         if (seg == VCPU_SREG_CS)
4244                 ar |= 0x08; /* code segment */
4245
4246         vmcs_write32(sf->ar_bytes, ar);
4247 }
4248
4249 static int alloc_apic_access_page(struct kvm *kvm)
4250 {
4251         struct page *page;
4252         int r = 0;
4253
4254         mutex_lock(&kvm->slots_lock);
4255         if (kvm->arch.apic_access_page_done)
4256                 goto out;
4257         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4258                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4259         if (r)
4260                 goto out;
4261
4262         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4263         if (is_error_page(page)) {
4264                 r = -EFAULT;
4265                 goto out;
4266         }
4267
4268         /*
4269          * Do not pin the page in memory, so that memory hot-unplug
4270          * is able to migrate it.
4271          */
4272         put_page(page);
4273         kvm->arch.apic_access_page_done = true;
4274 out:
4275         mutex_unlock(&kvm->slots_lock);
4276         return r;
4277 }
4278
4279 static int alloc_identity_pagetable(struct kvm *kvm)
4280 {
4281         /* Called with kvm->slots_lock held. */
4282
4283         int r = 0;
4284
4285         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4286
4287         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4288                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4289
4290         return r;
4291 }
4292
4293 static int allocate_vpid(void)
4294 {
4295         int vpid;
4296
4297         if (!enable_vpid)
4298                 return 0;
4299         spin_lock(&vmx_vpid_lock);
4300         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4301         if (vpid < VMX_NR_VPIDS)
4302                 __set_bit(vpid, vmx_vpid_bitmap);
4303         else
4304                 vpid = 0;
4305         spin_unlock(&vmx_vpid_lock);
4306         return vpid;
4307 }
4308
4309 static void free_vpid(int vpid)
4310 {
4311         if (!enable_vpid || vpid == 0)
4312                 return;
4313         spin_lock(&vmx_vpid_lock);
4314         __clear_bit(vpid, vmx_vpid_bitmap);
4315         spin_unlock(&vmx_vpid_lock);
4316 }
4317
4318 #define MSR_TYPE_R      1
4319 #define MSR_TYPE_W      2
4320 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4321                                                 u32 msr, int type)
4322 {
4323         int f = sizeof(unsigned long);
4324
4325         if (!cpu_has_vmx_msr_bitmap())
4326                 return;
4327
4328         /*
4329          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4330          * have the write-low and read-high bitmap offsets the wrong way round.
4331          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4332          */
4333         if (msr <= 0x1fff) {
4334                 if (type & MSR_TYPE_R)
4335                         /* read-low */
4336                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4337
4338                 if (type & MSR_TYPE_W)
4339                         /* write-low */
4340                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4341
4342         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4343                 msr &= 0x1fff;
4344                 if (type & MSR_TYPE_R)
4345                         /* read-high */
4346                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4347
4348                 if (type & MSR_TYPE_W)
4349                         /* write-high */
4350                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4351
4352         }
4353 }
4354
4355 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4356                                                 u32 msr, int type)
4357 {
4358         int f = sizeof(unsigned long);
4359
4360         if (!cpu_has_vmx_msr_bitmap())
4361                 return;
4362
4363         /*
4364          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4365          * have the write-low and read-high bitmap offsets the wrong way round.
4366          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4367          */
4368         if (msr <= 0x1fff) {
4369                 if (type & MSR_TYPE_R)
4370                         /* read-low */
4371                         __set_bit(msr, msr_bitmap + 0x000 / f);
4372
4373                 if (type & MSR_TYPE_W)
4374                         /* write-low */
4375                         __set_bit(msr, msr_bitmap + 0x800 / f);
4376
4377         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4378                 msr &= 0x1fff;
4379                 if (type & MSR_TYPE_R)
4380                         /* read-high */
4381                         __set_bit(msr, msr_bitmap + 0x400 / f);
4382
4383                 if (type & MSR_TYPE_W)
4384                         /* write-high */
4385                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4386
4387         }
4388 }
4389
4390 /*
4391  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4392  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4393  */
4394 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4395                                                unsigned long *msr_bitmap_nested,
4396                                                u32 msr, int type)
4397 {
4398         int f = sizeof(unsigned long);
4399
4400         if (!cpu_has_vmx_msr_bitmap()) {
4401                 WARN_ON(1);
4402                 return;
4403         }
4404
4405         /*
4406          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4407          * have the write-low and read-high bitmap offsets the wrong way round.
4408          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4409          */
4410         if (msr <= 0x1fff) {
4411                 if (type & MSR_TYPE_R &&
4412                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4413                         /* read-low */
4414                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4415
4416                 if (type & MSR_TYPE_W &&
4417                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4418                         /* write-low */
4419                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4420
4421         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4422                 msr &= 0x1fff;
4423                 if (type & MSR_TYPE_R &&
4424                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4425                         /* read-high */
4426                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4427
4428                 if (type & MSR_TYPE_W &&
4429                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4430                         /* write-high */
4431                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4432
4433         }
4434 }
4435
4436 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4437 {
4438         if (!longmode_only)
4439                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4440                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4441         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4442                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4443 }
4444
4445 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4446 {
4447         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4448                         msr, MSR_TYPE_R);
4449         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4450                         msr, MSR_TYPE_R);
4451 }
4452
4453 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4454 {
4455         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4456                         msr, MSR_TYPE_R);
4457         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4458                         msr, MSR_TYPE_R);
4459 }
4460
4461 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4462 {
4463         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4464                         msr, MSR_TYPE_W);
4465         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4466                         msr, MSR_TYPE_W);
4467 }
4468
4469 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4470 {
4471         return enable_apicv && lapic_in_kernel(vcpu);
4472 }
4473
4474 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4475 {
4476         struct vcpu_vmx *vmx = to_vmx(vcpu);
4477         int max_irr;
4478         void *vapic_page;
4479         u16 status;
4480
4481         if (vmx->nested.pi_desc &&
4482             vmx->nested.pi_pending) {
4483                 vmx->nested.pi_pending = false;
4484                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4485                         return 0;
4486
4487                 max_irr = find_last_bit(
4488                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4489
4490                 if (max_irr == 256)
4491                         return 0;
4492
4493                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4494                 if (!vapic_page) {
4495                         WARN_ON(1);
4496                         return -ENOMEM;
4497                 }
4498                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4499                 kunmap(vmx->nested.virtual_apic_page);
4500
4501                 status = vmcs_read16(GUEST_INTR_STATUS);
4502                 if ((u8)max_irr > ((u8)status & 0xff)) {
4503                         status &= ~0xff;
4504                         status |= (u8)max_irr;
4505                         vmcs_write16(GUEST_INTR_STATUS, status);
4506                 }
4507         }
4508         return 0;
4509 }
4510
4511 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4512 {
4513 #ifdef CONFIG_SMP
4514         if (vcpu->mode == IN_GUEST_MODE) {
4515                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4516
4517                 /*
4518                  * Currently, we don't support urgent interrupt,
4519                  * all interrupts are recognized as non-urgent
4520                  * interrupt, so we cannot post interrupts when
4521                  * 'SN' is set.
4522                  *
4523                  * If the vcpu is in guest mode, it means it is
4524                  * running instead of being scheduled out and
4525                  * waiting in the run queue, and that's the only
4526                  * case when 'SN' is set currently, warning if
4527                  * 'SN' is set.
4528                  */
4529                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4530
4531                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4532                                 POSTED_INTR_VECTOR);
4533                 return true;
4534         }
4535 #endif
4536         return false;
4537 }
4538
4539 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4540                                                 int vector)
4541 {
4542         struct vcpu_vmx *vmx = to_vmx(vcpu);
4543
4544         if (is_guest_mode(vcpu) &&
4545             vector == vmx->nested.posted_intr_nv) {
4546                 /* the PIR and ON have been set by L1. */
4547                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4548                 /*
4549                  * If a posted intr is not recognized by hardware,
4550                  * we will accomplish it in the next vmentry.
4551                  */
4552                 vmx->nested.pi_pending = true;
4553                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4554                 return 0;
4555         }
4556         return -1;
4557 }
4558 /*
4559  * Send interrupt to vcpu via posted interrupt way.
4560  * 1. If target vcpu is running(non-root mode), send posted interrupt
4561  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4562  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4563  * interrupt from PIR in next vmentry.
4564  */
4565 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4566 {
4567         struct vcpu_vmx *vmx = to_vmx(vcpu);
4568         int r;
4569
4570         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4571         if (!r)
4572                 return;
4573
4574         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4575                 return;
4576
4577         r = pi_test_and_set_on(&vmx->pi_desc);
4578         kvm_make_request(KVM_REQ_EVENT, vcpu);
4579         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4580                 kvm_vcpu_kick(vcpu);
4581 }
4582
4583 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4584 {
4585         struct vcpu_vmx *vmx = to_vmx(vcpu);
4586
4587         if (!pi_test_and_clear_on(&vmx->pi_desc))
4588                 return;
4589
4590         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4591 }
4592
4593 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4594 {
4595         return;
4596 }
4597
4598 /*
4599  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4600  * will not change in the lifetime of the guest.
4601  * Note that host-state that does change is set elsewhere. E.g., host-state
4602  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4603  */
4604 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4605 {
4606         u32 low32, high32;
4607         unsigned long tmpl;
4608         struct desc_ptr dt;
4609         unsigned long cr4;
4610
4611         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4612         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4613
4614         /* Save the most likely value for this task's CR4 in the VMCS. */
4615         cr4 = cr4_read_shadow();
4616         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4617         vmx->host_state.vmcs_host_cr4 = cr4;
4618
4619         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4620 #ifdef CONFIG_X86_64
4621         /*
4622          * Load null selectors, so we can avoid reloading them in
4623          * __vmx_load_host_state(), in case userspace uses the null selectors
4624          * too (the expected case).
4625          */
4626         vmcs_write16(HOST_DS_SELECTOR, 0);
4627         vmcs_write16(HOST_ES_SELECTOR, 0);
4628 #else
4629         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4630         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4631 #endif
4632         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4633         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4634
4635         native_store_idt(&dt);
4636         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4637         vmx->host_idt_base = dt.address;
4638
4639         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4640
4641         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4642         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4643         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4644         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4645
4646         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4647                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4648                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4649         }
4650 }
4651
4652 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4653 {
4654         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4655         if (enable_ept)
4656                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4657         if (is_guest_mode(&vmx->vcpu))
4658                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4659                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4660         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4661 }
4662
4663 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4664 {
4665         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4666
4667         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4668                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4669         return pin_based_exec_ctrl;
4670 }
4671
4672 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4673 {
4674         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4675
4676         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4677                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4678
4679         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4680                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4681 #ifdef CONFIG_X86_64
4682                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4683                                 CPU_BASED_CR8_LOAD_EXITING;
4684 #endif
4685         }
4686         if (!enable_ept)
4687                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4688                                 CPU_BASED_CR3_LOAD_EXITING  |
4689                                 CPU_BASED_INVLPG_EXITING;
4690         return exec_control;
4691 }
4692
4693 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4694 {
4695         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4696         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4697                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4698         if (vmx->vpid == 0)
4699                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4700         if (!enable_ept) {
4701                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4702                 enable_unrestricted_guest = 0;
4703                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4704                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4705         }
4706         if (!enable_unrestricted_guest)
4707                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4708         if (!ple_gap)
4709                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4710         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4711                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4712                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4713         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4714         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4715            (handle_vmptrld).
4716            We can NOT enable shadow_vmcs here because we don't have yet
4717            a current VMCS12
4718         */
4719         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4720
4721         if (!enable_pml)
4722                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4723
4724         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4725         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4726
4727         return exec_control;
4728 }
4729
4730 static void ept_set_mmio_spte_mask(void)
4731 {
4732         /*
4733          * EPT Misconfigurations can be generated if the value of bits 2:0
4734          * of an EPT paging-structure entry is 110b (write/execute).
4735          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4736          * spte.
4737          */
4738         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4739 }
4740
4741 #define VMX_XSS_EXIT_BITMAP 0
4742 /*
4743  * Sets up the vmcs for emulated real mode.
4744  */
4745 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4746 {
4747 #ifdef CONFIG_X86_64
4748         unsigned long a;
4749 #endif
4750         int i;
4751
4752         /* I/O */
4753         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4754         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4755
4756         if (enable_shadow_vmcs) {
4757                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4758                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4759         }
4760         if (cpu_has_vmx_msr_bitmap())
4761                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4762
4763         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4764
4765         /* Control */
4766         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4767
4768         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4769
4770         if (cpu_has_secondary_exec_ctrls())
4771                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4772                                 vmx_secondary_exec_control(vmx));
4773
4774         if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4775                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4776                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4777                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4778                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4779
4780                 vmcs_write16(GUEST_INTR_STATUS, 0);
4781
4782                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4783                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4784         }
4785
4786         if (ple_gap) {
4787                 vmcs_write32(PLE_GAP, ple_gap);
4788                 vmx->ple_window = ple_window;
4789                 vmx->ple_window_dirty = true;
4790         }
4791
4792         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4793         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4794         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4795
4796         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4797         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4798         vmx_set_constant_host_state(vmx);
4799 #ifdef CONFIG_X86_64
4800         rdmsrl(MSR_FS_BASE, a);
4801         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4802         rdmsrl(MSR_GS_BASE, a);
4803         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4804 #else
4805         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4806         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4807 #endif
4808
4809         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4810         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4811         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4812         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4813         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4814
4815         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4816                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4817
4818         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4819                 u32 index = vmx_msr_index[i];
4820                 u32 data_low, data_high;
4821                 int j = vmx->nmsrs;
4822
4823                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4824                         continue;
4825                 if (wrmsr_safe(index, data_low, data_high) < 0)
4826                         continue;
4827                 vmx->guest_msrs[j].index = i;
4828                 vmx->guest_msrs[j].data = 0;
4829                 vmx->guest_msrs[j].mask = -1ull;
4830                 ++vmx->nmsrs;
4831         }
4832
4833
4834         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4835
4836         /* 22.2.1, 20.8.1 */
4837         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4838
4839         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4840         set_cr4_guest_host_mask(vmx);
4841
4842         if (vmx_xsaves_supported())
4843                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4844
4845         return 0;
4846 }
4847
4848 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4849 {
4850         struct vcpu_vmx *vmx = to_vmx(vcpu);
4851         struct msr_data apic_base_msr;
4852         u64 cr0;
4853
4854         vmx->rmode.vm86_active = 0;
4855
4856         vmx->soft_vnmi_blocked = 0;
4857
4858         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4859         kvm_set_cr8(vcpu, 0);
4860
4861         if (!init_event) {
4862                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4863                                      MSR_IA32_APICBASE_ENABLE;
4864                 if (kvm_vcpu_is_reset_bsp(vcpu))
4865                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4866                 apic_base_msr.host_initiated = true;
4867                 kvm_set_apic_base(vcpu, &apic_base_msr);
4868         }
4869
4870         vmx_segment_cache_clear(vmx);
4871
4872         seg_setup(VCPU_SREG_CS);
4873         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4874         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4875
4876         seg_setup(VCPU_SREG_DS);
4877         seg_setup(VCPU_SREG_ES);
4878         seg_setup(VCPU_SREG_FS);
4879         seg_setup(VCPU_SREG_GS);
4880         seg_setup(VCPU_SREG_SS);
4881
4882         vmcs_write16(GUEST_TR_SELECTOR, 0);
4883         vmcs_writel(GUEST_TR_BASE, 0);
4884         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4885         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4886
4887         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4888         vmcs_writel(GUEST_LDTR_BASE, 0);
4889         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4890         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4891
4892         if (!init_event) {
4893                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4894                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4895                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4896                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4897         }
4898
4899         vmcs_writel(GUEST_RFLAGS, 0x02);
4900         kvm_rip_write(vcpu, 0xfff0);
4901
4902         vmcs_writel(GUEST_GDTR_BASE, 0);
4903         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4904
4905         vmcs_writel(GUEST_IDTR_BASE, 0);
4906         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4907
4908         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4909         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4910         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4911
4912         setup_msrs(vmx);
4913
4914         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4915
4916         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4917                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4918                 if (cpu_need_tpr_shadow(vcpu))
4919                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4920                                      __pa(vcpu->arch.apic->regs));
4921                 vmcs_write32(TPR_THRESHOLD, 0);
4922         }
4923
4924         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4925
4926         if (vmx_cpu_uses_apicv(vcpu))
4927                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4928
4929         if (vmx->vpid != 0)
4930                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4931
4932         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4933         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4934         vmx->vcpu.arch.cr0 = cr0;
4935         vmx_set_cr4(vcpu, 0);
4936         vmx_set_efer(vcpu, 0);
4937         vmx_fpu_activate(vcpu);
4938         update_exception_bitmap(vcpu);
4939
4940         vpid_sync_context(vmx->vpid);
4941 }
4942
4943 /*
4944  * In nested virtualization, check if L1 asked to exit on external interrupts.
4945  * For most existing hypervisors, this will always return true.
4946  */
4947 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4948 {
4949         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4950                 PIN_BASED_EXT_INTR_MASK;
4951 }
4952
4953 /*
4954  * In nested virtualization, check if L1 has set
4955  * VM_EXIT_ACK_INTR_ON_EXIT
4956  */
4957 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4958 {
4959         return get_vmcs12(vcpu)->vm_exit_controls &
4960                 VM_EXIT_ACK_INTR_ON_EXIT;
4961 }
4962
4963 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4964 {
4965         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4966                 PIN_BASED_NMI_EXITING;
4967 }
4968
4969 static void enable_irq_window(struct kvm_vcpu *vcpu)
4970 {
4971         u32 cpu_based_vm_exec_control;
4972
4973         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4974         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4975         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4976 }
4977
4978 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4979 {
4980         u32 cpu_based_vm_exec_control;
4981
4982         if (!cpu_has_virtual_nmis() ||
4983             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4984                 enable_irq_window(vcpu);
4985                 return;
4986         }
4987
4988         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4989         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4990         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4991 }
4992
4993 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4994 {
4995         struct vcpu_vmx *vmx = to_vmx(vcpu);
4996         uint32_t intr;
4997         int irq = vcpu->arch.interrupt.nr;
4998
4999         trace_kvm_inj_virq(irq);
5000
5001         ++vcpu->stat.irq_injections;
5002         if (vmx->rmode.vm86_active) {
5003                 int inc_eip = 0;
5004                 if (vcpu->arch.interrupt.soft)
5005                         inc_eip = vcpu->arch.event_exit_inst_len;
5006                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5007                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5008                 return;
5009         }
5010         intr = irq | INTR_INFO_VALID_MASK;
5011         if (vcpu->arch.interrupt.soft) {
5012                 intr |= INTR_TYPE_SOFT_INTR;
5013                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5014                              vmx->vcpu.arch.event_exit_inst_len);
5015         } else
5016                 intr |= INTR_TYPE_EXT_INTR;
5017         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5018 }
5019
5020 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5021 {
5022         struct vcpu_vmx *vmx = to_vmx(vcpu);
5023
5024         if (is_guest_mode(vcpu))
5025                 return;
5026
5027         if (!cpu_has_virtual_nmis()) {
5028                 /*
5029                  * Tracking the NMI-blocked state in software is built upon
5030                  * finding the next open IRQ window. This, in turn, depends on
5031                  * well-behaving guests: They have to keep IRQs disabled at
5032                  * least as long as the NMI handler runs. Otherwise we may
5033                  * cause NMI nesting, maybe breaking the guest. But as this is
5034                  * highly unlikely, we can live with the residual risk.
5035                  */
5036                 vmx->soft_vnmi_blocked = 1;
5037                 vmx->vnmi_blocked_time = 0;
5038         }
5039
5040         ++vcpu->stat.nmi_injections;
5041         vmx->nmi_known_unmasked = false;
5042         if (vmx->rmode.vm86_active) {
5043                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5044                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5045                 return;
5046         }
5047         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5048                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5049 }
5050
5051 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5052 {
5053         if (!cpu_has_virtual_nmis())
5054                 return to_vmx(vcpu)->soft_vnmi_blocked;
5055         if (to_vmx(vcpu)->nmi_known_unmasked)
5056                 return false;
5057         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5058 }
5059
5060 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5061 {
5062         struct vcpu_vmx *vmx = to_vmx(vcpu);
5063
5064         if (!cpu_has_virtual_nmis()) {
5065                 if (vmx->soft_vnmi_blocked != masked) {
5066                         vmx->soft_vnmi_blocked = masked;
5067                         vmx->vnmi_blocked_time = 0;
5068                 }
5069         } else {
5070                 vmx->nmi_known_unmasked = !masked;
5071                 if (masked)
5072                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5073                                       GUEST_INTR_STATE_NMI);
5074                 else
5075                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5076                                         GUEST_INTR_STATE_NMI);
5077         }
5078 }
5079
5080 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5081 {
5082         if (to_vmx(vcpu)->nested.nested_run_pending)
5083                 return 0;
5084
5085         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5086                 return 0;
5087
5088         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5089                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5090                    | GUEST_INTR_STATE_NMI));
5091 }
5092
5093 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5094 {
5095         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5096                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5097                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5098                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5099 }
5100
5101 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5102 {
5103         int ret;
5104
5105         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5106                                     PAGE_SIZE * 3);
5107         if (ret)
5108                 return ret;
5109         kvm->arch.tss_addr = addr;
5110         return init_rmode_tss(kvm);
5111 }
5112
5113 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5114 {
5115         switch (vec) {
5116         case BP_VECTOR:
5117                 /*
5118                  * Update instruction length as we may reinject the exception
5119                  * from user space while in guest debugging mode.
5120                  */
5121                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5122                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5123                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5124                         return false;
5125                 /* fall through */
5126         case DB_VECTOR:
5127                 if (vcpu->guest_debug &
5128                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5129                         return false;
5130                 /* fall through */
5131         case DE_VECTOR:
5132         case OF_VECTOR:
5133         case BR_VECTOR:
5134         case UD_VECTOR:
5135         case DF_VECTOR:
5136         case SS_VECTOR:
5137         case GP_VECTOR:
5138         case MF_VECTOR:
5139                 return true;
5140         break;
5141         }
5142         return false;
5143 }
5144
5145 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5146                                   int vec, u32 err_code)
5147 {
5148         /*
5149          * Instruction with address size override prefix opcode 0x67
5150          * Cause the #SS fault with 0 error code in VM86 mode.
5151          */
5152         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5153                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5154                         if (vcpu->arch.halt_request) {
5155                                 vcpu->arch.halt_request = 0;
5156                                 return kvm_vcpu_halt(vcpu);
5157                         }
5158                         return 1;
5159                 }
5160                 return 0;
5161         }
5162
5163         /*
5164          * Forward all other exceptions that are valid in real mode.
5165          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5166          *        the required debugging infrastructure rework.
5167          */
5168         kvm_queue_exception(vcpu, vec);
5169         return 1;
5170 }
5171
5172 /*
5173  * Trigger machine check on the host. We assume all the MSRs are already set up
5174  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5175  * We pass a fake environment to the machine check handler because we want
5176  * the guest to be always treated like user space, no matter what context
5177  * it used internally.
5178  */
5179 static void kvm_machine_check(void)
5180 {
5181 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5182         struct pt_regs regs = {
5183                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5184                 .flags = X86_EFLAGS_IF,
5185         };
5186
5187         do_machine_check(&regs, 0);
5188 #endif
5189 }
5190
5191 static int handle_machine_check(struct kvm_vcpu *vcpu)
5192 {
5193         /* already handled by vcpu_run */
5194         return 1;
5195 }
5196
5197 static int handle_exception(struct kvm_vcpu *vcpu)
5198 {
5199         struct vcpu_vmx *vmx = to_vmx(vcpu);
5200         struct kvm_run *kvm_run = vcpu->run;
5201         u32 intr_info, ex_no, error_code;
5202         unsigned long cr2, rip, dr6;
5203         u32 vect_info;
5204         enum emulation_result er;
5205
5206         vect_info = vmx->idt_vectoring_info;
5207         intr_info = vmx->exit_intr_info;
5208
5209         if (is_machine_check(intr_info))
5210                 return handle_machine_check(vcpu);
5211
5212         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5213                 return 1;  /* already handled by vmx_vcpu_run() */
5214
5215         if (is_no_device(intr_info)) {
5216                 vmx_fpu_activate(vcpu);
5217                 return 1;
5218         }
5219
5220         if (is_invalid_opcode(intr_info)) {
5221                 if (is_guest_mode(vcpu)) {
5222                         kvm_queue_exception(vcpu, UD_VECTOR);
5223                         return 1;
5224                 }
5225                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5226                 if (er != EMULATE_DONE)
5227                         kvm_queue_exception(vcpu, UD_VECTOR);
5228                 return 1;
5229         }
5230
5231         error_code = 0;
5232         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5233                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5234
5235         /*
5236          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5237          * MMIO, it is better to report an internal error.
5238          * See the comments in vmx_handle_exit.
5239          */
5240         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5241             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5242                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5243                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5244                 vcpu->run->internal.ndata = 3;
5245                 vcpu->run->internal.data[0] = vect_info;
5246                 vcpu->run->internal.data[1] = intr_info;
5247                 vcpu->run->internal.data[2] = error_code;
5248                 return 0;
5249         }
5250
5251         if (is_page_fault(intr_info)) {
5252                 /* EPT won't cause page fault directly */
5253                 BUG_ON(enable_ept);
5254                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5255                 trace_kvm_page_fault(cr2, error_code);
5256
5257                 if (kvm_event_needs_reinjection(vcpu))
5258                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5259                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5260         }
5261
5262         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5263
5264         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5265                 return handle_rmode_exception(vcpu, ex_no, error_code);
5266
5267         switch (ex_no) {
5268         case AC_VECTOR:
5269                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5270                 return 1;
5271         case DB_VECTOR:
5272                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5273                 if (!(vcpu->guest_debug &
5274                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5275                         vcpu->arch.dr6 &= ~15;
5276                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5277                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5278                                 skip_emulated_instruction(vcpu);
5279
5280                         kvm_queue_exception(vcpu, DB_VECTOR);
5281                         return 1;
5282                 }
5283                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5284                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5285                 /* fall through */
5286         case BP_VECTOR:
5287                 /*
5288                  * Update instruction length as we may reinject #BP from
5289                  * user space while in guest debugging mode. Reading it for
5290                  * #DB as well causes no harm, it is not used in that case.
5291                  */
5292                 vmx->vcpu.arch.event_exit_inst_len =
5293                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5294                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5295                 rip = kvm_rip_read(vcpu);
5296                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5297                 kvm_run->debug.arch.exception = ex_no;
5298                 break;
5299         default:
5300                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5301                 kvm_run->ex.exception = ex_no;
5302                 kvm_run->ex.error_code = error_code;
5303                 break;
5304         }
5305         return 0;
5306 }
5307
5308 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5309 {
5310         ++vcpu->stat.irq_exits;
5311         return 1;
5312 }
5313
5314 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5315 {
5316         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5317         return 0;
5318 }
5319
5320 static int handle_io(struct kvm_vcpu *vcpu)
5321 {
5322         unsigned long exit_qualification;
5323         int size, in, string;
5324         unsigned port;
5325
5326         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5327         string = (exit_qualification & 16) != 0;
5328         in = (exit_qualification & 8) != 0;
5329
5330         ++vcpu->stat.io_exits;
5331
5332         if (string || in)
5333                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5334
5335         port = exit_qualification >> 16;
5336         size = (exit_qualification & 7) + 1;
5337         skip_emulated_instruction(vcpu);
5338
5339         return kvm_fast_pio_out(vcpu, size, port);
5340 }
5341
5342 static void
5343 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5344 {
5345         /*
5346          * Patch in the VMCALL instruction:
5347          */
5348         hypercall[0] = 0x0f;
5349         hypercall[1] = 0x01;
5350         hypercall[2] = 0xc1;
5351 }
5352
5353 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5354 {
5355         unsigned long always_on = VMXON_CR0_ALWAYSON;
5356         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5357
5358         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5359                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5360             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5361                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5362         return (val & always_on) == always_on;
5363 }
5364
5365 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5366 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5367 {
5368         if (is_guest_mode(vcpu)) {
5369                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5370                 unsigned long orig_val = val;
5371
5372                 /*
5373                  * We get here when L2 changed cr0 in a way that did not change
5374                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5375                  * but did change L0 shadowed bits. So we first calculate the
5376                  * effective cr0 value that L1 would like to write into the
5377                  * hardware. It consists of the L2-owned bits from the new
5378                  * value combined with the L1-owned bits from L1's guest_cr0.
5379                  */
5380                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5381                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5382
5383                 if (!nested_cr0_valid(vcpu, val))
5384                         return 1;
5385
5386                 if (kvm_set_cr0(vcpu, val))
5387                         return 1;
5388                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5389                 return 0;
5390         } else {
5391                 if (to_vmx(vcpu)->nested.vmxon &&
5392                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5393                         return 1;
5394                 return kvm_set_cr0(vcpu, val);
5395         }
5396 }
5397
5398 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5399 {
5400         if (is_guest_mode(vcpu)) {
5401                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5402                 unsigned long orig_val = val;
5403
5404                 /* analogously to handle_set_cr0 */
5405                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5406                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5407                 if (kvm_set_cr4(vcpu, val))
5408                         return 1;
5409                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5410                 return 0;
5411         } else
5412                 return kvm_set_cr4(vcpu, val);
5413 }
5414
5415 /* called to set cr0 as approriate for clts instruction exit. */
5416 static void handle_clts(struct kvm_vcpu *vcpu)
5417 {
5418         if (is_guest_mode(vcpu)) {
5419                 /*
5420                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5421                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5422                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5423                  */
5424                 vmcs_writel(CR0_READ_SHADOW,
5425                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5426                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5427         } else
5428                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5429 }
5430
5431 static int handle_cr(struct kvm_vcpu *vcpu)
5432 {
5433         unsigned long exit_qualification, val;
5434         int cr;
5435         int reg;
5436         int err;
5437
5438         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5439         cr = exit_qualification & 15;
5440         reg = (exit_qualification >> 8) & 15;
5441         switch ((exit_qualification >> 4) & 3) {
5442         case 0: /* mov to cr */
5443                 val = kvm_register_readl(vcpu, reg);
5444                 trace_kvm_cr_write(cr, val);
5445                 switch (cr) {
5446                 case 0:
5447                         err = handle_set_cr0(vcpu, val);
5448                         kvm_complete_insn_gp(vcpu, err);
5449                         return 1;
5450                 case 3:
5451                         err = kvm_set_cr3(vcpu, val);
5452                         kvm_complete_insn_gp(vcpu, err);
5453                         return 1;
5454                 case 4:
5455                         err = handle_set_cr4(vcpu, val);
5456                         kvm_complete_insn_gp(vcpu, err);
5457                         return 1;
5458                 case 8: {
5459                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5460                                 u8 cr8 = (u8)val;
5461                                 err = kvm_set_cr8(vcpu, cr8);
5462                                 kvm_complete_insn_gp(vcpu, err);
5463                                 if (lapic_in_kernel(vcpu))
5464                                         return 1;
5465                                 if (cr8_prev <= cr8)
5466                                         return 1;
5467                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5468                                 return 0;
5469                         }
5470                 }
5471                 break;
5472         case 2: /* clts */
5473                 handle_clts(vcpu);
5474                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5475                 skip_emulated_instruction(vcpu);
5476                 vmx_fpu_activate(vcpu);
5477                 return 1;
5478         case 1: /*mov from cr*/
5479                 switch (cr) {
5480                 case 3:
5481                         val = kvm_read_cr3(vcpu);
5482                         kvm_register_write(vcpu, reg, val);
5483                         trace_kvm_cr_read(cr, val);
5484                         skip_emulated_instruction(vcpu);
5485                         return 1;
5486                 case 8:
5487                         val = kvm_get_cr8(vcpu);
5488                         kvm_register_write(vcpu, reg, val);
5489                         trace_kvm_cr_read(cr, val);
5490                         skip_emulated_instruction(vcpu);
5491                         return 1;
5492                 }
5493                 break;
5494         case 3: /* lmsw */
5495                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5496                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5497                 kvm_lmsw(vcpu, val);
5498
5499                 skip_emulated_instruction(vcpu);
5500                 return 1;
5501         default:
5502                 break;
5503         }
5504         vcpu->run->exit_reason = 0;
5505         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5506                (int)(exit_qualification >> 4) & 3, cr);
5507         return 0;
5508 }
5509
5510 static int handle_dr(struct kvm_vcpu *vcpu)
5511 {
5512         unsigned long exit_qualification;
5513         int dr, dr7, reg;
5514
5515         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5516         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5517
5518         /* First, if DR does not exist, trigger UD */
5519         if (!kvm_require_dr(vcpu, dr))
5520                 return 1;
5521
5522         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5523         if (!kvm_require_cpl(vcpu, 0))
5524                 return 1;
5525         dr7 = vmcs_readl(GUEST_DR7);
5526         if (dr7 & DR7_GD) {
5527                 /*
5528                  * As the vm-exit takes precedence over the debug trap, we
5529                  * need to emulate the latter, either for the host or the
5530                  * guest debugging itself.
5531                  */
5532                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5533                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5534                         vcpu->run->debug.arch.dr7 = dr7;
5535                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5536                         vcpu->run->debug.arch.exception = DB_VECTOR;
5537                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5538                         return 0;
5539                 } else {
5540                         vcpu->arch.dr6 &= ~15;
5541                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5542                         kvm_queue_exception(vcpu, DB_VECTOR);
5543                         return 1;
5544                 }
5545         }
5546
5547         if (vcpu->guest_debug == 0) {
5548                 u32 cpu_based_vm_exec_control;
5549
5550                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5551                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5552                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5553
5554                 /*
5555                  * No more DR vmexits; force a reload of the debug registers
5556                  * and reenter on this instruction.  The next vmexit will
5557                  * retrieve the full state of the debug registers.
5558                  */
5559                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5560                 return 1;
5561         }
5562
5563         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5564         if (exit_qualification & TYPE_MOV_FROM_DR) {
5565                 unsigned long val;
5566
5567                 if (kvm_get_dr(vcpu, dr, &val))
5568                         return 1;
5569                 kvm_register_write(vcpu, reg, val);
5570         } else
5571                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5572                         return 1;
5573
5574         skip_emulated_instruction(vcpu);
5575         return 1;
5576 }
5577
5578 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5579 {
5580         return vcpu->arch.dr6;
5581 }
5582
5583 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5584 {
5585 }
5586
5587 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5588 {
5589         u32 cpu_based_vm_exec_control;
5590
5591         get_debugreg(vcpu->arch.db[0], 0);
5592         get_debugreg(vcpu->arch.db[1], 1);
5593         get_debugreg(vcpu->arch.db[2], 2);
5594         get_debugreg(vcpu->arch.db[3], 3);
5595         get_debugreg(vcpu->arch.dr6, 6);
5596         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5597
5598         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5599
5600         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5601         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5602         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5603 }
5604
5605 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5606 {
5607         vmcs_writel(GUEST_DR7, val);
5608 }
5609
5610 static int handle_cpuid(struct kvm_vcpu *vcpu)
5611 {
5612         kvm_emulate_cpuid(vcpu);
5613         return 1;
5614 }
5615
5616 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5617 {
5618         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5619         struct msr_data msr_info;
5620
5621         msr_info.index = ecx;
5622         msr_info.host_initiated = false;
5623         if (vmx_get_msr(vcpu, &msr_info)) {
5624                 trace_kvm_msr_read_ex(ecx);
5625                 kvm_inject_gp(vcpu, 0);
5626                 return 1;
5627         }
5628
5629         trace_kvm_msr_read(ecx, msr_info.data);
5630
5631         /* FIXME: handling of bits 32:63 of rax, rdx */
5632         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5633         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5634         skip_emulated_instruction(vcpu);
5635         return 1;
5636 }
5637
5638 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5639 {
5640         struct msr_data msr;
5641         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5642         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5643                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5644
5645         msr.data = data;
5646         msr.index = ecx;
5647         msr.host_initiated = false;
5648         if (kvm_set_msr(vcpu, &msr) != 0) {
5649                 trace_kvm_msr_write_ex(ecx, data);
5650                 kvm_inject_gp(vcpu, 0);
5651                 return 1;
5652         }
5653
5654         trace_kvm_msr_write(ecx, data);
5655         skip_emulated_instruction(vcpu);
5656         return 1;
5657 }
5658
5659 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5660 {
5661         kvm_make_request(KVM_REQ_EVENT, vcpu);
5662         return 1;
5663 }
5664
5665 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5666 {
5667         u32 cpu_based_vm_exec_control;
5668
5669         /* clear pending irq */
5670         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5671         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5672         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5673
5674         kvm_make_request(KVM_REQ_EVENT, vcpu);
5675
5676         ++vcpu->stat.irq_window_exits;
5677         return 1;
5678 }
5679
5680 static int handle_halt(struct kvm_vcpu *vcpu)
5681 {
5682         return kvm_emulate_halt(vcpu);
5683 }
5684
5685 static int handle_vmcall(struct kvm_vcpu *vcpu)
5686 {
5687         kvm_emulate_hypercall(vcpu);
5688         return 1;
5689 }
5690
5691 static int handle_invd(struct kvm_vcpu *vcpu)
5692 {
5693         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5694 }
5695
5696 static int handle_invlpg(struct kvm_vcpu *vcpu)
5697 {
5698         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5699
5700         kvm_mmu_invlpg(vcpu, exit_qualification);
5701         skip_emulated_instruction(vcpu);
5702         return 1;
5703 }
5704
5705 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5706 {
5707         int err;
5708
5709         err = kvm_rdpmc(vcpu);
5710         kvm_complete_insn_gp(vcpu, err);
5711
5712         return 1;
5713 }
5714
5715 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5716 {
5717         kvm_emulate_wbinvd(vcpu);
5718         return 1;
5719 }
5720
5721 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5722 {
5723         u64 new_bv = kvm_read_edx_eax(vcpu);
5724         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5725
5726         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5727                 skip_emulated_instruction(vcpu);
5728         return 1;
5729 }
5730
5731 static int handle_xsaves(struct kvm_vcpu *vcpu)
5732 {
5733         skip_emulated_instruction(vcpu);
5734         WARN(1, "this should never happen\n");
5735         return 1;
5736 }
5737
5738 static int handle_xrstors(struct kvm_vcpu *vcpu)
5739 {
5740         skip_emulated_instruction(vcpu);
5741         WARN(1, "this should never happen\n");
5742         return 1;
5743 }
5744
5745 static int handle_apic_access(struct kvm_vcpu *vcpu)
5746 {
5747         if (likely(fasteoi)) {
5748                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5749                 int access_type, offset;
5750
5751                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5752                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5753                 /*
5754                  * Sane guest uses MOV to write EOI, with written value
5755                  * not cared. So make a short-circuit here by avoiding
5756                  * heavy instruction emulation.
5757                  */
5758                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5759                     (offset == APIC_EOI)) {
5760                         kvm_lapic_set_eoi(vcpu);
5761                         skip_emulated_instruction(vcpu);
5762                         return 1;
5763                 }
5764         }
5765         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5766 }
5767
5768 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5769 {
5770         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5771         int vector = exit_qualification & 0xff;
5772
5773         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5774         kvm_apic_set_eoi_accelerated(vcpu, vector);
5775         return 1;
5776 }
5777
5778 static int handle_apic_write(struct kvm_vcpu *vcpu)
5779 {
5780         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5781         u32 offset = exit_qualification & 0xfff;
5782
5783         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5784         kvm_apic_write_nodecode(vcpu, offset);
5785         return 1;
5786 }
5787
5788 static int handle_task_switch(struct kvm_vcpu *vcpu)
5789 {
5790         struct vcpu_vmx *vmx = to_vmx(vcpu);
5791         unsigned long exit_qualification;
5792         bool has_error_code = false;
5793         u32 error_code = 0;
5794         u16 tss_selector;
5795         int reason, type, idt_v, idt_index;
5796
5797         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5798         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5799         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5800
5801         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5802
5803         reason = (u32)exit_qualification >> 30;
5804         if (reason == TASK_SWITCH_GATE && idt_v) {
5805                 switch (type) {
5806                 case INTR_TYPE_NMI_INTR:
5807                         vcpu->arch.nmi_injected = false;
5808                         vmx_set_nmi_mask(vcpu, true);
5809                         break;
5810                 case INTR_TYPE_EXT_INTR:
5811                 case INTR_TYPE_SOFT_INTR:
5812                         kvm_clear_interrupt_queue(vcpu);
5813                         break;
5814                 case INTR_TYPE_HARD_EXCEPTION:
5815                         if (vmx->idt_vectoring_info &
5816                             VECTORING_INFO_DELIVER_CODE_MASK) {
5817                                 has_error_code = true;
5818                                 error_code =
5819                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5820                         }
5821                         /* fall through */
5822                 case INTR_TYPE_SOFT_EXCEPTION:
5823                         kvm_clear_exception_queue(vcpu);
5824                         break;
5825                 default:
5826                         break;
5827                 }
5828         }
5829         tss_selector = exit_qualification;
5830
5831         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5832                        type != INTR_TYPE_EXT_INTR &&
5833                        type != INTR_TYPE_NMI_INTR))
5834                 skip_emulated_instruction(vcpu);
5835
5836         if (kvm_task_switch(vcpu, tss_selector,
5837                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5838                             has_error_code, error_code) == EMULATE_FAIL) {
5839                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5840                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5841                 vcpu->run->internal.ndata = 0;
5842                 return 0;
5843         }
5844
5845         /*
5846          * TODO: What about debug traps on tss switch?
5847          *       Are we supposed to inject them and update dr6?
5848          */
5849
5850         return 1;
5851 }
5852
5853 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5854 {
5855         unsigned long exit_qualification;
5856         gpa_t gpa;
5857         u32 error_code;
5858         int gla_validity;
5859
5860         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5861
5862         gla_validity = (exit_qualification >> 7) & 0x3;
5863         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5864                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5865                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5866                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5867                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5868                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5869                         (long unsigned int)exit_qualification);
5870                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5871                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5872                 return 0;
5873         }
5874
5875         /*
5876          * EPT violation happened while executing iret from NMI,
5877          * "blocked by NMI" bit has to be set before next VM entry.
5878          * There are errata that may cause this bit to not be set:
5879          * AAK134, BY25.
5880          */
5881         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5882                         cpu_has_virtual_nmis() &&
5883                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5884                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5885
5886         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5887         trace_kvm_page_fault(gpa, exit_qualification);
5888
5889         /* It is a write fault? */
5890         error_code = exit_qualification & PFERR_WRITE_MASK;
5891         /* It is a fetch fault? */
5892         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5893         /* ept page table is present? */
5894         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5895
5896         vcpu->arch.exit_qualification = exit_qualification;
5897
5898         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5899 }
5900
5901 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5902 {
5903         int ret;
5904         gpa_t gpa;
5905
5906         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5907         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5908                 skip_emulated_instruction(vcpu);
5909                 trace_kvm_fast_mmio(gpa);
5910                 return 1;
5911         }
5912
5913         ret = handle_mmio_page_fault(vcpu, gpa, true);
5914         if (likely(ret == RET_MMIO_PF_EMULATE))
5915                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5916                                               EMULATE_DONE;
5917
5918         if (unlikely(ret == RET_MMIO_PF_INVALID))
5919                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5920
5921         if (unlikely(ret == RET_MMIO_PF_RETRY))
5922                 return 1;
5923
5924         /* It is the real ept misconfig */
5925         WARN_ON(1);
5926
5927         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5928         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5929
5930         return 0;
5931 }
5932
5933 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5934 {
5935         u32 cpu_based_vm_exec_control;
5936
5937         /* clear pending NMI */
5938         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5939         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5940         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5941         ++vcpu->stat.nmi_window_exits;
5942         kvm_make_request(KVM_REQ_EVENT, vcpu);
5943
5944         return 1;
5945 }
5946
5947 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5948 {
5949         struct vcpu_vmx *vmx = to_vmx(vcpu);
5950         enum emulation_result err = EMULATE_DONE;
5951         int ret = 1;
5952         u32 cpu_exec_ctrl;
5953         bool intr_window_requested;
5954         unsigned count = 130;
5955
5956         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5957         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5958
5959         while (vmx->emulation_required && count-- != 0) {
5960                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5961                         return handle_interrupt_window(&vmx->vcpu);
5962
5963                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5964                         return 1;
5965
5966                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5967
5968                 if (err == EMULATE_USER_EXIT) {
5969                         ++vcpu->stat.mmio_exits;
5970                         ret = 0;
5971                         goto out;
5972                 }
5973
5974                 if (err != EMULATE_DONE) {
5975                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5976                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5977                         vcpu->run->internal.ndata = 0;
5978                         return 0;
5979                 }
5980
5981                 if (vcpu->arch.halt_request) {
5982                         vcpu->arch.halt_request = 0;
5983                         ret = kvm_vcpu_halt(vcpu);
5984                         goto out;
5985                 }
5986
5987                 if (signal_pending(current))
5988                         goto out;
5989                 if (need_resched())
5990                         schedule();
5991         }
5992
5993 out:
5994         return ret;
5995 }
5996
5997 static int __grow_ple_window(int val)
5998 {
5999         if (ple_window_grow < 1)
6000                 return ple_window;
6001
6002         val = min(val, ple_window_actual_max);
6003
6004         if (ple_window_grow < ple_window)
6005                 val *= ple_window_grow;
6006         else
6007                 val += ple_window_grow;
6008
6009         return val;
6010 }
6011
6012 static int __shrink_ple_window(int val, int modifier, int minimum)
6013 {
6014         if (modifier < 1)
6015                 return ple_window;
6016
6017         if (modifier < ple_window)
6018                 val /= modifier;
6019         else
6020                 val -= modifier;
6021
6022         return max(val, minimum);
6023 }
6024
6025 static void grow_ple_window(struct kvm_vcpu *vcpu)
6026 {
6027         struct vcpu_vmx *vmx = to_vmx(vcpu);
6028         int old = vmx->ple_window;
6029
6030         vmx->ple_window = __grow_ple_window(old);
6031
6032         if (vmx->ple_window != old)
6033                 vmx->ple_window_dirty = true;
6034
6035         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6036 }
6037
6038 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6039 {
6040         struct vcpu_vmx *vmx = to_vmx(vcpu);
6041         int old = vmx->ple_window;
6042
6043         vmx->ple_window = __shrink_ple_window(old,
6044                                               ple_window_shrink, ple_window);
6045
6046         if (vmx->ple_window != old)
6047                 vmx->ple_window_dirty = true;
6048
6049         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6050 }
6051
6052 /*
6053  * ple_window_actual_max is computed to be one grow_ple_window() below
6054  * ple_window_max. (See __grow_ple_window for the reason.)
6055  * This prevents overflows, because ple_window_max is int.
6056  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6057  * this process.
6058  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6059  */
6060 static void update_ple_window_actual_max(void)
6061 {
6062         ple_window_actual_max =
6063                         __shrink_ple_window(max(ple_window_max, ple_window),
6064                                             ple_window_grow, INT_MIN);
6065 }
6066
6067 /*
6068  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6069  */
6070 static void wakeup_handler(void)
6071 {
6072         struct kvm_vcpu *vcpu;
6073         int cpu = smp_processor_id();
6074
6075         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6076         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6077                         blocked_vcpu_list) {
6078                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6079
6080                 if (pi_test_on(pi_desc) == 1)
6081                         kvm_vcpu_kick(vcpu);
6082         }
6083         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6084 }
6085
6086 static __init int hardware_setup(void)
6087 {
6088         int r = -ENOMEM, i, msr;
6089
6090         rdmsrl_safe(MSR_EFER, &host_efer);
6091
6092         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6093                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6094
6095         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6096         if (!vmx_io_bitmap_a)
6097                 return r;
6098
6099         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6100         if (!vmx_io_bitmap_b)
6101                 goto out;
6102
6103         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6104         if (!vmx_msr_bitmap_legacy)
6105                 goto out1;
6106
6107         vmx_msr_bitmap_legacy_x2apic =
6108                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6109         if (!vmx_msr_bitmap_legacy_x2apic)
6110                 goto out2;
6111
6112         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6113         if (!vmx_msr_bitmap_longmode)
6114                 goto out3;
6115
6116         vmx_msr_bitmap_longmode_x2apic =
6117                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6118         if (!vmx_msr_bitmap_longmode_x2apic)
6119                 goto out4;
6120
6121         if (nested) {
6122                 vmx_msr_bitmap_nested =
6123                         (unsigned long *)__get_free_page(GFP_KERNEL);
6124                 if (!vmx_msr_bitmap_nested)
6125                         goto out5;
6126         }
6127
6128         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6129         if (!vmx_vmread_bitmap)
6130                 goto out6;
6131
6132         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6133         if (!vmx_vmwrite_bitmap)
6134                 goto out7;
6135
6136         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6137         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6138
6139         /*
6140          * Allow direct access to the PC debug port (it is often used for I/O
6141          * delays, but the vmexits simply slow things down).
6142          */
6143         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6144         clear_bit(0x80, vmx_io_bitmap_a);
6145
6146         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6147
6148         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6149         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6150         if (nested)
6151                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6152
6153         if (setup_vmcs_config(&vmcs_config) < 0) {
6154                 r = -EIO;
6155                 goto out8;
6156         }
6157
6158         if (boot_cpu_has(X86_FEATURE_NX))
6159                 kvm_enable_efer_bits(EFER_NX);
6160
6161         if (!cpu_has_vmx_vpid())
6162                 enable_vpid = 0;
6163         if (!cpu_has_vmx_shadow_vmcs())
6164                 enable_shadow_vmcs = 0;
6165         if (enable_shadow_vmcs)
6166                 init_vmcs_shadow_fields();
6167
6168         if (!cpu_has_vmx_ept() ||
6169             !cpu_has_vmx_ept_4levels()) {
6170                 enable_ept = 0;
6171                 enable_unrestricted_guest = 0;
6172                 enable_ept_ad_bits = 0;
6173         }
6174
6175         if (!cpu_has_vmx_ept_ad_bits())
6176                 enable_ept_ad_bits = 0;
6177
6178         if (!cpu_has_vmx_unrestricted_guest())
6179                 enable_unrestricted_guest = 0;
6180
6181         if (!cpu_has_vmx_flexpriority())
6182                 flexpriority_enabled = 0;
6183
6184         /*
6185          * set_apic_access_page_addr() is used to reload apic access
6186          * page upon invalidation.  No need to do anything if not
6187          * using the APIC_ACCESS_ADDR VMCS field.
6188          */
6189         if (!flexpriority_enabled)
6190                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6191
6192         if (!cpu_has_vmx_tpr_shadow())
6193                 kvm_x86_ops->update_cr8_intercept = NULL;
6194
6195         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6196                 kvm_disable_largepages();
6197
6198         if (!cpu_has_vmx_ple())
6199                 ple_gap = 0;
6200
6201         if (!cpu_has_vmx_apicv())
6202                 enable_apicv = 0;
6203
6204         if (cpu_has_vmx_tsc_scaling()) {
6205                 kvm_has_tsc_control = true;
6206                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6207                 kvm_tsc_scaling_ratio_frac_bits = 48;
6208         }
6209
6210         if (enable_apicv)
6211                 kvm_x86_ops->update_cr8_intercept = NULL;
6212         else {
6213                 kvm_x86_ops->hwapic_irr_update = NULL;
6214                 kvm_x86_ops->hwapic_isr_update = NULL;
6215                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6216                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6217         }
6218
6219         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6220         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6221         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6222         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6223         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6224         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6225         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6226
6227         memcpy(vmx_msr_bitmap_legacy_x2apic,
6228                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6229         memcpy(vmx_msr_bitmap_longmode_x2apic,
6230                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6231
6232         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6233
6234         if (enable_apicv) {
6235                 for (msr = 0x800; msr <= 0x8ff; msr++)
6236                         vmx_disable_intercept_msr_read_x2apic(msr);
6237
6238                 /* According SDM, in x2apic mode, the whole id reg is used.
6239                  * But in KVM, it only use the highest eight bits. Need to
6240                  * intercept it */
6241                 vmx_enable_intercept_msr_read_x2apic(0x802);
6242                 /* TMCCT */
6243                 vmx_enable_intercept_msr_read_x2apic(0x839);
6244                 /* TPR */
6245                 vmx_disable_intercept_msr_write_x2apic(0x808);
6246                 /* EOI */
6247                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6248                 /* SELF-IPI */
6249                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6250         }
6251
6252         if (enable_ept) {
6253                 kvm_mmu_set_mask_ptes(0ull,
6254                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6255                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6256                         0ull, VMX_EPT_EXECUTABLE_MASK);
6257                 ept_set_mmio_spte_mask();
6258                 kvm_enable_tdp();
6259         } else
6260                 kvm_disable_tdp();
6261
6262         update_ple_window_actual_max();
6263
6264         /*
6265          * Only enable PML when hardware supports PML feature, and both EPT
6266          * and EPT A/D bit features are enabled -- PML depends on them to work.
6267          */
6268         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6269                 enable_pml = 0;
6270
6271         if (!enable_pml) {
6272                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6273                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6274                 kvm_x86_ops->flush_log_dirty = NULL;
6275                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6276         }
6277
6278         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6279
6280         return alloc_kvm_area();
6281
6282 out8:
6283         free_page((unsigned long)vmx_vmwrite_bitmap);
6284 out7:
6285         free_page((unsigned long)vmx_vmread_bitmap);
6286 out6:
6287         if (nested)
6288                 free_page((unsigned long)vmx_msr_bitmap_nested);
6289 out5:
6290         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6291 out4:
6292         free_page((unsigned long)vmx_msr_bitmap_longmode);
6293 out3:
6294         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6295 out2:
6296         free_page((unsigned long)vmx_msr_bitmap_legacy);
6297 out1:
6298         free_page((unsigned long)vmx_io_bitmap_b);
6299 out:
6300         free_page((unsigned long)vmx_io_bitmap_a);
6301
6302     return r;
6303 }
6304
6305 static __exit void hardware_unsetup(void)
6306 {
6307         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6308         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6309         free_page((unsigned long)vmx_msr_bitmap_legacy);
6310         free_page((unsigned long)vmx_msr_bitmap_longmode);
6311         free_page((unsigned long)vmx_io_bitmap_b);
6312         free_page((unsigned long)vmx_io_bitmap_a);
6313         free_page((unsigned long)vmx_vmwrite_bitmap);
6314         free_page((unsigned long)vmx_vmread_bitmap);
6315         if (nested)
6316                 free_page((unsigned long)vmx_msr_bitmap_nested);
6317
6318         free_kvm_area();
6319 }
6320
6321 /*
6322  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6323  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6324  */
6325 static int handle_pause(struct kvm_vcpu *vcpu)
6326 {
6327         if (ple_gap)
6328                 grow_ple_window(vcpu);
6329
6330         skip_emulated_instruction(vcpu);
6331         kvm_vcpu_on_spin(vcpu);
6332
6333         return 1;
6334 }
6335
6336 static int handle_nop(struct kvm_vcpu *vcpu)
6337 {
6338         skip_emulated_instruction(vcpu);
6339         return 1;
6340 }
6341
6342 static int handle_mwait(struct kvm_vcpu *vcpu)
6343 {
6344         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6345         return handle_nop(vcpu);
6346 }
6347
6348 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6349 {
6350         return 1;
6351 }
6352
6353 static int handle_monitor(struct kvm_vcpu *vcpu)
6354 {
6355         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6356         return handle_nop(vcpu);
6357 }
6358
6359 /*
6360  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6361  * We could reuse a single VMCS for all the L2 guests, but we also want the
6362  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6363  * allows keeping them loaded on the processor, and in the future will allow
6364  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6365  * every entry if they never change.
6366  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6367  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6368  *
6369  * The following functions allocate and free a vmcs02 in this pool.
6370  */
6371
6372 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6373 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6374 {
6375         struct vmcs02_list *item;
6376         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6377                 if (item->vmptr == vmx->nested.current_vmptr) {
6378                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6379                         return &item->vmcs02;
6380                 }
6381
6382         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6383                 /* Recycle the least recently used VMCS. */
6384                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6385                         struct vmcs02_list, list);
6386                 item->vmptr = vmx->nested.current_vmptr;
6387                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6388                 return &item->vmcs02;
6389         }
6390
6391         /* Create a new VMCS */
6392         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6393         if (!item)
6394                 return NULL;
6395         item->vmcs02.vmcs = alloc_vmcs();
6396         if (!item->vmcs02.vmcs) {
6397                 kfree(item);
6398                 return NULL;
6399         }
6400         loaded_vmcs_init(&item->vmcs02);
6401         item->vmptr = vmx->nested.current_vmptr;
6402         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6403         vmx->nested.vmcs02_num++;
6404         return &item->vmcs02;
6405 }
6406
6407 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6408 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6409 {
6410         struct vmcs02_list *item;
6411         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6412                 if (item->vmptr == vmptr) {
6413                         free_loaded_vmcs(&item->vmcs02);
6414                         list_del(&item->list);
6415                         kfree(item);
6416                         vmx->nested.vmcs02_num--;
6417                         return;
6418                 }
6419 }
6420
6421 /*
6422  * Free all VMCSs saved for this vcpu, except the one pointed by
6423  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6424  * must be &vmx->vmcs01.
6425  */
6426 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6427 {
6428         struct vmcs02_list *item, *n;
6429
6430         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6431         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6432                 /*
6433                  * Something will leak if the above WARN triggers.  Better than
6434                  * a use-after-free.
6435                  */
6436                 if (vmx->loaded_vmcs == &item->vmcs02)
6437                         continue;
6438
6439                 free_loaded_vmcs(&item->vmcs02);
6440                 list_del(&item->list);
6441                 kfree(item);
6442                 vmx->nested.vmcs02_num--;
6443         }
6444 }
6445
6446 /*
6447  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6448  * set the success or error code of an emulated VMX instruction, as specified
6449  * by Vol 2B, VMX Instruction Reference, "Conventions".
6450  */
6451 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6452 {
6453         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6454                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6455                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6456 }
6457
6458 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6459 {
6460         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6461                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6462                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6463                         | X86_EFLAGS_CF);
6464 }
6465
6466 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6467                                         u32 vm_instruction_error)
6468 {
6469         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6470                 /*
6471                  * failValid writes the error number to the current VMCS, which
6472                  * can't be done there isn't a current VMCS.
6473                  */
6474                 nested_vmx_failInvalid(vcpu);
6475                 return;
6476         }
6477         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6478                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6479                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6480                         | X86_EFLAGS_ZF);
6481         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6482         /*
6483          * We don't need to force a shadow sync because
6484          * VM_INSTRUCTION_ERROR is not shadowed
6485          */
6486 }
6487
6488 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6489 {
6490         /* TODO: not to reset guest simply here. */
6491         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6492         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6493 }
6494
6495 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6496 {
6497         struct vcpu_vmx *vmx =
6498                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6499
6500         vmx->nested.preemption_timer_expired = true;
6501         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6502         kvm_vcpu_kick(&vmx->vcpu);
6503
6504         return HRTIMER_NORESTART;
6505 }
6506
6507 /*
6508  * Decode the memory-address operand of a vmx instruction, as recorded on an
6509  * exit caused by such an instruction (run by a guest hypervisor).
6510  * On success, returns 0. When the operand is invalid, returns 1 and throws
6511  * #UD or #GP.
6512  */
6513 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6514                                  unsigned long exit_qualification,
6515                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6516 {
6517         gva_t off;
6518         bool exn;
6519         struct kvm_segment s;
6520
6521         /*
6522          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6523          * Execution", on an exit, vmx_instruction_info holds most of the
6524          * addressing components of the operand. Only the displacement part
6525          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6526          * For how an actual address is calculated from all these components,
6527          * refer to Vol. 1, "Operand Addressing".
6528          */
6529         int  scaling = vmx_instruction_info & 3;
6530         int  addr_size = (vmx_instruction_info >> 7) & 7;
6531         bool is_reg = vmx_instruction_info & (1u << 10);
6532         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6533         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6534         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6535         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6536         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6537
6538         if (is_reg) {
6539                 kvm_queue_exception(vcpu, UD_VECTOR);
6540                 return 1;
6541         }
6542
6543         /* Addr = segment_base + offset */
6544         /* offset = base + [index * scale] + displacement */
6545         off = exit_qualification; /* holds the displacement */
6546         if (base_is_valid)
6547                 off += kvm_register_read(vcpu, base_reg);
6548         if (index_is_valid)
6549                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6550         vmx_get_segment(vcpu, &s, seg_reg);
6551         *ret = s.base + off;
6552
6553         if (addr_size == 1) /* 32 bit */
6554                 *ret &= 0xffffffff;
6555
6556         /* Checks for #GP/#SS exceptions. */
6557         exn = false;
6558         if (is_protmode(vcpu)) {
6559                 /* Protected mode: apply checks for segment validity in the
6560                  * following order:
6561                  * - segment type check (#GP(0) may be thrown)
6562                  * - usability check (#GP(0)/#SS(0))
6563                  * - limit check (#GP(0)/#SS(0))
6564                  */
6565                 if (wr)
6566                         /* #GP(0) if the destination operand is located in a
6567                          * read-only data segment or any code segment.
6568                          */
6569                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6570                 else
6571                         /* #GP(0) if the source operand is located in an
6572                          * execute-only code segment
6573                          */
6574                         exn = ((s.type & 0xa) == 8);
6575         }
6576         if (exn) {
6577                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6578                 return 1;
6579         }
6580         if (is_long_mode(vcpu)) {
6581                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6582                  * non-canonical form. This is an only check for long mode.
6583                  */
6584                 exn = is_noncanonical_address(*ret);
6585         } else if (is_protmode(vcpu)) {
6586                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6587                  */
6588                 exn = (s.unusable != 0);
6589                 /* Protected mode: #GP(0)/#SS(0) if the memory
6590                  * operand is outside the segment limit.
6591                  */
6592                 exn = exn || (off + sizeof(u64) > s.limit);
6593         }
6594         if (exn) {
6595                 kvm_queue_exception_e(vcpu,
6596                                       seg_reg == VCPU_SREG_SS ?
6597                                                 SS_VECTOR : GP_VECTOR,
6598                                       0);
6599                 return 1;
6600         }
6601
6602         return 0;
6603 }
6604
6605 /*
6606  * This function performs the various checks including
6607  * - if it's 4KB aligned
6608  * - No bits beyond the physical address width are set
6609  * - Returns 0 on success or else 1
6610  * (Intel SDM Section 30.3)
6611  */
6612 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6613                                   gpa_t *vmpointer)
6614 {
6615         gva_t gva;
6616         gpa_t vmptr;
6617         struct x86_exception e;
6618         struct page *page;
6619         struct vcpu_vmx *vmx = to_vmx(vcpu);
6620         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6621
6622         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6623                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6624                 return 1;
6625
6626         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6627                                 sizeof(vmptr), &e)) {
6628                 kvm_inject_page_fault(vcpu, &e);
6629                 return 1;
6630         }
6631
6632         switch (exit_reason) {
6633         case EXIT_REASON_VMON:
6634                 /*
6635                  * SDM 3: 24.11.5
6636                  * The first 4 bytes of VMXON region contain the supported
6637                  * VMCS revision identifier
6638                  *
6639                  * Note - IA32_VMX_BASIC[48] will never be 1
6640                  * for the nested case;
6641                  * which replaces physical address width with 32
6642                  *
6643                  */
6644                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6645                         nested_vmx_failInvalid(vcpu);
6646                         skip_emulated_instruction(vcpu);
6647                         return 1;
6648                 }
6649
6650                 page = nested_get_page(vcpu, vmptr);
6651                 if (page == NULL ||
6652                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6653                         nested_vmx_failInvalid(vcpu);
6654                         kunmap(page);
6655                         skip_emulated_instruction(vcpu);
6656                         return 1;
6657                 }
6658                 kunmap(page);
6659                 vmx->nested.vmxon_ptr = vmptr;
6660                 break;
6661         case EXIT_REASON_VMCLEAR:
6662                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6663                         nested_vmx_failValid(vcpu,
6664                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6665                         skip_emulated_instruction(vcpu);
6666                         return 1;
6667                 }
6668
6669                 if (vmptr == vmx->nested.vmxon_ptr) {
6670                         nested_vmx_failValid(vcpu,
6671                                              VMXERR_VMCLEAR_VMXON_POINTER);
6672                         skip_emulated_instruction(vcpu);
6673                         return 1;
6674                 }
6675                 break;
6676         case EXIT_REASON_VMPTRLD:
6677                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6678                         nested_vmx_failValid(vcpu,
6679                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6680                         skip_emulated_instruction(vcpu);
6681                         return 1;
6682                 }
6683
6684                 if (vmptr == vmx->nested.vmxon_ptr) {
6685                         nested_vmx_failValid(vcpu,
6686                                              VMXERR_VMCLEAR_VMXON_POINTER);
6687                         skip_emulated_instruction(vcpu);
6688                         return 1;
6689                 }
6690                 break;
6691         default:
6692                 return 1; /* shouldn't happen */
6693         }
6694
6695         if (vmpointer)
6696                 *vmpointer = vmptr;
6697         return 0;
6698 }
6699
6700 /*
6701  * Emulate the VMXON instruction.
6702  * Currently, we just remember that VMX is active, and do not save or even
6703  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6704  * do not currently need to store anything in that guest-allocated memory
6705  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6706  * argument is different from the VMXON pointer (which the spec says they do).
6707  */
6708 static int handle_vmon(struct kvm_vcpu *vcpu)
6709 {
6710         struct kvm_segment cs;
6711         struct vcpu_vmx *vmx = to_vmx(vcpu);
6712         struct vmcs *shadow_vmcs;
6713         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6714                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6715
6716         /* The Intel VMX Instruction Reference lists a bunch of bits that
6717          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6718          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6719          * Otherwise, we should fail with #UD. We test these now:
6720          */
6721         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6722             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6723             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6724                 kvm_queue_exception(vcpu, UD_VECTOR);
6725                 return 1;
6726         }
6727
6728         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6729         if (is_long_mode(vcpu) && !cs.l) {
6730                 kvm_queue_exception(vcpu, UD_VECTOR);
6731                 return 1;
6732         }
6733
6734         if (vmx_get_cpl(vcpu)) {
6735                 kvm_inject_gp(vcpu, 0);
6736                 return 1;
6737         }
6738
6739         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6740                 return 1;
6741
6742         if (vmx->nested.vmxon) {
6743                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6744                 skip_emulated_instruction(vcpu);
6745                 return 1;
6746         }
6747
6748         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6749                         != VMXON_NEEDED_FEATURES) {
6750                 kvm_inject_gp(vcpu, 0);
6751                 return 1;
6752         }
6753
6754         if (enable_shadow_vmcs) {
6755                 shadow_vmcs = alloc_vmcs();
6756                 if (!shadow_vmcs)
6757                         return -ENOMEM;
6758                 /* mark vmcs as shadow */
6759                 shadow_vmcs->revision_id |= (1u << 31);
6760                 /* init shadow vmcs */
6761                 vmcs_clear(shadow_vmcs);
6762                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6763         }
6764
6765         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6766         vmx->nested.vmcs02_num = 0;
6767
6768         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6769                      HRTIMER_MODE_REL);
6770         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6771
6772         vmx->nested.vmxon = true;
6773
6774         skip_emulated_instruction(vcpu);
6775         nested_vmx_succeed(vcpu);
6776         return 1;
6777 }
6778
6779 /*
6780  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6781  * for running VMX instructions (except VMXON, whose prerequisites are
6782  * slightly different). It also specifies what exception to inject otherwise.
6783  */
6784 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6785 {
6786         struct kvm_segment cs;
6787         struct vcpu_vmx *vmx = to_vmx(vcpu);
6788
6789         if (!vmx->nested.vmxon) {
6790                 kvm_queue_exception(vcpu, UD_VECTOR);
6791                 return 0;
6792         }
6793
6794         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6795         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6796             (is_long_mode(vcpu) && !cs.l)) {
6797                 kvm_queue_exception(vcpu, UD_VECTOR);
6798                 return 0;
6799         }
6800
6801         if (vmx_get_cpl(vcpu)) {
6802                 kvm_inject_gp(vcpu, 0);
6803                 return 0;
6804         }
6805
6806         return 1;
6807 }
6808
6809 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6810 {
6811         if (vmx->nested.current_vmptr == -1ull)
6812                 return;
6813
6814         /* current_vmptr and current_vmcs12 are always set/reset together */
6815         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6816                 return;
6817
6818         if (enable_shadow_vmcs) {
6819                 /* copy to memory all shadowed fields in case
6820                    they were modified */
6821                 copy_shadow_to_vmcs12(vmx);
6822                 vmx->nested.sync_shadow_vmcs = false;
6823                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6824                                 SECONDARY_EXEC_SHADOW_VMCS);
6825                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6826         }
6827         vmx->nested.posted_intr_nv = -1;
6828         kunmap(vmx->nested.current_vmcs12_page);
6829         nested_release_page(vmx->nested.current_vmcs12_page);
6830         vmx->nested.current_vmptr = -1ull;
6831         vmx->nested.current_vmcs12 = NULL;
6832 }
6833
6834 /*
6835  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6836  * just stops using VMX.
6837  */
6838 static void free_nested(struct vcpu_vmx *vmx)
6839 {
6840         if (!vmx->nested.vmxon)
6841                 return;
6842
6843         vmx->nested.vmxon = false;
6844         free_vpid(vmx->nested.vpid02);
6845         nested_release_vmcs12(vmx);
6846         if (enable_shadow_vmcs)
6847                 free_vmcs(vmx->nested.current_shadow_vmcs);
6848         /* Unpin physical memory we referred to in current vmcs02 */
6849         if (vmx->nested.apic_access_page) {
6850                 nested_release_page(vmx->nested.apic_access_page);
6851                 vmx->nested.apic_access_page = NULL;
6852         }
6853         if (vmx->nested.virtual_apic_page) {
6854                 nested_release_page(vmx->nested.virtual_apic_page);
6855                 vmx->nested.virtual_apic_page = NULL;
6856         }
6857         if (vmx->nested.pi_desc_page) {
6858                 kunmap(vmx->nested.pi_desc_page);
6859                 nested_release_page(vmx->nested.pi_desc_page);
6860                 vmx->nested.pi_desc_page = NULL;
6861                 vmx->nested.pi_desc = NULL;
6862         }
6863
6864         nested_free_all_saved_vmcss(vmx);
6865 }
6866
6867 /* Emulate the VMXOFF instruction */
6868 static int handle_vmoff(struct kvm_vcpu *vcpu)
6869 {
6870         if (!nested_vmx_check_permission(vcpu))
6871                 return 1;
6872         free_nested(to_vmx(vcpu));
6873         skip_emulated_instruction(vcpu);
6874         nested_vmx_succeed(vcpu);
6875         return 1;
6876 }
6877
6878 /* Emulate the VMCLEAR instruction */
6879 static int handle_vmclear(struct kvm_vcpu *vcpu)
6880 {
6881         struct vcpu_vmx *vmx = to_vmx(vcpu);
6882         gpa_t vmptr;
6883         struct vmcs12 *vmcs12;
6884         struct page *page;
6885
6886         if (!nested_vmx_check_permission(vcpu))
6887                 return 1;
6888
6889         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6890                 return 1;
6891
6892         if (vmptr == vmx->nested.current_vmptr)
6893                 nested_release_vmcs12(vmx);
6894
6895         page = nested_get_page(vcpu, vmptr);
6896         if (page == NULL) {
6897                 /*
6898                  * For accurate processor emulation, VMCLEAR beyond available
6899                  * physical memory should do nothing at all. However, it is
6900                  * possible that a nested vmx bug, not a guest hypervisor bug,
6901                  * resulted in this case, so let's shut down before doing any
6902                  * more damage:
6903                  */
6904                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6905                 return 1;
6906         }
6907         vmcs12 = kmap(page);
6908         vmcs12->launch_state = 0;
6909         kunmap(page);
6910         nested_release_page(page);
6911
6912         nested_free_vmcs02(vmx, vmptr);
6913
6914         skip_emulated_instruction(vcpu);
6915         nested_vmx_succeed(vcpu);
6916         return 1;
6917 }
6918
6919 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6920
6921 /* Emulate the VMLAUNCH instruction */
6922 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6923 {
6924         return nested_vmx_run(vcpu, true);
6925 }
6926
6927 /* Emulate the VMRESUME instruction */
6928 static int handle_vmresume(struct kvm_vcpu *vcpu)
6929 {
6930
6931         return nested_vmx_run(vcpu, false);
6932 }
6933
6934 enum vmcs_field_type {
6935         VMCS_FIELD_TYPE_U16 = 0,
6936         VMCS_FIELD_TYPE_U64 = 1,
6937         VMCS_FIELD_TYPE_U32 = 2,
6938         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6939 };
6940
6941 static inline int vmcs_field_type(unsigned long field)
6942 {
6943         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6944                 return VMCS_FIELD_TYPE_U32;
6945         return (field >> 13) & 0x3 ;
6946 }
6947
6948 static inline int vmcs_field_readonly(unsigned long field)
6949 {
6950         return (((field >> 10) & 0x3) == 1);
6951 }
6952
6953 /*
6954  * Read a vmcs12 field. Since these can have varying lengths and we return
6955  * one type, we chose the biggest type (u64) and zero-extend the return value
6956  * to that size. Note that the caller, handle_vmread, might need to use only
6957  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6958  * 64-bit fields are to be returned).
6959  */
6960 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6961                                   unsigned long field, u64 *ret)
6962 {
6963         short offset = vmcs_field_to_offset(field);
6964         char *p;
6965
6966         if (offset < 0)
6967                 return offset;
6968
6969         p = ((char *)(get_vmcs12(vcpu))) + offset;
6970
6971         switch (vmcs_field_type(field)) {
6972         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6973                 *ret = *((natural_width *)p);
6974                 return 0;
6975         case VMCS_FIELD_TYPE_U16:
6976                 *ret = *((u16 *)p);
6977                 return 0;
6978         case VMCS_FIELD_TYPE_U32:
6979                 *ret = *((u32 *)p);
6980                 return 0;
6981         case VMCS_FIELD_TYPE_U64:
6982                 *ret = *((u64 *)p);
6983                 return 0;
6984         default:
6985                 WARN_ON(1);
6986                 return -ENOENT;
6987         }
6988 }
6989
6990
6991 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6992                                    unsigned long field, u64 field_value){
6993         short offset = vmcs_field_to_offset(field);
6994         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6995         if (offset < 0)
6996                 return offset;
6997
6998         switch (vmcs_field_type(field)) {
6999         case VMCS_FIELD_TYPE_U16:
7000                 *(u16 *)p = field_value;
7001                 return 0;
7002         case VMCS_FIELD_TYPE_U32:
7003                 *(u32 *)p = field_value;
7004                 return 0;
7005         case VMCS_FIELD_TYPE_U64:
7006                 *(u64 *)p = field_value;
7007                 return 0;
7008         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7009                 *(natural_width *)p = field_value;
7010                 return 0;
7011         default:
7012                 WARN_ON(1);
7013                 return -ENOENT;
7014         }
7015
7016 }
7017
7018 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7019 {
7020         int i;
7021         unsigned long field;
7022         u64 field_value;
7023         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7024         const unsigned long *fields = shadow_read_write_fields;
7025         const int num_fields = max_shadow_read_write_fields;
7026
7027         preempt_disable();
7028
7029         vmcs_load(shadow_vmcs);
7030
7031         for (i = 0; i < num_fields; i++) {
7032                 field = fields[i];
7033                 switch (vmcs_field_type(field)) {
7034                 case VMCS_FIELD_TYPE_U16:
7035                         field_value = vmcs_read16(field);
7036                         break;
7037                 case VMCS_FIELD_TYPE_U32:
7038                         field_value = vmcs_read32(field);
7039                         break;
7040                 case VMCS_FIELD_TYPE_U64:
7041                         field_value = vmcs_read64(field);
7042                         break;
7043                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7044                         field_value = vmcs_readl(field);
7045                         break;
7046                 default:
7047                         WARN_ON(1);
7048                         continue;
7049                 }
7050                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7051         }
7052
7053         vmcs_clear(shadow_vmcs);
7054         vmcs_load(vmx->loaded_vmcs->vmcs);
7055
7056         preempt_enable();
7057 }
7058
7059 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7060 {
7061         const unsigned long *fields[] = {
7062                 shadow_read_write_fields,
7063                 shadow_read_only_fields
7064         };
7065         const int max_fields[] = {
7066                 max_shadow_read_write_fields,
7067                 max_shadow_read_only_fields
7068         };
7069         int i, q;
7070         unsigned long field;
7071         u64 field_value = 0;
7072         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7073
7074         vmcs_load(shadow_vmcs);
7075
7076         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7077                 for (i = 0; i < max_fields[q]; i++) {
7078                         field = fields[q][i];
7079                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7080
7081                         switch (vmcs_field_type(field)) {
7082                         case VMCS_FIELD_TYPE_U16:
7083                                 vmcs_write16(field, (u16)field_value);
7084                                 break;
7085                         case VMCS_FIELD_TYPE_U32:
7086                                 vmcs_write32(field, (u32)field_value);
7087                                 break;
7088                         case VMCS_FIELD_TYPE_U64:
7089                                 vmcs_write64(field, (u64)field_value);
7090                                 break;
7091                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7092                                 vmcs_writel(field, (long)field_value);
7093                                 break;
7094                         default:
7095                                 WARN_ON(1);
7096                                 break;
7097                         }
7098                 }
7099         }
7100
7101         vmcs_clear(shadow_vmcs);
7102         vmcs_load(vmx->loaded_vmcs->vmcs);
7103 }
7104
7105 /*
7106  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7107  * used before) all generate the same failure when it is missing.
7108  */
7109 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7110 {
7111         struct vcpu_vmx *vmx = to_vmx(vcpu);
7112         if (vmx->nested.current_vmptr == -1ull) {
7113                 nested_vmx_failInvalid(vcpu);
7114                 skip_emulated_instruction(vcpu);
7115                 return 0;
7116         }
7117         return 1;
7118 }
7119
7120 static int handle_vmread(struct kvm_vcpu *vcpu)
7121 {
7122         unsigned long field;
7123         u64 field_value;
7124         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7125         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7126         gva_t gva = 0;
7127
7128         if (!nested_vmx_check_permission(vcpu) ||
7129             !nested_vmx_check_vmcs12(vcpu))
7130                 return 1;
7131
7132         /* Decode instruction info and find the field to read */
7133         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7134         /* Read the field, zero-extended to a u64 field_value */
7135         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7136                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7137                 skip_emulated_instruction(vcpu);
7138                 return 1;
7139         }
7140         /*
7141          * Now copy part of this value to register or memory, as requested.
7142          * Note that the number of bits actually copied is 32 or 64 depending
7143          * on the guest's mode (32 or 64 bit), not on the given field's length.
7144          */
7145         if (vmx_instruction_info & (1u << 10)) {
7146                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7147                         field_value);
7148         } else {
7149                 if (get_vmx_mem_address(vcpu, exit_qualification,
7150                                 vmx_instruction_info, true, &gva))
7151                         return 1;
7152                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7153                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7154                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7155         }
7156
7157         nested_vmx_succeed(vcpu);
7158         skip_emulated_instruction(vcpu);
7159         return 1;
7160 }
7161
7162
7163 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7164 {
7165         unsigned long field;
7166         gva_t gva;
7167         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7168         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7169         /* The value to write might be 32 or 64 bits, depending on L1's long
7170          * mode, and eventually we need to write that into a field of several
7171          * possible lengths. The code below first zero-extends the value to 64
7172          * bit (field_value), and then copies only the approriate number of
7173          * bits into the vmcs12 field.
7174          */
7175         u64 field_value = 0;
7176         struct x86_exception e;
7177
7178         if (!nested_vmx_check_permission(vcpu) ||
7179             !nested_vmx_check_vmcs12(vcpu))
7180                 return 1;
7181
7182         if (vmx_instruction_info & (1u << 10))
7183                 field_value = kvm_register_readl(vcpu,
7184                         (((vmx_instruction_info) >> 3) & 0xf));
7185         else {
7186                 if (get_vmx_mem_address(vcpu, exit_qualification,
7187                                 vmx_instruction_info, false, &gva))
7188                         return 1;
7189                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7190                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7191                         kvm_inject_page_fault(vcpu, &e);
7192                         return 1;
7193                 }
7194         }
7195
7196
7197         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7198         if (vmcs_field_readonly(field)) {
7199                 nested_vmx_failValid(vcpu,
7200                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7201                 skip_emulated_instruction(vcpu);
7202                 return 1;
7203         }
7204
7205         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7206                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7207                 skip_emulated_instruction(vcpu);
7208                 return 1;
7209         }
7210
7211         nested_vmx_succeed(vcpu);
7212         skip_emulated_instruction(vcpu);
7213         return 1;
7214 }
7215
7216 /* Emulate the VMPTRLD instruction */
7217 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7218 {
7219         struct vcpu_vmx *vmx = to_vmx(vcpu);
7220         gpa_t vmptr;
7221
7222         if (!nested_vmx_check_permission(vcpu))
7223                 return 1;
7224
7225         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7226                 return 1;
7227
7228         if (vmx->nested.current_vmptr != vmptr) {
7229                 struct vmcs12 *new_vmcs12;
7230                 struct page *page;
7231                 page = nested_get_page(vcpu, vmptr);
7232                 if (page == NULL) {
7233                         nested_vmx_failInvalid(vcpu);
7234                         skip_emulated_instruction(vcpu);
7235                         return 1;
7236                 }
7237                 new_vmcs12 = kmap(page);
7238                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7239                         kunmap(page);
7240                         nested_release_page_clean(page);
7241                         nested_vmx_failValid(vcpu,
7242                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7243                         skip_emulated_instruction(vcpu);
7244                         return 1;
7245                 }
7246
7247                 nested_release_vmcs12(vmx);
7248                 vmx->nested.current_vmptr = vmptr;
7249                 vmx->nested.current_vmcs12 = new_vmcs12;
7250                 vmx->nested.current_vmcs12_page = page;
7251                 if (enable_shadow_vmcs) {
7252                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7253                                       SECONDARY_EXEC_SHADOW_VMCS);
7254                         vmcs_write64(VMCS_LINK_POINTER,
7255                                      __pa(vmx->nested.current_shadow_vmcs));
7256                         vmx->nested.sync_shadow_vmcs = true;
7257                 }
7258         }
7259
7260         nested_vmx_succeed(vcpu);
7261         skip_emulated_instruction(vcpu);
7262         return 1;
7263 }
7264
7265 /* Emulate the VMPTRST instruction */
7266 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7267 {
7268         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7269         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7270         gva_t vmcs_gva;
7271         struct x86_exception e;
7272
7273         if (!nested_vmx_check_permission(vcpu))
7274                 return 1;
7275
7276         if (get_vmx_mem_address(vcpu, exit_qualification,
7277                         vmx_instruction_info, true, &vmcs_gva))
7278                 return 1;
7279         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7280         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7281                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7282                                  sizeof(u64), &e)) {
7283                 kvm_inject_page_fault(vcpu, &e);
7284                 return 1;
7285         }
7286         nested_vmx_succeed(vcpu);
7287         skip_emulated_instruction(vcpu);
7288         return 1;
7289 }
7290
7291 /* Emulate the INVEPT instruction */
7292 static int handle_invept(struct kvm_vcpu *vcpu)
7293 {
7294         struct vcpu_vmx *vmx = to_vmx(vcpu);
7295         u32 vmx_instruction_info, types;
7296         unsigned long type;
7297         gva_t gva;
7298         struct x86_exception e;
7299         struct {
7300                 u64 eptp, gpa;
7301         } operand;
7302
7303         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7304               SECONDARY_EXEC_ENABLE_EPT) ||
7305             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7306                 kvm_queue_exception(vcpu, UD_VECTOR);
7307                 return 1;
7308         }
7309
7310         if (!nested_vmx_check_permission(vcpu))
7311                 return 1;
7312
7313         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7314                 kvm_queue_exception(vcpu, UD_VECTOR);
7315                 return 1;
7316         }
7317
7318         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7319         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7320
7321         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7322
7323         if (!(types & (1UL << type))) {
7324                 nested_vmx_failValid(vcpu,
7325                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7326                 return 1;
7327         }
7328
7329         /* According to the Intel VMX instruction reference, the memory
7330          * operand is read even if it isn't needed (e.g., for type==global)
7331          */
7332         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7333                         vmx_instruction_info, false, &gva))
7334                 return 1;
7335         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7336                                 sizeof(operand), &e)) {
7337                 kvm_inject_page_fault(vcpu, &e);
7338                 return 1;
7339         }
7340
7341         switch (type) {
7342         case VMX_EPT_EXTENT_GLOBAL:
7343                 kvm_mmu_sync_roots(vcpu);
7344                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7345                 nested_vmx_succeed(vcpu);
7346                 break;
7347         default:
7348                 /* Trap single context invalidation invept calls */
7349                 BUG_ON(1);
7350                 break;
7351         }
7352
7353         skip_emulated_instruction(vcpu);
7354         return 1;
7355 }
7356
7357 static int handle_invvpid(struct kvm_vcpu *vcpu)
7358 {
7359         struct vcpu_vmx *vmx = to_vmx(vcpu);
7360         u32 vmx_instruction_info;
7361         unsigned long type, types;
7362         gva_t gva;
7363         struct x86_exception e;
7364         int vpid;
7365
7366         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7367               SECONDARY_EXEC_ENABLE_VPID) ||
7368                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7369                 kvm_queue_exception(vcpu, UD_VECTOR);
7370                 return 1;
7371         }
7372
7373         if (!nested_vmx_check_permission(vcpu))
7374                 return 1;
7375
7376         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7377         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7378
7379         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7380
7381         if (!(types & (1UL << type))) {
7382                 nested_vmx_failValid(vcpu,
7383                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7384                 return 1;
7385         }
7386
7387         /* according to the intel vmx instruction reference, the memory
7388          * operand is read even if it isn't needed (e.g., for type==global)
7389          */
7390         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7391                         vmx_instruction_info, false, &gva))
7392                 return 1;
7393         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7394                                 sizeof(u32), &e)) {
7395                 kvm_inject_page_fault(vcpu, &e);
7396                 return 1;
7397         }
7398
7399         switch (type) {
7400         case VMX_VPID_EXTENT_ALL_CONTEXT:
7401                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7402                 nested_vmx_succeed(vcpu);
7403                 break;
7404         default:
7405                 /* Trap single context invalidation invvpid calls */
7406                 BUG_ON(1);
7407                 break;
7408         }
7409
7410         skip_emulated_instruction(vcpu);
7411         return 1;
7412 }
7413
7414 static int handle_pml_full(struct kvm_vcpu *vcpu)
7415 {
7416         unsigned long exit_qualification;
7417
7418         trace_kvm_pml_full(vcpu->vcpu_id);
7419
7420         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7421
7422         /*
7423          * PML buffer FULL happened while executing iret from NMI,
7424          * "blocked by NMI" bit has to be set before next VM entry.
7425          */
7426         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7427                         cpu_has_virtual_nmis() &&
7428                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7429                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7430                                 GUEST_INTR_STATE_NMI);
7431
7432         /*
7433          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7434          * here.., and there's no userspace involvement needed for PML.
7435          */
7436         return 1;
7437 }
7438
7439 static int handle_pcommit(struct kvm_vcpu *vcpu)
7440 {
7441         /* we never catch pcommit instruct for L1 guest. */
7442         WARN_ON(1);
7443         return 1;
7444 }
7445
7446 /*
7447  * The exit handlers return 1 if the exit was handled fully and guest execution
7448  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7449  * to be done to userspace and return 0.
7450  */
7451 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7452         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7453         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7454         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7455         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7456         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7457         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7458         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7459         [EXIT_REASON_CPUID]                   = handle_cpuid,
7460         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7461         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7462         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7463         [EXIT_REASON_HLT]                     = handle_halt,
7464         [EXIT_REASON_INVD]                    = handle_invd,
7465         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7466         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7467         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7468         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7469         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7470         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7471         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7472         [EXIT_REASON_VMREAD]                  = handle_vmread,
7473         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7474         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7475         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7476         [EXIT_REASON_VMON]                    = handle_vmon,
7477         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7478         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7479         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7480         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7481         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7482         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7483         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7484         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7485         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7486         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7487         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7488         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7489         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7490         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7491         [EXIT_REASON_INVEPT]                  = handle_invept,
7492         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7493         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7494         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7495         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7496         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7497 };
7498
7499 static const int kvm_vmx_max_exit_handlers =
7500         ARRAY_SIZE(kvm_vmx_exit_handlers);
7501
7502 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7503                                        struct vmcs12 *vmcs12)
7504 {
7505         unsigned long exit_qualification;
7506         gpa_t bitmap, last_bitmap;
7507         unsigned int port;
7508         int size;
7509         u8 b;
7510
7511         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7512                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7513
7514         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7515
7516         port = exit_qualification >> 16;
7517         size = (exit_qualification & 7) + 1;
7518
7519         last_bitmap = (gpa_t)-1;
7520         b = -1;
7521
7522         while (size > 0) {
7523                 if (port < 0x8000)
7524                         bitmap = vmcs12->io_bitmap_a;
7525                 else if (port < 0x10000)
7526                         bitmap = vmcs12->io_bitmap_b;
7527                 else
7528                         return true;
7529                 bitmap += (port & 0x7fff) / 8;
7530
7531                 if (last_bitmap != bitmap)
7532                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7533                                 return true;
7534                 if (b & (1 << (port & 7)))
7535                         return true;
7536
7537                 port++;
7538                 size--;
7539                 last_bitmap = bitmap;
7540         }
7541
7542         return false;
7543 }
7544
7545 /*
7546  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7547  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7548  * disinterest in the current event (read or write a specific MSR) by using an
7549  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7550  */
7551 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7552         struct vmcs12 *vmcs12, u32 exit_reason)
7553 {
7554         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7555         gpa_t bitmap;
7556
7557         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7558                 return true;
7559
7560         /*
7561          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7562          * for the four combinations of read/write and low/high MSR numbers.
7563          * First we need to figure out which of the four to use:
7564          */
7565         bitmap = vmcs12->msr_bitmap;
7566         if (exit_reason == EXIT_REASON_MSR_WRITE)
7567                 bitmap += 2048;
7568         if (msr_index >= 0xc0000000) {
7569                 msr_index -= 0xc0000000;
7570                 bitmap += 1024;
7571         }
7572
7573         /* Then read the msr_index'th bit from this bitmap: */
7574         if (msr_index < 1024*8) {
7575                 unsigned char b;
7576                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7577                         return true;
7578                 return 1 & (b >> (msr_index & 7));
7579         } else
7580                 return true; /* let L1 handle the wrong parameter */
7581 }
7582
7583 /*
7584  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7585  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7586  * intercept (via guest_host_mask etc.) the current event.
7587  */
7588 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7589         struct vmcs12 *vmcs12)
7590 {
7591         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7592         int cr = exit_qualification & 15;
7593         int reg = (exit_qualification >> 8) & 15;
7594         unsigned long val = kvm_register_readl(vcpu, reg);
7595
7596         switch ((exit_qualification >> 4) & 3) {
7597         case 0: /* mov to cr */
7598                 switch (cr) {
7599                 case 0:
7600                         if (vmcs12->cr0_guest_host_mask &
7601                             (val ^ vmcs12->cr0_read_shadow))
7602                                 return true;
7603                         break;
7604                 case 3:
7605                         if ((vmcs12->cr3_target_count >= 1 &&
7606                                         vmcs12->cr3_target_value0 == val) ||
7607                                 (vmcs12->cr3_target_count >= 2 &&
7608                                         vmcs12->cr3_target_value1 == val) ||
7609                                 (vmcs12->cr3_target_count >= 3 &&
7610                                         vmcs12->cr3_target_value2 == val) ||
7611                                 (vmcs12->cr3_target_count >= 4 &&
7612                                         vmcs12->cr3_target_value3 == val))
7613                                 return false;
7614                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7615                                 return true;
7616                         break;
7617                 case 4:
7618                         if (vmcs12->cr4_guest_host_mask &
7619                             (vmcs12->cr4_read_shadow ^ val))
7620                                 return true;
7621                         break;
7622                 case 8:
7623                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7624                                 return true;
7625                         break;
7626                 }
7627                 break;
7628         case 2: /* clts */
7629                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7630                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7631                         return true;
7632                 break;
7633         case 1: /* mov from cr */
7634                 switch (cr) {
7635                 case 3:
7636                         if (vmcs12->cpu_based_vm_exec_control &
7637                             CPU_BASED_CR3_STORE_EXITING)
7638                                 return true;
7639                         break;
7640                 case 8:
7641                         if (vmcs12->cpu_based_vm_exec_control &
7642                             CPU_BASED_CR8_STORE_EXITING)
7643                                 return true;
7644                         break;
7645                 }
7646                 break;
7647         case 3: /* lmsw */
7648                 /*
7649                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7650                  * cr0. Other attempted changes are ignored, with no exit.
7651                  */
7652                 if (vmcs12->cr0_guest_host_mask & 0xe &
7653                     (val ^ vmcs12->cr0_read_shadow))
7654                         return true;
7655                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7656                     !(vmcs12->cr0_read_shadow & 0x1) &&
7657                     (val & 0x1))
7658                         return true;
7659                 break;
7660         }
7661         return false;
7662 }
7663
7664 /*
7665  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7666  * should handle it ourselves in L0 (and then continue L2). Only call this
7667  * when in is_guest_mode (L2).
7668  */
7669 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7670 {
7671         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7672         struct vcpu_vmx *vmx = to_vmx(vcpu);
7673         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7674         u32 exit_reason = vmx->exit_reason;
7675
7676         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7677                                 vmcs_readl(EXIT_QUALIFICATION),
7678                                 vmx->idt_vectoring_info,
7679                                 intr_info,
7680                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7681                                 KVM_ISA_VMX);
7682
7683         if (vmx->nested.nested_run_pending)
7684                 return false;
7685
7686         if (unlikely(vmx->fail)) {
7687                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7688                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7689                 return true;
7690         }
7691
7692         switch (exit_reason) {
7693         case EXIT_REASON_EXCEPTION_NMI:
7694                 if (!is_exception(intr_info))
7695                         return false;
7696                 else if (is_page_fault(intr_info))
7697                         return enable_ept;
7698                 else if (is_no_device(intr_info) &&
7699                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7700                         return false;
7701                 return vmcs12->exception_bitmap &
7702                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7703         case EXIT_REASON_EXTERNAL_INTERRUPT:
7704                 return false;
7705         case EXIT_REASON_TRIPLE_FAULT:
7706                 return true;
7707         case EXIT_REASON_PENDING_INTERRUPT:
7708                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7709         case EXIT_REASON_NMI_WINDOW:
7710                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7711         case EXIT_REASON_TASK_SWITCH:
7712                 return true;
7713         case EXIT_REASON_CPUID:
7714                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7715                         return false;
7716                 return true;
7717         case EXIT_REASON_HLT:
7718                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7719         case EXIT_REASON_INVD:
7720                 return true;
7721         case EXIT_REASON_INVLPG:
7722                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7723         case EXIT_REASON_RDPMC:
7724                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7725         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7726                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7727         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7728         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7729         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7730         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7731         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7732         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7733                 /*
7734                  * VMX instructions trap unconditionally. This allows L1 to
7735                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7736                  */
7737                 return true;
7738         case EXIT_REASON_CR_ACCESS:
7739                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7740         case EXIT_REASON_DR_ACCESS:
7741                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7742         case EXIT_REASON_IO_INSTRUCTION:
7743                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7744         case EXIT_REASON_MSR_READ:
7745         case EXIT_REASON_MSR_WRITE:
7746                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7747         case EXIT_REASON_INVALID_STATE:
7748                 return true;
7749         case EXIT_REASON_MWAIT_INSTRUCTION:
7750                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7751         case EXIT_REASON_MONITOR_TRAP_FLAG:
7752                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7753         case EXIT_REASON_MONITOR_INSTRUCTION:
7754                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7755         case EXIT_REASON_PAUSE_INSTRUCTION:
7756                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7757                         nested_cpu_has2(vmcs12,
7758                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7759         case EXIT_REASON_MCE_DURING_VMENTRY:
7760                 return false;
7761         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7762                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7763         case EXIT_REASON_APIC_ACCESS:
7764                 return nested_cpu_has2(vmcs12,
7765                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7766         case EXIT_REASON_APIC_WRITE:
7767         case EXIT_REASON_EOI_INDUCED:
7768                 /* apic_write and eoi_induced should exit unconditionally. */
7769                 return true;
7770         case EXIT_REASON_EPT_VIOLATION:
7771                 /*
7772                  * L0 always deals with the EPT violation. If nested EPT is
7773                  * used, and the nested mmu code discovers that the address is
7774                  * missing in the guest EPT table (EPT12), the EPT violation
7775                  * will be injected with nested_ept_inject_page_fault()
7776                  */
7777                 return false;
7778         case EXIT_REASON_EPT_MISCONFIG:
7779                 /*
7780                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7781                  * table (shadow on EPT) or a merged EPT table that L0 built
7782                  * (EPT on EPT). So any problems with the structure of the
7783                  * table is L0's fault.
7784                  */
7785                 return false;
7786         case EXIT_REASON_WBINVD:
7787                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7788         case EXIT_REASON_XSETBV:
7789                 return true;
7790         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7791                 /*
7792                  * This should never happen, since it is not possible to
7793                  * set XSS to a non-zero value---neither in L1 nor in L2.
7794                  * If if it were, XSS would have to be checked against
7795                  * the XSS exit bitmap in vmcs12.
7796                  */
7797                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7798         case EXIT_REASON_PCOMMIT:
7799                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7800         default:
7801                 return true;
7802         }
7803 }
7804
7805 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7806 {
7807         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7808         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7809 }
7810
7811 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7812 {
7813         struct page *pml_pg;
7814
7815         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7816         if (!pml_pg)
7817                 return -ENOMEM;
7818
7819         vmx->pml_pg = pml_pg;
7820
7821         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7822         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7823
7824         return 0;
7825 }
7826
7827 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7828 {
7829         if (vmx->pml_pg) {
7830                 __free_page(vmx->pml_pg);
7831                 vmx->pml_pg = NULL;
7832         }
7833 }
7834
7835 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7836 {
7837         struct vcpu_vmx *vmx = to_vmx(vcpu);
7838         u64 *pml_buf;
7839         u16 pml_idx;
7840
7841         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7842
7843         /* Do nothing if PML buffer is empty */
7844         if (pml_idx == (PML_ENTITY_NUM - 1))
7845                 return;
7846
7847         /* PML index always points to next available PML buffer entity */
7848         if (pml_idx >= PML_ENTITY_NUM)
7849                 pml_idx = 0;
7850         else
7851                 pml_idx++;
7852
7853         pml_buf = page_address(vmx->pml_pg);
7854         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7855                 u64 gpa;
7856
7857                 gpa = pml_buf[pml_idx];
7858                 WARN_ON(gpa & (PAGE_SIZE - 1));
7859                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7860         }
7861
7862         /* reset PML index */
7863         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7864 }
7865
7866 /*
7867  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7868  * Called before reporting dirty_bitmap to userspace.
7869  */
7870 static void kvm_flush_pml_buffers(struct kvm *kvm)
7871 {
7872         int i;
7873         struct kvm_vcpu *vcpu;
7874         /*
7875          * We only need to kick vcpu out of guest mode here, as PML buffer
7876          * is flushed at beginning of all VMEXITs, and it's obvious that only
7877          * vcpus running in guest are possible to have unflushed GPAs in PML
7878          * buffer.
7879          */
7880         kvm_for_each_vcpu(i, vcpu, kvm)
7881                 kvm_vcpu_kick(vcpu);
7882 }
7883
7884 static void vmx_dump_sel(char *name, uint32_t sel)
7885 {
7886         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7887                name, vmcs_read32(sel),
7888                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7889                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7890                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7891 }
7892
7893 static void vmx_dump_dtsel(char *name, uint32_t limit)
7894 {
7895         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7896                name, vmcs_read32(limit),
7897                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7898 }
7899
7900 static void dump_vmcs(void)
7901 {
7902         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7903         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7904         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7905         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7906         u32 secondary_exec_control = 0;
7907         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7908         u64 efer = vmcs_readl(GUEST_IA32_EFER);
7909         int i, n;
7910
7911         if (cpu_has_secondary_exec_ctrls())
7912                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7913
7914         pr_err("*** Guest State ***\n");
7915         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7916                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7917                vmcs_readl(CR0_GUEST_HOST_MASK));
7918         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7919                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7920         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7921         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7922             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7923         {
7924                 pr_err("PDPTR0 = 0x%016lx  PDPTR1 = 0x%016lx\n",
7925                        vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7926                 pr_err("PDPTR2 = 0x%016lx  PDPTR3 = 0x%016lx\n",
7927                        vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7928         }
7929         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7930                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7931         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7932                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7933         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7934                vmcs_readl(GUEST_SYSENTER_ESP),
7935                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7936         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7937         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7938         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7939         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7940         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7941         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7942         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7943         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7944         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7945         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7946         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7947             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7948                 pr_err("EFER =     0x%016llx  PAT = 0x%016lx\n",
7949                        efer, vmcs_readl(GUEST_IA32_PAT));
7950         pr_err("DebugCtl = 0x%016lx  DebugExceptions = 0x%016lx\n",
7951                vmcs_readl(GUEST_IA32_DEBUGCTL),
7952                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7953         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7954                 pr_err("PerfGlobCtl = 0x%016lx\n",
7955                        vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7956         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7957                 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7958         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7959                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7960                vmcs_read32(GUEST_ACTIVITY_STATE));
7961         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7962                 pr_err("InterruptStatus = %04x\n",
7963                        vmcs_read16(GUEST_INTR_STATUS));
7964
7965         pr_err("*** Host State ***\n");
7966         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
7967                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7968         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7969                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7970                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7971                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7972                vmcs_read16(HOST_TR_SELECTOR));
7973         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7974                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7975                vmcs_readl(HOST_TR_BASE));
7976         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7977                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7978         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7979                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7980                vmcs_readl(HOST_CR4));
7981         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7982                vmcs_readl(HOST_IA32_SYSENTER_ESP),
7983                vmcs_read32(HOST_IA32_SYSENTER_CS),
7984                vmcs_readl(HOST_IA32_SYSENTER_EIP));
7985         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7986                 pr_err("EFER = 0x%016lx  PAT = 0x%016lx\n",
7987                        vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7988         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7989                 pr_err("PerfGlobCtl = 0x%016lx\n",
7990                        vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7991
7992         pr_err("*** Control State ***\n");
7993         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7994                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7995         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7996         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7997                vmcs_read32(EXCEPTION_BITMAP),
7998                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7999                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8000         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8001                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8002                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8003                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8004         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8005                vmcs_read32(VM_EXIT_INTR_INFO),
8006                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8007                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8008         pr_err("        reason=%08x qualification=%016lx\n",
8009                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8010         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8011                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8012                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8013         pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8014         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8015                 pr_err("TSC Multiplier = 0x%016lx\n",
8016                        vmcs_readl(TSC_MULTIPLIER));
8017         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8018                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8019         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8020                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8021         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8022                 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8023         n = vmcs_read32(CR3_TARGET_COUNT);
8024         for (i = 0; i + 1 < n; i += 4)
8025                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8026                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8027                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8028         if (i < n)
8029                 pr_err("CR3 target%u=%016lx\n",
8030                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8031         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8032                 pr_err("PLE Gap=%08x Window=%08x\n",
8033                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8034         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8035                 pr_err("Virtual processor ID = 0x%04x\n",
8036                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8037 }
8038
8039 /*
8040  * The guest has exited.  See if we can fix it or if we need userspace
8041  * assistance.
8042  */
8043 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8044 {
8045         struct vcpu_vmx *vmx = to_vmx(vcpu);
8046         u32 exit_reason = vmx->exit_reason;
8047         u32 vectoring_info = vmx->idt_vectoring_info;
8048
8049         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8050
8051         /*
8052          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8053          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8054          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8055          * mode as if vcpus is in root mode, the PML buffer must has been
8056          * flushed already.
8057          */
8058         if (enable_pml)
8059                 vmx_flush_pml_buffer(vcpu);
8060
8061         /* If guest state is invalid, start emulating */
8062         if (vmx->emulation_required)
8063                 return handle_invalid_guest_state(vcpu);
8064
8065         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8066                 nested_vmx_vmexit(vcpu, exit_reason,
8067                                   vmcs_read32(VM_EXIT_INTR_INFO),
8068                                   vmcs_readl(EXIT_QUALIFICATION));
8069                 return 1;
8070         }
8071
8072         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8073                 dump_vmcs();
8074                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8075                 vcpu->run->fail_entry.hardware_entry_failure_reason
8076                         = exit_reason;
8077                 return 0;
8078         }
8079
8080         if (unlikely(vmx->fail)) {
8081                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8082                 vcpu->run->fail_entry.hardware_entry_failure_reason
8083                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8084                 return 0;
8085         }
8086
8087         /*
8088          * Note:
8089          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8090          * delivery event since it indicates guest is accessing MMIO.
8091          * The vm-exit can be triggered again after return to guest that
8092          * will cause infinite loop.
8093          */
8094         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8095                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8096                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8097                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8098                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8099                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8100                 vcpu->run->internal.ndata = 2;
8101                 vcpu->run->internal.data[0] = vectoring_info;
8102                 vcpu->run->internal.data[1] = exit_reason;
8103                 return 0;
8104         }
8105
8106         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8107             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8108                                         get_vmcs12(vcpu))))) {
8109                 if (vmx_interrupt_allowed(vcpu)) {
8110                         vmx->soft_vnmi_blocked = 0;
8111                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8112                            vcpu->arch.nmi_pending) {
8113                         /*
8114                          * This CPU don't support us in finding the end of an
8115                          * NMI-blocked window if the guest runs with IRQs
8116                          * disabled. So we pull the trigger after 1 s of
8117                          * futile waiting, but inform the user about this.
8118                          */
8119                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8120                                "state on VCPU %d after 1 s timeout\n",
8121                                __func__, vcpu->vcpu_id);
8122                         vmx->soft_vnmi_blocked = 0;
8123                 }
8124         }
8125
8126         if (exit_reason < kvm_vmx_max_exit_handlers
8127             && kvm_vmx_exit_handlers[exit_reason])
8128                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8129         else {
8130                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8131                 kvm_queue_exception(vcpu, UD_VECTOR);
8132                 return 1;
8133         }
8134 }
8135
8136 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8137 {
8138         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8139
8140         if (is_guest_mode(vcpu) &&
8141                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8142                 return;
8143
8144         if (irr == -1 || tpr < irr) {
8145                 vmcs_write32(TPR_THRESHOLD, 0);
8146                 return;
8147         }
8148
8149         vmcs_write32(TPR_THRESHOLD, irr);
8150 }
8151
8152 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8153 {
8154         u32 sec_exec_control;
8155
8156         /*
8157          * There is not point to enable virtualize x2apic without enable
8158          * apicv
8159          */
8160         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8161                                 !vmx_cpu_uses_apicv(vcpu))
8162                 return;
8163
8164         if (!cpu_need_tpr_shadow(vcpu))
8165                 return;
8166
8167         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8168
8169         if (set) {
8170                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8171                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8172         } else {
8173                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8174                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8175         }
8176         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8177
8178         vmx_set_msr_bitmap(vcpu);
8179 }
8180
8181 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8182 {
8183         struct vcpu_vmx *vmx = to_vmx(vcpu);
8184
8185         /*
8186          * Currently we do not handle the nested case where L2 has an
8187          * APIC access page of its own; that page is still pinned.
8188          * Hence, we skip the case where the VCPU is in guest mode _and_
8189          * L1 prepared an APIC access page for L2.
8190          *
8191          * For the case where L1 and L2 share the same APIC access page
8192          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8193          * in the vmcs12), this function will only update either the vmcs01
8194          * or the vmcs02.  If the former, the vmcs02 will be updated by
8195          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8196          * the next L2->L1 exit.
8197          */
8198         if (!is_guest_mode(vcpu) ||
8199             !nested_cpu_has2(vmx->nested.current_vmcs12,
8200                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8201                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8202 }
8203
8204 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8205 {
8206         u16 status;
8207         u8 old;
8208
8209         if (isr == -1)
8210                 isr = 0;
8211
8212         status = vmcs_read16(GUEST_INTR_STATUS);
8213         old = status >> 8;
8214         if (isr != old) {
8215                 status &= 0xff;
8216                 status |= isr << 8;
8217                 vmcs_write16(GUEST_INTR_STATUS, status);
8218         }
8219 }
8220
8221 static void vmx_set_rvi(int vector)
8222 {
8223         u16 status;
8224         u8 old;
8225
8226         if (vector == -1)
8227                 vector = 0;
8228
8229         status = vmcs_read16(GUEST_INTR_STATUS);
8230         old = (u8)status & 0xff;
8231         if ((u8)vector != old) {
8232                 status &= ~0xff;
8233                 status |= (u8)vector;
8234                 vmcs_write16(GUEST_INTR_STATUS, status);
8235         }
8236 }
8237
8238 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8239 {
8240         if (!is_guest_mode(vcpu)) {
8241                 vmx_set_rvi(max_irr);
8242                 return;
8243         }
8244
8245         if (max_irr == -1)
8246                 return;
8247
8248         /*
8249          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8250          * handles it.
8251          */
8252         if (nested_exit_on_intr(vcpu))
8253                 return;
8254
8255         /*
8256          * Else, fall back to pre-APICv interrupt injection since L2
8257          * is run without virtual interrupt delivery.
8258          */
8259         if (!kvm_event_needs_reinjection(vcpu) &&
8260             vmx_interrupt_allowed(vcpu)) {
8261                 kvm_queue_interrupt(vcpu, max_irr, false);
8262                 vmx_inject_irq(vcpu);
8263         }
8264 }
8265
8266 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8267 {
8268         u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8269         if (!vmx_cpu_uses_apicv(vcpu))
8270                 return;
8271
8272         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8273         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8274         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8275         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8276 }
8277
8278 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8279 {
8280         u32 exit_intr_info;
8281
8282         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8283               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8284                 return;
8285
8286         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8287         exit_intr_info = vmx->exit_intr_info;
8288
8289         /* Handle machine checks before interrupts are enabled */
8290         if (is_machine_check(exit_intr_info))
8291                 kvm_machine_check();
8292
8293         /* We need to handle NMIs before interrupts are enabled */
8294         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8295             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8296                 kvm_before_handle_nmi(&vmx->vcpu);
8297                 asm("int $2");
8298                 kvm_after_handle_nmi(&vmx->vcpu);
8299         }
8300 }
8301
8302 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8303 {
8304         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8305
8306         /*
8307          * If external interrupt exists, IF bit is set in rflags/eflags on the
8308          * interrupt stack frame, and interrupt will be enabled on a return
8309          * from interrupt handler.
8310          */
8311         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8312                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8313                 unsigned int vector;
8314                 unsigned long entry;
8315                 gate_desc *desc;
8316                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8317 #ifdef CONFIG_X86_64
8318                 unsigned long tmp;
8319 #endif
8320
8321                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8322                 desc = (gate_desc *)vmx->host_idt_base + vector;
8323                 entry = gate_offset(*desc);
8324                 asm volatile(
8325 #ifdef CONFIG_X86_64
8326                         "mov %%" _ASM_SP ", %[sp]\n\t"
8327                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8328                         "push $%c[ss]\n\t"
8329                         "push %[sp]\n\t"
8330 #endif
8331                         "pushf\n\t"
8332                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8333                         __ASM_SIZE(push) " $%c[cs]\n\t"
8334                         "call *%[entry]\n\t"
8335                         :
8336 #ifdef CONFIG_X86_64
8337                         [sp]"=&r"(tmp)
8338 #endif
8339                         :
8340                         [entry]"r"(entry),
8341                         [ss]"i"(__KERNEL_DS),
8342                         [cs]"i"(__KERNEL_CS)
8343                         );
8344         } else
8345                 local_irq_enable();
8346 }
8347
8348 static bool vmx_has_high_real_mode_segbase(void)
8349 {
8350         return enable_unrestricted_guest || emulate_invalid_guest_state;
8351 }
8352
8353 static bool vmx_mpx_supported(void)
8354 {
8355         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8356                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8357 }
8358
8359 static bool vmx_xsaves_supported(void)
8360 {
8361         return vmcs_config.cpu_based_2nd_exec_ctrl &
8362                 SECONDARY_EXEC_XSAVES;
8363 }
8364
8365 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8366 {
8367         u32 exit_intr_info;
8368         bool unblock_nmi;
8369         u8 vector;
8370         bool idtv_info_valid;
8371
8372         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8373
8374         if (cpu_has_virtual_nmis()) {
8375                 if (vmx->nmi_known_unmasked)
8376                         return;
8377                 /*
8378                  * Can't use vmx->exit_intr_info since we're not sure what
8379                  * the exit reason is.
8380                  */
8381                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8382                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8383                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8384                 /*
8385                  * SDM 3: 27.7.1.2 (September 2008)
8386                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8387                  * a guest IRET fault.
8388                  * SDM 3: 23.2.2 (September 2008)
8389                  * Bit 12 is undefined in any of the following cases:
8390                  *  If the VM exit sets the valid bit in the IDT-vectoring
8391                  *   information field.
8392                  *  If the VM exit is due to a double fault.
8393                  */
8394                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8395                     vector != DF_VECTOR && !idtv_info_valid)
8396                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8397                                       GUEST_INTR_STATE_NMI);
8398                 else
8399                         vmx->nmi_known_unmasked =
8400                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8401                                   & GUEST_INTR_STATE_NMI);
8402         } else if (unlikely(vmx->soft_vnmi_blocked))
8403                 vmx->vnmi_blocked_time +=
8404                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8405 }
8406
8407 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8408                                       u32 idt_vectoring_info,
8409                                       int instr_len_field,
8410                                       int error_code_field)
8411 {
8412         u8 vector;
8413         int type;
8414         bool idtv_info_valid;
8415
8416         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8417
8418         vcpu->arch.nmi_injected = false;
8419         kvm_clear_exception_queue(vcpu);
8420         kvm_clear_interrupt_queue(vcpu);
8421
8422         if (!idtv_info_valid)
8423                 return;
8424
8425         kvm_make_request(KVM_REQ_EVENT, vcpu);
8426
8427         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8428         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8429
8430         switch (type) {
8431         case INTR_TYPE_NMI_INTR:
8432                 vcpu->arch.nmi_injected = true;
8433                 /*
8434                  * SDM 3: 27.7.1.2 (September 2008)
8435                  * Clear bit "block by NMI" before VM entry if a NMI
8436                  * delivery faulted.
8437                  */
8438                 vmx_set_nmi_mask(vcpu, false);
8439                 break;
8440         case INTR_TYPE_SOFT_EXCEPTION:
8441                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8442                 /* fall through */
8443         case INTR_TYPE_HARD_EXCEPTION:
8444                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8445                         u32 err = vmcs_read32(error_code_field);
8446                         kvm_requeue_exception_e(vcpu, vector, err);
8447                 } else
8448                         kvm_requeue_exception(vcpu, vector);
8449                 break;
8450         case INTR_TYPE_SOFT_INTR:
8451                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8452                 /* fall through */
8453         case INTR_TYPE_EXT_INTR:
8454                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8455                 break;
8456         default:
8457                 break;
8458         }
8459 }
8460
8461 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8462 {
8463         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8464                                   VM_EXIT_INSTRUCTION_LEN,
8465                                   IDT_VECTORING_ERROR_CODE);
8466 }
8467
8468 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8469 {
8470         __vmx_complete_interrupts(vcpu,
8471                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8472                                   VM_ENTRY_INSTRUCTION_LEN,
8473                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8474
8475         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8476 }
8477
8478 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8479 {
8480         int i, nr_msrs;
8481         struct perf_guest_switch_msr *msrs;
8482
8483         msrs = perf_guest_get_msrs(&nr_msrs);
8484
8485         if (!msrs)
8486                 return;
8487
8488         for (i = 0; i < nr_msrs; i++)
8489                 if (msrs[i].host == msrs[i].guest)
8490                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8491                 else
8492                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8493                                         msrs[i].host);
8494 }
8495
8496 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8497 {
8498         struct vcpu_vmx *vmx = to_vmx(vcpu);
8499         unsigned long debugctlmsr, cr4;
8500
8501         /* Record the guest's net vcpu time for enforced NMI injections. */
8502         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8503                 vmx->entry_time = ktime_get();
8504
8505         /* Don't enter VMX if guest state is invalid, let the exit handler
8506            start emulation until we arrive back to a valid state */
8507         if (vmx->emulation_required)
8508                 return;
8509
8510         if (vmx->ple_window_dirty) {
8511                 vmx->ple_window_dirty = false;
8512                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8513         }
8514
8515         if (vmx->nested.sync_shadow_vmcs) {
8516                 copy_vmcs12_to_shadow(vmx);
8517                 vmx->nested.sync_shadow_vmcs = false;
8518         }
8519
8520         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8521                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8522         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8523                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8524
8525         cr4 = cr4_read_shadow();
8526         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8527                 vmcs_writel(HOST_CR4, cr4);
8528                 vmx->host_state.vmcs_host_cr4 = cr4;
8529         }
8530
8531         /* When single-stepping over STI and MOV SS, we must clear the
8532          * corresponding interruptibility bits in the guest state. Otherwise
8533          * vmentry fails as it then expects bit 14 (BS) in pending debug
8534          * exceptions being set, but that's not correct for the guest debugging
8535          * case. */
8536         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8537                 vmx_set_interrupt_shadow(vcpu, 0);
8538
8539         atomic_switch_perf_msrs(vmx);
8540         debugctlmsr = get_debugctlmsr();
8541
8542         vmx->__launched = vmx->loaded_vmcs->launched;
8543         asm(
8544                 /* Store host registers */
8545                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8546                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8547                 "push %%" _ASM_CX " \n\t"
8548                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8549                 "je 1f \n\t"
8550                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8551                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8552                 "1: \n\t"
8553                 /* Reload cr2 if changed */
8554                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8555                 "mov %%cr2, %%" _ASM_DX " \n\t"
8556                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8557                 "je 2f \n\t"
8558                 "mov %%" _ASM_AX", %%cr2 \n\t"
8559                 "2: \n\t"
8560                 /* Check if vmlaunch of vmresume is needed */
8561                 "cmpl $0, %c[launched](%0) \n\t"
8562                 /* Load guest registers.  Don't clobber flags. */
8563                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8564                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8565                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8566                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8567                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8568                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8569 #ifdef CONFIG_X86_64
8570                 "mov %c[r8](%0),  %%r8  \n\t"
8571                 "mov %c[r9](%0),  %%r9  \n\t"
8572                 "mov %c[r10](%0), %%r10 \n\t"
8573                 "mov %c[r11](%0), %%r11 \n\t"
8574                 "mov %c[r12](%0), %%r12 \n\t"
8575                 "mov %c[r13](%0), %%r13 \n\t"
8576                 "mov %c[r14](%0), %%r14 \n\t"
8577                 "mov %c[r15](%0), %%r15 \n\t"
8578 #endif
8579                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8580
8581                 /* Enter guest mode */
8582                 "jne 1f \n\t"
8583                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8584                 "jmp 2f \n\t"
8585                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8586                 "2: "
8587                 /* Save guest registers, load host registers, keep flags */
8588                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8589                 "pop %0 \n\t"
8590                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8591                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8592                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8593                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8594                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8595                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8596                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8597 #ifdef CONFIG_X86_64
8598                 "mov %%r8,  %c[r8](%0) \n\t"
8599                 "mov %%r9,  %c[r9](%0) \n\t"
8600                 "mov %%r10, %c[r10](%0) \n\t"
8601                 "mov %%r11, %c[r11](%0) \n\t"
8602                 "mov %%r12, %c[r12](%0) \n\t"
8603                 "mov %%r13, %c[r13](%0) \n\t"
8604                 "mov %%r14, %c[r14](%0) \n\t"
8605                 "mov %%r15, %c[r15](%0) \n\t"
8606 #endif
8607                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8608                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8609
8610                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8611                 "setbe %c[fail](%0) \n\t"
8612                 ".pushsection .rodata \n\t"
8613                 ".global vmx_return \n\t"
8614                 "vmx_return: " _ASM_PTR " 2b \n\t"
8615                 ".popsection"
8616               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8617                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8618                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8619                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8620                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8621                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8622                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8623                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8624                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8625                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8626                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8627 #ifdef CONFIG_X86_64
8628                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8629                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8630                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8631                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8632                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8633                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8634                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8635                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8636 #endif
8637                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8638                 [wordsize]"i"(sizeof(ulong))
8639               : "cc", "memory"
8640 #ifdef CONFIG_X86_64
8641                 , "rax", "rbx", "rdi", "rsi"
8642                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8643 #else
8644                 , "eax", "ebx", "edi", "esi"
8645 #endif
8646               );
8647
8648         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8649         if (debugctlmsr)
8650                 update_debugctlmsr(debugctlmsr);
8651
8652 #ifndef CONFIG_X86_64
8653         /*
8654          * The sysexit path does not restore ds/es, so we must set them to
8655          * a reasonable value ourselves.
8656          *
8657          * We can't defer this to vmx_load_host_state() since that function
8658          * may be executed in interrupt context, which saves and restore segments
8659          * around it, nullifying its effect.
8660          */
8661         loadsegment(ds, __USER_DS);
8662         loadsegment(es, __USER_DS);
8663 #endif
8664
8665         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8666                                   | (1 << VCPU_EXREG_RFLAGS)
8667                                   | (1 << VCPU_EXREG_PDPTR)
8668                                   | (1 << VCPU_EXREG_SEGMENTS)
8669                                   | (1 << VCPU_EXREG_CR3));
8670         vcpu->arch.regs_dirty = 0;
8671
8672         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8673
8674         vmx->loaded_vmcs->launched = 1;
8675
8676         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8677
8678         /*
8679          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8680          * we did not inject a still-pending event to L1 now because of
8681          * nested_run_pending, we need to re-enable this bit.
8682          */
8683         if (vmx->nested.nested_run_pending)
8684                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8685
8686         vmx->nested.nested_run_pending = 0;
8687
8688         vmx_complete_atomic_exit(vmx);
8689         vmx_recover_nmi_blocking(vmx);
8690         vmx_complete_interrupts(vmx);
8691 }
8692
8693 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8694 {
8695         struct vcpu_vmx *vmx = to_vmx(vcpu);
8696         int cpu;
8697
8698         if (vmx->loaded_vmcs == &vmx->vmcs01)
8699                 return;
8700
8701         cpu = get_cpu();
8702         vmx->loaded_vmcs = &vmx->vmcs01;
8703         vmx_vcpu_put(vcpu);
8704         vmx_vcpu_load(vcpu, cpu);
8705         vcpu->cpu = cpu;
8706         put_cpu();
8707 }
8708
8709 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8710 {
8711         struct vcpu_vmx *vmx = to_vmx(vcpu);
8712
8713         if (enable_pml)
8714                 vmx_destroy_pml_buffer(vmx);
8715         free_vpid(vmx->vpid);
8716         leave_guest_mode(vcpu);
8717         vmx_load_vmcs01(vcpu);
8718         free_nested(vmx);
8719         free_loaded_vmcs(vmx->loaded_vmcs);
8720         kfree(vmx->guest_msrs);
8721         kvm_vcpu_uninit(vcpu);
8722         kmem_cache_free(kvm_vcpu_cache, vmx);
8723 }
8724
8725 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8726 {
8727         int err;
8728         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8729         int cpu;
8730
8731         if (!vmx)
8732                 return ERR_PTR(-ENOMEM);
8733
8734         vmx->vpid = allocate_vpid();
8735
8736         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8737         if (err)
8738                 goto free_vcpu;
8739
8740         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8741         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8742                      > PAGE_SIZE);
8743
8744         err = -ENOMEM;
8745         if (!vmx->guest_msrs) {
8746                 goto uninit_vcpu;
8747         }
8748
8749         vmx->loaded_vmcs = &vmx->vmcs01;
8750         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8751         if (!vmx->loaded_vmcs->vmcs)
8752                 goto free_msrs;
8753         if (!vmm_exclusive)
8754                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8755         loaded_vmcs_init(vmx->loaded_vmcs);
8756         if (!vmm_exclusive)
8757                 kvm_cpu_vmxoff();
8758
8759         cpu = get_cpu();
8760         vmx_vcpu_load(&vmx->vcpu, cpu);
8761         vmx->vcpu.cpu = cpu;
8762         err = vmx_vcpu_setup(vmx);
8763         vmx_vcpu_put(&vmx->vcpu);
8764         put_cpu();
8765         if (err)
8766                 goto free_vmcs;
8767         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8768                 err = alloc_apic_access_page(kvm);
8769                 if (err)
8770                         goto free_vmcs;
8771         }
8772
8773         if (enable_ept) {
8774                 if (!kvm->arch.ept_identity_map_addr)
8775                         kvm->arch.ept_identity_map_addr =
8776                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8777                 err = init_rmode_identity_map(kvm);
8778                 if (err)
8779                         goto free_vmcs;
8780         }
8781
8782         if (nested) {
8783                 nested_vmx_setup_ctls_msrs(vmx);
8784                 vmx->nested.vpid02 = allocate_vpid();
8785         }
8786
8787         vmx->nested.posted_intr_nv = -1;
8788         vmx->nested.current_vmptr = -1ull;
8789         vmx->nested.current_vmcs12 = NULL;
8790
8791         /*
8792          * If PML is turned on, failure on enabling PML just results in failure
8793          * of creating the vcpu, therefore we can simplify PML logic (by
8794          * avoiding dealing with cases, such as enabling PML partially on vcpus
8795          * for the guest, etc.
8796          */
8797         if (enable_pml) {
8798                 err = vmx_create_pml_buffer(vmx);
8799                 if (err)
8800                         goto free_vmcs;
8801         }
8802
8803         return &vmx->vcpu;
8804
8805 free_vmcs:
8806         free_vpid(vmx->nested.vpid02);
8807         free_loaded_vmcs(vmx->loaded_vmcs);
8808 free_msrs:
8809         kfree(vmx->guest_msrs);
8810 uninit_vcpu:
8811         kvm_vcpu_uninit(&vmx->vcpu);
8812 free_vcpu:
8813         free_vpid(vmx->vpid);
8814         kmem_cache_free(kvm_vcpu_cache, vmx);
8815         return ERR_PTR(err);
8816 }
8817
8818 static void __init vmx_check_processor_compat(void *rtn)
8819 {
8820         struct vmcs_config vmcs_conf;
8821
8822         *(int *)rtn = 0;
8823         if (setup_vmcs_config(&vmcs_conf) < 0)
8824                 *(int *)rtn = -EIO;
8825         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8826                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8827                                 smp_processor_id());
8828                 *(int *)rtn = -EIO;
8829         }
8830 }
8831
8832 static int get_ept_level(void)
8833 {
8834         return VMX_EPT_DEFAULT_GAW + 1;
8835 }
8836
8837 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8838 {
8839         u8 cache;
8840         u64 ipat = 0;
8841
8842         /* For VT-d and EPT combination
8843          * 1. MMIO: always map as UC
8844          * 2. EPT with VT-d:
8845          *   a. VT-d without snooping control feature: can't guarantee the
8846          *      result, try to trust guest.
8847          *   b. VT-d with snooping control feature: snooping control feature of
8848          *      VT-d engine can guarantee the cache correctness. Just set it
8849          *      to WB to keep consistent with host. So the same as item 3.
8850          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8851          *    consistent with host MTRR
8852          */
8853         if (is_mmio) {
8854                 cache = MTRR_TYPE_UNCACHABLE;
8855                 goto exit;
8856         }
8857
8858         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8859                 ipat = VMX_EPT_IPAT_BIT;
8860                 cache = MTRR_TYPE_WRBACK;
8861                 goto exit;
8862         }
8863
8864         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8865                 ipat = VMX_EPT_IPAT_BIT;
8866                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8867                         cache = MTRR_TYPE_WRBACK;
8868                 else
8869                         cache = MTRR_TYPE_UNCACHABLE;
8870                 goto exit;
8871         }
8872
8873         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8874
8875 exit:
8876         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8877 }
8878
8879 static int vmx_get_lpage_level(void)
8880 {
8881         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8882                 return PT_DIRECTORY_LEVEL;
8883         else
8884                 /* For shadow and EPT supported 1GB page */
8885                 return PT_PDPE_LEVEL;
8886 }
8887
8888 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8889 {
8890         /*
8891          * These bits in the secondary execution controls field
8892          * are dynamic, the others are mostly based on the hypervisor
8893          * architecture and the guest's CPUID.  Do not touch the
8894          * dynamic bits.
8895          */
8896         u32 mask =
8897                 SECONDARY_EXEC_SHADOW_VMCS |
8898                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8899                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8900
8901         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8902
8903         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8904                      (new_ctl & ~mask) | (cur_ctl & mask));
8905 }
8906
8907 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8908 {
8909         struct kvm_cpuid_entry2 *best;
8910         struct vcpu_vmx *vmx = to_vmx(vcpu);
8911         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8912
8913         if (vmx_rdtscp_supported()) {
8914                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8915                 if (!rdtscp_enabled)
8916                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8917
8918                 if (nested) {
8919                         if (rdtscp_enabled)
8920                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8921                                         SECONDARY_EXEC_RDTSCP;
8922                         else
8923                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8924                                         ~SECONDARY_EXEC_RDTSCP;
8925                 }
8926         }
8927
8928         /* Exposing INVPCID only when PCID is exposed */
8929         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8930         if (vmx_invpcid_supported() &&
8931             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8932             !guest_cpuid_has_pcid(vcpu))) {
8933                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8934
8935                 if (best)
8936                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8937         }
8938
8939         if (cpu_has_secondary_exec_ctrls())
8940                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8941
8942         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8943                 if (guest_cpuid_has_pcommit(vcpu))
8944                         vmx->nested.nested_vmx_secondary_ctls_high |=
8945                                 SECONDARY_EXEC_PCOMMIT;
8946                 else
8947                         vmx->nested.nested_vmx_secondary_ctls_high &=
8948                                 ~SECONDARY_EXEC_PCOMMIT;
8949         }
8950 }
8951
8952 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8953 {
8954         if (func == 1 && nested)
8955                 entry->ecx |= bit(X86_FEATURE_VMX);
8956 }
8957
8958 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8959                 struct x86_exception *fault)
8960 {
8961         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8962         u32 exit_reason;
8963
8964         if (fault->error_code & PFERR_RSVD_MASK)
8965                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8966         else
8967                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8968         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8969         vmcs12->guest_physical_address = fault->address;
8970 }
8971
8972 /* Callbacks for nested_ept_init_mmu_context: */
8973
8974 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8975 {
8976         /* return the page table to be shadowed - in our case, EPT12 */
8977         return get_vmcs12(vcpu)->ept_pointer;
8978 }
8979
8980 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8981 {
8982         WARN_ON(mmu_is_nested(vcpu));
8983         kvm_init_shadow_ept_mmu(vcpu,
8984                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8985                         VMX_EPT_EXECUTE_ONLY_BIT);
8986         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8987         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8988         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8989
8990         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8991 }
8992
8993 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8994 {
8995         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8996 }
8997
8998 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8999                                             u16 error_code)
9000 {
9001         bool inequality, bit;
9002
9003         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9004         inequality =
9005                 (error_code & vmcs12->page_fault_error_code_mask) !=
9006                  vmcs12->page_fault_error_code_match;
9007         return inequality ^ bit;
9008 }
9009
9010 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9011                 struct x86_exception *fault)
9012 {
9013         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9014
9015         WARN_ON(!is_guest_mode(vcpu));
9016
9017         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9018                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9019                                   vmcs_read32(VM_EXIT_INTR_INFO),
9020                                   vmcs_readl(EXIT_QUALIFICATION));
9021         else
9022                 kvm_inject_page_fault(vcpu, fault);
9023 }
9024
9025 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9026                                         struct vmcs12 *vmcs12)
9027 {
9028         struct vcpu_vmx *vmx = to_vmx(vcpu);
9029         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9030
9031         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9032                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9033                     vmcs12->apic_access_addr >> maxphyaddr)
9034                         return false;
9035
9036                 /*
9037                  * Translate L1 physical address to host physical
9038                  * address for vmcs02. Keep the page pinned, so this
9039                  * physical address remains valid. We keep a reference
9040                  * to it so we can release it later.
9041                  */
9042                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9043                         nested_release_page(vmx->nested.apic_access_page);
9044                 vmx->nested.apic_access_page =
9045                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9046         }
9047
9048         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9049                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9050                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9051                         return false;
9052
9053                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9054                         nested_release_page(vmx->nested.virtual_apic_page);
9055                 vmx->nested.virtual_apic_page =
9056                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9057
9058                 /*
9059                  * Failing the vm entry is _not_ what the processor does
9060                  * but it's basically the only possibility we have.
9061                  * We could still enter the guest if CR8 load exits are
9062                  * enabled, CR8 store exits are enabled, and virtualize APIC
9063                  * access is disabled; in this case the processor would never
9064                  * use the TPR shadow and we could simply clear the bit from
9065                  * the execution control.  But such a configuration is useless,
9066                  * so let's keep the code simple.
9067                  */
9068                 if (!vmx->nested.virtual_apic_page)
9069                         return false;
9070         }
9071
9072         if (nested_cpu_has_posted_intr(vmcs12)) {
9073                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9074                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9075                         return false;
9076
9077                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9078                         kunmap(vmx->nested.pi_desc_page);
9079                         nested_release_page(vmx->nested.pi_desc_page);
9080                 }
9081                 vmx->nested.pi_desc_page =
9082                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9083                 if (!vmx->nested.pi_desc_page)
9084                         return false;
9085
9086                 vmx->nested.pi_desc =
9087                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9088                 if (!vmx->nested.pi_desc) {
9089                         nested_release_page_clean(vmx->nested.pi_desc_page);
9090                         return false;
9091                 }
9092                 vmx->nested.pi_desc =
9093                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9094                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9095                         (PAGE_SIZE - 1)));
9096         }
9097
9098         return true;
9099 }
9100
9101 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9102 {
9103         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9104         struct vcpu_vmx *vmx = to_vmx(vcpu);
9105
9106         if (vcpu->arch.virtual_tsc_khz == 0)
9107                 return;
9108
9109         /* Make sure short timeouts reliably trigger an immediate vmexit.
9110          * hrtimer_start does not guarantee this. */
9111         if (preemption_timeout <= 1) {
9112                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9113                 return;
9114         }
9115
9116         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9117         preemption_timeout *= 1000000;
9118         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9119         hrtimer_start(&vmx->nested.preemption_timer,
9120                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9121 }
9122
9123 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9124                                                 struct vmcs12 *vmcs12)
9125 {
9126         int maxphyaddr;
9127         u64 addr;
9128
9129         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9130                 return 0;
9131
9132         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9133                 WARN_ON(1);
9134                 return -EINVAL;
9135         }
9136         maxphyaddr = cpuid_maxphyaddr(vcpu);
9137
9138         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9139            ((addr + PAGE_SIZE) >> maxphyaddr))
9140                 return -EINVAL;
9141
9142         return 0;
9143 }
9144
9145 /*
9146  * Merge L0's and L1's MSR bitmap, return false to indicate that
9147  * we do not use the hardware.
9148  */
9149 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9150                                                struct vmcs12 *vmcs12)
9151 {
9152         int msr;
9153         struct page *page;
9154         unsigned long *msr_bitmap;
9155
9156         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9157                 return false;
9158
9159         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9160         if (!page) {
9161                 WARN_ON(1);
9162                 return false;
9163         }
9164         msr_bitmap = (unsigned long *)kmap(page);
9165         if (!msr_bitmap) {
9166                 nested_release_page_clean(page);
9167                 WARN_ON(1);
9168                 return false;
9169         }
9170
9171         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9172                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9173                         for (msr = 0x800; msr <= 0x8ff; msr++)
9174                                 nested_vmx_disable_intercept_for_msr(
9175                                         msr_bitmap,
9176                                         vmx_msr_bitmap_nested,
9177                                         msr, MSR_TYPE_R);
9178                 /* TPR is allowed */
9179                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9180                                 vmx_msr_bitmap_nested,
9181                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9182                                 MSR_TYPE_R | MSR_TYPE_W);
9183                 if (nested_cpu_has_vid(vmcs12)) {
9184                         /* EOI and self-IPI are allowed */
9185                         nested_vmx_disable_intercept_for_msr(
9186                                 msr_bitmap,
9187                                 vmx_msr_bitmap_nested,
9188                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9189                                 MSR_TYPE_W);
9190                         nested_vmx_disable_intercept_for_msr(
9191                                 msr_bitmap,
9192                                 vmx_msr_bitmap_nested,
9193                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9194                                 MSR_TYPE_W);
9195                 }
9196         } else {
9197                 /*
9198                  * Enable reading intercept of all the x2apic
9199                  * MSRs. We should not rely on vmcs12 to do any
9200                  * optimizations here, it may have been modified
9201                  * by L1.
9202                  */
9203                 for (msr = 0x800; msr <= 0x8ff; msr++)
9204                         __vmx_enable_intercept_for_msr(
9205                                 vmx_msr_bitmap_nested,
9206                                 msr,
9207                                 MSR_TYPE_R);
9208
9209                 __vmx_enable_intercept_for_msr(
9210                                 vmx_msr_bitmap_nested,
9211                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9212                                 MSR_TYPE_W);
9213                 __vmx_enable_intercept_for_msr(
9214                                 vmx_msr_bitmap_nested,
9215                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9216                                 MSR_TYPE_W);
9217                 __vmx_enable_intercept_for_msr(
9218                                 vmx_msr_bitmap_nested,
9219                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9220                                 MSR_TYPE_W);
9221         }
9222         kunmap(page);
9223         nested_release_page_clean(page);
9224
9225         return true;
9226 }
9227
9228 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9229                                            struct vmcs12 *vmcs12)
9230 {
9231         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9232             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9233             !nested_cpu_has_vid(vmcs12) &&
9234             !nested_cpu_has_posted_intr(vmcs12))
9235                 return 0;
9236
9237         /*
9238          * If virtualize x2apic mode is enabled,
9239          * virtualize apic access must be disabled.
9240          */
9241         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9242             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9243                 return -EINVAL;
9244
9245         /*
9246          * If virtual interrupt delivery is enabled,
9247          * we must exit on external interrupts.
9248          */
9249         if (nested_cpu_has_vid(vmcs12) &&
9250            !nested_exit_on_intr(vcpu))
9251                 return -EINVAL;
9252
9253         /*
9254          * bits 15:8 should be zero in posted_intr_nv,
9255          * the descriptor address has been already checked
9256          * in nested_get_vmcs12_pages.
9257          */
9258         if (nested_cpu_has_posted_intr(vmcs12) &&
9259            (!nested_cpu_has_vid(vmcs12) ||
9260             !nested_exit_intr_ack_set(vcpu) ||
9261             vmcs12->posted_intr_nv & 0xff00))
9262                 return -EINVAL;
9263
9264         /* tpr shadow is needed by all apicv features. */
9265         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9266                 return -EINVAL;
9267
9268         return 0;
9269 }
9270
9271 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9272                                        unsigned long count_field,
9273                                        unsigned long addr_field)
9274 {
9275         int maxphyaddr;
9276         u64 count, addr;
9277
9278         if (vmcs12_read_any(vcpu, count_field, &count) ||
9279             vmcs12_read_any(vcpu, addr_field, &addr)) {
9280                 WARN_ON(1);
9281                 return -EINVAL;
9282         }
9283         if (count == 0)
9284                 return 0;
9285         maxphyaddr = cpuid_maxphyaddr(vcpu);
9286         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9287             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9288                 pr_warn_ratelimited(
9289                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9290                         addr_field, maxphyaddr, count, addr);
9291                 return -EINVAL;
9292         }
9293         return 0;
9294 }
9295
9296 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9297                                                 struct vmcs12 *vmcs12)
9298 {
9299         if (vmcs12->vm_exit_msr_load_count == 0 &&
9300             vmcs12->vm_exit_msr_store_count == 0 &&
9301             vmcs12->vm_entry_msr_load_count == 0)
9302                 return 0; /* Fast path */
9303         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9304                                         VM_EXIT_MSR_LOAD_ADDR) ||
9305             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9306                                         VM_EXIT_MSR_STORE_ADDR) ||
9307             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9308                                         VM_ENTRY_MSR_LOAD_ADDR))
9309                 return -EINVAL;
9310         return 0;
9311 }
9312
9313 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9314                                        struct vmx_msr_entry *e)
9315 {
9316         /* x2APIC MSR accesses are not allowed */
9317         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9318                 return -EINVAL;
9319         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9320             e->index == MSR_IA32_UCODE_REV)
9321                 return -EINVAL;
9322         if (e->reserved != 0)
9323                 return -EINVAL;
9324         return 0;
9325 }
9326
9327 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9328                                      struct vmx_msr_entry *e)
9329 {
9330         if (e->index == MSR_FS_BASE ||
9331             e->index == MSR_GS_BASE ||
9332             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9333             nested_vmx_msr_check_common(vcpu, e))
9334                 return -EINVAL;
9335         return 0;
9336 }
9337
9338 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9339                                       struct vmx_msr_entry *e)
9340 {
9341         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9342             nested_vmx_msr_check_common(vcpu, e))
9343                 return -EINVAL;
9344         return 0;
9345 }
9346
9347 /*
9348  * Load guest's/host's msr at nested entry/exit.
9349  * return 0 for success, entry index for failure.
9350  */
9351 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9352 {
9353         u32 i;
9354         struct vmx_msr_entry e;
9355         struct msr_data msr;
9356
9357         msr.host_initiated = false;
9358         for (i = 0; i < count; i++) {
9359                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9360                                         &e, sizeof(e))) {
9361                         pr_warn_ratelimited(
9362                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9363                                 __func__, i, gpa + i * sizeof(e));
9364                         goto fail;
9365                 }
9366                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9367                         pr_warn_ratelimited(
9368                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9369                                 __func__, i, e.index, e.reserved);
9370                         goto fail;
9371                 }
9372                 msr.index = e.index;
9373                 msr.data = e.value;
9374                 if (kvm_set_msr(vcpu, &msr)) {
9375                         pr_warn_ratelimited(
9376                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9377                                 __func__, i, e.index, e.value);
9378                         goto fail;
9379                 }
9380         }
9381         return 0;
9382 fail:
9383         return i + 1;
9384 }
9385
9386 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9387 {
9388         u32 i;
9389         struct vmx_msr_entry e;
9390
9391         for (i = 0; i < count; i++) {
9392                 struct msr_data msr_info;
9393                 if (kvm_vcpu_read_guest(vcpu,
9394                                         gpa + i * sizeof(e),
9395                                         &e, 2 * sizeof(u32))) {
9396                         pr_warn_ratelimited(
9397                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9398                                 __func__, i, gpa + i * sizeof(e));
9399                         return -EINVAL;
9400                 }
9401                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9402                         pr_warn_ratelimited(
9403                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9404                                 __func__, i, e.index, e.reserved);
9405                         return -EINVAL;
9406                 }
9407                 msr_info.host_initiated = false;
9408                 msr_info.index = e.index;
9409                 if (kvm_get_msr(vcpu, &msr_info)) {
9410                         pr_warn_ratelimited(
9411                                 "%s cannot read MSR (%u, 0x%x)\n",
9412                                 __func__, i, e.index);
9413                         return -EINVAL;
9414                 }
9415                 if (kvm_vcpu_write_guest(vcpu,
9416                                          gpa + i * sizeof(e) +
9417                                              offsetof(struct vmx_msr_entry, value),
9418                                          &msr_info.data, sizeof(msr_info.data))) {
9419                         pr_warn_ratelimited(
9420                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9421                                 __func__, i, e.index, msr_info.data);
9422                         return -EINVAL;
9423                 }
9424         }
9425         return 0;
9426 }
9427
9428 /*
9429  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9430  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9431  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9432  * guest in a way that will both be appropriate to L1's requests, and our
9433  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9434  * function also has additional necessary side-effects, like setting various
9435  * vcpu->arch fields.
9436  */
9437 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9438 {
9439         struct vcpu_vmx *vmx = to_vmx(vcpu);
9440         u32 exec_control;
9441
9442         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9443         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9444         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9445         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9446         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9447         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9448         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9449         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9450         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9451         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9452         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9453         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9454         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9455         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9456         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9457         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9458         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9459         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9460         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9461         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9462         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9463         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9464         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9465         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9466         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9467         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9468         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9469         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9470         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9471         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9472         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9473         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9474         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9475         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9476         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9477         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9478
9479         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9480                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9481                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9482         } else {
9483                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9484                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9485         }
9486         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9487                 vmcs12->vm_entry_intr_info_field);
9488         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9489                 vmcs12->vm_entry_exception_error_code);
9490         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9491                 vmcs12->vm_entry_instruction_len);
9492         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9493                 vmcs12->guest_interruptibility_info);
9494         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9495         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9496         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9497                 vmcs12->guest_pending_dbg_exceptions);
9498         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9499         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9500
9501         if (nested_cpu_has_xsaves(vmcs12))
9502                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9503         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9504
9505         exec_control = vmcs12->pin_based_vm_exec_control;
9506         exec_control |= vmcs_config.pin_based_exec_ctrl;
9507         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9508
9509         if (nested_cpu_has_posted_intr(vmcs12)) {
9510                 /*
9511                  * Note that we use L0's vector here and in
9512                  * vmx_deliver_nested_posted_interrupt.
9513                  */
9514                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9515                 vmx->nested.pi_pending = false;
9516                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9517                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9518                         page_to_phys(vmx->nested.pi_desc_page) +
9519                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9520                         (PAGE_SIZE - 1)));
9521         } else
9522                 exec_control &= ~PIN_BASED_POSTED_INTR;
9523
9524         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9525
9526         vmx->nested.preemption_timer_expired = false;
9527         if (nested_cpu_has_preemption_timer(vmcs12))
9528                 vmx_start_preemption_timer(vcpu);
9529
9530         /*
9531          * Whether page-faults are trapped is determined by a combination of
9532          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9533          * If enable_ept, L0 doesn't care about page faults and we should
9534          * set all of these to L1's desires. However, if !enable_ept, L0 does
9535          * care about (at least some) page faults, and because it is not easy
9536          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9537          * to exit on each and every L2 page fault. This is done by setting
9538          * MASK=MATCH=0 and (see below) EB.PF=1.
9539          * Note that below we don't need special code to set EB.PF beyond the
9540          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9541          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9542          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9543          *
9544          * A problem with this approach (when !enable_ept) is that L1 may be
9545          * injected with more page faults than it asked for. This could have
9546          * caused problems, but in practice existing hypervisors don't care.
9547          * To fix this, we will need to emulate the PFEC checking (on the L1
9548          * page tables), using walk_addr(), when injecting PFs to L1.
9549          */
9550         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9551                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9552         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9553                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9554
9555         if (cpu_has_secondary_exec_ctrls()) {
9556                 exec_control = vmx_secondary_exec_control(vmx);
9557
9558                 /* Take the following fields only from vmcs12 */
9559                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9560                                   SECONDARY_EXEC_RDTSCP |
9561                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9562                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9563                                   SECONDARY_EXEC_PCOMMIT);
9564                 if (nested_cpu_has(vmcs12,
9565                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9566                         exec_control |= vmcs12->secondary_vm_exec_control;
9567
9568                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9569                         /*
9570                          * If translation failed, no matter: This feature asks
9571                          * to exit when accessing the given address, and if it
9572                          * can never be accessed, this feature won't do
9573                          * anything anyway.
9574                          */
9575                         if (!vmx->nested.apic_access_page)
9576                                 exec_control &=
9577                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9578                         else
9579                                 vmcs_write64(APIC_ACCESS_ADDR,
9580                                   page_to_phys(vmx->nested.apic_access_page));
9581                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9582                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9583                         exec_control |=
9584                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9585                         kvm_vcpu_reload_apic_access_page(vcpu);
9586                 }
9587
9588                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9589                         vmcs_write64(EOI_EXIT_BITMAP0,
9590                                 vmcs12->eoi_exit_bitmap0);
9591                         vmcs_write64(EOI_EXIT_BITMAP1,
9592                                 vmcs12->eoi_exit_bitmap1);
9593                         vmcs_write64(EOI_EXIT_BITMAP2,
9594                                 vmcs12->eoi_exit_bitmap2);
9595                         vmcs_write64(EOI_EXIT_BITMAP3,
9596                                 vmcs12->eoi_exit_bitmap3);
9597                         vmcs_write16(GUEST_INTR_STATUS,
9598                                 vmcs12->guest_intr_status);
9599                 }
9600
9601                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9602         }
9603
9604
9605         /*
9606          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9607          * Some constant fields are set here by vmx_set_constant_host_state().
9608          * Other fields are different per CPU, and will be set later when
9609          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9610          */
9611         vmx_set_constant_host_state(vmx);
9612
9613         /*
9614          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9615          * entry, but only if the current (host) sp changed from the value
9616          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9617          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9618          * here we just force the write to happen on entry.
9619          */
9620         vmx->host_rsp = 0;
9621
9622         exec_control = vmx_exec_control(vmx); /* L0's desires */
9623         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9624         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9625         exec_control &= ~CPU_BASED_TPR_SHADOW;
9626         exec_control |= vmcs12->cpu_based_vm_exec_control;
9627
9628         if (exec_control & CPU_BASED_TPR_SHADOW) {
9629                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9630                                 page_to_phys(vmx->nested.virtual_apic_page));
9631                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9632         }
9633
9634         if (cpu_has_vmx_msr_bitmap() &&
9635             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9636                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9637                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9638         } else
9639                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9640
9641         /*
9642          * Merging of IO bitmap not currently supported.
9643          * Rather, exit every time.
9644          */
9645         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9646         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9647
9648         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9649
9650         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9651          * bitwise-or of what L1 wants to trap for L2, and what we want to
9652          * trap. Note that CR0.TS also needs updating - we do this later.
9653          */
9654         update_exception_bitmap(vcpu);
9655         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9656         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9657
9658         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9659          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9660          * bits are further modified by vmx_set_efer() below.
9661          */
9662         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9663
9664         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9665          * emulated by vmx_set_efer(), below.
9666          */
9667         vm_entry_controls_init(vmx,
9668                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9669                         ~VM_ENTRY_IA32E_MODE) |
9670                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9671
9672         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9673                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9674                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9675         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9676                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9677
9678
9679         set_cr4_guest_host_mask(vmx);
9680
9681         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9682                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9683
9684         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9685                 vmcs_write64(TSC_OFFSET,
9686                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9687         else
9688                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9689
9690         if (enable_vpid) {
9691                 /*
9692                  * There is no direct mapping between vpid02 and vpid12, the
9693                  * vpid02 is per-vCPU for L0 and reused while the value of
9694                  * vpid12 is changed w/ one invvpid during nested vmentry.
9695                  * The vpid12 is allocated by L1 for L2, so it will not
9696                  * influence global bitmap(for vpid01 and vpid02 allocation)
9697                  * even if spawn a lot of nested vCPUs.
9698                  */
9699                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9700                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9701                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9702                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9703                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9704                         }
9705                 } else {
9706                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9707                         vmx_flush_tlb(vcpu);
9708                 }
9709
9710         }
9711
9712         if (nested_cpu_has_ept(vmcs12)) {
9713                 kvm_mmu_unload(vcpu);
9714                 nested_ept_init_mmu_context(vcpu);
9715         }
9716
9717         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9718                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9719         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9720                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9721         else
9722                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9723         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9724         vmx_set_efer(vcpu, vcpu->arch.efer);
9725
9726         /*
9727          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9728          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9729          * The CR0_READ_SHADOW is what L2 should have expected to read given
9730          * the specifications by L1; It's not enough to take
9731          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9732          * have more bits than L1 expected.
9733          */
9734         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9735         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9736
9737         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9738         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9739
9740         /* shadow page tables on either EPT or shadow page tables */
9741         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9742         kvm_mmu_reset_context(vcpu);
9743
9744         if (!enable_ept)
9745                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9746
9747         /*
9748          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9749          */
9750         if (enable_ept) {
9751                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9752                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9753                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9754                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9755         }
9756
9757         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9758         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9759 }
9760
9761 /*
9762  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9763  * for running an L2 nested guest.
9764  */
9765 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9766 {
9767         struct vmcs12 *vmcs12;
9768         struct vcpu_vmx *vmx = to_vmx(vcpu);
9769         int cpu;
9770         struct loaded_vmcs *vmcs02;
9771         bool ia32e;
9772         u32 msr_entry_idx;
9773
9774         if (!nested_vmx_check_permission(vcpu) ||
9775             !nested_vmx_check_vmcs12(vcpu))
9776                 return 1;
9777
9778         skip_emulated_instruction(vcpu);
9779         vmcs12 = get_vmcs12(vcpu);
9780
9781         if (enable_shadow_vmcs)
9782                 copy_shadow_to_vmcs12(vmx);
9783
9784         /*
9785          * The nested entry process starts with enforcing various prerequisites
9786          * on vmcs12 as required by the Intel SDM, and act appropriately when
9787          * they fail: As the SDM explains, some conditions should cause the
9788          * instruction to fail, while others will cause the instruction to seem
9789          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9790          * To speed up the normal (success) code path, we should avoid checking
9791          * for misconfigurations which will anyway be caught by the processor
9792          * when using the merged vmcs02.
9793          */
9794         if (vmcs12->launch_state == launch) {
9795                 nested_vmx_failValid(vcpu,
9796                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9797                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9798                 return 1;
9799         }
9800
9801         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9802             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9803                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9804                 return 1;
9805         }
9806
9807         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9808                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9809                 return 1;
9810         }
9811
9812         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9813                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9814                 return 1;
9815         }
9816
9817         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9818                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9819                 return 1;
9820         }
9821
9822         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9823                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9824                 return 1;
9825         }
9826
9827         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9828                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9829                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9830             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9831                                 vmx->nested.nested_vmx_secondary_ctls_low,
9832                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9833             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9834                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9835                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9836             !vmx_control_verify(vmcs12->vm_exit_controls,
9837                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9838                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9839             !vmx_control_verify(vmcs12->vm_entry_controls,
9840                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9841                                 vmx->nested.nested_vmx_entry_ctls_high))
9842         {
9843                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9844                 return 1;
9845         }
9846
9847         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9848             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9849                 nested_vmx_failValid(vcpu,
9850                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9851                 return 1;
9852         }
9853
9854         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9855             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9856                 nested_vmx_entry_failure(vcpu, vmcs12,
9857                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9858                 return 1;
9859         }
9860         if (vmcs12->vmcs_link_pointer != -1ull) {
9861                 nested_vmx_entry_failure(vcpu, vmcs12,
9862                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9863                 return 1;
9864         }
9865
9866         /*
9867          * If the load IA32_EFER VM-entry control is 1, the following checks
9868          * are performed on the field for the IA32_EFER MSR:
9869          * - Bits reserved in the IA32_EFER MSR must be 0.
9870          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9871          *   the IA-32e mode guest VM-exit control. It must also be identical
9872          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9873          *   CR0.PG) is 1.
9874          */
9875         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9876                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9877                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9878                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9879                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9880                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9881                         nested_vmx_entry_failure(vcpu, vmcs12,
9882                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9883                         return 1;
9884                 }
9885         }
9886
9887         /*
9888          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9889          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9890          * the values of the LMA and LME bits in the field must each be that of
9891          * the host address-space size VM-exit control.
9892          */
9893         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9894                 ia32e = (vmcs12->vm_exit_controls &
9895                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9896                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9897                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9898                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9899                         nested_vmx_entry_failure(vcpu, vmcs12,
9900                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9901                         return 1;
9902                 }
9903         }
9904
9905         /*
9906          * We're finally done with prerequisite checking, and can start with
9907          * the nested entry.
9908          */
9909
9910         vmcs02 = nested_get_current_vmcs02(vmx);
9911         if (!vmcs02)
9912                 return -ENOMEM;
9913
9914         enter_guest_mode(vcpu);
9915
9916         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9917
9918         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9919                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9920
9921         cpu = get_cpu();
9922         vmx->loaded_vmcs = vmcs02;
9923         vmx_vcpu_put(vcpu);
9924         vmx_vcpu_load(vcpu, cpu);
9925         vcpu->cpu = cpu;
9926         put_cpu();
9927
9928         vmx_segment_cache_clear(vmx);
9929
9930         prepare_vmcs02(vcpu, vmcs12);
9931
9932         msr_entry_idx = nested_vmx_load_msr(vcpu,
9933                                             vmcs12->vm_entry_msr_load_addr,
9934                                             vmcs12->vm_entry_msr_load_count);
9935         if (msr_entry_idx) {
9936                 leave_guest_mode(vcpu);
9937                 vmx_load_vmcs01(vcpu);
9938                 nested_vmx_entry_failure(vcpu, vmcs12,
9939                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9940                 return 1;
9941         }
9942
9943         vmcs12->launch_state = 1;
9944
9945         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9946                 return kvm_vcpu_halt(vcpu);
9947
9948         vmx->nested.nested_run_pending = 1;
9949
9950         /*
9951          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9952          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9953          * returned as far as L1 is concerned. It will only return (and set
9954          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9955          */
9956         return 1;
9957 }
9958
9959 /*
9960  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9961  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9962  * This function returns the new value we should put in vmcs12.guest_cr0.
9963  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9964  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9965  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9966  *     didn't trap the bit, because if L1 did, so would L0).
9967  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9968  *     been modified by L2, and L1 knows it. So just leave the old value of
9969  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9970  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9971  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9972  *     changed these bits, and therefore they need to be updated, but L0
9973  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9974  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9975  */
9976 static inline unsigned long
9977 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9978 {
9979         return
9980         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9981         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9982         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9983                         vcpu->arch.cr0_guest_owned_bits));
9984 }
9985
9986 static inline unsigned long
9987 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9988 {
9989         return
9990         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9991         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9992         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9993                         vcpu->arch.cr4_guest_owned_bits));
9994 }
9995
9996 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9997                                        struct vmcs12 *vmcs12)
9998 {
9999         u32 idt_vectoring;
10000         unsigned int nr;
10001
10002         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10003                 nr = vcpu->arch.exception.nr;
10004                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10005
10006                 if (kvm_exception_is_soft(nr)) {
10007                         vmcs12->vm_exit_instruction_len =
10008                                 vcpu->arch.event_exit_inst_len;
10009                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10010                 } else
10011                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10012
10013                 if (vcpu->arch.exception.has_error_code) {
10014                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10015                         vmcs12->idt_vectoring_error_code =
10016                                 vcpu->arch.exception.error_code;
10017                 }
10018
10019                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10020         } else if (vcpu->arch.nmi_injected) {
10021                 vmcs12->idt_vectoring_info_field =
10022                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10023         } else if (vcpu->arch.interrupt.pending) {
10024                 nr = vcpu->arch.interrupt.nr;
10025                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10026
10027                 if (vcpu->arch.interrupt.soft) {
10028                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10029                         vmcs12->vm_entry_instruction_len =
10030                                 vcpu->arch.event_exit_inst_len;
10031                 } else
10032                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10033
10034                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10035         }
10036 }
10037
10038 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10039 {
10040         struct vcpu_vmx *vmx = to_vmx(vcpu);
10041
10042         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10043             vmx->nested.preemption_timer_expired) {
10044                 if (vmx->nested.nested_run_pending)
10045                         return -EBUSY;
10046                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10047                 return 0;
10048         }
10049
10050         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10051                 if (vmx->nested.nested_run_pending ||
10052                     vcpu->arch.interrupt.pending)
10053                         return -EBUSY;
10054                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10055                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10056                                   INTR_INFO_VALID_MASK, 0);
10057                 /*
10058                  * The NMI-triggered VM exit counts as injection:
10059                  * clear this one and block further NMIs.
10060                  */
10061                 vcpu->arch.nmi_pending = 0;
10062                 vmx_set_nmi_mask(vcpu, true);
10063                 return 0;
10064         }
10065
10066         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10067             nested_exit_on_intr(vcpu)) {
10068                 if (vmx->nested.nested_run_pending)
10069                         return -EBUSY;
10070                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10071                 return 0;
10072         }
10073
10074         return vmx_complete_nested_posted_interrupt(vcpu);
10075 }
10076
10077 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10078 {
10079         ktime_t remaining =
10080                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10081         u64 value;
10082
10083         if (ktime_to_ns(remaining) <= 0)
10084                 return 0;
10085
10086         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10087         do_div(value, 1000000);
10088         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10089 }
10090
10091 /*
10092  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10093  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10094  * and this function updates it to reflect the changes to the guest state while
10095  * L2 was running (and perhaps made some exits which were handled directly by L0
10096  * without going back to L1), and to reflect the exit reason.
10097  * Note that we do not have to copy here all VMCS fields, just those that
10098  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10099  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10100  * which already writes to vmcs12 directly.
10101  */
10102 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10103                            u32 exit_reason, u32 exit_intr_info,
10104                            unsigned long exit_qualification)
10105 {
10106         /* update guest state fields: */
10107         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10108         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10109
10110         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10111         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10112         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10113
10114         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10115         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10116         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10117         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10118         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10119         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10120         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10121         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10122         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10123         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10124         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10125         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10126         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10127         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10128         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10129         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10130         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10131         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10132         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10133         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10134         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10135         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10136         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10137         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10138         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10139         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10140         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10141         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10142         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10143         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10144         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10145         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10146         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10147         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10148         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10149         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10150
10151         vmcs12->guest_interruptibility_info =
10152                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10153         vmcs12->guest_pending_dbg_exceptions =
10154                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10155         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10156                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10157         else
10158                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10159
10160         if (nested_cpu_has_preemption_timer(vmcs12)) {
10161                 if (vmcs12->vm_exit_controls &
10162                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10163                         vmcs12->vmx_preemption_timer_value =
10164                                 vmx_get_preemption_timer_value(vcpu);
10165                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10166         }
10167
10168         /*
10169          * In some cases (usually, nested EPT), L2 is allowed to change its
10170          * own CR3 without exiting. If it has changed it, we must keep it.
10171          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10172          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10173          *
10174          * Additionally, restore L2's PDPTR to vmcs12.
10175          */
10176         if (enable_ept) {
10177                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10178                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10179                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10180                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10181                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10182         }
10183
10184         if (nested_cpu_has_vid(vmcs12))
10185                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10186
10187         vmcs12->vm_entry_controls =
10188                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10189                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10190
10191         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10192                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10193                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10194         }
10195
10196         /* TODO: These cannot have changed unless we have MSR bitmaps and
10197          * the relevant bit asks not to trap the change */
10198         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10199                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10200         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10201                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10202         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10203         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10204         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10205         if (vmx_mpx_supported())
10206                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10207         if (nested_cpu_has_xsaves(vmcs12))
10208                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10209
10210         /* update exit information fields: */
10211
10212         vmcs12->vm_exit_reason = exit_reason;
10213         vmcs12->exit_qualification = exit_qualification;
10214
10215         vmcs12->vm_exit_intr_info = exit_intr_info;
10216         if ((vmcs12->vm_exit_intr_info &
10217              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10218             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10219                 vmcs12->vm_exit_intr_error_code =
10220                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10221         vmcs12->idt_vectoring_info_field = 0;
10222         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10223         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10224
10225         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10226                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10227                  * instead of reading the real value. */
10228                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10229
10230                 /*
10231                  * Transfer the event that L0 or L1 may wanted to inject into
10232                  * L2 to IDT_VECTORING_INFO_FIELD.
10233                  */
10234                 vmcs12_save_pending_event(vcpu, vmcs12);
10235         }
10236
10237         /*
10238          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10239          * preserved above and would only end up incorrectly in L1.
10240          */
10241         vcpu->arch.nmi_injected = false;
10242         kvm_clear_exception_queue(vcpu);
10243         kvm_clear_interrupt_queue(vcpu);
10244 }
10245
10246 /*
10247  * A part of what we need to when the nested L2 guest exits and we want to
10248  * run its L1 parent, is to reset L1's guest state to the host state specified
10249  * in vmcs12.
10250  * This function is to be called not only on normal nested exit, but also on
10251  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10252  * Failures During or After Loading Guest State").
10253  * This function should be called when the active VMCS is L1's (vmcs01).
10254  */
10255 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10256                                    struct vmcs12 *vmcs12)
10257 {
10258         struct kvm_segment seg;
10259
10260         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10261                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10262         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10263                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10264         else
10265                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10266         vmx_set_efer(vcpu, vcpu->arch.efer);
10267
10268         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10269         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10270         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10271         /*
10272          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10273          * actually changed, because it depends on the current state of
10274          * fpu_active (which may have changed).
10275          * Note that vmx_set_cr0 refers to efer set above.
10276          */
10277         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10278         /*
10279          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10280          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10281          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10282          */
10283         update_exception_bitmap(vcpu);
10284         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10285         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10286
10287         /*
10288          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10289          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10290          */
10291         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10292         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10293
10294         nested_ept_uninit_mmu_context(vcpu);
10295
10296         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10297         kvm_mmu_reset_context(vcpu);
10298
10299         if (!enable_ept)
10300                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10301
10302         if (enable_vpid) {
10303                 /*
10304                  * Trivially support vpid by letting L2s share their parent
10305                  * L1's vpid. TODO: move to a more elaborate solution, giving
10306                  * each L2 its own vpid and exposing the vpid feature to L1.
10307                  */
10308                 vmx_flush_tlb(vcpu);
10309         }
10310
10311
10312         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10313         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10314         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10315         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10316         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10317
10318         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10319         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10320                 vmcs_write64(GUEST_BNDCFGS, 0);
10321
10322         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10323                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10324                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10325         }
10326         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10327                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10328                         vmcs12->host_ia32_perf_global_ctrl);
10329
10330         /* Set L1 segment info according to Intel SDM
10331             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10332         seg = (struct kvm_segment) {
10333                 .base = 0,
10334                 .limit = 0xFFFFFFFF,
10335                 .selector = vmcs12->host_cs_selector,
10336                 .type = 11,
10337                 .present = 1,
10338                 .s = 1,
10339                 .g = 1
10340         };
10341         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10342                 seg.l = 1;
10343         else
10344                 seg.db = 1;
10345         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10346         seg = (struct kvm_segment) {
10347                 .base = 0,
10348                 .limit = 0xFFFFFFFF,
10349                 .type = 3,
10350                 .present = 1,
10351                 .s = 1,
10352                 .db = 1,
10353                 .g = 1
10354         };
10355         seg.selector = vmcs12->host_ds_selector;
10356         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10357         seg.selector = vmcs12->host_es_selector;
10358         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10359         seg.selector = vmcs12->host_ss_selector;
10360         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10361         seg.selector = vmcs12->host_fs_selector;
10362         seg.base = vmcs12->host_fs_base;
10363         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10364         seg.selector = vmcs12->host_gs_selector;
10365         seg.base = vmcs12->host_gs_base;
10366         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10367         seg = (struct kvm_segment) {
10368                 .base = vmcs12->host_tr_base,
10369                 .limit = 0x67,
10370                 .selector = vmcs12->host_tr_selector,
10371                 .type = 11,
10372                 .present = 1
10373         };
10374         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10375
10376         kvm_set_dr(vcpu, 7, 0x400);
10377         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10378
10379         if (cpu_has_vmx_msr_bitmap())
10380                 vmx_set_msr_bitmap(vcpu);
10381
10382         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10383                                 vmcs12->vm_exit_msr_load_count))
10384                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10385 }
10386
10387 /*
10388  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10389  * and modify vmcs12 to make it see what it would expect to see there if
10390  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10391  */
10392 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10393                               u32 exit_intr_info,
10394                               unsigned long exit_qualification)
10395 {
10396         struct vcpu_vmx *vmx = to_vmx(vcpu);
10397         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10398
10399         /* trying to cancel vmlaunch/vmresume is a bug */
10400         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10401
10402         leave_guest_mode(vcpu);
10403         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10404                        exit_qualification);
10405
10406         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10407                                  vmcs12->vm_exit_msr_store_count))
10408                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10409
10410         vmx_load_vmcs01(vcpu);
10411
10412         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10413             && nested_exit_intr_ack_set(vcpu)) {
10414                 int irq = kvm_cpu_get_interrupt(vcpu);
10415                 WARN_ON(irq < 0);
10416                 vmcs12->vm_exit_intr_info = irq |
10417                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10418         }
10419
10420         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10421                                        vmcs12->exit_qualification,
10422                                        vmcs12->idt_vectoring_info_field,
10423                                        vmcs12->vm_exit_intr_info,
10424                                        vmcs12->vm_exit_intr_error_code,
10425                                        KVM_ISA_VMX);
10426
10427         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10428         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10429         vmx_segment_cache_clear(vmx);
10430
10431         /* if no vmcs02 cache requested, remove the one we used */
10432         if (VMCS02_POOL_SIZE == 0)
10433                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10434
10435         load_vmcs12_host_state(vcpu, vmcs12);
10436
10437         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10438         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10439
10440         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10441         vmx->host_rsp = 0;
10442
10443         /* Unpin physical memory we referred to in vmcs02 */
10444         if (vmx->nested.apic_access_page) {
10445                 nested_release_page(vmx->nested.apic_access_page);
10446                 vmx->nested.apic_access_page = NULL;
10447         }
10448         if (vmx->nested.virtual_apic_page) {
10449                 nested_release_page(vmx->nested.virtual_apic_page);
10450                 vmx->nested.virtual_apic_page = NULL;
10451         }
10452         if (vmx->nested.pi_desc_page) {
10453                 kunmap(vmx->nested.pi_desc_page);
10454                 nested_release_page(vmx->nested.pi_desc_page);
10455                 vmx->nested.pi_desc_page = NULL;
10456                 vmx->nested.pi_desc = NULL;
10457         }
10458
10459         /*
10460          * We are now running in L2, mmu_notifier will force to reload the
10461          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10462          */
10463         kvm_vcpu_reload_apic_access_page(vcpu);
10464
10465         /*
10466          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10467          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10468          * success or failure flag accordingly.
10469          */
10470         if (unlikely(vmx->fail)) {
10471                 vmx->fail = 0;
10472                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10473         } else
10474                 nested_vmx_succeed(vcpu);
10475         if (enable_shadow_vmcs)
10476                 vmx->nested.sync_shadow_vmcs = true;
10477
10478         /* in case we halted in L2 */
10479         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10480 }
10481
10482 /*
10483  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10484  */
10485 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10486 {
10487         if (is_guest_mode(vcpu))
10488                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10489         free_nested(to_vmx(vcpu));
10490 }
10491
10492 /*
10493  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10494  * 23.7 "VM-entry failures during or after loading guest state" (this also
10495  * lists the acceptable exit-reason and exit-qualification parameters).
10496  * It should only be called before L2 actually succeeded to run, and when
10497  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10498  */
10499 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10500                         struct vmcs12 *vmcs12,
10501                         u32 reason, unsigned long qualification)
10502 {
10503         load_vmcs12_host_state(vcpu, vmcs12);
10504         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10505         vmcs12->exit_qualification = qualification;
10506         nested_vmx_succeed(vcpu);
10507         if (enable_shadow_vmcs)
10508                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10509 }
10510
10511 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10512                                struct x86_instruction_info *info,
10513                                enum x86_intercept_stage stage)
10514 {
10515         return X86EMUL_CONTINUE;
10516 }
10517
10518 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10519 {
10520         if (ple_gap)
10521                 shrink_ple_window(vcpu);
10522 }
10523
10524 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10525                                      struct kvm_memory_slot *slot)
10526 {
10527         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10528         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10529 }
10530
10531 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10532                                        struct kvm_memory_slot *slot)
10533 {
10534         kvm_mmu_slot_set_dirty(kvm, slot);
10535 }
10536
10537 static void vmx_flush_log_dirty(struct kvm *kvm)
10538 {
10539         kvm_flush_pml_buffers(kvm);
10540 }
10541
10542 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10543                                            struct kvm_memory_slot *memslot,
10544                                            gfn_t offset, unsigned long mask)
10545 {
10546         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10547 }
10548
10549 /*
10550  * This routine does the following things for vCPU which is going
10551  * to be blocked if VT-d PI is enabled.
10552  * - Store the vCPU to the wakeup list, so when interrupts happen
10553  *   we can find the right vCPU to wake up.
10554  * - Change the Posted-interrupt descriptor as below:
10555  *      'NDST' <-- vcpu->pre_pcpu
10556  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10557  * - If 'ON' is set during this process, which means at least one
10558  *   interrupt is posted for this vCPU, we cannot block it, in
10559  *   this case, return 1, otherwise, return 0.
10560  *
10561  */
10562 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10563 {
10564         unsigned long flags;
10565         unsigned int dest;
10566         struct pi_desc old, new;
10567         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10568
10569         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10570                 !irq_remapping_cap(IRQ_POSTING_CAP))
10571                 return 0;
10572
10573         vcpu->pre_pcpu = vcpu->cpu;
10574         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10575                           vcpu->pre_pcpu), flags);
10576         list_add_tail(&vcpu->blocked_vcpu_list,
10577                       &per_cpu(blocked_vcpu_on_cpu,
10578                       vcpu->pre_pcpu));
10579         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10580                                vcpu->pre_pcpu), flags);
10581
10582         do {
10583                 old.control = new.control = pi_desc->control;
10584
10585                 /*
10586                  * We should not block the vCPU if
10587                  * an interrupt is posted for it.
10588                  */
10589                 if (pi_test_on(pi_desc) == 1) {
10590                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10591                                           vcpu->pre_pcpu), flags);
10592                         list_del(&vcpu->blocked_vcpu_list);
10593                         spin_unlock_irqrestore(
10594                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10595                                         vcpu->pre_pcpu), flags);
10596                         vcpu->pre_pcpu = -1;
10597
10598                         return 1;
10599                 }
10600
10601                 WARN((pi_desc->sn == 1),
10602                      "Warning: SN field of posted-interrupts "
10603                      "is set before blocking\n");
10604
10605                 /*
10606                  * Since vCPU can be preempted during this process,
10607                  * vcpu->cpu could be different with pre_pcpu, we
10608                  * need to set pre_pcpu as the destination of wakeup
10609                  * notification event, then we can find the right vCPU
10610                  * to wakeup in wakeup handler if interrupts happen
10611                  * when the vCPU is in blocked state.
10612                  */
10613                 dest = cpu_physical_id(vcpu->pre_pcpu);
10614
10615                 if (x2apic_enabled())
10616                         new.ndst = dest;
10617                 else
10618                         new.ndst = (dest << 8) & 0xFF00;
10619
10620                 /* set 'NV' to 'wakeup vector' */
10621                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10622         } while (cmpxchg(&pi_desc->control, old.control,
10623                         new.control) != old.control);
10624
10625         return 0;
10626 }
10627
10628 static void vmx_post_block(struct kvm_vcpu *vcpu)
10629 {
10630         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10631         struct pi_desc old, new;
10632         unsigned int dest;
10633         unsigned long flags;
10634
10635         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10636                 !irq_remapping_cap(IRQ_POSTING_CAP))
10637                 return;
10638
10639         do {
10640                 old.control = new.control = pi_desc->control;
10641
10642                 dest = cpu_physical_id(vcpu->cpu);
10643
10644                 if (x2apic_enabled())
10645                         new.ndst = dest;
10646                 else
10647                         new.ndst = (dest << 8) & 0xFF00;
10648
10649                 /* Allow posting non-urgent interrupts */
10650                 new.sn = 0;
10651
10652                 /* set 'NV' to 'notification vector' */
10653                 new.nv = POSTED_INTR_VECTOR;
10654         } while (cmpxchg(&pi_desc->control, old.control,
10655                         new.control) != old.control);
10656
10657         if(vcpu->pre_pcpu != -1) {
10658                 spin_lock_irqsave(
10659                         &per_cpu(blocked_vcpu_on_cpu_lock,
10660                         vcpu->pre_pcpu), flags);
10661                 list_del(&vcpu->blocked_vcpu_list);
10662                 spin_unlock_irqrestore(
10663                         &per_cpu(blocked_vcpu_on_cpu_lock,
10664                         vcpu->pre_pcpu), flags);
10665                 vcpu->pre_pcpu = -1;
10666         }
10667 }
10668
10669 /*
10670  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10671  *
10672  * @kvm: kvm
10673  * @host_irq: host irq of the interrupt
10674  * @guest_irq: gsi of the interrupt
10675  * @set: set or unset PI
10676  * returns 0 on success, < 0 on failure
10677  */
10678 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10679                               uint32_t guest_irq, bool set)
10680 {
10681         struct kvm_kernel_irq_routing_entry *e;
10682         struct kvm_irq_routing_table *irq_rt;
10683         struct kvm_lapic_irq irq;
10684         struct kvm_vcpu *vcpu;
10685         struct vcpu_data vcpu_info;
10686         int idx, ret = -EINVAL;
10687
10688         if (!kvm_arch_has_assigned_device(kvm) ||
10689                 !irq_remapping_cap(IRQ_POSTING_CAP))
10690                 return 0;
10691
10692         idx = srcu_read_lock(&kvm->irq_srcu);
10693         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10694         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10695
10696         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10697                 if (e->type != KVM_IRQ_ROUTING_MSI)
10698                         continue;
10699                 /*
10700                  * VT-d PI cannot support posting multicast/broadcast
10701                  * interrupts to a vCPU, we still use interrupt remapping
10702                  * for these kind of interrupts.
10703                  *
10704                  * For lowest-priority interrupts, we only support
10705                  * those with single CPU as the destination, e.g. user
10706                  * configures the interrupts via /proc/irq or uses
10707                  * irqbalance to make the interrupts single-CPU.
10708                  *
10709                  * We will support full lowest-priority interrupt later.
10710                  */
10711
10712                 kvm_set_msi_irq(e, &irq);
10713                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10714                         continue;
10715
10716                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10717                 vcpu_info.vector = irq.vector;
10718
10719                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10720                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10721
10722                 if (set)
10723                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10724                 else {
10725                         /* suppress notification event before unposting */
10726                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10727                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10728                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10729                 }
10730
10731                 if (ret < 0) {
10732                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10733                                         __func__);
10734                         goto out;
10735                 }
10736         }
10737
10738         ret = 0;
10739 out:
10740         srcu_read_unlock(&kvm->irq_srcu, idx);
10741         return ret;
10742 }
10743
10744 static struct kvm_x86_ops vmx_x86_ops = {
10745         .cpu_has_kvm_support = cpu_has_kvm_support,
10746         .disabled_by_bios = vmx_disabled_by_bios,
10747         .hardware_setup = hardware_setup,
10748         .hardware_unsetup = hardware_unsetup,
10749         .check_processor_compatibility = vmx_check_processor_compat,
10750         .hardware_enable = hardware_enable,
10751         .hardware_disable = hardware_disable,
10752         .cpu_has_accelerated_tpr = report_flexpriority,
10753         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10754
10755         .vcpu_create = vmx_create_vcpu,
10756         .vcpu_free = vmx_free_vcpu,
10757         .vcpu_reset = vmx_vcpu_reset,
10758
10759         .prepare_guest_switch = vmx_save_host_state,
10760         .vcpu_load = vmx_vcpu_load,
10761         .vcpu_put = vmx_vcpu_put,
10762
10763         .update_bp_intercept = update_exception_bitmap,
10764         .get_msr = vmx_get_msr,
10765         .set_msr = vmx_set_msr,
10766         .get_segment_base = vmx_get_segment_base,
10767         .get_segment = vmx_get_segment,
10768         .set_segment = vmx_set_segment,
10769         .get_cpl = vmx_get_cpl,
10770         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10771         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10772         .decache_cr3 = vmx_decache_cr3,
10773         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10774         .set_cr0 = vmx_set_cr0,
10775         .set_cr3 = vmx_set_cr3,
10776         .set_cr4 = vmx_set_cr4,
10777         .set_efer = vmx_set_efer,
10778         .get_idt = vmx_get_idt,
10779         .set_idt = vmx_set_idt,
10780         .get_gdt = vmx_get_gdt,
10781         .set_gdt = vmx_set_gdt,
10782         .get_dr6 = vmx_get_dr6,
10783         .set_dr6 = vmx_set_dr6,
10784         .set_dr7 = vmx_set_dr7,
10785         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10786         .cache_reg = vmx_cache_reg,
10787         .get_rflags = vmx_get_rflags,
10788         .set_rflags = vmx_set_rflags,
10789         .fpu_activate = vmx_fpu_activate,
10790         .fpu_deactivate = vmx_fpu_deactivate,
10791
10792         .tlb_flush = vmx_flush_tlb,
10793
10794         .run = vmx_vcpu_run,
10795         .handle_exit = vmx_handle_exit,
10796         .skip_emulated_instruction = skip_emulated_instruction,
10797         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10798         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10799         .patch_hypercall = vmx_patch_hypercall,
10800         .set_irq = vmx_inject_irq,
10801         .set_nmi = vmx_inject_nmi,
10802         .queue_exception = vmx_queue_exception,
10803         .cancel_injection = vmx_cancel_injection,
10804         .interrupt_allowed = vmx_interrupt_allowed,
10805         .nmi_allowed = vmx_nmi_allowed,
10806         .get_nmi_mask = vmx_get_nmi_mask,
10807         .set_nmi_mask = vmx_set_nmi_mask,
10808         .enable_nmi_window = enable_nmi_window,
10809         .enable_irq_window = enable_irq_window,
10810         .update_cr8_intercept = update_cr8_intercept,
10811         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10812         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10813         .cpu_uses_apicv = vmx_cpu_uses_apicv,
10814         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10815         .hwapic_irr_update = vmx_hwapic_irr_update,
10816         .hwapic_isr_update = vmx_hwapic_isr_update,
10817         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10818         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10819
10820         .set_tss_addr = vmx_set_tss_addr,
10821         .get_tdp_level = get_ept_level,
10822         .get_mt_mask = vmx_get_mt_mask,
10823
10824         .get_exit_info = vmx_get_exit_info,
10825
10826         .get_lpage_level = vmx_get_lpage_level,
10827
10828         .cpuid_update = vmx_cpuid_update,
10829
10830         .rdtscp_supported = vmx_rdtscp_supported,
10831         .invpcid_supported = vmx_invpcid_supported,
10832
10833         .set_supported_cpuid = vmx_set_supported_cpuid,
10834
10835         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10836
10837         .read_tsc_offset = vmx_read_tsc_offset,
10838         .write_tsc_offset = vmx_write_tsc_offset,
10839         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10840         .read_l1_tsc = vmx_read_l1_tsc,
10841
10842         .set_tdp_cr3 = vmx_set_cr3,
10843
10844         .check_intercept = vmx_check_intercept,
10845         .handle_external_intr = vmx_handle_external_intr,
10846         .mpx_supported = vmx_mpx_supported,
10847         .xsaves_supported = vmx_xsaves_supported,
10848
10849         .check_nested_events = vmx_check_nested_events,
10850
10851         .sched_in = vmx_sched_in,
10852
10853         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10854         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10855         .flush_log_dirty = vmx_flush_log_dirty,
10856         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10857
10858         .pre_block = vmx_pre_block,
10859         .post_block = vmx_post_block,
10860
10861         .pmu_ops = &intel_pmu_ops,
10862
10863         .update_pi_irte = vmx_update_pi_irte,
10864 };
10865
10866 static int __init vmx_init(void)
10867 {
10868         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10869                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10870         if (r)
10871                 return r;
10872
10873 #ifdef CONFIG_KEXEC_CORE
10874         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10875                            crash_vmclear_local_loaded_vmcss);
10876 #endif
10877
10878         return 0;
10879 }
10880
10881 static void __exit vmx_exit(void)
10882 {
10883 #ifdef CONFIG_KEXEC_CORE
10884         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10885         synchronize_rcu();
10886 #endif
10887
10888         kvm_exit();
10889 }
10890
10891 module_init(vmx_init)
10892 module_exit(vmx_exit)