arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * ple_gap:    upper bound on the amount of time between two successive
 120  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 121  *             According to test, this time is usually smaller than 128 cycles.
 122  * ple_window: upper bound on the amount of time a guest is allowed to execute
 123  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 124  *             less than 2^12 cycles
 125  * Time is measured based on a counter that runs at the same rate as the TSC,
 126  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 127  */
 128 #define KVM_VMX_DEFAULT_PLE_GAP           128
 129 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 130 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 131 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 132 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 133                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 134
 135 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 136 module_param(ple_gap, int, S_IRUGO);
 137
 138 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 139 module_param(ple_window, int, S_IRUGO);
 140
 141 /* Default doubles per-vcpu window every exit. */
 142 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 143 module_param(ple_window_grow, int, S_IRUGO);
 144
 145 /* Default resets per-vcpu window every exit to ple_window. */
 146 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 147 module_param(ple_window_shrink, int, S_IRUGO);
 148
 149 /* Default is to compute the maximum so we can never overflow. */
 150 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 151 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 152 module_param(ple_window_max, int, S_IRUGO);
 153
 154 extern const ulong vmx_return;
 155
 156 #define NR_AUTOLOAD_MSRS 8
 157 #define VMCS02_POOL_SIZE 1
 158
 159 struct vmcs {
 160         u32 revision_id;
 161         u32 abort;
 162         char data[0];
 163 };
 164
 165 /*
 166  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 167  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 168  * loaded on this CPU (so we can clear them if the CPU goes down).
 169  */
 170 struct loaded_vmcs {
 171         struct vmcs *vmcs;
 172         int cpu;
 173         int launched;
 174         struct list_head loaded_vmcss_on_cpu_link;
 175 };
 176
 177 struct shared_msr_entry {
 178         unsigned index;
 179         u64 data;
 180         u64 mask;
 181 };
 182
 183 /*
 184  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 185  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 186  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 187  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 188  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 189  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 190  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 191  * underlying hardware which will be used to run L2.
 192  * This structure is packed to ensure that its layout is identical across
 193  * machines (necessary for live migration).
 194  * If there are changes in this struct, VMCS12_REVISION must be changed.
 195  */
 196 typedef u64 natural_width;
 197 struct __packed vmcs12 {
 198         /* According to the Intel spec, a VMCS region must start with the
 199          * following two fields. Then follow implementation-specific data.
 200          */
 201         u32 revision_id;
 202         u32 abort;
 203
 204         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 205         u32 padding[7]; /* room for future expansion */
 206
 207         u64 io_bitmap_a;
 208         u64 io_bitmap_b;
 209         u64 msr_bitmap;
 210         u64 vm_exit_msr_store_addr;
 211         u64 vm_exit_msr_load_addr;
 212         u64 vm_entry_msr_load_addr;
 213         u64 tsc_offset;
 214         u64 virtual_apic_page_addr;
 215         u64 apic_access_addr;
 216         u64 ept_pointer;
 217         u64 guest_physical_address;
 218         u64 vmcs_link_pointer;
 219         u64 guest_ia32_debugctl;
 220         u64 guest_ia32_pat;
 221         u64 guest_ia32_efer;
 222         u64 guest_ia32_perf_global_ctrl;
 223         u64 guest_pdptr0;
 224         u64 guest_pdptr1;
 225         u64 guest_pdptr2;
 226         u64 guest_pdptr3;
 227         u64 guest_bndcfgs;
 228         u64 host_ia32_pat;
 229         u64 host_ia32_efer;
 230         u64 host_ia32_perf_global_ctrl;
 231         u64 padding64[8]; /* room for future expansion */
 232         /*
 233          * To allow migration of L1 (complete with its L2 guests) between
 234          * machines of different natural widths (32 or 64 bit), we cannot have
 235          * unsigned long fields with no explict size. We use u64 (aliased
 236          * natural_width) instead. Luckily, x86 is little-endian.
 237          */
 238         natural_width cr0_guest_host_mask;
 239         natural_width cr4_guest_host_mask;
 240         natural_width cr0_read_shadow;
 241         natural_width cr4_read_shadow;
 242         natural_width cr3_target_value0;
 243         natural_width cr3_target_value1;
 244         natural_width cr3_target_value2;
 245         natural_width cr3_target_value3;
 246         natural_width exit_qualification;
 247         natural_width guest_linear_address;
 248         natural_width guest_cr0;
 249         natural_width guest_cr3;
 250         natural_width guest_cr4;
 251         natural_width guest_es_base;
 252         natural_width guest_cs_base;
 253         natural_width guest_ss_base;
 254         natural_width guest_ds_base;
 255         natural_width guest_fs_base;
 256         natural_width guest_gs_base;
 257         natural_width guest_ldtr_base;
 258         natural_width guest_tr_base;
 259         natural_width guest_gdtr_base;
 260         natural_width guest_idtr_base;
 261         natural_width guest_dr7;
 262         natural_width guest_rsp;
 263         natural_width guest_rip;
 264         natural_width guest_rflags;
 265         natural_width guest_pending_dbg_exceptions;
 266         natural_width guest_sysenter_esp;
 267         natural_width guest_sysenter_eip;
 268         natural_width host_cr0;
 269         natural_width host_cr3;
 270         natural_width host_cr4;
 271         natural_width host_fs_base;
 272         natural_width host_gs_base;
 273         natural_width host_tr_base;
 274         natural_width host_gdtr_base;
 275         natural_width host_idtr_base;
 276         natural_width host_ia32_sysenter_esp;
 277         natural_width host_ia32_sysenter_eip;
 278         natural_width host_rsp;
 279         natural_width host_rip;
 280         natural_width paddingl[8]; /* room for future expansion */
 281         u32 pin_based_vm_exec_control;
 282         u32 cpu_based_vm_exec_control;
 283         u32 exception_bitmap;
 284         u32 page_fault_error_code_mask;
 285         u32 page_fault_error_code_match;
 286         u32 cr3_target_count;
 287         u32 vm_exit_controls;
 288         u32 vm_exit_msr_store_count;
 289         u32 vm_exit_msr_load_count;
 290         u32 vm_entry_controls;
 291         u32 vm_entry_msr_load_count;
 292         u32 vm_entry_intr_info_field;
 293         u32 vm_entry_exception_error_code;
 294         u32 vm_entry_instruction_len;
 295         u32 tpr_threshold;
 296         u32 secondary_vm_exec_control;
 297         u32 vm_instruction_error;
 298         u32 vm_exit_reason;
 299         u32 vm_exit_intr_info;
 300         u32 vm_exit_intr_error_code;
 301         u32 idt_vectoring_info_field;
 302         u32 idt_vectoring_error_code;
 303         u32 vm_exit_instruction_len;
 304         u32 vmx_instruction_info;
 305         u32 guest_es_limit;
 306         u32 guest_cs_limit;
 307         u32 guest_ss_limit;
 308         u32 guest_ds_limit;
 309         u32 guest_fs_limit;
 310         u32 guest_gs_limit;
 311         u32 guest_ldtr_limit;
 312         u32 guest_tr_limit;
 313         u32 guest_gdtr_limit;
 314         u32 guest_idtr_limit;
 315         u32 guest_es_ar_bytes;
 316         u32 guest_cs_ar_bytes;
 317         u32 guest_ss_ar_bytes;
 318         u32 guest_ds_ar_bytes;
 319         u32 guest_fs_ar_bytes;
 320         u32 guest_gs_ar_bytes;
 321         u32 guest_ldtr_ar_bytes;
 322         u32 guest_tr_ar_bytes;
 323         u32 guest_interruptibility_info;
 324         u32 guest_activity_state;
 325         u32 guest_sysenter_cs;
 326         u32 host_ia32_sysenter_cs;
 327         u32 vmx_preemption_timer_value;
 328         u32 padding32[7]; /* room for future expansion */
 329         u16 virtual_processor_id;
 330         u16 guest_es_selector;
 331         u16 guest_cs_selector;
 332         u16 guest_ss_selector;
 333         u16 guest_ds_selector;
 334         u16 guest_fs_selector;
 335         u16 guest_gs_selector;
 336         u16 guest_ldtr_selector;
 337         u16 guest_tr_selector;
 338         u16 host_es_selector;
 339         u16 host_cs_selector;
 340         u16 host_ss_selector;
 341         u16 host_ds_selector;
 342         u16 host_fs_selector;
 343         u16 host_gs_selector;
 344         u16 host_tr_selector;
 345 };
 346
 347 /*
 348  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 349  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 350  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 351  */
 352 #define VMCS12_REVISION 0x11e57ed0
 353
 354 /*
 355  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 356  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 357  * current implementation, 4K are reserved to avoid future complications.
 358  */
 359 #define VMCS12_SIZE 0x1000
 360
 361 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 362 struct vmcs02_list {
 363         struct list_head list;
 364         gpa_t vmptr;
 365         struct loaded_vmcs vmcs02;
 366 };
 367
 368 /*
 369  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 370  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 371  */
 372 struct nested_vmx {
 373         /* Has the level1 guest done vmxon? */
 374         bool vmxon;
 375         gpa_t vmxon_ptr;
 376
 377         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 378         gpa_t current_vmptr;
 379         /* The host-usable pointer to the above */
 380         struct page *current_vmcs12_page;
 381         struct vmcs12 *current_vmcs12;
 382         struct vmcs *current_shadow_vmcs;
 383         /*
 384          * Indicates if the shadow vmcs must be updated with the
 385          * data hold by vmcs12
 386          */
 387         bool sync_shadow_vmcs;
 388
 389         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 390         struct list_head vmcs02_pool;
 391         int vmcs02_num;
 392         u64 vmcs01_tsc_offset;
 393         /* L2 must run next, and mustn't decide to exit to L1. */
 394         bool nested_run_pending;
 395         /*
 396          * Guest pages referred to in vmcs02 with host-physical pointers, so
 397          * we must keep them pinned while L2 runs.
 398          */
 399         struct page *apic_access_page;
 400         struct page *virtual_apic_page;
 401         u64 msr_ia32_feature_control;
 402
 403         struct hrtimer preemption_timer;
 404         bool preemption_timer_expired;
 405
 406         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 407         u64 vmcs01_debugctl;
 408 };
 409
 410 #define POSTED_INTR_ON  0
 411 /* Posted-Interrupt Descriptor */
 412 struct pi_desc {
 413         u32 pir[8];     /* Posted interrupt requested */
 414         u32 control;    /* bit 0 of control is outstanding notification bit */
 415         u32 rsvd[7];
 416 } __aligned(64);
 417
 418 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 419 {
 420         return test_and_set_bit(POSTED_INTR_ON,
 421                         (unsigned long *)&pi_desc->control);
 422 }
 423
 424 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 425 {
 426         return test_and_clear_bit(POSTED_INTR_ON,
 427                         (unsigned long *)&pi_desc->control);
 428 }
 429
 430 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 431 {
 432         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 433 }
 434
 435 struct vcpu_vmx {
 436         struct kvm_vcpu       vcpu;
 437         unsigned long         host_rsp;
 438         u8                    fail;
 439         bool                  nmi_known_unmasked;
 440         u32                   exit_intr_info;
 441         u32                   idt_vectoring_info;
 442         ulong                 rflags;
 443         struct shared_msr_entry *guest_msrs;
 444         int                   nmsrs;
 445         int                   save_nmsrs;
 446         unsigned long         host_idt_base;
 447 #ifdef CONFIG_X86_64
 448         u64                   msr_host_kernel_gs_base;
 449         u64                   msr_guest_kernel_gs_base;
 450 #endif
 451         u32 vm_entry_controls_shadow;
 452         u32 vm_exit_controls_shadow;
 453         /*
 454          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 455          * non-nested (L1) guest, it always points to vmcs01. For a nested
 456          * guest (L2), it points to a different VMCS.
 457          */
 458         struct loaded_vmcs    vmcs01;
 459         struct loaded_vmcs   *loaded_vmcs;
 460         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 461         struct msr_autoload {
 462                 unsigned nr;
 463                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 464                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 465         } msr_autoload;
 466         struct {
 467                 int           loaded;
 468                 u16           fs_sel, gs_sel, ldt_sel;
 469 #ifdef CONFIG_X86_64
 470                 u16           ds_sel, es_sel;
 471 #endif
 472                 int           gs_ldt_reload_needed;
 473                 int           fs_reload_needed;
 474                 u64           msr_host_bndcfgs;
 475         } host_state;
 476         struct {
 477                 int vm86_active;
 478                 ulong save_rflags;
 479                 struct kvm_segment segs[8];
 480         } rmode;
 481         struct {
 482                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 483                 struct kvm_save_segment {
 484                         u16 selector;
 485                         unsigned long base;
 486                         u32 limit;
 487                         u32 ar;
 488                 } seg[8];
 489         } segment_cache;
 490         int vpid;
 491         bool emulation_required;
 492
 493         /* Support for vnmi-less CPUs */
 494         int soft_vnmi_blocked;
 495         ktime_t entry_time;
 496         s64 vnmi_blocked_time;
 497         u32 exit_reason;
 498
 499         bool rdtscp_enabled;
 500
 501         /* Posted interrupt descriptor */
 502         struct pi_desc pi_desc;
 503
 504         /* Support for a guest hypervisor (nested VMX) */
 505         struct nested_vmx nested;
 506
 507         /* Dynamic PLE window. */
 508         int ple_window;
 509         bool ple_window_dirty;
 510 };
 511
 512 enum segment_cache_field {
 513         SEG_FIELD_SEL = 0,
 514         SEG_FIELD_BASE = 1,
 515         SEG_FIELD_LIMIT = 2,
 516         SEG_FIELD_AR = 3,
 517
 518         SEG_FIELD_NR = 4
 519 };
 520
 521 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 522 {
 523         return container_of(vcpu, struct vcpu_vmx, vcpu);
 524 }
 525
 526 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 527 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 528 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 529                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 530
 531
 532 static unsigned long shadow_read_only_fields[] = {
 533         /*
 534          * We do NOT shadow fields that are modified when L0
 535          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 536          * VMXON...) executed by L1.
 537          * For example, VM_INSTRUCTION_ERROR is read
 538          * by L1 if a vmx instruction fails (part of the error path).
 539          * Note the code assumes this logic. If for some reason
 540          * we start shadowing these fields then we need to
 541          * force a shadow sync when L0 emulates vmx instructions
 542          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 543          * by nested_vmx_failValid)
 544          */
 545         VM_EXIT_REASON,
 546         VM_EXIT_INTR_INFO,
 547         VM_EXIT_INSTRUCTION_LEN,
 548         IDT_VECTORING_INFO_FIELD,
 549         IDT_VECTORING_ERROR_CODE,
 550         VM_EXIT_INTR_ERROR_CODE,
 551         EXIT_QUALIFICATION,
 552         GUEST_LINEAR_ADDRESS,
 553         GUEST_PHYSICAL_ADDRESS
 554 };
 555 static int max_shadow_read_only_fields =
 556         ARRAY_SIZE(shadow_read_only_fields);
 557
 558 static unsigned long shadow_read_write_fields[] = {
 559         TPR_THRESHOLD,
 560         GUEST_RIP,
 561         GUEST_RSP,
 562         GUEST_CR0,
 563         GUEST_CR3,
 564         GUEST_CR4,
 565         GUEST_INTERRUPTIBILITY_INFO,
 566         GUEST_RFLAGS,
 567         GUEST_CS_SELECTOR,
 568         GUEST_CS_AR_BYTES,
 569         GUEST_CS_LIMIT,
 570         GUEST_CS_BASE,
 571         GUEST_ES_BASE,
 572         GUEST_BNDCFGS,
 573         CR0_GUEST_HOST_MASK,
 574         CR0_READ_SHADOW,
 575         CR4_READ_SHADOW,
 576         TSC_OFFSET,
 577         EXCEPTION_BITMAP,
 578         CPU_BASED_VM_EXEC_CONTROL,
 579         VM_ENTRY_EXCEPTION_ERROR_CODE,
 580         VM_ENTRY_INTR_INFO_FIELD,
 581         VM_ENTRY_INSTRUCTION_LEN,
 582         VM_ENTRY_EXCEPTION_ERROR_CODE,
 583         HOST_FS_BASE,
 584         HOST_GS_BASE,
 585         HOST_FS_SELECTOR,
 586         HOST_GS_SELECTOR
 587 };
 588 static int max_shadow_read_write_fields =
 589         ARRAY_SIZE(shadow_read_write_fields);
 590
 591 static const unsigned short vmcs_field_to_offset_table[] = {
 592         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 593         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 594         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 595         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 596         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 597         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 598         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 599         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 600         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 601         FIELD(HOST_ES_SELECTOR, host_es_selector),
 602         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 603         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 604         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 605         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 606         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 607         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 608         FIELD64(IO_BITMAP_A, io_bitmap_a),
 609         FIELD64(IO_BITMAP_B, io_bitmap_b),
 610         FIELD64(MSR_BITMAP, msr_bitmap),
 611         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 612         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 613         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 614         FIELD64(TSC_OFFSET, tsc_offset),
 615         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 616         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 617         FIELD64(EPT_POINTER, ept_pointer),
 618         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 619         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 620         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 621         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 622         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 623         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 624         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 625         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 626         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 627         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 628         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 629         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 630         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 631         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 632         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 633         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 634         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 635         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 636         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 637         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 638         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 639         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 640         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 641         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 642         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 643         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 644         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 645         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 646         FIELD(TPR_THRESHOLD, tpr_threshold),
 647         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 648         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 649         FIELD(VM_EXIT_REASON, vm_exit_reason),
 650         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 651         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 652         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 653         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 654         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 655         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 656         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 657         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 658         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 659         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 660         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 661         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 662         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 663         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 664         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 665         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 666         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 667         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 668         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 669         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 670         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 671         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 672         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 673         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 674         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 675         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 676         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 677         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 678         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 679         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 680         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 681         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 682         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 683         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 684         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 685         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 686         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 687         FIELD(EXIT_QUALIFICATION, exit_qualification),
 688         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 689         FIELD(GUEST_CR0, guest_cr0),
 690         FIELD(GUEST_CR3, guest_cr3),
 691         FIELD(GUEST_CR4, guest_cr4),
 692         FIELD(GUEST_ES_BASE, guest_es_base),
 693         FIELD(GUEST_CS_BASE, guest_cs_base),
 694         FIELD(GUEST_SS_BASE, guest_ss_base),
 695         FIELD(GUEST_DS_BASE, guest_ds_base),
 696         FIELD(GUEST_FS_BASE, guest_fs_base),
 697         FIELD(GUEST_GS_BASE, guest_gs_base),
 698         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 699         FIELD(GUEST_TR_BASE, guest_tr_base),
 700         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 701         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 702         FIELD(GUEST_DR7, guest_dr7),
 703         FIELD(GUEST_RSP, guest_rsp),
 704         FIELD(GUEST_RIP, guest_rip),
 705         FIELD(GUEST_RFLAGS, guest_rflags),
 706         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 707         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 708         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 709         FIELD(HOST_CR0, host_cr0),
 710         FIELD(HOST_CR3, host_cr3),
 711         FIELD(HOST_CR4, host_cr4),
 712         FIELD(HOST_FS_BASE, host_fs_base),
 713         FIELD(HOST_GS_BASE, host_gs_base),
 714         FIELD(HOST_TR_BASE, host_tr_base),
 715         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 716         FIELD(HOST_IDTR_BASE, host_idtr_base),
 717         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 718         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 719         FIELD(HOST_RSP, host_rsp),
 720         FIELD(HOST_RIP, host_rip),
 721 };
 722 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 723
 724 static inline short vmcs_field_to_offset(unsigned long field)
 725 {
 726         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 727                 return -1;
 728         return vmcs_field_to_offset_table[field];
 729 }
 730
 731 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 732 {
 733         return to_vmx(vcpu)->nested.current_vmcs12;
 734 }
 735
 736 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 737 {
 738         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 739         if (is_error_page(page))
 740                 return NULL;
 741
 742         return page;
 743 }
 744
 745 static void nested_release_page(struct page *page)
 746 {
 747         kvm_release_page_dirty(page);
 748 }
 749
 750 static void nested_release_page_clean(struct page *page)
 751 {
 752         kvm_release_page_clean(page);
 753 }
 754
 755 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 756 static u64 construct_eptp(unsigned long root_hpa);
 757 static void kvm_cpu_vmxon(u64 addr);
 758 static void kvm_cpu_vmxoff(void);
 759 static bool vmx_mpx_supported(void);
 760 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 761 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 762                             struct kvm_segment *var, int seg);
 763 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 764                             struct kvm_segment *var, int seg);
 765 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 766 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 767 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 768 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 769 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 770 static int alloc_identity_pagetable(struct kvm *kvm);
 771
 772 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 773 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 774 /*
 775  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 776  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 777  */
 778 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 779 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 780
 781 static unsigned long *vmx_io_bitmap_a;
 782 static unsigned long *vmx_io_bitmap_b;
 783 static unsigned long *vmx_msr_bitmap_legacy;
 784 static unsigned long *vmx_msr_bitmap_longmode;
 785 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 786 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 787 static unsigned long *vmx_vmread_bitmap;
 788 static unsigned long *vmx_vmwrite_bitmap;
 789
 790 static bool cpu_has_load_ia32_efer;
 791 static bool cpu_has_load_perf_global_ctrl;
 792
 793 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 794 static DEFINE_SPINLOCK(vmx_vpid_lock);
 795
 796 static struct vmcs_config {
 797         int size;
 798         int order;
 799         u32 revision_id;
 800         u32 pin_based_exec_ctrl;
 801         u32 cpu_based_exec_ctrl;
 802         u32 cpu_based_2nd_exec_ctrl;
 803         u32 vmexit_ctrl;
 804         u32 vmentry_ctrl;
 805 } vmcs_config;
 806
 807 static struct vmx_capability {
 808         u32 ept;
 809         u32 vpid;
 810 } vmx_capability;
 811
 812 #define VMX_SEGMENT_FIELD(seg)                                  \
 813         [VCPU_SREG_##seg] = {                                   \
 814                 .selector = GUEST_##seg##_SELECTOR,             \
 815                 .base = GUEST_##seg##_BASE,                     \
 816                 .limit = GUEST_##seg##_LIMIT,                   \
 817                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 818         }
 819
 820 static const struct kvm_vmx_segment_field {
 821         unsigned selector;
 822         unsigned base;
 823         unsigned limit;
 824         unsigned ar_bytes;
 825 } kvm_vmx_segment_fields[] = {
 826         VMX_SEGMENT_FIELD(CS),
 827         VMX_SEGMENT_FIELD(DS),
 828         VMX_SEGMENT_FIELD(ES),
 829         VMX_SEGMENT_FIELD(FS),
 830         VMX_SEGMENT_FIELD(GS),
 831         VMX_SEGMENT_FIELD(SS),
 832         VMX_SEGMENT_FIELD(TR),
 833         VMX_SEGMENT_FIELD(LDTR),
 834 };
 835
 836 static u64 host_efer;
 837
 838 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 839
 840 /*
 841  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 842  * away by decrementing the array size.
 843  */
 844 static const u32 vmx_msr_index[] = {
 845 #ifdef CONFIG_X86_64
 846         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 847 #endif
 848         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 849 };
 850
 851 static inline bool is_page_fault(u32 intr_info)
 852 {
 853         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 854                              INTR_INFO_VALID_MASK)) ==
 855                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 856 }
 857
 858 static inline bool is_no_device(u32 intr_info)
 859 {
 860         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 861                              INTR_INFO_VALID_MASK)) ==
 862                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 863 }
 864
 865 static inline bool is_invalid_opcode(u32 intr_info)
 866 {
 867         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 868                              INTR_INFO_VALID_MASK)) ==
 869                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 870 }
 871
 872 static inline bool is_external_interrupt(u32 intr_info)
 873 {
 874         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 875                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 876 }
 877
 878 static inline bool is_machine_check(u32 intr_info)
 879 {
 880         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 881                              INTR_INFO_VALID_MASK)) ==
 882                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 883 }
 884
 885 static inline bool cpu_has_vmx_msr_bitmap(void)
 886 {
 887         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 888 }
 889
 890 static inline bool cpu_has_vmx_tpr_shadow(void)
 891 {
 892         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 893 }
 894
 895 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 896 {
 897         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 898 }
 899
 900 static inline bool cpu_has_secondary_exec_ctrls(void)
 901 {
 902         return vmcs_config.cpu_based_exec_ctrl &
 903                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 904 }
 905
 906 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 907 {
 908         return vmcs_config.cpu_based_2nd_exec_ctrl &
 909                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 910 }
 911
 912 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 913 {
 914         return vmcs_config.cpu_based_2nd_exec_ctrl &
 915                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 916 }
 917
 918 static inline bool cpu_has_vmx_apic_register_virt(void)
 919 {
 920         return vmcs_config.cpu_based_2nd_exec_ctrl &
 921                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 922 }
 923
 924 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 925 {
 926         return vmcs_config.cpu_based_2nd_exec_ctrl &
 927                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 928 }
 929
 930 static inline bool cpu_has_vmx_posted_intr(void)
 931 {
 932         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 933 }
 934
 935 static inline bool cpu_has_vmx_apicv(void)
 936 {
 937         return cpu_has_vmx_apic_register_virt() &&
 938                 cpu_has_vmx_virtual_intr_delivery() &&
 939                 cpu_has_vmx_posted_intr();
 940 }
 941
 942 static inline bool cpu_has_vmx_flexpriority(void)
 943 {
 944         return cpu_has_vmx_tpr_shadow() &&
 945                 cpu_has_vmx_virtualize_apic_accesses();
 946 }
 947
 948 static inline bool cpu_has_vmx_ept_execute_only(void)
 949 {
 950         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 951 }
 952
 953 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 954 {
 955         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 956 }
 957
 958 static inline bool cpu_has_vmx_eptp_writeback(void)
 959 {
 960         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 961 }
 962
 963 static inline bool cpu_has_vmx_ept_2m_page(void)
 964 {
 965         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 966 }
 967
 968 static inline bool cpu_has_vmx_ept_1g_page(void)
 969 {
 970         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 971 }
 972
 973 static inline bool cpu_has_vmx_ept_4levels(void)
 974 {
 975         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 976 }
 977
 978 static inline bool cpu_has_vmx_ept_ad_bits(void)
 979 {
 980         return vmx_capability.ept & VMX_EPT_AD_BIT;
 981 }
 982
 983 static inline bool cpu_has_vmx_invept_context(void)
 984 {
 985         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 986 }
 987
 988 static inline bool cpu_has_vmx_invept_global(void)
 989 {
 990         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 991 }
 992
 993 static inline bool cpu_has_vmx_invvpid_single(void)
 994 {
 995         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 996 }
 997
 998 static inline bool cpu_has_vmx_invvpid_global(void)
 999 {
1000         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1001 }
1002
1003 static inline bool cpu_has_vmx_ept(void)
1004 {
1005         return vmcs_config.cpu_based_2nd_exec_ctrl &
1006                 SECONDARY_EXEC_ENABLE_EPT;
1007 }
1008
1009 static inline bool cpu_has_vmx_unrestricted_guest(void)
1010 {
1011         return vmcs_config.cpu_based_2nd_exec_ctrl &
1012                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1013 }
1014
1015 static inline bool cpu_has_vmx_ple(void)
1016 {
1017         return vmcs_config.cpu_based_2nd_exec_ctrl &
1018                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1019 }
1020
1021 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1022 {
1023         return flexpriority_enabled && irqchip_in_kernel(kvm);
1024 }
1025
1026 static inline bool cpu_has_vmx_vpid(void)
1027 {
1028         return vmcs_config.cpu_based_2nd_exec_ctrl &
1029                 SECONDARY_EXEC_ENABLE_VPID;
1030 }
1031
1032 static inline bool cpu_has_vmx_rdtscp(void)
1033 {
1034         return vmcs_config.cpu_based_2nd_exec_ctrl &
1035                 SECONDARY_EXEC_RDTSCP;
1036 }
1037
1038 static inline bool cpu_has_vmx_invpcid(void)
1039 {
1040         return vmcs_config.cpu_based_2nd_exec_ctrl &
1041                 SECONDARY_EXEC_ENABLE_INVPCID;
1042 }
1043
1044 static inline bool cpu_has_virtual_nmis(void)
1045 {
1046         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1047 }
1048
1049 static inline bool cpu_has_vmx_wbinvd_exit(void)
1050 {
1051         return vmcs_config.cpu_based_2nd_exec_ctrl &
1052                 SECONDARY_EXEC_WBINVD_EXITING;
1053 }
1054
1055 static inline bool cpu_has_vmx_shadow_vmcs(void)
1056 {
1057         u64 vmx_msr;
1058         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1059         /* check if the cpu supports writing r/o exit information fields */
1060         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1061                 return false;
1062
1063         return vmcs_config.cpu_based_2nd_exec_ctrl &
1064                 SECONDARY_EXEC_SHADOW_VMCS;
1065 }
1066
1067 static inline bool report_flexpriority(void)
1068 {
1069         return flexpriority_enabled;
1070 }
1071
1072 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1073 {
1074         return vmcs12->cpu_based_vm_exec_control & bit;
1075 }
1076
1077 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1078 {
1079         return (vmcs12->cpu_based_vm_exec_control &
1080                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1081                 (vmcs12->secondary_vm_exec_control & bit);
1082 }
1083
1084 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1085 {
1086         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1087 }
1088
1089 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1090 {
1091         return vmcs12->pin_based_vm_exec_control &
1092                 PIN_BASED_VMX_PREEMPTION_TIMER;
1093 }
1094
1095 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1096 {
1097         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1098 }
1099
1100 static inline bool is_exception(u32 intr_info)
1101 {
1102         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1103                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1104 }
1105
1106 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1107                               u32 exit_intr_info,
1108                               unsigned long exit_qualification);
1109 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1110                         struct vmcs12 *vmcs12,
1111                         u32 reason, unsigned long qualification);
1112
1113 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1114 {
1115         int i;
1116
1117         for (i = 0; i < vmx->nmsrs; ++i)
1118                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1119                         return i;
1120         return -1;
1121 }
1122
1123 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1124 {
1125     struct {
1126         u64 vpid : 16;
1127         u64 rsvd : 48;
1128         u64 gva;
1129     } operand = { vpid, 0, gva };
1130
1131     asm volatile (__ex(ASM_VMX_INVVPID)
1132                   /* CF==1 or ZF==1 --> rc = -1 */
1133                   "; ja 1f ; ud2 ; 1:"
1134                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1135 }
1136
1137 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1138 {
1139         struct {
1140                 u64 eptp, gpa;
1141         } operand = {eptp, gpa};
1142
1143         asm volatile (__ex(ASM_VMX_INVEPT)
1144                         /* CF==1 or ZF==1 --> rc = -1 */
1145                         "; ja 1f ; ud2 ; 1:\n"
1146                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1147 }
1148
1149 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1150 {
1151         int i;
1152
1153         i = __find_msr_index(vmx, msr);
1154         if (i >= 0)
1155                 return &vmx->guest_msrs[i];
1156         return NULL;
1157 }
1158
1159 static void vmcs_clear(struct vmcs *vmcs)
1160 {
1161         u64 phys_addr = __pa(vmcs);
1162         u8 error;
1163
1164         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1165                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1166                       : "cc", "memory");
1167         if (error)
1168                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1169                        vmcs, phys_addr);
1170 }
1171
1172 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1173 {
1174         vmcs_clear(loaded_vmcs->vmcs);
1175         loaded_vmcs->cpu = -1;
1176         loaded_vmcs->launched = 0;
1177 }
1178
1179 static void vmcs_load(struct vmcs *vmcs)
1180 {
1181         u64 phys_addr = __pa(vmcs);
1182         u8 error;
1183
1184         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1185                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1186                         : "cc", "memory");
1187         if (error)
1188                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1189                        vmcs, phys_addr);
1190 }
1191
1192 #ifdef CONFIG_KEXEC
1193 /*
1194  * This bitmap is used to indicate whether the vmclear
1195  * operation is enabled on all cpus. All disabled by
1196  * default.
1197  */
1198 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1199
1200 static inline void crash_enable_local_vmclear(int cpu)
1201 {
1202         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1203 }
1204
1205 static inline void crash_disable_local_vmclear(int cpu)
1206 {
1207         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1208 }
1209
1210 static inline int crash_local_vmclear_enabled(int cpu)
1211 {
1212         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1213 }
1214
1215 static void crash_vmclear_local_loaded_vmcss(void)
1216 {
1217         int cpu = raw_smp_processor_id();
1218         struct loaded_vmcs *v;
1219
1220         if (!crash_local_vmclear_enabled(cpu))
1221                 return;
1222
1223         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1224                             loaded_vmcss_on_cpu_link)
1225                 vmcs_clear(v->vmcs);
1226 }
1227 #else
1228 static inline void crash_enable_local_vmclear(int cpu) { }
1229 static inline void crash_disable_local_vmclear(int cpu) { }
1230 #endif /* CONFIG_KEXEC */
1231
1232 static void __loaded_vmcs_clear(void *arg)
1233 {
1234         struct loaded_vmcs *loaded_vmcs = arg;
1235         int cpu = raw_smp_processor_id();
1236
1237         if (loaded_vmcs->cpu != cpu)
1238                 return; /* vcpu migration can race with cpu offline */
1239         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1240                 per_cpu(current_vmcs, cpu) = NULL;
1241         crash_disable_local_vmclear(cpu);
1242         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1243
1244         /*
1245          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1246          * is before setting loaded_vmcs->vcpu to -1 which is done in
1247          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1248          * then adds the vmcs into percpu list before it is deleted.
1249          */
1250         smp_wmb();
1251
1252         loaded_vmcs_init(loaded_vmcs);
1253         crash_enable_local_vmclear(cpu);
1254 }
1255
1256 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1257 {
1258         int cpu = loaded_vmcs->cpu;
1259
1260         if (cpu != -1)
1261                 smp_call_function_single(cpu,
1262                          __loaded_vmcs_clear, loaded_vmcs, 1);
1263 }
1264
1265 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1266 {
1267         if (vmx->vpid == 0)
1268                 return;
1269
1270         if (cpu_has_vmx_invvpid_single())
1271                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1272 }
1273
1274 static inline void vpid_sync_vcpu_global(void)
1275 {
1276         if (cpu_has_vmx_invvpid_global())
1277                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1278 }
1279
1280 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1281 {
1282         if (cpu_has_vmx_invvpid_single())
1283                 vpid_sync_vcpu_single(vmx);
1284         else
1285                 vpid_sync_vcpu_global();
1286 }
1287
1288 static inline void ept_sync_global(void)
1289 {
1290         if (cpu_has_vmx_invept_global())
1291                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1292 }
1293
1294 static inline void ept_sync_context(u64 eptp)
1295 {
1296         if (enable_ept) {
1297                 if (cpu_has_vmx_invept_context())
1298                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1299                 else
1300                         ept_sync_global();
1301         }
1302 }
1303
1304 static __always_inline unsigned long vmcs_readl(unsigned long field)
1305 {
1306         unsigned long value;
1307
1308         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1309                       : "=a"(value) : "d"(field) : "cc");
1310         return value;
1311 }
1312
1313 static __always_inline u16 vmcs_read16(unsigned long field)
1314 {
1315         return vmcs_readl(field);
1316 }
1317
1318 static __always_inline u32 vmcs_read32(unsigned long field)
1319 {
1320         return vmcs_readl(field);
1321 }
1322
1323 static __always_inline u64 vmcs_read64(unsigned long field)
1324 {
1325 #ifdef CONFIG_X86_64
1326         return vmcs_readl(field);
1327 #else
1328         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1329 #endif
1330 }
1331
1332 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1333 {
1334         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1335                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1336         dump_stack();
1337 }
1338
1339 static void vmcs_writel(unsigned long field, unsigned long value)
1340 {
1341         u8 error;
1342
1343         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1344                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1345         if (unlikely(error))
1346                 vmwrite_error(field, value);
1347 }
1348
1349 static void vmcs_write16(unsigned long field, u16 value)
1350 {
1351         vmcs_writel(field, value);
1352 }
1353
1354 static void vmcs_write32(unsigned long field, u32 value)
1355 {
1356         vmcs_writel(field, value);
1357 }
1358
1359 static void vmcs_write64(unsigned long field, u64 value)
1360 {
1361         vmcs_writel(field, value);
1362 #ifndef CONFIG_X86_64
1363         asm volatile ("");
1364         vmcs_writel(field+1, value >> 32);
1365 #endif
1366 }
1367
1368 static void vmcs_clear_bits(unsigned long field, u32 mask)
1369 {
1370         vmcs_writel(field, vmcs_readl(field) & ~mask);
1371 }
1372
1373 static void vmcs_set_bits(unsigned long field, u32 mask)
1374 {
1375         vmcs_writel(field, vmcs_readl(field) | mask);
1376 }
1377
1378 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1379 {
1380         vmcs_write32(VM_ENTRY_CONTROLS, val);
1381         vmx->vm_entry_controls_shadow = val;
1382 }
1383
1384 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1385 {
1386         if (vmx->vm_entry_controls_shadow != val)
1387                 vm_entry_controls_init(vmx, val);
1388 }
1389
1390 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1391 {
1392         return vmx->vm_entry_controls_shadow;
1393 }
1394
1395
1396 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1397 {
1398         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1399 }
1400
1401 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1402 {
1403         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1404 }
1405
1406 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1407 {
1408         vmcs_write32(VM_EXIT_CONTROLS, val);
1409         vmx->vm_exit_controls_shadow = val;
1410 }
1411
1412 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1413 {
1414         if (vmx->vm_exit_controls_shadow != val)
1415                 vm_exit_controls_init(vmx, val);
1416 }
1417
1418 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1419 {
1420         return vmx->vm_exit_controls_shadow;
1421 }
1422
1423
1424 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1425 {
1426         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1427 }
1428
1429 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1430 {
1431         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1432 }
1433
1434 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1435 {
1436         vmx->segment_cache.bitmask = 0;
1437 }
1438
1439 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1440                                        unsigned field)
1441 {
1442         bool ret;
1443         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1444
1445         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1446                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1447                 vmx->segment_cache.bitmask = 0;
1448         }
1449         ret = vmx->segment_cache.bitmask & mask;
1450         vmx->segment_cache.bitmask |= mask;
1451         return ret;
1452 }
1453
1454 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1455 {
1456         u16 *p = &vmx->segment_cache.seg[seg].selector;
1457
1458         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1459                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1460         return *p;
1461 }
1462
1463 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1464 {
1465         ulong *p = &vmx->segment_cache.seg[seg].base;
1466
1467         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1468                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1469         return *p;
1470 }
1471
1472 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1473 {
1474         u32 *p = &vmx->segment_cache.seg[seg].limit;
1475
1476         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1477                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1478         return *p;
1479 }
1480
1481 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1482 {
1483         u32 *p = &vmx->segment_cache.seg[seg].ar;
1484
1485         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1486                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1487         return *p;
1488 }
1489
1490 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1491 {
1492         u32 eb;
1493
1494         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1495              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1496         if ((vcpu->guest_debug &
1497              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1498             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1499                 eb |= 1u << BP_VECTOR;
1500         if (to_vmx(vcpu)->rmode.vm86_active)
1501                 eb = ~0;
1502         if (enable_ept)
1503                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1504         if (vcpu->fpu_active)
1505                 eb &= ~(1u << NM_VECTOR);
1506
1507         /* When we are running a nested L2 guest and L1 specified for it a
1508          * certain exception bitmap, we must trap the same exceptions and pass
1509          * them to L1. When running L2, we will only handle the exceptions
1510          * specified above if L1 did not want them.
1511          */
1512         if (is_guest_mode(vcpu))
1513                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1514
1515         vmcs_write32(EXCEPTION_BITMAP, eb);
1516 }
1517
1518 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1519                 unsigned long entry, unsigned long exit)
1520 {
1521         vm_entry_controls_clearbit(vmx, entry);
1522         vm_exit_controls_clearbit(vmx, exit);
1523 }
1524
1525 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1526 {
1527         unsigned i;
1528         struct msr_autoload *m = &vmx->msr_autoload;
1529
1530         switch (msr) {
1531         case MSR_EFER:
1532                 if (cpu_has_load_ia32_efer) {
1533                         clear_atomic_switch_msr_special(vmx,
1534                                         VM_ENTRY_LOAD_IA32_EFER,
1535                                         VM_EXIT_LOAD_IA32_EFER);
1536                         return;
1537                 }
1538                 break;
1539         case MSR_CORE_PERF_GLOBAL_CTRL:
1540                 if (cpu_has_load_perf_global_ctrl) {
1541                         clear_atomic_switch_msr_special(vmx,
1542                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1543                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1544                         return;
1545                 }
1546                 break;
1547         }
1548
1549         for (i = 0; i < m->nr; ++i)
1550                 if (m->guest[i].index == msr)
1551                         break;
1552
1553         if (i == m->nr)
1554                 return;
1555         --m->nr;
1556         m->guest[i] = m->guest[m->nr];
1557         m->host[i] = m->host[m->nr];
1558         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1559         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1560 }
1561
1562 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1563                 unsigned long entry, unsigned long exit,
1564                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1565                 u64 guest_val, u64 host_val)
1566 {
1567         vmcs_write64(guest_val_vmcs, guest_val);
1568         vmcs_write64(host_val_vmcs, host_val);
1569         vm_entry_controls_setbit(vmx, entry);
1570         vm_exit_controls_setbit(vmx, exit);
1571 }
1572
1573 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1574                                   u64 guest_val, u64 host_val)
1575 {
1576         unsigned i;
1577         struct msr_autoload *m = &vmx->msr_autoload;
1578
1579         switch (msr) {
1580         case MSR_EFER:
1581                 if (cpu_has_load_ia32_efer) {
1582                         add_atomic_switch_msr_special(vmx,
1583                                         VM_ENTRY_LOAD_IA32_EFER,
1584                                         VM_EXIT_LOAD_IA32_EFER,
1585                                         GUEST_IA32_EFER,
1586                                         HOST_IA32_EFER,
1587                                         guest_val, host_val);
1588                         return;
1589                 }
1590                 break;
1591         case MSR_CORE_PERF_GLOBAL_CTRL:
1592                 if (cpu_has_load_perf_global_ctrl) {
1593                         add_atomic_switch_msr_special(vmx,
1594                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1595                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1596                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1597                                         HOST_IA32_PERF_GLOBAL_CTRL,
1598                                         guest_val, host_val);
1599                         return;
1600                 }
1601                 break;
1602         }
1603
1604         for (i = 0; i < m->nr; ++i)
1605                 if (m->guest[i].index == msr)
1606                         break;
1607
1608         if (i == NR_AUTOLOAD_MSRS) {
1609                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1610                                 "Can't add msr %x\n", msr);
1611                 return;
1612         } else if (i == m->nr) {
1613                 ++m->nr;
1614                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1615                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1616         }
1617
1618         m->guest[i].index = msr;
1619         m->guest[i].value = guest_val;
1620         m->host[i].index = msr;
1621         m->host[i].value = host_val;
1622 }
1623
1624 static void reload_tss(void)
1625 {
1626         /*
1627          * VT restores TR but not its size.  Useless.
1628          */
1629         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1630         struct desc_struct *descs;
1631
1632         descs = (void *)gdt->address;
1633         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1634         load_TR_desc();
1635 }
1636
1637 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1638 {
1639         u64 guest_efer;
1640         u64 ignore_bits;
1641
1642         guest_efer = vmx->vcpu.arch.efer;
1643
1644         /*
1645          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1646          * outside long mode
1647          */
1648         ignore_bits = EFER_NX | EFER_SCE;
1649 #ifdef CONFIG_X86_64
1650         ignore_bits |= EFER_LMA | EFER_LME;
1651         /* SCE is meaningful only in long mode on Intel */
1652         if (guest_efer & EFER_LMA)
1653                 ignore_bits &= ~(u64)EFER_SCE;
1654 #endif
1655         guest_efer &= ~ignore_bits;
1656         guest_efer |= host_efer & ignore_bits;
1657         vmx->guest_msrs[efer_offset].data = guest_efer;
1658         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1659
1660         clear_atomic_switch_msr(vmx, MSR_EFER);
1661         /* On ept, can't emulate nx, and must switch nx atomically */
1662         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1663                 guest_efer = vmx->vcpu.arch.efer;
1664                 if (!(guest_efer & EFER_LMA))
1665                         guest_efer &= ~EFER_LME;
1666                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1667                 return false;
1668         }
1669
1670         return true;
1671 }
1672
1673 static unsigned long segment_base(u16 selector)
1674 {
1675         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1676         struct desc_struct *d;
1677         unsigned long table_base;
1678         unsigned long v;
1679
1680         if (!(selector & ~3))
1681                 return 0;
1682
1683         table_base = gdt->address;
1684
1685         if (selector & 4) {           /* from ldt */
1686                 u16 ldt_selector = kvm_read_ldt();
1687
1688                 if (!(ldt_selector & ~3))
1689                         return 0;
1690
1691                 table_base = segment_base(ldt_selector);
1692         }
1693         d = (struct desc_struct *)(table_base + (selector & ~7));
1694         v = get_desc_base(d);
1695 #ifdef CONFIG_X86_64
1696        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1697                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1698 #endif
1699         return v;
1700 }
1701
1702 static inline unsigned long kvm_read_tr_base(void)
1703 {
1704         u16 tr;
1705         asm("str %0" : "=g"(tr));
1706         return segment_base(tr);
1707 }
1708
1709 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1710 {
1711         struct vcpu_vmx *vmx = to_vmx(vcpu);
1712         int i;
1713
1714         if (vmx->host_state.loaded)
1715                 return;
1716
1717         vmx->host_state.loaded = 1;
1718         /*
1719          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1720          * allow segment selectors with cpl > 0 or ti == 1.
1721          */
1722         vmx->host_state.ldt_sel = kvm_read_ldt();
1723         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1724         savesegment(fs, vmx->host_state.fs_sel);
1725         if (!(vmx->host_state.fs_sel & 7)) {
1726                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1727                 vmx->host_state.fs_reload_needed = 0;
1728         } else {
1729                 vmcs_write16(HOST_FS_SELECTOR, 0);
1730                 vmx->host_state.fs_reload_needed = 1;
1731         }
1732         savesegment(gs, vmx->host_state.gs_sel);
1733         if (!(vmx->host_state.gs_sel & 7))
1734                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1735         else {
1736                 vmcs_write16(HOST_GS_SELECTOR, 0);
1737                 vmx->host_state.gs_ldt_reload_needed = 1;
1738         }
1739
1740 #ifdef CONFIG_X86_64
1741         savesegment(ds, vmx->host_state.ds_sel);
1742         savesegment(es, vmx->host_state.es_sel);
1743 #endif
1744
1745 #ifdef CONFIG_X86_64
1746         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1747         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1748 #else
1749         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1750         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1751 #endif
1752
1753 #ifdef CONFIG_X86_64
1754         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1755         if (is_long_mode(&vmx->vcpu))
1756                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1757 #endif
1758         if (boot_cpu_has(X86_FEATURE_MPX))
1759                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1760         for (i = 0; i < vmx->save_nmsrs; ++i)
1761                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1762                                    vmx->guest_msrs[i].data,
1763                                    vmx->guest_msrs[i].mask);
1764 }
1765
1766 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1767 {
1768         if (!vmx->host_state.loaded)
1769                 return;
1770
1771         ++vmx->vcpu.stat.host_state_reload;
1772         vmx->host_state.loaded = 0;
1773 #ifdef CONFIG_X86_64
1774         if (is_long_mode(&vmx->vcpu))
1775                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1776 #endif
1777         if (vmx->host_state.gs_ldt_reload_needed) {
1778                 kvm_load_ldt(vmx->host_state.ldt_sel);
1779 #ifdef CONFIG_X86_64
1780                 load_gs_index(vmx->host_state.gs_sel);
1781 #else
1782                 loadsegment(gs, vmx->host_state.gs_sel);
1783 #endif
1784         }
1785         if (vmx->host_state.fs_reload_needed)
1786                 loadsegment(fs, vmx->host_state.fs_sel);
1787 #ifdef CONFIG_X86_64
1788         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1789                 loadsegment(ds, vmx->host_state.ds_sel);
1790                 loadsegment(es, vmx->host_state.es_sel);
1791         }
1792 #endif
1793         reload_tss();
1794 #ifdef CONFIG_X86_64
1795         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1796 #endif
1797         if (vmx->host_state.msr_host_bndcfgs)
1798                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1799         /*
1800          * If the FPU is not active (through the host task or
1801          * the guest vcpu), then restore the cr0.TS bit.
1802          */
1803         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1804                 stts();
1805         load_gdt(this_cpu_ptr(&host_gdt));
1806 }
1807
1808 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1809 {
1810         preempt_disable();
1811         __vmx_load_host_state(vmx);
1812         preempt_enable();
1813 }
1814
1815 /*
1816  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1817  * vcpu mutex is already taken.
1818  */
1819 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1820 {
1821         struct vcpu_vmx *vmx = to_vmx(vcpu);
1822         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1823
1824         if (!vmm_exclusive)
1825                 kvm_cpu_vmxon(phys_addr);
1826         else if (vmx->loaded_vmcs->cpu != cpu)
1827                 loaded_vmcs_clear(vmx->loaded_vmcs);
1828
1829         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1830                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1831                 vmcs_load(vmx->loaded_vmcs->vmcs);
1832         }
1833
1834         if (vmx->loaded_vmcs->cpu != cpu) {
1835                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1836                 unsigned long sysenter_esp;
1837
1838                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1839                 local_irq_disable();
1840                 crash_disable_local_vmclear(cpu);
1841
1842                 /*
1843                  * Read loaded_vmcs->cpu should be before fetching
1844                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1845                  * See the comments in __loaded_vmcs_clear().
1846                  */
1847                 smp_rmb();
1848
1849                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1850                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1851                 crash_enable_local_vmclear(cpu);
1852                 local_irq_enable();
1853
1854                 /*
1855                  * Linux uses per-cpu TSS and GDT, so set these when switching
1856                  * processors.
1857                  */
1858                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1859                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1860
1861                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1862                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1863                 vmx->loaded_vmcs->cpu = cpu;
1864         }
1865 }
1866
1867 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1868 {
1869         __vmx_load_host_state(to_vmx(vcpu));
1870         if (!vmm_exclusive) {
1871                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1872                 vcpu->cpu = -1;
1873                 kvm_cpu_vmxoff();
1874         }
1875 }
1876
1877 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1878 {
1879         ulong cr0;
1880
1881         if (vcpu->fpu_active)
1882                 return;
1883         vcpu->fpu_active = 1;
1884         cr0 = vmcs_readl(GUEST_CR0);
1885         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1886         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1887         vmcs_writel(GUEST_CR0, cr0);
1888         update_exception_bitmap(vcpu);
1889         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1890         if (is_guest_mode(vcpu))
1891                 vcpu->arch.cr0_guest_owned_bits &=
1892                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1893         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1894 }
1895
1896 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1897
1898 /*
1899  * Return the cr0 value that a nested guest would read. This is a combination
1900  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1901  * its hypervisor (cr0_read_shadow).
1902  */
1903 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1904 {
1905         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1906                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1907 }
1908 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1909 {
1910         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1911                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1912 }
1913
1914 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1915 {
1916         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1917          * set this *before* calling this function.
1918          */
1919         vmx_decache_cr0_guest_bits(vcpu);
1920         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1921         update_exception_bitmap(vcpu);
1922         vcpu->arch.cr0_guest_owned_bits = 0;
1923         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1924         if (is_guest_mode(vcpu)) {
1925                 /*
1926                  * L1's specified read shadow might not contain the TS bit,
1927                  * so now that we turned on shadowing of this bit, we need to
1928                  * set this bit of the shadow. Like in nested_vmx_run we need
1929                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1930                  * up-to-date here because we just decached cr0.TS (and we'll
1931                  * only update vmcs12->guest_cr0 on nested exit).
1932                  */
1933                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1934                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1935                         (vcpu->arch.cr0 & X86_CR0_TS);
1936                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1937         } else
1938                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1939 }
1940
1941 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1942 {
1943         unsigned long rflags, save_rflags;
1944
1945         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1946                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1947                 rflags = vmcs_readl(GUEST_RFLAGS);
1948                 if (to_vmx(vcpu)->rmode.vm86_active) {
1949                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1950                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1951                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1952                 }
1953                 to_vmx(vcpu)->rflags = rflags;
1954         }
1955         return to_vmx(vcpu)->rflags;
1956 }
1957
1958 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1959 {
1960         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1961         to_vmx(vcpu)->rflags = rflags;
1962         if (to_vmx(vcpu)->rmode.vm86_active) {
1963                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1964                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1965         }
1966         vmcs_writel(GUEST_RFLAGS, rflags);
1967 }
1968
1969 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1970 {
1971         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1972         int ret = 0;
1973
1974         if (interruptibility & GUEST_INTR_STATE_STI)
1975                 ret |= KVM_X86_SHADOW_INT_STI;
1976         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1977                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1978
1979         return ret;
1980 }
1981
1982 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1983 {
1984         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1985         u32 interruptibility = interruptibility_old;
1986
1987         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1988
1989         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1990                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1991         else if (mask & KVM_X86_SHADOW_INT_STI)
1992                 interruptibility |= GUEST_INTR_STATE_STI;
1993
1994         if ((interruptibility != interruptibility_old))
1995                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1996 }
1997
1998 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1999 {
2000         unsigned long rip;
2001
2002         rip = kvm_rip_read(vcpu);
2003         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2004         kvm_rip_write(vcpu, rip);
2005
2006         /* skipping an emulated instruction also counts */
2007         vmx_set_interrupt_shadow(vcpu, 0);
2008 }
2009
2010 /*
2011  * KVM wants to inject page-faults which it got to the guest. This function
2012  * checks whether in a nested guest, we need to inject them to L1 or L2.
2013  */
2014 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2015 {
2016         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017
2018         if (!(vmcs12->exception_bitmap & (1u << nr)))
2019                 return 0;
2020
2021         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2022                           vmcs_read32(VM_EXIT_INTR_INFO),
2023                           vmcs_readl(EXIT_QUALIFICATION));
2024         return 1;
2025 }
2026
2027 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2028                                 bool has_error_code, u32 error_code,
2029                                 bool reinject)
2030 {
2031         struct vcpu_vmx *vmx = to_vmx(vcpu);
2032         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2033
2034         if (!reinject && is_guest_mode(vcpu) &&
2035             nested_vmx_check_exception(vcpu, nr))
2036                 return;
2037
2038         if (has_error_code) {
2039                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2040                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2041         }
2042
2043         if (vmx->rmode.vm86_active) {
2044                 int inc_eip = 0;
2045                 if (kvm_exception_is_soft(nr))
2046                         inc_eip = vcpu->arch.event_exit_inst_len;
2047                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2048                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2049                 return;
2050         }
2051
2052         if (kvm_exception_is_soft(nr)) {
2053                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2054                              vmx->vcpu.arch.event_exit_inst_len);
2055                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2056         } else
2057                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2058
2059         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2060 }
2061
2062 static bool vmx_rdtscp_supported(void)
2063 {
2064         return cpu_has_vmx_rdtscp();
2065 }
2066
2067 static bool vmx_invpcid_supported(void)
2068 {
2069         return cpu_has_vmx_invpcid() && enable_ept;
2070 }
2071
2072 /*
2073  * Swap MSR entry in host/guest MSR entry array.
2074  */
2075 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2076 {
2077         struct shared_msr_entry tmp;
2078
2079         tmp = vmx->guest_msrs[to];
2080         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2081         vmx->guest_msrs[from] = tmp;
2082 }
2083
2084 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2085 {
2086         unsigned long *msr_bitmap;
2087
2088         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2089                 if (is_long_mode(vcpu))
2090                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2091                 else
2092                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2093         } else {
2094                 if (is_long_mode(vcpu))
2095                         msr_bitmap = vmx_msr_bitmap_longmode;
2096                 else
2097                         msr_bitmap = vmx_msr_bitmap_legacy;
2098         }
2099
2100         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2101 }
2102
2103 /*
2104  * Set up the vmcs to automatically save and restore system
2105  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2106  * mode, as fiddling with msrs is very expensive.
2107  */
2108 static void setup_msrs(struct vcpu_vmx *vmx)
2109 {
2110         int save_nmsrs, index;
2111
2112         save_nmsrs = 0;
2113 #ifdef CONFIG_X86_64
2114         if (is_long_mode(&vmx->vcpu)) {
2115                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2116                 if (index >= 0)
2117                         move_msr_up(vmx, index, save_nmsrs++);
2118                 index = __find_msr_index(vmx, MSR_LSTAR);
2119                 if (index >= 0)
2120                         move_msr_up(vmx, index, save_nmsrs++);
2121                 index = __find_msr_index(vmx, MSR_CSTAR);
2122                 if (index >= 0)
2123                         move_msr_up(vmx, index, save_nmsrs++);
2124                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2125                 if (index >= 0 && vmx->rdtscp_enabled)
2126                         move_msr_up(vmx, index, save_nmsrs++);
2127                 /*
2128                  * MSR_STAR is only needed on long mode guests, and only
2129                  * if efer.sce is enabled.
2130                  */
2131                 index = __find_msr_index(vmx, MSR_STAR);
2132                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2133                         move_msr_up(vmx, index, save_nmsrs++);
2134         }
2135 #endif
2136         index = __find_msr_index(vmx, MSR_EFER);
2137         if (index >= 0 && update_transition_efer(vmx, index))
2138                 move_msr_up(vmx, index, save_nmsrs++);
2139
2140         vmx->save_nmsrs = save_nmsrs;
2141
2142         if (cpu_has_vmx_msr_bitmap())
2143                 vmx_set_msr_bitmap(&vmx->vcpu);
2144 }
2145
2146 /*
2147  * reads and returns guest's timestamp counter "register"
2148  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2149  */
2150 static u64 guest_read_tsc(void)
2151 {
2152         u64 host_tsc, tsc_offset;
2153
2154         rdtscll(host_tsc);
2155         tsc_offset = vmcs_read64(TSC_OFFSET);
2156         return host_tsc + tsc_offset;
2157 }
2158
2159 /*
2160  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2161  * counter, even if a nested guest (L2) is currently running.
2162  */
2163 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2164 {
2165         u64 tsc_offset;
2166
2167         tsc_offset = is_guest_mode(vcpu) ?
2168                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2169                 vmcs_read64(TSC_OFFSET);
2170         return host_tsc + tsc_offset;
2171 }
2172
2173 /*
2174  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2175  * software catchup for faster rates on slower CPUs.
2176  */
2177 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2178 {
2179         if (!scale)
2180                 return;
2181
2182         if (user_tsc_khz > tsc_khz) {
2183                 vcpu->arch.tsc_catchup = 1;
2184                 vcpu->arch.tsc_always_catchup = 1;
2185         } else
2186                 WARN(1, "user requested TSC rate below hardware speed\n");
2187 }
2188
2189 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2190 {
2191         return vmcs_read64(TSC_OFFSET);
2192 }
2193
2194 /*
2195  * writes 'offset' into guest's timestamp counter offset register
2196  */
2197 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2198 {
2199         if (is_guest_mode(vcpu)) {
2200                 /*
2201                  * We're here if L1 chose not to trap WRMSR to TSC. According
2202                  * to the spec, this should set L1's TSC; The offset that L1
2203                  * set for L2 remains unchanged, and still needs to be added
2204                  * to the newly set TSC to get L2's TSC.
2205                  */
2206                 struct vmcs12 *vmcs12;
2207                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2208                 /* recalculate vmcs02.TSC_OFFSET: */
2209                 vmcs12 = get_vmcs12(vcpu);
2210                 vmcs_write64(TSC_OFFSET, offset +
2211                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2212                          vmcs12->tsc_offset : 0));
2213         } else {
2214                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2215                                            vmcs_read64(TSC_OFFSET), offset);
2216                 vmcs_write64(TSC_OFFSET, offset);
2217         }
2218 }
2219
2220 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2221 {
2222         u64 offset = vmcs_read64(TSC_OFFSET);
2223
2224         vmcs_write64(TSC_OFFSET, offset + adjustment);
2225         if (is_guest_mode(vcpu)) {
2226                 /* Even when running L2, the adjustment needs to apply to L1 */
2227                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2228         } else
2229                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2230                                            offset + adjustment);
2231 }
2232
2233 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2234 {
2235         return target_tsc - native_read_tsc();
2236 }
2237
2238 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2239 {
2240         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2241         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2242 }
2243
2244 /*
2245  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2246  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2247  * all guests if the "nested" module option is off, and can also be disabled
2248  * for a single guest by disabling its VMX cpuid bit.
2249  */
2250 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2251 {
2252         return nested && guest_cpuid_has_vmx(vcpu);
2253 }
2254
2255 /*
2256  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2257  * returned for the various VMX controls MSRs when nested VMX is enabled.
2258  * The same values should also be used to verify that vmcs12 control fields are
2259  * valid during nested entry from L1 to L2.
2260  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2261  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2262  * bit in the high half is on if the corresponding bit in the control field
2263  * may be on. See also vmx_control_verify().
2264  * TODO: allow these variables to be modified (downgraded) by module options
2265  * or other means.
2266  */
2267 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2268 static u32 nested_vmx_true_procbased_ctls_low;
2269 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2270 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2271 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2272 static u32 nested_vmx_true_exit_ctls_low;
2273 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2274 static u32 nested_vmx_true_entry_ctls_low;
2275 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2276 static u32 nested_vmx_ept_caps;
2277 static __init void nested_vmx_setup_ctls_msrs(void)
2278 {
2279         /*
2280          * Note that as a general rule, the high half of the MSRs (bits in
2281          * the control fields which may be 1) should be initialized by the
2282          * intersection of the underlying hardware's MSR (i.e., features which
2283          * can be supported) and the list of features we want to expose -
2284          * because they are known to be properly supported in our code.
2285          * Also, usually, the low half of the MSRs (bits which must be 1) can
2286          * be set to 0, meaning that L1 may turn off any of these bits. The
2287          * reason is that if one of these bits is necessary, it will appear
2288          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2289          * fields of vmcs01 and vmcs02, will turn these bits off - and
2290          * nested_vmx_exit_handled() will not pass related exits to L1.
2291          * These rules have exceptions below.
2292          */
2293
2294         /* pin-based controls */
2295         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2296               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2297         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2298         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2299                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2300         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2301                 PIN_BASED_VMX_PREEMPTION_TIMER;
2302
2303         /* exit controls */
2304         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2305                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2306         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2307
2308         nested_vmx_exit_ctls_high &=
2309 #ifdef CONFIG_X86_64
2310                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2311 #endif
2312                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2313         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2314                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2315                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2316
2317         if (vmx_mpx_supported())
2318                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2319
2320         /* We support free control of debug control saving. */
2321         nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2322                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2323
2324         /* entry controls */
2325         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2326                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2327         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2328         nested_vmx_entry_ctls_high &=
2329 #ifdef CONFIG_X86_64
2330                 VM_ENTRY_IA32E_MODE |
2331 #endif
2332                 VM_ENTRY_LOAD_IA32_PAT;
2333         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2334                                        VM_ENTRY_LOAD_IA32_EFER);
2335         if (vmx_mpx_supported())
2336                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2337
2338         /* We support free control of debug control loading. */
2339         nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2340                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2341
2342         /* cpu-based controls */
2343         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2344                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2345         nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2346         nested_vmx_procbased_ctls_high &=
2347                 CPU_BASED_VIRTUAL_INTR_PENDING |
2348                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2349                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2350                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2351                 CPU_BASED_CR3_STORE_EXITING |
2352 #ifdef CONFIG_X86_64
2353                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2354 #endif
2355                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2356                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2357                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2358                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2359                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2360         /*
2361          * We can allow some features even when not supported by the
2362          * hardware. For example, L1 can specify an MSR bitmap - and we
2363          * can use it to avoid exits to L1 - even when L0 runs L2
2364          * without MSR bitmaps.
2365          */
2366         nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2367                 CPU_BASED_USE_MSR_BITMAPS;
2368
2369         /* We support free control of CR3 access interception. */
2370         nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2371                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2372
2373         /* secondary cpu-based controls */
2374         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2375                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2376         nested_vmx_secondary_ctls_low = 0;
2377         nested_vmx_secondary_ctls_high &=
2378                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2379                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2380                 SECONDARY_EXEC_WBINVD_EXITING;
2381
2382         if (enable_ept) {
2383                 /* nested EPT: emulate EPT also to L1 */
2384                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2385                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2386                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2387                          VMX_EPT_INVEPT_BIT;
2388                 nested_vmx_ept_caps &= vmx_capability.ept;
2389                 /*
2390                  * For nested guests, we don't do anything specific
2391                  * for single context invalidation. Hence, only advertise
2392                  * support for global context invalidation.
2393                  */
2394                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2395         } else
2396                 nested_vmx_ept_caps = 0;
2397
2398         /* miscellaneous data */
2399         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2400         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2401         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2402                 VMX_MISC_ACTIVITY_HLT;
2403         nested_vmx_misc_high = 0;
2404 }
2405
2406 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2407 {
2408         /*
2409          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2410          */
2411         return ((control & high) | low) == control;
2412 }
2413
2414 static inline u64 vmx_control_msr(u32 low, u32 high)
2415 {
2416         return low | ((u64)high << 32);
2417 }
2418
2419 /* Returns 0 on success, non-0 otherwise. */
2420 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2421 {
2422         switch (msr_index) {
2423         case MSR_IA32_VMX_BASIC:
2424                 /*
2425                  * This MSR reports some information about VMX support. We
2426                  * should return information about the VMX we emulate for the
2427                  * guest, and the VMCS structure we give it - not about the
2428                  * VMX support of the underlying hardware.
2429                  */
2430                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2431                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2432                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2433                 break;
2434         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2435         case MSR_IA32_VMX_PINBASED_CTLS:
2436                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2437                                         nested_vmx_pinbased_ctls_high);
2438                 break;
2439         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2440                 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2441                                         nested_vmx_procbased_ctls_high);
2442                 break;
2443         case MSR_IA32_VMX_PROCBASED_CTLS:
2444                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2445                                         nested_vmx_procbased_ctls_high);
2446                 break;
2447         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2448                 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2449                                         nested_vmx_exit_ctls_high);
2450                 break;
2451         case MSR_IA32_VMX_EXIT_CTLS:
2452                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2453                                         nested_vmx_exit_ctls_high);
2454                 break;
2455         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2456                 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2457                                         nested_vmx_entry_ctls_high);
2458                 break;
2459         case MSR_IA32_VMX_ENTRY_CTLS:
2460                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2461                                         nested_vmx_entry_ctls_high);
2462                 break;
2463         case MSR_IA32_VMX_MISC:
2464                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2465                                          nested_vmx_misc_high);
2466                 break;
2467         /*
2468          * These MSRs specify bits which the guest must keep fixed (on or off)
2469          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2470          * We picked the standard core2 setting.
2471          */
2472 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2473 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2474         case MSR_IA32_VMX_CR0_FIXED0:
2475                 *pdata = VMXON_CR0_ALWAYSON;
2476                 break;
2477         case MSR_IA32_VMX_CR0_FIXED1:
2478                 *pdata = -1ULL;
2479                 break;
2480         case MSR_IA32_VMX_CR4_FIXED0:
2481                 *pdata = VMXON_CR4_ALWAYSON;
2482                 break;
2483         case MSR_IA32_VMX_CR4_FIXED1:
2484                 *pdata = -1ULL;
2485                 break;
2486         case MSR_IA32_VMX_VMCS_ENUM:
2487                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2488                 break;
2489         case MSR_IA32_VMX_PROCBASED_CTLS2:
2490                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2491                                         nested_vmx_secondary_ctls_high);
2492                 break;
2493         case MSR_IA32_VMX_EPT_VPID_CAP:
2494                 /* Currently, no nested vpid support */
2495                 *pdata = nested_vmx_ept_caps;
2496                 break;
2497         default:
2498                 return 1;
2499         }
2500
2501         return 0;
2502 }
2503
2504 /*
2505  * Reads an msr value (of 'msr_index') into 'pdata'.
2506  * Returns 0 on success, non-0 otherwise.
2507  * Assumes vcpu_load() was already called.
2508  */
2509 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2510 {
2511         u64 data;
2512         struct shared_msr_entry *msr;
2513
2514         if (!pdata) {
2515                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2516                 return -EINVAL;
2517         }
2518
2519         switch (msr_index) {
2520 #ifdef CONFIG_X86_64
2521         case MSR_FS_BASE:
2522                 data = vmcs_readl(GUEST_FS_BASE);
2523                 break;
2524         case MSR_GS_BASE:
2525                 data = vmcs_readl(GUEST_GS_BASE);
2526                 break;
2527         case MSR_KERNEL_GS_BASE:
2528                 vmx_load_host_state(to_vmx(vcpu));
2529                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2530                 break;
2531 #endif
2532         case MSR_EFER:
2533                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2534         case MSR_IA32_TSC:
2535                 data = guest_read_tsc();
2536                 break;
2537         case MSR_IA32_SYSENTER_CS:
2538                 data = vmcs_read32(GUEST_SYSENTER_CS);
2539                 break;
2540         case MSR_IA32_SYSENTER_EIP:
2541                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2542                 break;
2543         case MSR_IA32_SYSENTER_ESP:
2544                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2545                 break;
2546         case MSR_IA32_BNDCFGS:
2547                 if (!vmx_mpx_supported())
2548                         return 1;
2549                 data = vmcs_read64(GUEST_BNDCFGS);
2550                 break;
2551         case MSR_IA32_FEATURE_CONTROL:
2552                 if (!nested_vmx_allowed(vcpu))
2553                         return 1;
2554                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2555                 break;
2556         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2557                 if (!nested_vmx_allowed(vcpu))
2558                         return 1;
2559                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2560         case MSR_TSC_AUX:
2561                 if (!to_vmx(vcpu)->rdtscp_enabled)
2562                         return 1;
2563                 /* Otherwise falls through */
2564         default:
2565                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2566                 if (msr) {
2567                         data = msr->data;
2568                         break;
2569                 }
2570                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2571         }
2572
2573         *pdata = data;
2574         return 0;
2575 }
2576
2577 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2578
2579 /*
2580  * Writes msr value into into the appropriate "register".
2581  * Returns 0 on success, non-0 otherwise.
2582  * Assumes vcpu_load() was already called.
2583  */
2584 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2585 {
2586         struct vcpu_vmx *vmx = to_vmx(vcpu);
2587         struct shared_msr_entry *msr;
2588         int ret = 0;
2589         u32 msr_index = msr_info->index;
2590         u64 data = msr_info->data;
2591
2592         switch (msr_index) {
2593         case MSR_EFER:
2594                 ret = kvm_set_msr_common(vcpu, msr_info);
2595                 break;
2596 #ifdef CONFIG_X86_64
2597         case MSR_FS_BASE:
2598                 vmx_segment_cache_clear(vmx);
2599                 vmcs_writel(GUEST_FS_BASE, data);
2600                 break;
2601         case MSR_GS_BASE:
2602                 vmx_segment_cache_clear(vmx);
2603                 vmcs_writel(GUEST_GS_BASE, data);
2604                 break;
2605         case MSR_KERNEL_GS_BASE:
2606                 vmx_load_host_state(vmx);
2607                 vmx->msr_guest_kernel_gs_base = data;
2608                 break;
2609 #endif
2610         case MSR_IA32_SYSENTER_CS:
2611                 vmcs_write32(GUEST_SYSENTER_CS, data);
2612                 break;
2613         case MSR_IA32_SYSENTER_EIP:
2614                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2615                 break;
2616         case MSR_IA32_SYSENTER_ESP:
2617                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2618                 break;
2619         case MSR_IA32_BNDCFGS:
2620                 if (!vmx_mpx_supported())
2621                         return 1;
2622                 vmcs_write64(GUEST_BNDCFGS, data);
2623                 break;
2624         case MSR_IA32_TSC:
2625                 kvm_write_tsc(vcpu, msr_info);
2626                 break;
2627         case MSR_IA32_CR_PAT:
2628                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2629                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2630                                 return 1;
2631                         vmcs_write64(GUEST_IA32_PAT, data);
2632                         vcpu->arch.pat = data;
2633                         break;
2634                 }
2635                 ret = kvm_set_msr_common(vcpu, msr_info);
2636                 break;
2637         case MSR_IA32_TSC_ADJUST:
2638                 ret = kvm_set_msr_common(vcpu, msr_info);
2639                 break;
2640         case MSR_IA32_FEATURE_CONTROL:
2641                 if (!nested_vmx_allowed(vcpu) ||
2642                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2643                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2644                         return 1;
2645                 vmx->nested.msr_ia32_feature_control = data;
2646                 if (msr_info->host_initiated && data == 0)
2647                         vmx_leave_nested(vcpu);
2648                 break;
2649         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2650                 return 1; /* they are read-only */
2651         case MSR_TSC_AUX:
2652                 if (!vmx->rdtscp_enabled)
2653                         return 1;
2654                 /* Check reserved bit, higher 32 bits should be zero */
2655                 if ((data >> 32) != 0)
2656                         return 1;
2657                 /* Otherwise falls through */
2658         default:
2659                 msr = find_msr_entry(vmx, msr_index);
2660                 if (msr) {
2661                         msr->data = data;
2662                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2663                                 preempt_disable();
2664                                 kvm_set_shared_msr(msr->index, msr->data,
2665                                                    msr->mask);
2666                                 preempt_enable();
2667                         }
2668                         break;
2669                 }
2670                 ret = kvm_set_msr_common(vcpu, msr_info);
2671         }
2672
2673         return ret;
2674 }
2675
2676 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2677 {
2678         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2679         switch (reg) {
2680         case VCPU_REGS_RSP:
2681                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2682                 break;
2683         case VCPU_REGS_RIP:
2684                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2685                 break;
2686         case VCPU_EXREG_PDPTR:
2687                 if (enable_ept)
2688                         ept_save_pdptrs(vcpu);
2689                 break;
2690         default:
2691                 break;
2692         }
2693 }
2694
2695 static __init int cpu_has_kvm_support(void)
2696 {
2697         return cpu_has_vmx();
2698 }
2699
2700 static __init int vmx_disabled_by_bios(void)
2701 {
2702         u64 msr;
2703
2704         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2705         if (msr & FEATURE_CONTROL_LOCKED) {
2706                 /* launched w/ TXT and VMX disabled */
2707                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2708                         && tboot_enabled())
2709                         return 1;
2710                 /* launched w/o TXT and VMX only enabled w/ TXT */
2711                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2712                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2713                         && !tboot_enabled()) {
2714                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2715                                 "activate TXT before enabling KVM\n");
2716                         return 1;
2717                 }
2718                 /* launched w/o TXT and VMX disabled */
2719                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2720                         && !tboot_enabled())
2721                         return 1;
2722         }
2723
2724         return 0;
2725 }
2726
2727 static void kvm_cpu_vmxon(u64 addr)
2728 {
2729         asm volatile (ASM_VMX_VMXON_RAX
2730                         : : "a"(&addr), "m"(addr)
2731                         : "memory", "cc");
2732 }
2733
2734 static int hardware_enable(void)
2735 {
2736         int cpu = raw_smp_processor_id();
2737         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2738         u64 old, test_bits;
2739
2740         if (read_cr4() & X86_CR4_VMXE)
2741                 return -EBUSY;
2742
2743         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2744
2745         /*
2746          * Now we can enable the vmclear operation in kdump
2747          * since the loaded_vmcss_on_cpu list on this cpu
2748          * has been initialized.
2749          *
2750          * Though the cpu is not in VMX operation now, there
2751          * is no problem to enable the vmclear operation
2752          * for the loaded_vmcss_on_cpu list is empty!
2753          */
2754         crash_enable_local_vmclear(cpu);
2755
2756         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2757
2758         test_bits = FEATURE_CONTROL_LOCKED;
2759         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2760         if (tboot_enabled())
2761                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2762
2763         if ((old & test_bits) != test_bits) {
2764                 /* enable and lock */
2765                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2766         }
2767         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2768
2769         if (vmm_exclusive) {
2770                 kvm_cpu_vmxon(phys_addr);
2771                 ept_sync_global();
2772         }
2773
2774         native_store_gdt(this_cpu_ptr(&host_gdt));
2775
2776         return 0;
2777 }
2778
2779 static void vmclear_local_loaded_vmcss(void)
2780 {
2781         int cpu = raw_smp_processor_id();
2782         struct loaded_vmcs *v, *n;
2783
2784         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2785                                  loaded_vmcss_on_cpu_link)
2786                 __loaded_vmcs_clear(v);
2787 }
2788
2789
2790 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2791  * tricks.
2792  */
2793 static void kvm_cpu_vmxoff(void)
2794 {
2795         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2796 }
2797
2798 static void hardware_disable(void)
2799 {
2800         if (vmm_exclusive) {
2801                 vmclear_local_loaded_vmcss();
2802                 kvm_cpu_vmxoff();
2803         }
2804         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2805 }
2806
2807 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2808                                       u32 msr, u32 *result)
2809 {
2810         u32 vmx_msr_low, vmx_msr_high;
2811         u32 ctl = ctl_min | ctl_opt;
2812
2813         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2814
2815         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2816         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2817
2818         /* Ensure minimum (required) set of control bits are supported. */
2819         if (ctl_min & ~ctl)
2820                 return -EIO;
2821
2822         *result = ctl;
2823         return 0;
2824 }
2825
2826 static __init bool allow_1_setting(u32 msr, u32 ctl)
2827 {
2828         u32 vmx_msr_low, vmx_msr_high;
2829
2830         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2831         return vmx_msr_high & ctl;
2832 }
2833
2834 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2835 {
2836         u32 vmx_msr_low, vmx_msr_high;
2837         u32 min, opt, min2, opt2;
2838         u32 _pin_based_exec_control = 0;
2839         u32 _cpu_based_exec_control = 0;
2840         u32 _cpu_based_2nd_exec_control = 0;
2841         u32 _vmexit_control = 0;
2842         u32 _vmentry_control = 0;
2843
2844         min = CPU_BASED_HLT_EXITING |
2845 #ifdef CONFIG_X86_64
2846               CPU_BASED_CR8_LOAD_EXITING |
2847               CPU_BASED_CR8_STORE_EXITING |
2848 #endif
2849               CPU_BASED_CR3_LOAD_EXITING |
2850               CPU_BASED_CR3_STORE_EXITING |
2851               CPU_BASED_USE_IO_BITMAPS |
2852               CPU_BASED_MOV_DR_EXITING |
2853               CPU_BASED_USE_TSC_OFFSETING |
2854               CPU_BASED_MWAIT_EXITING |
2855               CPU_BASED_MONITOR_EXITING |
2856               CPU_BASED_INVLPG_EXITING |
2857               CPU_BASED_RDPMC_EXITING;
2858
2859         opt = CPU_BASED_TPR_SHADOW |
2860               CPU_BASED_USE_MSR_BITMAPS |
2861               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2862         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2863                                 &_cpu_based_exec_control) < 0)
2864                 return -EIO;
2865 #ifdef CONFIG_X86_64
2866         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2867                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2868                                            ~CPU_BASED_CR8_STORE_EXITING;
2869 #endif
2870         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2871                 min2 = 0;
2872                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2873                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2874                         SECONDARY_EXEC_WBINVD_EXITING |
2875                         SECONDARY_EXEC_ENABLE_VPID |
2876                         SECONDARY_EXEC_ENABLE_EPT |
2877                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2878                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2879                         SECONDARY_EXEC_RDTSCP |
2880                         SECONDARY_EXEC_ENABLE_INVPCID |
2881                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2882                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2883                         SECONDARY_EXEC_SHADOW_VMCS;
2884                 if (adjust_vmx_controls(min2, opt2,
2885                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2886                                         &_cpu_based_2nd_exec_control) < 0)
2887                         return -EIO;
2888         }
2889 #ifndef CONFIG_X86_64
2890         if (!(_cpu_based_2nd_exec_control &
2891                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2892                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2893 #endif
2894
2895         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2896                 _cpu_based_2nd_exec_control &= ~(
2897                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2898                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2899                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2900
2901         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2902                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2903                    enabled */
2904                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2905                                              CPU_BASED_CR3_STORE_EXITING |
2906                                              CPU_BASED_INVLPG_EXITING);
2907                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2908                       vmx_capability.ept, vmx_capability.vpid);
2909         }
2910
2911         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2912 #ifdef CONFIG_X86_64
2913         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2914 #endif
2915         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2916                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2917         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2918                                 &_vmexit_control) < 0)
2919                 return -EIO;
2920
2921         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2922         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2923         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2924                                 &_pin_based_exec_control) < 0)
2925                 return -EIO;
2926
2927         if (!(_cpu_based_2nd_exec_control &
2928                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2929                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2930                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2931
2932         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2933         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2934         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2935                                 &_vmentry_control) < 0)
2936                 return -EIO;
2937
2938         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2939
2940         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2941         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2942                 return -EIO;
2943
2944 #ifdef CONFIG_X86_64
2945         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2946         if (vmx_msr_high & (1u<<16))
2947                 return -EIO;
2948 #endif
2949
2950         /* Require Write-Back (WB) memory type for VMCS accesses. */
2951         if (((vmx_msr_high >> 18) & 15) != 6)
2952                 return -EIO;
2953
2954         vmcs_conf->size = vmx_msr_high & 0x1fff;
2955         vmcs_conf->order = get_order(vmcs_config.size);
2956         vmcs_conf->revision_id = vmx_msr_low;
2957
2958         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2959         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2960         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2961         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2962         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2963
2964         cpu_has_load_ia32_efer =
2965                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2966                                 VM_ENTRY_LOAD_IA32_EFER)
2967                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2968                                    VM_EXIT_LOAD_IA32_EFER);
2969
2970         cpu_has_load_perf_global_ctrl =
2971                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2972                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2973                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2974                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2975
2976         /*
2977          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2978          * but due to arrata below it can't be used. Workaround is to use
2979          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2980          *
2981          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2982          *
2983          * AAK155             (model 26)
2984          * AAP115             (model 30)
2985          * AAT100             (model 37)
2986          * BC86,AAY89,BD102   (model 44)
2987          * BA97               (model 46)
2988          *
2989          */
2990         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2991                 switch (boot_cpu_data.x86_model) {
2992                 case 26:
2993                 case 30:
2994                 case 37:
2995                 case 44:
2996                 case 46:
2997                         cpu_has_load_perf_global_ctrl = false;
2998                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2999                                         "does not work properly. Using workaround\n");
3000                         break;
3001                 default:
3002                         break;
3003                 }
3004         }
3005
3006         return 0;
3007 }
3008
3009 static struct vmcs *alloc_vmcs_cpu(int cpu)
3010 {
3011         int node = cpu_to_node(cpu);
3012         struct page *pages;
3013         struct vmcs *vmcs;
3014
3015         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3016         if (!pages)
3017                 return NULL;
3018         vmcs = page_address(pages);
3019         memset(vmcs, 0, vmcs_config.size);
3020         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3021         return vmcs;
3022 }
3023
3024 static struct vmcs *alloc_vmcs(void)
3025 {
3026         return alloc_vmcs_cpu(raw_smp_processor_id());
3027 }
3028
3029 static void free_vmcs(struct vmcs *vmcs)
3030 {
3031         free_pages((unsigned long)vmcs, vmcs_config.order);
3032 }
3033
3034 /*
3035  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3036  */
3037 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3038 {
3039         if (!loaded_vmcs->vmcs)
3040                 return;
3041         loaded_vmcs_clear(loaded_vmcs);
3042         free_vmcs(loaded_vmcs->vmcs);
3043         loaded_vmcs->vmcs = NULL;
3044 }
3045
3046 static void free_kvm_area(void)
3047 {
3048         int cpu;
3049
3050         for_each_possible_cpu(cpu) {
3051                 free_vmcs(per_cpu(vmxarea, cpu));
3052                 per_cpu(vmxarea, cpu) = NULL;
3053         }
3054 }
3055
3056 static void init_vmcs_shadow_fields(void)
3057 {
3058         int i, j;
3059
3060         /* No checks for read only fields yet */
3061
3062         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3063                 switch (shadow_read_write_fields[i]) {
3064                 case GUEST_BNDCFGS:
3065                         if (!vmx_mpx_supported())
3066                                 continue;
3067                         break;
3068                 default:
3069                         break;
3070                 }
3071
3072                 if (j < i)
3073                         shadow_read_write_fields[j] =
3074                                 shadow_read_write_fields[i];
3075                 j++;
3076         }
3077         max_shadow_read_write_fields = j;
3078
3079         /* shadowed fields guest access without vmexit */
3080         for (i = 0; i < max_shadow_read_write_fields; i++) {
3081                 clear_bit(shadow_read_write_fields[i],
3082                           vmx_vmwrite_bitmap);
3083                 clear_bit(shadow_read_write_fields[i],
3084                           vmx_vmread_bitmap);
3085         }
3086         for (i = 0; i < max_shadow_read_only_fields; i++)
3087                 clear_bit(shadow_read_only_fields[i],
3088                           vmx_vmread_bitmap);
3089 }
3090
3091 static __init int alloc_kvm_area(void)
3092 {
3093         int cpu;
3094
3095         for_each_possible_cpu(cpu) {
3096                 struct vmcs *vmcs;
3097
3098                 vmcs = alloc_vmcs_cpu(cpu);
3099                 if (!vmcs) {
3100                         free_kvm_area();
3101                         return -ENOMEM;
3102                 }
3103
3104                 per_cpu(vmxarea, cpu) = vmcs;
3105         }
3106         return 0;
3107 }
3108
3109 static __init int hardware_setup(void)
3110 {
3111         if (setup_vmcs_config(&vmcs_config) < 0)
3112                 return -EIO;
3113
3114         if (boot_cpu_has(X86_FEATURE_NX))
3115                 kvm_enable_efer_bits(EFER_NX);
3116
3117         if (!cpu_has_vmx_vpid())
3118                 enable_vpid = 0;
3119         if (!cpu_has_vmx_shadow_vmcs())
3120                 enable_shadow_vmcs = 0;
3121         if (enable_shadow_vmcs)
3122                 init_vmcs_shadow_fields();
3123
3124         if (!cpu_has_vmx_ept() ||
3125             !cpu_has_vmx_ept_4levels()) {
3126                 enable_ept = 0;
3127                 enable_unrestricted_guest = 0;
3128                 enable_ept_ad_bits = 0;
3129         }
3130
3131         if (!cpu_has_vmx_ept_ad_bits())
3132                 enable_ept_ad_bits = 0;
3133
3134         if (!cpu_has_vmx_unrestricted_guest())
3135                 enable_unrestricted_guest = 0;
3136
3137         if (!cpu_has_vmx_flexpriority()) {
3138                 flexpriority_enabled = 0;
3139
3140                 /*
3141                  * set_apic_access_page_addr() is used to reload apic access
3142                  * page upon invalidation.  No need to do anything if the
3143                  * processor does not have the APIC_ACCESS_ADDR VMCS field.
3144                  */
3145                 kvm_x86_ops->set_apic_access_page_addr = NULL;
3146         }
3147
3148         if (!cpu_has_vmx_tpr_shadow())
3149                 kvm_x86_ops->update_cr8_intercept = NULL;
3150
3151         if (enable_ept && !cpu_has_vmx_ept_2m_page())
3152                 kvm_disable_largepages();
3153
3154         if (!cpu_has_vmx_ple())
3155                 ple_gap = 0;
3156
3157         if (!cpu_has_vmx_apicv())
3158                 enable_apicv = 0;
3159
3160         if (enable_apicv)
3161                 kvm_x86_ops->update_cr8_intercept = NULL;
3162         else {
3163                 kvm_x86_ops->hwapic_irr_update = NULL;
3164                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3165                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3166         }
3167
3168         if (nested)
3169                 nested_vmx_setup_ctls_msrs();
3170
3171         return alloc_kvm_area();
3172 }
3173
3174 static __exit void hardware_unsetup(void)
3175 {
3176         free_kvm_area();
3177 }
3178
3179 static bool emulation_required(struct kvm_vcpu *vcpu)
3180 {
3181         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3182 }
3183
3184 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3185                 struct kvm_segment *save)
3186 {
3187         if (!emulate_invalid_guest_state) {
3188                 /*
3189                  * CS and SS RPL should be equal during guest entry according
3190                  * to VMX spec, but in reality it is not always so. Since vcpu
3191                  * is in the middle of the transition from real mode to
3192                  * protected mode it is safe to assume that RPL 0 is a good
3193                  * default value.
3194                  */
3195                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3196                         save->selector &= ~SELECTOR_RPL_MASK;
3197                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3198                 save->s = 1;
3199         }
3200         vmx_set_segment(vcpu, save, seg);
3201 }
3202
3203 static void enter_pmode(struct kvm_vcpu *vcpu)
3204 {
3205         unsigned long flags;
3206         struct vcpu_vmx *vmx = to_vmx(vcpu);
3207
3208         /*
3209          * Update real mode segment cache. It may be not up-to-date if sement
3210          * register was written while vcpu was in a guest mode.
3211          */
3212         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3213         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3214         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3215         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3216         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3217         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3218
3219         vmx->rmode.vm86_active = 0;
3220
3221         vmx_segment_cache_clear(vmx);
3222
3223         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3224
3225         flags = vmcs_readl(GUEST_RFLAGS);
3226         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3227         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3228         vmcs_writel(GUEST_RFLAGS, flags);
3229
3230         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3231                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3232
3233         update_exception_bitmap(vcpu);
3234
3235         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3236         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3237         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3238         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3239         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3240         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3241 }
3242
3243 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3244 {
3245         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3246         struct kvm_segment var = *save;
3247
3248         var.dpl = 0x3;
3249         if (seg == VCPU_SREG_CS)
3250                 var.type = 0x3;
3251
3252         if (!emulate_invalid_guest_state) {
3253                 var.selector = var.base >> 4;
3254                 var.base = var.base & 0xffff0;
3255                 var.limit = 0xffff;
3256                 var.g = 0;
3257                 var.db = 0;
3258                 var.present = 1;
3259                 var.s = 1;
3260                 var.l = 0;
3261                 var.unusable = 0;
3262                 var.type = 0x3;
3263                 var.avl = 0;
3264                 if (save->base & 0xf)
3265                         printk_once(KERN_WARNING "kvm: segment base is not "
3266                                         "paragraph aligned when entering "
3267                                         "protected mode (seg=%d)", seg);
3268         }
3269
3270         vmcs_write16(sf->selector, var.selector);
3271         vmcs_write32(sf->base, var.base);
3272         vmcs_write32(sf->limit, var.limit);
3273         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3274 }
3275
3276 static void enter_rmode(struct kvm_vcpu *vcpu)
3277 {
3278         unsigned long flags;
3279         struct vcpu_vmx *vmx = to_vmx(vcpu);
3280
3281         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3282         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3283         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3284         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3285         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3286         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3287         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3288
3289         vmx->rmode.vm86_active = 1;
3290
3291         /*
3292          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3293          * vcpu. Warn the user that an update is overdue.
3294          */
3295         if (!vcpu->kvm->arch.tss_addr)
3296                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3297                              "called before entering vcpu\n");
3298
3299         vmx_segment_cache_clear(vmx);
3300
3301         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3302         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3303         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3304
3305         flags = vmcs_readl(GUEST_RFLAGS);
3306         vmx->rmode.save_rflags = flags;
3307
3308         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3309
3310         vmcs_writel(GUEST_RFLAGS, flags);
3311         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3312         update_exception_bitmap(vcpu);
3313
3314         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3315         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3316         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3317         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3318         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3319         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3320
3321         kvm_mmu_reset_context(vcpu);
3322 }
3323
3324 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3325 {
3326         struct vcpu_vmx *vmx = to_vmx(vcpu);
3327         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3328
3329         if (!msr)
3330                 return;
3331
3332         /*
3333          * Force kernel_gs_base reloading before EFER changes, as control
3334          * of this msr depends on is_long_mode().
3335          */
3336         vmx_load_host_state(to_vmx(vcpu));
3337         vcpu->arch.efer = efer;
3338         if (efer & EFER_LMA) {
3339                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3340                 msr->data = efer;
3341         } else {
3342                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3343
3344                 msr->data = efer & ~EFER_LME;
3345         }
3346         setup_msrs(vmx);
3347 }
3348
3349 #ifdef CONFIG_X86_64
3350
3351 static void enter_lmode(struct kvm_vcpu *vcpu)
3352 {
3353         u32 guest_tr_ar;
3354
3355         vmx_segment_cache_clear(to_vmx(vcpu));
3356
3357         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3358         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3359                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3360                                      __func__);
3361                 vmcs_write32(GUEST_TR_AR_BYTES,
3362                              (guest_tr_ar & ~AR_TYPE_MASK)
3363                              | AR_TYPE_BUSY_64_TSS);
3364         }
3365         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3366 }
3367
3368 static void exit_lmode(struct kvm_vcpu *vcpu)
3369 {
3370         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3371         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3372 }
3373
3374 #endif
3375
3376 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3377 {
3378         vpid_sync_context(to_vmx(vcpu));
3379         if (enable_ept) {
3380                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3381                         return;
3382                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3383         }
3384 }
3385
3386 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3387 {
3388         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3389
3390         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3391         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3392 }
3393
3394 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3395 {
3396         if (enable_ept && is_paging(vcpu))
3397                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3398         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3399 }
3400
3401 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3402 {
3403         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3404
3405         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3406         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3407 }
3408
3409 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3410 {
3411         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3412
3413         if (!test_bit(VCPU_EXREG_PDPTR,
3414                       (unsigned long *)&vcpu->arch.regs_dirty))
3415                 return;
3416
3417         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3418                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3419                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3420                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3421                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3422         }
3423 }
3424
3425 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3426 {
3427         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3428
3429         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3430                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3431                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3432                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3433                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3434         }
3435
3436         __set_bit(VCPU_EXREG_PDPTR,
3437                   (unsigned long *)&vcpu->arch.regs_avail);
3438         __set_bit(VCPU_EXREG_PDPTR,
3439                   (unsigned long *)&vcpu->arch.regs_dirty);
3440 }
3441
3442 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3443
3444 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3445                                         unsigned long cr0,
3446                                         struct kvm_vcpu *vcpu)
3447 {
3448         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3449                 vmx_decache_cr3(vcpu);
3450         if (!(cr0 & X86_CR0_PG)) {
3451                 /* From paging/starting to nonpaging */
3452                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3453                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3454                              (CPU_BASED_CR3_LOAD_EXITING |
3455                               CPU_BASED_CR3_STORE_EXITING));
3456                 vcpu->arch.cr0 = cr0;
3457                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3458         } else if (!is_paging(vcpu)) {
3459                 /* From nonpaging to paging */
3460                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3461                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3462                              ~(CPU_BASED_CR3_LOAD_EXITING |
3463                                CPU_BASED_CR3_STORE_EXITING));
3464                 vcpu->arch.cr0 = cr0;
3465                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3466         }
3467
3468         if (!(cr0 & X86_CR0_WP))
3469                 *hw_cr0 &= ~X86_CR0_WP;
3470 }
3471
3472 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3473 {
3474         struct vcpu_vmx *vmx = to_vmx(vcpu);
3475         unsigned long hw_cr0;
3476
3477         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3478         if (enable_unrestricted_guest)
3479                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3480         else {
3481                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3482
3483                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3484                         enter_pmode(vcpu);
3485
3486                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3487                         enter_rmode(vcpu);
3488         }
3489
3490 #ifdef CONFIG_X86_64
3491         if (vcpu->arch.efer & EFER_LME) {
3492                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3493                         enter_lmode(vcpu);
3494                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3495                         exit_lmode(vcpu);
3496         }
3497 #endif
3498
3499         if (enable_ept)
3500                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3501
3502         if (!vcpu->fpu_active)
3503                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3504
3505         vmcs_writel(CR0_READ_SHADOW, cr0);
3506         vmcs_writel(GUEST_CR0, hw_cr0);
3507         vcpu->arch.cr0 = cr0;
3508
3509         /* depends on vcpu->arch.cr0 to be set to a new value */
3510         vmx->emulation_required = emulation_required(vcpu);
3511 }
3512
3513 static u64 construct_eptp(unsigned long root_hpa)
3514 {
3515         u64 eptp;
3516
3517         /* TODO write the value reading from MSR */
3518         eptp = VMX_EPT_DEFAULT_MT |
3519                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3520         if (enable_ept_ad_bits)
3521                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3522         eptp |= (root_hpa & PAGE_MASK);
3523
3524         return eptp;
3525 }
3526
3527 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3528 {
3529         unsigned long guest_cr3;
3530         u64 eptp;
3531
3532         guest_cr3 = cr3;
3533         if (enable_ept) {
3534                 eptp = construct_eptp(cr3);
3535                 vmcs_write64(EPT_POINTER, eptp);
3536                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3537                         guest_cr3 = kvm_read_cr3(vcpu);
3538                 else
3539                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3540                 ept_load_pdptrs(vcpu);
3541         }
3542
3543         vmx_flush_tlb(vcpu);
3544         vmcs_writel(GUEST_CR3, guest_cr3);
3545 }
3546
3547 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3548 {
3549         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3550                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3551
3552         if (cr4 & X86_CR4_VMXE) {
3553                 /*
3554                  * To use VMXON (and later other VMX instructions), a guest
3555                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3556                  * So basically the check on whether to allow nested VMX
3557                  * is here.
3558                  */
3559                 if (!nested_vmx_allowed(vcpu))
3560                         return 1;
3561         }
3562         if (to_vmx(vcpu)->nested.vmxon &&
3563             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3564                 return 1;
3565
3566         vcpu->arch.cr4 = cr4;
3567         if (enable_ept) {
3568                 if (!is_paging(vcpu)) {
3569                         hw_cr4 &= ~X86_CR4_PAE;
3570                         hw_cr4 |= X86_CR4_PSE;
3571                         /*
3572                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3573                          * in hardware. However KVM always uses paging mode to
3574                          * emulate guest non-paging mode with TDP.
3575                          * To emulate this behavior, SMEP/SMAP needs to be
3576                          * manually disabled when guest switches to non-paging
3577                          * mode.
3578                          */
3579                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3580                 } else if (!(cr4 & X86_CR4_PAE)) {
3581                         hw_cr4 &= ~X86_CR4_PAE;
3582                 }
3583         }
3584
3585         vmcs_writel(CR4_READ_SHADOW, cr4);
3586         vmcs_writel(GUEST_CR4, hw_cr4);
3587         return 0;
3588 }
3589
3590 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3591                             struct kvm_segment *var, int seg)
3592 {
3593         struct vcpu_vmx *vmx = to_vmx(vcpu);
3594         u32 ar;
3595
3596         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3597                 *var = vmx->rmode.segs[seg];
3598                 if (seg == VCPU_SREG_TR
3599                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3600                         return;
3601                 var->base = vmx_read_guest_seg_base(vmx, seg);
3602                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3603                 return;
3604         }
3605         var->base = vmx_read_guest_seg_base(vmx, seg);
3606         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3607         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3608         ar = vmx_read_guest_seg_ar(vmx, seg);
3609         var->unusable = (ar >> 16) & 1;
3610         var->type = ar & 15;
3611         var->s = (ar >> 4) & 1;
3612         var->dpl = (ar >> 5) & 3;
3613         /*
3614          * Some userspaces do not preserve unusable property. Since usable
3615          * segment has to be present according to VMX spec we can use present
3616          * property to amend userspace bug by making unusable segment always
3617          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3618          * segment as unusable.
3619          */
3620         var->present = !var->unusable;
3621         var->avl = (ar >> 12) & 1;
3622         var->l = (ar >> 13) & 1;
3623         var->db = (ar >> 14) & 1;
3624         var->g = (ar >> 15) & 1;
3625 }
3626
3627 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3628 {
3629         struct kvm_segment s;
3630
3631         if (to_vmx(vcpu)->rmode.vm86_active) {
3632                 vmx_get_segment(vcpu, &s, seg);
3633                 return s.base;
3634         }
3635         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3636 }
3637
3638 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3639 {
3640         struct vcpu_vmx *vmx = to_vmx(vcpu);
3641
3642         if (unlikely(vmx->rmode.vm86_active))
3643                 return 0;
3644         else {
3645                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3646                 return AR_DPL(ar);
3647         }
3648 }
3649
3650 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3651 {
3652         u32 ar;
3653
3654         if (var->unusable || !var->present)
3655                 ar = 1 << 16;
3656         else {
3657                 ar = var->type & 15;
3658                 ar |= (var->s & 1) << 4;
3659                 ar |= (var->dpl & 3) << 5;
3660                 ar |= (var->present & 1) << 7;
3661                 ar |= (var->avl & 1) << 12;
3662                 ar |= (var->l & 1) << 13;
3663                 ar |= (var->db & 1) << 14;
3664                 ar |= (var->g & 1) << 15;
3665         }
3666
3667         return ar;
3668 }
3669
3670 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3671                             struct kvm_segment *var, int seg)
3672 {
3673         struct vcpu_vmx *vmx = to_vmx(vcpu);
3674         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3675
3676         vmx_segment_cache_clear(vmx);
3677
3678         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3679                 vmx->rmode.segs[seg] = *var;
3680                 if (seg == VCPU_SREG_TR)
3681                         vmcs_write16(sf->selector, var->selector);
3682                 else if (var->s)
3683                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3684                 goto out;
3685         }
3686
3687         vmcs_writel(sf->base, var->base);
3688         vmcs_write32(sf->limit, var->limit);
3689         vmcs_write16(sf->selector, var->selector);
3690
3691         /*
3692          *   Fix the "Accessed" bit in AR field of segment registers for older
3693          * qemu binaries.
3694          *   IA32 arch specifies that at the time of processor reset the
3695          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3696          * is setting it to 0 in the userland code. This causes invalid guest
3697          * state vmexit when "unrestricted guest" mode is turned on.
3698          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3699          * tree. Newer qemu binaries with that qemu fix would not need this
3700          * kvm hack.
3701          */
3702         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3703                 var->type |= 0x1; /* Accessed */
3704
3705         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3706
3707 out:
3708         vmx->emulation_required = emulation_required(vcpu);
3709 }
3710
3711 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3712 {
3713         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3714
3715         *db = (ar >> 14) & 1;
3716         *l = (ar >> 13) & 1;
3717 }
3718
3719 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3720 {
3721         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3722         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3723 }
3724
3725 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3726 {
3727         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3728         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3729 }
3730
3731 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3732 {
3733         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3734         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3735 }
3736
3737 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3738 {
3739         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3740         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3741 }
3742
3743 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3744 {
3745         struct kvm_segment var;
3746         u32 ar;
3747
3748         vmx_get_segment(vcpu, &var, seg);
3749         var.dpl = 0x3;
3750         if (seg == VCPU_SREG_CS)
3751                 var.type = 0x3;
3752         ar = vmx_segment_access_rights(&var);
3753
3754         if (var.base != (var.selector << 4))
3755                 return false;
3756         if (var.limit != 0xffff)
3757                 return false;
3758         if (ar != 0xf3)
3759                 return false;
3760
3761         return true;
3762 }
3763
3764 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3765 {
3766         struct kvm_segment cs;
3767         unsigned int cs_rpl;
3768
3769         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3770         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3771
3772         if (cs.unusable)
3773                 return false;
3774         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3775                 return false;
3776         if (!cs.s)
3777                 return false;
3778         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3779                 if (cs.dpl > cs_rpl)
3780                         return false;
3781         } else {
3782                 if (cs.dpl != cs_rpl)
3783                         return false;
3784         }
3785         if (!cs.present)
3786                 return false;
3787
3788         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3789         return true;
3790 }
3791
3792 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3793 {
3794         struct kvm_segment ss;
3795         unsigned int ss_rpl;
3796
3797         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3798         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3799
3800         if (ss.unusable)
3801                 return true;
3802         if (ss.type != 3 && ss.type != 7)
3803                 return false;
3804         if (!ss.s)
3805                 return false;
3806         if (ss.dpl != ss_rpl) /* DPL != RPL */
3807                 return false;
3808         if (!ss.present)
3809                 return false;
3810
3811         return true;
3812 }
3813
3814 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3815 {
3816         struct kvm_segment var;
3817         unsigned int rpl;
3818
3819         vmx_get_segment(vcpu, &var, seg);
3820         rpl = var.selector & SELECTOR_RPL_MASK;
3821
3822         if (var.unusable)
3823                 return true;
3824         if (!var.s)
3825                 return false;
3826         if (!var.present)
3827                 return false;
3828         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3829                 if (var.dpl < rpl) /* DPL < RPL */
3830                         return false;
3831         }
3832
3833         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3834          * rights flags
3835          */
3836         return true;
3837 }
3838
3839 static bool tr_valid(struct kvm_vcpu *vcpu)
3840 {
3841         struct kvm_segment tr;
3842
3843         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3844
3845         if (tr.unusable)
3846                 return false;
3847         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3848                 return false;
3849         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3850                 return false;
3851         if (!tr.present)
3852                 return false;
3853
3854         return true;
3855 }
3856
3857 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3858 {
3859         struct kvm_segment ldtr;
3860
3861         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3862
3863         if (ldtr.unusable)
3864                 return true;
3865         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3866                 return false;
3867         if (ldtr.type != 2)
3868                 return false;
3869         if (!ldtr.present)
3870                 return false;
3871
3872         return true;
3873 }
3874
3875 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3876 {
3877         struct kvm_segment cs, ss;
3878
3879         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3880         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3881
3882         return ((cs.selector & SELECTOR_RPL_MASK) ==
3883                  (ss.selector & SELECTOR_RPL_MASK));
3884 }
3885
3886 /*
3887  * Check if guest state is valid. Returns true if valid, false if
3888  * not.
3889  * We assume that registers are always usable
3890  */
3891 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3892 {
3893         if (enable_unrestricted_guest)
3894                 return true;
3895
3896         /* real mode guest state checks */
3897         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3898                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3899                         return false;
3900                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3901                         return false;
3902                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3903                         return false;
3904                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3905                         return false;
3906                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3907                         return false;
3908                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3909                         return false;
3910         } else {
3911         /* protected mode guest state checks */
3912                 if (!cs_ss_rpl_check(vcpu))
3913                         return false;
3914                 if (!code_segment_valid(vcpu))
3915                         return false;
3916                 if (!stack_segment_valid(vcpu))
3917                         return false;
3918                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3919                         return false;
3920                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3921                         return false;
3922                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3923                         return false;
3924                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3925                         return false;
3926                 if (!tr_valid(vcpu))
3927                         return false;
3928                 if (!ldtr_valid(vcpu))
3929                         return false;
3930         }
3931         /* TODO:
3932          * - Add checks on RIP
3933          * - Add checks on RFLAGS
3934          */
3935
3936         return true;
3937 }
3938
3939 static int init_rmode_tss(struct kvm *kvm)
3940 {
3941         gfn_t fn;
3942         u16 data = 0;
3943         int idx, r;
3944
3945         idx = srcu_read_lock(&kvm->srcu);
3946         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3947         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3948         if (r < 0)
3949                 goto out;
3950         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3951         r = kvm_write_guest_page(kvm, fn++, &data,
3952                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3953         if (r < 0)
3954                 goto out;
3955         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3956         if (r < 0)
3957                 goto out;
3958         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3959         if (r < 0)
3960                 goto out;
3961         data = ~0;
3962         r = kvm_write_guest_page(kvm, fn, &data,
3963                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3964                                  sizeof(u8));
3965 out:
3966         srcu_read_unlock(&kvm->srcu, idx);
3967         return r;
3968 }
3969
3970 static int init_rmode_identity_map(struct kvm *kvm)
3971 {
3972         int i, idx, r = 0;
3973         pfn_t identity_map_pfn;
3974         u32 tmp;
3975
3976         if (!enable_ept)
3977                 return 0;
3978
3979         /* Protect kvm->arch.ept_identity_pagetable_done. */
3980         mutex_lock(&kvm->slots_lock);
3981
3982         if (likely(kvm->arch.ept_identity_pagetable_done))
3983                 goto out2;
3984
3985         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3986
3987         r = alloc_identity_pagetable(kvm);
3988         if (r < 0)
3989                 goto out2;
3990
3991         idx = srcu_read_lock(&kvm->srcu);
3992         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3993         if (r < 0)
3994                 goto out;
3995         /* Set up identity-mapping pagetable for EPT in real mode */
3996         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3997                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3998                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3999                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4000                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4001                 if (r < 0)
4002                         goto out;
4003         }
4004         kvm->arch.ept_identity_pagetable_done = true;
4005
4006 out:
4007         srcu_read_unlock(&kvm->srcu, idx);
4008
4009 out2:
4010         mutex_unlock(&kvm->slots_lock);
4011         return r;
4012 }
4013
4014 static void seg_setup(int seg)
4015 {
4016         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4017         unsigned int ar;
4018
4019         vmcs_write16(sf->selector, 0);
4020         vmcs_writel(sf->base, 0);
4021         vmcs_write32(sf->limit, 0xffff);
4022         ar = 0x93;
4023         if (seg == VCPU_SREG_CS)
4024                 ar |= 0x08; /* code segment */
4025
4026         vmcs_write32(sf->ar_bytes, ar);
4027 }
4028
4029 static int alloc_apic_access_page(struct kvm *kvm)
4030 {
4031         struct page *page;
4032         struct kvm_userspace_memory_region kvm_userspace_mem;
4033         int r = 0;
4034
4035         mutex_lock(&kvm->slots_lock);
4036         if (kvm->arch.apic_access_page_done)
4037                 goto out;
4038         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4039         kvm_userspace_mem.flags = 0;
4040         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
4041         kvm_userspace_mem.memory_size = PAGE_SIZE;
4042         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4043         if (r)
4044                 goto out;
4045
4046         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4047         if (is_error_page(page)) {
4048                 r = -EFAULT;
4049                 goto out;
4050         }
4051
4052         /*
4053          * Do not pin the page in memory, so that memory hot-unplug
4054          * is able to migrate it.
4055          */
4056         put_page(page);
4057         kvm->arch.apic_access_page_done = true;
4058 out:
4059         mutex_unlock(&kvm->slots_lock);
4060         return r;
4061 }
4062
4063 static int alloc_identity_pagetable(struct kvm *kvm)
4064 {
4065         /* Called with kvm->slots_lock held. */
4066
4067         struct kvm_userspace_memory_region kvm_userspace_mem;
4068         int r = 0;
4069
4070         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4071
4072         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4073         kvm_userspace_mem.flags = 0;
4074         kvm_userspace_mem.guest_phys_addr =
4075                 kvm->arch.ept_identity_map_addr;
4076         kvm_userspace_mem.memory_size = PAGE_SIZE;
4077         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4078
4079         return r;
4080 }
4081
4082 static void allocate_vpid(struct vcpu_vmx *vmx)
4083 {
4084         int vpid;
4085
4086         vmx->vpid = 0;
4087         if (!enable_vpid)
4088                 return;
4089         spin_lock(&vmx_vpid_lock);
4090         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4091         if (vpid < VMX_NR_VPIDS) {
4092                 vmx->vpid = vpid;
4093                 __set_bit(vpid, vmx_vpid_bitmap);
4094         }
4095         spin_unlock(&vmx_vpid_lock);
4096 }
4097
4098 static void free_vpid(struct vcpu_vmx *vmx)
4099 {
4100         if (!enable_vpid)
4101                 return;
4102         spin_lock(&vmx_vpid_lock);
4103         if (vmx->vpid != 0)
4104                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4105         spin_unlock(&vmx_vpid_lock);
4106 }
4107
4108 #define MSR_TYPE_R      1
4109 #define MSR_TYPE_W      2
4110 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4111                                                 u32 msr, int type)
4112 {
4113         int f = sizeof(unsigned long);
4114
4115         if (!cpu_has_vmx_msr_bitmap())
4116                 return;
4117
4118         /*
4119          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4120          * have the write-low and read-high bitmap offsets the wrong way round.
4121          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4122          */
4123         if (msr <= 0x1fff) {
4124                 if (type & MSR_TYPE_R)
4125                         /* read-low */
4126                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4127
4128                 if (type & MSR_TYPE_W)
4129                         /* write-low */
4130                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4131
4132         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4133                 msr &= 0x1fff;
4134                 if (type & MSR_TYPE_R)
4135                         /* read-high */
4136                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4137
4138                 if (type & MSR_TYPE_W)
4139                         /* write-high */
4140                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4141
4142         }
4143 }
4144
4145 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4146                                                 u32 msr, int type)
4147 {
4148         int f = sizeof(unsigned long);
4149
4150         if (!cpu_has_vmx_msr_bitmap())
4151                 return;
4152
4153         /*
4154          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4155          * have the write-low and read-high bitmap offsets the wrong way round.
4156          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4157          */
4158         if (msr <= 0x1fff) {
4159                 if (type & MSR_TYPE_R)
4160                         /* read-low */
4161                         __set_bit(msr, msr_bitmap + 0x000 / f);
4162
4163                 if (type & MSR_TYPE_W)
4164                         /* write-low */
4165                         __set_bit(msr, msr_bitmap + 0x800 / f);
4166
4167         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4168                 msr &= 0x1fff;
4169                 if (type & MSR_TYPE_R)
4170                         /* read-high */
4171                         __set_bit(msr, msr_bitmap + 0x400 / f);
4172
4173                 if (type & MSR_TYPE_W)
4174                         /* write-high */
4175                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4176
4177         }
4178 }
4179
4180 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4181 {
4182         if (!longmode_only)
4183                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4184                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4185         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4186                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4187 }
4188
4189 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4190 {
4191         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4192                         msr, MSR_TYPE_R);
4193         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4194                         msr, MSR_TYPE_R);
4195 }
4196
4197 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4198 {
4199         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4200                         msr, MSR_TYPE_R);
4201         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4202                         msr, MSR_TYPE_R);
4203 }
4204
4205 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4206 {
4207         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4208                         msr, MSR_TYPE_W);
4209         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4210                         msr, MSR_TYPE_W);
4211 }
4212
4213 static int vmx_vm_has_apicv(struct kvm *kvm)
4214 {
4215         return enable_apicv && irqchip_in_kernel(kvm);
4216 }
4217
4218 /*
4219  * Send interrupt to vcpu via posted interrupt way.
4220  * 1. If target vcpu is running(non-root mode), send posted interrupt
4221  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4222  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4223  * interrupt from PIR in next vmentry.
4224  */
4225 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4226 {
4227         struct vcpu_vmx *vmx = to_vmx(vcpu);
4228         int r;
4229
4230         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4231                 return;
4232
4233         r = pi_test_and_set_on(&vmx->pi_desc);
4234         kvm_make_request(KVM_REQ_EVENT, vcpu);
4235 #ifdef CONFIG_SMP
4236         if (!r && (vcpu->mode == IN_GUEST_MODE))
4237                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4238                                 POSTED_INTR_VECTOR);
4239         else
4240 #endif
4241                 kvm_vcpu_kick(vcpu);
4242 }
4243
4244 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4245 {
4246         struct vcpu_vmx *vmx = to_vmx(vcpu);
4247
4248         if (!pi_test_and_clear_on(&vmx->pi_desc))
4249                 return;
4250
4251         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4252 }
4253
4254 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4255 {
4256         return;
4257 }
4258
4259 /*
4260  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4261  * will not change in the lifetime of the guest.
4262  * Note that host-state that does change is set elsewhere. E.g., host-state
4263  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4264  */
4265 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4266 {
4267         u32 low32, high32;
4268         unsigned long tmpl;
4269         struct desc_ptr dt;
4270
4271         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4272         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4273         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4274
4275         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4276 #ifdef CONFIG_X86_64
4277         /*
4278          * Load null selectors, so we can avoid reloading them in
4279          * __vmx_load_host_state(), in case userspace uses the null selectors
4280          * too (the expected case).
4281          */
4282         vmcs_write16(HOST_DS_SELECTOR, 0);
4283         vmcs_write16(HOST_ES_SELECTOR, 0);
4284 #else
4285         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4286         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4287 #endif
4288         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4289         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4290
4291         native_store_idt(&dt);
4292         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4293         vmx->host_idt_base = dt.address;
4294
4295         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4296
4297         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4298         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4299         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4300         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4301
4302         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4303                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4304                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4305         }
4306 }
4307
4308 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4309 {
4310         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4311         if (enable_ept)
4312                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4313         if (is_guest_mode(&vmx->vcpu))
4314                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4315                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4316         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4317 }
4318
4319 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4320 {
4321         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4322
4323         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4324                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4325         return pin_based_exec_ctrl;
4326 }
4327
4328 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4329 {
4330         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4331
4332         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4333                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4334
4335         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4336                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4337 #ifdef CONFIG_X86_64
4338                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4339                                 CPU_BASED_CR8_LOAD_EXITING;
4340 #endif
4341         }
4342         if (!enable_ept)
4343                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4344                                 CPU_BASED_CR3_LOAD_EXITING  |
4345                                 CPU_BASED_INVLPG_EXITING;
4346         return exec_control;
4347 }
4348
4349 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4350 {
4351         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4352         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4353                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4354         if (vmx->vpid == 0)
4355                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4356         if (!enable_ept) {
4357                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4358                 enable_unrestricted_guest = 0;
4359                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4360                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4361         }
4362         if (!enable_unrestricted_guest)
4363                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4364         if (!ple_gap)
4365                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4366         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4367                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4368                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4369         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4370         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4371            (handle_vmptrld).
4372            We can NOT enable shadow_vmcs here because we don't have yet
4373            a current VMCS12
4374         */
4375         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4376         return exec_control;
4377 }
4378
4379 static void ept_set_mmio_spte_mask(void)
4380 {
4381         /*
4382          * EPT Misconfigurations can be generated if the value of bits 2:0
4383          * of an EPT paging-structure entry is 110b (write/execute).
4384          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4385          * spte.
4386          */
4387         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4388 }
4389
4390 /*
4391  * Sets up the vmcs for emulated real mode.
4392  */
4393 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4394 {
4395 #ifdef CONFIG_X86_64
4396         unsigned long a;
4397 #endif
4398         int i;
4399
4400         /* I/O */
4401         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4402         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4403
4404         if (enable_shadow_vmcs) {
4405                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4406                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4407         }
4408         if (cpu_has_vmx_msr_bitmap())
4409                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4410
4411         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4412
4413         /* Control */
4414         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4415
4416         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4417
4418         if (cpu_has_secondary_exec_ctrls()) {
4419                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4420                                 vmx_secondary_exec_control(vmx));
4421         }
4422
4423         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4424                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4425                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4426                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4427                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4428
4429                 vmcs_write16(GUEST_INTR_STATUS, 0);
4430
4431                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4432                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4433         }
4434
4435         if (ple_gap) {
4436                 vmcs_write32(PLE_GAP, ple_gap);
4437                 vmx->ple_window = ple_window;
4438                 vmx->ple_window_dirty = true;
4439         }
4440
4441         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4442         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4443         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4444
4445         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4446         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4447         vmx_set_constant_host_state(vmx);
4448 #ifdef CONFIG_X86_64
4449         rdmsrl(MSR_FS_BASE, a);
4450         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4451         rdmsrl(MSR_GS_BASE, a);
4452         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4453 #else
4454         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4455         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4456 #endif
4457
4458         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4459         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4460         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4461         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4462         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4463
4464         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4465                 u32 msr_low, msr_high;
4466                 u64 host_pat;
4467                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4468                 host_pat = msr_low | ((u64) msr_high << 32);
4469                 /* Write the default value follow host pat */
4470                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4471                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4472                 vmx->vcpu.arch.pat = host_pat;
4473         }
4474
4475         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4476                 u32 index = vmx_msr_index[i];
4477                 u32 data_low, data_high;
4478                 int j = vmx->nmsrs;
4479
4480                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4481                         continue;
4482                 if (wrmsr_safe(index, data_low, data_high) < 0)
4483                         continue;
4484                 vmx->guest_msrs[j].index = i;
4485                 vmx->guest_msrs[j].data = 0;
4486                 vmx->guest_msrs[j].mask = -1ull;
4487                 ++vmx->nmsrs;
4488         }
4489
4490
4491         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4492
4493         /* 22.2.1, 20.8.1 */
4494         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4495
4496         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4497         set_cr4_guest_host_mask(vmx);
4498
4499         return 0;
4500 }
4501
4502 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4503 {
4504         struct vcpu_vmx *vmx = to_vmx(vcpu);
4505         struct msr_data apic_base_msr;
4506
4507         vmx->rmode.vm86_active = 0;
4508
4509         vmx->soft_vnmi_blocked = 0;
4510
4511         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4512         kvm_set_cr8(&vmx->vcpu, 0);
4513         apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4514         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4515                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4516         apic_base_msr.host_initiated = true;
4517         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4518
4519         vmx_segment_cache_clear(vmx);
4520
4521         seg_setup(VCPU_SREG_CS);
4522         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4523         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4524
4525         seg_setup(VCPU_SREG_DS);
4526         seg_setup(VCPU_SREG_ES);
4527         seg_setup(VCPU_SREG_FS);
4528         seg_setup(VCPU_SREG_GS);
4529         seg_setup(VCPU_SREG_SS);
4530
4531         vmcs_write16(GUEST_TR_SELECTOR, 0);
4532         vmcs_writel(GUEST_TR_BASE, 0);
4533         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4534         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4535
4536         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4537         vmcs_writel(GUEST_LDTR_BASE, 0);
4538         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4539         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4540
4541         vmcs_write32(GUEST_SYSENTER_CS, 0);
4542         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4543         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4544
4545         vmcs_writel(GUEST_RFLAGS, 0x02);
4546         kvm_rip_write(vcpu, 0xfff0);
4547
4548         vmcs_writel(GUEST_GDTR_BASE, 0);
4549         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4550
4551         vmcs_writel(GUEST_IDTR_BASE, 0);
4552         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4553
4554         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4555         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4556         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4557
4558         /* Special registers */
4559         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4560
4561         setup_msrs(vmx);
4562
4563         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4564
4565         if (cpu_has_vmx_tpr_shadow()) {
4566                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4567                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4568                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4569                                      __pa(vmx->vcpu.arch.apic->regs));
4570                 vmcs_write32(TPR_THRESHOLD, 0);
4571         }
4572
4573         kvm_vcpu_reload_apic_access_page(vcpu);
4574
4575         if (vmx_vm_has_apicv(vcpu->kvm))
4576                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4577
4578         if (vmx->vpid != 0)
4579                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4580
4581         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4582         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4583         vmx_set_cr4(&vmx->vcpu, 0);
4584         vmx_set_efer(&vmx->vcpu, 0);
4585         vmx_fpu_activate(&vmx->vcpu);
4586         update_exception_bitmap(&vmx->vcpu);
4587
4588         vpid_sync_context(vmx);
4589 }
4590
4591 /*
4592  * In nested virtualization, check if L1 asked to exit on external interrupts.
4593  * For most existing hypervisors, this will always return true.
4594  */
4595 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4596 {
4597         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4598                 PIN_BASED_EXT_INTR_MASK;
4599 }
4600
4601 /*
4602  * In nested virtualization, check if L1 has set
4603  * VM_EXIT_ACK_INTR_ON_EXIT
4604  */
4605 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4606 {
4607         return get_vmcs12(vcpu)->vm_exit_controls &
4608                 VM_EXIT_ACK_INTR_ON_EXIT;
4609 }
4610
4611 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4612 {
4613         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4614                 PIN_BASED_NMI_EXITING;
4615 }
4616
4617 static void enable_irq_window(struct kvm_vcpu *vcpu)
4618 {
4619         u32 cpu_based_vm_exec_control;
4620
4621         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4622         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4623         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4624 }
4625
4626 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4627 {
4628         u32 cpu_based_vm_exec_control;
4629
4630         if (!cpu_has_virtual_nmis() ||
4631             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4632                 enable_irq_window(vcpu);
4633                 return;
4634         }
4635
4636         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4637         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4638         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4639 }
4640
4641 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4642 {
4643         struct vcpu_vmx *vmx = to_vmx(vcpu);
4644         uint32_t intr;
4645         int irq = vcpu->arch.interrupt.nr;
4646
4647         trace_kvm_inj_virq(irq);
4648
4649         ++vcpu->stat.irq_injections;
4650         if (vmx->rmode.vm86_active) {
4651                 int inc_eip = 0;
4652                 if (vcpu->arch.interrupt.soft)
4653                         inc_eip = vcpu->arch.event_exit_inst_len;
4654                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4655                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4656                 return;
4657         }
4658         intr = irq | INTR_INFO_VALID_MASK;
4659         if (vcpu->arch.interrupt.soft) {
4660                 intr |= INTR_TYPE_SOFT_INTR;
4661                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4662                              vmx->vcpu.arch.event_exit_inst_len);
4663         } else
4664                 intr |= INTR_TYPE_EXT_INTR;
4665         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4666 }
4667
4668 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4669 {
4670         struct vcpu_vmx *vmx = to_vmx(vcpu);
4671
4672         if (is_guest_mode(vcpu))
4673                 return;
4674
4675         if (!cpu_has_virtual_nmis()) {
4676                 /*
4677                  * Tracking the NMI-blocked state in software is built upon
4678                  * finding the next open IRQ window. This, in turn, depends on
4679                  * well-behaving guests: They have to keep IRQs disabled at
4680                  * least as long as the NMI handler runs. Otherwise we may
4681                  * cause NMI nesting, maybe breaking the guest. But as this is
4682                  * highly unlikely, we can live with the residual risk.
4683                  */
4684                 vmx->soft_vnmi_blocked = 1;
4685                 vmx->vnmi_blocked_time = 0;
4686         }
4687
4688         ++vcpu->stat.nmi_injections;
4689         vmx->nmi_known_unmasked = false;
4690         if (vmx->rmode.vm86_active) {
4691                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4692                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4693                 return;
4694         }
4695         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4696                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4697 }
4698
4699 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4700 {
4701         if (!cpu_has_virtual_nmis())
4702                 return to_vmx(vcpu)->soft_vnmi_blocked;
4703         if (to_vmx(vcpu)->nmi_known_unmasked)
4704                 return false;
4705         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4706 }
4707
4708 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4709 {
4710         struct vcpu_vmx *vmx = to_vmx(vcpu);
4711
4712         if (!cpu_has_virtual_nmis()) {
4713                 if (vmx->soft_vnmi_blocked != masked) {
4714                         vmx->soft_vnmi_blocked = masked;
4715                         vmx->vnmi_blocked_time = 0;
4716                 }
4717         } else {
4718                 vmx->nmi_known_unmasked = !masked;
4719                 if (masked)
4720                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4721                                       GUEST_INTR_STATE_NMI);
4722                 else
4723                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4724                                         GUEST_INTR_STATE_NMI);
4725         }
4726 }
4727
4728 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4729 {
4730         if (to_vmx(vcpu)->nested.nested_run_pending)
4731                 return 0;
4732
4733         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4734                 return 0;
4735
4736         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4737                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4738                    | GUEST_INTR_STATE_NMI));
4739 }
4740
4741 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4742 {
4743         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4744                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4745                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4746                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4747 }
4748
4749 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4750 {
4751         int ret;
4752         struct kvm_userspace_memory_region tss_mem = {
4753                 .slot = TSS_PRIVATE_MEMSLOT,
4754                 .guest_phys_addr = addr,
4755                 .memory_size = PAGE_SIZE * 3,
4756                 .flags = 0,
4757         };
4758
4759         ret = kvm_set_memory_region(kvm, &tss_mem);
4760         if (ret)
4761                 return ret;
4762         kvm->arch.tss_addr = addr;
4763         return init_rmode_tss(kvm);
4764 }
4765
4766 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4767 {
4768         switch (vec) {
4769         case BP_VECTOR:
4770                 /*
4771                  * Update instruction length as we may reinject the exception
4772                  * from user space while in guest debugging mode.
4773                  */
4774                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4775                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4776                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4777                         return false;
4778                 /* fall through */
4779         case DB_VECTOR:
4780                 if (vcpu->guest_debug &
4781                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4782                         return false;
4783                 /* fall through */
4784         case DE_VECTOR:
4785         case OF_VECTOR:
4786         case BR_VECTOR:
4787         case UD_VECTOR:
4788         case DF_VECTOR:
4789         case SS_VECTOR:
4790         case GP_VECTOR:
4791         case MF_VECTOR:
4792                 return true;
4793         break;
4794         }
4795         return false;
4796 }
4797
4798 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4799                                   int vec, u32 err_code)
4800 {
4801         /*
4802          * Instruction with address size override prefix opcode 0x67
4803          * Cause the #SS fault with 0 error code in VM86 mode.
4804          */
4805         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4806                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4807                         if (vcpu->arch.halt_request) {
4808                                 vcpu->arch.halt_request = 0;
4809                                 return kvm_emulate_halt(vcpu);
4810                         }
4811                         return 1;
4812                 }
4813                 return 0;
4814         }
4815
4816         /*
4817          * Forward all other exceptions that are valid in real mode.
4818          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4819          *        the required debugging infrastructure rework.
4820          */
4821         kvm_queue_exception(vcpu, vec);
4822         return 1;
4823 }
4824
4825 /*
4826  * Trigger machine check on the host. We assume all the MSRs are already set up
4827  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4828  * We pass a fake environment to the machine check handler because we want
4829  * the guest to be always treated like user space, no matter what context
4830  * it used internally.
4831  */
4832 static void kvm_machine_check(void)
4833 {
4834 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4835         struct pt_regs regs = {
4836                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4837                 .flags = X86_EFLAGS_IF,
4838         };
4839
4840         do_machine_check(&regs, 0);
4841 #endif
4842 }
4843
4844 static int handle_machine_check(struct kvm_vcpu *vcpu)
4845 {
4846         /* already handled by vcpu_run */
4847         return 1;
4848 }
4849
4850 static int handle_exception(struct kvm_vcpu *vcpu)
4851 {
4852         struct vcpu_vmx *vmx = to_vmx(vcpu);
4853         struct kvm_run *kvm_run = vcpu->run;
4854         u32 intr_info, ex_no, error_code;
4855         unsigned long cr2, rip, dr6;
4856         u32 vect_info;
4857         enum emulation_result er;
4858
4859         vect_info = vmx->idt_vectoring_info;
4860         intr_info = vmx->exit_intr_info;
4861
4862         if (is_machine_check(intr_info))
4863                 return handle_machine_check(vcpu);
4864
4865         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4866                 return 1;  /* already handled by vmx_vcpu_run() */
4867
4868         if (is_no_device(intr_info)) {
4869                 vmx_fpu_activate(vcpu);
4870                 return 1;
4871         }
4872
4873         if (is_invalid_opcode(intr_info)) {
4874                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4875                 if (er != EMULATE_DONE)
4876                         kvm_queue_exception(vcpu, UD_VECTOR);
4877                 return 1;
4878         }
4879
4880         error_code = 0;
4881         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4882                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4883
4884         /*
4885          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4886          * MMIO, it is better to report an internal error.
4887          * See the comments in vmx_handle_exit.
4888          */
4889         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4890             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4891                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4892                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4893                 vcpu->run->internal.ndata = 2;
4894                 vcpu->run->internal.data[0] = vect_info;
4895                 vcpu->run->internal.data[1] = intr_info;
4896                 return 0;
4897         }
4898
4899         if (is_page_fault(intr_info)) {
4900                 /* EPT won't cause page fault directly */
4901                 BUG_ON(enable_ept);
4902                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4903                 trace_kvm_page_fault(cr2, error_code);
4904
4905                 if (kvm_event_needs_reinjection(vcpu))
4906                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4907                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4908         }
4909
4910         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4911
4912         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4913                 return handle_rmode_exception(vcpu, ex_no, error_code);
4914
4915         switch (ex_no) {
4916         case DB_VECTOR:
4917                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4918                 if (!(vcpu->guest_debug &
4919                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4920                         vcpu->arch.dr6 &= ~15;
4921                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4922                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4923                                 skip_emulated_instruction(vcpu);
4924
4925                         kvm_queue_exception(vcpu, DB_VECTOR);
4926                         return 1;
4927                 }
4928                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4929                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4930                 /* fall through */
4931         case BP_VECTOR:
4932                 /*
4933                  * Update instruction length as we may reinject #BP from
4934                  * user space while in guest debugging mode. Reading it for
4935                  * #DB as well causes no harm, it is not used in that case.
4936                  */
4937                 vmx->vcpu.arch.event_exit_inst_len =
4938                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4939                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4940                 rip = kvm_rip_read(vcpu);
4941                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4942                 kvm_run->debug.arch.exception = ex_no;
4943                 break;
4944         default:
4945                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4946                 kvm_run->ex.exception = ex_no;
4947                 kvm_run->ex.error_code = error_code;
4948                 break;
4949         }
4950         return 0;
4951 }
4952
4953 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4954 {
4955         ++vcpu->stat.irq_exits;
4956         return 1;
4957 }
4958
4959 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4960 {
4961         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4962         return 0;
4963 }
4964
4965 static int handle_io(struct kvm_vcpu *vcpu)
4966 {
4967         unsigned long exit_qualification;
4968         int size, in, string;
4969         unsigned port;
4970
4971         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4972         string = (exit_qualification & 16) != 0;
4973         in = (exit_qualification & 8) != 0;
4974
4975         ++vcpu->stat.io_exits;
4976
4977         if (string || in)
4978                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4979
4980         port = exit_qualification >> 16;
4981         size = (exit_qualification & 7) + 1;
4982         skip_emulated_instruction(vcpu);
4983
4984         return kvm_fast_pio_out(vcpu, size, port);
4985 }
4986
4987 static void
4988 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4989 {
4990         /*
4991          * Patch in the VMCALL instruction:
4992          */
4993         hypercall[0] = 0x0f;
4994         hypercall[1] = 0x01;
4995         hypercall[2] = 0xc1;
4996 }
4997
4998 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4999 {
5000         unsigned long always_on = VMXON_CR0_ALWAYSON;
5001
5002         if (nested_vmx_secondary_ctls_high &
5003                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5004             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5005                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5006         return (val & always_on) == always_on;
5007 }
5008
5009 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5010 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5011 {
5012         if (is_guest_mode(vcpu)) {
5013                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5014                 unsigned long orig_val = val;
5015
5016                 /*
5017                  * We get here when L2 changed cr0 in a way that did not change
5018                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5019                  * but did change L0 shadowed bits. So we first calculate the
5020                  * effective cr0 value that L1 would like to write into the
5021                  * hardware. It consists of the L2-owned bits from the new
5022                  * value combined with the L1-owned bits from L1's guest_cr0.
5023                  */
5024                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5025                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5026
5027                 if (!nested_cr0_valid(vmcs12, val))
5028                         return 1;
5029
5030                 if (kvm_set_cr0(vcpu, val))
5031                         return 1;
5032                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5033                 return 0;
5034         } else {
5035                 if (to_vmx(vcpu)->nested.vmxon &&
5036                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5037                         return 1;
5038                 return kvm_set_cr0(vcpu, val);
5039         }
5040 }
5041
5042 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5043 {
5044         if (is_guest_mode(vcpu)) {
5045                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5046                 unsigned long orig_val = val;
5047
5048                 /* analogously to handle_set_cr0 */
5049                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5050                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5051                 if (kvm_set_cr4(vcpu, val))
5052                         return 1;
5053                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5054                 return 0;
5055         } else
5056                 return kvm_set_cr4(vcpu, val);
5057 }
5058
5059 /* called to set cr0 as approriate for clts instruction exit. */
5060 static void handle_clts(struct kvm_vcpu *vcpu)
5061 {
5062         if (is_guest_mode(vcpu)) {
5063                 /*
5064                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5065                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5066                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5067                  */
5068                 vmcs_writel(CR0_READ_SHADOW,
5069                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5070                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5071         } else
5072                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5073 }
5074
5075 static int handle_cr(struct kvm_vcpu *vcpu)
5076 {
5077         unsigned long exit_qualification, val;
5078         int cr;
5079         int reg;
5080         int err;
5081
5082         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5083         cr = exit_qualification & 15;
5084         reg = (exit_qualification >> 8) & 15;
5085         switch ((exit_qualification >> 4) & 3) {
5086         case 0: /* mov to cr */
5087                 val = kvm_register_readl(vcpu, reg);
5088                 trace_kvm_cr_write(cr, val);
5089                 switch (cr) {
5090                 case 0:
5091                         err = handle_set_cr0(vcpu, val);
5092                         kvm_complete_insn_gp(vcpu, err);
5093                         return 1;
5094                 case 3:
5095                         err = kvm_set_cr3(vcpu, val);
5096                         kvm_complete_insn_gp(vcpu, err);
5097                         return 1;
5098                 case 4:
5099                         err = handle_set_cr4(vcpu, val);
5100                         kvm_complete_insn_gp(vcpu, err);
5101                         return 1;
5102                 case 8: {
5103                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5104                                 u8 cr8 = (u8)val;
5105                                 err = kvm_set_cr8(vcpu, cr8);
5106                                 kvm_complete_insn_gp(vcpu, err);
5107                                 if (irqchip_in_kernel(vcpu->kvm))
5108                                         return 1;
5109                                 if (cr8_prev <= cr8)
5110                                         return 1;
5111                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5112                                 return 0;
5113                         }
5114                 }
5115                 break;
5116         case 2: /* clts */
5117                 handle_clts(vcpu);
5118                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5119                 skip_emulated_instruction(vcpu);
5120                 vmx_fpu_activate(vcpu);
5121                 return 1;
5122         case 1: /*mov from cr*/
5123                 switch (cr) {
5124                 case 3:
5125                         val = kvm_read_cr3(vcpu);
5126                         kvm_register_write(vcpu, reg, val);
5127                         trace_kvm_cr_read(cr, val);
5128                         skip_emulated_instruction(vcpu);
5129                         return 1;
5130                 case 8:
5131                         val = kvm_get_cr8(vcpu);
5132                         kvm_register_write(vcpu, reg, val);
5133                         trace_kvm_cr_read(cr, val);
5134                         skip_emulated_instruction(vcpu);
5135                         return 1;
5136                 }
5137                 break;
5138         case 3: /* lmsw */
5139                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5140                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5141                 kvm_lmsw(vcpu, val);
5142
5143                 skip_emulated_instruction(vcpu);
5144                 return 1;
5145         default:
5146                 break;
5147         }
5148         vcpu->run->exit_reason = 0;
5149         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5150                (int)(exit_qualification >> 4) & 3, cr);
5151         return 0;
5152 }
5153
5154 static int handle_dr(struct kvm_vcpu *vcpu)
5155 {
5156         unsigned long exit_qualification;
5157         int dr, reg;
5158
5159         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5160         if (!kvm_require_cpl(vcpu, 0))
5161                 return 1;
5162         dr = vmcs_readl(GUEST_DR7);
5163         if (dr & DR7_GD) {
5164                 /*
5165                  * As the vm-exit takes precedence over the debug trap, we
5166                  * need to emulate the latter, either for the host or the
5167                  * guest debugging itself.
5168                  */
5169                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5170                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5171                         vcpu->run->debug.arch.dr7 = dr;
5172                         vcpu->run->debug.arch.pc =
5173                                 vmcs_readl(GUEST_CS_BASE) +
5174                                 vmcs_readl(GUEST_RIP);
5175                         vcpu->run->debug.arch.exception = DB_VECTOR;
5176                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5177                         return 0;
5178                 } else {
5179                         vcpu->arch.dr7 &= ~DR7_GD;
5180                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5181                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5182                         kvm_queue_exception(vcpu, DB_VECTOR);
5183                         return 1;
5184                 }
5185         }
5186
5187         if (vcpu->guest_debug == 0) {
5188                 u32 cpu_based_vm_exec_control;
5189
5190                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5191                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5192                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5193
5194                 /*
5195                  * No more DR vmexits; force a reload of the debug registers
5196                  * and reenter on this instruction.  The next vmexit will
5197                  * retrieve the full state of the debug registers.
5198                  */
5199                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5200                 return 1;
5201         }
5202
5203         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5204         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5205         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5206         if (exit_qualification & TYPE_MOV_FROM_DR) {
5207                 unsigned long val;
5208
5209                 if (kvm_get_dr(vcpu, dr, &val))
5210                         return 1;
5211                 kvm_register_write(vcpu, reg, val);
5212         } else
5213                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5214                         return 1;
5215
5216         skip_emulated_instruction(vcpu);
5217         return 1;
5218 }
5219
5220 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5221 {
5222         return vcpu->arch.dr6;
5223 }
5224
5225 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5226 {
5227 }
5228
5229 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5230 {
5231         u32 cpu_based_vm_exec_control;
5232
5233         get_debugreg(vcpu->arch.db[0], 0);
5234         get_debugreg(vcpu->arch.db[1], 1);
5235         get_debugreg(vcpu->arch.db[2], 2);
5236         get_debugreg(vcpu->arch.db[3], 3);
5237         get_debugreg(vcpu->arch.dr6, 6);
5238         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5239
5240         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5241
5242         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5243         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5244         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5245 }
5246
5247 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5248 {
5249         vmcs_writel(GUEST_DR7, val);
5250 }
5251
5252 static int handle_cpuid(struct kvm_vcpu *vcpu)
5253 {
5254         kvm_emulate_cpuid(vcpu);
5255         return 1;
5256 }
5257
5258 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5259 {
5260         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5261         u64 data;
5262
5263         if (vmx_get_msr(vcpu, ecx, &data)) {
5264                 trace_kvm_msr_read_ex(ecx);
5265                 kvm_inject_gp(vcpu, 0);
5266                 return 1;
5267         }
5268
5269         trace_kvm_msr_read(ecx, data);
5270
5271         /* FIXME: handling of bits 32:63 of rax, rdx */
5272         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5273         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5274         skip_emulated_instruction(vcpu);
5275         return 1;
5276 }
5277
5278 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5279 {
5280         struct msr_data msr;
5281         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5282         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5283                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5284
5285         msr.data = data;
5286         msr.index = ecx;
5287         msr.host_initiated = false;
5288         if (vmx_set_msr(vcpu, &msr) != 0) {
5289                 trace_kvm_msr_write_ex(ecx, data);
5290                 kvm_inject_gp(vcpu, 0);
5291                 return 1;
5292         }
5293
5294         trace_kvm_msr_write(ecx, data);
5295         skip_emulated_instruction(vcpu);
5296         return 1;
5297 }
5298
5299 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5300 {
5301         kvm_make_request(KVM_REQ_EVENT, vcpu);
5302         return 1;
5303 }
5304
5305 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5306 {
5307         u32 cpu_based_vm_exec_control;
5308
5309         /* clear pending irq */
5310         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5311         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5312         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5313
5314         kvm_make_request(KVM_REQ_EVENT, vcpu);
5315
5316         ++vcpu->stat.irq_window_exits;
5317
5318         /*
5319          * If the user space waits to inject interrupts, exit as soon as
5320          * possible
5321          */
5322         if (!irqchip_in_kernel(vcpu->kvm) &&
5323             vcpu->run->request_interrupt_window &&
5324             !kvm_cpu_has_interrupt(vcpu)) {
5325                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5326                 return 0;
5327         }
5328         return 1;
5329 }
5330
5331 static int handle_halt(struct kvm_vcpu *vcpu)
5332 {
5333         skip_emulated_instruction(vcpu);
5334         return kvm_emulate_halt(vcpu);
5335 }
5336
5337 static int handle_vmcall(struct kvm_vcpu *vcpu)
5338 {
5339         skip_emulated_instruction(vcpu);
5340         kvm_emulate_hypercall(vcpu);
5341         return 1;
5342 }
5343
5344 static int handle_invd(struct kvm_vcpu *vcpu)
5345 {
5346         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5347 }
5348
5349 static int handle_invlpg(struct kvm_vcpu *vcpu)
5350 {
5351         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5352
5353         kvm_mmu_invlpg(vcpu, exit_qualification);
5354         skip_emulated_instruction(vcpu);
5355         return 1;
5356 }
5357
5358 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5359 {
5360         int err;
5361
5362         err = kvm_rdpmc(vcpu);
5363         kvm_complete_insn_gp(vcpu, err);
5364
5365         return 1;
5366 }
5367
5368 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5369 {
5370         skip_emulated_instruction(vcpu);
5371         kvm_emulate_wbinvd(vcpu);
5372         return 1;
5373 }
5374
5375 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5376 {
5377         u64 new_bv = kvm_read_edx_eax(vcpu);
5378         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5379
5380         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5381                 skip_emulated_instruction(vcpu);
5382         return 1;
5383 }
5384
5385 static int handle_apic_access(struct kvm_vcpu *vcpu)
5386 {
5387         if (likely(fasteoi)) {
5388                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5389                 int access_type, offset;
5390
5391                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5392                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5393                 /*
5394                  * Sane guest uses MOV to write EOI, with written value
5395                  * not cared. So make a short-circuit here by avoiding
5396                  * heavy instruction emulation.
5397                  */
5398                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5399                     (offset == APIC_EOI)) {
5400                         kvm_lapic_set_eoi(vcpu);
5401                         skip_emulated_instruction(vcpu);
5402                         return 1;
5403                 }
5404         }
5405         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5406 }
5407
5408 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5409 {
5410         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5411         int vector = exit_qualification & 0xff;
5412
5413         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5414         kvm_apic_set_eoi_accelerated(vcpu, vector);
5415         return 1;
5416 }
5417
5418 static int handle_apic_write(struct kvm_vcpu *vcpu)
5419 {
5420         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5421         u32 offset = exit_qualification & 0xfff;
5422
5423         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5424         kvm_apic_write_nodecode(vcpu, offset);
5425         return 1;
5426 }
5427
5428 static int handle_task_switch(struct kvm_vcpu *vcpu)
5429 {
5430         struct vcpu_vmx *vmx = to_vmx(vcpu);
5431         unsigned long exit_qualification;
5432         bool has_error_code = false;
5433         u32 error_code = 0;
5434         u16 tss_selector;
5435         int reason, type, idt_v, idt_index;
5436
5437         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5438         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5439         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5440
5441         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5442
5443         reason = (u32)exit_qualification >> 30;
5444         if (reason == TASK_SWITCH_GATE && idt_v) {
5445                 switch (type) {
5446                 case INTR_TYPE_NMI_INTR:
5447                         vcpu->arch.nmi_injected = false;
5448                         vmx_set_nmi_mask(vcpu, true);
5449                         break;
5450                 case INTR_TYPE_EXT_INTR:
5451                 case INTR_TYPE_SOFT_INTR:
5452                         kvm_clear_interrupt_queue(vcpu);
5453                         break;
5454                 case INTR_TYPE_HARD_EXCEPTION:
5455                         if (vmx->idt_vectoring_info &
5456                             VECTORING_INFO_DELIVER_CODE_MASK) {
5457                                 has_error_code = true;
5458                                 error_code =
5459                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5460                         }
5461                         /* fall through */
5462                 case INTR_TYPE_SOFT_EXCEPTION:
5463                         kvm_clear_exception_queue(vcpu);
5464                         break;
5465                 default:
5466                         break;
5467                 }
5468         }
5469         tss_selector = exit_qualification;
5470
5471         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5472                        type != INTR_TYPE_EXT_INTR &&
5473                        type != INTR_TYPE_NMI_INTR))
5474                 skip_emulated_instruction(vcpu);
5475
5476         if (kvm_task_switch(vcpu, tss_selector,
5477                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5478                             has_error_code, error_code) == EMULATE_FAIL) {
5479                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5480                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5481                 vcpu->run->internal.ndata = 0;
5482                 return 0;
5483         }
5484
5485         /* clear all local breakpoint enable flags */
5486         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
5487
5488         /*
5489          * TODO: What about debug traps on tss switch?
5490          *       Are we supposed to inject them and update dr6?
5491          */
5492
5493         return 1;
5494 }
5495
5496 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5497 {
5498         unsigned long exit_qualification;
5499         gpa_t gpa;
5500         u32 error_code;
5501         int gla_validity;
5502
5503         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5504
5505         gla_validity = (exit_qualification >> 7) & 0x3;
5506         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5507                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5508                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5509                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5510                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5511                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5512                         (long unsigned int)exit_qualification);
5513                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5514                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5515                 return 0;
5516         }
5517
5518         /*
5519          * EPT violation happened while executing iret from NMI,
5520          * "blocked by NMI" bit has to be set before next VM entry.
5521          * There are errata that may cause this bit to not be set:
5522          * AAK134, BY25.
5523          */
5524         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5525                         cpu_has_virtual_nmis() &&
5526                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5527                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5528
5529         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5530         trace_kvm_page_fault(gpa, exit_qualification);
5531
5532         /* It is a write fault? */
5533         error_code = exit_qualification & (1U << 1);
5534         /* It is a fetch fault? */
5535         error_code |= (exit_qualification & (1U << 2)) << 2;
5536         /* ept page table is present? */
5537         error_code |= (exit_qualification >> 3) & 0x1;
5538
5539         vcpu->arch.exit_qualification = exit_qualification;
5540
5541         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5542 }
5543
5544 static u64 ept_rsvd_mask(u64 spte, int level)
5545 {
5546         int i;
5547         u64 mask = 0;
5548
5549         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5550                 mask |= (1ULL << i);
5551
5552         if (level == 4)
5553                 /* bits 7:3 reserved */
5554                 mask |= 0xf8;
5555         else if (spte & (1ULL << 7))
5556                 /*
5557                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5558                  * level == 1 if the hypervisor is using the ignored bit 7.
5559                  */
5560                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5561         else if (level > 1)
5562                 /* bits 6:3 reserved */
5563                 mask |= 0x78;
5564
5565         return mask;
5566 }
5567
5568 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5569                                        int level)
5570 {
5571         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5572
5573         /* 010b (write-only) */
5574         WARN_ON((spte & 0x7) == 0x2);
5575
5576         /* 110b (write/execute) */
5577         WARN_ON((spte & 0x7) == 0x6);
5578
5579         /* 100b (execute-only) and value not supported by logical processor */
5580         if (!cpu_has_vmx_ept_execute_only())
5581                 WARN_ON((spte & 0x7) == 0x4);
5582
5583         /* not 000b */
5584         if ((spte & 0x7)) {
5585                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5586
5587                 if (rsvd_bits != 0) {
5588                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5589                                          __func__, rsvd_bits);
5590                         WARN_ON(1);
5591                 }
5592
5593                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5594                 if ((rsvd_bits & 0x38) == 0) {
5595                         u64 ept_mem_type = (spte & 0x38) >> 3;
5596
5597                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5598                             ept_mem_type == 7) {
5599                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5600                                                 __func__, ept_mem_type);
5601                                 WARN_ON(1);
5602                         }
5603                 }
5604         }
5605 }
5606
5607 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5608 {
5609         u64 sptes[4];
5610         int nr_sptes, i, ret;
5611         gpa_t gpa;
5612
5613         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5614         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5615                 skip_emulated_instruction(vcpu);
5616                 return 1;
5617         }
5618
5619         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5620         if (likely(ret == RET_MMIO_PF_EMULATE))
5621                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5622                                               EMULATE_DONE;
5623
5624         if (unlikely(ret == RET_MMIO_PF_INVALID))
5625                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5626
5627         if (unlikely(ret == RET_MMIO_PF_RETRY))
5628                 return 1;
5629
5630         /* It is the real ept misconfig */
5631         printk(KERN_ERR "EPT: Misconfiguration.\n");
5632         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5633
5634         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5635
5636         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5637                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5638
5639         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5640         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5641
5642         return 0;
5643 }
5644
5645 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5646 {
5647         u32 cpu_based_vm_exec_control;
5648
5649         /* clear pending NMI */
5650         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5651         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5652         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5653         ++vcpu->stat.nmi_window_exits;
5654         kvm_make_request(KVM_REQ_EVENT, vcpu);
5655
5656         return 1;
5657 }
5658
5659 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5660 {
5661         struct vcpu_vmx *vmx = to_vmx(vcpu);
5662         enum emulation_result err = EMULATE_DONE;
5663         int ret = 1;
5664         u32 cpu_exec_ctrl;
5665         bool intr_window_requested;
5666         unsigned count = 130;
5667
5668         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5669         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5670
5671         while (vmx->emulation_required && count-- != 0) {
5672                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5673                         return handle_interrupt_window(&vmx->vcpu);
5674
5675                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5676                         return 1;
5677
5678                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5679
5680                 if (err == EMULATE_USER_EXIT) {
5681                         ++vcpu->stat.mmio_exits;
5682                         ret = 0;
5683                         goto out;
5684                 }
5685
5686                 if (err != EMULATE_DONE) {
5687                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5688                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5689                         vcpu->run->internal.ndata = 0;
5690                         return 0;
5691                 }
5692
5693                 if (vcpu->arch.halt_request) {
5694                         vcpu->arch.halt_request = 0;
5695                         ret = kvm_emulate_halt(vcpu);
5696                         goto out;
5697                 }
5698
5699                 if (signal_pending(current))
5700                         goto out;
5701                 if (need_resched())
5702                         schedule();
5703         }
5704
5705 out:
5706         return ret;
5707 }
5708
5709 static int __grow_ple_window(int val)
5710 {
5711         if (ple_window_grow < 1)
5712                 return ple_window;
5713
5714         val = min(val, ple_window_actual_max);
5715
5716         if (ple_window_grow < ple_window)
5717                 val *= ple_window_grow;
5718         else
5719                 val += ple_window_grow;
5720
5721         return val;
5722 }
5723
5724 static int __shrink_ple_window(int val, int modifier, int minimum)
5725 {
5726         if (modifier < 1)
5727                 return ple_window;
5728
5729         if (modifier < ple_window)
5730                 val /= modifier;
5731         else
5732                 val -= modifier;
5733
5734         return max(val, minimum);
5735 }
5736
5737 static void grow_ple_window(struct kvm_vcpu *vcpu)
5738 {
5739         struct vcpu_vmx *vmx = to_vmx(vcpu);
5740         int old = vmx->ple_window;
5741
5742         vmx->ple_window = __grow_ple_window(old);
5743
5744         if (vmx->ple_window != old)
5745                 vmx->ple_window_dirty = true;
5746
5747         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5748 }
5749
5750 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5751 {
5752         struct vcpu_vmx *vmx = to_vmx(vcpu);
5753         int old = vmx->ple_window;
5754
5755         vmx->ple_window = __shrink_ple_window(old,
5756                                               ple_window_shrink, ple_window);
5757
5758         if (vmx->ple_window != old)
5759                 vmx->ple_window_dirty = true;
5760
5761         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5762 }
5763
5764 /*
5765  * ple_window_actual_max is computed to be one grow_ple_window() below
5766  * ple_window_max. (See __grow_ple_window for the reason.)
5767  * This prevents overflows, because ple_window_max is int.
5768  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5769  * this process.
5770  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5771  */
5772 static void update_ple_window_actual_max(void)
5773 {
5774         ple_window_actual_max =
5775                         __shrink_ple_window(max(ple_window_max, ple_window),
5776                                             ple_window_grow, INT_MIN);
5777 }
5778
5779 /*
5780  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5781  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5782  */
5783 static int handle_pause(struct kvm_vcpu *vcpu)
5784 {
5785         if (ple_gap)
5786                 grow_ple_window(vcpu);
5787
5788         skip_emulated_instruction(vcpu);
5789         kvm_vcpu_on_spin(vcpu);
5790
5791         return 1;
5792 }
5793
5794 static int handle_nop(struct kvm_vcpu *vcpu)
5795 {
5796         skip_emulated_instruction(vcpu);
5797         return 1;
5798 }
5799
5800 static int handle_mwait(struct kvm_vcpu *vcpu)
5801 {
5802         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5803         return handle_nop(vcpu);
5804 }
5805
5806 static int handle_monitor(struct kvm_vcpu *vcpu)
5807 {
5808         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5809         return handle_nop(vcpu);
5810 }
5811
5812 /*
5813  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5814  * We could reuse a single VMCS for all the L2 guests, but we also want the
5815  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5816  * allows keeping them loaded on the processor, and in the future will allow
5817  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5818  * every entry if they never change.
5819  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5820  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5821  *
5822  * The following functions allocate and free a vmcs02 in this pool.
5823  */
5824
5825 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5826 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5827 {
5828         struct vmcs02_list *item;
5829         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5830                 if (item->vmptr == vmx->nested.current_vmptr) {
5831                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5832                         return &item->vmcs02;
5833                 }
5834
5835         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5836                 /* Recycle the least recently used VMCS. */
5837                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5838                         struct vmcs02_list, list);
5839                 item->vmptr = vmx->nested.current_vmptr;
5840                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5841                 return &item->vmcs02;
5842         }
5843
5844         /* Create a new VMCS */
5845         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5846         if (!item)
5847                 return NULL;
5848         item->vmcs02.vmcs = alloc_vmcs();
5849         if (!item->vmcs02.vmcs) {
5850                 kfree(item);
5851                 return NULL;
5852         }
5853         loaded_vmcs_init(&item->vmcs02);
5854         item->vmptr = vmx->nested.current_vmptr;
5855         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5856         vmx->nested.vmcs02_num++;
5857         return &item->vmcs02;
5858 }
5859
5860 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5861 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5862 {
5863         struct vmcs02_list *item;
5864         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5865                 if (item->vmptr == vmptr) {
5866                         free_loaded_vmcs(&item->vmcs02);
5867                         list_del(&item->list);
5868                         kfree(item);
5869                         vmx->nested.vmcs02_num--;
5870                         return;
5871                 }
5872 }
5873
5874 /*
5875  * Free all VMCSs saved for this vcpu, except the one pointed by
5876  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5877  * must be &vmx->vmcs01.
5878  */
5879 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5880 {
5881         struct vmcs02_list *item, *n;
5882
5883         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
5884         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5885                 /*
5886                  * Something will leak if the above WARN triggers.  Better than
5887                  * a use-after-free.
5888                  */
5889                 if (vmx->loaded_vmcs == &item->vmcs02)
5890                         continue;
5891
5892                 free_loaded_vmcs(&item->vmcs02);
5893                 list_del(&item->list);
5894                 kfree(item);
5895                 vmx->nested.vmcs02_num--;
5896         }
5897 }
5898
5899 /*
5900  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5901  * set the success or error code of an emulated VMX instruction, as specified
5902  * by Vol 2B, VMX Instruction Reference, "Conventions".
5903  */
5904 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5905 {
5906         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5907                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5908                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5909 }
5910
5911 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5912 {
5913         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5914                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5915                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5916                         | X86_EFLAGS_CF);
5917 }
5918
5919 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5920                                         u32 vm_instruction_error)
5921 {
5922         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5923                 /*
5924                  * failValid writes the error number to the current VMCS, which
5925                  * can't be done there isn't a current VMCS.
5926                  */
5927                 nested_vmx_failInvalid(vcpu);
5928                 return;
5929         }
5930         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5931                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5932                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5933                         | X86_EFLAGS_ZF);
5934         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5935         /*
5936          * We don't need to force a shadow sync because
5937          * VM_INSTRUCTION_ERROR is not shadowed
5938          */
5939 }
5940
5941 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5942 {
5943         struct vcpu_vmx *vmx =
5944                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5945
5946         vmx->nested.preemption_timer_expired = true;
5947         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5948         kvm_vcpu_kick(&vmx->vcpu);
5949
5950         return HRTIMER_NORESTART;
5951 }
5952
5953 /*
5954  * Decode the memory-address operand of a vmx instruction, as recorded on an
5955  * exit caused by such an instruction (run by a guest hypervisor).
5956  * On success, returns 0. When the operand is invalid, returns 1 and throws
5957  * #UD or #GP.
5958  */
5959 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5960                                  unsigned long exit_qualification,
5961                                  u32 vmx_instruction_info, gva_t *ret)
5962 {
5963         /*
5964          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5965          * Execution", on an exit, vmx_instruction_info holds most of the
5966          * addressing components of the operand. Only the displacement part
5967          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5968          * For how an actual address is calculated from all these components,
5969          * refer to Vol. 1, "Operand Addressing".
5970          */
5971         int  scaling = vmx_instruction_info & 3;
5972         int  addr_size = (vmx_instruction_info >> 7) & 7;
5973         bool is_reg = vmx_instruction_info & (1u << 10);
5974         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5975         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5976         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5977         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5978         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5979
5980         if (is_reg) {
5981                 kvm_queue_exception(vcpu, UD_VECTOR);
5982                 return 1;
5983         }
5984
5985         /* Addr = segment_base + offset */
5986         /* offset = base + [index * scale] + displacement */
5987         *ret = vmx_get_segment_base(vcpu, seg_reg);
5988         if (base_is_valid)
5989                 *ret += kvm_register_read(vcpu, base_reg);
5990         if (index_is_valid)
5991                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5992         *ret += exit_qualification; /* holds the displacement */
5993
5994         if (addr_size == 1) /* 32 bit */
5995                 *ret &= 0xffffffff;
5996
5997         /*
5998          * TODO: throw #GP (and return 1) in various cases that the VM*
5999          * instructions require it - e.g., offset beyond segment limit,
6000          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6001          * address, and so on. Currently these are not checked.
6002          */
6003         return 0;
6004 }
6005
6006 /*
6007  * This function performs the various checks including
6008  * - if it's 4KB aligned
6009  * - No bits beyond the physical address width are set
6010  * - Returns 0 on success or else 1
6011  * (Intel SDM Section 30.3)
6012  */
6013 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6014                                   gpa_t *vmpointer)
6015 {
6016         gva_t gva;
6017         gpa_t vmptr;
6018         struct x86_exception e;
6019         struct page *page;
6020         struct vcpu_vmx *vmx = to_vmx(vcpu);
6021         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6022
6023         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6024                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6025                 return 1;
6026
6027         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6028                                 sizeof(vmptr), &e)) {
6029                 kvm_inject_page_fault(vcpu, &e);
6030                 return 1;
6031         }
6032
6033         switch (exit_reason) {
6034         case EXIT_REASON_VMON:
6035                 /*
6036                  * SDM 3: 24.11.5
6037                  * The first 4 bytes of VMXON region contain the supported
6038                  * VMCS revision identifier
6039                  *
6040                  * Note - IA32_VMX_BASIC[48] will never be 1
6041                  * for the nested case;
6042                  * which replaces physical address width with 32
6043                  *
6044                  */
6045                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6046                         nested_vmx_failInvalid(vcpu);
6047                         skip_emulated_instruction(vcpu);
6048                         return 1;
6049                 }
6050
6051                 page = nested_get_page(vcpu, vmptr);
6052                 if (page == NULL ||
6053                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6054                         nested_vmx_failInvalid(vcpu);
6055                         kunmap(page);
6056                         skip_emulated_instruction(vcpu);
6057                         return 1;
6058                 }
6059                 kunmap(page);
6060                 vmx->nested.vmxon_ptr = vmptr;
6061                 break;
6062         case EXIT_REASON_VMCLEAR:
6063                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6064                         nested_vmx_failValid(vcpu,
6065                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6066                         skip_emulated_instruction(vcpu);
6067                         return 1;
6068                 }
6069
6070                 if (vmptr == vmx->nested.vmxon_ptr) {
6071                         nested_vmx_failValid(vcpu,
6072                                              VMXERR_VMCLEAR_VMXON_POINTER);
6073                         skip_emulated_instruction(vcpu);
6074                         return 1;
6075                 }
6076                 break;
6077         case EXIT_REASON_VMPTRLD:
6078                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6079                         nested_vmx_failValid(vcpu,
6080                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6081                         skip_emulated_instruction(vcpu);
6082                         return 1;
6083                 }
6084
6085                 if (vmptr == vmx->nested.vmxon_ptr) {
6086                         nested_vmx_failValid(vcpu,
6087                                              VMXERR_VMCLEAR_VMXON_POINTER);
6088                         skip_emulated_instruction(vcpu);
6089                         return 1;
6090                 }
6091                 break;
6092         default:
6093                 return 1; /* shouldn't happen */
6094         }
6095
6096         if (vmpointer)
6097                 *vmpointer = vmptr;
6098         return 0;
6099 }
6100
6101 /*
6102  * Emulate the VMXON instruction.
6103  * Currently, we just remember that VMX is active, and do not save or even
6104  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6105  * do not currently need to store anything in that guest-allocated memory
6106  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6107  * argument is different from the VMXON pointer (which the spec says they do).
6108  */
6109 static int handle_vmon(struct kvm_vcpu *vcpu)
6110 {
6111         struct kvm_segment cs;
6112         struct vcpu_vmx *vmx = to_vmx(vcpu);
6113         struct vmcs *shadow_vmcs;
6114         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6115                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6116
6117         /* The Intel VMX Instruction Reference lists a bunch of bits that
6118          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6119          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6120          * Otherwise, we should fail with #UD. We test these now:
6121          */
6122         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6123             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6124             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6125                 kvm_queue_exception(vcpu, UD_VECTOR);
6126                 return 1;
6127         }
6128
6129         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6130         if (is_long_mode(vcpu) && !cs.l) {
6131                 kvm_queue_exception(vcpu, UD_VECTOR);
6132                 return 1;
6133         }
6134
6135         if (vmx_get_cpl(vcpu)) {
6136                 kvm_inject_gp(vcpu, 0);
6137                 return 1;
6138         }
6139
6140         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6141                 return 1;
6142
6143         if (vmx->nested.vmxon) {
6144                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6145                 skip_emulated_instruction(vcpu);
6146                 return 1;
6147         }
6148
6149         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6150                         != VMXON_NEEDED_FEATURES) {
6151                 kvm_inject_gp(vcpu, 0);
6152                 return 1;
6153         }
6154
6155         if (enable_shadow_vmcs) {
6156                 shadow_vmcs = alloc_vmcs();
6157                 if (!shadow_vmcs)
6158                         return -ENOMEM;
6159                 /* mark vmcs as shadow */
6160                 shadow_vmcs->revision_id |= (1u << 31);
6161                 /* init shadow vmcs */
6162                 vmcs_clear(shadow_vmcs);
6163                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6164         }
6165
6166         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6167         vmx->nested.vmcs02_num = 0;
6168
6169         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6170                      HRTIMER_MODE_REL);
6171         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6172
6173         vmx->nested.vmxon = true;
6174
6175         skip_emulated_instruction(vcpu);
6176         nested_vmx_succeed(vcpu);
6177         return 1;
6178 }
6179
6180 /*
6181  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6182  * for running VMX instructions (except VMXON, whose prerequisites are
6183  * slightly different). It also specifies what exception to inject otherwise.
6184  */
6185 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6186 {
6187         struct kvm_segment cs;
6188         struct vcpu_vmx *vmx = to_vmx(vcpu);
6189
6190         if (!vmx->nested.vmxon) {
6191                 kvm_queue_exception(vcpu, UD_VECTOR);
6192                 return 0;
6193         }
6194
6195         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6196         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6197             (is_long_mode(vcpu) && !cs.l)) {
6198                 kvm_queue_exception(vcpu, UD_VECTOR);
6199                 return 0;
6200         }
6201
6202         if (vmx_get_cpl(vcpu)) {
6203                 kvm_inject_gp(vcpu, 0);
6204                 return 0;
6205         }
6206
6207         return 1;
6208 }
6209
6210 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6211 {
6212         u32 exec_control;
6213         if (vmx->nested.current_vmptr == -1ull)
6214                 return;
6215
6216         /* current_vmptr and current_vmcs12 are always set/reset together */
6217         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6218                 return;
6219
6220         if (enable_shadow_vmcs) {
6221                 /* copy to memory all shadowed fields in case
6222                    they were modified */
6223                 copy_shadow_to_vmcs12(vmx);
6224                 vmx->nested.sync_shadow_vmcs = false;
6225                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6226                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6227                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6228                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6229         }
6230         kunmap(vmx->nested.current_vmcs12_page);
6231         nested_release_page(vmx->nested.current_vmcs12_page);
6232         vmx->nested.current_vmptr = -1ull;
6233         vmx->nested.current_vmcs12 = NULL;
6234 }
6235
6236 /*
6237  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6238  * just stops using VMX.
6239  */
6240 static void free_nested(struct vcpu_vmx *vmx)
6241 {
6242         if (!vmx->nested.vmxon)
6243                 return;
6244
6245         vmx->nested.vmxon = false;
6246         nested_release_vmcs12(vmx);
6247         if (enable_shadow_vmcs)
6248                 free_vmcs(vmx->nested.current_shadow_vmcs);
6249         /* Unpin physical memory we referred to in current vmcs02 */
6250         if (vmx->nested.apic_access_page) {
6251                 nested_release_page(vmx->nested.apic_access_page);
6252                 vmx->nested.apic_access_page = NULL;
6253         }
6254         if (vmx->nested.virtual_apic_page) {
6255                 nested_release_page(vmx->nested.virtual_apic_page);
6256                 vmx->nested.virtual_apic_page = NULL;
6257         }
6258
6259         nested_free_all_saved_vmcss(vmx);
6260 }
6261
6262 /* Emulate the VMXOFF instruction */
6263 static int handle_vmoff(struct kvm_vcpu *vcpu)
6264 {
6265         if (!nested_vmx_check_permission(vcpu))
6266                 return 1;
6267         free_nested(to_vmx(vcpu));
6268         skip_emulated_instruction(vcpu);
6269         nested_vmx_succeed(vcpu);
6270         return 1;
6271 }
6272
6273 /* Emulate the VMCLEAR instruction */
6274 static int handle_vmclear(struct kvm_vcpu *vcpu)
6275 {
6276         struct vcpu_vmx *vmx = to_vmx(vcpu);
6277         gpa_t vmptr;
6278         struct vmcs12 *vmcs12;
6279         struct page *page;
6280
6281         if (!nested_vmx_check_permission(vcpu))
6282                 return 1;
6283
6284         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6285                 return 1;
6286
6287         if (vmptr == vmx->nested.current_vmptr)
6288                 nested_release_vmcs12(vmx);
6289
6290         page = nested_get_page(vcpu, vmptr);
6291         if (page == NULL) {
6292                 /*
6293                  * For accurate processor emulation, VMCLEAR beyond available
6294                  * physical memory should do nothing at all. However, it is
6295                  * possible that a nested vmx bug, not a guest hypervisor bug,
6296                  * resulted in this case, so let's shut down before doing any
6297                  * more damage:
6298                  */
6299                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6300                 return 1;
6301         }
6302         vmcs12 = kmap(page);
6303         vmcs12->launch_state = 0;
6304         kunmap(page);
6305         nested_release_page(page);
6306
6307         nested_free_vmcs02(vmx, vmptr);
6308
6309         skip_emulated_instruction(vcpu);
6310         nested_vmx_succeed(vcpu);
6311         return 1;
6312 }
6313
6314 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6315
6316 /* Emulate the VMLAUNCH instruction */
6317 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6318 {
6319         return nested_vmx_run(vcpu, true);
6320 }
6321
6322 /* Emulate the VMRESUME instruction */
6323 static int handle_vmresume(struct kvm_vcpu *vcpu)
6324 {
6325
6326         return nested_vmx_run(vcpu, false);
6327 }
6328
6329 enum vmcs_field_type {
6330         VMCS_FIELD_TYPE_U16 = 0,
6331         VMCS_FIELD_TYPE_U64 = 1,
6332         VMCS_FIELD_TYPE_U32 = 2,
6333         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6334 };
6335
6336 static inline int vmcs_field_type(unsigned long field)
6337 {
6338         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6339                 return VMCS_FIELD_TYPE_U32;
6340         return (field >> 13) & 0x3 ;
6341 }
6342
6343 static inline int vmcs_field_readonly(unsigned long field)
6344 {
6345         return (((field >> 10) & 0x3) == 1);
6346 }
6347
6348 /*
6349  * Read a vmcs12 field. Since these can have varying lengths and we return
6350  * one type, we chose the biggest type (u64) and zero-extend the return value
6351  * to that size. Note that the caller, handle_vmread, might need to use only
6352  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6353  * 64-bit fields are to be returned).
6354  */
6355 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6356                                         unsigned long field, u64 *ret)
6357 {
6358         short offset = vmcs_field_to_offset(field);
6359         char *p;
6360
6361         if (offset < 0)
6362                 return 0;
6363
6364         p = ((char *)(get_vmcs12(vcpu))) + offset;
6365
6366         switch (vmcs_field_type(field)) {
6367         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6368                 *ret = *((natural_width *)p);
6369                 return 1;
6370         case VMCS_FIELD_TYPE_U16:
6371                 *ret = *((u16 *)p);
6372                 return 1;
6373         case VMCS_FIELD_TYPE_U32:
6374                 *ret = *((u32 *)p);
6375                 return 1;
6376         case VMCS_FIELD_TYPE_U64:
6377                 *ret = *((u64 *)p);
6378                 return 1;
6379         default:
6380                 return 0; /* can never happen. */
6381         }
6382 }
6383
6384
6385 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6386                                     unsigned long field, u64 field_value){
6387         short offset = vmcs_field_to_offset(field);
6388         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6389         if (offset < 0)
6390                 return false;
6391
6392         switch (vmcs_field_type(field)) {
6393         case VMCS_FIELD_TYPE_U16:
6394                 *(u16 *)p = field_value;
6395                 return true;
6396         case VMCS_FIELD_TYPE_U32:
6397                 *(u32 *)p = field_value;
6398                 return true;
6399         case VMCS_FIELD_TYPE_U64:
6400                 *(u64 *)p = field_value;
6401                 return true;
6402         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6403                 *(natural_width *)p = field_value;
6404                 return true;
6405         default:
6406                 return false; /* can never happen. */
6407         }
6408
6409 }
6410
6411 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6412 {
6413         int i;
6414         unsigned long field;
6415         u64 field_value;
6416         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6417         const unsigned long *fields = shadow_read_write_fields;
6418         const int num_fields = max_shadow_read_write_fields;
6419
6420         vmcs_load(shadow_vmcs);
6421
6422         for (i = 0; i < num_fields; i++) {
6423                 field = fields[i];
6424                 switch (vmcs_field_type(field)) {
6425                 case VMCS_FIELD_TYPE_U16:
6426                         field_value = vmcs_read16(field);
6427                         break;
6428                 case VMCS_FIELD_TYPE_U32:
6429                         field_value = vmcs_read32(field);
6430                         break;
6431                 case VMCS_FIELD_TYPE_U64:
6432                         field_value = vmcs_read64(field);
6433                         break;
6434                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6435                         field_value = vmcs_readl(field);
6436                         break;
6437                 }
6438                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6439         }
6440
6441         vmcs_clear(shadow_vmcs);
6442         vmcs_load(vmx->loaded_vmcs->vmcs);
6443 }
6444
6445 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6446 {
6447         const unsigned long *fields[] = {
6448                 shadow_read_write_fields,
6449                 shadow_read_only_fields
6450         };
6451         const int max_fields[] = {
6452                 max_shadow_read_write_fields,
6453                 max_shadow_read_only_fields
6454         };
6455         int i, q;
6456         unsigned long field;
6457         u64 field_value = 0;
6458         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6459
6460         vmcs_load(shadow_vmcs);
6461
6462         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6463                 for (i = 0; i < max_fields[q]; i++) {
6464                         field = fields[q][i];
6465                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6466
6467                         switch (vmcs_field_type(field)) {
6468                         case VMCS_FIELD_TYPE_U16:
6469                                 vmcs_write16(field, (u16)field_value);
6470                                 break;
6471                         case VMCS_FIELD_TYPE_U32:
6472                                 vmcs_write32(field, (u32)field_value);
6473                                 break;
6474                         case VMCS_FIELD_TYPE_U64:
6475                                 vmcs_write64(field, (u64)field_value);
6476                                 break;
6477                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6478                                 vmcs_writel(field, (long)field_value);
6479                                 break;
6480                         }
6481                 }
6482         }
6483
6484         vmcs_clear(shadow_vmcs);
6485         vmcs_load(vmx->loaded_vmcs->vmcs);
6486 }
6487
6488 /*
6489  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6490  * used before) all generate the same failure when it is missing.
6491  */
6492 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6493 {
6494         struct vcpu_vmx *vmx = to_vmx(vcpu);
6495         if (vmx->nested.current_vmptr == -1ull) {
6496                 nested_vmx_failInvalid(vcpu);
6497                 skip_emulated_instruction(vcpu);
6498                 return 0;
6499         }
6500         return 1;
6501 }
6502
6503 static int handle_vmread(struct kvm_vcpu *vcpu)
6504 {
6505         unsigned long field;
6506         u64 field_value;
6507         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6508         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6509         gva_t gva = 0;
6510
6511         if (!nested_vmx_check_permission(vcpu) ||
6512             !nested_vmx_check_vmcs12(vcpu))
6513                 return 1;
6514
6515         /* Decode instruction info and find the field to read */
6516         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6517         /* Read the field, zero-extended to a u64 field_value */
6518         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6519                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6520                 skip_emulated_instruction(vcpu);
6521                 return 1;
6522         }
6523         /*
6524          * Now copy part of this value to register or memory, as requested.
6525          * Note that the number of bits actually copied is 32 or 64 depending
6526          * on the guest's mode (32 or 64 bit), not on the given field's length.
6527          */
6528         if (vmx_instruction_info & (1u << 10)) {
6529                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6530                         field_value);
6531         } else {
6532                 if (get_vmx_mem_address(vcpu, exit_qualification,
6533                                 vmx_instruction_info, &gva))
6534                         return 1;
6535                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6536                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6537                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6538         }
6539
6540         nested_vmx_succeed(vcpu);
6541         skip_emulated_instruction(vcpu);
6542         return 1;
6543 }
6544
6545
6546 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6547 {
6548         unsigned long field;
6549         gva_t gva;
6550         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6551         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6552         /* The value to write might be 32 or 64 bits, depending on L1's long
6553          * mode, and eventually we need to write that into a field of several
6554          * possible lengths. The code below first zero-extends the value to 64
6555          * bit (field_value), and then copies only the approriate number of
6556          * bits into the vmcs12 field.
6557          */
6558         u64 field_value = 0;
6559         struct x86_exception e;
6560
6561         if (!nested_vmx_check_permission(vcpu) ||
6562             !nested_vmx_check_vmcs12(vcpu))
6563                 return 1;
6564
6565         if (vmx_instruction_info & (1u << 10))
6566                 field_value = kvm_register_readl(vcpu,
6567                         (((vmx_instruction_info) >> 3) & 0xf));
6568         else {
6569                 if (get_vmx_mem_address(vcpu, exit_qualification,
6570                                 vmx_instruction_info, &gva))
6571                         return 1;
6572                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6573                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
6574                         kvm_inject_page_fault(vcpu, &e);
6575                         return 1;
6576                 }
6577         }
6578
6579
6580         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6581         if (vmcs_field_readonly(field)) {
6582                 nested_vmx_failValid(vcpu,
6583                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6584                 skip_emulated_instruction(vcpu);
6585                 return 1;
6586         }
6587
6588         if (!vmcs12_write_any(vcpu, field, field_value)) {
6589                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6590                 skip_emulated_instruction(vcpu);
6591                 return 1;
6592         }
6593
6594         nested_vmx_succeed(vcpu);
6595         skip_emulated_instruction(vcpu);
6596         return 1;
6597 }
6598
6599 /* Emulate the VMPTRLD instruction */
6600 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6601 {
6602         struct vcpu_vmx *vmx = to_vmx(vcpu);
6603         gpa_t vmptr;
6604         u32 exec_control;
6605
6606         if (!nested_vmx_check_permission(vcpu))
6607                 return 1;
6608
6609         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
6610                 return 1;
6611
6612         if (vmx->nested.current_vmptr != vmptr) {
6613                 struct vmcs12 *new_vmcs12;
6614                 struct page *page;
6615                 page = nested_get_page(vcpu, vmptr);
6616                 if (page == NULL) {
6617                         nested_vmx_failInvalid(vcpu);
6618                         skip_emulated_instruction(vcpu);
6619                         return 1;
6620                 }
6621                 new_vmcs12 = kmap(page);
6622                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6623                         kunmap(page);
6624                         nested_release_page_clean(page);
6625                         nested_vmx_failValid(vcpu,
6626                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6627                         skip_emulated_instruction(vcpu);
6628                         return 1;
6629                 }
6630
6631                 nested_release_vmcs12(vmx);
6632                 vmx->nested.current_vmptr = vmptr;
6633                 vmx->nested.current_vmcs12 = new_vmcs12;
6634                 vmx->nested.current_vmcs12_page = page;
6635                 if (enable_shadow_vmcs) {
6636                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6637                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6638                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6639                         vmcs_write64(VMCS_LINK_POINTER,
6640                                      __pa(vmx->nested.current_shadow_vmcs));
6641                         vmx->nested.sync_shadow_vmcs = true;
6642                 }
6643         }
6644
6645         nested_vmx_succeed(vcpu);
6646         skip_emulated_instruction(vcpu);
6647         return 1;
6648 }
6649
6650 /* Emulate the VMPTRST instruction */
6651 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6652 {
6653         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6654         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6655         gva_t vmcs_gva;
6656         struct x86_exception e;
6657
6658         if (!nested_vmx_check_permission(vcpu))
6659                 return 1;
6660
6661         if (get_vmx_mem_address(vcpu, exit_qualification,
6662                         vmx_instruction_info, &vmcs_gva))
6663                 return 1;
6664         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6665         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6666                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6667                                  sizeof(u64), &e)) {
6668                 kvm_inject_page_fault(vcpu, &e);
6669                 return 1;
6670         }
6671         nested_vmx_succeed(vcpu);
6672         skip_emulated_instruction(vcpu);
6673         return 1;
6674 }
6675
6676 /* Emulate the INVEPT instruction */
6677 static int handle_invept(struct kvm_vcpu *vcpu)
6678 {
6679         u32 vmx_instruction_info, types;
6680         unsigned long type;
6681         gva_t gva;
6682         struct x86_exception e;
6683         struct {
6684                 u64 eptp, gpa;
6685         } operand;
6686
6687         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6688             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6689                 kvm_queue_exception(vcpu, UD_VECTOR);
6690                 return 1;
6691         }
6692
6693         if (!nested_vmx_check_permission(vcpu))
6694                 return 1;
6695
6696         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6697                 kvm_queue_exception(vcpu, UD_VECTOR);
6698                 return 1;
6699         }
6700
6701         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6702         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
6703
6704         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6705
6706         if (!(types & (1UL << type))) {
6707                 nested_vmx_failValid(vcpu,
6708                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6709                 return 1;
6710         }
6711
6712         /* According to the Intel VMX instruction reference, the memory
6713          * operand is read even if it isn't needed (e.g., for type==global)
6714          */
6715         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6716                         vmx_instruction_info, &gva))
6717                 return 1;
6718         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6719                                 sizeof(operand), &e)) {
6720                 kvm_inject_page_fault(vcpu, &e);
6721                 return 1;
6722         }
6723
6724         switch (type) {
6725         case VMX_EPT_EXTENT_GLOBAL:
6726                 kvm_mmu_sync_roots(vcpu);
6727                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
6728                 nested_vmx_succeed(vcpu);
6729                 break;
6730         default:
6731                 /* Trap single context invalidation invept calls */
6732                 BUG_ON(1);
6733                 break;
6734         }
6735
6736         skip_emulated_instruction(vcpu);
6737         return 1;
6738 }
6739
6740 /*
6741  * The exit handlers return 1 if the exit was handled fully and guest execution
6742  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6743  * to be done to userspace and return 0.
6744  */
6745 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6746         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6747         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6748         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6749         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6750         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6751         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6752         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6753         [EXIT_REASON_CPUID]                   = handle_cpuid,
6754         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6755         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6756         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6757         [EXIT_REASON_HLT]                     = handle_halt,
6758         [EXIT_REASON_INVD]                    = handle_invd,
6759         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6760         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6761         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6762         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6763         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6764         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6765         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6766         [EXIT_REASON_VMREAD]                  = handle_vmread,
6767         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6768         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6769         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6770         [EXIT_REASON_VMON]                    = handle_vmon,
6771         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6772         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6773         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6774         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6775         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6776         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6777         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6778         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6779         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6780         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6781         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6782         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
6783         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
6784         [EXIT_REASON_INVEPT]                  = handle_invept,
6785 };
6786
6787 static const int kvm_vmx_max_exit_handlers =
6788         ARRAY_SIZE(kvm_vmx_exit_handlers);
6789
6790 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6791                                        struct vmcs12 *vmcs12)
6792 {
6793         unsigned long exit_qualification;
6794         gpa_t bitmap, last_bitmap;
6795         unsigned int port;
6796         int size;
6797         u8 b;
6798
6799         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6800                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6801
6802         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6803
6804         port = exit_qualification >> 16;
6805         size = (exit_qualification & 7) + 1;
6806
6807         last_bitmap = (gpa_t)-1;
6808         b = -1;
6809
6810         while (size > 0) {
6811                 if (port < 0x8000)
6812                         bitmap = vmcs12->io_bitmap_a;
6813                 else if (port < 0x10000)
6814                         bitmap = vmcs12->io_bitmap_b;
6815                 else
6816                         return 1;
6817                 bitmap += (port & 0x7fff) / 8;
6818
6819                 if (last_bitmap != bitmap)
6820                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6821                                 return 1;
6822                 if (b & (1 << (port & 7)))
6823                         return 1;
6824
6825                 port++;
6826                 size--;
6827                 last_bitmap = bitmap;
6828         }
6829
6830         return 0;
6831 }
6832
6833 /*
6834  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6835  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6836  * disinterest in the current event (read or write a specific MSR) by using an
6837  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6838  */
6839 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6840         struct vmcs12 *vmcs12, u32 exit_reason)
6841 {
6842         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6843         gpa_t bitmap;
6844
6845         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6846                 return 1;
6847
6848         /*
6849          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6850          * for the four combinations of read/write and low/high MSR numbers.
6851          * First we need to figure out which of the four to use:
6852          */
6853         bitmap = vmcs12->msr_bitmap;
6854         if (exit_reason == EXIT_REASON_MSR_WRITE)
6855                 bitmap += 2048;
6856         if (msr_index >= 0xc0000000) {
6857                 msr_index -= 0xc0000000;
6858                 bitmap += 1024;
6859         }
6860
6861         /* Then read the msr_index'th bit from this bitmap: */
6862         if (msr_index < 1024*8) {
6863                 unsigned char b;
6864                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6865                         return 1;
6866                 return 1 & (b >> (msr_index & 7));
6867         } else
6868                 return 1; /* let L1 handle the wrong parameter */
6869 }
6870
6871 /*
6872  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6873  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6874  * intercept (via guest_host_mask etc.) the current event.
6875  */
6876 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6877         struct vmcs12 *vmcs12)
6878 {
6879         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6880         int cr = exit_qualification & 15;
6881         int reg = (exit_qualification >> 8) & 15;
6882         unsigned long val = kvm_register_readl(vcpu, reg);
6883
6884         switch ((exit_qualification >> 4) & 3) {
6885         case 0: /* mov to cr */
6886                 switch (cr) {
6887                 case 0:
6888                         if (vmcs12->cr0_guest_host_mask &
6889                             (val ^ vmcs12->cr0_read_shadow))
6890                                 return 1;
6891                         break;
6892                 case 3:
6893                         if ((vmcs12->cr3_target_count >= 1 &&
6894                                         vmcs12->cr3_target_value0 == val) ||
6895                                 (vmcs12->cr3_target_count >= 2 &&
6896                                         vmcs12->cr3_target_value1 == val) ||
6897                                 (vmcs12->cr3_target_count >= 3 &&
6898                                         vmcs12->cr3_target_value2 == val) ||
6899                                 (vmcs12->cr3_target_count >= 4 &&
6900                                         vmcs12->cr3_target_value3 == val))
6901                                 return 0;
6902                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6903                                 return 1;
6904                         break;
6905                 case 4:
6906                         if (vmcs12->cr4_guest_host_mask &
6907                             (vmcs12->cr4_read_shadow ^ val))
6908                                 return 1;
6909                         break;
6910                 case 8:
6911                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6912                                 return 1;
6913                         break;
6914                 }
6915                 break;
6916         case 2: /* clts */
6917                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6918                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6919                         return 1;
6920                 break;
6921         case 1: /* mov from cr */
6922                 switch (cr) {
6923                 case 3:
6924                         if (vmcs12->cpu_based_vm_exec_control &
6925                             CPU_BASED_CR3_STORE_EXITING)
6926                                 return 1;
6927                         break;
6928                 case 8:
6929                         if (vmcs12->cpu_based_vm_exec_control &
6930                             CPU_BASED_CR8_STORE_EXITING)
6931                                 return 1;
6932                         break;
6933                 }
6934                 break;
6935         case 3: /* lmsw */
6936                 /*
6937                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6938                  * cr0. Other attempted changes are ignored, with no exit.
6939                  */
6940                 if (vmcs12->cr0_guest_host_mask & 0xe &
6941                     (val ^ vmcs12->cr0_read_shadow))
6942                         return 1;
6943                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6944                     !(vmcs12->cr0_read_shadow & 0x1) &&
6945                     (val & 0x1))
6946                         return 1;
6947                 break;
6948         }
6949         return 0;
6950 }
6951
6952 /*
6953  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6954  * should handle it ourselves in L0 (and then continue L2). Only call this
6955  * when in is_guest_mode (L2).
6956  */
6957 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6958 {
6959         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6960         struct vcpu_vmx *vmx = to_vmx(vcpu);
6961         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6962         u32 exit_reason = vmx->exit_reason;
6963
6964         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6965                                 vmcs_readl(EXIT_QUALIFICATION),
6966                                 vmx->idt_vectoring_info,
6967                                 intr_info,
6968                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6969                                 KVM_ISA_VMX);
6970
6971         if (vmx->nested.nested_run_pending)
6972                 return 0;
6973
6974         if (unlikely(vmx->fail)) {
6975                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6976                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6977                 return 1;
6978         }
6979
6980         switch (exit_reason) {
6981         case EXIT_REASON_EXCEPTION_NMI:
6982                 if (!is_exception(intr_info))
6983                         return 0;
6984                 else if (is_page_fault(intr_info))
6985                         return enable_ept;
6986                 else if (is_no_device(intr_info) &&
6987                          !(vmcs12->guest_cr0 & X86_CR0_TS))
6988                         return 0;
6989                 return vmcs12->exception_bitmap &
6990                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6991         case EXIT_REASON_EXTERNAL_INTERRUPT:
6992                 return 0;
6993         case EXIT_REASON_TRIPLE_FAULT:
6994                 return 1;
6995         case EXIT_REASON_PENDING_INTERRUPT:
6996                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6997         case EXIT_REASON_NMI_WINDOW:
6998                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6999         case EXIT_REASON_TASK_SWITCH:
7000                 return 1;
7001         case EXIT_REASON_CPUID:
7002                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7003                         return 0;
7004                 return 1;
7005         case EXIT_REASON_HLT:
7006                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7007         case EXIT_REASON_INVD:
7008                 return 1;
7009         case EXIT_REASON_INVLPG:
7010                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7011         case EXIT_REASON_RDPMC:
7012                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7013         case EXIT_REASON_RDTSC:
7014                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7015         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7016         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7017         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7018         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7019         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7020         case EXIT_REASON_INVEPT:
7021                 /*
7022                  * VMX instructions trap unconditionally. This allows L1 to
7023                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7024                  */
7025                 return 1;
7026         case EXIT_REASON_CR_ACCESS:
7027                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7028         case EXIT_REASON_DR_ACCESS:
7029                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7030         case EXIT_REASON_IO_INSTRUCTION:
7031                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7032         case EXIT_REASON_MSR_READ:
7033         case EXIT_REASON_MSR_WRITE:
7034                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7035         case EXIT_REASON_INVALID_STATE:
7036                 return 1;
7037         case EXIT_REASON_MWAIT_INSTRUCTION:
7038                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7039         case EXIT_REASON_MONITOR_INSTRUCTION:
7040                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7041         case EXIT_REASON_PAUSE_INSTRUCTION:
7042                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7043                         nested_cpu_has2(vmcs12,
7044                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7045         case EXIT_REASON_MCE_DURING_VMENTRY:
7046                 return 0;
7047         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7048                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7049         case EXIT_REASON_APIC_ACCESS:
7050                 return nested_cpu_has2(vmcs12,
7051                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7052         case EXIT_REASON_EPT_VIOLATION:
7053                 /*
7054                  * L0 always deals with the EPT violation. If nested EPT is
7055                  * used, and the nested mmu code discovers that the address is
7056                  * missing in the guest EPT table (EPT12), the EPT violation
7057                  * will be injected with nested_ept_inject_page_fault()
7058                  */
7059                 return 0;
7060         case EXIT_REASON_EPT_MISCONFIG:
7061                 /*
7062                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7063                  * table (shadow on EPT) or a merged EPT table that L0 built
7064                  * (EPT on EPT). So any problems with the structure of the
7065                  * table is L0's fault.
7066                  */
7067                 return 0;
7068         case EXIT_REASON_WBINVD:
7069                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7070         case EXIT_REASON_XSETBV:
7071                 return 1;
7072         default:
7073                 return 1;
7074         }
7075 }
7076
7077 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7078 {
7079         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7080         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7081 }
7082
7083 /*
7084  * The guest has exited.  See if we can fix it or if we need userspace
7085  * assistance.
7086  */
7087 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7088 {
7089         struct vcpu_vmx *vmx = to_vmx(vcpu);
7090         u32 exit_reason = vmx->exit_reason;
7091         u32 vectoring_info = vmx->idt_vectoring_info;
7092
7093         /* If guest state is invalid, start emulating */
7094         if (vmx->emulation_required)
7095                 return handle_invalid_guest_state(vcpu);
7096
7097         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7098                 nested_vmx_vmexit(vcpu, exit_reason,
7099                                   vmcs_read32(VM_EXIT_INTR_INFO),
7100                                   vmcs_readl(EXIT_QUALIFICATION));
7101                 return 1;
7102         }
7103
7104         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7105                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7106                 vcpu->run->fail_entry.hardware_entry_failure_reason
7107                         = exit_reason;
7108                 return 0;
7109         }
7110
7111         if (unlikely(vmx->fail)) {
7112                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7113                 vcpu->run->fail_entry.hardware_entry_failure_reason
7114                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7115                 return 0;
7116         }
7117
7118         /*
7119          * Note:
7120          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7121          * delivery event since it indicates guest is accessing MMIO.
7122          * The vm-exit can be triggered again after return to guest that
7123          * will cause infinite loop.
7124          */
7125         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7126                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7127                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7128                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7129                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7130                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7131                 vcpu->run->internal.ndata = 2;
7132                 vcpu->run->internal.data[0] = vectoring_info;
7133                 vcpu->run->internal.data[1] = exit_reason;
7134                 return 0;
7135         }
7136
7137         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7138             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7139                                         get_vmcs12(vcpu))))) {
7140                 if (vmx_interrupt_allowed(vcpu)) {
7141                         vmx->soft_vnmi_blocked = 0;
7142                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7143                            vcpu->arch.nmi_pending) {
7144                         /*
7145                          * This CPU don't support us in finding the end of an
7146                          * NMI-blocked window if the guest runs with IRQs
7147                          * disabled. So we pull the trigger after 1 s of
7148                          * futile waiting, but inform the user about this.
7149                          */
7150                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7151                                "state on VCPU %d after 1 s timeout\n",
7152                                __func__, vcpu->vcpu_id);
7153                         vmx->soft_vnmi_blocked = 0;
7154                 }
7155         }
7156
7157         if (exit_reason < kvm_vmx_max_exit_handlers
7158             && kvm_vmx_exit_handlers[exit_reason])
7159                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7160         else {
7161                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7162                 vcpu->run->hw.hardware_exit_reason = exit_reason;
7163         }
7164         return 0;
7165 }
7166
7167 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7168 {
7169         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7170
7171         if (is_guest_mode(vcpu) &&
7172                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7173                 return;
7174
7175         if (irr == -1 || tpr < irr) {
7176                 vmcs_write32(TPR_THRESHOLD, 0);
7177                 return;
7178         }
7179
7180         vmcs_write32(TPR_THRESHOLD, irr);
7181 }
7182
7183 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7184 {
7185         u32 sec_exec_control;
7186
7187         /*
7188          * There is not point to enable virtualize x2apic without enable
7189          * apicv
7190          */
7191         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7192                                 !vmx_vm_has_apicv(vcpu->kvm))
7193                 return;
7194
7195         if (!vm_need_tpr_shadow(vcpu->kvm))
7196                 return;
7197
7198         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7199
7200         if (set) {
7201                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7202                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7203         } else {
7204                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7205                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7206         }
7207         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7208
7209         vmx_set_msr_bitmap(vcpu);
7210 }
7211
7212 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7213 {
7214         struct vcpu_vmx *vmx = to_vmx(vcpu);
7215
7216         /*
7217          * Currently we do not handle the nested case where L2 has an
7218          * APIC access page of its own; that page is still pinned.
7219          * Hence, we skip the case where the VCPU is in guest mode _and_
7220          * L1 prepared an APIC access page for L2.
7221          *
7222          * For the case where L1 and L2 share the same APIC access page
7223          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7224          * in the vmcs12), this function will only update either the vmcs01
7225          * or the vmcs02.  If the former, the vmcs02 will be updated by
7226          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
7227          * the next L2->L1 exit.
7228          */
7229         if (!is_guest_mode(vcpu) ||
7230             !nested_cpu_has2(vmx->nested.current_vmcs12,
7231                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7232                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7233 }
7234
7235 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7236 {
7237         u16 status;
7238         u8 old;
7239
7240         if (!vmx_vm_has_apicv(kvm))
7241                 return;
7242
7243         if (isr == -1)
7244                 isr = 0;
7245
7246         status = vmcs_read16(GUEST_INTR_STATUS);
7247         old = status >> 8;
7248         if (isr != old) {
7249                 status &= 0xff;
7250                 status |= isr << 8;
7251                 vmcs_write16(GUEST_INTR_STATUS, status);
7252         }
7253 }
7254
7255 static void vmx_set_rvi(int vector)
7256 {
7257         u16 status;
7258         u8 old;
7259
7260         status = vmcs_read16(GUEST_INTR_STATUS);
7261         old = (u8)status & 0xff;
7262         if ((u8)vector != old) {
7263                 status &= ~0xff;
7264                 status |= (u8)vector;
7265                 vmcs_write16(GUEST_INTR_STATUS, status);
7266         }
7267 }
7268
7269 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7270 {
7271         if (max_irr == -1)
7272                 return;
7273
7274         /*
7275          * If a vmexit is needed, vmx_check_nested_events handles it.
7276          */
7277         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
7278                 return;
7279
7280         if (!is_guest_mode(vcpu)) {
7281                 vmx_set_rvi(max_irr);
7282                 return;
7283         }
7284
7285         /*
7286          * Fall back to pre-APICv interrupt injection since L2
7287          * is run without virtual interrupt delivery.
7288          */
7289         if (!kvm_event_needs_reinjection(vcpu) &&
7290             vmx_interrupt_allowed(vcpu)) {
7291                 kvm_queue_interrupt(vcpu, max_irr, false);
7292                 vmx_inject_irq(vcpu);
7293         }
7294 }
7295
7296 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7297 {
7298         if (!vmx_vm_has_apicv(vcpu->kvm))
7299                 return;
7300
7301         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7302         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7303         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7304         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7305 }
7306
7307 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7308 {
7309         u32 exit_intr_info;
7310
7311         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7312               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7313                 return;
7314
7315         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7316         exit_intr_info = vmx->exit_intr_info;
7317
7318         /* Handle machine checks before interrupts are enabled */
7319         if (is_machine_check(exit_intr_info))
7320                 kvm_machine_check();
7321
7322         /* We need to handle NMIs before interrupts are enabled */
7323         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7324             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7325                 kvm_before_handle_nmi(&vmx->vcpu);
7326                 asm("int $2");
7327                 kvm_after_handle_nmi(&vmx->vcpu);
7328         }
7329 }
7330
7331 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7332 {
7333         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7334
7335         /*
7336          * If external interrupt exists, IF bit is set in rflags/eflags on the
7337          * interrupt stack frame, and interrupt will be enabled on a return
7338          * from interrupt handler.
7339          */
7340         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7341                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7342                 unsigned int vector;
7343                 unsigned long entry;
7344                 gate_desc *desc;
7345                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7346 #ifdef CONFIG_X86_64
7347                 unsigned long tmp;
7348 #endif
7349
7350                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7351                 desc = (gate_desc *)vmx->host_idt_base + vector;
7352                 entry = gate_offset(*desc);
7353                 asm volatile(
7354 #ifdef CONFIG_X86_64
7355                         "mov %%" _ASM_SP ", %[sp]\n\t"
7356                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7357                         "push $%c[ss]\n\t"
7358                         "push %[sp]\n\t"
7359 #endif
7360                         "pushf\n\t"
7361                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7362                         __ASM_SIZE(push) " $%c[cs]\n\t"
7363                         "call *%[entry]\n\t"
7364                         :
7365 #ifdef CONFIG_X86_64
7366                         [sp]"=&r"(tmp)
7367 #endif
7368                         :
7369                         [entry]"r"(entry),
7370                         [ss]"i"(__KERNEL_DS),
7371                         [cs]"i"(__KERNEL_CS)
7372                         );
7373         } else
7374                 local_irq_enable();
7375 }
7376
7377 static bool vmx_mpx_supported(void)
7378 {
7379         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7380                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7381 }
7382
7383 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7384 {
7385         u32 exit_intr_info;
7386         bool unblock_nmi;
7387         u8 vector;
7388         bool idtv_info_valid;
7389
7390         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7391
7392         if (cpu_has_virtual_nmis()) {
7393                 if (vmx->nmi_known_unmasked)
7394                         return;
7395                 /*
7396                  * Can't use vmx->exit_intr_info since we're not sure what
7397                  * the exit reason is.
7398                  */
7399                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7400                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7401                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7402                 /*
7403                  * SDM 3: 27.7.1.2 (September 2008)
7404                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7405                  * a guest IRET fault.
7406                  * SDM 3: 23.2.2 (September 2008)
7407                  * Bit 12 is undefined in any of the following cases:
7408                  *  If the VM exit sets the valid bit in the IDT-vectoring
7409                  *   information field.
7410                  *  If the VM exit is due to a double fault.
7411                  */
7412                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7413                     vector != DF_VECTOR && !idtv_info_valid)
7414                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7415                                       GUEST_INTR_STATE_NMI);
7416                 else
7417                         vmx->nmi_known_unmasked =
7418                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7419                                   & GUEST_INTR_STATE_NMI);
7420         } else if (unlikely(vmx->soft_vnmi_blocked))
7421                 vmx->vnmi_blocked_time +=
7422                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7423 }
7424
7425 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7426                                       u32 idt_vectoring_info,
7427                                       int instr_len_field,
7428                                       int error_code_field)
7429 {
7430         u8 vector;
7431         int type;
7432         bool idtv_info_valid;
7433
7434         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7435
7436         vcpu->arch.nmi_injected = false;
7437         kvm_clear_exception_queue(vcpu);
7438         kvm_clear_interrupt_queue(vcpu);
7439
7440         if (!idtv_info_valid)
7441                 return;
7442
7443         kvm_make_request(KVM_REQ_EVENT, vcpu);
7444
7445         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7446         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7447
7448         switch (type) {
7449         case INTR_TYPE_NMI_INTR:
7450                 vcpu->arch.nmi_injected = true;
7451                 /*
7452                  * SDM 3: 27.7.1.2 (September 2008)
7453                  * Clear bit "block by NMI" before VM entry if a NMI
7454                  * delivery faulted.
7455                  */
7456                 vmx_set_nmi_mask(vcpu, false);
7457                 break;
7458         case INTR_TYPE_SOFT_EXCEPTION:
7459                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7460                 /* fall through */
7461         case INTR_TYPE_HARD_EXCEPTION:
7462                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7463                         u32 err = vmcs_read32(error_code_field);
7464                         kvm_requeue_exception_e(vcpu, vector, err);
7465                 } else
7466                         kvm_requeue_exception(vcpu, vector);
7467                 break;
7468         case INTR_TYPE_SOFT_INTR:
7469                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7470                 /* fall through */
7471         case INTR_TYPE_EXT_INTR:
7472                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7473                 break;
7474         default:
7475                 break;
7476         }
7477 }
7478
7479 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7480 {
7481         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7482                                   VM_EXIT_INSTRUCTION_LEN,
7483                                   IDT_VECTORING_ERROR_CODE);
7484 }
7485
7486 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7487 {
7488         __vmx_complete_interrupts(vcpu,
7489                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7490                                   VM_ENTRY_INSTRUCTION_LEN,
7491                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7492
7493         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7494 }
7495
7496 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7497 {
7498         int i, nr_msrs;
7499         struct perf_guest_switch_msr *msrs;
7500
7501         msrs = perf_guest_get_msrs(&nr_msrs);
7502
7503         if (!msrs)
7504                 return;
7505
7506         for (i = 0; i < nr_msrs; i++)
7507                 if (msrs[i].host == msrs[i].guest)
7508                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7509                 else
7510                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7511                                         msrs[i].host);
7512 }
7513
7514 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7515 {
7516         struct vcpu_vmx *vmx = to_vmx(vcpu);
7517         unsigned long debugctlmsr;
7518
7519         /* Record the guest's net vcpu time for enforced NMI injections. */
7520         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7521                 vmx->entry_time = ktime_get();
7522
7523         /* Don't enter VMX if guest state is invalid, let the exit handler
7524            start emulation until we arrive back to a valid state */
7525         if (vmx->emulation_required)
7526                 return;
7527
7528         if (vmx->ple_window_dirty) {
7529                 vmx->ple_window_dirty = false;
7530                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7531         }
7532
7533         if (vmx->nested.sync_shadow_vmcs) {
7534                 copy_vmcs12_to_shadow(vmx);
7535                 vmx->nested.sync_shadow_vmcs = false;
7536         }
7537
7538         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7539                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7540         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7541                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7542
7543         /* When single-stepping over STI and MOV SS, we must clear the
7544          * corresponding interruptibility bits in the guest state. Otherwise
7545          * vmentry fails as it then expects bit 14 (BS) in pending debug
7546          * exceptions being set, but that's not correct for the guest debugging
7547          * case. */
7548         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7549                 vmx_set_interrupt_shadow(vcpu, 0);
7550
7551         atomic_switch_perf_msrs(vmx);
7552         debugctlmsr = get_debugctlmsr();
7553
7554         vmx->__launched = vmx->loaded_vmcs->launched;
7555         asm(
7556                 /* Store host registers */
7557                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7558                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7559                 "push %%" _ASM_CX " \n\t"
7560                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7561                 "je 1f \n\t"
7562                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7563                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7564                 "1: \n\t"
7565                 /* Reload cr2 if changed */
7566                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7567                 "mov %%cr2, %%" _ASM_DX " \n\t"
7568                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7569                 "je 2f \n\t"
7570                 "mov %%" _ASM_AX", %%cr2 \n\t"
7571                 "2: \n\t"
7572                 /* Check if vmlaunch of vmresume is needed */
7573                 "cmpl $0, %c[launched](%0) \n\t"
7574                 /* Load guest registers.  Don't clobber flags. */
7575                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7576                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7577                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7578                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7579                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7580                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7581 #ifdef CONFIG_X86_64
7582                 "mov %c[r8](%0),  %%r8  \n\t"
7583                 "mov %c[r9](%0),  %%r9  \n\t"
7584                 "mov %c[r10](%0), %%r10 \n\t"
7585                 "mov %c[r11](%0), %%r11 \n\t"
7586                 "mov %c[r12](%0), %%r12 \n\t"
7587                 "mov %c[r13](%0), %%r13 \n\t"
7588                 "mov %c[r14](%0), %%r14 \n\t"
7589                 "mov %c[r15](%0), %%r15 \n\t"
7590 #endif
7591                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7592
7593                 /* Enter guest mode */
7594                 "jne 1f \n\t"
7595                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7596                 "jmp 2f \n\t"
7597                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7598                 "2: "
7599                 /* Save guest registers, load host registers, keep flags */
7600                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7601                 "pop %0 \n\t"
7602                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7603                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7604                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7605                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7606                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7607                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7608                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7609 #ifdef CONFIG_X86_64
7610                 "mov %%r8,  %c[r8](%0) \n\t"
7611                 "mov %%r9,  %c[r9](%0) \n\t"
7612                 "mov %%r10, %c[r10](%0) \n\t"
7613                 "mov %%r11, %c[r11](%0) \n\t"
7614                 "mov %%r12, %c[r12](%0) \n\t"
7615                 "mov %%r13, %c[r13](%0) \n\t"
7616                 "mov %%r14, %c[r14](%0) \n\t"
7617                 "mov %%r15, %c[r15](%0) \n\t"
7618 #endif
7619                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7620                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7621
7622                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7623                 "setbe %c[fail](%0) \n\t"
7624                 ".pushsection .rodata \n\t"
7625                 ".global vmx_return \n\t"
7626                 "vmx_return: " _ASM_PTR " 2b \n\t"
7627                 ".popsection"
7628               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7629                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7630                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7631                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7632                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7633                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7634                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7635                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7636                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7637                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7638                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7639 #ifdef CONFIG_X86_64
7640                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7641                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7642                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7643                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7644                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7645                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7646                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7647                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7648 #endif
7649                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7650                 [wordsize]"i"(sizeof(ulong))
7651               : "cc", "memory"
7652 #ifdef CONFIG_X86_64
7653                 , "rax", "rbx", "rdi", "rsi"
7654                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7655 #else
7656                 , "eax", "ebx", "edi", "esi"
7657 #endif
7658               );
7659
7660         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7661         if (debugctlmsr)
7662                 update_debugctlmsr(debugctlmsr);
7663
7664 #ifndef CONFIG_X86_64
7665         /*
7666          * The sysexit path does not restore ds/es, so we must set them to
7667          * a reasonable value ourselves.
7668          *
7669          * We can't defer this to vmx_load_host_state() since that function
7670          * may be executed in interrupt context, which saves and restore segments
7671          * around it, nullifying its effect.
7672          */
7673         loadsegment(ds, __USER_DS);
7674         loadsegment(es, __USER_DS);
7675 #endif
7676
7677         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7678                                   | (1 << VCPU_EXREG_RFLAGS)
7679                                   | (1 << VCPU_EXREG_PDPTR)
7680                                   | (1 << VCPU_EXREG_SEGMENTS)
7681                                   | (1 << VCPU_EXREG_CR3));
7682         vcpu->arch.regs_dirty = 0;
7683
7684         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7685
7686         vmx->loaded_vmcs->launched = 1;
7687
7688         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7689         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7690
7691         /*
7692          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7693          * we did not inject a still-pending event to L1 now because of
7694          * nested_run_pending, we need to re-enable this bit.
7695          */
7696         if (vmx->nested.nested_run_pending)
7697                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7698
7699         vmx->nested.nested_run_pending = 0;
7700
7701         vmx_complete_atomic_exit(vmx);
7702         vmx_recover_nmi_blocking(vmx);
7703         vmx_complete_interrupts(vmx);
7704 }
7705
7706 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7707 {
7708         struct vcpu_vmx *vmx = to_vmx(vcpu);
7709         int cpu;
7710
7711         if (vmx->loaded_vmcs == &vmx->vmcs01)
7712                 return;
7713
7714         cpu = get_cpu();
7715         vmx->loaded_vmcs = &vmx->vmcs01;
7716         vmx_vcpu_put(vcpu);
7717         vmx_vcpu_load(vcpu, cpu);
7718         vcpu->cpu = cpu;
7719         put_cpu();
7720 }
7721
7722 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7723 {
7724         struct vcpu_vmx *vmx = to_vmx(vcpu);
7725
7726         free_vpid(vmx);
7727         leave_guest_mode(vcpu);
7728         vmx_load_vmcs01(vcpu);
7729         free_nested(vmx);
7730         free_loaded_vmcs(vmx->loaded_vmcs);
7731         kfree(vmx->guest_msrs);
7732         kvm_vcpu_uninit(vcpu);
7733         kmem_cache_free(kvm_vcpu_cache, vmx);
7734 }
7735
7736 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7737 {
7738         int err;
7739         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7740         int cpu;
7741
7742         if (!vmx)
7743                 return ERR_PTR(-ENOMEM);
7744
7745         allocate_vpid(vmx);
7746
7747         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7748         if (err)
7749                 goto free_vcpu;
7750
7751         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7752         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7753                      > PAGE_SIZE);
7754
7755         err = -ENOMEM;
7756         if (!vmx->guest_msrs) {
7757                 goto uninit_vcpu;
7758         }
7759
7760         vmx->loaded_vmcs = &vmx->vmcs01;
7761         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7762         if (!vmx->loaded_vmcs->vmcs)
7763                 goto free_msrs;
7764         if (!vmm_exclusive)
7765                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7766         loaded_vmcs_init(vmx->loaded_vmcs);
7767         if (!vmm_exclusive)
7768                 kvm_cpu_vmxoff();
7769
7770         cpu = get_cpu();
7771         vmx_vcpu_load(&vmx->vcpu, cpu);
7772         vmx->vcpu.cpu = cpu;
7773         err = vmx_vcpu_setup(vmx);
7774         vmx_vcpu_put(&vmx->vcpu);
7775         put_cpu();
7776         if (err)
7777                 goto free_vmcs;
7778         if (vm_need_virtualize_apic_accesses(kvm)) {
7779                 err = alloc_apic_access_page(kvm);
7780                 if (err)
7781                         goto free_vmcs;
7782         }
7783
7784         if (enable_ept) {
7785                 if (!kvm->arch.ept_identity_map_addr)
7786                         kvm->arch.ept_identity_map_addr =
7787                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7788                 err = init_rmode_identity_map(kvm);
7789                 if (err)
7790                         goto free_vmcs;
7791         }
7792
7793         vmx->nested.current_vmptr = -1ull;
7794         vmx->nested.current_vmcs12 = NULL;
7795
7796         return &vmx->vcpu;
7797
7798 free_vmcs:
7799         free_loaded_vmcs(vmx->loaded_vmcs);
7800 free_msrs:
7801         kfree(vmx->guest_msrs);
7802 uninit_vcpu:
7803         kvm_vcpu_uninit(&vmx->vcpu);
7804 free_vcpu:
7805         free_vpid(vmx);
7806         kmem_cache_free(kvm_vcpu_cache, vmx);
7807         return ERR_PTR(err);
7808 }
7809
7810 static void __init vmx_check_processor_compat(void *rtn)
7811 {
7812         struct vmcs_config vmcs_conf;
7813
7814         *(int *)rtn = 0;
7815         if (setup_vmcs_config(&vmcs_conf) < 0)
7816                 *(int *)rtn = -EIO;
7817         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7818                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7819                                 smp_processor_id());
7820                 *(int *)rtn = -EIO;
7821         }
7822 }
7823
7824 static int get_ept_level(void)
7825 {
7826         return VMX_EPT_DEFAULT_GAW + 1;
7827 }
7828
7829 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7830 {
7831         u64 ret;
7832
7833         /* For VT-d and EPT combination
7834          * 1. MMIO: always map as UC
7835          * 2. EPT with VT-d:
7836          *   a. VT-d without snooping control feature: can't guarantee the
7837          *      result, try to trust guest.
7838          *   b. VT-d with snooping control feature: snooping control feature of
7839          *      VT-d engine can guarantee the cache correctness. Just set it
7840          *      to WB to keep consistent with host. So the same as item 3.
7841          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7842          *    consistent with host MTRR
7843          */
7844         if (is_mmio)
7845                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7846         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
7847                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7848                       VMX_EPT_MT_EPTE_SHIFT;
7849         else
7850                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7851                         | VMX_EPT_IPAT_BIT;
7852
7853         return ret;
7854 }
7855
7856 static int vmx_get_lpage_level(void)
7857 {
7858         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7859                 return PT_DIRECTORY_LEVEL;
7860         else
7861                 /* For shadow and EPT supported 1GB page */
7862                 return PT_PDPE_LEVEL;
7863 }
7864
7865 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7866 {
7867         struct kvm_cpuid_entry2 *best;
7868         struct vcpu_vmx *vmx = to_vmx(vcpu);
7869         u32 exec_control;
7870
7871         vmx->rdtscp_enabled = false;
7872         if (vmx_rdtscp_supported()) {
7873                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7874                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7875                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7876                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7877                                 vmx->rdtscp_enabled = true;
7878                         else {
7879                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7880                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7881                                                 exec_control);
7882                         }
7883                 }
7884         }
7885
7886         /* Exposing INVPCID only when PCID is exposed */
7887         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7888         if (vmx_invpcid_supported() &&
7889             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7890             guest_cpuid_has_pcid(vcpu)) {
7891                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7892                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7893                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7894                              exec_control);
7895         } else {
7896                 if (cpu_has_secondary_exec_ctrls()) {
7897                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7898                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7899                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7900                                      exec_control);
7901                 }
7902                 if (best)
7903                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7904         }
7905 }
7906
7907 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7908 {
7909         if (func == 1 && nested)
7910                 entry->ecx |= bit(X86_FEATURE_VMX);
7911 }
7912
7913 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7914                 struct x86_exception *fault)
7915 {
7916         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7917         u32 exit_reason;
7918
7919         if (fault->error_code & PFERR_RSVD_MASK)
7920                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
7921         else
7922                 exit_reason = EXIT_REASON_EPT_VIOLATION;
7923         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
7924         vmcs12->guest_physical_address = fault->address;
7925 }
7926
7927 /* Callbacks for nested_ept_init_mmu_context: */
7928
7929 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7930 {
7931         /* return the page table to be shadowed - in our case, EPT12 */
7932         return get_vmcs12(vcpu)->ept_pointer;
7933 }
7934
7935 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7936 {
7937         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7938                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7939
7940         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7941         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7942         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7943
7944         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7945 }
7946
7947 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7948 {
7949         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7950 }
7951
7952 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7953                 struct x86_exception *fault)
7954 {
7955         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7956
7957         WARN_ON(!is_guest_mode(vcpu));
7958
7959         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7960         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7961                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7962                                   vmcs_read32(VM_EXIT_INTR_INFO),
7963                                   vmcs_readl(EXIT_QUALIFICATION));
7964         else
7965                 kvm_inject_page_fault(vcpu, fault);
7966 }
7967
7968 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
7969                                         struct vmcs12 *vmcs12)
7970 {
7971         struct vcpu_vmx *vmx = to_vmx(vcpu);
7972
7973         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
7974                 /* TODO: Also verify bits beyond physical address width are 0 */
7975                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
7976                         return false;
7977
7978                 /*
7979                  * Translate L1 physical address to host physical
7980                  * address for vmcs02. Keep the page pinned, so this
7981                  * physical address remains valid. We keep a reference
7982                  * to it so we can release it later.
7983                  */
7984                 if (vmx->nested.apic_access_page) /* shouldn't happen */
7985                         nested_release_page(vmx->nested.apic_access_page);
7986                 vmx->nested.apic_access_page =
7987                         nested_get_page(vcpu, vmcs12->apic_access_addr);
7988         }
7989
7990         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
7991                 /* TODO: Also verify bits beyond physical address width are 0 */
7992                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
7993                         return false;
7994
7995                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
7996                         nested_release_page(vmx->nested.virtual_apic_page);
7997                 vmx->nested.virtual_apic_page =
7998                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
7999
8000                 /*
8001                  * Failing the vm entry is _not_ what the processor does
8002                  * but it's basically the only possibility we have.
8003                  * We could still enter the guest if CR8 load exits are
8004                  * enabled, CR8 store exits are enabled, and virtualize APIC
8005                  * access is disabled; in this case the processor would never
8006                  * use the TPR shadow and we could simply clear the bit from
8007                  * the execution control.  But such a configuration is useless,
8008                  * so let's keep the code simple.
8009                  */
8010                 if (!vmx->nested.virtual_apic_page)
8011                         return false;
8012         }
8013
8014         return true;
8015 }
8016
8017 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8018 {
8019         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8020         struct vcpu_vmx *vmx = to_vmx(vcpu);
8021
8022         if (vcpu->arch.virtual_tsc_khz == 0)
8023                 return;
8024
8025         /* Make sure short timeouts reliably trigger an immediate vmexit.
8026          * hrtimer_start does not guarantee this. */
8027         if (preemption_timeout <= 1) {
8028                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8029                 return;
8030         }
8031
8032         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8033         preemption_timeout *= 1000000;
8034         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8035         hrtimer_start(&vmx->nested.preemption_timer,
8036                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8037 }
8038
8039 /*
8040  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8041  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
8042  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
8043  * guest in a way that will both be appropriate to L1's requests, and our
8044  * needs. In addition to modifying the active vmcs (which is vmcs02), this
8045  * function also has additional necessary side-effects, like setting various
8046  * vcpu->arch fields.
8047  */
8048 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8049 {
8050         struct vcpu_vmx *vmx = to_vmx(vcpu);
8051         u32 exec_control;
8052
8053         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8054         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8055         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8056         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8057         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8058         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8059         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8060         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8061         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8062         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8063         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8064         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8065         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8066         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8067         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8068         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8069         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8070         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8071         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8072         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8073         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8074         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8075         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8076         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8077         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8078         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8079         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8080         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8081         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8082         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8083         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8084         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8085         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8086         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8087         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8088         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8089
8090         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8091                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8092                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8093         } else {
8094                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8095                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8096         }
8097         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8098                 vmcs12->vm_entry_intr_info_field);
8099         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8100                 vmcs12->vm_entry_exception_error_code);
8101         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8102                 vmcs12->vm_entry_instruction_len);
8103         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8104                 vmcs12->guest_interruptibility_info);
8105         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
8106         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
8107         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8108                 vmcs12->guest_pending_dbg_exceptions);
8109         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8110         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8111
8112         vmcs_write64(VMCS_LINK_POINTER, -1ull);
8113
8114         exec_control = vmcs12->pin_based_vm_exec_control;
8115         exec_control |= vmcs_config.pin_based_exec_ctrl;
8116         exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8117                           PIN_BASED_POSTED_INTR);
8118         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
8119
8120         vmx->nested.preemption_timer_expired = false;
8121         if (nested_cpu_has_preemption_timer(vmcs12))
8122                 vmx_start_preemption_timer(vcpu);
8123
8124         /*
8125          * Whether page-faults are trapped is determined by a combination of
8126          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8127          * If enable_ept, L0 doesn't care about page faults and we should
8128          * set all of these to L1's desires. However, if !enable_ept, L0 does
8129          * care about (at least some) page faults, and because it is not easy
8130          * (if at all possible?) to merge L0 and L1's desires, we simply ask
8131          * to exit on each and every L2 page fault. This is done by setting
8132          * MASK=MATCH=0 and (see below) EB.PF=1.
8133          * Note that below we don't need special code to set EB.PF beyond the
8134          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8135          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8136          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8137          *
8138          * A problem with this approach (when !enable_ept) is that L1 may be
8139          * injected with more page faults than it asked for. This could have
8140          * caused problems, but in practice existing hypervisors don't care.
8141          * To fix this, we will need to emulate the PFEC checking (on the L1
8142          * page tables), using walk_addr(), when injecting PFs to L1.
8143          */
8144         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8145                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8146         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8147                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8148
8149         if (cpu_has_secondary_exec_ctrls()) {
8150                 exec_control = vmx_secondary_exec_control(vmx);
8151                 if (!vmx->rdtscp_enabled)
8152                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
8153                 /* Take the following fields only from vmcs12 */
8154                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8155                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8156                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
8157                 if (nested_cpu_has(vmcs12,
8158                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8159                         exec_control |= vmcs12->secondary_vm_exec_control;
8160
8161                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
8162                         /*
8163                          * If translation failed, no matter: This feature asks
8164                          * to exit when accessing the given address, and if it
8165                          * can never be accessed, this feature won't do
8166                          * anything anyway.
8167                          */
8168                         if (!vmx->nested.apic_access_page)
8169                                 exec_control &=
8170                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8171                         else
8172                                 vmcs_write64(APIC_ACCESS_ADDR,
8173                                   page_to_phys(vmx->nested.apic_access_page));
8174                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8175                         exec_control |=
8176                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8177                         kvm_vcpu_reload_apic_access_page(vcpu);
8178                 }
8179
8180                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8181         }
8182
8183
8184         /*
8185          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8186          * Some constant fields are set here by vmx_set_constant_host_state().
8187          * Other fields are different per CPU, and will be set later when
8188          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8189          */
8190         vmx_set_constant_host_state(vmx);
8191
8192         /*
8193          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8194          * entry, but only if the current (host) sp changed from the value
8195          * we wrote last (vmx->host_rsp). This cache is no longer relevant
8196          * if we switch vmcs, and rather than hold a separate cache per vmcs,
8197          * here we just force the write to happen on entry.
8198          */
8199         vmx->host_rsp = 0;
8200
8201         exec_control = vmx_exec_control(vmx); /* L0's desires */
8202         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8203         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8204         exec_control &= ~CPU_BASED_TPR_SHADOW;
8205         exec_control |= vmcs12->cpu_based_vm_exec_control;
8206
8207         if (exec_control & CPU_BASED_TPR_SHADOW) {
8208                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8209                                 page_to_phys(vmx->nested.virtual_apic_page));
8210                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8211         }
8212
8213         /*
8214          * Merging of IO and MSR bitmaps not currently supported.
8215          * Rather, exit every time.
8216          */
8217         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8218         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8219         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8220
8221         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8222
8223         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8224          * bitwise-or of what L1 wants to trap for L2, and what we want to
8225          * trap. Note that CR0.TS also needs updating - we do this later.
8226          */
8227         update_exception_bitmap(vcpu);
8228         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8229         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8230
8231         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8232          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8233          * bits are further modified by vmx_set_efer() below.
8234          */
8235         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8236
8237         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8238          * emulated by vmx_set_efer(), below.
8239          */
8240         vm_entry_controls_init(vmx,
8241                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8242                         ~VM_ENTRY_IA32E_MODE) |
8243                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8244
8245         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
8246                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
8247                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8248         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
8249                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8250
8251
8252         set_cr4_guest_host_mask(vmx);
8253
8254         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8255                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8256
8257         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8258                 vmcs_write64(TSC_OFFSET,
8259                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8260         else
8261                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8262
8263         if (enable_vpid) {
8264                 /*
8265                  * Trivially support vpid by letting L2s share their parent
8266                  * L1's vpid. TODO: move to a more elaborate solution, giving
8267                  * each L2 its own vpid and exposing the vpid feature to L1.
8268                  */
8269                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8270                 vmx_flush_tlb(vcpu);
8271         }
8272
8273         if (nested_cpu_has_ept(vmcs12)) {
8274                 kvm_mmu_unload(vcpu);
8275                 nested_ept_init_mmu_context(vcpu);
8276         }
8277
8278         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8279                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
8280         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
8281                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8282         else
8283                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8284         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8285         vmx_set_efer(vcpu, vcpu->arch.efer);
8286
8287         /*
8288          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8289          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8290          * The CR0_READ_SHADOW is what L2 should have expected to read given
8291          * the specifications by L1; It's not enough to take
8292          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8293          * have more bits than L1 expected.
8294          */
8295         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8296         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8297
8298         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8299         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8300
8301         /* shadow page tables on either EPT or shadow page tables */
8302         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8303         kvm_mmu_reset_context(vcpu);
8304
8305         if (!enable_ept)
8306                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8307
8308         /*
8309          * L1 may access the L2's PDPTR, so save them to construct vmcs12
8310          */
8311         if (enable_ept) {
8312                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8313                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8314                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8315                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8316         }
8317
8318         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8319         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8320 }
8321
8322 /*
8323  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8324  * for running an L2 nested guest.
8325  */
8326 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8327 {
8328         struct vmcs12 *vmcs12;
8329         struct vcpu_vmx *vmx = to_vmx(vcpu);
8330         int cpu;
8331         struct loaded_vmcs *vmcs02;
8332         bool ia32e;
8333
8334         if (!nested_vmx_check_permission(vcpu) ||
8335             !nested_vmx_check_vmcs12(vcpu))
8336                 return 1;
8337
8338         skip_emulated_instruction(vcpu);
8339         vmcs12 = get_vmcs12(vcpu);
8340
8341         if (enable_shadow_vmcs)
8342                 copy_shadow_to_vmcs12(vmx);
8343
8344         /*
8345          * The nested entry process starts with enforcing various prerequisites
8346          * on vmcs12 as required by the Intel SDM, and act appropriately when
8347          * they fail: As the SDM explains, some conditions should cause the
8348          * instruction to fail, while others will cause the instruction to seem
8349          * to succeed, but return an EXIT_REASON_INVALID_STATE.
8350          * To speed up the normal (success) code path, we should avoid checking
8351          * for misconfigurations which will anyway be caught by the processor
8352          * when using the merged vmcs02.
8353          */
8354         if (vmcs12->launch_state == launch) {
8355                 nested_vmx_failValid(vcpu,
8356                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8357                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8358                 return 1;
8359         }
8360
8361         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8362             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
8363                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8364                 return 1;
8365         }
8366
8367         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8368                         !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
8369                 /*TODO: Also verify bits beyond physical address width are 0*/
8370                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8371                 return 1;
8372         }
8373
8374         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
8375                 /*TODO: Also verify bits beyond physical address width are 0*/
8376                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8377                 return 1;
8378         }
8379
8380         if (vmcs12->vm_entry_msr_load_count > 0 ||
8381             vmcs12->vm_exit_msr_load_count > 0 ||
8382             vmcs12->vm_exit_msr_store_count > 0) {
8383                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8384                                     __func__);
8385                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8386                 return 1;
8387         }
8388
8389         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8390                                 nested_vmx_true_procbased_ctls_low,
8391                                 nested_vmx_procbased_ctls_high) ||
8392             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8393               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8394             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8395               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8396             !vmx_control_verify(vmcs12->vm_exit_controls,
8397                                 nested_vmx_true_exit_ctls_low,
8398                                 nested_vmx_exit_ctls_high) ||
8399             !vmx_control_verify(vmcs12->vm_entry_controls,
8400                                 nested_vmx_true_entry_ctls_low,
8401                                 nested_vmx_entry_ctls_high))
8402         {
8403                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8404                 return 1;
8405         }
8406
8407         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8408             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8409                 nested_vmx_failValid(vcpu,
8410                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8411                 return 1;
8412         }
8413
8414         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8415             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8416                 nested_vmx_entry_failure(vcpu, vmcs12,
8417                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8418                 return 1;
8419         }
8420         if (vmcs12->vmcs_link_pointer != -1ull) {
8421                 nested_vmx_entry_failure(vcpu, vmcs12,
8422                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8423                 return 1;
8424         }
8425
8426         /*
8427          * If the load IA32_EFER VM-entry control is 1, the following checks
8428          * are performed on the field for the IA32_EFER MSR:
8429          * - Bits reserved in the IA32_EFER MSR must be 0.
8430          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8431          *   the IA-32e mode guest VM-exit control. It must also be identical
8432          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8433          *   CR0.PG) is 1.
8434          */
8435         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8436                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8437                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8438                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8439                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8440                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8441                         nested_vmx_entry_failure(vcpu, vmcs12,
8442                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8443                         return 1;
8444                 }
8445         }
8446
8447         /*
8448          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8449          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8450          * the values of the LMA and LME bits in the field must each be that of
8451          * the host address-space size VM-exit control.
8452          */
8453         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8454                 ia32e = (vmcs12->vm_exit_controls &
8455                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8456                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8457                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8458                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8459                         nested_vmx_entry_failure(vcpu, vmcs12,
8460                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8461                         return 1;
8462                 }
8463         }
8464
8465         /*
8466          * We're finally done with prerequisite checking, and can start with
8467          * the nested entry.
8468          */
8469
8470         vmcs02 = nested_get_current_vmcs02(vmx);
8471         if (!vmcs02)
8472                 return -ENOMEM;
8473
8474         enter_guest_mode(vcpu);
8475
8476         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8477
8478         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8479                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8480
8481         cpu = get_cpu();
8482         vmx->loaded_vmcs = vmcs02;
8483         vmx_vcpu_put(vcpu);
8484         vmx_vcpu_load(vcpu, cpu);
8485         vcpu->cpu = cpu;
8486         put_cpu();
8487
8488         vmx_segment_cache_clear(vmx);
8489
8490         vmcs12->launch_state = 1;
8491
8492         prepare_vmcs02(vcpu, vmcs12);
8493
8494         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8495                 return kvm_emulate_halt(vcpu);
8496
8497         vmx->nested.nested_run_pending = 1;
8498
8499         /*
8500          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8501          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8502          * returned as far as L1 is concerned. It will only return (and set
8503          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8504          */
8505         return 1;
8506 }
8507
8508 /*
8509  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8510  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8511  * This function returns the new value we should put in vmcs12.guest_cr0.
8512  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8513  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8514  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8515  *     didn't trap the bit, because if L1 did, so would L0).
8516  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8517  *     been modified by L2, and L1 knows it. So just leave the old value of
8518  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8519  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8520  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8521  *     changed these bits, and therefore they need to be updated, but L0
8522  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8523  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8524  */
8525 static inline unsigned long
8526 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8527 {
8528         return
8529         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8530         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8531         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8532                         vcpu->arch.cr0_guest_owned_bits));
8533 }
8534
8535 static inline unsigned long
8536 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8537 {
8538         return
8539         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8540         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8541         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8542                         vcpu->arch.cr4_guest_owned_bits));
8543 }
8544
8545 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8546                                        struct vmcs12 *vmcs12)
8547 {
8548         u32 idt_vectoring;
8549         unsigned int nr;
8550
8551         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8552                 nr = vcpu->arch.exception.nr;
8553                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8554
8555                 if (kvm_exception_is_soft(nr)) {
8556                         vmcs12->vm_exit_instruction_len =
8557                                 vcpu->arch.event_exit_inst_len;
8558                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8559                 } else
8560                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8561
8562                 if (vcpu->arch.exception.has_error_code) {
8563                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8564                         vmcs12->idt_vectoring_error_code =
8565                                 vcpu->arch.exception.error_code;
8566                 }
8567
8568                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8569         } else if (vcpu->arch.nmi_injected) {
8570                 vmcs12->idt_vectoring_info_field =
8571                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8572         } else if (vcpu->arch.interrupt.pending) {
8573                 nr = vcpu->arch.interrupt.nr;
8574                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8575
8576                 if (vcpu->arch.interrupt.soft) {
8577                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8578                         vmcs12->vm_entry_instruction_len =
8579                                 vcpu->arch.event_exit_inst_len;
8580                 } else
8581                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8582
8583                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8584         }
8585 }
8586
8587 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8588 {
8589         struct vcpu_vmx *vmx = to_vmx(vcpu);
8590
8591         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8592             vmx->nested.preemption_timer_expired) {
8593                 if (vmx->nested.nested_run_pending)
8594                         return -EBUSY;
8595                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8596                 return 0;
8597         }
8598
8599         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8600                 if (vmx->nested.nested_run_pending ||
8601                     vcpu->arch.interrupt.pending)
8602                         return -EBUSY;
8603                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8604                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8605                                   INTR_INFO_VALID_MASK, 0);
8606                 /*
8607                  * The NMI-triggered VM exit counts as injection:
8608                  * clear this one and block further NMIs.
8609                  */
8610                 vcpu->arch.nmi_pending = 0;
8611                 vmx_set_nmi_mask(vcpu, true);
8612                 return 0;
8613         }
8614
8615         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8616             nested_exit_on_intr(vcpu)) {
8617                 if (vmx->nested.nested_run_pending)
8618                         return -EBUSY;
8619                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8620         }
8621
8622         return 0;
8623 }
8624
8625 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8626 {
8627         ktime_t remaining =
8628                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8629         u64 value;
8630
8631         if (ktime_to_ns(remaining) <= 0)
8632                 return 0;
8633
8634         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8635         do_div(value, 1000000);
8636         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8637 }
8638
8639 /*
8640  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8641  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8642  * and this function updates it to reflect the changes to the guest state while
8643  * L2 was running (and perhaps made some exits which were handled directly by L0
8644  * without going back to L1), and to reflect the exit reason.
8645  * Note that we do not have to copy here all VMCS fields, just those that
8646  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8647  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8648  * which already writes to vmcs12 directly.
8649  */
8650 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8651                            u32 exit_reason, u32 exit_intr_info,
8652                            unsigned long exit_qualification)
8653 {
8654         /* update guest state fields: */
8655         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8656         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8657
8658         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8659         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8660         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8661
8662         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8663         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8664         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8665         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8666         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8667         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8668         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8669         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8670         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8671         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8672         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8673         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8674         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8675         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8676         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8677         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8678         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8679         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8680         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8681         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8682         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8683         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8684         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8685         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8686         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8687         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8688         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8689         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8690         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8691         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8692         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8693         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8694         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8695         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8696         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8697         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8698
8699         vmcs12->guest_interruptibility_info =
8700                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8701         vmcs12->guest_pending_dbg_exceptions =
8702                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8703         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8704                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8705         else
8706                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8707
8708         if (nested_cpu_has_preemption_timer(vmcs12)) {
8709                 if (vmcs12->vm_exit_controls &
8710                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8711                         vmcs12->vmx_preemption_timer_value =
8712                                 vmx_get_preemption_timer_value(vcpu);
8713                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8714         }
8715
8716         /*
8717          * In some cases (usually, nested EPT), L2 is allowed to change its
8718          * own CR3 without exiting. If it has changed it, we must keep it.
8719          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8720          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8721          *
8722          * Additionally, restore L2's PDPTR to vmcs12.
8723          */
8724         if (enable_ept) {
8725                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8726                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8727                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8728                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8729                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8730         }
8731
8732         vmcs12->vm_entry_controls =
8733                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8734                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8735
8736         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8737                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8738                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8739         }
8740
8741         /* TODO: These cannot have changed unless we have MSR bitmaps and
8742          * the relevant bit asks not to trap the change */
8743         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8744                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8745         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8746                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8747         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8748         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8749         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8750         if (vmx_mpx_supported())
8751                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8752
8753         /* update exit information fields: */
8754
8755         vmcs12->vm_exit_reason = exit_reason;
8756         vmcs12->exit_qualification = exit_qualification;
8757
8758         vmcs12->vm_exit_intr_info = exit_intr_info;
8759         if ((vmcs12->vm_exit_intr_info &
8760              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8761             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8762                 vmcs12->vm_exit_intr_error_code =
8763                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8764         vmcs12->idt_vectoring_info_field = 0;
8765         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8766         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8767
8768         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8769                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8770                  * instead of reading the real value. */
8771                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8772
8773                 /*
8774                  * Transfer the event that L0 or L1 may wanted to inject into
8775                  * L2 to IDT_VECTORING_INFO_FIELD.
8776                  */
8777                 vmcs12_save_pending_event(vcpu, vmcs12);
8778         }
8779
8780         /*
8781          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8782          * preserved above and would only end up incorrectly in L1.
8783          */
8784         vcpu->arch.nmi_injected = false;
8785         kvm_clear_exception_queue(vcpu);
8786         kvm_clear_interrupt_queue(vcpu);
8787 }
8788
8789 /*
8790  * A part of what we need to when the nested L2 guest exits and we want to
8791  * run its L1 parent, is to reset L1's guest state to the host state specified
8792  * in vmcs12.
8793  * This function is to be called not only on normal nested exit, but also on
8794  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8795  * Failures During or After Loading Guest State").
8796  * This function should be called when the active VMCS is L1's (vmcs01).
8797  */
8798 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8799                                    struct vmcs12 *vmcs12)
8800 {
8801         struct kvm_segment seg;
8802
8803         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8804                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8805         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8806                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8807         else
8808                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8809         vmx_set_efer(vcpu, vcpu->arch.efer);
8810
8811         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8812         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8813         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8814         /*
8815          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8816          * actually changed, because it depends on the current state of
8817          * fpu_active (which may have changed).
8818          * Note that vmx_set_cr0 refers to efer set above.
8819          */
8820         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8821         /*
8822          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8823          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8824          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8825          */
8826         update_exception_bitmap(vcpu);
8827         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8828         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8829
8830         /*
8831          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8832          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8833          */
8834         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8835         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8836
8837         nested_ept_uninit_mmu_context(vcpu);
8838
8839         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8840         kvm_mmu_reset_context(vcpu);
8841
8842         if (!enable_ept)
8843                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8844
8845         if (enable_vpid) {
8846                 /*
8847                  * Trivially support vpid by letting L2s share their parent
8848                  * L1's vpid. TODO: move to a more elaborate solution, giving
8849                  * each L2 its own vpid and exposing the vpid feature to L1.
8850                  */
8851                 vmx_flush_tlb(vcpu);
8852         }
8853
8854
8855         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8856         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8857         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8858         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8859         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8860
8861         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
8862         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8863                 vmcs_write64(GUEST_BNDCFGS, 0);
8864
8865         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8866                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8867                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8868         }
8869         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8870                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8871                         vmcs12->host_ia32_perf_global_ctrl);
8872
8873         /* Set L1 segment info according to Intel SDM
8874             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8875         seg = (struct kvm_segment) {
8876                 .base = 0,
8877                 .limit = 0xFFFFFFFF,
8878                 .selector = vmcs12->host_cs_selector,
8879                 .type = 11,
8880                 .present = 1,
8881                 .s = 1,
8882                 .g = 1
8883         };
8884         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8885                 seg.l = 1;
8886         else
8887                 seg.db = 1;
8888         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8889         seg = (struct kvm_segment) {
8890                 .base = 0,
8891                 .limit = 0xFFFFFFFF,
8892                 .type = 3,
8893                 .present = 1,
8894                 .s = 1,
8895                 .db = 1,
8896                 .g = 1
8897         };
8898         seg.selector = vmcs12->host_ds_selector;
8899         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8900         seg.selector = vmcs12->host_es_selector;
8901         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8902         seg.selector = vmcs12->host_ss_selector;
8903         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8904         seg.selector = vmcs12->host_fs_selector;
8905         seg.base = vmcs12->host_fs_base;
8906         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8907         seg.selector = vmcs12->host_gs_selector;
8908         seg.base = vmcs12->host_gs_base;
8909         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8910         seg = (struct kvm_segment) {
8911                 .base = vmcs12->host_tr_base,
8912                 .limit = 0x67,
8913                 .selector = vmcs12->host_tr_selector,
8914                 .type = 11,
8915                 .present = 1
8916         };
8917         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8918
8919         kvm_set_dr(vcpu, 7, 0x400);
8920         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8921 }
8922
8923 /*
8924  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8925  * and modify vmcs12 to make it see what it would expect to see there if
8926  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8927  */
8928 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8929                               u32 exit_intr_info,
8930                               unsigned long exit_qualification)
8931 {
8932         struct vcpu_vmx *vmx = to_vmx(vcpu);
8933         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8934
8935         /* trying to cancel vmlaunch/vmresume is a bug */
8936         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8937
8938         leave_guest_mode(vcpu);
8939         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8940                        exit_qualification);
8941
8942         vmx_load_vmcs01(vcpu);
8943
8944         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8945             && nested_exit_intr_ack_set(vcpu)) {
8946                 int irq = kvm_cpu_get_interrupt(vcpu);
8947                 WARN_ON(irq < 0);
8948                 vmcs12->vm_exit_intr_info = irq |
8949                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8950         }
8951
8952         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8953                                        vmcs12->exit_qualification,
8954                                        vmcs12->idt_vectoring_info_field,
8955                                        vmcs12->vm_exit_intr_info,
8956                                        vmcs12->vm_exit_intr_error_code,
8957                                        KVM_ISA_VMX);
8958
8959         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8960         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
8961         vmx_segment_cache_clear(vmx);
8962
8963         /* if no vmcs02 cache requested, remove the one we used */
8964         if (VMCS02_POOL_SIZE == 0)
8965                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8966
8967         load_vmcs12_host_state(vcpu, vmcs12);
8968
8969         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8970         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8971
8972         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8973         vmx->host_rsp = 0;
8974
8975         /* Unpin physical memory we referred to in vmcs02 */
8976         if (vmx->nested.apic_access_page) {
8977                 nested_release_page(vmx->nested.apic_access_page);
8978                 vmx->nested.apic_access_page = NULL;
8979         }
8980         if (vmx->nested.virtual_apic_page) {
8981                 nested_release_page(vmx->nested.virtual_apic_page);
8982                 vmx->nested.virtual_apic_page = NULL;
8983         }
8984
8985         /*
8986          * We are now running in L2, mmu_notifier will force to reload the
8987          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
8988          */
8989         kvm_vcpu_reload_apic_access_page(vcpu);
8990
8991         /*
8992          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8993          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8994          * success or failure flag accordingly.
8995          */
8996         if (unlikely(vmx->fail)) {
8997                 vmx->fail = 0;
8998                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8999         } else
9000                 nested_vmx_succeed(vcpu);
9001         if (enable_shadow_vmcs)
9002                 vmx->nested.sync_shadow_vmcs = true;
9003
9004         /* in case we halted in L2 */
9005         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9006 }
9007
9008 /*
9009  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9010  */
9011 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9012 {
9013         if (is_guest_mode(vcpu))
9014                 nested_vmx_vmexit(vcpu, -1, 0, 0);
9015         free_nested(to_vmx(vcpu));
9016 }
9017
9018 /*
9019  * L1's failure to enter L2 is a subset of a normal exit, as explained in
9020  * 23.7 "VM-entry failures during or after loading guest state" (this also
9021  * lists the acceptable exit-reason and exit-qualification parameters).
9022  * It should only be called before L2 actually succeeded to run, and when
9023  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9024  */
9025 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9026                         struct vmcs12 *vmcs12,
9027                         u32 reason, unsigned long qualification)
9028 {
9029         load_vmcs12_host_state(vcpu, vmcs12);
9030         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9031         vmcs12->exit_qualification = qualification;
9032         nested_vmx_succeed(vcpu);
9033         if (enable_shadow_vmcs)
9034                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
9035 }
9036
9037 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9038                                struct x86_instruction_info *info,
9039                                enum x86_intercept_stage stage)
9040 {
9041         return X86EMUL_CONTINUE;
9042 }
9043
9044 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
9045 {
9046         if (ple_gap)
9047                 shrink_ple_window(vcpu);
9048 }
9049
9050 static struct kvm_x86_ops vmx_x86_ops = {
9051         .cpu_has_kvm_support = cpu_has_kvm_support,
9052         .disabled_by_bios = vmx_disabled_by_bios,
9053         .hardware_setup = hardware_setup,
9054         .hardware_unsetup = hardware_unsetup,
9055         .check_processor_compatibility = vmx_check_processor_compat,
9056         .hardware_enable = hardware_enable,
9057         .hardware_disable = hardware_disable,
9058         .cpu_has_accelerated_tpr = report_flexpriority,
9059
9060         .vcpu_create = vmx_create_vcpu,
9061         .vcpu_free = vmx_free_vcpu,
9062         .vcpu_reset = vmx_vcpu_reset,
9063
9064         .prepare_guest_switch = vmx_save_host_state,
9065         .vcpu_load = vmx_vcpu_load,
9066         .vcpu_put = vmx_vcpu_put,
9067
9068         .update_db_bp_intercept = update_exception_bitmap,
9069         .get_msr = vmx_get_msr,
9070         .set_msr = vmx_set_msr,
9071         .get_segment_base = vmx_get_segment_base,
9072         .get_segment = vmx_get_segment,
9073         .set_segment = vmx_set_segment,
9074         .get_cpl = vmx_get_cpl,
9075         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
9076         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
9077         .decache_cr3 = vmx_decache_cr3,
9078         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
9079         .set_cr0 = vmx_set_cr0,
9080         .set_cr3 = vmx_set_cr3,
9081         .set_cr4 = vmx_set_cr4,
9082         .set_efer = vmx_set_efer,
9083         .get_idt = vmx_get_idt,
9084         .set_idt = vmx_set_idt,
9085         .get_gdt = vmx_get_gdt,
9086         .set_gdt = vmx_set_gdt,
9087         .get_dr6 = vmx_get_dr6,
9088         .set_dr6 = vmx_set_dr6,
9089         .set_dr7 = vmx_set_dr7,
9090         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
9091         .cache_reg = vmx_cache_reg,
9092         .get_rflags = vmx_get_rflags,
9093         .set_rflags = vmx_set_rflags,
9094         .fpu_deactivate = vmx_fpu_deactivate,
9095
9096         .tlb_flush = vmx_flush_tlb,
9097
9098         .run = vmx_vcpu_run,
9099         .handle_exit = vmx_handle_exit,
9100         .skip_emulated_instruction = skip_emulated_instruction,
9101         .set_interrupt_shadow = vmx_set_interrupt_shadow,
9102         .get_interrupt_shadow = vmx_get_interrupt_shadow,
9103         .patch_hypercall = vmx_patch_hypercall,
9104         .set_irq = vmx_inject_irq,
9105         .set_nmi = vmx_inject_nmi,
9106         .queue_exception = vmx_queue_exception,
9107         .cancel_injection = vmx_cancel_injection,
9108         .interrupt_allowed = vmx_interrupt_allowed,
9109         .nmi_allowed = vmx_nmi_allowed,
9110         .get_nmi_mask = vmx_get_nmi_mask,
9111         .set_nmi_mask = vmx_set_nmi_mask,
9112         .enable_nmi_window = enable_nmi_window,
9113         .enable_irq_window = enable_irq_window,
9114         .update_cr8_intercept = update_cr8_intercept,
9115         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
9116         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
9117         .vm_has_apicv = vmx_vm_has_apicv,
9118         .load_eoi_exitmap = vmx_load_eoi_exitmap,
9119         .hwapic_irr_update = vmx_hwapic_irr_update,
9120         .hwapic_isr_update = vmx_hwapic_isr_update,
9121         .sync_pir_to_irr = vmx_sync_pir_to_irr,
9122         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
9123
9124         .set_tss_addr = vmx_set_tss_addr,
9125         .get_tdp_level = get_ept_level,
9126         .get_mt_mask = vmx_get_mt_mask,
9127
9128         .get_exit_info = vmx_get_exit_info,
9129
9130         .get_lpage_level = vmx_get_lpage_level,
9131
9132         .cpuid_update = vmx_cpuid_update,
9133
9134         .rdtscp_supported = vmx_rdtscp_supported,
9135         .invpcid_supported = vmx_invpcid_supported,
9136
9137         .set_supported_cpuid = vmx_set_supported_cpuid,
9138
9139         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
9140
9141         .set_tsc_khz = vmx_set_tsc_khz,
9142         .read_tsc_offset = vmx_read_tsc_offset,
9143         .write_tsc_offset = vmx_write_tsc_offset,
9144         .adjust_tsc_offset = vmx_adjust_tsc_offset,
9145         .compute_tsc_offset = vmx_compute_tsc_offset,
9146         .read_l1_tsc = vmx_read_l1_tsc,
9147
9148         .set_tdp_cr3 = vmx_set_cr3,
9149
9150         .check_intercept = vmx_check_intercept,
9151         .handle_external_intr = vmx_handle_external_intr,
9152         .mpx_supported = vmx_mpx_supported,
9153
9154         .check_nested_events = vmx_check_nested_events,
9155
9156         .sched_in = vmx_sched_in,
9157 };
9158
9159 static int __init vmx_init(void)
9160 {
9161         int r, i, msr;
9162
9163         rdmsrl_safe(MSR_EFER, &host_efer);
9164
9165         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
9166                 kvm_define_shared_msr(i, vmx_msr_index[i]);
9167
9168         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
9169         if (!vmx_io_bitmap_a)
9170                 return -ENOMEM;
9171
9172         r = -ENOMEM;
9173
9174         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
9175         if (!vmx_io_bitmap_b)
9176                 goto out;
9177
9178         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
9179         if (!vmx_msr_bitmap_legacy)
9180                 goto out1;
9181
9182         vmx_msr_bitmap_legacy_x2apic =
9183                                 (unsigned long *)__get_free_page(GFP_KERNEL);
9184         if (!vmx_msr_bitmap_legacy_x2apic)
9185                 goto out2;
9186
9187         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
9188         if (!vmx_msr_bitmap_longmode)
9189                 goto out3;
9190
9191         vmx_msr_bitmap_longmode_x2apic =
9192                                 (unsigned long *)__get_free_page(GFP_KERNEL);
9193         if (!vmx_msr_bitmap_longmode_x2apic)
9194                 goto out4;
9195         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9196         if (!vmx_vmread_bitmap)
9197                 goto out5;
9198
9199         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9200         if (!vmx_vmwrite_bitmap)
9201                 goto out6;
9202
9203         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
9204         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
9205
9206         /*
9207          * Allow direct access to the PC debug port (it is often used for I/O
9208          * delays, but the vmexits simply slow things down).
9209          */
9210         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
9211         clear_bit(0x80, vmx_io_bitmap_a);
9212
9213         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
9214
9215         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
9216         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
9217
9218         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
9219
9220         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9221                      __alignof__(struct vcpu_vmx), THIS_MODULE);
9222         if (r)
9223                 goto out7;
9224
9225 #ifdef CONFIG_KEXEC
9226         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9227                            crash_vmclear_local_loaded_vmcss);
9228 #endif
9229
9230         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
9231         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
9232         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
9233         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
9234         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
9235         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
9236         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
9237
9238         memcpy(vmx_msr_bitmap_legacy_x2apic,
9239                         vmx_msr_bitmap_legacy, PAGE_SIZE);
9240         memcpy(vmx_msr_bitmap_longmode_x2apic,
9241                         vmx_msr_bitmap_longmode, PAGE_SIZE);
9242
9243         if (enable_apicv) {
9244                 for (msr = 0x800; msr <= 0x8ff; msr++)
9245                         vmx_disable_intercept_msr_read_x2apic(msr);
9246
9247                 /* According SDM, in x2apic mode, the whole id reg is used.
9248                  * But in KVM, it only use the highest eight bits. Need to
9249                  * intercept it */
9250                 vmx_enable_intercept_msr_read_x2apic(0x802);
9251                 /* TMCCT */
9252                 vmx_enable_intercept_msr_read_x2apic(0x839);
9253                 /* TPR */
9254                 vmx_disable_intercept_msr_write_x2apic(0x808);
9255                 /* EOI */
9256                 vmx_disable_intercept_msr_write_x2apic(0x80b);
9257                 /* SELF-IPI */
9258                 vmx_disable_intercept_msr_write_x2apic(0x83f);
9259         }
9260
9261         if (enable_ept) {
9262                 kvm_mmu_set_mask_ptes(0ull,
9263                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
9264                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
9265                         0ull, VMX_EPT_EXECUTABLE_MASK);
9266                 ept_set_mmio_spte_mask();
9267                 kvm_enable_tdp();
9268         } else
9269                 kvm_disable_tdp();
9270
9271         update_ple_window_actual_max();
9272
9273         return 0;
9274
9275 out7:
9276         free_page((unsigned long)vmx_vmwrite_bitmap);
9277 out6:
9278         free_page((unsigned long)vmx_vmread_bitmap);
9279 out5:
9280         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
9281 out4:
9282         free_page((unsigned long)vmx_msr_bitmap_longmode);
9283 out3:
9284         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9285 out2:
9286         free_page((unsigned long)vmx_msr_bitmap_legacy);
9287 out1:
9288         free_page((unsigned long)vmx_io_bitmap_b);
9289 out:
9290         free_page((unsigned long)vmx_io_bitmap_a);
9291         return r;
9292 }
9293
9294 static void __exit vmx_exit(void)
9295 {
9296         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9297         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
9298         free_page((unsigned long)vmx_msr_bitmap_legacy);
9299         free_page((unsigned long)vmx_msr_bitmap_longmode);
9300         free_page((unsigned long)vmx_io_bitmap_b);
9301         free_page((unsigned long)vmx_io_bitmap_a);
9302         free_page((unsigned long)vmx_vmwrite_bitmap);
9303         free_page((unsigned long)vmx_vmread_bitmap);
9304
9305 #ifdef CONFIG_KEXEC
9306         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
9307         synchronize_rcu();
9308 #endif
9309
9310         kvm_exit();
9311 }
9312
9313 module_init(vmx_init)
9314 module_exit(vmx_exit)