2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/trace_events.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
42 #include <asm/virtext.h>
44 #include <asm/fpu/internal.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
49 #include <asm/irq_remapping.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
55 #define __ex_clear(x, reg) \
56 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
58 MODULE_AUTHOR("Qumranet");
59 MODULE_LICENSE("GPL");
61 static const struct x86_cpu_id vmx_cpu_id[] = {
62 X86_FEATURE_MATCH(X86_FEATURE_VMX),
65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
67 static bool __read_mostly enable_vpid = 1;
68 module_param_named(vpid, enable_vpid, bool, 0444);
70 static bool __read_mostly flexpriority_enabled = 1;
71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
73 static bool __read_mostly enable_ept = 1;
74 module_param_named(ept, enable_ept, bool, S_IRUGO);
76 static bool __read_mostly enable_unrestricted_guest = 1;
77 module_param_named(unrestricted_guest,
78 enable_unrestricted_guest, bool, S_IRUGO);
80 static bool __read_mostly enable_ept_ad_bits = 1;
81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
83 static bool __read_mostly emulate_invalid_guest_state = true;
84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
86 static bool __read_mostly vmm_exclusive = 1;
87 module_param(vmm_exclusive, bool, S_IRUGO);
89 static bool __read_mostly fasteoi = 1;
90 module_param(fasteoi, bool, S_IRUGO);
92 static bool __read_mostly enable_apicv = 1;
93 module_param(enable_apicv, bool, S_IRUGO);
95 static bool __read_mostly enable_shadow_vmcs = 1;
96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested = 0;
103 module_param(nested, bool, S_IRUGO);
105 static u64 __read_mostly host_xss;
107 static bool __read_mostly enable_pml = 1;
108 module_param_named(pml, enable_pml, bool, S_IRUGO);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
114 #define KVM_VM_CR0_ALWAYS_ON \
115 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
116 #define KVM_CR4_GUEST_OWNED_BITS \
117 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
118 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
128 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
129 * ple_gap: upper bound on the amount of time between two successive
130 * executions of PAUSE in a loop. Also indicate if ple enabled.
131 * According to test, this time is usually smaller than 128 cycles.
132 * ple_window: upper bound on the amount of time a guest is allowed to execute
133 * in a PAUSE loop. Tests indicate that most spinlocks are held for
134 * less than 2^12 cycles
135 * Time is measured based on a counter that runs at the same rate as the TSC,
136 * refer SDM volume 3b section 21.6.13 & 22.1.3.
138 #define KVM_VMX_DEFAULT_PLE_GAP 128
139 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
143 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
146 module_param(ple_gap, int, S_IRUGO);
148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
149 module_param(ple_window, int, S_IRUGO);
151 /* Default doubles per-vcpu window every exit. */
152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
153 module_param(ple_window_grow, int, S_IRUGO);
155 /* Default resets per-vcpu window every exit to ple_window. */
156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
157 module_param(ple_window_shrink, int, S_IRUGO);
159 /* Default is to compute the maximum so we can never overflow. */
160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
161 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
162 module_param(ple_window_max, int, S_IRUGO);
164 extern const ulong vmx_return;
166 #define NR_AUTOLOAD_MSRS 8
167 #define VMCS02_POOL_SIZE 1
176 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
177 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
178 * loaded on this CPU (so we can clear them if the CPU goes down).
184 struct list_head loaded_vmcss_on_cpu_link;
187 struct shared_msr_entry {
194 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
195 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
196 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
197 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
198 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
199 * More than one of these structures may exist, if L1 runs multiple L2 guests.
200 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
201 * underlying hardware which will be used to run L2.
202 * This structure is packed to ensure that its layout is identical across
203 * machines (necessary for live migration).
204 * If there are changes in this struct, VMCS12_REVISION must be changed.
206 typedef u64 natural_width;
207 struct __packed vmcs12 {
208 /* According to the Intel spec, a VMCS region must start with the
209 * following two fields. Then follow implementation-specific data.
214 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
215 u32 padding[7]; /* room for future expansion */
220 u64 vm_exit_msr_store_addr;
221 u64 vm_exit_msr_load_addr;
222 u64 vm_entry_msr_load_addr;
224 u64 virtual_apic_page_addr;
225 u64 apic_access_addr;
226 u64 posted_intr_desc_addr;
228 u64 eoi_exit_bitmap0;
229 u64 eoi_exit_bitmap1;
230 u64 eoi_exit_bitmap2;
231 u64 eoi_exit_bitmap3;
233 u64 guest_physical_address;
234 u64 vmcs_link_pointer;
235 u64 guest_ia32_debugctl;
238 u64 guest_ia32_perf_global_ctrl;
246 u64 host_ia32_perf_global_ctrl;
247 u64 padding64[8]; /* room for future expansion */
249 * To allow migration of L1 (complete with its L2 guests) between
250 * machines of different natural widths (32 or 64 bit), we cannot have
251 * unsigned long fields with no explict size. We use u64 (aliased
252 * natural_width) instead. Luckily, x86 is little-endian.
254 natural_width cr0_guest_host_mask;
255 natural_width cr4_guest_host_mask;
256 natural_width cr0_read_shadow;
257 natural_width cr4_read_shadow;
258 natural_width cr3_target_value0;
259 natural_width cr3_target_value1;
260 natural_width cr3_target_value2;
261 natural_width cr3_target_value3;
262 natural_width exit_qualification;
263 natural_width guest_linear_address;
264 natural_width guest_cr0;
265 natural_width guest_cr3;
266 natural_width guest_cr4;
267 natural_width guest_es_base;
268 natural_width guest_cs_base;
269 natural_width guest_ss_base;
270 natural_width guest_ds_base;
271 natural_width guest_fs_base;
272 natural_width guest_gs_base;
273 natural_width guest_ldtr_base;
274 natural_width guest_tr_base;
275 natural_width guest_gdtr_base;
276 natural_width guest_idtr_base;
277 natural_width guest_dr7;
278 natural_width guest_rsp;
279 natural_width guest_rip;
280 natural_width guest_rflags;
281 natural_width guest_pending_dbg_exceptions;
282 natural_width guest_sysenter_esp;
283 natural_width guest_sysenter_eip;
284 natural_width host_cr0;
285 natural_width host_cr3;
286 natural_width host_cr4;
287 natural_width host_fs_base;
288 natural_width host_gs_base;
289 natural_width host_tr_base;
290 natural_width host_gdtr_base;
291 natural_width host_idtr_base;
292 natural_width host_ia32_sysenter_esp;
293 natural_width host_ia32_sysenter_eip;
294 natural_width host_rsp;
295 natural_width host_rip;
296 natural_width paddingl[8]; /* room for future expansion */
297 u32 pin_based_vm_exec_control;
298 u32 cpu_based_vm_exec_control;
299 u32 exception_bitmap;
300 u32 page_fault_error_code_mask;
301 u32 page_fault_error_code_match;
302 u32 cr3_target_count;
303 u32 vm_exit_controls;
304 u32 vm_exit_msr_store_count;
305 u32 vm_exit_msr_load_count;
306 u32 vm_entry_controls;
307 u32 vm_entry_msr_load_count;
308 u32 vm_entry_intr_info_field;
309 u32 vm_entry_exception_error_code;
310 u32 vm_entry_instruction_len;
312 u32 secondary_vm_exec_control;
313 u32 vm_instruction_error;
315 u32 vm_exit_intr_info;
316 u32 vm_exit_intr_error_code;
317 u32 idt_vectoring_info_field;
318 u32 idt_vectoring_error_code;
319 u32 vm_exit_instruction_len;
320 u32 vmx_instruction_info;
327 u32 guest_ldtr_limit;
329 u32 guest_gdtr_limit;
330 u32 guest_idtr_limit;
331 u32 guest_es_ar_bytes;
332 u32 guest_cs_ar_bytes;
333 u32 guest_ss_ar_bytes;
334 u32 guest_ds_ar_bytes;
335 u32 guest_fs_ar_bytes;
336 u32 guest_gs_ar_bytes;
337 u32 guest_ldtr_ar_bytes;
338 u32 guest_tr_ar_bytes;
339 u32 guest_interruptibility_info;
340 u32 guest_activity_state;
341 u32 guest_sysenter_cs;
342 u32 host_ia32_sysenter_cs;
343 u32 vmx_preemption_timer_value;
344 u32 padding32[7]; /* room for future expansion */
345 u16 virtual_processor_id;
347 u16 guest_es_selector;
348 u16 guest_cs_selector;
349 u16 guest_ss_selector;
350 u16 guest_ds_selector;
351 u16 guest_fs_selector;
352 u16 guest_gs_selector;
353 u16 guest_ldtr_selector;
354 u16 guest_tr_selector;
355 u16 guest_intr_status;
356 u16 host_es_selector;
357 u16 host_cs_selector;
358 u16 host_ss_selector;
359 u16 host_ds_selector;
360 u16 host_fs_selector;
361 u16 host_gs_selector;
362 u16 host_tr_selector;
366 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
367 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
368 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
370 #define VMCS12_REVISION 0x11e57ed0
373 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
374 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
375 * current implementation, 4K are reserved to avoid future complications.
377 #define VMCS12_SIZE 0x1000
379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
381 struct list_head list;
383 struct loaded_vmcs vmcs02;
387 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
388 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
391 /* Has the level1 guest done vmxon? */
395 /* The guest-physical address of the current VMCS L1 keeps for L2 */
397 /* The host-usable pointer to the above */
398 struct page *current_vmcs12_page;
399 struct vmcs12 *current_vmcs12;
400 struct vmcs *current_shadow_vmcs;
402 * Indicates if the shadow vmcs must be updated with the
403 * data hold by vmcs12
405 bool sync_shadow_vmcs;
407 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
408 struct list_head vmcs02_pool;
410 u64 vmcs01_tsc_offset;
411 /* L2 must run next, and mustn't decide to exit to L1. */
412 bool nested_run_pending;
414 * Guest pages referred to in vmcs02 with host-physical pointers, so
415 * we must keep them pinned while L2 runs.
417 struct page *apic_access_page;
418 struct page *virtual_apic_page;
419 struct page *pi_desc_page;
420 struct pi_desc *pi_desc;
423 u64 msr_ia32_feature_control;
425 struct hrtimer preemption_timer;
426 bool preemption_timer_expired;
428 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
434 u32 nested_vmx_procbased_ctls_low;
435 u32 nested_vmx_procbased_ctls_high;
436 u32 nested_vmx_true_procbased_ctls_low;
437 u32 nested_vmx_secondary_ctls_low;
438 u32 nested_vmx_secondary_ctls_high;
439 u32 nested_vmx_pinbased_ctls_low;
440 u32 nested_vmx_pinbased_ctls_high;
441 u32 nested_vmx_exit_ctls_low;
442 u32 nested_vmx_exit_ctls_high;
443 u32 nested_vmx_true_exit_ctls_low;
444 u32 nested_vmx_entry_ctls_low;
445 u32 nested_vmx_entry_ctls_high;
446 u32 nested_vmx_true_entry_ctls_low;
447 u32 nested_vmx_misc_low;
448 u32 nested_vmx_misc_high;
449 u32 nested_vmx_ept_caps;
450 u32 nested_vmx_vpid_caps;
453 #define POSTED_INTR_ON 0
454 #define POSTED_INTR_SN 1
456 /* Posted-Interrupt Descriptor */
458 u32 pir[8]; /* Posted interrupt requested */
461 /* bit 256 - Outstanding Notification */
463 /* bit 257 - Suppress Notification */
465 /* bit 271:258 - Reserved */
467 /* bit 279:272 - Notification Vector */
469 /* bit 287:280 - Reserved */
471 /* bit 319:288 - Notification Destination */
479 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
481 return test_and_set_bit(POSTED_INTR_ON,
482 (unsigned long *)&pi_desc->control);
485 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
487 return test_and_clear_bit(POSTED_INTR_ON,
488 (unsigned long *)&pi_desc->control);
491 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
493 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
496 static inline void pi_clear_sn(struct pi_desc *pi_desc)
498 return clear_bit(POSTED_INTR_SN,
499 (unsigned long *)&pi_desc->control);
502 static inline void pi_set_sn(struct pi_desc *pi_desc)
504 return set_bit(POSTED_INTR_SN,
505 (unsigned long *)&pi_desc->control);
508 static inline int pi_test_on(struct pi_desc *pi_desc)
510 return test_bit(POSTED_INTR_ON,
511 (unsigned long *)&pi_desc->control);
514 static inline int pi_test_sn(struct pi_desc *pi_desc)
516 return test_bit(POSTED_INTR_SN,
517 (unsigned long *)&pi_desc->control);
521 struct kvm_vcpu vcpu;
522 unsigned long host_rsp;
524 bool nmi_known_unmasked;
526 u32 idt_vectoring_info;
528 struct shared_msr_entry *guest_msrs;
531 unsigned long host_idt_base;
533 u64 msr_host_kernel_gs_base;
534 u64 msr_guest_kernel_gs_base;
536 u32 vm_entry_controls_shadow;
537 u32 vm_exit_controls_shadow;
539 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
540 * non-nested (L1) guest, it always points to vmcs01. For a nested
541 * guest (L2), it points to a different VMCS.
543 struct loaded_vmcs vmcs01;
544 struct loaded_vmcs *loaded_vmcs;
545 bool __launched; /* temporary, used in vmx_vcpu_run */
546 struct msr_autoload {
548 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
549 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
553 u16 fs_sel, gs_sel, ldt_sel;
557 int gs_ldt_reload_needed;
558 int fs_reload_needed;
559 u64 msr_host_bndcfgs;
560 unsigned long vmcs_host_cr4; /* May not match real cr4 */
565 struct kvm_segment segs[8];
568 u32 bitmask; /* 4 bits per segment (1 bit per field) */
569 struct kvm_save_segment {
577 bool emulation_required;
579 /* Support for vnmi-less CPUs */
580 int soft_vnmi_blocked;
582 s64 vnmi_blocked_time;
585 /* Posted interrupt descriptor */
586 struct pi_desc pi_desc;
588 /* Support for a guest hypervisor (nested VMX) */
589 struct nested_vmx nested;
591 /* Dynamic PLE window. */
593 bool ple_window_dirty;
595 /* Support for PML */
596 #define PML_ENTITY_NUM 512
600 enum segment_cache_field {
609 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
611 return container_of(vcpu, struct vcpu_vmx, vcpu);
614 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
616 return &(to_vmx(vcpu)->pi_desc);
619 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
620 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
621 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
622 [number##_HIGH] = VMCS12_OFFSET(name)+4
625 static unsigned long shadow_read_only_fields[] = {
627 * We do NOT shadow fields that are modified when L0
628 * traps and emulates any vmx instruction (e.g. VMPTRLD,
629 * VMXON...) executed by L1.
630 * For example, VM_INSTRUCTION_ERROR is read
631 * by L1 if a vmx instruction fails (part of the error path).
632 * Note the code assumes this logic. If for some reason
633 * we start shadowing these fields then we need to
634 * force a shadow sync when L0 emulates vmx instructions
635 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
636 * by nested_vmx_failValid)
640 VM_EXIT_INSTRUCTION_LEN,
641 IDT_VECTORING_INFO_FIELD,
642 IDT_VECTORING_ERROR_CODE,
643 VM_EXIT_INTR_ERROR_CODE,
645 GUEST_LINEAR_ADDRESS,
646 GUEST_PHYSICAL_ADDRESS
648 static int max_shadow_read_only_fields =
649 ARRAY_SIZE(shadow_read_only_fields);
651 static unsigned long shadow_read_write_fields[] = {
658 GUEST_INTERRUPTIBILITY_INFO,
671 CPU_BASED_VM_EXEC_CONTROL,
672 VM_ENTRY_EXCEPTION_ERROR_CODE,
673 VM_ENTRY_INTR_INFO_FIELD,
674 VM_ENTRY_INSTRUCTION_LEN,
675 VM_ENTRY_EXCEPTION_ERROR_CODE,
681 static int max_shadow_read_write_fields =
682 ARRAY_SIZE(shadow_read_write_fields);
684 static const unsigned short vmcs_field_to_offset_table[] = {
685 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
686 FIELD(POSTED_INTR_NV, posted_intr_nv),
687 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
688 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
689 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
690 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
691 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
692 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
693 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
694 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
695 FIELD(GUEST_INTR_STATUS, guest_intr_status),
696 FIELD(HOST_ES_SELECTOR, host_es_selector),
697 FIELD(HOST_CS_SELECTOR, host_cs_selector),
698 FIELD(HOST_SS_SELECTOR, host_ss_selector),
699 FIELD(HOST_DS_SELECTOR, host_ds_selector),
700 FIELD(HOST_FS_SELECTOR, host_fs_selector),
701 FIELD(HOST_GS_SELECTOR, host_gs_selector),
702 FIELD(HOST_TR_SELECTOR, host_tr_selector),
703 FIELD64(IO_BITMAP_A, io_bitmap_a),
704 FIELD64(IO_BITMAP_B, io_bitmap_b),
705 FIELD64(MSR_BITMAP, msr_bitmap),
706 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
707 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
708 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
709 FIELD64(TSC_OFFSET, tsc_offset),
710 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
711 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
712 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
713 FIELD64(EPT_POINTER, ept_pointer),
714 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
715 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
716 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
717 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
718 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
719 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
720 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
721 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
722 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
723 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
724 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
725 FIELD64(GUEST_PDPTR0, guest_pdptr0),
726 FIELD64(GUEST_PDPTR1, guest_pdptr1),
727 FIELD64(GUEST_PDPTR2, guest_pdptr2),
728 FIELD64(GUEST_PDPTR3, guest_pdptr3),
729 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
730 FIELD64(HOST_IA32_PAT, host_ia32_pat),
731 FIELD64(HOST_IA32_EFER, host_ia32_efer),
732 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
733 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
734 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
735 FIELD(EXCEPTION_BITMAP, exception_bitmap),
736 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
737 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
738 FIELD(CR3_TARGET_COUNT, cr3_target_count),
739 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
740 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
741 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
742 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
743 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
744 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
745 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
746 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
747 FIELD(TPR_THRESHOLD, tpr_threshold),
748 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
749 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
750 FIELD(VM_EXIT_REASON, vm_exit_reason),
751 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
752 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
753 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
754 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
755 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
756 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
757 FIELD(GUEST_ES_LIMIT, guest_es_limit),
758 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
759 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
760 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
761 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
762 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
763 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
764 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
765 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
766 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
767 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
768 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
769 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
770 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
771 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
772 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
773 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
774 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
775 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
776 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
777 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
778 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
779 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
780 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
781 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
782 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
783 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
784 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
785 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
786 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
787 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
788 FIELD(EXIT_QUALIFICATION, exit_qualification),
789 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
790 FIELD(GUEST_CR0, guest_cr0),
791 FIELD(GUEST_CR3, guest_cr3),
792 FIELD(GUEST_CR4, guest_cr4),
793 FIELD(GUEST_ES_BASE, guest_es_base),
794 FIELD(GUEST_CS_BASE, guest_cs_base),
795 FIELD(GUEST_SS_BASE, guest_ss_base),
796 FIELD(GUEST_DS_BASE, guest_ds_base),
797 FIELD(GUEST_FS_BASE, guest_fs_base),
798 FIELD(GUEST_GS_BASE, guest_gs_base),
799 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
800 FIELD(GUEST_TR_BASE, guest_tr_base),
801 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
802 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
803 FIELD(GUEST_DR7, guest_dr7),
804 FIELD(GUEST_RSP, guest_rsp),
805 FIELD(GUEST_RIP, guest_rip),
806 FIELD(GUEST_RFLAGS, guest_rflags),
807 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
808 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
809 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
810 FIELD(HOST_CR0, host_cr0),
811 FIELD(HOST_CR3, host_cr3),
812 FIELD(HOST_CR4, host_cr4),
813 FIELD(HOST_FS_BASE, host_fs_base),
814 FIELD(HOST_GS_BASE, host_gs_base),
815 FIELD(HOST_TR_BASE, host_tr_base),
816 FIELD(HOST_GDTR_BASE, host_gdtr_base),
817 FIELD(HOST_IDTR_BASE, host_idtr_base),
818 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
819 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
820 FIELD(HOST_RSP, host_rsp),
821 FIELD(HOST_RIP, host_rip),
824 static inline short vmcs_field_to_offset(unsigned long field)
826 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
828 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
829 vmcs_field_to_offset_table[field] == 0)
832 return vmcs_field_to_offset_table[field];
835 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
837 return to_vmx(vcpu)->nested.current_vmcs12;
840 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
842 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
843 if (is_error_page(page))
849 static void nested_release_page(struct page *page)
851 kvm_release_page_dirty(page);
854 static void nested_release_page_clean(struct page *page)
856 kvm_release_page_clean(page);
859 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
860 static u64 construct_eptp(unsigned long root_hpa);
861 static void kvm_cpu_vmxon(u64 addr);
862 static void kvm_cpu_vmxoff(void);
863 static bool vmx_mpx_supported(void);
864 static bool vmx_xsaves_supported(void);
865 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
866 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
867 static void vmx_set_segment(struct kvm_vcpu *vcpu,
868 struct kvm_segment *var, int seg);
869 static void vmx_get_segment(struct kvm_vcpu *vcpu,
870 struct kvm_segment *var, int seg);
871 static bool guest_state_valid(struct kvm_vcpu *vcpu);
872 static u32 vmx_segment_access_rights(struct kvm_segment *var);
873 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
874 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
875 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
876 static int alloc_identity_pagetable(struct kvm *kvm);
878 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
879 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
881 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
882 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
884 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
885 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
888 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
889 * can find which vCPU should be waken up.
891 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
892 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
894 static unsigned long *vmx_io_bitmap_a;
895 static unsigned long *vmx_io_bitmap_b;
896 static unsigned long *vmx_msr_bitmap_legacy;
897 static unsigned long *vmx_msr_bitmap_longmode;
898 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
899 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
900 static unsigned long *vmx_msr_bitmap_nested;
901 static unsigned long *vmx_vmread_bitmap;
902 static unsigned long *vmx_vmwrite_bitmap;
904 static bool cpu_has_load_ia32_efer;
905 static bool cpu_has_load_perf_global_ctrl;
907 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
908 static DEFINE_SPINLOCK(vmx_vpid_lock);
910 static struct vmcs_config {
914 u32 pin_based_exec_ctrl;
915 u32 cpu_based_exec_ctrl;
916 u32 cpu_based_2nd_exec_ctrl;
921 static struct vmx_capability {
926 #define VMX_SEGMENT_FIELD(seg) \
927 [VCPU_SREG_##seg] = { \
928 .selector = GUEST_##seg##_SELECTOR, \
929 .base = GUEST_##seg##_BASE, \
930 .limit = GUEST_##seg##_LIMIT, \
931 .ar_bytes = GUEST_##seg##_AR_BYTES, \
934 static const struct kvm_vmx_segment_field {
939 } kvm_vmx_segment_fields[] = {
940 VMX_SEGMENT_FIELD(CS),
941 VMX_SEGMENT_FIELD(DS),
942 VMX_SEGMENT_FIELD(ES),
943 VMX_SEGMENT_FIELD(FS),
944 VMX_SEGMENT_FIELD(GS),
945 VMX_SEGMENT_FIELD(SS),
946 VMX_SEGMENT_FIELD(TR),
947 VMX_SEGMENT_FIELD(LDTR),
950 static u64 host_efer;
952 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
955 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
956 * away by decrementing the array size.
958 static const u32 vmx_msr_index[] = {
960 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
962 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
965 static inline bool is_page_fault(u32 intr_info)
967 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
968 INTR_INFO_VALID_MASK)) ==
969 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
972 static inline bool is_no_device(u32 intr_info)
974 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
975 INTR_INFO_VALID_MASK)) ==
976 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
979 static inline bool is_invalid_opcode(u32 intr_info)
981 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
982 INTR_INFO_VALID_MASK)) ==
983 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
986 static inline bool is_external_interrupt(u32 intr_info)
988 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
989 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
992 static inline bool is_machine_check(u32 intr_info)
994 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
995 INTR_INFO_VALID_MASK)) ==
996 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
999 static inline bool cpu_has_vmx_msr_bitmap(void)
1001 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1004 static inline bool cpu_has_vmx_tpr_shadow(void)
1006 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1009 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1011 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1014 static inline bool cpu_has_secondary_exec_ctrls(void)
1016 return vmcs_config.cpu_based_exec_ctrl &
1017 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1020 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1026 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1028 return vmcs_config.cpu_based_2nd_exec_ctrl &
1029 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1032 static inline bool cpu_has_vmx_apic_register_virt(void)
1034 return vmcs_config.cpu_based_2nd_exec_ctrl &
1035 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1038 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1040 return vmcs_config.cpu_based_2nd_exec_ctrl &
1041 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1044 static inline bool cpu_has_vmx_posted_intr(void)
1046 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1047 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1050 static inline bool cpu_has_vmx_apicv(void)
1052 return cpu_has_vmx_apic_register_virt() &&
1053 cpu_has_vmx_virtual_intr_delivery() &&
1054 cpu_has_vmx_posted_intr();
1057 static inline bool cpu_has_vmx_flexpriority(void)
1059 return cpu_has_vmx_tpr_shadow() &&
1060 cpu_has_vmx_virtualize_apic_accesses();
1063 static inline bool cpu_has_vmx_ept_execute_only(void)
1065 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1068 static inline bool cpu_has_vmx_ept_2m_page(void)
1070 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1073 static inline bool cpu_has_vmx_ept_1g_page(void)
1075 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1078 static inline bool cpu_has_vmx_ept_4levels(void)
1080 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1083 static inline bool cpu_has_vmx_ept_ad_bits(void)
1085 return vmx_capability.ept & VMX_EPT_AD_BIT;
1088 static inline bool cpu_has_vmx_invept_context(void)
1090 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1093 static inline bool cpu_has_vmx_invept_global(void)
1095 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1098 static inline bool cpu_has_vmx_invvpid_single(void)
1100 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1103 static inline bool cpu_has_vmx_invvpid_global(void)
1105 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1108 static inline bool cpu_has_vmx_ept(void)
1110 return vmcs_config.cpu_based_2nd_exec_ctrl &
1111 SECONDARY_EXEC_ENABLE_EPT;
1114 static inline bool cpu_has_vmx_unrestricted_guest(void)
1116 return vmcs_config.cpu_based_2nd_exec_ctrl &
1117 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1120 static inline bool cpu_has_vmx_ple(void)
1122 return vmcs_config.cpu_based_2nd_exec_ctrl &
1123 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1126 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1128 return flexpriority_enabled && lapic_in_kernel(vcpu);
1131 static inline bool cpu_has_vmx_vpid(void)
1133 return vmcs_config.cpu_based_2nd_exec_ctrl &
1134 SECONDARY_EXEC_ENABLE_VPID;
1137 static inline bool cpu_has_vmx_rdtscp(void)
1139 return vmcs_config.cpu_based_2nd_exec_ctrl &
1140 SECONDARY_EXEC_RDTSCP;
1143 static inline bool cpu_has_vmx_invpcid(void)
1145 return vmcs_config.cpu_based_2nd_exec_ctrl &
1146 SECONDARY_EXEC_ENABLE_INVPCID;
1149 static inline bool cpu_has_virtual_nmis(void)
1151 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1154 static inline bool cpu_has_vmx_wbinvd_exit(void)
1156 return vmcs_config.cpu_based_2nd_exec_ctrl &
1157 SECONDARY_EXEC_WBINVD_EXITING;
1160 static inline bool cpu_has_vmx_shadow_vmcs(void)
1163 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1164 /* check if the cpu supports writing r/o exit information fields */
1165 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1168 return vmcs_config.cpu_based_2nd_exec_ctrl &
1169 SECONDARY_EXEC_SHADOW_VMCS;
1172 static inline bool cpu_has_vmx_pml(void)
1174 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1177 static inline bool cpu_has_vmx_tsc_scaling(void)
1179 return vmcs_config.cpu_based_2nd_exec_ctrl &
1180 SECONDARY_EXEC_TSC_SCALING;
1183 static inline bool report_flexpriority(void)
1185 return flexpriority_enabled;
1188 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1190 return vmcs12->cpu_based_vm_exec_control & bit;
1193 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1195 return (vmcs12->cpu_based_vm_exec_control &
1196 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1197 (vmcs12->secondary_vm_exec_control & bit);
1200 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1202 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1205 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1207 return vmcs12->pin_based_vm_exec_control &
1208 PIN_BASED_VMX_PREEMPTION_TIMER;
1211 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1213 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1216 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1218 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1219 vmx_xsaves_supported();
1222 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1224 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1227 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1229 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1232 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1234 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1237 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1239 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1242 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1244 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1247 static inline bool is_exception(u32 intr_info)
1249 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1250 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1253 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1255 unsigned long exit_qualification);
1256 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1257 struct vmcs12 *vmcs12,
1258 u32 reason, unsigned long qualification);
1260 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1264 for (i = 0; i < vmx->nmsrs; ++i)
1265 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1270 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1276 } operand = { vpid, 0, gva };
1278 asm volatile (__ex(ASM_VMX_INVVPID)
1279 /* CF==1 or ZF==1 --> rc = -1 */
1280 "; ja 1f ; ud2 ; 1:"
1281 : : "a"(&operand), "c"(ext) : "cc", "memory");
1284 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1288 } operand = {eptp, gpa};
1290 asm volatile (__ex(ASM_VMX_INVEPT)
1291 /* CF==1 or ZF==1 --> rc = -1 */
1292 "; ja 1f ; ud2 ; 1:\n"
1293 : : "a" (&operand), "c" (ext) : "cc", "memory");
1296 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1300 i = __find_msr_index(vmx, msr);
1302 return &vmx->guest_msrs[i];
1306 static void vmcs_clear(struct vmcs *vmcs)
1308 u64 phys_addr = __pa(vmcs);
1311 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1312 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1315 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1319 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1321 vmcs_clear(loaded_vmcs->vmcs);
1322 loaded_vmcs->cpu = -1;
1323 loaded_vmcs->launched = 0;
1326 static void vmcs_load(struct vmcs *vmcs)
1328 u64 phys_addr = __pa(vmcs);
1331 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1332 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1335 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1339 #ifdef CONFIG_KEXEC_CORE
1341 * This bitmap is used to indicate whether the vmclear
1342 * operation is enabled on all cpus. All disabled by
1345 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1347 static inline void crash_enable_local_vmclear(int cpu)
1349 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1352 static inline void crash_disable_local_vmclear(int cpu)
1354 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1357 static inline int crash_local_vmclear_enabled(int cpu)
1359 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1362 static void crash_vmclear_local_loaded_vmcss(void)
1364 int cpu = raw_smp_processor_id();
1365 struct loaded_vmcs *v;
1367 if (!crash_local_vmclear_enabled(cpu))
1370 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1371 loaded_vmcss_on_cpu_link)
1372 vmcs_clear(v->vmcs);
1375 static inline void crash_enable_local_vmclear(int cpu) { }
1376 static inline void crash_disable_local_vmclear(int cpu) { }
1377 #endif /* CONFIG_KEXEC_CORE */
1379 static void __loaded_vmcs_clear(void *arg)
1381 struct loaded_vmcs *loaded_vmcs = arg;
1382 int cpu = raw_smp_processor_id();
1384 if (loaded_vmcs->cpu != cpu)
1385 return; /* vcpu migration can race with cpu offline */
1386 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1387 per_cpu(current_vmcs, cpu) = NULL;
1388 crash_disable_local_vmclear(cpu);
1389 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1392 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1393 * is before setting loaded_vmcs->vcpu to -1 which is done in
1394 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1395 * then adds the vmcs into percpu list before it is deleted.
1399 loaded_vmcs_init(loaded_vmcs);
1400 crash_enable_local_vmclear(cpu);
1403 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1405 int cpu = loaded_vmcs->cpu;
1408 smp_call_function_single(cpu,
1409 __loaded_vmcs_clear, loaded_vmcs, 1);
1412 static inline void vpid_sync_vcpu_single(int vpid)
1417 if (cpu_has_vmx_invvpid_single())
1418 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1421 static inline void vpid_sync_vcpu_global(void)
1423 if (cpu_has_vmx_invvpid_global())
1424 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1427 static inline void vpid_sync_context(int vpid)
1429 if (cpu_has_vmx_invvpid_single())
1430 vpid_sync_vcpu_single(vpid);
1432 vpid_sync_vcpu_global();
1435 static inline void ept_sync_global(void)
1437 if (cpu_has_vmx_invept_global())
1438 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1441 static inline void ept_sync_context(u64 eptp)
1444 if (cpu_has_vmx_invept_context())
1445 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1451 static __always_inline unsigned long vmcs_readl(unsigned long field)
1453 unsigned long value;
1455 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1456 : "=a"(value) : "d"(field) : "cc");
1460 static __always_inline u16 vmcs_read16(unsigned long field)
1462 return vmcs_readl(field);
1465 static __always_inline u32 vmcs_read32(unsigned long field)
1467 return vmcs_readl(field);
1470 static __always_inline u64 vmcs_read64(unsigned long field)
1472 #ifdef CONFIG_X86_64
1473 return vmcs_readl(field);
1475 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1479 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1481 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1482 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1486 static void vmcs_writel(unsigned long field, unsigned long value)
1490 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1491 : "=q"(error) : "a"(value), "d"(field) : "cc");
1492 if (unlikely(error))
1493 vmwrite_error(field, value);
1496 static void vmcs_write16(unsigned long field, u16 value)
1498 vmcs_writel(field, value);
1501 static void vmcs_write32(unsigned long field, u32 value)
1503 vmcs_writel(field, value);
1506 static void vmcs_write64(unsigned long field, u64 value)
1508 vmcs_writel(field, value);
1509 #ifndef CONFIG_X86_64
1511 vmcs_writel(field+1, value >> 32);
1515 static void vmcs_clear_bits(unsigned long field, u32 mask)
1517 vmcs_writel(field, vmcs_readl(field) & ~mask);
1520 static void vmcs_set_bits(unsigned long field, u32 mask)
1522 vmcs_writel(field, vmcs_readl(field) | mask);
1525 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1527 vmcs_write32(VM_ENTRY_CONTROLS, val);
1528 vmx->vm_entry_controls_shadow = val;
1531 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1533 if (vmx->vm_entry_controls_shadow != val)
1534 vm_entry_controls_init(vmx, val);
1537 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1539 return vmx->vm_entry_controls_shadow;
1543 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1545 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1548 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1550 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1553 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1555 vmcs_write32(VM_EXIT_CONTROLS, val);
1556 vmx->vm_exit_controls_shadow = val;
1559 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1561 if (vmx->vm_exit_controls_shadow != val)
1562 vm_exit_controls_init(vmx, val);
1565 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1567 return vmx->vm_exit_controls_shadow;
1571 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1573 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1576 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1578 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1581 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1583 vmx->segment_cache.bitmask = 0;
1586 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1590 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1592 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1593 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1594 vmx->segment_cache.bitmask = 0;
1596 ret = vmx->segment_cache.bitmask & mask;
1597 vmx->segment_cache.bitmask |= mask;
1601 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1603 u16 *p = &vmx->segment_cache.seg[seg].selector;
1605 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1606 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1610 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1612 ulong *p = &vmx->segment_cache.seg[seg].base;
1614 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1615 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1619 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1621 u32 *p = &vmx->segment_cache.seg[seg].limit;
1623 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1624 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1628 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1630 u32 *p = &vmx->segment_cache.seg[seg].ar;
1632 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1633 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1637 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1641 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1642 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1643 if ((vcpu->guest_debug &
1644 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1645 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1646 eb |= 1u << BP_VECTOR;
1647 if (to_vmx(vcpu)->rmode.vm86_active)
1650 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1651 if (vcpu->fpu_active)
1652 eb &= ~(1u << NM_VECTOR);
1654 /* When we are running a nested L2 guest and L1 specified for it a
1655 * certain exception bitmap, we must trap the same exceptions and pass
1656 * them to L1. When running L2, we will only handle the exceptions
1657 * specified above if L1 did not want them.
1659 if (is_guest_mode(vcpu))
1660 eb |= get_vmcs12(vcpu)->exception_bitmap;
1662 vmcs_write32(EXCEPTION_BITMAP, eb);
1665 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1666 unsigned long entry, unsigned long exit)
1668 vm_entry_controls_clearbit(vmx, entry);
1669 vm_exit_controls_clearbit(vmx, exit);
1672 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1675 struct msr_autoload *m = &vmx->msr_autoload;
1679 if (cpu_has_load_ia32_efer) {
1680 clear_atomic_switch_msr_special(vmx,
1681 VM_ENTRY_LOAD_IA32_EFER,
1682 VM_EXIT_LOAD_IA32_EFER);
1686 case MSR_CORE_PERF_GLOBAL_CTRL:
1687 if (cpu_has_load_perf_global_ctrl) {
1688 clear_atomic_switch_msr_special(vmx,
1689 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1690 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1696 for (i = 0; i < m->nr; ++i)
1697 if (m->guest[i].index == msr)
1703 m->guest[i] = m->guest[m->nr];
1704 m->host[i] = m->host[m->nr];
1705 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1706 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1709 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1710 unsigned long entry, unsigned long exit,
1711 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1712 u64 guest_val, u64 host_val)
1714 vmcs_write64(guest_val_vmcs, guest_val);
1715 vmcs_write64(host_val_vmcs, host_val);
1716 vm_entry_controls_setbit(vmx, entry);
1717 vm_exit_controls_setbit(vmx, exit);
1720 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1721 u64 guest_val, u64 host_val)
1724 struct msr_autoload *m = &vmx->msr_autoload;
1728 if (cpu_has_load_ia32_efer) {
1729 add_atomic_switch_msr_special(vmx,
1730 VM_ENTRY_LOAD_IA32_EFER,
1731 VM_EXIT_LOAD_IA32_EFER,
1734 guest_val, host_val);
1738 case MSR_CORE_PERF_GLOBAL_CTRL:
1739 if (cpu_has_load_perf_global_ctrl) {
1740 add_atomic_switch_msr_special(vmx,
1741 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1742 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1743 GUEST_IA32_PERF_GLOBAL_CTRL,
1744 HOST_IA32_PERF_GLOBAL_CTRL,
1745 guest_val, host_val);
1751 for (i = 0; i < m->nr; ++i)
1752 if (m->guest[i].index == msr)
1755 if (i == NR_AUTOLOAD_MSRS) {
1756 printk_once(KERN_WARNING "Not enough msr switch entries. "
1757 "Can't add msr %x\n", msr);
1759 } else if (i == m->nr) {
1761 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1762 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1765 m->guest[i].index = msr;
1766 m->guest[i].value = guest_val;
1767 m->host[i].index = msr;
1768 m->host[i].value = host_val;
1771 static void reload_tss(void)
1774 * VT restores TR but not its size. Useless.
1776 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1777 struct desc_struct *descs;
1779 descs = (void *)gdt->address;
1780 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1784 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1789 guest_efer = vmx->vcpu.arch.efer;
1792 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1795 ignore_bits = EFER_NX | EFER_SCE;
1796 #ifdef CONFIG_X86_64
1797 ignore_bits |= EFER_LMA | EFER_LME;
1798 /* SCE is meaningful only in long mode on Intel */
1799 if (guest_efer & EFER_LMA)
1800 ignore_bits &= ~(u64)EFER_SCE;
1802 guest_efer &= ~ignore_bits;
1803 guest_efer |= host_efer & ignore_bits;
1804 vmx->guest_msrs[efer_offset].data = guest_efer;
1805 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1807 clear_atomic_switch_msr(vmx, MSR_EFER);
1810 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1811 * On CPUs that support "load IA32_EFER", always switch EFER
1812 * atomically, since it's faster than switching it manually.
1814 if (cpu_has_load_ia32_efer ||
1815 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1816 guest_efer = vmx->vcpu.arch.efer;
1817 if (!(guest_efer & EFER_LMA))
1818 guest_efer &= ~EFER_LME;
1819 if (guest_efer != host_efer)
1820 add_atomic_switch_msr(vmx, MSR_EFER,
1821 guest_efer, host_efer);
1828 static unsigned long segment_base(u16 selector)
1830 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1831 struct desc_struct *d;
1832 unsigned long table_base;
1835 if (!(selector & ~3))
1838 table_base = gdt->address;
1840 if (selector & 4) { /* from ldt */
1841 u16 ldt_selector = kvm_read_ldt();
1843 if (!(ldt_selector & ~3))
1846 table_base = segment_base(ldt_selector);
1848 d = (struct desc_struct *)(table_base + (selector & ~7));
1849 v = get_desc_base(d);
1850 #ifdef CONFIG_X86_64
1851 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1852 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1857 static inline unsigned long kvm_read_tr_base(void)
1860 asm("str %0" : "=g"(tr));
1861 return segment_base(tr);
1864 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1866 struct vcpu_vmx *vmx = to_vmx(vcpu);
1869 if (vmx->host_state.loaded)
1872 vmx->host_state.loaded = 1;
1874 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1875 * allow segment selectors with cpl > 0 or ti == 1.
1877 vmx->host_state.ldt_sel = kvm_read_ldt();
1878 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1879 savesegment(fs, vmx->host_state.fs_sel);
1880 if (!(vmx->host_state.fs_sel & 7)) {
1881 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1882 vmx->host_state.fs_reload_needed = 0;
1884 vmcs_write16(HOST_FS_SELECTOR, 0);
1885 vmx->host_state.fs_reload_needed = 1;
1887 savesegment(gs, vmx->host_state.gs_sel);
1888 if (!(vmx->host_state.gs_sel & 7))
1889 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1891 vmcs_write16(HOST_GS_SELECTOR, 0);
1892 vmx->host_state.gs_ldt_reload_needed = 1;
1895 #ifdef CONFIG_X86_64
1896 savesegment(ds, vmx->host_state.ds_sel);
1897 savesegment(es, vmx->host_state.es_sel);
1900 #ifdef CONFIG_X86_64
1901 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1902 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1904 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1905 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1908 #ifdef CONFIG_X86_64
1909 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1910 if (is_long_mode(&vmx->vcpu))
1911 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1913 if (boot_cpu_has(X86_FEATURE_MPX))
1914 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1915 for (i = 0; i < vmx->save_nmsrs; ++i)
1916 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1917 vmx->guest_msrs[i].data,
1918 vmx->guest_msrs[i].mask);
1921 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1923 if (!vmx->host_state.loaded)
1926 ++vmx->vcpu.stat.host_state_reload;
1927 vmx->host_state.loaded = 0;
1928 #ifdef CONFIG_X86_64
1929 if (is_long_mode(&vmx->vcpu))
1930 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1932 if (vmx->host_state.gs_ldt_reload_needed) {
1933 kvm_load_ldt(vmx->host_state.ldt_sel);
1934 #ifdef CONFIG_X86_64
1935 load_gs_index(vmx->host_state.gs_sel);
1937 loadsegment(gs, vmx->host_state.gs_sel);
1940 if (vmx->host_state.fs_reload_needed)
1941 loadsegment(fs, vmx->host_state.fs_sel);
1942 #ifdef CONFIG_X86_64
1943 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1944 loadsegment(ds, vmx->host_state.ds_sel);
1945 loadsegment(es, vmx->host_state.es_sel);
1949 #ifdef CONFIG_X86_64
1950 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1952 if (vmx->host_state.msr_host_bndcfgs)
1953 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1955 * If the FPU is not active (through the host task or
1956 * the guest vcpu), then restore the cr0.TS bit.
1958 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1960 load_gdt(this_cpu_ptr(&host_gdt));
1963 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1966 __vmx_load_host_state(vmx);
1970 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1972 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1973 struct pi_desc old, new;
1976 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1977 !irq_remapping_cap(IRQ_POSTING_CAP))
1981 old.control = new.control = pi_desc->control;
1984 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1985 * are two possible cases:
1986 * 1. After running 'pre_block', context switch
1987 * happened. For this case, 'sn' was set in
1988 * vmx_vcpu_put(), so we need to clear it here.
1989 * 2. After running 'pre_block', we were blocked,
1990 * and woken up by some other guy. For this case,
1991 * we don't need to do anything, 'pi_post_block'
1992 * will do everything for us. However, we cannot
1993 * check whether it is case #1 or case #2 here
1994 * (maybe, not needed), so we also clear sn here,
1995 * I think it is not a big deal.
1997 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
1998 if (vcpu->cpu != cpu) {
1999 dest = cpu_physical_id(cpu);
2001 if (x2apic_enabled())
2004 new.ndst = (dest << 8) & 0xFF00;
2007 /* set 'NV' to 'notification vector' */
2008 new.nv = POSTED_INTR_VECTOR;
2011 /* Allow posting non-urgent interrupts */
2013 } while (cmpxchg(&pi_desc->control, old.control,
2014 new.control) != old.control);
2017 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2018 * vcpu mutex is already taken.
2020 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2022 struct vcpu_vmx *vmx = to_vmx(vcpu);
2023 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2026 kvm_cpu_vmxon(phys_addr);
2027 else if (vmx->loaded_vmcs->cpu != cpu)
2028 loaded_vmcs_clear(vmx->loaded_vmcs);
2030 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2031 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2032 vmcs_load(vmx->loaded_vmcs->vmcs);
2035 if (vmx->loaded_vmcs->cpu != cpu) {
2036 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2037 unsigned long sysenter_esp;
2039 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2040 local_irq_disable();
2041 crash_disable_local_vmclear(cpu);
2044 * Read loaded_vmcs->cpu should be before fetching
2045 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2046 * See the comments in __loaded_vmcs_clear().
2050 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2051 &per_cpu(loaded_vmcss_on_cpu, cpu));
2052 crash_enable_local_vmclear(cpu);
2056 * Linux uses per-cpu TSS and GDT, so set these when switching
2059 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2060 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
2062 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2063 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2065 /* Setup TSC multiplier */
2066 if (cpu_has_vmx_tsc_scaling())
2067 vmcs_write64(TSC_MULTIPLIER,
2068 vcpu->arch.tsc_scaling_ratio);
2070 vmx->loaded_vmcs->cpu = cpu;
2073 vmx_vcpu_pi_load(vcpu, cpu);
2076 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2078 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2080 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2081 !irq_remapping_cap(IRQ_POSTING_CAP))
2084 /* Set SN when the vCPU is preempted */
2085 if (vcpu->preempted)
2089 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2091 vmx_vcpu_pi_put(vcpu);
2093 __vmx_load_host_state(to_vmx(vcpu));
2094 if (!vmm_exclusive) {
2095 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2101 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2105 if (vcpu->fpu_active)
2107 vcpu->fpu_active = 1;
2108 cr0 = vmcs_readl(GUEST_CR0);
2109 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2110 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2111 vmcs_writel(GUEST_CR0, cr0);
2112 update_exception_bitmap(vcpu);
2113 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2114 if (is_guest_mode(vcpu))
2115 vcpu->arch.cr0_guest_owned_bits &=
2116 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2117 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2120 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2123 * Return the cr0 value that a nested guest would read. This is a combination
2124 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2125 * its hypervisor (cr0_read_shadow).
2127 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2129 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2130 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2132 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2134 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2135 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2138 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2140 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2141 * set this *before* calling this function.
2143 vmx_decache_cr0_guest_bits(vcpu);
2144 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2145 update_exception_bitmap(vcpu);
2146 vcpu->arch.cr0_guest_owned_bits = 0;
2147 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2148 if (is_guest_mode(vcpu)) {
2150 * L1's specified read shadow might not contain the TS bit,
2151 * so now that we turned on shadowing of this bit, we need to
2152 * set this bit of the shadow. Like in nested_vmx_run we need
2153 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2154 * up-to-date here because we just decached cr0.TS (and we'll
2155 * only update vmcs12->guest_cr0 on nested exit).
2157 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2158 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2159 (vcpu->arch.cr0 & X86_CR0_TS);
2160 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2162 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2165 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2167 unsigned long rflags, save_rflags;
2169 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2170 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2171 rflags = vmcs_readl(GUEST_RFLAGS);
2172 if (to_vmx(vcpu)->rmode.vm86_active) {
2173 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2174 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2175 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2177 to_vmx(vcpu)->rflags = rflags;
2179 return to_vmx(vcpu)->rflags;
2182 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2184 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2185 to_vmx(vcpu)->rflags = rflags;
2186 if (to_vmx(vcpu)->rmode.vm86_active) {
2187 to_vmx(vcpu)->rmode.save_rflags = rflags;
2188 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2190 vmcs_writel(GUEST_RFLAGS, rflags);
2193 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2195 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2198 if (interruptibility & GUEST_INTR_STATE_STI)
2199 ret |= KVM_X86_SHADOW_INT_STI;
2200 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2201 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2206 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2208 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2209 u32 interruptibility = interruptibility_old;
2211 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2213 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2214 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2215 else if (mask & KVM_X86_SHADOW_INT_STI)
2216 interruptibility |= GUEST_INTR_STATE_STI;
2218 if ((interruptibility != interruptibility_old))
2219 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2222 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2226 rip = kvm_rip_read(vcpu);
2227 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2228 kvm_rip_write(vcpu, rip);
2230 /* skipping an emulated instruction also counts */
2231 vmx_set_interrupt_shadow(vcpu, 0);
2235 * KVM wants to inject page-faults which it got to the guest. This function
2236 * checks whether in a nested guest, we need to inject them to L1 or L2.
2238 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2240 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2242 if (!(vmcs12->exception_bitmap & (1u << nr)))
2245 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2246 vmcs_read32(VM_EXIT_INTR_INFO),
2247 vmcs_readl(EXIT_QUALIFICATION));
2251 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2252 bool has_error_code, u32 error_code,
2255 struct vcpu_vmx *vmx = to_vmx(vcpu);
2256 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2258 if (!reinject && is_guest_mode(vcpu) &&
2259 nested_vmx_check_exception(vcpu, nr))
2262 if (has_error_code) {
2263 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2264 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2267 if (vmx->rmode.vm86_active) {
2269 if (kvm_exception_is_soft(nr))
2270 inc_eip = vcpu->arch.event_exit_inst_len;
2271 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2272 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2276 if (kvm_exception_is_soft(nr)) {
2277 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2278 vmx->vcpu.arch.event_exit_inst_len);
2279 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2281 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2283 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2286 static bool vmx_rdtscp_supported(void)
2288 return cpu_has_vmx_rdtscp();
2291 static bool vmx_invpcid_supported(void)
2293 return cpu_has_vmx_invpcid() && enable_ept;
2297 * Swap MSR entry in host/guest MSR entry array.
2299 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2301 struct shared_msr_entry tmp;
2303 tmp = vmx->guest_msrs[to];
2304 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2305 vmx->guest_msrs[from] = tmp;
2308 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2310 unsigned long *msr_bitmap;
2312 if (is_guest_mode(vcpu))
2313 msr_bitmap = vmx_msr_bitmap_nested;
2314 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2315 if (is_long_mode(vcpu))
2316 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2318 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2320 if (is_long_mode(vcpu))
2321 msr_bitmap = vmx_msr_bitmap_longmode;
2323 msr_bitmap = vmx_msr_bitmap_legacy;
2326 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2330 * Set up the vmcs to automatically save and restore system
2331 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2332 * mode, as fiddling with msrs is very expensive.
2334 static void setup_msrs(struct vcpu_vmx *vmx)
2336 int save_nmsrs, index;
2339 #ifdef CONFIG_X86_64
2340 if (is_long_mode(&vmx->vcpu)) {
2341 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2343 move_msr_up(vmx, index, save_nmsrs++);
2344 index = __find_msr_index(vmx, MSR_LSTAR);
2346 move_msr_up(vmx, index, save_nmsrs++);
2347 index = __find_msr_index(vmx, MSR_CSTAR);
2349 move_msr_up(vmx, index, save_nmsrs++);
2350 index = __find_msr_index(vmx, MSR_TSC_AUX);
2351 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2352 move_msr_up(vmx, index, save_nmsrs++);
2354 * MSR_STAR is only needed on long mode guests, and only
2355 * if efer.sce is enabled.
2357 index = __find_msr_index(vmx, MSR_STAR);
2358 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2359 move_msr_up(vmx, index, save_nmsrs++);
2362 index = __find_msr_index(vmx, MSR_EFER);
2363 if (index >= 0 && update_transition_efer(vmx, index))
2364 move_msr_up(vmx, index, save_nmsrs++);
2366 vmx->save_nmsrs = save_nmsrs;
2368 if (cpu_has_vmx_msr_bitmap())
2369 vmx_set_msr_bitmap(&vmx->vcpu);
2373 * reads and returns guest's timestamp counter "register"
2374 * guest_tsc = host_tsc + tsc_offset -- 21.3
2376 static u64 guest_read_tsc(void)
2378 u64 host_tsc, tsc_offset;
2381 tsc_offset = vmcs_read64(TSC_OFFSET);
2382 return host_tsc + tsc_offset;
2386 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2387 * counter, even if a nested guest (L2) is currently running.
2389 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2393 tsc_offset = is_guest_mode(vcpu) ?
2394 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2395 vmcs_read64(TSC_OFFSET);
2396 return host_tsc + tsc_offset;
2399 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2401 return vmcs_read64(TSC_OFFSET);
2405 * writes 'offset' into guest's timestamp counter offset register
2407 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2409 if (is_guest_mode(vcpu)) {
2411 * We're here if L1 chose not to trap WRMSR to TSC. According
2412 * to the spec, this should set L1's TSC; The offset that L1
2413 * set for L2 remains unchanged, and still needs to be added
2414 * to the newly set TSC to get L2's TSC.
2416 struct vmcs12 *vmcs12;
2417 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2418 /* recalculate vmcs02.TSC_OFFSET: */
2419 vmcs12 = get_vmcs12(vcpu);
2420 vmcs_write64(TSC_OFFSET, offset +
2421 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2422 vmcs12->tsc_offset : 0));
2424 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2425 vmcs_read64(TSC_OFFSET), offset);
2426 vmcs_write64(TSC_OFFSET, offset);
2430 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2432 u64 offset = vmcs_read64(TSC_OFFSET);
2434 vmcs_write64(TSC_OFFSET, offset + adjustment);
2435 if (is_guest_mode(vcpu)) {
2436 /* Even when running L2, the adjustment needs to apply to L1 */
2437 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2439 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2440 offset + adjustment);
2443 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2445 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2446 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2450 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2451 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2452 * all guests if the "nested" module option is off, and can also be disabled
2453 * for a single guest by disabling its VMX cpuid bit.
2455 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2457 return nested && guest_cpuid_has_vmx(vcpu);
2461 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2462 * returned for the various VMX controls MSRs when nested VMX is enabled.
2463 * The same values should also be used to verify that vmcs12 control fields are
2464 * valid during nested entry from L1 to L2.
2465 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2466 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2467 * bit in the high half is on if the corresponding bit in the control field
2468 * may be on. See also vmx_control_verify().
2470 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2473 * Note that as a general rule, the high half of the MSRs (bits in
2474 * the control fields which may be 1) should be initialized by the
2475 * intersection of the underlying hardware's MSR (i.e., features which
2476 * can be supported) and the list of features we want to expose -
2477 * because they are known to be properly supported in our code.
2478 * Also, usually, the low half of the MSRs (bits which must be 1) can
2479 * be set to 0, meaning that L1 may turn off any of these bits. The
2480 * reason is that if one of these bits is necessary, it will appear
2481 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2482 * fields of vmcs01 and vmcs02, will turn these bits off - and
2483 * nested_vmx_exit_handled() will not pass related exits to L1.
2484 * These rules have exceptions below.
2487 /* pin-based controls */
2488 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2489 vmx->nested.nested_vmx_pinbased_ctls_low,
2490 vmx->nested.nested_vmx_pinbased_ctls_high);
2491 vmx->nested.nested_vmx_pinbased_ctls_low |=
2492 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2493 vmx->nested.nested_vmx_pinbased_ctls_high &=
2494 PIN_BASED_EXT_INTR_MASK |
2495 PIN_BASED_NMI_EXITING |
2496 PIN_BASED_VIRTUAL_NMIS;
2497 vmx->nested.nested_vmx_pinbased_ctls_high |=
2498 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2499 PIN_BASED_VMX_PREEMPTION_TIMER;
2500 if (vmx_cpu_uses_apicv(&vmx->vcpu))
2501 vmx->nested.nested_vmx_pinbased_ctls_high |=
2502 PIN_BASED_POSTED_INTR;
2505 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2506 vmx->nested.nested_vmx_exit_ctls_low,
2507 vmx->nested.nested_vmx_exit_ctls_high);
2508 vmx->nested.nested_vmx_exit_ctls_low =
2509 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2511 vmx->nested.nested_vmx_exit_ctls_high &=
2512 #ifdef CONFIG_X86_64
2513 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2515 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2516 vmx->nested.nested_vmx_exit_ctls_high |=
2517 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2518 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2519 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2521 if (vmx_mpx_supported())
2522 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2524 /* We support free control of debug control saving. */
2525 vmx->nested.nested_vmx_true_exit_ctls_low =
2526 vmx->nested.nested_vmx_exit_ctls_low &
2527 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2529 /* entry controls */
2530 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2531 vmx->nested.nested_vmx_entry_ctls_low,
2532 vmx->nested.nested_vmx_entry_ctls_high);
2533 vmx->nested.nested_vmx_entry_ctls_low =
2534 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2535 vmx->nested.nested_vmx_entry_ctls_high &=
2536 #ifdef CONFIG_X86_64
2537 VM_ENTRY_IA32E_MODE |
2539 VM_ENTRY_LOAD_IA32_PAT;
2540 vmx->nested.nested_vmx_entry_ctls_high |=
2541 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2542 if (vmx_mpx_supported())
2543 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2545 /* We support free control of debug control loading. */
2546 vmx->nested.nested_vmx_true_entry_ctls_low =
2547 vmx->nested.nested_vmx_entry_ctls_low &
2548 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2550 /* cpu-based controls */
2551 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2552 vmx->nested.nested_vmx_procbased_ctls_low,
2553 vmx->nested.nested_vmx_procbased_ctls_high);
2554 vmx->nested.nested_vmx_procbased_ctls_low =
2555 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2556 vmx->nested.nested_vmx_procbased_ctls_high &=
2557 CPU_BASED_VIRTUAL_INTR_PENDING |
2558 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2559 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2560 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2561 CPU_BASED_CR3_STORE_EXITING |
2562 #ifdef CONFIG_X86_64
2563 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2565 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2566 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2567 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2568 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2569 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2571 * We can allow some features even when not supported by the
2572 * hardware. For example, L1 can specify an MSR bitmap - and we
2573 * can use it to avoid exits to L1 - even when L0 runs L2
2574 * without MSR bitmaps.
2576 vmx->nested.nested_vmx_procbased_ctls_high |=
2577 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2578 CPU_BASED_USE_MSR_BITMAPS;
2580 /* We support free control of CR3 access interception. */
2581 vmx->nested.nested_vmx_true_procbased_ctls_low =
2582 vmx->nested.nested_vmx_procbased_ctls_low &
2583 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2585 /* secondary cpu-based controls */
2586 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2587 vmx->nested.nested_vmx_secondary_ctls_low,
2588 vmx->nested.nested_vmx_secondary_ctls_high);
2589 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2590 vmx->nested.nested_vmx_secondary_ctls_high &=
2591 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2592 SECONDARY_EXEC_RDTSCP |
2593 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2594 SECONDARY_EXEC_ENABLE_VPID |
2595 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2596 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2597 SECONDARY_EXEC_WBINVD_EXITING |
2598 SECONDARY_EXEC_XSAVES |
2599 SECONDARY_EXEC_PCOMMIT;
2602 /* nested EPT: emulate EPT also to L1 */
2603 vmx->nested.nested_vmx_secondary_ctls_high |=
2604 SECONDARY_EXEC_ENABLE_EPT;
2605 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2606 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2608 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2610 * For nested guests, we don't do anything specific
2611 * for single context invalidation. Hence, only advertise
2612 * support for global context invalidation.
2614 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2616 vmx->nested.nested_vmx_ept_caps = 0;
2619 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2620 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2622 vmx->nested.nested_vmx_vpid_caps = 0;
2624 if (enable_unrestricted_guest)
2625 vmx->nested.nested_vmx_secondary_ctls_high |=
2626 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2628 /* miscellaneous data */
2629 rdmsr(MSR_IA32_VMX_MISC,
2630 vmx->nested.nested_vmx_misc_low,
2631 vmx->nested.nested_vmx_misc_high);
2632 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2633 vmx->nested.nested_vmx_misc_low |=
2634 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2635 VMX_MISC_ACTIVITY_HLT;
2636 vmx->nested.nested_vmx_misc_high = 0;
2639 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2642 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2644 return ((control & high) | low) == control;
2647 static inline u64 vmx_control_msr(u32 low, u32 high)
2649 return low | ((u64)high << 32);
2652 /* Returns 0 on success, non-0 otherwise. */
2653 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2655 struct vcpu_vmx *vmx = to_vmx(vcpu);
2657 switch (msr_index) {
2658 case MSR_IA32_VMX_BASIC:
2660 * This MSR reports some information about VMX support. We
2661 * should return information about the VMX we emulate for the
2662 * guest, and the VMCS structure we give it - not about the
2663 * VMX support of the underlying hardware.
2665 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2666 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2667 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2669 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2670 case MSR_IA32_VMX_PINBASED_CTLS:
2671 *pdata = vmx_control_msr(
2672 vmx->nested.nested_vmx_pinbased_ctls_low,
2673 vmx->nested.nested_vmx_pinbased_ctls_high);
2675 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2676 *pdata = vmx_control_msr(
2677 vmx->nested.nested_vmx_true_procbased_ctls_low,
2678 vmx->nested.nested_vmx_procbased_ctls_high);
2680 case MSR_IA32_VMX_PROCBASED_CTLS:
2681 *pdata = vmx_control_msr(
2682 vmx->nested.nested_vmx_procbased_ctls_low,
2683 vmx->nested.nested_vmx_procbased_ctls_high);
2685 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2686 *pdata = vmx_control_msr(
2687 vmx->nested.nested_vmx_true_exit_ctls_low,
2688 vmx->nested.nested_vmx_exit_ctls_high);
2690 case MSR_IA32_VMX_EXIT_CTLS:
2691 *pdata = vmx_control_msr(
2692 vmx->nested.nested_vmx_exit_ctls_low,
2693 vmx->nested.nested_vmx_exit_ctls_high);
2695 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2696 *pdata = vmx_control_msr(
2697 vmx->nested.nested_vmx_true_entry_ctls_low,
2698 vmx->nested.nested_vmx_entry_ctls_high);
2700 case MSR_IA32_VMX_ENTRY_CTLS:
2701 *pdata = vmx_control_msr(
2702 vmx->nested.nested_vmx_entry_ctls_low,
2703 vmx->nested.nested_vmx_entry_ctls_high);
2705 case MSR_IA32_VMX_MISC:
2706 *pdata = vmx_control_msr(
2707 vmx->nested.nested_vmx_misc_low,
2708 vmx->nested.nested_vmx_misc_high);
2711 * These MSRs specify bits which the guest must keep fixed (on or off)
2712 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2713 * We picked the standard core2 setting.
2715 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2716 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2717 case MSR_IA32_VMX_CR0_FIXED0:
2718 *pdata = VMXON_CR0_ALWAYSON;
2720 case MSR_IA32_VMX_CR0_FIXED1:
2723 case MSR_IA32_VMX_CR4_FIXED0:
2724 *pdata = VMXON_CR4_ALWAYSON;
2726 case MSR_IA32_VMX_CR4_FIXED1:
2729 case MSR_IA32_VMX_VMCS_ENUM:
2730 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2732 case MSR_IA32_VMX_PROCBASED_CTLS2:
2733 *pdata = vmx_control_msr(
2734 vmx->nested.nested_vmx_secondary_ctls_low,
2735 vmx->nested.nested_vmx_secondary_ctls_high);
2737 case MSR_IA32_VMX_EPT_VPID_CAP:
2738 /* Currently, no nested vpid support */
2739 *pdata = vmx->nested.nested_vmx_ept_caps |
2740 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2750 * Reads an msr value (of 'msr_index') into 'pdata'.
2751 * Returns 0 on success, non-0 otherwise.
2752 * Assumes vcpu_load() was already called.
2754 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2756 struct shared_msr_entry *msr;
2758 switch (msr_info->index) {
2759 #ifdef CONFIG_X86_64
2761 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2764 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2766 case MSR_KERNEL_GS_BASE:
2767 vmx_load_host_state(to_vmx(vcpu));
2768 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2772 return kvm_get_msr_common(vcpu, msr_info);
2774 msr_info->data = guest_read_tsc();
2776 case MSR_IA32_SYSENTER_CS:
2777 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2779 case MSR_IA32_SYSENTER_EIP:
2780 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2782 case MSR_IA32_SYSENTER_ESP:
2783 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2785 case MSR_IA32_BNDCFGS:
2786 if (!vmx_mpx_supported())
2788 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2790 case MSR_IA32_FEATURE_CONTROL:
2791 if (!nested_vmx_allowed(vcpu))
2793 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2795 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2796 if (!nested_vmx_allowed(vcpu))
2798 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2800 if (!vmx_xsaves_supported())
2802 msr_info->data = vcpu->arch.ia32_xss;
2805 if (!guest_cpuid_has_rdtscp(vcpu))
2807 /* Otherwise falls through */
2809 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2811 msr_info->data = msr->data;
2814 return kvm_get_msr_common(vcpu, msr_info);
2820 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2823 * Writes msr value into into the appropriate "register".
2824 * Returns 0 on success, non-0 otherwise.
2825 * Assumes vcpu_load() was already called.
2827 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2829 struct vcpu_vmx *vmx = to_vmx(vcpu);
2830 struct shared_msr_entry *msr;
2832 u32 msr_index = msr_info->index;
2833 u64 data = msr_info->data;
2835 switch (msr_index) {
2837 ret = kvm_set_msr_common(vcpu, msr_info);
2839 #ifdef CONFIG_X86_64
2841 vmx_segment_cache_clear(vmx);
2842 vmcs_writel(GUEST_FS_BASE, data);
2845 vmx_segment_cache_clear(vmx);
2846 vmcs_writel(GUEST_GS_BASE, data);
2848 case MSR_KERNEL_GS_BASE:
2849 vmx_load_host_state(vmx);
2850 vmx->msr_guest_kernel_gs_base = data;
2853 case MSR_IA32_SYSENTER_CS:
2854 vmcs_write32(GUEST_SYSENTER_CS, data);
2856 case MSR_IA32_SYSENTER_EIP:
2857 vmcs_writel(GUEST_SYSENTER_EIP, data);
2859 case MSR_IA32_SYSENTER_ESP:
2860 vmcs_writel(GUEST_SYSENTER_ESP, data);
2862 case MSR_IA32_BNDCFGS:
2863 if (!vmx_mpx_supported())
2865 vmcs_write64(GUEST_BNDCFGS, data);
2868 kvm_write_tsc(vcpu, msr_info);
2870 case MSR_IA32_CR_PAT:
2871 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2872 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2874 vmcs_write64(GUEST_IA32_PAT, data);
2875 vcpu->arch.pat = data;
2878 ret = kvm_set_msr_common(vcpu, msr_info);
2880 case MSR_IA32_TSC_ADJUST:
2881 ret = kvm_set_msr_common(vcpu, msr_info);
2883 case MSR_IA32_FEATURE_CONTROL:
2884 if (!nested_vmx_allowed(vcpu) ||
2885 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2886 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2888 vmx->nested.msr_ia32_feature_control = data;
2889 if (msr_info->host_initiated && data == 0)
2890 vmx_leave_nested(vcpu);
2892 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2893 return 1; /* they are read-only */
2895 if (!vmx_xsaves_supported())
2898 * The only supported bit as of Skylake is bit 8, but
2899 * it is not supported on KVM.
2903 vcpu->arch.ia32_xss = data;
2904 if (vcpu->arch.ia32_xss != host_xss)
2905 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2906 vcpu->arch.ia32_xss, host_xss);
2908 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2911 if (!guest_cpuid_has_rdtscp(vcpu))
2913 /* Check reserved bit, higher 32 bits should be zero */
2914 if ((data >> 32) != 0)
2916 /* Otherwise falls through */
2918 msr = find_msr_entry(vmx, msr_index);
2920 u64 old_msr_data = msr->data;
2922 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2924 ret = kvm_set_shared_msr(msr->index, msr->data,
2928 msr->data = old_msr_data;
2932 ret = kvm_set_msr_common(vcpu, msr_info);
2938 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2940 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2943 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2946 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2948 case VCPU_EXREG_PDPTR:
2950 ept_save_pdptrs(vcpu);
2957 static __init int cpu_has_kvm_support(void)
2959 return cpu_has_vmx();
2962 static __init int vmx_disabled_by_bios(void)
2966 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2967 if (msr & FEATURE_CONTROL_LOCKED) {
2968 /* launched w/ TXT and VMX disabled */
2969 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2972 /* launched w/o TXT and VMX only enabled w/ TXT */
2973 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2974 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2975 && !tboot_enabled()) {
2976 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2977 "activate TXT before enabling KVM\n");
2980 /* launched w/o TXT and VMX disabled */
2981 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2982 && !tboot_enabled())
2989 static void kvm_cpu_vmxon(u64 addr)
2991 asm volatile (ASM_VMX_VMXON_RAX
2992 : : "a"(&addr), "m"(addr)
2996 static int hardware_enable(void)
2998 int cpu = raw_smp_processor_id();
2999 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3002 if (cr4_read_shadow() & X86_CR4_VMXE)
3005 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3006 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3007 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3010 * Now we can enable the vmclear operation in kdump
3011 * since the loaded_vmcss_on_cpu list on this cpu
3012 * has been initialized.
3014 * Though the cpu is not in VMX operation now, there
3015 * is no problem to enable the vmclear operation
3016 * for the loaded_vmcss_on_cpu list is empty!
3018 crash_enable_local_vmclear(cpu);
3020 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3022 test_bits = FEATURE_CONTROL_LOCKED;
3023 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3024 if (tboot_enabled())
3025 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3027 if ((old & test_bits) != test_bits) {
3028 /* enable and lock */
3029 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3031 cr4_set_bits(X86_CR4_VMXE);
3033 if (vmm_exclusive) {
3034 kvm_cpu_vmxon(phys_addr);
3038 native_store_gdt(this_cpu_ptr(&host_gdt));
3043 static void vmclear_local_loaded_vmcss(void)
3045 int cpu = raw_smp_processor_id();
3046 struct loaded_vmcs *v, *n;
3048 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3049 loaded_vmcss_on_cpu_link)
3050 __loaded_vmcs_clear(v);
3054 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3057 static void kvm_cpu_vmxoff(void)
3059 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3062 static void hardware_disable(void)
3064 if (vmm_exclusive) {
3065 vmclear_local_loaded_vmcss();
3068 cr4_clear_bits(X86_CR4_VMXE);
3071 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3072 u32 msr, u32 *result)
3074 u32 vmx_msr_low, vmx_msr_high;
3075 u32 ctl = ctl_min | ctl_opt;
3077 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3079 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3080 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3082 /* Ensure minimum (required) set of control bits are supported. */
3090 static __init bool allow_1_setting(u32 msr, u32 ctl)
3092 u32 vmx_msr_low, vmx_msr_high;
3094 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3095 return vmx_msr_high & ctl;
3098 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3100 u32 vmx_msr_low, vmx_msr_high;
3101 u32 min, opt, min2, opt2;
3102 u32 _pin_based_exec_control = 0;
3103 u32 _cpu_based_exec_control = 0;
3104 u32 _cpu_based_2nd_exec_control = 0;
3105 u32 _vmexit_control = 0;
3106 u32 _vmentry_control = 0;
3108 min = CPU_BASED_HLT_EXITING |
3109 #ifdef CONFIG_X86_64
3110 CPU_BASED_CR8_LOAD_EXITING |
3111 CPU_BASED_CR8_STORE_EXITING |
3113 CPU_BASED_CR3_LOAD_EXITING |
3114 CPU_BASED_CR3_STORE_EXITING |
3115 CPU_BASED_USE_IO_BITMAPS |
3116 CPU_BASED_MOV_DR_EXITING |
3117 CPU_BASED_USE_TSC_OFFSETING |
3118 CPU_BASED_MWAIT_EXITING |
3119 CPU_BASED_MONITOR_EXITING |
3120 CPU_BASED_INVLPG_EXITING |
3121 CPU_BASED_RDPMC_EXITING;
3123 opt = CPU_BASED_TPR_SHADOW |
3124 CPU_BASED_USE_MSR_BITMAPS |
3125 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3126 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3127 &_cpu_based_exec_control) < 0)
3129 #ifdef CONFIG_X86_64
3130 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3131 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3132 ~CPU_BASED_CR8_STORE_EXITING;
3134 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3136 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3137 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3138 SECONDARY_EXEC_WBINVD_EXITING |
3139 SECONDARY_EXEC_ENABLE_VPID |
3140 SECONDARY_EXEC_ENABLE_EPT |
3141 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3142 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3143 SECONDARY_EXEC_RDTSCP |
3144 SECONDARY_EXEC_ENABLE_INVPCID |
3145 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3146 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3147 SECONDARY_EXEC_SHADOW_VMCS |
3148 SECONDARY_EXEC_XSAVES |
3149 SECONDARY_EXEC_ENABLE_PML |
3150 SECONDARY_EXEC_PCOMMIT |
3151 SECONDARY_EXEC_TSC_SCALING;
3152 if (adjust_vmx_controls(min2, opt2,
3153 MSR_IA32_VMX_PROCBASED_CTLS2,
3154 &_cpu_based_2nd_exec_control) < 0)
3157 #ifndef CONFIG_X86_64
3158 if (!(_cpu_based_2nd_exec_control &
3159 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3160 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3163 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3164 _cpu_based_2nd_exec_control &= ~(
3165 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3166 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3167 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3169 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3170 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3172 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3173 CPU_BASED_CR3_STORE_EXITING |
3174 CPU_BASED_INVLPG_EXITING);
3175 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3176 vmx_capability.ept, vmx_capability.vpid);
3179 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3180 #ifdef CONFIG_X86_64
3181 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3183 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3184 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3185 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3186 &_vmexit_control) < 0)
3189 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3190 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3191 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3192 &_pin_based_exec_control) < 0)
3195 if (!(_cpu_based_2nd_exec_control &
3196 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3197 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3198 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3200 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3201 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3202 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3203 &_vmentry_control) < 0)
3206 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3208 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3209 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3212 #ifdef CONFIG_X86_64
3213 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3214 if (vmx_msr_high & (1u<<16))
3218 /* Require Write-Back (WB) memory type for VMCS accesses. */
3219 if (((vmx_msr_high >> 18) & 15) != 6)
3222 vmcs_conf->size = vmx_msr_high & 0x1fff;
3223 vmcs_conf->order = get_order(vmcs_config.size);
3224 vmcs_conf->revision_id = vmx_msr_low;
3226 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3227 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3228 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3229 vmcs_conf->vmexit_ctrl = _vmexit_control;
3230 vmcs_conf->vmentry_ctrl = _vmentry_control;
3232 cpu_has_load_ia32_efer =
3233 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3234 VM_ENTRY_LOAD_IA32_EFER)
3235 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3236 VM_EXIT_LOAD_IA32_EFER);
3238 cpu_has_load_perf_global_ctrl =
3239 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3240 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3241 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3242 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3245 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3246 * but due to arrata below it can't be used. Workaround is to use
3247 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3249 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3254 * BC86,AAY89,BD102 (model 44)
3258 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3259 switch (boot_cpu_data.x86_model) {
3265 cpu_has_load_perf_global_ctrl = false;
3266 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3267 "does not work properly. Using workaround\n");
3275 rdmsrl(MSR_IA32_XSS, host_xss);
3280 static struct vmcs *alloc_vmcs_cpu(int cpu)
3282 int node = cpu_to_node(cpu);
3286 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3289 vmcs = page_address(pages);
3290 memset(vmcs, 0, vmcs_config.size);
3291 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3295 static struct vmcs *alloc_vmcs(void)
3297 return alloc_vmcs_cpu(raw_smp_processor_id());
3300 static void free_vmcs(struct vmcs *vmcs)
3302 free_pages((unsigned long)vmcs, vmcs_config.order);
3306 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3308 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3310 if (!loaded_vmcs->vmcs)
3312 loaded_vmcs_clear(loaded_vmcs);
3313 free_vmcs(loaded_vmcs->vmcs);
3314 loaded_vmcs->vmcs = NULL;
3317 static void free_kvm_area(void)
3321 for_each_possible_cpu(cpu) {
3322 free_vmcs(per_cpu(vmxarea, cpu));
3323 per_cpu(vmxarea, cpu) = NULL;
3327 static void init_vmcs_shadow_fields(void)
3331 /* No checks for read only fields yet */
3333 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3334 switch (shadow_read_write_fields[i]) {
3336 if (!vmx_mpx_supported())
3344 shadow_read_write_fields[j] =
3345 shadow_read_write_fields[i];
3348 max_shadow_read_write_fields = j;
3350 /* shadowed fields guest access without vmexit */
3351 for (i = 0; i < max_shadow_read_write_fields; i++) {
3352 clear_bit(shadow_read_write_fields[i],
3353 vmx_vmwrite_bitmap);
3354 clear_bit(shadow_read_write_fields[i],
3357 for (i = 0; i < max_shadow_read_only_fields; i++)
3358 clear_bit(shadow_read_only_fields[i],
3362 static __init int alloc_kvm_area(void)
3366 for_each_possible_cpu(cpu) {
3369 vmcs = alloc_vmcs_cpu(cpu);
3375 per_cpu(vmxarea, cpu) = vmcs;
3380 static bool emulation_required(struct kvm_vcpu *vcpu)
3382 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3385 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3386 struct kvm_segment *save)
3388 if (!emulate_invalid_guest_state) {
3390 * CS and SS RPL should be equal during guest entry according
3391 * to VMX spec, but in reality it is not always so. Since vcpu
3392 * is in the middle of the transition from real mode to
3393 * protected mode it is safe to assume that RPL 0 is a good
3396 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3397 save->selector &= ~SEGMENT_RPL_MASK;
3398 save->dpl = save->selector & SEGMENT_RPL_MASK;
3401 vmx_set_segment(vcpu, save, seg);
3404 static void enter_pmode(struct kvm_vcpu *vcpu)
3406 unsigned long flags;
3407 struct vcpu_vmx *vmx = to_vmx(vcpu);
3410 * Update real mode segment cache. It may be not up-to-date if sement
3411 * register was written while vcpu was in a guest mode.
3413 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3414 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3415 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3416 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3417 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3418 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3420 vmx->rmode.vm86_active = 0;
3422 vmx_segment_cache_clear(vmx);
3424 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3426 flags = vmcs_readl(GUEST_RFLAGS);
3427 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3428 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3429 vmcs_writel(GUEST_RFLAGS, flags);
3431 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3432 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3434 update_exception_bitmap(vcpu);
3436 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3437 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3438 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3439 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3440 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3441 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3444 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3446 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3447 struct kvm_segment var = *save;
3450 if (seg == VCPU_SREG_CS)
3453 if (!emulate_invalid_guest_state) {
3454 var.selector = var.base >> 4;
3455 var.base = var.base & 0xffff0;
3465 if (save->base & 0xf)
3466 printk_once(KERN_WARNING "kvm: segment base is not "
3467 "paragraph aligned when entering "
3468 "protected mode (seg=%d)", seg);
3471 vmcs_write16(sf->selector, var.selector);
3472 vmcs_write32(sf->base, var.base);
3473 vmcs_write32(sf->limit, var.limit);
3474 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3477 static void enter_rmode(struct kvm_vcpu *vcpu)
3479 unsigned long flags;
3480 struct vcpu_vmx *vmx = to_vmx(vcpu);
3482 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3483 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3484 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3485 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3486 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3487 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3488 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3490 vmx->rmode.vm86_active = 1;
3493 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3494 * vcpu. Warn the user that an update is overdue.
3496 if (!vcpu->kvm->arch.tss_addr)
3497 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3498 "called before entering vcpu\n");
3500 vmx_segment_cache_clear(vmx);
3502 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3503 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3504 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3506 flags = vmcs_readl(GUEST_RFLAGS);
3507 vmx->rmode.save_rflags = flags;
3509 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3511 vmcs_writel(GUEST_RFLAGS, flags);
3512 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3513 update_exception_bitmap(vcpu);
3515 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3516 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3517 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3518 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3519 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3520 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3522 kvm_mmu_reset_context(vcpu);
3525 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3527 struct vcpu_vmx *vmx = to_vmx(vcpu);
3528 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3534 * Force kernel_gs_base reloading before EFER changes, as control
3535 * of this msr depends on is_long_mode().
3537 vmx_load_host_state(to_vmx(vcpu));
3538 vcpu->arch.efer = efer;
3539 if (efer & EFER_LMA) {
3540 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3543 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3545 msr->data = efer & ~EFER_LME;
3550 #ifdef CONFIG_X86_64
3552 static void enter_lmode(struct kvm_vcpu *vcpu)
3556 vmx_segment_cache_clear(to_vmx(vcpu));
3558 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3559 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3560 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3562 vmcs_write32(GUEST_TR_AR_BYTES,
3563 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3564 | VMX_AR_TYPE_BUSY_64_TSS);
3566 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3569 static void exit_lmode(struct kvm_vcpu *vcpu)
3571 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3572 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3577 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3579 vpid_sync_context(vpid);
3581 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3583 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3587 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3589 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3592 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3594 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3596 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3597 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3600 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3602 if (enable_ept && is_paging(vcpu))
3603 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3604 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3607 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3609 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3611 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3612 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3615 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3617 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3619 if (!test_bit(VCPU_EXREG_PDPTR,
3620 (unsigned long *)&vcpu->arch.regs_dirty))
3623 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3624 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3625 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3626 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3627 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3631 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3633 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3635 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3636 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3637 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3638 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3639 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3642 __set_bit(VCPU_EXREG_PDPTR,
3643 (unsigned long *)&vcpu->arch.regs_avail);
3644 __set_bit(VCPU_EXREG_PDPTR,
3645 (unsigned long *)&vcpu->arch.regs_dirty);
3648 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3650 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3652 struct kvm_vcpu *vcpu)
3654 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3655 vmx_decache_cr3(vcpu);
3656 if (!(cr0 & X86_CR0_PG)) {
3657 /* From paging/starting to nonpaging */
3658 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3659 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3660 (CPU_BASED_CR3_LOAD_EXITING |
3661 CPU_BASED_CR3_STORE_EXITING));
3662 vcpu->arch.cr0 = cr0;
3663 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3664 } else if (!is_paging(vcpu)) {
3665 /* From nonpaging to paging */
3666 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3667 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3668 ~(CPU_BASED_CR3_LOAD_EXITING |
3669 CPU_BASED_CR3_STORE_EXITING));
3670 vcpu->arch.cr0 = cr0;
3671 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3674 if (!(cr0 & X86_CR0_WP))
3675 *hw_cr0 &= ~X86_CR0_WP;
3678 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3680 struct vcpu_vmx *vmx = to_vmx(vcpu);
3681 unsigned long hw_cr0;
3683 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3684 if (enable_unrestricted_guest)
3685 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3687 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3689 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3692 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3696 #ifdef CONFIG_X86_64
3697 if (vcpu->arch.efer & EFER_LME) {
3698 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3700 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3706 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3708 if (!vcpu->fpu_active)
3709 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3711 vmcs_writel(CR0_READ_SHADOW, cr0);
3712 vmcs_writel(GUEST_CR0, hw_cr0);
3713 vcpu->arch.cr0 = cr0;
3715 /* depends on vcpu->arch.cr0 to be set to a new value */
3716 vmx->emulation_required = emulation_required(vcpu);
3719 static u64 construct_eptp(unsigned long root_hpa)
3723 /* TODO write the value reading from MSR */
3724 eptp = VMX_EPT_DEFAULT_MT |
3725 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3726 if (enable_ept_ad_bits)
3727 eptp |= VMX_EPT_AD_ENABLE_BIT;
3728 eptp |= (root_hpa & PAGE_MASK);
3733 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3735 unsigned long guest_cr3;
3740 eptp = construct_eptp(cr3);
3741 vmcs_write64(EPT_POINTER, eptp);
3742 if (is_paging(vcpu) || is_guest_mode(vcpu))
3743 guest_cr3 = kvm_read_cr3(vcpu);
3745 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3746 ept_load_pdptrs(vcpu);
3749 vmx_flush_tlb(vcpu);
3750 vmcs_writel(GUEST_CR3, guest_cr3);
3753 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3756 * Pass through host's Machine Check Enable value to hw_cr4, which
3757 * is in force while we are in guest mode. Do not let guests control
3758 * this bit, even if host CR4.MCE == 0.
3760 unsigned long hw_cr4 =
3761 (cr4_read_shadow() & X86_CR4_MCE) |
3762 (cr4 & ~X86_CR4_MCE) |
3763 (to_vmx(vcpu)->rmode.vm86_active ?
3764 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3766 if (cr4 & X86_CR4_VMXE) {
3768 * To use VMXON (and later other VMX instructions), a guest
3769 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3770 * So basically the check on whether to allow nested VMX
3773 if (!nested_vmx_allowed(vcpu))
3776 if (to_vmx(vcpu)->nested.vmxon &&
3777 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3780 vcpu->arch.cr4 = cr4;
3782 if (!is_paging(vcpu)) {
3783 hw_cr4 &= ~X86_CR4_PAE;
3784 hw_cr4 |= X86_CR4_PSE;
3785 } else if (!(cr4 & X86_CR4_PAE)) {
3786 hw_cr4 &= ~X86_CR4_PAE;
3790 if (!enable_unrestricted_guest && !is_paging(vcpu))
3792 * SMEP/SMAP is disabled if CPU is in non-paging mode in
3793 * hardware. However KVM always uses paging mode without
3794 * unrestricted guest.
3795 * To emulate this behavior, SMEP/SMAP needs to be manually
3796 * disabled when guest switches to non-paging mode.
3798 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3800 vmcs_writel(CR4_READ_SHADOW, cr4);
3801 vmcs_writel(GUEST_CR4, hw_cr4);
3805 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3806 struct kvm_segment *var, int seg)
3808 struct vcpu_vmx *vmx = to_vmx(vcpu);
3811 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3812 *var = vmx->rmode.segs[seg];
3813 if (seg == VCPU_SREG_TR
3814 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3816 var->base = vmx_read_guest_seg_base(vmx, seg);
3817 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3820 var->base = vmx_read_guest_seg_base(vmx, seg);
3821 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3822 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3823 ar = vmx_read_guest_seg_ar(vmx, seg);
3824 var->unusable = (ar >> 16) & 1;
3825 var->type = ar & 15;
3826 var->s = (ar >> 4) & 1;
3827 var->dpl = (ar >> 5) & 3;
3829 * Some userspaces do not preserve unusable property. Since usable
3830 * segment has to be present according to VMX spec we can use present
3831 * property to amend userspace bug by making unusable segment always
3832 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3833 * segment as unusable.
3835 var->present = !var->unusable;
3836 var->avl = (ar >> 12) & 1;
3837 var->l = (ar >> 13) & 1;
3838 var->db = (ar >> 14) & 1;
3839 var->g = (ar >> 15) & 1;
3842 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3844 struct kvm_segment s;
3846 if (to_vmx(vcpu)->rmode.vm86_active) {
3847 vmx_get_segment(vcpu, &s, seg);
3850 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3853 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3855 struct vcpu_vmx *vmx = to_vmx(vcpu);
3857 if (unlikely(vmx->rmode.vm86_active))
3860 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3861 return VMX_AR_DPL(ar);
3865 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3869 if (var->unusable || !var->present)
3872 ar = var->type & 15;
3873 ar |= (var->s & 1) << 4;
3874 ar |= (var->dpl & 3) << 5;
3875 ar |= (var->present & 1) << 7;
3876 ar |= (var->avl & 1) << 12;
3877 ar |= (var->l & 1) << 13;
3878 ar |= (var->db & 1) << 14;
3879 ar |= (var->g & 1) << 15;
3885 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3886 struct kvm_segment *var, int seg)
3888 struct vcpu_vmx *vmx = to_vmx(vcpu);
3889 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3891 vmx_segment_cache_clear(vmx);
3893 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3894 vmx->rmode.segs[seg] = *var;
3895 if (seg == VCPU_SREG_TR)
3896 vmcs_write16(sf->selector, var->selector);
3898 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3902 vmcs_writel(sf->base, var->base);
3903 vmcs_write32(sf->limit, var->limit);
3904 vmcs_write16(sf->selector, var->selector);
3907 * Fix the "Accessed" bit in AR field of segment registers for older
3909 * IA32 arch specifies that at the time of processor reset the
3910 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3911 * is setting it to 0 in the userland code. This causes invalid guest
3912 * state vmexit when "unrestricted guest" mode is turned on.
3913 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3914 * tree. Newer qemu binaries with that qemu fix would not need this
3917 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3918 var->type |= 0x1; /* Accessed */
3920 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3923 vmx->emulation_required = emulation_required(vcpu);
3926 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3928 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3930 *db = (ar >> 14) & 1;
3931 *l = (ar >> 13) & 1;
3934 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3936 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3937 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3940 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3942 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3943 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3946 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3948 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3949 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3952 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3954 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3955 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3958 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3960 struct kvm_segment var;
3963 vmx_get_segment(vcpu, &var, seg);
3965 if (seg == VCPU_SREG_CS)
3967 ar = vmx_segment_access_rights(&var);
3969 if (var.base != (var.selector << 4))
3971 if (var.limit != 0xffff)
3979 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3981 struct kvm_segment cs;
3982 unsigned int cs_rpl;
3984 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3985 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3989 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3993 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3994 if (cs.dpl > cs_rpl)
3997 if (cs.dpl != cs_rpl)
4003 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4007 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4009 struct kvm_segment ss;
4010 unsigned int ss_rpl;
4012 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4013 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4017 if (ss.type != 3 && ss.type != 7)
4021 if (ss.dpl != ss_rpl) /* DPL != RPL */
4029 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4031 struct kvm_segment var;
4034 vmx_get_segment(vcpu, &var, seg);
4035 rpl = var.selector & SEGMENT_RPL_MASK;
4043 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4044 if (var.dpl < rpl) /* DPL < RPL */
4048 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4054 static bool tr_valid(struct kvm_vcpu *vcpu)
4056 struct kvm_segment tr;
4058 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4062 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4064 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4072 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4074 struct kvm_segment ldtr;
4076 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4080 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4090 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4092 struct kvm_segment cs, ss;
4094 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4095 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4097 return ((cs.selector & SEGMENT_RPL_MASK) ==
4098 (ss.selector & SEGMENT_RPL_MASK));
4102 * Check if guest state is valid. Returns true if valid, false if
4104 * We assume that registers are always usable
4106 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4108 if (enable_unrestricted_guest)
4111 /* real mode guest state checks */
4112 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4113 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4115 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4117 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4119 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4121 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4123 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4126 /* protected mode guest state checks */
4127 if (!cs_ss_rpl_check(vcpu))
4129 if (!code_segment_valid(vcpu))
4131 if (!stack_segment_valid(vcpu))
4133 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4135 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4137 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4139 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4141 if (!tr_valid(vcpu))
4143 if (!ldtr_valid(vcpu))
4147 * - Add checks on RIP
4148 * - Add checks on RFLAGS
4154 static int init_rmode_tss(struct kvm *kvm)
4160 idx = srcu_read_lock(&kvm->srcu);
4161 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4162 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4165 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4166 r = kvm_write_guest_page(kvm, fn++, &data,
4167 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4170 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4173 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4177 r = kvm_write_guest_page(kvm, fn, &data,
4178 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4181 srcu_read_unlock(&kvm->srcu, idx);
4185 static int init_rmode_identity_map(struct kvm *kvm)
4188 pfn_t identity_map_pfn;
4194 /* Protect kvm->arch.ept_identity_pagetable_done. */
4195 mutex_lock(&kvm->slots_lock);
4197 if (likely(kvm->arch.ept_identity_pagetable_done))
4200 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4202 r = alloc_identity_pagetable(kvm);
4206 idx = srcu_read_lock(&kvm->srcu);
4207 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4210 /* Set up identity-mapping pagetable for EPT in real mode */
4211 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4212 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4213 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4214 r = kvm_write_guest_page(kvm, identity_map_pfn,
4215 &tmp, i * sizeof(tmp), sizeof(tmp));
4219 kvm->arch.ept_identity_pagetable_done = true;
4222 srcu_read_unlock(&kvm->srcu, idx);
4225 mutex_unlock(&kvm->slots_lock);
4229 static void seg_setup(int seg)
4231 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4234 vmcs_write16(sf->selector, 0);
4235 vmcs_writel(sf->base, 0);
4236 vmcs_write32(sf->limit, 0xffff);
4238 if (seg == VCPU_SREG_CS)
4239 ar |= 0x08; /* code segment */
4241 vmcs_write32(sf->ar_bytes, ar);
4244 static int alloc_apic_access_page(struct kvm *kvm)
4249 mutex_lock(&kvm->slots_lock);
4250 if (kvm->arch.apic_access_page_done)
4252 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4253 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4257 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4258 if (is_error_page(page)) {
4264 * Do not pin the page in memory, so that memory hot-unplug
4265 * is able to migrate it.
4268 kvm->arch.apic_access_page_done = true;
4270 mutex_unlock(&kvm->slots_lock);
4274 static int alloc_identity_pagetable(struct kvm *kvm)
4276 /* Called with kvm->slots_lock held. */
4280 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4282 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4283 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4288 static int allocate_vpid(void)
4294 spin_lock(&vmx_vpid_lock);
4295 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4296 if (vpid < VMX_NR_VPIDS)
4297 __set_bit(vpid, vmx_vpid_bitmap);
4300 spin_unlock(&vmx_vpid_lock);
4304 static void free_vpid(int vpid)
4306 if (!enable_vpid || vpid == 0)
4308 spin_lock(&vmx_vpid_lock);
4309 __clear_bit(vpid, vmx_vpid_bitmap);
4310 spin_unlock(&vmx_vpid_lock);
4313 #define MSR_TYPE_R 1
4314 #define MSR_TYPE_W 2
4315 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4318 int f = sizeof(unsigned long);
4320 if (!cpu_has_vmx_msr_bitmap())
4324 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4325 * have the write-low and read-high bitmap offsets the wrong way round.
4326 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4328 if (msr <= 0x1fff) {
4329 if (type & MSR_TYPE_R)
4331 __clear_bit(msr, msr_bitmap + 0x000 / f);
4333 if (type & MSR_TYPE_W)
4335 __clear_bit(msr, msr_bitmap + 0x800 / f);
4337 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4339 if (type & MSR_TYPE_R)
4341 __clear_bit(msr, msr_bitmap + 0x400 / f);
4343 if (type & MSR_TYPE_W)
4345 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4350 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4353 int f = sizeof(unsigned long);
4355 if (!cpu_has_vmx_msr_bitmap())
4359 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4360 * have the write-low and read-high bitmap offsets the wrong way round.
4361 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4363 if (msr <= 0x1fff) {
4364 if (type & MSR_TYPE_R)
4366 __set_bit(msr, msr_bitmap + 0x000 / f);
4368 if (type & MSR_TYPE_W)
4370 __set_bit(msr, msr_bitmap + 0x800 / f);
4372 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4374 if (type & MSR_TYPE_R)
4376 __set_bit(msr, msr_bitmap + 0x400 / f);
4378 if (type & MSR_TYPE_W)
4380 __set_bit(msr, msr_bitmap + 0xc00 / f);
4386 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4387 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4389 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4390 unsigned long *msr_bitmap_nested,
4393 int f = sizeof(unsigned long);
4395 if (!cpu_has_vmx_msr_bitmap()) {
4401 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4402 * have the write-low and read-high bitmap offsets the wrong way round.
4403 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4405 if (msr <= 0x1fff) {
4406 if (type & MSR_TYPE_R &&
4407 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4409 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4411 if (type & MSR_TYPE_W &&
4412 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4414 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4416 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4418 if (type & MSR_TYPE_R &&
4419 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4421 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4423 if (type & MSR_TYPE_W &&
4424 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4426 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4431 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4434 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4435 msr, MSR_TYPE_R | MSR_TYPE_W);
4436 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4437 msr, MSR_TYPE_R | MSR_TYPE_W);
4440 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4442 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4444 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4448 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4450 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4452 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4456 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4458 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4460 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4464 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4466 return enable_apicv && lapic_in_kernel(vcpu);
4469 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4471 struct vcpu_vmx *vmx = to_vmx(vcpu);
4476 if (vmx->nested.pi_desc &&
4477 vmx->nested.pi_pending) {
4478 vmx->nested.pi_pending = false;
4479 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4482 max_irr = find_last_bit(
4483 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4488 vapic_page = kmap(vmx->nested.virtual_apic_page);
4493 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4494 kunmap(vmx->nested.virtual_apic_page);
4496 status = vmcs_read16(GUEST_INTR_STATUS);
4497 if ((u8)max_irr > ((u8)status & 0xff)) {
4499 status |= (u8)max_irr;
4500 vmcs_write16(GUEST_INTR_STATUS, status);
4506 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4509 if (vcpu->mode == IN_GUEST_MODE) {
4510 struct vcpu_vmx *vmx = to_vmx(vcpu);
4513 * Currently, we don't support urgent interrupt,
4514 * all interrupts are recognized as non-urgent
4515 * interrupt, so we cannot post interrupts when
4518 * If the vcpu is in guest mode, it means it is
4519 * running instead of being scheduled out and
4520 * waiting in the run queue, and that's the only
4521 * case when 'SN' is set currently, warning if
4524 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4526 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4527 POSTED_INTR_VECTOR);
4534 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4537 struct vcpu_vmx *vmx = to_vmx(vcpu);
4539 if (is_guest_mode(vcpu) &&
4540 vector == vmx->nested.posted_intr_nv) {
4541 /* the PIR and ON have been set by L1. */
4542 kvm_vcpu_trigger_posted_interrupt(vcpu);
4544 * If a posted intr is not recognized by hardware,
4545 * we will accomplish it in the next vmentry.
4547 vmx->nested.pi_pending = true;
4548 kvm_make_request(KVM_REQ_EVENT, vcpu);
4554 * Send interrupt to vcpu via posted interrupt way.
4555 * 1. If target vcpu is running(non-root mode), send posted interrupt
4556 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4557 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4558 * interrupt from PIR in next vmentry.
4560 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4562 struct vcpu_vmx *vmx = to_vmx(vcpu);
4565 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4569 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4572 r = pi_test_and_set_on(&vmx->pi_desc);
4573 kvm_make_request(KVM_REQ_EVENT, vcpu);
4574 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4575 kvm_vcpu_kick(vcpu);
4578 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4580 struct vcpu_vmx *vmx = to_vmx(vcpu);
4582 if (!pi_test_and_clear_on(&vmx->pi_desc))
4585 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4588 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4594 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4595 * will not change in the lifetime of the guest.
4596 * Note that host-state that does change is set elsewhere. E.g., host-state
4597 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4599 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4606 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4607 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4609 /* Save the most likely value for this task's CR4 in the VMCS. */
4610 cr4 = cr4_read_shadow();
4611 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4612 vmx->host_state.vmcs_host_cr4 = cr4;
4614 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4615 #ifdef CONFIG_X86_64
4617 * Load null selectors, so we can avoid reloading them in
4618 * __vmx_load_host_state(), in case userspace uses the null selectors
4619 * too (the expected case).
4621 vmcs_write16(HOST_DS_SELECTOR, 0);
4622 vmcs_write16(HOST_ES_SELECTOR, 0);
4624 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4625 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4627 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4628 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4630 native_store_idt(&dt);
4631 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4632 vmx->host_idt_base = dt.address;
4634 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4636 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4637 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4638 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4639 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4641 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4642 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4643 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4647 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4649 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4651 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4652 if (is_guest_mode(&vmx->vcpu))
4653 vmx->vcpu.arch.cr4_guest_owned_bits &=
4654 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4655 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4658 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4660 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4662 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4663 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4664 return pin_based_exec_ctrl;
4667 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4669 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4671 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4672 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4674 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4675 exec_control &= ~CPU_BASED_TPR_SHADOW;
4676 #ifdef CONFIG_X86_64
4677 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4678 CPU_BASED_CR8_LOAD_EXITING;
4682 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4683 CPU_BASED_CR3_LOAD_EXITING |
4684 CPU_BASED_INVLPG_EXITING;
4685 return exec_control;
4688 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4690 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4691 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4692 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4694 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4696 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4697 enable_unrestricted_guest = 0;
4698 /* Enable INVPCID for non-ept guests may cause performance regression. */
4699 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4701 if (!enable_unrestricted_guest)
4702 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4704 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4705 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4706 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4707 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4708 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4709 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4711 We can NOT enable shadow_vmcs here because we don't have yet
4714 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4717 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4719 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4720 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4722 return exec_control;
4725 static void ept_set_mmio_spte_mask(void)
4728 * EPT Misconfigurations can be generated if the value of bits 2:0
4729 * of an EPT paging-structure entry is 110b (write/execute).
4730 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4733 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4736 #define VMX_XSS_EXIT_BITMAP 0
4738 * Sets up the vmcs for emulated real mode.
4740 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4742 #ifdef CONFIG_X86_64
4748 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4749 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4751 if (enable_shadow_vmcs) {
4752 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4753 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4755 if (cpu_has_vmx_msr_bitmap())
4756 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4758 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4761 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4763 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4765 if (cpu_has_secondary_exec_ctrls())
4766 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4767 vmx_secondary_exec_control(vmx));
4769 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4770 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4771 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4772 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4773 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4775 vmcs_write16(GUEST_INTR_STATUS, 0);
4777 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4778 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4782 vmcs_write32(PLE_GAP, ple_gap);
4783 vmx->ple_window = ple_window;
4784 vmx->ple_window_dirty = true;
4787 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4788 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4789 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4791 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4792 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4793 vmx_set_constant_host_state(vmx);
4794 #ifdef CONFIG_X86_64
4795 rdmsrl(MSR_FS_BASE, a);
4796 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4797 rdmsrl(MSR_GS_BASE, a);
4798 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4800 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4801 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4804 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4805 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4806 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4807 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4808 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4810 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4811 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4813 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4814 u32 index = vmx_msr_index[i];
4815 u32 data_low, data_high;
4818 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4820 if (wrmsr_safe(index, data_low, data_high) < 0)
4822 vmx->guest_msrs[j].index = i;
4823 vmx->guest_msrs[j].data = 0;
4824 vmx->guest_msrs[j].mask = -1ull;
4829 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4831 /* 22.2.1, 20.8.1 */
4832 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4834 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4835 set_cr4_guest_host_mask(vmx);
4837 if (vmx_xsaves_supported())
4838 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4843 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4845 struct vcpu_vmx *vmx = to_vmx(vcpu);
4846 struct msr_data apic_base_msr;
4849 vmx->rmode.vm86_active = 0;
4851 vmx->soft_vnmi_blocked = 0;
4853 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4854 kvm_set_cr8(vcpu, 0);
4857 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4858 MSR_IA32_APICBASE_ENABLE;
4859 if (kvm_vcpu_is_reset_bsp(vcpu))
4860 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4861 apic_base_msr.host_initiated = true;
4862 kvm_set_apic_base(vcpu, &apic_base_msr);
4865 vmx_segment_cache_clear(vmx);
4867 seg_setup(VCPU_SREG_CS);
4868 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4869 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4871 seg_setup(VCPU_SREG_DS);
4872 seg_setup(VCPU_SREG_ES);
4873 seg_setup(VCPU_SREG_FS);
4874 seg_setup(VCPU_SREG_GS);
4875 seg_setup(VCPU_SREG_SS);
4877 vmcs_write16(GUEST_TR_SELECTOR, 0);
4878 vmcs_writel(GUEST_TR_BASE, 0);
4879 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4880 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4882 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4883 vmcs_writel(GUEST_LDTR_BASE, 0);
4884 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4885 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4888 vmcs_write32(GUEST_SYSENTER_CS, 0);
4889 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4890 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4891 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4894 vmcs_writel(GUEST_RFLAGS, 0x02);
4895 kvm_rip_write(vcpu, 0xfff0);
4897 vmcs_writel(GUEST_GDTR_BASE, 0);
4898 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4900 vmcs_writel(GUEST_IDTR_BASE, 0);
4901 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4903 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4904 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4905 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4909 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4911 if (cpu_has_vmx_tpr_shadow() && !init_event) {
4912 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4913 if (cpu_need_tpr_shadow(vcpu))
4914 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4915 __pa(vcpu->arch.apic->regs));
4916 vmcs_write32(TPR_THRESHOLD, 0);
4919 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4921 if (vmx_cpu_uses_apicv(vcpu))
4922 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4925 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4927 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4928 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4929 vmx->vcpu.arch.cr0 = cr0;
4930 vmx_set_cr4(vcpu, 0);
4931 vmx_set_efer(vcpu, 0);
4932 vmx_fpu_activate(vcpu);
4933 update_exception_bitmap(vcpu);
4935 vpid_sync_context(vmx->vpid);
4939 * In nested virtualization, check if L1 asked to exit on external interrupts.
4940 * For most existing hypervisors, this will always return true.
4942 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4944 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4945 PIN_BASED_EXT_INTR_MASK;
4949 * In nested virtualization, check if L1 has set
4950 * VM_EXIT_ACK_INTR_ON_EXIT
4952 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4954 return get_vmcs12(vcpu)->vm_exit_controls &
4955 VM_EXIT_ACK_INTR_ON_EXIT;
4958 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4960 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4961 PIN_BASED_NMI_EXITING;
4964 static void enable_irq_window(struct kvm_vcpu *vcpu)
4966 u32 cpu_based_vm_exec_control;
4968 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4969 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4970 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4973 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4975 u32 cpu_based_vm_exec_control;
4977 if (!cpu_has_virtual_nmis() ||
4978 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4979 enable_irq_window(vcpu);
4983 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4984 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4985 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4988 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4990 struct vcpu_vmx *vmx = to_vmx(vcpu);
4992 int irq = vcpu->arch.interrupt.nr;
4994 trace_kvm_inj_virq(irq);
4996 ++vcpu->stat.irq_injections;
4997 if (vmx->rmode.vm86_active) {
4999 if (vcpu->arch.interrupt.soft)
5000 inc_eip = vcpu->arch.event_exit_inst_len;
5001 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5002 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5005 intr = irq | INTR_INFO_VALID_MASK;
5006 if (vcpu->arch.interrupt.soft) {
5007 intr |= INTR_TYPE_SOFT_INTR;
5008 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5009 vmx->vcpu.arch.event_exit_inst_len);
5011 intr |= INTR_TYPE_EXT_INTR;
5012 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5015 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5017 struct vcpu_vmx *vmx = to_vmx(vcpu);
5019 if (is_guest_mode(vcpu))
5022 if (!cpu_has_virtual_nmis()) {
5024 * Tracking the NMI-blocked state in software is built upon
5025 * finding the next open IRQ window. This, in turn, depends on
5026 * well-behaving guests: They have to keep IRQs disabled at
5027 * least as long as the NMI handler runs. Otherwise we may
5028 * cause NMI nesting, maybe breaking the guest. But as this is
5029 * highly unlikely, we can live with the residual risk.
5031 vmx->soft_vnmi_blocked = 1;
5032 vmx->vnmi_blocked_time = 0;
5035 ++vcpu->stat.nmi_injections;
5036 vmx->nmi_known_unmasked = false;
5037 if (vmx->rmode.vm86_active) {
5038 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5039 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5042 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5043 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5046 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5048 if (!cpu_has_virtual_nmis())
5049 return to_vmx(vcpu)->soft_vnmi_blocked;
5050 if (to_vmx(vcpu)->nmi_known_unmasked)
5052 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5055 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5057 struct vcpu_vmx *vmx = to_vmx(vcpu);
5059 if (!cpu_has_virtual_nmis()) {
5060 if (vmx->soft_vnmi_blocked != masked) {
5061 vmx->soft_vnmi_blocked = masked;
5062 vmx->vnmi_blocked_time = 0;
5065 vmx->nmi_known_unmasked = !masked;
5067 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5068 GUEST_INTR_STATE_NMI);
5070 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5071 GUEST_INTR_STATE_NMI);
5075 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5077 if (to_vmx(vcpu)->nested.nested_run_pending)
5080 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5083 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5084 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5085 | GUEST_INTR_STATE_NMI));
5088 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5090 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5091 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5092 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5093 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5096 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5100 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5104 kvm->arch.tss_addr = addr;
5105 return init_rmode_tss(kvm);
5108 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5113 * Update instruction length as we may reinject the exception
5114 * from user space while in guest debugging mode.
5116 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5117 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5118 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5122 if (vcpu->guest_debug &
5123 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5140 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5141 int vec, u32 err_code)
5144 * Instruction with address size override prefix opcode 0x67
5145 * Cause the #SS fault with 0 error code in VM86 mode.
5147 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5148 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5149 if (vcpu->arch.halt_request) {
5150 vcpu->arch.halt_request = 0;
5151 return kvm_vcpu_halt(vcpu);
5159 * Forward all other exceptions that are valid in real mode.
5160 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5161 * the required debugging infrastructure rework.
5163 kvm_queue_exception(vcpu, vec);
5168 * Trigger machine check on the host. We assume all the MSRs are already set up
5169 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5170 * We pass a fake environment to the machine check handler because we want
5171 * the guest to be always treated like user space, no matter what context
5172 * it used internally.
5174 static void kvm_machine_check(void)
5176 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5177 struct pt_regs regs = {
5178 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5179 .flags = X86_EFLAGS_IF,
5182 do_machine_check(®s, 0);
5186 static int handle_machine_check(struct kvm_vcpu *vcpu)
5188 /* already handled by vcpu_run */
5192 static int handle_exception(struct kvm_vcpu *vcpu)
5194 struct vcpu_vmx *vmx = to_vmx(vcpu);
5195 struct kvm_run *kvm_run = vcpu->run;
5196 u32 intr_info, ex_no, error_code;
5197 unsigned long cr2, rip, dr6;
5199 enum emulation_result er;
5201 vect_info = vmx->idt_vectoring_info;
5202 intr_info = vmx->exit_intr_info;
5204 if (is_machine_check(intr_info))
5205 return handle_machine_check(vcpu);
5207 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5208 return 1; /* already handled by vmx_vcpu_run() */
5210 if (is_no_device(intr_info)) {
5211 vmx_fpu_activate(vcpu);
5215 if (is_invalid_opcode(intr_info)) {
5216 if (is_guest_mode(vcpu)) {
5217 kvm_queue_exception(vcpu, UD_VECTOR);
5220 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5221 if (er != EMULATE_DONE)
5222 kvm_queue_exception(vcpu, UD_VECTOR);
5227 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5228 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5231 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5232 * MMIO, it is better to report an internal error.
5233 * See the comments in vmx_handle_exit.
5235 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5236 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5237 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5238 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5239 vcpu->run->internal.ndata = 3;
5240 vcpu->run->internal.data[0] = vect_info;
5241 vcpu->run->internal.data[1] = intr_info;
5242 vcpu->run->internal.data[2] = error_code;
5246 if (is_page_fault(intr_info)) {
5247 /* EPT won't cause page fault directly */
5249 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5250 trace_kvm_page_fault(cr2, error_code);
5252 if (kvm_event_needs_reinjection(vcpu))
5253 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5254 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5257 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5259 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5260 return handle_rmode_exception(vcpu, ex_no, error_code);
5264 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5265 if (!(vcpu->guest_debug &
5266 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5267 vcpu->arch.dr6 &= ~15;
5268 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5269 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5270 skip_emulated_instruction(vcpu);
5272 kvm_queue_exception(vcpu, DB_VECTOR);
5275 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5276 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5280 * Update instruction length as we may reinject #BP from
5281 * user space while in guest debugging mode. Reading it for
5282 * #DB as well causes no harm, it is not used in that case.
5284 vmx->vcpu.arch.event_exit_inst_len =
5285 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5286 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5287 rip = kvm_rip_read(vcpu);
5288 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5289 kvm_run->debug.arch.exception = ex_no;
5292 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5293 kvm_run->ex.exception = ex_no;
5294 kvm_run->ex.error_code = error_code;
5300 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5302 ++vcpu->stat.irq_exits;
5306 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5308 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5312 static int handle_io(struct kvm_vcpu *vcpu)
5314 unsigned long exit_qualification;
5315 int size, in, string;
5318 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5319 string = (exit_qualification & 16) != 0;
5320 in = (exit_qualification & 8) != 0;
5322 ++vcpu->stat.io_exits;
5325 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5327 port = exit_qualification >> 16;
5328 size = (exit_qualification & 7) + 1;
5329 skip_emulated_instruction(vcpu);
5331 return kvm_fast_pio_out(vcpu, size, port);
5335 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5338 * Patch in the VMCALL instruction:
5340 hypercall[0] = 0x0f;
5341 hypercall[1] = 0x01;
5342 hypercall[2] = 0xc1;
5345 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5347 unsigned long always_on = VMXON_CR0_ALWAYSON;
5348 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5350 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5351 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5352 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5353 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5354 return (val & always_on) == always_on;
5357 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5358 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5360 if (is_guest_mode(vcpu)) {
5361 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5362 unsigned long orig_val = val;
5365 * We get here when L2 changed cr0 in a way that did not change
5366 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5367 * but did change L0 shadowed bits. So we first calculate the
5368 * effective cr0 value that L1 would like to write into the
5369 * hardware. It consists of the L2-owned bits from the new
5370 * value combined with the L1-owned bits from L1's guest_cr0.
5372 val = (val & ~vmcs12->cr0_guest_host_mask) |
5373 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5375 if (!nested_cr0_valid(vcpu, val))
5378 if (kvm_set_cr0(vcpu, val))
5380 vmcs_writel(CR0_READ_SHADOW, orig_val);
5383 if (to_vmx(vcpu)->nested.vmxon &&
5384 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5386 return kvm_set_cr0(vcpu, val);
5390 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5392 if (is_guest_mode(vcpu)) {
5393 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5394 unsigned long orig_val = val;
5396 /* analogously to handle_set_cr0 */
5397 val = (val & ~vmcs12->cr4_guest_host_mask) |
5398 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5399 if (kvm_set_cr4(vcpu, val))
5401 vmcs_writel(CR4_READ_SHADOW, orig_val);
5404 return kvm_set_cr4(vcpu, val);
5407 /* called to set cr0 as approriate for clts instruction exit. */
5408 static void handle_clts(struct kvm_vcpu *vcpu)
5410 if (is_guest_mode(vcpu)) {
5412 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5413 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5414 * just pretend it's off (also in arch.cr0 for fpu_activate).
5416 vmcs_writel(CR0_READ_SHADOW,
5417 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5418 vcpu->arch.cr0 &= ~X86_CR0_TS;
5420 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5423 static int handle_cr(struct kvm_vcpu *vcpu)
5425 unsigned long exit_qualification, val;
5430 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5431 cr = exit_qualification & 15;
5432 reg = (exit_qualification >> 8) & 15;
5433 switch ((exit_qualification >> 4) & 3) {
5434 case 0: /* mov to cr */
5435 val = kvm_register_readl(vcpu, reg);
5436 trace_kvm_cr_write(cr, val);
5439 err = handle_set_cr0(vcpu, val);
5440 kvm_complete_insn_gp(vcpu, err);
5443 err = kvm_set_cr3(vcpu, val);
5444 kvm_complete_insn_gp(vcpu, err);
5447 err = handle_set_cr4(vcpu, val);
5448 kvm_complete_insn_gp(vcpu, err);
5451 u8 cr8_prev = kvm_get_cr8(vcpu);
5453 err = kvm_set_cr8(vcpu, cr8);
5454 kvm_complete_insn_gp(vcpu, err);
5455 if (lapic_in_kernel(vcpu))
5457 if (cr8_prev <= cr8)
5459 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5466 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5467 skip_emulated_instruction(vcpu);
5468 vmx_fpu_activate(vcpu);
5470 case 1: /*mov from cr*/
5473 val = kvm_read_cr3(vcpu);
5474 kvm_register_write(vcpu, reg, val);
5475 trace_kvm_cr_read(cr, val);
5476 skip_emulated_instruction(vcpu);
5479 val = kvm_get_cr8(vcpu);
5480 kvm_register_write(vcpu, reg, val);
5481 trace_kvm_cr_read(cr, val);
5482 skip_emulated_instruction(vcpu);
5487 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5488 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5489 kvm_lmsw(vcpu, val);
5491 skip_emulated_instruction(vcpu);
5496 vcpu->run->exit_reason = 0;
5497 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5498 (int)(exit_qualification >> 4) & 3, cr);
5502 static int handle_dr(struct kvm_vcpu *vcpu)
5504 unsigned long exit_qualification;
5507 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5508 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5510 /* First, if DR does not exist, trigger UD */
5511 if (!kvm_require_dr(vcpu, dr))
5514 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5515 if (!kvm_require_cpl(vcpu, 0))
5517 dr7 = vmcs_readl(GUEST_DR7);
5520 * As the vm-exit takes precedence over the debug trap, we
5521 * need to emulate the latter, either for the host or the
5522 * guest debugging itself.
5524 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5525 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5526 vcpu->run->debug.arch.dr7 = dr7;
5527 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5528 vcpu->run->debug.arch.exception = DB_VECTOR;
5529 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5532 vcpu->arch.dr6 &= ~15;
5533 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5534 kvm_queue_exception(vcpu, DB_VECTOR);
5539 if (vcpu->guest_debug == 0) {
5540 u32 cpu_based_vm_exec_control;
5542 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5543 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5544 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5547 * No more DR vmexits; force a reload of the debug registers
5548 * and reenter on this instruction. The next vmexit will
5549 * retrieve the full state of the debug registers.
5551 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5555 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5556 if (exit_qualification & TYPE_MOV_FROM_DR) {
5559 if (kvm_get_dr(vcpu, dr, &val))
5561 kvm_register_write(vcpu, reg, val);
5563 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5566 skip_emulated_instruction(vcpu);
5570 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5572 return vcpu->arch.dr6;
5575 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5579 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5581 u32 cpu_based_vm_exec_control;
5583 get_debugreg(vcpu->arch.db[0], 0);
5584 get_debugreg(vcpu->arch.db[1], 1);
5585 get_debugreg(vcpu->arch.db[2], 2);
5586 get_debugreg(vcpu->arch.db[3], 3);
5587 get_debugreg(vcpu->arch.dr6, 6);
5588 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5590 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5592 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5593 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5594 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5597 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5599 vmcs_writel(GUEST_DR7, val);
5602 static int handle_cpuid(struct kvm_vcpu *vcpu)
5604 kvm_emulate_cpuid(vcpu);
5608 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5610 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5611 struct msr_data msr_info;
5613 msr_info.index = ecx;
5614 msr_info.host_initiated = false;
5615 if (vmx_get_msr(vcpu, &msr_info)) {
5616 trace_kvm_msr_read_ex(ecx);
5617 kvm_inject_gp(vcpu, 0);
5621 trace_kvm_msr_read(ecx, msr_info.data);
5623 /* FIXME: handling of bits 32:63 of rax, rdx */
5624 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5625 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5626 skip_emulated_instruction(vcpu);
5630 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5632 struct msr_data msr;
5633 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5634 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5635 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5639 msr.host_initiated = false;
5640 if (kvm_set_msr(vcpu, &msr) != 0) {
5641 trace_kvm_msr_write_ex(ecx, data);
5642 kvm_inject_gp(vcpu, 0);
5646 trace_kvm_msr_write(ecx, data);
5647 skip_emulated_instruction(vcpu);
5651 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5653 kvm_make_request(KVM_REQ_EVENT, vcpu);
5657 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5659 u32 cpu_based_vm_exec_control;
5661 /* clear pending irq */
5662 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5663 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5664 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5666 kvm_make_request(KVM_REQ_EVENT, vcpu);
5668 ++vcpu->stat.irq_window_exits;
5672 static int handle_halt(struct kvm_vcpu *vcpu)
5674 return kvm_emulate_halt(vcpu);
5677 static int handle_vmcall(struct kvm_vcpu *vcpu)
5679 kvm_emulate_hypercall(vcpu);
5683 static int handle_invd(struct kvm_vcpu *vcpu)
5685 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5688 static int handle_invlpg(struct kvm_vcpu *vcpu)
5690 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5692 kvm_mmu_invlpg(vcpu, exit_qualification);
5693 skip_emulated_instruction(vcpu);
5697 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5701 err = kvm_rdpmc(vcpu);
5702 kvm_complete_insn_gp(vcpu, err);
5707 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5709 kvm_emulate_wbinvd(vcpu);
5713 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5715 u64 new_bv = kvm_read_edx_eax(vcpu);
5716 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5718 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5719 skip_emulated_instruction(vcpu);
5723 static int handle_xsaves(struct kvm_vcpu *vcpu)
5725 skip_emulated_instruction(vcpu);
5726 WARN(1, "this should never happen\n");
5730 static int handle_xrstors(struct kvm_vcpu *vcpu)
5732 skip_emulated_instruction(vcpu);
5733 WARN(1, "this should never happen\n");
5737 static int handle_apic_access(struct kvm_vcpu *vcpu)
5739 if (likely(fasteoi)) {
5740 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5741 int access_type, offset;
5743 access_type = exit_qualification & APIC_ACCESS_TYPE;
5744 offset = exit_qualification & APIC_ACCESS_OFFSET;
5746 * Sane guest uses MOV to write EOI, with written value
5747 * not cared. So make a short-circuit here by avoiding
5748 * heavy instruction emulation.
5750 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5751 (offset == APIC_EOI)) {
5752 kvm_lapic_set_eoi(vcpu);
5753 skip_emulated_instruction(vcpu);
5757 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5760 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5762 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5763 int vector = exit_qualification & 0xff;
5765 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5766 kvm_apic_set_eoi_accelerated(vcpu, vector);
5770 static int handle_apic_write(struct kvm_vcpu *vcpu)
5772 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5773 u32 offset = exit_qualification & 0xfff;
5775 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5776 kvm_apic_write_nodecode(vcpu, offset);
5780 static int handle_task_switch(struct kvm_vcpu *vcpu)
5782 struct vcpu_vmx *vmx = to_vmx(vcpu);
5783 unsigned long exit_qualification;
5784 bool has_error_code = false;
5787 int reason, type, idt_v, idt_index;
5789 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5790 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5791 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5793 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5795 reason = (u32)exit_qualification >> 30;
5796 if (reason == TASK_SWITCH_GATE && idt_v) {
5798 case INTR_TYPE_NMI_INTR:
5799 vcpu->arch.nmi_injected = false;
5800 vmx_set_nmi_mask(vcpu, true);
5802 case INTR_TYPE_EXT_INTR:
5803 case INTR_TYPE_SOFT_INTR:
5804 kvm_clear_interrupt_queue(vcpu);
5806 case INTR_TYPE_HARD_EXCEPTION:
5807 if (vmx->idt_vectoring_info &
5808 VECTORING_INFO_DELIVER_CODE_MASK) {
5809 has_error_code = true;
5811 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5814 case INTR_TYPE_SOFT_EXCEPTION:
5815 kvm_clear_exception_queue(vcpu);
5821 tss_selector = exit_qualification;
5823 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5824 type != INTR_TYPE_EXT_INTR &&
5825 type != INTR_TYPE_NMI_INTR))
5826 skip_emulated_instruction(vcpu);
5828 if (kvm_task_switch(vcpu, tss_selector,
5829 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5830 has_error_code, error_code) == EMULATE_FAIL) {
5831 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5832 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5833 vcpu->run->internal.ndata = 0;
5838 * TODO: What about debug traps on tss switch?
5839 * Are we supposed to inject them and update dr6?
5845 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5847 unsigned long exit_qualification;
5852 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5854 gla_validity = (exit_qualification >> 7) & 0x3;
5855 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5856 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5857 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5858 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5859 vmcs_readl(GUEST_LINEAR_ADDRESS));
5860 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5861 (long unsigned int)exit_qualification);
5862 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5863 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5868 * EPT violation happened while executing iret from NMI,
5869 * "blocked by NMI" bit has to be set before next VM entry.
5870 * There are errata that may cause this bit to not be set:
5873 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5874 cpu_has_virtual_nmis() &&
5875 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5876 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5878 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5879 trace_kvm_page_fault(gpa, exit_qualification);
5881 /* It is a write fault? */
5882 error_code = exit_qualification & PFERR_WRITE_MASK;
5883 /* It is a fetch fault? */
5884 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5885 /* ept page table is present? */
5886 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5888 vcpu->arch.exit_qualification = exit_qualification;
5890 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5893 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5898 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5899 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5900 skip_emulated_instruction(vcpu);
5901 trace_kvm_fast_mmio(gpa);
5905 ret = handle_mmio_page_fault(vcpu, gpa, true);
5906 if (likely(ret == RET_MMIO_PF_EMULATE))
5907 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5910 if (unlikely(ret == RET_MMIO_PF_INVALID))
5911 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5913 if (unlikely(ret == RET_MMIO_PF_RETRY))
5916 /* It is the real ept misconfig */
5919 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5920 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5925 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5927 u32 cpu_based_vm_exec_control;
5929 /* clear pending NMI */
5930 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5931 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5932 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5933 ++vcpu->stat.nmi_window_exits;
5934 kvm_make_request(KVM_REQ_EVENT, vcpu);
5939 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5941 struct vcpu_vmx *vmx = to_vmx(vcpu);
5942 enum emulation_result err = EMULATE_DONE;
5945 bool intr_window_requested;
5946 unsigned count = 130;
5948 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5949 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5951 while (vmx->emulation_required && count-- != 0) {
5952 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5953 return handle_interrupt_window(&vmx->vcpu);
5955 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5958 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5960 if (err == EMULATE_USER_EXIT) {
5961 ++vcpu->stat.mmio_exits;
5966 if (err != EMULATE_DONE) {
5967 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5968 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5969 vcpu->run->internal.ndata = 0;
5973 if (vcpu->arch.halt_request) {
5974 vcpu->arch.halt_request = 0;
5975 ret = kvm_vcpu_halt(vcpu);
5979 if (signal_pending(current))
5989 static int __grow_ple_window(int val)
5991 if (ple_window_grow < 1)
5994 val = min(val, ple_window_actual_max);
5996 if (ple_window_grow < ple_window)
5997 val *= ple_window_grow;
5999 val += ple_window_grow;
6004 static int __shrink_ple_window(int val, int modifier, int minimum)
6009 if (modifier < ple_window)
6014 return max(val, minimum);
6017 static void grow_ple_window(struct kvm_vcpu *vcpu)
6019 struct vcpu_vmx *vmx = to_vmx(vcpu);
6020 int old = vmx->ple_window;
6022 vmx->ple_window = __grow_ple_window(old);
6024 if (vmx->ple_window != old)
6025 vmx->ple_window_dirty = true;
6027 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6030 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6032 struct vcpu_vmx *vmx = to_vmx(vcpu);
6033 int old = vmx->ple_window;
6035 vmx->ple_window = __shrink_ple_window(old,
6036 ple_window_shrink, ple_window);
6038 if (vmx->ple_window != old)
6039 vmx->ple_window_dirty = true;
6041 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6045 * ple_window_actual_max is computed to be one grow_ple_window() below
6046 * ple_window_max. (See __grow_ple_window for the reason.)
6047 * This prevents overflows, because ple_window_max is int.
6048 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6050 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6052 static void update_ple_window_actual_max(void)
6054 ple_window_actual_max =
6055 __shrink_ple_window(max(ple_window_max, ple_window),
6056 ple_window_grow, INT_MIN);
6060 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6062 static void wakeup_handler(void)
6064 struct kvm_vcpu *vcpu;
6065 int cpu = smp_processor_id();
6067 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6068 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6069 blocked_vcpu_list) {
6070 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6072 if (pi_test_on(pi_desc) == 1)
6073 kvm_vcpu_kick(vcpu);
6075 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6078 static __init int hardware_setup(void)
6080 int r = -ENOMEM, i, msr;
6082 rdmsrl_safe(MSR_EFER, &host_efer);
6084 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6085 kvm_define_shared_msr(i, vmx_msr_index[i]);
6087 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6088 if (!vmx_io_bitmap_a)
6091 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6092 if (!vmx_io_bitmap_b)
6095 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6096 if (!vmx_msr_bitmap_legacy)
6099 vmx_msr_bitmap_legacy_x2apic =
6100 (unsigned long *)__get_free_page(GFP_KERNEL);
6101 if (!vmx_msr_bitmap_legacy_x2apic)
6104 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6105 if (!vmx_msr_bitmap_longmode)
6108 vmx_msr_bitmap_longmode_x2apic =
6109 (unsigned long *)__get_free_page(GFP_KERNEL);
6110 if (!vmx_msr_bitmap_longmode_x2apic)
6114 vmx_msr_bitmap_nested =
6115 (unsigned long *)__get_free_page(GFP_KERNEL);
6116 if (!vmx_msr_bitmap_nested)
6120 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6121 if (!vmx_vmread_bitmap)
6124 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6125 if (!vmx_vmwrite_bitmap)
6128 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6129 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6132 * Allow direct access to the PC debug port (it is often used for I/O
6133 * delays, but the vmexits simply slow things down).
6135 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6136 clear_bit(0x80, vmx_io_bitmap_a);
6138 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6140 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6141 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6143 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6145 if (setup_vmcs_config(&vmcs_config) < 0) {
6150 if (boot_cpu_has(X86_FEATURE_NX))
6151 kvm_enable_efer_bits(EFER_NX);
6153 if (!cpu_has_vmx_vpid())
6155 if (!cpu_has_vmx_shadow_vmcs())
6156 enable_shadow_vmcs = 0;
6157 if (enable_shadow_vmcs)
6158 init_vmcs_shadow_fields();
6160 if (!cpu_has_vmx_ept() ||
6161 !cpu_has_vmx_ept_4levels()) {
6163 enable_unrestricted_guest = 0;
6164 enable_ept_ad_bits = 0;
6167 if (!cpu_has_vmx_ept_ad_bits())
6168 enable_ept_ad_bits = 0;
6170 if (!cpu_has_vmx_unrestricted_guest())
6171 enable_unrestricted_guest = 0;
6173 if (!cpu_has_vmx_flexpriority())
6174 flexpriority_enabled = 0;
6177 * set_apic_access_page_addr() is used to reload apic access
6178 * page upon invalidation. No need to do anything if not
6179 * using the APIC_ACCESS_ADDR VMCS field.
6181 if (!flexpriority_enabled)
6182 kvm_x86_ops->set_apic_access_page_addr = NULL;
6184 if (!cpu_has_vmx_tpr_shadow())
6185 kvm_x86_ops->update_cr8_intercept = NULL;
6187 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6188 kvm_disable_largepages();
6190 if (!cpu_has_vmx_ple())
6193 if (!cpu_has_vmx_apicv())
6196 if (cpu_has_vmx_tsc_scaling()) {
6197 kvm_has_tsc_control = true;
6198 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6199 kvm_tsc_scaling_ratio_frac_bits = 48;
6203 kvm_x86_ops->update_cr8_intercept = NULL;
6205 kvm_x86_ops->hwapic_irr_update = NULL;
6206 kvm_x86_ops->hwapic_isr_update = NULL;
6207 kvm_x86_ops->deliver_posted_interrupt = NULL;
6208 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6211 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6212 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6213 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6214 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6215 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6216 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6217 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6219 memcpy(vmx_msr_bitmap_legacy_x2apic,
6220 vmx_msr_bitmap_legacy, PAGE_SIZE);
6221 memcpy(vmx_msr_bitmap_longmode_x2apic,
6222 vmx_msr_bitmap_longmode, PAGE_SIZE);
6224 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6227 for (msr = 0x800; msr <= 0x8ff; msr++)
6228 vmx_disable_intercept_msr_read_x2apic(msr);
6230 /* According SDM, in x2apic mode, the whole id reg is used.
6231 * But in KVM, it only use the highest eight bits. Need to
6233 vmx_enable_intercept_msr_read_x2apic(0x802);
6235 vmx_enable_intercept_msr_read_x2apic(0x839);
6237 vmx_disable_intercept_msr_write_x2apic(0x808);
6239 vmx_disable_intercept_msr_write_x2apic(0x80b);
6241 vmx_disable_intercept_msr_write_x2apic(0x83f);
6245 kvm_mmu_set_mask_ptes(0ull,
6246 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6247 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6248 0ull, VMX_EPT_EXECUTABLE_MASK);
6249 ept_set_mmio_spte_mask();
6254 update_ple_window_actual_max();
6257 * Only enable PML when hardware supports PML feature, and both EPT
6258 * and EPT A/D bit features are enabled -- PML depends on them to work.
6260 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6264 kvm_x86_ops->slot_enable_log_dirty = NULL;
6265 kvm_x86_ops->slot_disable_log_dirty = NULL;
6266 kvm_x86_ops->flush_log_dirty = NULL;
6267 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6270 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6272 return alloc_kvm_area();
6275 free_page((unsigned long)vmx_vmwrite_bitmap);
6277 free_page((unsigned long)vmx_vmread_bitmap);
6280 free_page((unsigned long)vmx_msr_bitmap_nested);
6282 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6284 free_page((unsigned long)vmx_msr_bitmap_longmode);
6286 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6288 free_page((unsigned long)vmx_msr_bitmap_legacy);
6290 free_page((unsigned long)vmx_io_bitmap_b);
6292 free_page((unsigned long)vmx_io_bitmap_a);
6297 static __exit void hardware_unsetup(void)
6299 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6300 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6301 free_page((unsigned long)vmx_msr_bitmap_legacy);
6302 free_page((unsigned long)vmx_msr_bitmap_longmode);
6303 free_page((unsigned long)vmx_io_bitmap_b);
6304 free_page((unsigned long)vmx_io_bitmap_a);
6305 free_page((unsigned long)vmx_vmwrite_bitmap);
6306 free_page((unsigned long)vmx_vmread_bitmap);
6308 free_page((unsigned long)vmx_msr_bitmap_nested);
6314 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6315 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6317 static int handle_pause(struct kvm_vcpu *vcpu)
6320 grow_ple_window(vcpu);
6322 skip_emulated_instruction(vcpu);
6323 kvm_vcpu_on_spin(vcpu);
6328 static int handle_nop(struct kvm_vcpu *vcpu)
6330 skip_emulated_instruction(vcpu);
6334 static int handle_mwait(struct kvm_vcpu *vcpu)
6336 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6337 return handle_nop(vcpu);
6340 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6345 static int handle_monitor(struct kvm_vcpu *vcpu)
6347 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6348 return handle_nop(vcpu);
6352 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6353 * We could reuse a single VMCS for all the L2 guests, but we also want the
6354 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6355 * allows keeping them loaded on the processor, and in the future will allow
6356 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6357 * every entry if they never change.
6358 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6359 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6361 * The following functions allocate and free a vmcs02 in this pool.
6364 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6365 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6367 struct vmcs02_list *item;
6368 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6369 if (item->vmptr == vmx->nested.current_vmptr) {
6370 list_move(&item->list, &vmx->nested.vmcs02_pool);
6371 return &item->vmcs02;
6374 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6375 /* Recycle the least recently used VMCS. */
6376 item = list_entry(vmx->nested.vmcs02_pool.prev,
6377 struct vmcs02_list, list);
6378 item->vmptr = vmx->nested.current_vmptr;
6379 list_move(&item->list, &vmx->nested.vmcs02_pool);
6380 return &item->vmcs02;
6383 /* Create a new VMCS */
6384 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6387 item->vmcs02.vmcs = alloc_vmcs();
6388 if (!item->vmcs02.vmcs) {
6392 loaded_vmcs_init(&item->vmcs02);
6393 item->vmptr = vmx->nested.current_vmptr;
6394 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6395 vmx->nested.vmcs02_num++;
6396 return &item->vmcs02;
6399 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6400 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6402 struct vmcs02_list *item;
6403 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6404 if (item->vmptr == vmptr) {
6405 free_loaded_vmcs(&item->vmcs02);
6406 list_del(&item->list);
6408 vmx->nested.vmcs02_num--;
6414 * Free all VMCSs saved for this vcpu, except the one pointed by
6415 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6416 * must be &vmx->vmcs01.
6418 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6420 struct vmcs02_list *item, *n;
6422 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6423 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6425 * Something will leak if the above WARN triggers. Better than
6428 if (vmx->loaded_vmcs == &item->vmcs02)
6431 free_loaded_vmcs(&item->vmcs02);
6432 list_del(&item->list);
6434 vmx->nested.vmcs02_num--;
6439 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6440 * set the success or error code of an emulated VMX instruction, as specified
6441 * by Vol 2B, VMX Instruction Reference, "Conventions".
6443 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6445 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6446 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6447 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6450 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6452 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6453 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6454 X86_EFLAGS_SF | X86_EFLAGS_OF))
6458 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6459 u32 vm_instruction_error)
6461 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6463 * failValid writes the error number to the current VMCS, which
6464 * can't be done there isn't a current VMCS.
6466 nested_vmx_failInvalid(vcpu);
6469 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6470 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6471 X86_EFLAGS_SF | X86_EFLAGS_OF))
6473 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6475 * We don't need to force a shadow sync because
6476 * VM_INSTRUCTION_ERROR is not shadowed
6480 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6482 /* TODO: not to reset guest simply here. */
6483 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6484 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6487 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6489 struct vcpu_vmx *vmx =
6490 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6492 vmx->nested.preemption_timer_expired = true;
6493 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6494 kvm_vcpu_kick(&vmx->vcpu);
6496 return HRTIMER_NORESTART;
6500 * Decode the memory-address operand of a vmx instruction, as recorded on an
6501 * exit caused by such an instruction (run by a guest hypervisor).
6502 * On success, returns 0. When the operand is invalid, returns 1 and throws
6505 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6506 unsigned long exit_qualification,
6507 u32 vmx_instruction_info, bool wr, gva_t *ret)
6511 struct kvm_segment s;
6514 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6515 * Execution", on an exit, vmx_instruction_info holds most of the
6516 * addressing components of the operand. Only the displacement part
6517 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6518 * For how an actual address is calculated from all these components,
6519 * refer to Vol. 1, "Operand Addressing".
6521 int scaling = vmx_instruction_info & 3;
6522 int addr_size = (vmx_instruction_info >> 7) & 7;
6523 bool is_reg = vmx_instruction_info & (1u << 10);
6524 int seg_reg = (vmx_instruction_info >> 15) & 7;
6525 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6526 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6527 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6528 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6531 kvm_queue_exception(vcpu, UD_VECTOR);
6535 /* Addr = segment_base + offset */
6536 /* offset = base + [index * scale] + displacement */
6537 off = exit_qualification; /* holds the displacement */
6539 off += kvm_register_read(vcpu, base_reg);
6541 off += kvm_register_read(vcpu, index_reg)<<scaling;
6542 vmx_get_segment(vcpu, &s, seg_reg);
6543 *ret = s.base + off;
6545 if (addr_size == 1) /* 32 bit */
6548 /* Checks for #GP/#SS exceptions. */
6550 if (is_protmode(vcpu)) {
6551 /* Protected mode: apply checks for segment validity in the
6553 * - segment type check (#GP(0) may be thrown)
6554 * - usability check (#GP(0)/#SS(0))
6555 * - limit check (#GP(0)/#SS(0))
6558 /* #GP(0) if the destination operand is located in a
6559 * read-only data segment or any code segment.
6561 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6563 /* #GP(0) if the source operand is located in an
6564 * execute-only code segment
6566 exn = ((s.type & 0xa) == 8);
6569 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6572 if (is_long_mode(vcpu)) {
6573 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6574 * non-canonical form. This is an only check for long mode.
6576 exn = is_noncanonical_address(*ret);
6577 } else if (is_protmode(vcpu)) {
6578 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6580 exn = (s.unusable != 0);
6581 /* Protected mode: #GP(0)/#SS(0) if the memory
6582 * operand is outside the segment limit.
6584 exn = exn || (off + sizeof(u64) > s.limit);
6587 kvm_queue_exception_e(vcpu,
6588 seg_reg == VCPU_SREG_SS ?
6589 SS_VECTOR : GP_VECTOR,
6598 * This function performs the various checks including
6599 * - if it's 4KB aligned
6600 * - No bits beyond the physical address width are set
6601 * - Returns 0 on success or else 1
6602 * (Intel SDM Section 30.3)
6604 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6609 struct x86_exception e;
6611 struct vcpu_vmx *vmx = to_vmx(vcpu);
6612 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6614 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6615 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6618 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6619 sizeof(vmptr), &e)) {
6620 kvm_inject_page_fault(vcpu, &e);
6624 switch (exit_reason) {
6625 case EXIT_REASON_VMON:
6628 * The first 4 bytes of VMXON region contain the supported
6629 * VMCS revision identifier
6631 * Note - IA32_VMX_BASIC[48] will never be 1
6632 * for the nested case;
6633 * which replaces physical address width with 32
6636 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6637 nested_vmx_failInvalid(vcpu);
6638 skip_emulated_instruction(vcpu);
6642 page = nested_get_page(vcpu, vmptr);
6644 *(u32 *)kmap(page) != VMCS12_REVISION) {
6645 nested_vmx_failInvalid(vcpu);
6647 skip_emulated_instruction(vcpu);
6651 vmx->nested.vmxon_ptr = vmptr;
6653 case EXIT_REASON_VMCLEAR:
6654 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6655 nested_vmx_failValid(vcpu,
6656 VMXERR_VMCLEAR_INVALID_ADDRESS);
6657 skip_emulated_instruction(vcpu);
6661 if (vmptr == vmx->nested.vmxon_ptr) {
6662 nested_vmx_failValid(vcpu,
6663 VMXERR_VMCLEAR_VMXON_POINTER);
6664 skip_emulated_instruction(vcpu);
6668 case EXIT_REASON_VMPTRLD:
6669 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6670 nested_vmx_failValid(vcpu,
6671 VMXERR_VMPTRLD_INVALID_ADDRESS);
6672 skip_emulated_instruction(vcpu);
6676 if (vmptr == vmx->nested.vmxon_ptr) {
6677 nested_vmx_failValid(vcpu,
6678 VMXERR_VMCLEAR_VMXON_POINTER);
6679 skip_emulated_instruction(vcpu);
6684 return 1; /* shouldn't happen */
6693 * Emulate the VMXON instruction.
6694 * Currently, we just remember that VMX is active, and do not save or even
6695 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6696 * do not currently need to store anything in that guest-allocated memory
6697 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6698 * argument is different from the VMXON pointer (which the spec says they do).
6700 static int handle_vmon(struct kvm_vcpu *vcpu)
6702 struct kvm_segment cs;
6703 struct vcpu_vmx *vmx = to_vmx(vcpu);
6704 struct vmcs *shadow_vmcs;
6705 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6706 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6708 /* The Intel VMX Instruction Reference lists a bunch of bits that
6709 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6710 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6711 * Otherwise, we should fail with #UD. We test these now:
6713 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6714 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6715 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6716 kvm_queue_exception(vcpu, UD_VECTOR);
6720 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6721 if (is_long_mode(vcpu) && !cs.l) {
6722 kvm_queue_exception(vcpu, UD_VECTOR);
6726 if (vmx_get_cpl(vcpu)) {
6727 kvm_inject_gp(vcpu, 0);
6731 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6734 if (vmx->nested.vmxon) {
6735 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6736 skip_emulated_instruction(vcpu);
6740 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6741 != VMXON_NEEDED_FEATURES) {
6742 kvm_inject_gp(vcpu, 0);
6746 if (enable_shadow_vmcs) {
6747 shadow_vmcs = alloc_vmcs();
6750 /* mark vmcs as shadow */
6751 shadow_vmcs->revision_id |= (1u << 31);
6752 /* init shadow vmcs */
6753 vmcs_clear(shadow_vmcs);
6754 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6757 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6758 vmx->nested.vmcs02_num = 0;
6760 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6762 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6764 vmx->nested.vmxon = true;
6766 skip_emulated_instruction(vcpu);
6767 nested_vmx_succeed(vcpu);
6772 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6773 * for running VMX instructions (except VMXON, whose prerequisites are
6774 * slightly different). It also specifies what exception to inject otherwise.
6776 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6778 struct kvm_segment cs;
6779 struct vcpu_vmx *vmx = to_vmx(vcpu);
6781 if (!vmx->nested.vmxon) {
6782 kvm_queue_exception(vcpu, UD_VECTOR);
6786 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6787 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6788 (is_long_mode(vcpu) && !cs.l)) {
6789 kvm_queue_exception(vcpu, UD_VECTOR);
6793 if (vmx_get_cpl(vcpu)) {
6794 kvm_inject_gp(vcpu, 0);
6801 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6803 if (vmx->nested.current_vmptr == -1ull)
6806 /* current_vmptr and current_vmcs12 are always set/reset together */
6807 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6810 if (enable_shadow_vmcs) {
6811 /* copy to memory all shadowed fields in case
6812 they were modified */
6813 copy_shadow_to_vmcs12(vmx);
6814 vmx->nested.sync_shadow_vmcs = false;
6815 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6816 SECONDARY_EXEC_SHADOW_VMCS);
6817 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6819 vmx->nested.posted_intr_nv = -1;
6820 kunmap(vmx->nested.current_vmcs12_page);
6821 nested_release_page(vmx->nested.current_vmcs12_page);
6822 vmx->nested.current_vmptr = -1ull;
6823 vmx->nested.current_vmcs12 = NULL;
6827 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6828 * just stops using VMX.
6830 static void free_nested(struct vcpu_vmx *vmx)
6832 if (!vmx->nested.vmxon)
6835 vmx->nested.vmxon = false;
6836 free_vpid(vmx->nested.vpid02);
6837 nested_release_vmcs12(vmx);
6838 if (enable_shadow_vmcs)
6839 free_vmcs(vmx->nested.current_shadow_vmcs);
6840 /* Unpin physical memory we referred to in current vmcs02 */
6841 if (vmx->nested.apic_access_page) {
6842 nested_release_page(vmx->nested.apic_access_page);
6843 vmx->nested.apic_access_page = NULL;
6845 if (vmx->nested.virtual_apic_page) {
6846 nested_release_page(vmx->nested.virtual_apic_page);
6847 vmx->nested.virtual_apic_page = NULL;
6849 if (vmx->nested.pi_desc_page) {
6850 kunmap(vmx->nested.pi_desc_page);
6851 nested_release_page(vmx->nested.pi_desc_page);
6852 vmx->nested.pi_desc_page = NULL;
6853 vmx->nested.pi_desc = NULL;
6856 nested_free_all_saved_vmcss(vmx);
6859 /* Emulate the VMXOFF instruction */
6860 static int handle_vmoff(struct kvm_vcpu *vcpu)
6862 if (!nested_vmx_check_permission(vcpu))
6864 free_nested(to_vmx(vcpu));
6865 skip_emulated_instruction(vcpu);
6866 nested_vmx_succeed(vcpu);
6870 /* Emulate the VMCLEAR instruction */
6871 static int handle_vmclear(struct kvm_vcpu *vcpu)
6873 struct vcpu_vmx *vmx = to_vmx(vcpu);
6875 struct vmcs12 *vmcs12;
6878 if (!nested_vmx_check_permission(vcpu))
6881 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6884 if (vmptr == vmx->nested.current_vmptr)
6885 nested_release_vmcs12(vmx);
6887 page = nested_get_page(vcpu, vmptr);
6890 * For accurate processor emulation, VMCLEAR beyond available
6891 * physical memory should do nothing at all. However, it is
6892 * possible that a nested vmx bug, not a guest hypervisor bug,
6893 * resulted in this case, so let's shut down before doing any
6896 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6899 vmcs12 = kmap(page);
6900 vmcs12->launch_state = 0;
6902 nested_release_page(page);
6904 nested_free_vmcs02(vmx, vmptr);
6906 skip_emulated_instruction(vcpu);
6907 nested_vmx_succeed(vcpu);
6911 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6913 /* Emulate the VMLAUNCH instruction */
6914 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6916 return nested_vmx_run(vcpu, true);
6919 /* Emulate the VMRESUME instruction */
6920 static int handle_vmresume(struct kvm_vcpu *vcpu)
6923 return nested_vmx_run(vcpu, false);
6926 enum vmcs_field_type {
6927 VMCS_FIELD_TYPE_U16 = 0,
6928 VMCS_FIELD_TYPE_U64 = 1,
6929 VMCS_FIELD_TYPE_U32 = 2,
6930 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6933 static inline int vmcs_field_type(unsigned long field)
6935 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6936 return VMCS_FIELD_TYPE_U32;
6937 return (field >> 13) & 0x3 ;
6940 static inline int vmcs_field_readonly(unsigned long field)
6942 return (((field >> 10) & 0x3) == 1);
6946 * Read a vmcs12 field. Since these can have varying lengths and we return
6947 * one type, we chose the biggest type (u64) and zero-extend the return value
6948 * to that size. Note that the caller, handle_vmread, might need to use only
6949 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6950 * 64-bit fields are to be returned).
6952 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6953 unsigned long field, u64 *ret)
6955 short offset = vmcs_field_to_offset(field);
6961 p = ((char *)(get_vmcs12(vcpu))) + offset;
6963 switch (vmcs_field_type(field)) {
6964 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6965 *ret = *((natural_width *)p);
6967 case VMCS_FIELD_TYPE_U16:
6970 case VMCS_FIELD_TYPE_U32:
6973 case VMCS_FIELD_TYPE_U64:
6983 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6984 unsigned long field, u64 field_value){
6985 short offset = vmcs_field_to_offset(field);
6986 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6990 switch (vmcs_field_type(field)) {
6991 case VMCS_FIELD_TYPE_U16:
6992 *(u16 *)p = field_value;
6994 case VMCS_FIELD_TYPE_U32:
6995 *(u32 *)p = field_value;
6997 case VMCS_FIELD_TYPE_U64:
6998 *(u64 *)p = field_value;
7000 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7001 *(natural_width *)p = field_value;
7010 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7013 unsigned long field;
7015 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7016 const unsigned long *fields = shadow_read_write_fields;
7017 const int num_fields = max_shadow_read_write_fields;
7021 vmcs_load(shadow_vmcs);
7023 for (i = 0; i < num_fields; i++) {
7025 switch (vmcs_field_type(field)) {
7026 case VMCS_FIELD_TYPE_U16:
7027 field_value = vmcs_read16(field);
7029 case VMCS_FIELD_TYPE_U32:
7030 field_value = vmcs_read32(field);
7032 case VMCS_FIELD_TYPE_U64:
7033 field_value = vmcs_read64(field);
7035 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7036 field_value = vmcs_readl(field);
7042 vmcs12_write_any(&vmx->vcpu, field, field_value);
7045 vmcs_clear(shadow_vmcs);
7046 vmcs_load(vmx->loaded_vmcs->vmcs);
7051 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7053 const unsigned long *fields[] = {
7054 shadow_read_write_fields,
7055 shadow_read_only_fields
7057 const int max_fields[] = {
7058 max_shadow_read_write_fields,
7059 max_shadow_read_only_fields
7062 unsigned long field;
7063 u64 field_value = 0;
7064 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7066 vmcs_load(shadow_vmcs);
7068 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7069 for (i = 0; i < max_fields[q]; i++) {
7070 field = fields[q][i];
7071 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7073 switch (vmcs_field_type(field)) {
7074 case VMCS_FIELD_TYPE_U16:
7075 vmcs_write16(field, (u16)field_value);
7077 case VMCS_FIELD_TYPE_U32:
7078 vmcs_write32(field, (u32)field_value);
7080 case VMCS_FIELD_TYPE_U64:
7081 vmcs_write64(field, (u64)field_value);
7083 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7084 vmcs_writel(field, (long)field_value);
7093 vmcs_clear(shadow_vmcs);
7094 vmcs_load(vmx->loaded_vmcs->vmcs);
7098 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7099 * used before) all generate the same failure when it is missing.
7101 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7103 struct vcpu_vmx *vmx = to_vmx(vcpu);
7104 if (vmx->nested.current_vmptr == -1ull) {
7105 nested_vmx_failInvalid(vcpu);
7106 skip_emulated_instruction(vcpu);
7112 static int handle_vmread(struct kvm_vcpu *vcpu)
7114 unsigned long field;
7116 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7117 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7120 if (!nested_vmx_check_permission(vcpu) ||
7121 !nested_vmx_check_vmcs12(vcpu))
7124 /* Decode instruction info and find the field to read */
7125 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7126 /* Read the field, zero-extended to a u64 field_value */
7127 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7128 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7129 skip_emulated_instruction(vcpu);
7133 * Now copy part of this value to register or memory, as requested.
7134 * Note that the number of bits actually copied is 32 or 64 depending
7135 * on the guest's mode (32 or 64 bit), not on the given field's length.
7137 if (vmx_instruction_info & (1u << 10)) {
7138 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7141 if (get_vmx_mem_address(vcpu, exit_qualification,
7142 vmx_instruction_info, true, &gva))
7144 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7145 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7146 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7149 nested_vmx_succeed(vcpu);
7150 skip_emulated_instruction(vcpu);
7155 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7157 unsigned long field;
7159 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7160 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7161 /* The value to write might be 32 or 64 bits, depending on L1's long
7162 * mode, and eventually we need to write that into a field of several
7163 * possible lengths. The code below first zero-extends the value to 64
7164 * bit (field_value), and then copies only the approriate number of
7165 * bits into the vmcs12 field.
7167 u64 field_value = 0;
7168 struct x86_exception e;
7170 if (!nested_vmx_check_permission(vcpu) ||
7171 !nested_vmx_check_vmcs12(vcpu))
7174 if (vmx_instruction_info & (1u << 10))
7175 field_value = kvm_register_readl(vcpu,
7176 (((vmx_instruction_info) >> 3) & 0xf));
7178 if (get_vmx_mem_address(vcpu, exit_qualification,
7179 vmx_instruction_info, false, &gva))
7181 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7182 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7183 kvm_inject_page_fault(vcpu, &e);
7189 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7190 if (vmcs_field_readonly(field)) {
7191 nested_vmx_failValid(vcpu,
7192 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7193 skip_emulated_instruction(vcpu);
7197 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7198 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7199 skip_emulated_instruction(vcpu);
7203 nested_vmx_succeed(vcpu);
7204 skip_emulated_instruction(vcpu);
7208 /* Emulate the VMPTRLD instruction */
7209 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7211 struct vcpu_vmx *vmx = to_vmx(vcpu);
7214 if (!nested_vmx_check_permission(vcpu))
7217 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7220 if (vmx->nested.current_vmptr != vmptr) {
7221 struct vmcs12 *new_vmcs12;
7223 page = nested_get_page(vcpu, vmptr);
7225 nested_vmx_failInvalid(vcpu);
7226 skip_emulated_instruction(vcpu);
7229 new_vmcs12 = kmap(page);
7230 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7232 nested_release_page_clean(page);
7233 nested_vmx_failValid(vcpu,
7234 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7235 skip_emulated_instruction(vcpu);
7239 nested_release_vmcs12(vmx);
7240 vmx->nested.current_vmptr = vmptr;
7241 vmx->nested.current_vmcs12 = new_vmcs12;
7242 vmx->nested.current_vmcs12_page = page;
7243 if (enable_shadow_vmcs) {
7244 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7245 SECONDARY_EXEC_SHADOW_VMCS);
7246 vmcs_write64(VMCS_LINK_POINTER,
7247 __pa(vmx->nested.current_shadow_vmcs));
7248 vmx->nested.sync_shadow_vmcs = true;
7252 nested_vmx_succeed(vcpu);
7253 skip_emulated_instruction(vcpu);
7257 /* Emulate the VMPTRST instruction */
7258 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7260 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7261 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7263 struct x86_exception e;
7265 if (!nested_vmx_check_permission(vcpu))
7268 if (get_vmx_mem_address(vcpu, exit_qualification,
7269 vmx_instruction_info, true, &vmcs_gva))
7271 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7272 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7273 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7275 kvm_inject_page_fault(vcpu, &e);
7278 nested_vmx_succeed(vcpu);
7279 skip_emulated_instruction(vcpu);
7283 /* Emulate the INVEPT instruction */
7284 static int handle_invept(struct kvm_vcpu *vcpu)
7286 struct vcpu_vmx *vmx = to_vmx(vcpu);
7287 u32 vmx_instruction_info, types;
7290 struct x86_exception e;
7295 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7296 SECONDARY_EXEC_ENABLE_EPT) ||
7297 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7298 kvm_queue_exception(vcpu, UD_VECTOR);
7302 if (!nested_vmx_check_permission(vcpu))
7305 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7306 kvm_queue_exception(vcpu, UD_VECTOR);
7310 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7311 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7313 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7315 if (!(types & (1UL << type))) {
7316 nested_vmx_failValid(vcpu,
7317 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7321 /* According to the Intel VMX instruction reference, the memory
7322 * operand is read even if it isn't needed (e.g., for type==global)
7324 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7325 vmx_instruction_info, false, &gva))
7327 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7328 sizeof(operand), &e)) {
7329 kvm_inject_page_fault(vcpu, &e);
7334 case VMX_EPT_EXTENT_GLOBAL:
7335 kvm_mmu_sync_roots(vcpu);
7336 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7337 nested_vmx_succeed(vcpu);
7340 /* Trap single context invalidation invept calls */
7345 skip_emulated_instruction(vcpu);
7349 static int handle_invvpid(struct kvm_vcpu *vcpu)
7351 struct vcpu_vmx *vmx = to_vmx(vcpu);
7352 u32 vmx_instruction_info;
7353 unsigned long type, types;
7355 struct x86_exception e;
7358 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7359 SECONDARY_EXEC_ENABLE_VPID) ||
7360 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7361 kvm_queue_exception(vcpu, UD_VECTOR);
7365 if (!nested_vmx_check_permission(vcpu))
7368 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7369 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7371 types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7373 if (!(types & (1UL << type))) {
7374 nested_vmx_failValid(vcpu,
7375 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7379 /* according to the intel vmx instruction reference, the memory
7380 * operand is read even if it isn't needed (e.g., for type==global)
7382 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7383 vmx_instruction_info, false, &gva))
7385 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7387 kvm_inject_page_fault(vcpu, &e);
7392 case VMX_VPID_EXTENT_ALL_CONTEXT:
7393 if (get_vmcs12(vcpu)->virtual_processor_id == 0) {
7394 nested_vmx_failValid(vcpu,
7395 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7398 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7399 nested_vmx_succeed(vcpu);
7402 /* Trap single context invalidation invvpid calls */
7407 skip_emulated_instruction(vcpu);
7411 static int handle_pml_full(struct kvm_vcpu *vcpu)
7413 unsigned long exit_qualification;
7415 trace_kvm_pml_full(vcpu->vcpu_id);
7417 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7420 * PML buffer FULL happened while executing iret from NMI,
7421 * "blocked by NMI" bit has to be set before next VM entry.
7423 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7424 cpu_has_virtual_nmis() &&
7425 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7426 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7427 GUEST_INTR_STATE_NMI);
7430 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7431 * here.., and there's no userspace involvement needed for PML.
7436 static int handle_pcommit(struct kvm_vcpu *vcpu)
7438 /* we never catch pcommit instruct for L1 guest. */
7444 * The exit handlers return 1 if the exit was handled fully and guest execution
7445 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7446 * to be done to userspace and return 0.
7448 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7449 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7450 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7451 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7452 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7453 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7454 [EXIT_REASON_CR_ACCESS] = handle_cr,
7455 [EXIT_REASON_DR_ACCESS] = handle_dr,
7456 [EXIT_REASON_CPUID] = handle_cpuid,
7457 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7458 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7459 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7460 [EXIT_REASON_HLT] = handle_halt,
7461 [EXIT_REASON_INVD] = handle_invd,
7462 [EXIT_REASON_INVLPG] = handle_invlpg,
7463 [EXIT_REASON_RDPMC] = handle_rdpmc,
7464 [EXIT_REASON_VMCALL] = handle_vmcall,
7465 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7466 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7467 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7468 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7469 [EXIT_REASON_VMREAD] = handle_vmread,
7470 [EXIT_REASON_VMRESUME] = handle_vmresume,
7471 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7472 [EXIT_REASON_VMOFF] = handle_vmoff,
7473 [EXIT_REASON_VMON] = handle_vmon,
7474 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7475 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7476 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7477 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7478 [EXIT_REASON_WBINVD] = handle_wbinvd,
7479 [EXIT_REASON_XSETBV] = handle_xsetbv,
7480 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7481 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7482 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7483 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7484 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7485 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7486 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7487 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7488 [EXIT_REASON_INVEPT] = handle_invept,
7489 [EXIT_REASON_INVVPID] = handle_invvpid,
7490 [EXIT_REASON_XSAVES] = handle_xsaves,
7491 [EXIT_REASON_XRSTORS] = handle_xrstors,
7492 [EXIT_REASON_PML_FULL] = handle_pml_full,
7493 [EXIT_REASON_PCOMMIT] = handle_pcommit,
7496 static const int kvm_vmx_max_exit_handlers =
7497 ARRAY_SIZE(kvm_vmx_exit_handlers);
7499 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7500 struct vmcs12 *vmcs12)
7502 unsigned long exit_qualification;
7503 gpa_t bitmap, last_bitmap;
7508 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7509 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7511 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7513 port = exit_qualification >> 16;
7514 size = (exit_qualification & 7) + 1;
7516 last_bitmap = (gpa_t)-1;
7521 bitmap = vmcs12->io_bitmap_a;
7522 else if (port < 0x10000)
7523 bitmap = vmcs12->io_bitmap_b;
7526 bitmap += (port & 0x7fff) / 8;
7528 if (last_bitmap != bitmap)
7529 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7531 if (b & (1 << (port & 7)))
7536 last_bitmap = bitmap;
7543 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7544 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7545 * disinterest in the current event (read or write a specific MSR) by using an
7546 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7548 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7549 struct vmcs12 *vmcs12, u32 exit_reason)
7551 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7554 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7558 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7559 * for the four combinations of read/write and low/high MSR numbers.
7560 * First we need to figure out which of the four to use:
7562 bitmap = vmcs12->msr_bitmap;
7563 if (exit_reason == EXIT_REASON_MSR_WRITE)
7565 if (msr_index >= 0xc0000000) {
7566 msr_index -= 0xc0000000;
7570 /* Then read the msr_index'th bit from this bitmap: */
7571 if (msr_index < 1024*8) {
7573 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7575 return 1 & (b >> (msr_index & 7));
7577 return true; /* let L1 handle the wrong parameter */
7581 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7582 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7583 * intercept (via guest_host_mask etc.) the current event.
7585 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7586 struct vmcs12 *vmcs12)
7588 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7589 int cr = exit_qualification & 15;
7590 int reg = (exit_qualification >> 8) & 15;
7591 unsigned long val = kvm_register_readl(vcpu, reg);
7593 switch ((exit_qualification >> 4) & 3) {
7594 case 0: /* mov to cr */
7597 if (vmcs12->cr0_guest_host_mask &
7598 (val ^ vmcs12->cr0_read_shadow))
7602 if ((vmcs12->cr3_target_count >= 1 &&
7603 vmcs12->cr3_target_value0 == val) ||
7604 (vmcs12->cr3_target_count >= 2 &&
7605 vmcs12->cr3_target_value1 == val) ||
7606 (vmcs12->cr3_target_count >= 3 &&
7607 vmcs12->cr3_target_value2 == val) ||
7608 (vmcs12->cr3_target_count >= 4 &&
7609 vmcs12->cr3_target_value3 == val))
7611 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7615 if (vmcs12->cr4_guest_host_mask &
7616 (vmcs12->cr4_read_shadow ^ val))
7620 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7626 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7627 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7630 case 1: /* mov from cr */
7633 if (vmcs12->cpu_based_vm_exec_control &
7634 CPU_BASED_CR3_STORE_EXITING)
7638 if (vmcs12->cpu_based_vm_exec_control &
7639 CPU_BASED_CR8_STORE_EXITING)
7646 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7647 * cr0. Other attempted changes are ignored, with no exit.
7649 if (vmcs12->cr0_guest_host_mask & 0xe &
7650 (val ^ vmcs12->cr0_read_shadow))
7652 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7653 !(vmcs12->cr0_read_shadow & 0x1) &&
7662 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7663 * should handle it ourselves in L0 (and then continue L2). Only call this
7664 * when in is_guest_mode (L2).
7666 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7668 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7669 struct vcpu_vmx *vmx = to_vmx(vcpu);
7670 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7671 u32 exit_reason = vmx->exit_reason;
7673 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7674 vmcs_readl(EXIT_QUALIFICATION),
7675 vmx->idt_vectoring_info,
7677 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7680 if (vmx->nested.nested_run_pending)
7683 if (unlikely(vmx->fail)) {
7684 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7685 vmcs_read32(VM_INSTRUCTION_ERROR));
7689 switch (exit_reason) {
7690 case EXIT_REASON_EXCEPTION_NMI:
7691 if (!is_exception(intr_info))
7693 else if (is_page_fault(intr_info))
7695 else if (is_no_device(intr_info) &&
7696 !(vmcs12->guest_cr0 & X86_CR0_TS))
7698 return vmcs12->exception_bitmap &
7699 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7700 case EXIT_REASON_EXTERNAL_INTERRUPT:
7702 case EXIT_REASON_TRIPLE_FAULT:
7704 case EXIT_REASON_PENDING_INTERRUPT:
7705 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7706 case EXIT_REASON_NMI_WINDOW:
7707 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7708 case EXIT_REASON_TASK_SWITCH:
7710 case EXIT_REASON_CPUID:
7711 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7714 case EXIT_REASON_HLT:
7715 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7716 case EXIT_REASON_INVD:
7718 case EXIT_REASON_INVLPG:
7719 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7720 case EXIT_REASON_RDPMC:
7721 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7722 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7723 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7724 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7725 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7726 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7727 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7728 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7729 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7731 * VMX instructions trap unconditionally. This allows L1 to
7732 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7735 case EXIT_REASON_CR_ACCESS:
7736 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7737 case EXIT_REASON_DR_ACCESS:
7738 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7739 case EXIT_REASON_IO_INSTRUCTION:
7740 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7741 case EXIT_REASON_MSR_READ:
7742 case EXIT_REASON_MSR_WRITE:
7743 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7744 case EXIT_REASON_INVALID_STATE:
7746 case EXIT_REASON_MWAIT_INSTRUCTION:
7747 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7748 case EXIT_REASON_MONITOR_TRAP_FLAG:
7749 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7750 case EXIT_REASON_MONITOR_INSTRUCTION:
7751 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7752 case EXIT_REASON_PAUSE_INSTRUCTION:
7753 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7754 nested_cpu_has2(vmcs12,
7755 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7756 case EXIT_REASON_MCE_DURING_VMENTRY:
7758 case EXIT_REASON_TPR_BELOW_THRESHOLD:
7759 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7760 case EXIT_REASON_APIC_ACCESS:
7761 return nested_cpu_has2(vmcs12,
7762 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7763 case EXIT_REASON_APIC_WRITE:
7764 case EXIT_REASON_EOI_INDUCED:
7765 /* apic_write and eoi_induced should exit unconditionally. */
7767 case EXIT_REASON_EPT_VIOLATION:
7769 * L0 always deals with the EPT violation. If nested EPT is
7770 * used, and the nested mmu code discovers that the address is
7771 * missing in the guest EPT table (EPT12), the EPT violation
7772 * will be injected with nested_ept_inject_page_fault()
7775 case EXIT_REASON_EPT_MISCONFIG:
7777 * L2 never uses directly L1's EPT, but rather L0's own EPT
7778 * table (shadow on EPT) or a merged EPT table that L0 built
7779 * (EPT on EPT). So any problems with the structure of the
7780 * table is L0's fault.
7783 case EXIT_REASON_WBINVD:
7784 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7785 case EXIT_REASON_XSETBV:
7787 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7789 * This should never happen, since it is not possible to
7790 * set XSS to a non-zero value---neither in L1 nor in L2.
7791 * If if it were, XSS would have to be checked against
7792 * the XSS exit bitmap in vmcs12.
7794 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7795 case EXIT_REASON_PCOMMIT:
7796 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7802 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7804 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7805 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7808 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7810 struct page *pml_pg;
7812 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7816 vmx->pml_pg = pml_pg;
7818 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7819 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7824 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7827 __free_page(vmx->pml_pg);
7832 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7834 struct vcpu_vmx *vmx = to_vmx(vcpu);
7838 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7840 /* Do nothing if PML buffer is empty */
7841 if (pml_idx == (PML_ENTITY_NUM - 1))
7844 /* PML index always points to next available PML buffer entity */
7845 if (pml_idx >= PML_ENTITY_NUM)
7850 pml_buf = page_address(vmx->pml_pg);
7851 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7854 gpa = pml_buf[pml_idx];
7855 WARN_ON(gpa & (PAGE_SIZE - 1));
7856 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7859 /* reset PML index */
7860 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7864 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7865 * Called before reporting dirty_bitmap to userspace.
7867 static void kvm_flush_pml_buffers(struct kvm *kvm)
7870 struct kvm_vcpu *vcpu;
7872 * We only need to kick vcpu out of guest mode here, as PML buffer
7873 * is flushed at beginning of all VMEXITs, and it's obvious that only
7874 * vcpus running in guest are possible to have unflushed GPAs in PML
7877 kvm_for_each_vcpu(i, vcpu, kvm)
7878 kvm_vcpu_kick(vcpu);
7881 static void vmx_dump_sel(char *name, uint32_t sel)
7883 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7884 name, vmcs_read32(sel),
7885 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7886 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7887 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7890 static void vmx_dump_dtsel(char *name, uint32_t limit)
7892 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7893 name, vmcs_read32(limit),
7894 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7897 static void dump_vmcs(void)
7899 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7900 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7901 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7902 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7903 u32 secondary_exec_control = 0;
7904 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7905 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7908 if (cpu_has_secondary_exec_ctrls())
7909 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7911 pr_err("*** Guest State ***\n");
7912 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7913 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7914 vmcs_readl(CR0_GUEST_HOST_MASK));
7915 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7916 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7917 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7918 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7919 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7921 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7922 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7923 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7924 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7926 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7927 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7928 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7929 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7930 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7931 vmcs_readl(GUEST_SYSENTER_ESP),
7932 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7933 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7934 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7935 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7936 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7937 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7938 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7939 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7940 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7941 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7942 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7943 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7944 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7945 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7946 efer, vmcs_readl(GUEST_IA32_PAT));
7947 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7948 vmcs_readl(GUEST_IA32_DEBUGCTL),
7949 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7950 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7951 pr_err("PerfGlobCtl = 0x%016lx\n",
7952 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7953 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7954 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7955 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7956 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7957 vmcs_read32(GUEST_ACTIVITY_STATE));
7958 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7959 pr_err("InterruptStatus = %04x\n",
7960 vmcs_read16(GUEST_INTR_STATUS));
7962 pr_err("*** Host State ***\n");
7963 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7964 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7965 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7966 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7967 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7968 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7969 vmcs_read16(HOST_TR_SELECTOR));
7970 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7971 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7972 vmcs_readl(HOST_TR_BASE));
7973 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7974 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7975 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7976 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7977 vmcs_readl(HOST_CR4));
7978 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7979 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7980 vmcs_read32(HOST_IA32_SYSENTER_CS),
7981 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7982 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7983 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7984 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7985 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7986 pr_err("PerfGlobCtl = 0x%016lx\n",
7987 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7989 pr_err("*** Control State ***\n");
7990 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7991 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7992 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7993 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7994 vmcs_read32(EXCEPTION_BITMAP),
7995 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7996 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7997 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7998 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7999 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8000 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8001 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8002 vmcs_read32(VM_EXIT_INTR_INFO),
8003 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8004 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8005 pr_err(" reason=%08x qualification=%016lx\n",
8006 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8007 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8008 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8009 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8010 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8011 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8012 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8013 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8014 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8015 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8016 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8017 n = vmcs_read32(CR3_TARGET_COUNT);
8018 for (i = 0; i + 1 < n; i += 4)
8019 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8020 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8021 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8023 pr_err("CR3 target%u=%016lx\n",
8024 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8025 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8026 pr_err("PLE Gap=%08x Window=%08x\n",
8027 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8028 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8029 pr_err("Virtual processor ID = 0x%04x\n",
8030 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8034 * The guest has exited. See if we can fix it or if we need userspace
8037 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8039 struct vcpu_vmx *vmx = to_vmx(vcpu);
8040 u32 exit_reason = vmx->exit_reason;
8041 u32 vectoring_info = vmx->idt_vectoring_info;
8044 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8045 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8046 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8047 * mode as if vcpus is in root mode, the PML buffer must has been
8051 vmx_flush_pml_buffer(vcpu);
8053 /* If guest state is invalid, start emulating */
8054 if (vmx->emulation_required)
8055 return handle_invalid_guest_state(vcpu);
8057 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8058 nested_vmx_vmexit(vcpu, exit_reason,
8059 vmcs_read32(VM_EXIT_INTR_INFO),
8060 vmcs_readl(EXIT_QUALIFICATION));
8064 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8066 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8067 vcpu->run->fail_entry.hardware_entry_failure_reason
8072 if (unlikely(vmx->fail)) {
8073 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8074 vcpu->run->fail_entry.hardware_entry_failure_reason
8075 = vmcs_read32(VM_INSTRUCTION_ERROR);
8081 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8082 * delivery event since it indicates guest is accessing MMIO.
8083 * The vm-exit can be triggered again after return to guest that
8084 * will cause infinite loop.
8086 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8087 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8088 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8089 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8090 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8091 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8092 vcpu->run->internal.ndata = 2;
8093 vcpu->run->internal.data[0] = vectoring_info;
8094 vcpu->run->internal.data[1] = exit_reason;
8098 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8099 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8100 get_vmcs12(vcpu))))) {
8101 if (vmx_interrupt_allowed(vcpu)) {
8102 vmx->soft_vnmi_blocked = 0;
8103 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8104 vcpu->arch.nmi_pending) {
8106 * This CPU don't support us in finding the end of an
8107 * NMI-blocked window if the guest runs with IRQs
8108 * disabled. So we pull the trigger after 1 s of
8109 * futile waiting, but inform the user about this.
8111 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8112 "state on VCPU %d after 1 s timeout\n",
8113 __func__, vcpu->vcpu_id);
8114 vmx->soft_vnmi_blocked = 0;
8118 if (exit_reason < kvm_vmx_max_exit_handlers
8119 && kvm_vmx_exit_handlers[exit_reason])
8120 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8122 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8123 kvm_queue_exception(vcpu, UD_VECTOR);
8128 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8130 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8132 if (is_guest_mode(vcpu) &&
8133 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8136 if (irr == -1 || tpr < irr) {
8137 vmcs_write32(TPR_THRESHOLD, 0);
8141 vmcs_write32(TPR_THRESHOLD, irr);
8144 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8146 u32 sec_exec_control;
8149 * There is not point to enable virtualize x2apic without enable
8152 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8153 !vmx_cpu_uses_apicv(vcpu))
8156 if (!cpu_need_tpr_shadow(vcpu))
8159 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8162 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8163 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8165 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8166 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8168 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8170 vmx_set_msr_bitmap(vcpu);
8173 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8175 struct vcpu_vmx *vmx = to_vmx(vcpu);
8178 * Currently we do not handle the nested case where L2 has an
8179 * APIC access page of its own; that page is still pinned.
8180 * Hence, we skip the case where the VCPU is in guest mode _and_
8181 * L1 prepared an APIC access page for L2.
8183 * For the case where L1 and L2 share the same APIC access page
8184 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8185 * in the vmcs12), this function will only update either the vmcs01
8186 * or the vmcs02. If the former, the vmcs02 will be updated by
8187 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8188 * the next L2->L1 exit.
8190 if (!is_guest_mode(vcpu) ||
8191 !nested_cpu_has2(vmx->nested.current_vmcs12,
8192 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8193 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8196 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8204 status = vmcs_read16(GUEST_INTR_STATUS);
8209 vmcs_write16(GUEST_INTR_STATUS, status);
8213 static void vmx_set_rvi(int vector)
8221 status = vmcs_read16(GUEST_INTR_STATUS);
8222 old = (u8)status & 0xff;
8223 if ((u8)vector != old) {
8225 status |= (u8)vector;
8226 vmcs_write16(GUEST_INTR_STATUS, status);
8230 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8232 if (!is_guest_mode(vcpu)) {
8233 vmx_set_rvi(max_irr);
8241 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8244 if (nested_exit_on_intr(vcpu))
8248 * Else, fall back to pre-APICv interrupt injection since L2
8249 * is run without virtual interrupt delivery.
8251 if (!kvm_event_needs_reinjection(vcpu) &&
8252 vmx_interrupt_allowed(vcpu)) {
8253 kvm_queue_interrupt(vcpu, max_irr, false);
8254 vmx_inject_irq(vcpu);
8258 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8260 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8261 if (!vmx_cpu_uses_apicv(vcpu))
8264 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8265 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8266 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8267 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8270 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8274 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8275 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8278 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8279 exit_intr_info = vmx->exit_intr_info;
8281 /* Handle machine checks before interrupts are enabled */
8282 if (is_machine_check(exit_intr_info))
8283 kvm_machine_check();
8285 /* We need to handle NMIs before interrupts are enabled */
8286 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8287 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8288 kvm_before_handle_nmi(&vmx->vcpu);
8290 kvm_after_handle_nmi(&vmx->vcpu);
8294 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8296 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8299 * If external interrupt exists, IF bit is set in rflags/eflags on the
8300 * interrupt stack frame, and interrupt will be enabled on a return
8301 * from interrupt handler.
8303 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8304 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8305 unsigned int vector;
8306 unsigned long entry;
8308 struct vcpu_vmx *vmx = to_vmx(vcpu);
8309 #ifdef CONFIG_X86_64
8313 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8314 desc = (gate_desc *)vmx->host_idt_base + vector;
8315 entry = gate_offset(*desc);
8317 #ifdef CONFIG_X86_64
8318 "mov %%" _ASM_SP ", %[sp]\n\t"
8319 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8324 "orl $0x200, (%%" _ASM_SP ")\n\t"
8325 __ASM_SIZE(push) " $%c[cs]\n\t"
8326 "call *%[entry]\n\t"
8328 #ifdef CONFIG_X86_64
8333 [ss]"i"(__KERNEL_DS),
8334 [cs]"i"(__KERNEL_CS)
8340 static bool vmx_has_high_real_mode_segbase(void)
8342 return enable_unrestricted_guest || emulate_invalid_guest_state;
8345 static bool vmx_mpx_supported(void)
8347 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8348 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8351 static bool vmx_xsaves_supported(void)
8353 return vmcs_config.cpu_based_2nd_exec_ctrl &
8354 SECONDARY_EXEC_XSAVES;
8357 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8362 bool idtv_info_valid;
8364 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8366 if (cpu_has_virtual_nmis()) {
8367 if (vmx->nmi_known_unmasked)
8370 * Can't use vmx->exit_intr_info since we're not sure what
8371 * the exit reason is.
8373 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8374 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8375 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8377 * SDM 3: 27.7.1.2 (September 2008)
8378 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8379 * a guest IRET fault.
8380 * SDM 3: 23.2.2 (September 2008)
8381 * Bit 12 is undefined in any of the following cases:
8382 * If the VM exit sets the valid bit in the IDT-vectoring
8383 * information field.
8384 * If the VM exit is due to a double fault.
8386 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8387 vector != DF_VECTOR && !idtv_info_valid)
8388 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8389 GUEST_INTR_STATE_NMI);
8391 vmx->nmi_known_unmasked =
8392 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8393 & GUEST_INTR_STATE_NMI);
8394 } else if (unlikely(vmx->soft_vnmi_blocked))
8395 vmx->vnmi_blocked_time +=
8396 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8399 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8400 u32 idt_vectoring_info,
8401 int instr_len_field,
8402 int error_code_field)
8406 bool idtv_info_valid;
8408 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8410 vcpu->arch.nmi_injected = false;
8411 kvm_clear_exception_queue(vcpu);
8412 kvm_clear_interrupt_queue(vcpu);
8414 if (!idtv_info_valid)
8417 kvm_make_request(KVM_REQ_EVENT, vcpu);
8419 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8420 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8423 case INTR_TYPE_NMI_INTR:
8424 vcpu->arch.nmi_injected = true;
8426 * SDM 3: 27.7.1.2 (September 2008)
8427 * Clear bit "block by NMI" before VM entry if a NMI
8430 vmx_set_nmi_mask(vcpu, false);
8432 case INTR_TYPE_SOFT_EXCEPTION:
8433 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8435 case INTR_TYPE_HARD_EXCEPTION:
8436 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8437 u32 err = vmcs_read32(error_code_field);
8438 kvm_requeue_exception_e(vcpu, vector, err);
8440 kvm_requeue_exception(vcpu, vector);
8442 case INTR_TYPE_SOFT_INTR:
8443 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8445 case INTR_TYPE_EXT_INTR:
8446 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8453 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8455 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8456 VM_EXIT_INSTRUCTION_LEN,
8457 IDT_VECTORING_ERROR_CODE);
8460 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8462 __vmx_complete_interrupts(vcpu,
8463 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8464 VM_ENTRY_INSTRUCTION_LEN,
8465 VM_ENTRY_EXCEPTION_ERROR_CODE);
8467 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8470 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8473 struct perf_guest_switch_msr *msrs;
8475 msrs = perf_guest_get_msrs(&nr_msrs);
8480 for (i = 0; i < nr_msrs; i++)
8481 if (msrs[i].host == msrs[i].guest)
8482 clear_atomic_switch_msr(vmx, msrs[i].msr);
8484 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8488 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8490 struct vcpu_vmx *vmx = to_vmx(vcpu);
8491 unsigned long debugctlmsr, cr4;
8493 /* Record the guest's net vcpu time for enforced NMI injections. */
8494 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8495 vmx->entry_time = ktime_get();
8497 /* Don't enter VMX if guest state is invalid, let the exit handler
8498 start emulation until we arrive back to a valid state */
8499 if (vmx->emulation_required)
8502 if (vmx->ple_window_dirty) {
8503 vmx->ple_window_dirty = false;
8504 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8507 if (vmx->nested.sync_shadow_vmcs) {
8508 copy_vmcs12_to_shadow(vmx);
8509 vmx->nested.sync_shadow_vmcs = false;
8512 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8513 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8514 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8515 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8517 cr4 = cr4_read_shadow();
8518 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8519 vmcs_writel(HOST_CR4, cr4);
8520 vmx->host_state.vmcs_host_cr4 = cr4;
8523 /* When single-stepping over STI and MOV SS, we must clear the
8524 * corresponding interruptibility bits in the guest state. Otherwise
8525 * vmentry fails as it then expects bit 14 (BS) in pending debug
8526 * exceptions being set, but that's not correct for the guest debugging
8528 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8529 vmx_set_interrupt_shadow(vcpu, 0);
8531 atomic_switch_perf_msrs(vmx);
8532 debugctlmsr = get_debugctlmsr();
8534 vmx->__launched = vmx->loaded_vmcs->launched;
8536 /* Store host registers */
8537 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8538 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8539 "push %%" _ASM_CX " \n\t"
8540 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8542 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8543 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8545 /* Reload cr2 if changed */
8546 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8547 "mov %%cr2, %%" _ASM_DX " \n\t"
8548 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8550 "mov %%" _ASM_AX", %%cr2 \n\t"
8552 /* Check if vmlaunch of vmresume is needed */
8553 "cmpl $0, %c[launched](%0) \n\t"
8554 /* Load guest registers. Don't clobber flags. */
8555 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8556 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8557 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8558 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8559 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8560 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8561 #ifdef CONFIG_X86_64
8562 "mov %c[r8](%0), %%r8 \n\t"
8563 "mov %c[r9](%0), %%r9 \n\t"
8564 "mov %c[r10](%0), %%r10 \n\t"
8565 "mov %c[r11](%0), %%r11 \n\t"
8566 "mov %c[r12](%0), %%r12 \n\t"
8567 "mov %c[r13](%0), %%r13 \n\t"
8568 "mov %c[r14](%0), %%r14 \n\t"
8569 "mov %c[r15](%0), %%r15 \n\t"
8571 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8573 /* Enter guest mode */
8575 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8577 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8579 /* Save guest registers, load host registers, keep flags */
8580 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8582 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8583 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8584 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8585 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8586 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8587 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8588 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8589 #ifdef CONFIG_X86_64
8590 "mov %%r8, %c[r8](%0) \n\t"
8591 "mov %%r9, %c[r9](%0) \n\t"
8592 "mov %%r10, %c[r10](%0) \n\t"
8593 "mov %%r11, %c[r11](%0) \n\t"
8594 "mov %%r12, %c[r12](%0) \n\t"
8595 "mov %%r13, %c[r13](%0) \n\t"
8596 "mov %%r14, %c[r14](%0) \n\t"
8597 "mov %%r15, %c[r15](%0) \n\t"
8599 "mov %%cr2, %%" _ASM_AX " \n\t"
8600 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8602 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8603 "setbe %c[fail](%0) \n\t"
8604 ".pushsection .rodata \n\t"
8605 ".global vmx_return \n\t"
8606 "vmx_return: " _ASM_PTR " 2b \n\t"
8608 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8609 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8610 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8611 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8612 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8613 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8614 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8615 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8616 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8617 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8618 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8619 #ifdef CONFIG_X86_64
8620 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8621 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8622 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8623 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8624 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8625 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8626 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8627 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8629 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8630 [wordsize]"i"(sizeof(ulong))
8632 #ifdef CONFIG_X86_64
8633 , "rax", "rbx", "rdi", "rsi"
8634 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8636 , "eax", "ebx", "edi", "esi"
8640 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8642 update_debugctlmsr(debugctlmsr);
8644 #ifndef CONFIG_X86_64
8646 * The sysexit path does not restore ds/es, so we must set them to
8647 * a reasonable value ourselves.
8649 * We can't defer this to vmx_load_host_state() since that function
8650 * may be executed in interrupt context, which saves and restore segments
8651 * around it, nullifying its effect.
8653 loadsegment(ds, __USER_DS);
8654 loadsegment(es, __USER_DS);
8657 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8658 | (1 << VCPU_EXREG_RFLAGS)
8659 | (1 << VCPU_EXREG_PDPTR)
8660 | (1 << VCPU_EXREG_SEGMENTS)
8661 | (1 << VCPU_EXREG_CR3));
8662 vcpu->arch.regs_dirty = 0;
8664 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8666 vmx->loaded_vmcs->launched = 1;
8668 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8669 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
8672 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8673 * we did not inject a still-pending event to L1 now because of
8674 * nested_run_pending, we need to re-enable this bit.
8676 if (vmx->nested.nested_run_pending)
8677 kvm_make_request(KVM_REQ_EVENT, vcpu);
8679 vmx->nested.nested_run_pending = 0;
8681 vmx_complete_atomic_exit(vmx);
8682 vmx_recover_nmi_blocking(vmx);
8683 vmx_complete_interrupts(vmx);
8686 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8688 struct vcpu_vmx *vmx = to_vmx(vcpu);
8691 if (vmx->loaded_vmcs == &vmx->vmcs01)
8695 vmx->loaded_vmcs = &vmx->vmcs01;
8697 vmx_vcpu_load(vcpu, cpu);
8702 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8704 struct vcpu_vmx *vmx = to_vmx(vcpu);
8707 vmx_destroy_pml_buffer(vmx);
8708 free_vpid(vmx->vpid);
8709 leave_guest_mode(vcpu);
8710 vmx_load_vmcs01(vcpu);
8712 free_loaded_vmcs(vmx->loaded_vmcs);
8713 kfree(vmx->guest_msrs);
8714 kvm_vcpu_uninit(vcpu);
8715 kmem_cache_free(kvm_vcpu_cache, vmx);
8718 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8721 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8725 return ERR_PTR(-ENOMEM);
8727 vmx->vpid = allocate_vpid();
8729 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8733 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8734 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8738 if (!vmx->guest_msrs) {
8742 vmx->loaded_vmcs = &vmx->vmcs01;
8743 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8744 if (!vmx->loaded_vmcs->vmcs)
8747 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8748 loaded_vmcs_init(vmx->loaded_vmcs);
8753 vmx_vcpu_load(&vmx->vcpu, cpu);
8754 vmx->vcpu.cpu = cpu;
8755 err = vmx_vcpu_setup(vmx);
8756 vmx_vcpu_put(&vmx->vcpu);
8760 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8761 err = alloc_apic_access_page(kvm);
8767 if (!kvm->arch.ept_identity_map_addr)
8768 kvm->arch.ept_identity_map_addr =
8769 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8770 err = init_rmode_identity_map(kvm);
8776 nested_vmx_setup_ctls_msrs(vmx);
8777 vmx->nested.vpid02 = allocate_vpid();
8780 vmx->nested.posted_intr_nv = -1;
8781 vmx->nested.current_vmptr = -1ull;
8782 vmx->nested.current_vmcs12 = NULL;
8785 * If PML is turned on, failure on enabling PML just results in failure
8786 * of creating the vcpu, therefore we can simplify PML logic (by
8787 * avoiding dealing with cases, such as enabling PML partially on vcpus
8788 * for the guest, etc.
8791 err = vmx_create_pml_buffer(vmx);
8799 free_vpid(vmx->nested.vpid02);
8800 free_loaded_vmcs(vmx->loaded_vmcs);
8802 kfree(vmx->guest_msrs);
8804 kvm_vcpu_uninit(&vmx->vcpu);
8806 free_vpid(vmx->vpid);
8807 kmem_cache_free(kvm_vcpu_cache, vmx);
8808 return ERR_PTR(err);
8811 static void __init vmx_check_processor_compat(void *rtn)
8813 struct vmcs_config vmcs_conf;
8816 if (setup_vmcs_config(&vmcs_conf) < 0)
8818 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8819 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8820 smp_processor_id());
8825 static int get_ept_level(void)
8827 return VMX_EPT_DEFAULT_GAW + 1;
8830 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8835 /* For VT-d and EPT combination
8836 * 1. MMIO: always map as UC
8838 * a. VT-d without snooping control feature: can't guarantee the
8839 * result, try to trust guest.
8840 * b. VT-d with snooping control feature: snooping control feature of
8841 * VT-d engine can guarantee the cache correctness. Just set it
8842 * to WB to keep consistent with host. So the same as item 3.
8843 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8844 * consistent with host MTRR
8847 cache = MTRR_TYPE_UNCACHABLE;
8851 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8852 ipat = VMX_EPT_IPAT_BIT;
8853 cache = MTRR_TYPE_WRBACK;
8857 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8858 ipat = VMX_EPT_IPAT_BIT;
8859 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8860 cache = MTRR_TYPE_WRBACK;
8862 cache = MTRR_TYPE_UNCACHABLE;
8866 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8869 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8872 static int vmx_get_lpage_level(void)
8874 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8875 return PT_DIRECTORY_LEVEL;
8877 /* For shadow and EPT supported 1GB page */
8878 return PT_PDPE_LEVEL;
8881 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8884 * These bits in the secondary execution controls field
8885 * are dynamic, the others are mostly based on the hypervisor
8886 * architecture and the guest's CPUID. Do not touch the
8890 SECONDARY_EXEC_SHADOW_VMCS |
8891 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8892 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8894 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8896 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8897 (new_ctl & ~mask) | (cur_ctl & mask));
8900 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8902 struct kvm_cpuid_entry2 *best;
8903 struct vcpu_vmx *vmx = to_vmx(vcpu);
8904 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8906 if (vmx_rdtscp_supported()) {
8907 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8908 if (!rdtscp_enabled)
8909 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8913 vmx->nested.nested_vmx_secondary_ctls_high |=
8914 SECONDARY_EXEC_RDTSCP;
8916 vmx->nested.nested_vmx_secondary_ctls_high &=
8917 ~SECONDARY_EXEC_RDTSCP;
8921 /* Exposing INVPCID only when PCID is exposed */
8922 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8923 if (vmx_invpcid_supported() &&
8924 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8925 !guest_cpuid_has_pcid(vcpu))) {
8926 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8929 best->ebx &= ~bit(X86_FEATURE_INVPCID);
8932 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8934 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8935 if (guest_cpuid_has_pcommit(vcpu))
8936 vmx->nested.nested_vmx_secondary_ctls_high |=
8937 SECONDARY_EXEC_PCOMMIT;
8939 vmx->nested.nested_vmx_secondary_ctls_high &=
8940 ~SECONDARY_EXEC_PCOMMIT;
8944 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8946 if (func == 1 && nested)
8947 entry->ecx |= bit(X86_FEATURE_VMX);
8950 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8951 struct x86_exception *fault)
8953 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8956 if (fault->error_code & PFERR_RSVD_MASK)
8957 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8959 exit_reason = EXIT_REASON_EPT_VIOLATION;
8960 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8961 vmcs12->guest_physical_address = fault->address;
8964 /* Callbacks for nested_ept_init_mmu_context: */
8966 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8968 /* return the page table to be shadowed - in our case, EPT12 */
8969 return get_vmcs12(vcpu)->ept_pointer;
8972 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8974 WARN_ON(mmu_is_nested(vcpu));
8975 kvm_init_shadow_ept_mmu(vcpu,
8976 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8977 VMX_EPT_EXECUTE_ONLY_BIT);
8978 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8979 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8980 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8982 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
8985 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8987 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8990 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8993 bool inequality, bit;
8995 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8997 (error_code & vmcs12->page_fault_error_code_mask) !=
8998 vmcs12->page_fault_error_code_match;
8999 return inequality ^ bit;
9002 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9003 struct x86_exception *fault)
9005 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9007 WARN_ON(!is_guest_mode(vcpu));
9009 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9010 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9011 vmcs_read32(VM_EXIT_INTR_INFO),
9012 vmcs_readl(EXIT_QUALIFICATION));
9014 kvm_inject_page_fault(vcpu, fault);
9017 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9018 struct vmcs12 *vmcs12)
9020 struct vcpu_vmx *vmx = to_vmx(vcpu);
9021 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9023 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9024 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9025 vmcs12->apic_access_addr >> maxphyaddr)
9029 * Translate L1 physical address to host physical
9030 * address for vmcs02. Keep the page pinned, so this
9031 * physical address remains valid. We keep a reference
9032 * to it so we can release it later.
9034 if (vmx->nested.apic_access_page) /* shouldn't happen */
9035 nested_release_page(vmx->nested.apic_access_page);
9036 vmx->nested.apic_access_page =
9037 nested_get_page(vcpu, vmcs12->apic_access_addr);
9040 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9041 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9042 vmcs12->virtual_apic_page_addr >> maxphyaddr)
9045 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9046 nested_release_page(vmx->nested.virtual_apic_page);
9047 vmx->nested.virtual_apic_page =
9048 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9051 * Failing the vm entry is _not_ what the processor does
9052 * but it's basically the only possibility we have.
9053 * We could still enter the guest if CR8 load exits are
9054 * enabled, CR8 store exits are enabled, and virtualize APIC
9055 * access is disabled; in this case the processor would never
9056 * use the TPR shadow and we could simply clear the bit from
9057 * the execution control. But such a configuration is useless,
9058 * so let's keep the code simple.
9060 if (!vmx->nested.virtual_apic_page)
9064 if (nested_cpu_has_posted_intr(vmcs12)) {
9065 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9066 vmcs12->posted_intr_desc_addr >> maxphyaddr)
9069 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9070 kunmap(vmx->nested.pi_desc_page);
9071 nested_release_page(vmx->nested.pi_desc_page);
9073 vmx->nested.pi_desc_page =
9074 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9075 if (!vmx->nested.pi_desc_page)
9078 vmx->nested.pi_desc =
9079 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9080 if (!vmx->nested.pi_desc) {
9081 nested_release_page_clean(vmx->nested.pi_desc_page);
9084 vmx->nested.pi_desc =
9085 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9086 (unsigned long)(vmcs12->posted_intr_desc_addr &
9093 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9095 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9096 struct vcpu_vmx *vmx = to_vmx(vcpu);
9098 if (vcpu->arch.virtual_tsc_khz == 0)
9101 /* Make sure short timeouts reliably trigger an immediate vmexit.
9102 * hrtimer_start does not guarantee this. */
9103 if (preemption_timeout <= 1) {
9104 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9108 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9109 preemption_timeout *= 1000000;
9110 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9111 hrtimer_start(&vmx->nested.preemption_timer,
9112 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9115 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9116 struct vmcs12 *vmcs12)
9121 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9124 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9128 maxphyaddr = cpuid_maxphyaddr(vcpu);
9130 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9131 ((addr + PAGE_SIZE) >> maxphyaddr))
9138 * Merge L0's and L1's MSR bitmap, return false to indicate that
9139 * we do not use the hardware.
9141 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9142 struct vmcs12 *vmcs12)
9146 unsigned long *msr_bitmap;
9148 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9151 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9156 msr_bitmap = (unsigned long *)kmap(page);
9158 nested_release_page_clean(page);
9163 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9164 if (nested_cpu_has_apic_reg_virt(vmcs12))
9165 for (msr = 0x800; msr <= 0x8ff; msr++)
9166 nested_vmx_disable_intercept_for_msr(
9168 vmx_msr_bitmap_nested,
9170 /* TPR is allowed */
9171 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9172 vmx_msr_bitmap_nested,
9173 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9174 MSR_TYPE_R | MSR_TYPE_W);
9175 if (nested_cpu_has_vid(vmcs12)) {
9176 /* EOI and self-IPI are allowed */
9177 nested_vmx_disable_intercept_for_msr(
9179 vmx_msr_bitmap_nested,
9180 APIC_BASE_MSR + (APIC_EOI >> 4),
9182 nested_vmx_disable_intercept_for_msr(
9184 vmx_msr_bitmap_nested,
9185 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9190 * Enable reading intercept of all the x2apic
9191 * MSRs. We should not rely on vmcs12 to do any
9192 * optimizations here, it may have been modified
9195 for (msr = 0x800; msr <= 0x8ff; msr++)
9196 __vmx_enable_intercept_for_msr(
9197 vmx_msr_bitmap_nested,
9201 __vmx_enable_intercept_for_msr(
9202 vmx_msr_bitmap_nested,
9203 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9205 __vmx_enable_intercept_for_msr(
9206 vmx_msr_bitmap_nested,
9207 APIC_BASE_MSR + (APIC_EOI >> 4),
9209 __vmx_enable_intercept_for_msr(
9210 vmx_msr_bitmap_nested,
9211 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9215 nested_release_page_clean(page);
9220 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9221 struct vmcs12 *vmcs12)
9223 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9224 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9225 !nested_cpu_has_vid(vmcs12) &&
9226 !nested_cpu_has_posted_intr(vmcs12))
9230 * If virtualize x2apic mode is enabled,
9231 * virtualize apic access must be disabled.
9233 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9234 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9238 * If virtual interrupt delivery is enabled,
9239 * we must exit on external interrupts.
9241 if (nested_cpu_has_vid(vmcs12) &&
9242 !nested_exit_on_intr(vcpu))
9246 * bits 15:8 should be zero in posted_intr_nv,
9247 * the descriptor address has been already checked
9248 * in nested_get_vmcs12_pages.
9250 if (nested_cpu_has_posted_intr(vmcs12) &&
9251 (!nested_cpu_has_vid(vmcs12) ||
9252 !nested_exit_intr_ack_set(vcpu) ||
9253 vmcs12->posted_intr_nv & 0xff00))
9256 /* tpr shadow is needed by all apicv features. */
9257 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9263 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9264 unsigned long count_field,
9265 unsigned long addr_field)
9270 if (vmcs12_read_any(vcpu, count_field, &count) ||
9271 vmcs12_read_any(vcpu, addr_field, &addr)) {
9277 maxphyaddr = cpuid_maxphyaddr(vcpu);
9278 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9279 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9280 pr_warn_ratelimited(
9281 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9282 addr_field, maxphyaddr, count, addr);
9288 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9289 struct vmcs12 *vmcs12)
9291 if (vmcs12->vm_exit_msr_load_count == 0 &&
9292 vmcs12->vm_exit_msr_store_count == 0 &&
9293 vmcs12->vm_entry_msr_load_count == 0)
9294 return 0; /* Fast path */
9295 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9296 VM_EXIT_MSR_LOAD_ADDR) ||
9297 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9298 VM_EXIT_MSR_STORE_ADDR) ||
9299 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9300 VM_ENTRY_MSR_LOAD_ADDR))
9305 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9306 struct vmx_msr_entry *e)
9308 /* x2APIC MSR accesses are not allowed */
9309 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9311 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9312 e->index == MSR_IA32_UCODE_REV)
9314 if (e->reserved != 0)
9319 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9320 struct vmx_msr_entry *e)
9322 if (e->index == MSR_FS_BASE ||
9323 e->index == MSR_GS_BASE ||
9324 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9325 nested_vmx_msr_check_common(vcpu, e))
9330 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9331 struct vmx_msr_entry *e)
9333 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9334 nested_vmx_msr_check_common(vcpu, e))
9340 * Load guest's/host's msr at nested entry/exit.
9341 * return 0 for success, entry index for failure.
9343 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9346 struct vmx_msr_entry e;
9347 struct msr_data msr;
9349 msr.host_initiated = false;
9350 for (i = 0; i < count; i++) {
9351 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9353 pr_warn_ratelimited(
9354 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9355 __func__, i, gpa + i * sizeof(e));
9358 if (nested_vmx_load_msr_check(vcpu, &e)) {
9359 pr_warn_ratelimited(
9360 "%s check failed (%u, 0x%x, 0x%x)\n",
9361 __func__, i, e.index, e.reserved);
9364 msr.index = e.index;
9366 if (kvm_set_msr(vcpu, &msr)) {
9367 pr_warn_ratelimited(
9368 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9369 __func__, i, e.index, e.value);
9378 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9381 struct vmx_msr_entry e;
9383 for (i = 0; i < count; i++) {
9384 struct msr_data msr_info;
9385 if (kvm_vcpu_read_guest(vcpu,
9386 gpa + i * sizeof(e),
9387 &e, 2 * sizeof(u32))) {
9388 pr_warn_ratelimited(
9389 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9390 __func__, i, gpa + i * sizeof(e));
9393 if (nested_vmx_store_msr_check(vcpu, &e)) {
9394 pr_warn_ratelimited(
9395 "%s check failed (%u, 0x%x, 0x%x)\n",
9396 __func__, i, e.index, e.reserved);
9399 msr_info.host_initiated = false;
9400 msr_info.index = e.index;
9401 if (kvm_get_msr(vcpu, &msr_info)) {
9402 pr_warn_ratelimited(
9403 "%s cannot read MSR (%u, 0x%x)\n",
9404 __func__, i, e.index);
9407 if (kvm_vcpu_write_guest(vcpu,
9408 gpa + i * sizeof(e) +
9409 offsetof(struct vmx_msr_entry, value),
9410 &msr_info.data, sizeof(msr_info.data))) {
9411 pr_warn_ratelimited(
9412 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9413 __func__, i, e.index, msr_info.data);
9421 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9422 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9423 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9424 * guest in a way that will both be appropriate to L1's requests, and our
9425 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9426 * function also has additional necessary side-effects, like setting various
9427 * vcpu->arch fields.
9429 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9431 struct vcpu_vmx *vmx = to_vmx(vcpu);
9434 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9435 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9436 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9437 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9438 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9439 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9440 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9441 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9442 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9443 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9444 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9445 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9446 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9447 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9448 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9449 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9450 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9451 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9452 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9453 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9454 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9455 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9456 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9457 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9458 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9459 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9460 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9461 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9462 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9463 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9464 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9465 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9466 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9467 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9468 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9469 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9471 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9472 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9473 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9475 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9476 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9478 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9479 vmcs12->vm_entry_intr_info_field);
9480 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9481 vmcs12->vm_entry_exception_error_code);
9482 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9483 vmcs12->vm_entry_instruction_len);
9484 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9485 vmcs12->guest_interruptibility_info);
9486 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9487 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9488 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9489 vmcs12->guest_pending_dbg_exceptions);
9490 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9491 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9493 if (nested_cpu_has_xsaves(vmcs12))
9494 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9495 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9497 exec_control = vmcs12->pin_based_vm_exec_control;
9498 exec_control |= vmcs_config.pin_based_exec_ctrl;
9499 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9501 if (nested_cpu_has_posted_intr(vmcs12)) {
9503 * Note that we use L0's vector here and in
9504 * vmx_deliver_nested_posted_interrupt.
9506 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9507 vmx->nested.pi_pending = false;
9508 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9509 vmcs_write64(POSTED_INTR_DESC_ADDR,
9510 page_to_phys(vmx->nested.pi_desc_page) +
9511 (unsigned long)(vmcs12->posted_intr_desc_addr &
9514 exec_control &= ~PIN_BASED_POSTED_INTR;
9516 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9518 vmx->nested.preemption_timer_expired = false;
9519 if (nested_cpu_has_preemption_timer(vmcs12))
9520 vmx_start_preemption_timer(vcpu);
9523 * Whether page-faults are trapped is determined by a combination of
9524 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9525 * If enable_ept, L0 doesn't care about page faults and we should
9526 * set all of these to L1's desires. However, if !enable_ept, L0 does
9527 * care about (at least some) page faults, and because it is not easy
9528 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9529 * to exit on each and every L2 page fault. This is done by setting
9530 * MASK=MATCH=0 and (see below) EB.PF=1.
9531 * Note that below we don't need special code to set EB.PF beyond the
9532 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9533 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9534 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9536 * A problem with this approach (when !enable_ept) is that L1 may be
9537 * injected with more page faults than it asked for. This could have
9538 * caused problems, but in practice existing hypervisors don't care.
9539 * To fix this, we will need to emulate the PFEC checking (on the L1
9540 * page tables), using walk_addr(), when injecting PFs to L1.
9542 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9543 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9544 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9545 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9547 if (cpu_has_secondary_exec_ctrls()) {
9548 exec_control = vmx_secondary_exec_control(vmx);
9550 /* Take the following fields only from vmcs12 */
9551 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9552 SECONDARY_EXEC_RDTSCP |
9553 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9554 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9555 SECONDARY_EXEC_PCOMMIT);
9556 if (nested_cpu_has(vmcs12,
9557 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9558 exec_control |= vmcs12->secondary_vm_exec_control;
9560 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9562 * If translation failed, no matter: This feature asks
9563 * to exit when accessing the given address, and if it
9564 * can never be accessed, this feature won't do
9567 if (!vmx->nested.apic_access_page)
9569 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9571 vmcs_write64(APIC_ACCESS_ADDR,
9572 page_to_phys(vmx->nested.apic_access_page));
9573 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9574 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9576 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9577 kvm_vcpu_reload_apic_access_page(vcpu);
9580 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9581 vmcs_write64(EOI_EXIT_BITMAP0,
9582 vmcs12->eoi_exit_bitmap0);
9583 vmcs_write64(EOI_EXIT_BITMAP1,
9584 vmcs12->eoi_exit_bitmap1);
9585 vmcs_write64(EOI_EXIT_BITMAP2,
9586 vmcs12->eoi_exit_bitmap2);
9587 vmcs_write64(EOI_EXIT_BITMAP3,
9588 vmcs12->eoi_exit_bitmap3);
9589 vmcs_write16(GUEST_INTR_STATUS,
9590 vmcs12->guest_intr_status);
9593 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9598 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9599 * Some constant fields are set here by vmx_set_constant_host_state().
9600 * Other fields are different per CPU, and will be set later when
9601 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9603 vmx_set_constant_host_state(vmx);
9606 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9607 * entry, but only if the current (host) sp changed from the value
9608 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9609 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9610 * here we just force the write to happen on entry.
9614 exec_control = vmx_exec_control(vmx); /* L0's desires */
9615 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9616 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9617 exec_control &= ~CPU_BASED_TPR_SHADOW;
9618 exec_control |= vmcs12->cpu_based_vm_exec_control;
9620 if (exec_control & CPU_BASED_TPR_SHADOW) {
9621 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9622 page_to_phys(vmx->nested.virtual_apic_page));
9623 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9626 if (cpu_has_vmx_msr_bitmap() &&
9627 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9628 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9629 /* MSR_BITMAP will be set by following vmx_set_efer. */
9631 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9634 * Merging of IO bitmap not currently supported.
9635 * Rather, exit every time.
9637 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9638 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9640 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9642 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9643 * bitwise-or of what L1 wants to trap for L2, and what we want to
9644 * trap. Note that CR0.TS also needs updating - we do this later.
9646 update_exception_bitmap(vcpu);
9647 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9648 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9650 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9651 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9652 * bits are further modified by vmx_set_efer() below.
9654 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9656 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9657 * emulated by vmx_set_efer(), below.
9659 vm_entry_controls_init(vmx,
9660 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9661 ~VM_ENTRY_IA32E_MODE) |
9662 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9664 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9665 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9666 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9667 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9668 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9671 set_cr4_guest_host_mask(vmx);
9673 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9674 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9676 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9677 vmcs_write64(TSC_OFFSET,
9678 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9680 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9684 * There is no direct mapping between vpid02 and vpid12, the
9685 * vpid02 is per-vCPU for L0 and reused while the value of
9686 * vpid12 is changed w/ one invvpid during nested vmentry.
9687 * The vpid12 is allocated by L1 for L2, so it will not
9688 * influence global bitmap(for vpid01 and vpid02 allocation)
9689 * even if spawn a lot of nested vCPUs.
9691 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9692 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9693 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9694 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9695 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9698 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9699 vmx_flush_tlb(vcpu);
9704 if (nested_cpu_has_ept(vmcs12)) {
9705 kvm_mmu_unload(vcpu);
9706 nested_ept_init_mmu_context(vcpu);
9709 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9710 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9711 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9712 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9714 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9715 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9716 vmx_set_efer(vcpu, vcpu->arch.efer);
9719 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9720 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9721 * The CR0_READ_SHADOW is what L2 should have expected to read given
9722 * the specifications by L1; It's not enough to take
9723 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9724 * have more bits than L1 expected.
9726 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9727 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9729 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9730 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9732 /* shadow page tables on either EPT or shadow page tables */
9733 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9734 kvm_mmu_reset_context(vcpu);
9737 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9740 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9743 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9744 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9745 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9746 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9749 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9750 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9754 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9755 * for running an L2 nested guest.
9757 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9759 struct vmcs12 *vmcs12;
9760 struct vcpu_vmx *vmx = to_vmx(vcpu);
9762 struct loaded_vmcs *vmcs02;
9766 if (!nested_vmx_check_permission(vcpu) ||
9767 !nested_vmx_check_vmcs12(vcpu))
9770 skip_emulated_instruction(vcpu);
9771 vmcs12 = get_vmcs12(vcpu);
9773 if (enable_shadow_vmcs)
9774 copy_shadow_to_vmcs12(vmx);
9777 * The nested entry process starts with enforcing various prerequisites
9778 * on vmcs12 as required by the Intel SDM, and act appropriately when
9779 * they fail: As the SDM explains, some conditions should cause the
9780 * instruction to fail, while others will cause the instruction to seem
9781 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9782 * To speed up the normal (success) code path, we should avoid checking
9783 * for misconfigurations which will anyway be caught by the processor
9784 * when using the merged vmcs02.
9786 if (vmcs12->launch_state == launch) {
9787 nested_vmx_failValid(vcpu,
9788 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9789 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9793 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9794 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9795 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9799 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9800 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9804 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9805 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9809 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9810 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9814 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9815 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9819 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9820 vmx->nested.nested_vmx_true_procbased_ctls_low,
9821 vmx->nested.nested_vmx_procbased_ctls_high) ||
9822 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9823 vmx->nested.nested_vmx_secondary_ctls_low,
9824 vmx->nested.nested_vmx_secondary_ctls_high) ||
9825 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9826 vmx->nested.nested_vmx_pinbased_ctls_low,
9827 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9828 !vmx_control_verify(vmcs12->vm_exit_controls,
9829 vmx->nested.nested_vmx_true_exit_ctls_low,
9830 vmx->nested.nested_vmx_exit_ctls_high) ||
9831 !vmx_control_verify(vmcs12->vm_entry_controls,
9832 vmx->nested.nested_vmx_true_entry_ctls_low,
9833 vmx->nested.nested_vmx_entry_ctls_high))
9835 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9839 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9840 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9841 nested_vmx_failValid(vcpu,
9842 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9846 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9847 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9848 nested_vmx_entry_failure(vcpu, vmcs12,
9849 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9852 if (vmcs12->vmcs_link_pointer != -1ull) {
9853 nested_vmx_entry_failure(vcpu, vmcs12,
9854 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9859 * If the load IA32_EFER VM-entry control is 1, the following checks
9860 * are performed on the field for the IA32_EFER MSR:
9861 * - Bits reserved in the IA32_EFER MSR must be 0.
9862 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9863 * the IA-32e mode guest VM-exit control. It must also be identical
9864 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9867 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9868 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9869 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9870 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9871 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9872 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9873 nested_vmx_entry_failure(vcpu, vmcs12,
9874 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9880 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9881 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9882 * the values of the LMA and LME bits in the field must each be that of
9883 * the host address-space size VM-exit control.
9885 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9886 ia32e = (vmcs12->vm_exit_controls &
9887 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9888 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9889 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9890 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9891 nested_vmx_entry_failure(vcpu, vmcs12,
9892 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9898 * We're finally done with prerequisite checking, and can start with
9902 vmcs02 = nested_get_current_vmcs02(vmx);
9906 enter_guest_mode(vcpu);
9908 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9910 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9911 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9914 vmx->loaded_vmcs = vmcs02;
9916 vmx_vcpu_load(vcpu, cpu);
9920 vmx_segment_cache_clear(vmx);
9922 prepare_vmcs02(vcpu, vmcs12);
9924 msr_entry_idx = nested_vmx_load_msr(vcpu,
9925 vmcs12->vm_entry_msr_load_addr,
9926 vmcs12->vm_entry_msr_load_count);
9927 if (msr_entry_idx) {
9928 leave_guest_mode(vcpu);
9929 vmx_load_vmcs01(vcpu);
9930 nested_vmx_entry_failure(vcpu, vmcs12,
9931 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9935 vmcs12->launch_state = 1;
9937 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9938 return kvm_vcpu_halt(vcpu);
9940 vmx->nested.nested_run_pending = 1;
9943 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9944 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9945 * returned as far as L1 is concerned. It will only return (and set
9946 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9952 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9953 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9954 * This function returns the new value we should put in vmcs12.guest_cr0.
9955 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9956 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9957 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9958 * didn't trap the bit, because if L1 did, so would L0).
9959 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9960 * been modified by L2, and L1 knows it. So just leave the old value of
9961 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9962 * isn't relevant, because if L0 traps this bit it can set it to anything.
9963 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9964 * changed these bits, and therefore they need to be updated, but L0
9965 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9966 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9968 static inline unsigned long
9969 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9972 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9973 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9974 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9975 vcpu->arch.cr0_guest_owned_bits));
9978 static inline unsigned long
9979 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9982 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9983 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9984 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9985 vcpu->arch.cr4_guest_owned_bits));
9988 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9989 struct vmcs12 *vmcs12)
9994 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9995 nr = vcpu->arch.exception.nr;
9996 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9998 if (kvm_exception_is_soft(nr)) {
9999 vmcs12->vm_exit_instruction_len =
10000 vcpu->arch.event_exit_inst_len;
10001 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10003 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10005 if (vcpu->arch.exception.has_error_code) {
10006 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10007 vmcs12->idt_vectoring_error_code =
10008 vcpu->arch.exception.error_code;
10011 vmcs12->idt_vectoring_info_field = idt_vectoring;
10012 } else if (vcpu->arch.nmi_injected) {
10013 vmcs12->idt_vectoring_info_field =
10014 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10015 } else if (vcpu->arch.interrupt.pending) {
10016 nr = vcpu->arch.interrupt.nr;
10017 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10019 if (vcpu->arch.interrupt.soft) {
10020 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10021 vmcs12->vm_entry_instruction_len =
10022 vcpu->arch.event_exit_inst_len;
10024 idt_vectoring |= INTR_TYPE_EXT_INTR;
10026 vmcs12->idt_vectoring_info_field = idt_vectoring;
10030 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10032 struct vcpu_vmx *vmx = to_vmx(vcpu);
10034 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10035 vmx->nested.preemption_timer_expired) {
10036 if (vmx->nested.nested_run_pending)
10038 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10042 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10043 if (vmx->nested.nested_run_pending ||
10044 vcpu->arch.interrupt.pending)
10046 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10047 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10048 INTR_INFO_VALID_MASK, 0);
10050 * The NMI-triggered VM exit counts as injection:
10051 * clear this one and block further NMIs.
10053 vcpu->arch.nmi_pending = 0;
10054 vmx_set_nmi_mask(vcpu, true);
10058 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10059 nested_exit_on_intr(vcpu)) {
10060 if (vmx->nested.nested_run_pending)
10062 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10066 return vmx_complete_nested_posted_interrupt(vcpu);
10069 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10071 ktime_t remaining =
10072 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10075 if (ktime_to_ns(remaining) <= 0)
10078 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10079 do_div(value, 1000000);
10080 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10084 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10085 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10086 * and this function updates it to reflect the changes to the guest state while
10087 * L2 was running (and perhaps made some exits which were handled directly by L0
10088 * without going back to L1), and to reflect the exit reason.
10089 * Note that we do not have to copy here all VMCS fields, just those that
10090 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10091 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10092 * which already writes to vmcs12 directly.
10094 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10095 u32 exit_reason, u32 exit_intr_info,
10096 unsigned long exit_qualification)
10098 /* update guest state fields: */
10099 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10100 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10102 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10103 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10104 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10106 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10107 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10108 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10109 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10110 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10111 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10112 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10113 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10114 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10115 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10116 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10117 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10118 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10119 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10120 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10121 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10122 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10123 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10124 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10125 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10126 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10127 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10128 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10129 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10130 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10131 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10132 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10133 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10134 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10135 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10136 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10137 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10138 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10139 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10140 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10141 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10143 vmcs12->guest_interruptibility_info =
10144 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10145 vmcs12->guest_pending_dbg_exceptions =
10146 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10147 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10148 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10150 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10152 if (nested_cpu_has_preemption_timer(vmcs12)) {
10153 if (vmcs12->vm_exit_controls &
10154 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10155 vmcs12->vmx_preemption_timer_value =
10156 vmx_get_preemption_timer_value(vcpu);
10157 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10161 * In some cases (usually, nested EPT), L2 is allowed to change its
10162 * own CR3 without exiting. If it has changed it, we must keep it.
10163 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10164 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10166 * Additionally, restore L2's PDPTR to vmcs12.
10169 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10170 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10171 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10172 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10173 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10176 if (nested_cpu_has_vid(vmcs12))
10177 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10179 vmcs12->vm_entry_controls =
10180 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10181 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10183 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10184 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10185 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10188 /* TODO: These cannot have changed unless we have MSR bitmaps and
10189 * the relevant bit asks not to trap the change */
10190 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10191 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10192 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10193 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10194 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10195 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10196 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10197 if (vmx_mpx_supported())
10198 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10199 if (nested_cpu_has_xsaves(vmcs12))
10200 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10202 /* update exit information fields: */
10204 vmcs12->vm_exit_reason = exit_reason;
10205 vmcs12->exit_qualification = exit_qualification;
10207 vmcs12->vm_exit_intr_info = exit_intr_info;
10208 if ((vmcs12->vm_exit_intr_info &
10209 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10210 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10211 vmcs12->vm_exit_intr_error_code =
10212 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10213 vmcs12->idt_vectoring_info_field = 0;
10214 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10215 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10217 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10218 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10219 * instead of reading the real value. */
10220 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10223 * Transfer the event that L0 or L1 may wanted to inject into
10224 * L2 to IDT_VECTORING_INFO_FIELD.
10226 vmcs12_save_pending_event(vcpu, vmcs12);
10230 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10231 * preserved above and would only end up incorrectly in L1.
10233 vcpu->arch.nmi_injected = false;
10234 kvm_clear_exception_queue(vcpu);
10235 kvm_clear_interrupt_queue(vcpu);
10239 * A part of what we need to when the nested L2 guest exits and we want to
10240 * run its L1 parent, is to reset L1's guest state to the host state specified
10242 * This function is to be called not only on normal nested exit, but also on
10243 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10244 * Failures During or After Loading Guest State").
10245 * This function should be called when the active VMCS is L1's (vmcs01).
10247 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10248 struct vmcs12 *vmcs12)
10250 struct kvm_segment seg;
10252 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10253 vcpu->arch.efer = vmcs12->host_ia32_efer;
10254 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10255 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10257 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10258 vmx_set_efer(vcpu, vcpu->arch.efer);
10260 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10261 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10262 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10264 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10265 * actually changed, because it depends on the current state of
10266 * fpu_active (which may have changed).
10267 * Note that vmx_set_cr0 refers to efer set above.
10269 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10271 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10272 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10273 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10275 update_exception_bitmap(vcpu);
10276 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10277 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10280 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10281 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10283 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10284 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10286 nested_ept_uninit_mmu_context(vcpu);
10288 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10289 kvm_mmu_reset_context(vcpu);
10292 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10296 * Trivially support vpid by letting L2s share their parent
10297 * L1's vpid. TODO: move to a more elaborate solution, giving
10298 * each L2 its own vpid and exposing the vpid feature to L1.
10300 vmx_flush_tlb(vcpu);
10304 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10305 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10306 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10307 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10308 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10310 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10311 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10312 vmcs_write64(GUEST_BNDCFGS, 0);
10314 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10315 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10316 vcpu->arch.pat = vmcs12->host_ia32_pat;
10318 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10319 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10320 vmcs12->host_ia32_perf_global_ctrl);
10322 /* Set L1 segment info according to Intel SDM
10323 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10324 seg = (struct kvm_segment) {
10326 .limit = 0xFFFFFFFF,
10327 .selector = vmcs12->host_cs_selector,
10333 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10337 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10338 seg = (struct kvm_segment) {
10340 .limit = 0xFFFFFFFF,
10347 seg.selector = vmcs12->host_ds_selector;
10348 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10349 seg.selector = vmcs12->host_es_selector;
10350 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10351 seg.selector = vmcs12->host_ss_selector;
10352 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10353 seg.selector = vmcs12->host_fs_selector;
10354 seg.base = vmcs12->host_fs_base;
10355 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10356 seg.selector = vmcs12->host_gs_selector;
10357 seg.base = vmcs12->host_gs_base;
10358 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10359 seg = (struct kvm_segment) {
10360 .base = vmcs12->host_tr_base,
10362 .selector = vmcs12->host_tr_selector,
10366 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10368 kvm_set_dr(vcpu, 7, 0x400);
10369 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10371 if (cpu_has_vmx_msr_bitmap())
10372 vmx_set_msr_bitmap(vcpu);
10374 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10375 vmcs12->vm_exit_msr_load_count))
10376 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10380 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10381 * and modify vmcs12 to make it see what it would expect to see there if
10382 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10384 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10385 u32 exit_intr_info,
10386 unsigned long exit_qualification)
10388 struct vcpu_vmx *vmx = to_vmx(vcpu);
10389 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10391 /* trying to cancel vmlaunch/vmresume is a bug */
10392 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10394 leave_guest_mode(vcpu);
10395 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10396 exit_qualification);
10398 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10399 vmcs12->vm_exit_msr_store_count))
10400 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10402 vmx_load_vmcs01(vcpu);
10404 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10405 && nested_exit_intr_ack_set(vcpu)) {
10406 int irq = kvm_cpu_get_interrupt(vcpu);
10408 vmcs12->vm_exit_intr_info = irq |
10409 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10412 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10413 vmcs12->exit_qualification,
10414 vmcs12->idt_vectoring_info_field,
10415 vmcs12->vm_exit_intr_info,
10416 vmcs12->vm_exit_intr_error_code,
10419 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10420 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10421 vmx_segment_cache_clear(vmx);
10423 /* if no vmcs02 cache requested, remove the one we used */
10424 if (VMCS02_POOL_SIZE == 0)
10425 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10427 load_vmcs12_host_state(vcpu, vmcs12);
10429 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10430 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10432 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10435 /* Unpin physical memory we referred to in vmcs02 */
10436 if (vmx->nested.apic_access_page) {
10437 nested_release_page(vmx->nested.apic_access_page);
10438 vmx->nested.apic_access_page = NULL;
10440 if (vmx->nested.virtual_apic_page) {
10441 nested_release_page(vmx->nested.virtual_apic_page);
10442 vmx->nested.virtual_apic_page = NULL;
10444 if (vmx->nested.pi_desc_page) {
10445 kunmap(vmx->nested.pi_desc_page);
10446 nested_release_page(vmx->nested.pi_desc_page);
10447 vmx->nested.pi_desc_page = NULL;
10448 vmx->nested.pi_desc = NULL;
10452 * We are now running in L2, mmu_notifier will force to reload the
10453 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10455 kvm_vcpu_reload_apic_access_page(vcpu);
10458 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10459 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10460 * success or failure flag accordingly.
10462 if (unlikely(vmx->fail)) {
10464 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10466 nested_vmx_succeed(vcpu);
10467 if (enable_shadow_vmcs)
10468 vmx->nested.sync_shadow_vmcs = true;
10470 /* in case we halted in L2 */
10471 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10475 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10477 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10479 if (is_guest_mode(vcpu))
10480 nested_vmx_vmexit(vcpu, -1, 0, 0);
10481 free_nested(to_vmx(vcpu));
10485 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10486 * 23.7 "VM-entry failures during or after loading guest state" (this also
10487 * lists the acceptable exit-reason and exit-qualification parameters).
10488 * It should only be called before L2 actually succeeded to run, and when
10489 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10491 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10492 struct vmcs12 *vmcs12,
10493 u32 reason, unsigned long qualification)
10495 load_vmcs12_host_state(vcpu, vmcs12);
10496 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10497 vmcs12->exit_qualification = qualification;
10498 nested_vmx_succeed(vcpu);
10499 if (enable_shadow_vmcs)
10500 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10503 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10504 struct x86_instruction_info *info,
10505 enum x86_intercept_stage stage)
10507 return X86EMUL_CONTINUE;
10510 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10513 shrink_ple_window(vcpu);
10516 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10517 struct kvm_memory_slot *slot)
10519 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10520 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10523 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10524 struct kvm_memory_slot *slot)
10526 kvm_mmu_slot_set_dirty(kvm, slot);
10529 static void vmx_flush_log_dirty(struct kvm *kvm)
10531 kvm_flush_pml_buffers(kvm);
10534 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10535 struct kvm_memory_slot *memslot,
10536 gfn_t offset, unsigned long mask)
10538 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10542 * This routine does the following things for vCPU which is going
10543 * to be blocked if VT-d PI is enabled.
10544 * - Store the vCPU to the wakeup list, so when interrupts happen
10545 * we can find the right vCPU to wake up.
10546 * - Change the Posted-interrupt descriptor as below:
10547 * 'NDST' <-- vcpu->pre_pcpu
10548 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10549 * - If 'ON' is set during this process, which means at least one
10550 * interrupt is posted for this vCPU, we cannot block it, in
10551 * this case, return 1, otherwise, return 0.
10554 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10556 unsigned long flags;
10558 struct pi_desc old, new;
10559 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10561 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10562 !irq_remapping_cap(IRQ_POSTING_CAP))
10565 vcpu->pre_pcpu = vcpu->cpu;
10566 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10567 vcpu->pre_pcpu), flags);
10568 list_add_tail(&vcpu->blocked_vcpu_list,
10569 &per_cpu(blocked_vcpu_on_cpu,
10571 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10572 vcpu->pre_pcpu), flags);
10575 old.control = new.control = pi_desc->control;
10578 * We should not block the vCPU if
10579 * an interrupt is posted for it.
10581 if (pi_test_on(pi_desc) == 1) {
10582 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10583 vcpu->pre_pcpu), flags);
10584 list_del(&vcpu->blocked_vcpu_list);
10585 spin_unlock_irqrestore(
10586 &per_cpu(blocked_vcpu_on_cpu_lock,
10587 vcpu->pre_pcpu), flags);
10588 vcpu->pre_pcpu = -1;
10593 WARN((pi_desc->sn == 1),
10594 "Warning: SN field of posted-interrupts "
10595 "is set before blocking\n");
10598 * Since vCPU can be preempted during this process,
10599 * vcpu->cpu could be different with pre_pcpu, we
10600 * need to set pre_pcpu as the destination of wakeup
10601 * notification event, then we can find the right vCPU
10602 * to wakeup in wakeup handler if interrupts happen
10603 * when the vCPU is in blocked state.
10605 dest = cpu_physical_id(vcpu->pre_pcpu);
10607 if (x2apic_enabled())
10610 new.ndst = (dest << 8) & 0xFF00;
10612 /* set 'NV' to 'wakeup vector' */
10613 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10614 } while (cmpxchg(&pi_desc->control, old.control,
10615 new.control) != old.control);
10620 static void vmx_post_block(struct kvm_vcpu *vcpu)
10622 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10623 struct pi_desc old, new;
10625 unsigned long flags;
10627 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10628 !irq_remapping_cap(IRQ_POSTING_CAP))
10632 old.control = new.control = pi_desc->control;
10634 dest = cpu_physical_id(vcpu->cpu);
10636 if (x2apic_enabled())
10639 new.ndst = (dest << 8) & 0xFF00;
10641 /* Allow posting non-urgent interrupts */
10644 /* set 'NV' to 'notification vector' */
10645 new.nv = POSTED_INTR_VECTOR;
10646 } while (cmpxchg(&pi_desc->control, old.control,
10647 new.control) != old.control);
10649 if(vcpu->pre_pcpu != -1) {
10651 &per_cpu(blocked_vcpu_on_cpu_lock,
10652 vcpu->pre_pcpu), flags);
10653 list_del(&vcpu->blocked_vcpu_list);
10654 spin_unlock_irqrestore(
10655 &per_cpu(blocked_vcpu_on_cpu_lock,
10656 vcpu->pre_pcpu), flags);
10657 vcpu->pre_pcpu = -1;
10662 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10665 * @host_irq: host irq of the interrupt
10666 * @guest_irq: gsi of the interrupt
10667 * @set: set or unset PI
10668 * returns 0 on success, < 0 on failure
10670 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10671 uint32_t guest_irq, bool set)
10673 struct kvm_kernel_irq_routing_entry *e;
10674 struct kvm_irq_routing_table *irq_rt;
10675 struct kvm_lapic_irq irq;
10676 struct kvm_vcpu *vcpu;
10677 struct vcpu_data vcpu_info;
10678 int idx, ret = -EINVAL;
10680 if (!kvm_arch_has_assigned_device(kvm) ||
10681 !irq_remapping_cap(IRQ_POSTING_CAP))
10684 idx = srcu_read_lock(&kvm->irq_srcu);
10685 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10686 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10688 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10689 if (e->type != KVM_IRQ_ROUTING_MSI)
10692 * VT-d PI cannot support posting multicast/broadcast
10693 * interrupts to a vCPU, we still use interrupt remapping
10694 * for these kind of interrupts.
10696 * For lowest-priority interrupts, we only support
10697 * those with single CPU as the destination, e.g. user
10698 * configures the interrupts via /proc/irq or uses
10699 * irqbalance to make the interrupts single-CPU.
10701 * We will support full lowest-priority interrupt later.
10704 kvm_set_msi_irq(e, &irq);
10705 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10708 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10709 vcpu_info.vector = irq.vector;
10711 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10712 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10715 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10717 /* suppress notification event before unposting */
10718 pi_set_sn(vcpu_to_pi_desc(vcpu));
10719 ret = irq_set_vcpu_affinity(host_irq, NULL);
10720 pi_clear_sn(vcpu_to_pi_desc(vcpu));
10724 printk(KERN_INFO "%s: failed to update PI IRTE\n",
10732 srcu_read_unlock(&kvm->irq_srcu, idx);
10736 static struct kvm_x86_ops vmx_x86_ops = {
10737 .cpu_has_kvm_support = cpu_has_kvm_support,
10738 .disabled_by_bios = vmx_disabled_by_bios,
10739 .hardware_setup = hardware_setup,
10740 .hardware_unsetup = hardware_unsetup,
10741 .check_processor_compatibility = vmx_check_processor_compat,
10742 .hardware_enable = hardware_enable,
10743 .hardware_disable = hardware_disable,
10744 .cpu_has_accelerated_tpr = report_flexpriority,
10745 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10747 .vcpu_create = vmx_create_vcpu,
10748 .vcpu_free = vmx_free_vcpu,
10749 .vcpu_reset = vmx_vcpu_reset,
10751 .prepare_guest_switch = vmx_save_host_state,
10752 .vcpu_load = vmx_vcpu_load,
10753 .vcpu_put = vmx_vcpu_put,
10755 .update_db_bp_intercept = update_exception_bitmap,
10756 .get_msr = vmx_get_msr,
10757 .set_msr = vmx_set_msr,
10758 .get_segment_base = vmx_get_segment_base,
10759 .get_segment = vmx_get_segment,
10760 .set_segment = vmx_set_segment,
10761 .get_cpl = vmx_get_cpl,
10762 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10763 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10764 .decache_cr3 = vmx_decache_cr3,
10765 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10766 .set_cr0 = vmx_set_cr0,
10767 .set_cr3 = vmx_set_cr3,
10768 .set_cr4 = vmx_set_cr4,
10769 .set_efer = vmx_set_efer,
10770 .get_idt = vmx_get_idt,
10771 .set_idt = vmx_set_idt,
10772 .get_gdt = vmx_get_gdt,
10773 .set_gdt = vmx_set_gdt,
10774 .get_dr6 = vmx_get_dr6,
10775 .set_dr6 = vmx_set_dr6,
10776 .set_dr7 = vmx_set_dr7,
10777 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10778 .cache_reg = vmx_cache_reg,
10779 .get_rflags = vmx_get_rflags,
10780 .set_rflags = vmx_set_rflags,
10781 .fpu_activate = vmx_fpu_activate,
10782 .fpu_deactivate = vmx_fpu_deactivate,
10784 .tlb_flush = vmx_flush_tlb,
10786 .run = vmx_vcpu_run,
10787 .handle_exit = vmx_handle_exit,
10788 .skip_emulated_instruction = skip_emulated_instruction,
10789 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10790 .get_interrupt_shadow = vmx_get_interrupt_shadow,
10791 .patch_hypercall = vmx_patch_hypercall,
10792 .set_irq = vmx_inject_irq,
10793 .set_nmi = vmx_inject_nmi,
10794 .queue_exception = vmx_queue_exception,
10795 .cancel_injection = vmx_cancel_injection,
10796 .interrupt_allowed = vmx_interrupt_allowed,
10797 .nmi_allowed = vmx_nmi_allowed,
10798 .get_nmi_mask = vmx_get_nmi_mask,
10799 .set_nmi_mask = vmx_set_nmi_mask,
10800 .enable_nmi_window = enable_nmi_window,
10801 .enable_irq_window = enable_irq_window,
10802 .update_cr8_intercept = update_cr8_intercept,
10803 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10804 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10805 .cpu_uses_apicv = vmx_cpu_uses_apicv,
10806 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10807 .hwapic_irr_update = vmx_hwapic_irr_update,
10808 .hwapic_isr_update = vmx_hwapic_isr_update,
10809 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10810 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10812 .set_tss_addr = vmx_set_tss_addr,
10813 .get_tdp_level = get_ept_level,
10814 .get_mt_mask = vmx_get_mt_mask,
10816 .get_exit_info = vmx_get_exit_info,
10818 .get_lpage_level = vmx_get_lpage_level,
10820 .cpuid_update = vmx_cpuid_update,
10822 .rdtscp_supported = vmx_rdtscp_supported,
10823 .invpcid_supported = vmx_invpcid_supported,
10825 .set_supported_cpuid = vmx_set_supported_cpuid,
10827 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10829 .read_tsc_offset = vmx_read_tsc_offset,
10830 .write_tsc_offset = vmx_write_tsc_offset,
10831 .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10832 .read_l1_tsc = vmx_read_l1_tsc,
10834 .set_tdp_cr3 = vmx_set_cr3,
10836 .check_intercept = vmx_check_intercept,
10837 .handle_external_intr = vmx_handle_external_intr,
10838 .mpx_supported = vmx_mpx_supported,
10839 .xsaves_supported = vmx_xsaves_supported,
10841 .check_nested_events = vmx_check_nested_events,
10843 .sched_in = vmx_sched_in,
10845 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10846 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10847 .flush_log_dirty = vmx_flush_log_dirty,
10848 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10850 .pre_block = vmx_pre_block,
10851 .post_block = vmx_post_block,
10853 .pmu_ops = &intel_pmu_ops,
10855 .update_pi_irte = vmx_update_pi_irte,
10858 static int __init vmx_init(void)
10860 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10861 __alignof__(struct vcpu_vmx), THIS_MODULE);
10865 #ifdef CONFIG_KEXEC_CORE
10866 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10867 crash_vmclear_local_loaded_vmcss);
10873 static void __exit vmx_exit(void)
10875 #ifdef CONFIG_KEXEC_CORE
10876 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10883 module_init(vmx_init)
10884 module_exit(vmx_exit)