2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
53 #define CREATE_TRACE_POINTS
56 #include <asm/debugreg.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
97 bool kvm_has_tsc_control;
98 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99 u32 kvm_max_guest_tsc_khz;
100 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
102 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103 static u32 tsc_tolerance_ppm = 250;
104 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
106 #define KVM_NR_SHARED_MSRS 16
108 struct kvm_shared_msrs_global {
110 u32 msrs[KVM_NR_SHARED_MSRS];
113 struct kvm_shared_msrs {
114 struct user_return_notifier urn;
116 struct kvm_shared_msr_values {
119 } values[KVM_NR_SHARED_MSRS];
122 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123 static struct kvm_shared_msrs __percpu *shared_msrs;
125 struct kvm_stats_debugfs_item debugfs_entries[] = {
126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
138 { "hypercalls", VCPU_STAT(hypercalls) },
139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
146 { "irq_injections", VCPU_STAT(irq_injections) },
147 { "nmi_injections", VCPU_STAT(nmi_injections) },
148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
155 { "mmu_unsync", VM_STAT(mmu_unsync) },
156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
157 { "largepages", VM_STAT(lpages) },
161 u64 __read_mostly host_xcr0;
163 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
165 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
172 static void kvm_on_user_return(struct user_return_notifier *urn)
175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
177 struct kvm_shared_msr_values *values;
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
190 static void shared_msr_update(unsigned slot, u32 msr)
193 unsigned int cpu = smp_processor_id();
194 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
207 void kvm_define_shared_msr(unsigned slot, u32 msr)
209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
215 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
217 static void kvm_shared_msr_cpu_online(void)
221 for (i = 0; i < shared_msrs_global.nr; ++i)
222 shared_msr_update(i, shared_msrs_global.msrs[i]);
225 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
227 unsigned int cpu = smp_processor_id();
228 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
230 if (((value ^ smsr->values[slot].curr) & mask) == 0)
232 smsr->values[slot].curr = value;
233 wrmsrl(shared_msrs_global.msrs[slot], value);
234 if (!smsr->registered) {
235 smsr->urn.on_user_return = kvm_on_user_return;
236 user_return_notifier_register(&smsr->urn);
237 smsr->registered = true;
240 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
242 static void drop_user_return_notifiers(void *ignore)
244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
251 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
253 return vcpu->arch.apic_base;
255 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
257 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
259 /* TODO: reserve bits check */
260 kvm_lapic_set_base(vcpu, data);
262 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
264 asmlinkage void kvm_spurious_fault(void)
266 /* Fault while not rebooting. We want the trace. */
269 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
271 #define EXCPT_BENIGN 0
272 #define EXCPT_CONTRIBUTORY 1
275 static int exception_class(int vector)
285 return EXCPT_CONTRIBUTORY;
292 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
293 unsigned nr, bool has_error, u32 error_code,
299 kvm_make_request(KVM_REQ_EVENT, vcpu);
301 if (!vcpu->arch.exception.pending) {
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
307 vcpu->arch.exception.reinject = reinject;
311 /* to check exception */
312 prev_nr = vcpu->arch.exception.nr;
313 if (prev_nr == DF_VECTOR) {
314 /* triple fault -> shutdown */
315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
318 class1 = exception_class(prev_nr);
319 class2 = exception_class(nr);
320 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322 /* generate double fault per SDM Table 5-5 */
323 vcpu->arch.exception.pending = true;
324 vcpu->arch.exception.has_error_code = true;
325 vcpu->arch.exception.nr = DF_VECTOR;
326 vcpu->arch.exception.error_code = 0;
328 /* replace previous exception with a new one in a hope
329 that instruction re-execution will regenerate lost
334 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336 kvm_multiple_exception(vcpu, nr, false, 0, false);
338 EXPORT_SYMBOL_GPL(kvm_queue_exception);
340 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
342 kvm_multiple_exception(vcpu, nr, false, 0, true);
344 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
346 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
349 kvm_inject_gp(vcpu, 0);
351 kvm_x86_ops->skip_emulated_instruction(vcpu);
353 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
355 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
357 ++vcpu->stat.pf_guest;
358 vcpu->arch.cr2 = fault->address;
359 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
361 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
363 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
365 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
368 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
371 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
373 atomic_inc(&vcpu->arch.nmi_queued);
374 kvm_make_request(KVM_REQ_NMI, vcpu);
376 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
378 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380 kvm_multiple_exception(vcpu, nr, true, error_code, false);
382 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
384 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
386 kvm_multiple_exception(vcpu, nr, true, error_code, true);
388 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
391 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
392 * a #GP and return false.
394 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
396 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
398 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
401 EXPORT_SYMBOL_GPL(kvm_require_cpl);
404 * This function will be used to read from the physical memory of the currently
405 * running guest. The difference to kvm_read_guest_page is that this function
406 * can read from guest physical or from the guest's guest physical memory.
408 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409 gfn_t ngfn, void *data, int offset, int len,
415 ngpa = gfn_to_gpa(ngfn);
416 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417 if (real_gfn == UNMAPPED_GVA)
420 real_gfn = gpa_to_gfn(real_gfn);
422 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
424 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
426 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427 void *data, int offset, int len, u32 access)
429 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430 data, offset, len, access);
434 * Load the pae pdptrs. Return true is they are all valid.
436 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
438 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
442 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
444 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445 offset * sizeof(u64), sizeof(pdpte),
446 PFERR_USER_MASK|PFERR_WRITE_MASK);
451 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
452 if (is_present_gpte(pdpte[i]) &&
453 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
460 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
461 __set_bit(VCPU_EXREG_PDPTR,
462 (unsigned long *)&vcpu->arch.regs_avail);
463 __set_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_dirty);
469 EXPORT_SYMBOL_GPL(load_pdptrs);
471 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
473 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
479 if (is_long_mode(vcpu) || !is_pae(vcpu))
482 if (!test_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail))
486 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
488 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489 PFERR_USER_MASK | PFERR_WRITE_MASK);
492 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
498 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
500 unsigned long old_cr0 = kvm_read_cr0(vcpu);
501 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502 X86_CR0_CD | X86_CR0_NW;
507 if (cr0 & 0xffffffff00000000UL)
511 cr0 &= ~CR0_RESERVED_BITS;
513 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
516 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
519 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
521 if ((vcpu->arch.efer & EFER_LME)) {
526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
531 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
536 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
539 kvm_x86_ops->set_cr0(vcpu, cr0);
541 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
542 kvm_clear_async_pf_completion_queue(vcpu);
543 kvm_async_pf_hash_reset(vcpu);
546 if ((cr0 ^ old_cr0) & update_bits)
547 kvm_mmu_reset_context(vcpu);
550 EXPORT_SYMBOL_GPL(kvm_set_cr0);
552 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
554 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
556 EXPORT_SYMBOL_GPL(kvm_lmsw);
558 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
560 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
561 !vcpu->guest_xcr0_loaded) {
562 /* kvm_set_xcr() also depends on this */
563 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
564 vcpu->guest_xcr0_loaded = 1;
568 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
570 if (vcpu->guest_xcr0_loaded) {
571 if (vcpu->arch.xcr0 != host_xcr0)
572 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
573 vcpu->guest_xcr0_loaded = 0;
577 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
581 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
582 if (index != XCR_XFEATURE_ENABLED_MASK)
585 if (!(xcr0 & XSTATE_FP))
587 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
589 if (xcr0 & ~host_xcr0)
591 kvm_put_guest_xcr0(vcpu);
592 vcpu->arch.xcr0 = xcr0;
596 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
598 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
599 __kvm_set_xcr(vcpu, index, xcr)) {
600 kvm_inject_gp(vcpu, 0);
605 EXPORT_SYMBOL_GPL(kvm_set_xcr);
607 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
609 unsigned long old_cr4 = kvm_read_cr4(vcpu);
610 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
611 X86_CR4_PAE | X86_CR4_SMEP;
612 if (cr4 & CR4_RESERVED_BITS)
615 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
618 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
621 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
624 if (is_long_mode(vcpu)) {
625 if (!(cr4 & X86_CR4_PAE))
627 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
628 && ((cr4 ^ old_cr4) & pdptr_bits)
629 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
633 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
634 if (!guest_cpuid_has_pcid(vcpu))
637 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
638 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
642 if (kvm_x86_ops->set_cr4(vcpu, cr4))
645 if (((cr4 ^ old_cr4) & pdptr_bits) ||
646 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
647 kvm_mmu_reset_context(vcpu);
649 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
650 kvm_update_cpuid(vcpu);
654 EXPORT_SYMBOL_GPL(kvm_set_cr4);
656 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
658 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
659 kvm_mmu_sync_roots(vcpu);
660 kvm_mmu_flush_tlb(vcpu);
664 if (is_long_mode(vcpu)) {
665 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
666 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
669 if (cr3 & CR3_L_MODE_RESERVED_BITS)
673 if (cr3 & CR3_PAE_RESERVED_BITS)
675 if (is_paging(vcpu) &&
676 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
680 * We don't check reserved bits in nonpae mode, because
681 * this isn't enforced, and VMware depends on this.
686 * Does the new cr3 value map to physical memory? (Note, we
687 * catch an invalid cr3 even in real-mode, because it would
688 * cause trouble later on when we turn on paging anyway.)
690 * A real CPU would silently accept an invalid cr3 and would
691 * attempt to use it - with largely undefined (and often hard
692 * to debug) behavior on the guest side.
694 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
696 vcpu->arch.cr3 = cr3;
697 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
698 vcpu->arch.mmu.new_cr3(vcpu);
701 EXPORT_SYMBOL_GPL(kvm_set_cr3);
703 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
705 if (cr8 & CR8_RESERVED_BITS)
707 if (irqchip_in_kernel(vcpu->kvm))
708 kvm_lapic_set_tpr(vcpu, cr8);
710 vcpu->arch.cr8 = cr8;
713 EXPORT_SYMBOL_GPL(kvm_set_cr8);
715 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
717 if (irqchip_in_kernel(vcpu->kvm))
718 return kvm_lapic_get_cr8(vcpu);
720 return vcpu->arch.cr8;
722 EXPORT_SYMBOL_GPL(kvm_get_cr8);
724 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
728 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
729 dr7 = vcpu->arch.guest_debug_dr7;
731 dr7 = vcpu->arch.dr7;
732 kvm_x86_ops->set_dr7(vcpu, dr7);
733 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
736 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
740 vcpu->arch.db[dr] = val;
741 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
742 vcpu->arch.eff_db[dr] = val;
745 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
749 if (val & 0xffffffff00000000ULL)
751 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
754 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
758 if (val & 0xffffffff00000000ULL)
760 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
761 kvm_update_dr7(vcpu);
768 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
772 res = __kvm_set_dr(vcpu, dr, val);
774 kvm_queue_exception(vcpu, UD_VECTOR);
776 kvm_inject_gp(vcpu, 0);
780 EXPORT_SYMBOL_GPL(kvm_set_dr);
782 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
786 *val = vcpu->arch.db[dr];
789 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
793 *val = vcpu->arch.dr6;
796 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
800 *val = vcpu->arch.dr7;
807 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809 if (_kvm_get_dr(vcpu, dr, val)) {
810 kvm_queue_exception(vcpu, UD_VECTOR);
815 EXPORT_SYMBOL_GPL(kvm_get_dr);
817 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
819 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
823 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
826 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
827 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
830 EXPORT_SYMBOL_GPL(kvm_rdpmc);
833 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
834 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
836 * This list is modified at module load time to reflect the
837 * capabilities of the host cpu. This capabilities test skips MSRs that are
838 * kvm-specific. Those are put in the beginning of the list.
841 #define KVM_SAVE_MSRS_BEGIN 10
842 static u32 msrs_to_save[] = {
843 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
844 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
845 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
846 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
848 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
851 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
853 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
856 static unsigned num_msrs_to_save;
858 static const u32 emulated_msrs[] = {
860 MSR_IA32_TSCDEADLINE,
861 MSR_IA32_MISC_ENABLE,
866 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
868 if (efer & efer_reserved_bits)
871 if (efer & EFER_FFXSR) {
872 struct kvm_cpuid_entry2 *feat;
874 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
875 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
879 if (efer & EFER_SVME) {
880 struct kvm_cpuid_entry2 *feat;
882 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
883 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
889 EXPORT_SYMBOL_GPL(kvm_valid_efer);
891 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
893 u64 old_efer = vcpu->arch.efer;
895 if (!kvm_valid_efer(vcpu, efer))
899 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
903 efer |= vcpu->arch.efer & EFER_LMA;
905 kvm_x86_ops->set_efer(vcpu, efer);
907 /* Update reserved bits */
908 if ((efer ^ old_efer) & EFER_NX)
909 kvm_mmu_reset_context(vcpu);
914 void kvm_enable_efer_bits(u64 mask)
916 efer_reserved_bits &= ~mask;
918 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
922 * Writes msr value into into the appropriate "register".
923 * Returns 0 on success, non-0 otherwise.
924 * Assumes vcpu_load() was already called.
926 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
928 return kvm_x86_ops->set_msr(vcpu, msr);
932 * Adapt set_msr() to msr_io()'s calling convention
934 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
940 msr.host_initiated = true;
941 return kvm_set_msr(vcpu, &msr);
945 struct pvclock_gtod_data {
948 struct { /* extract of a clocksource struct */
956 /* open coded 'struct timespec' */
957 u64 monotonic_time_snsec;
958 time_t monotonic_time_sec;
961 static struct pvclock_gtod_data pvclock_gtod_data;
963 static void update_pvclock_gtod(struct timekeeper *tk)
965 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
967 write_seqcount_begin(&vdata->seq);
969 /* copy pvclock gtod data */
970 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
971 vdata->clock.cycle_last = tk->clock->cycle_last;
972 vdata->clock.mask = tk->clock->mask;
973 vdata->clock.mult = tk->mult;
974 vdata->clock.shift = tk->shift;
976 vdata->monotonic_time_sec = tk->xtime_sec
977 + tk->wall_to_monotonic.tv_sec;
978 vdata->monotonic_time_snsec = tk->xtime_nsec
979 + (tk->wall_to_monotonic.tv_nsec
981 while (vdata->monotonic_time_snsec >=
982 (((u64)NSEC_PER_SEC) << tk->shift)) {
983 vdata->monotonic_time_snsec -=
984 ((u64)NSEC_PER_SEC) << tk->shift;
985 vdata->monotonic_time_sec++;
988 write_seqcount_end(&vdata->seq);
993 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
997 struct pvclock_wall_clock wc;
998 struct timespec boot;
1003 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1008 ++version; /* first time write, random junk */
1012 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1015 * The guest calculates current wall clock time by adding
1016 * system time (updated by kvm_guest_time_update below) to the
1017 * wall clock specified here. guest system time equals host
1018 * system time for us, thus we must fill in host boot time here.
1022 if (kvm->arch.kvmclock_offset) {
1023 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1024 boot = timespec_sub(boot, ts);
1026 wc.sec = boot.tv_sec;
1027 wc.nsec = boot.tv_nsec;
1028 wc.version = version;
1030 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1033 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1036 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1038 uint32_t quotient, remainder;
1040 /* Don't try to replace with do_div(), this one calculates
1041 * "(dividend << 32) / divisor" */
1043 : "=a" (quotient), "=d" (remainder)
1044 : "0" (0), "1" (dividend), "r" (divisor) );
1048 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1049 s8 *pshift, u32 *pmultiplier)
1056 tps64 = base_khz * 1000LL;
1057 scaled64 = scaled_khz * 1000LL;
1058 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1063 tps32 = (uint32_t)tps64;
1064 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1065 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1073 *pmultiplier = div_frac(scaled64, tps32);
1075 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1076 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1079 static inline u64 get_kernel_ns(void)
1083 WARN_ON(preemptible());
1085 monotonic_to_bootbased(&ts);
1086 return timespec_to_ns(&ts);
1089 #ifdef CONFIG_X86_64
1090 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1093 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1094 unsigned long max_tsc_khz;
1096 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1098 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1099 vcpu->arch.virtual_tsc_shift);
1102 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1104 u64 v = (u64)khz * (1000000 + ppm);
1109 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1111 u32 thresh_lo, thresh_hi;
1112 int use_scaling = 0;
1114 /* tsc_khz can be zero if TSC calibration fails */
1115 if (this_tsc_khz == 0)
1118 /* Compute a scale to convert nanoseconds in TSC cycles */
1119 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1120 &vcpu->arch.virtual_tsc_shift,
1121 &vcpu->arch.virtual_tsc_mult);
1122 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1125 * Compute the variation in TSC rate which is acceptable
1126 * within the range of tolerance and decide if the
1127 * rate being applied is within that bounds of the hardware
1128 * rate. If so, no scaling or compensation need be done.
1130 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1131 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1132 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1133 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1136 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1139 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1141 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1142 vcpu->arch.virtual_tsc_mult,
1143 vcpu->arch.virtual_tsc_shift);
1144 tsc += vcpu->arch.this_tsc_write;
1148 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1150 #ifdef CONFIG_X86_64
1152 bool do_request = false;
1153 struct kvm_arch *ka = &vcpu->kvm->arch;
1154 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1156 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1157 atomic_read(&vcpu->kvm->online_vcpus));
1159 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1160 if (!ka->use_master_clock)
1163 if (!vcpus_matched && ka->use_master_clock)
1167 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1169 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1170 atomic_read(&vcpu->kvm->online_vcpus),
1171 ka->use_master_clock, gtod->clock.vclock_mode);
1175 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1177 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1178 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1181 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1183 struct kvm *kvm = vcpu->kvm;
1184 u64 offset, ns, elapsed;
1185 unsigned long flags;
1188 u64 data = msr->data;
1190 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1191 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1192 ns = get_kernel_ns();
1193 elapsed = ns - kvm->arch.last_tsc_nsec;
1195 if (vcpu->arch.virtual_tsc_khz) {
1196 /* n.b - signed multiplication and division required */
1197 usdiff = data - kvm->arch.last_tsc_write;
1198 #ifdef CONFIG_X86_64
1199 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1201 /* do_div() only does unsigned */
1202 asm("idivl %2; xor %%edx, %%edx"
1204 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1206 do_div(elapsed, 1000);
1211 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1214 * Special case: TSC write with a small delta (1 second) of virtual
1215 * cycle time against real time is interpreted as an attempt to
1216 * synchronize the CPU.
1218 * For a reliable TSC, we can match TSC offsets, and for an unstable
1219 * TSC, we add elapsed time in this computation. We could let the
1220 * compensation code attempt to catch up if we fall behind, but
1221 * it's better to try to match offsets from the beginning.
1223 if (usdiff < USEC_PER_SEC &&
1224 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1225 if (!check_tsc_unstable()) {
1226 offset = kvm->arch.cur_tsc_offset;
1227 pr_debug("kvm: matched tsc offset for %llu\n", data);
1229 u64 delta = nsec_to_cycles(vcpu, elapsed);
1231 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1232 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1237 * We split periods of matched TSC writes into generations.
1238 * For each generation, we track the original measured
1239 * nanosecond time, offset, and write, so if TSCs are in
1240 * sync, we can match exact offset, and if not, we can match
1241 * exact software computation in compute_guest_tsc()
1243 * These values are tracked in kvm->arch.cur_xxx variables.
1245 kvm->arch.cur_tsc_generation++;
1246 kvm->arch.cur_tsc_nsec = ns;
1247 kvm->arch.cur_tsc_write = data;
1248 kvm->arch.cur_tsc_offset = offset;
1250 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1251 kvm->arch.cur_tsc_generation, data);
1255 * We also track th most recent recorded KHZ, write and time to
1256 * allow the matching interval to be extended at each write.
1258 kvm->arch.last_tsc_nsec = ns;
1259 kvm->arch.last_tsc_write = data;
1260 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1262 /* Reset of TSC must disable overshoot protection below */
1263 vcpu->arch.hv_clock.tsc_timestamp = 0;
1264 vcpu->arch.last_guest_tsc = data;
1266 /* Keep track of which generation this VCPU has synchronized to */
1267 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1268 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1269 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1271 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1272 update_ia32_tsc_adjust_msr(vcpu, offset);
1273 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1274 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1276 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1278 kvm->arch.nr_vcpus_matched_tsc++;
1280 kvm->arch.nr_vcpus_matched_tsc = 0;
1282 kvm_track_tsc_matching(vcpu);
1283 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1286 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1288 #ifdef CONFIG_X86_64
1290 static cycle_t read_tsc(void)
1296 * Empirically, a fence (of type that depends on the CPU)
1297 * before rdtsc is enough to ensure that rdtsc is ordered
1298 * with respect to loads. The various CPU manuals are unclear
1299 * as to whether rdtsc can be reordered with later loads,
1300 * but no one has ever seen it happen.
1303 ret = (cycle_t)vget_cycles();
1305 last = pvclock_gtod_data.clock.cycle_last;
1307 if (likely(ret >= last))
1311 * GCC likes to generate cmov here, but this branch is extremely
1312 * predictable (it's just a funciton of time and the likely is
1313 * very likely) and there's a data dependence, so force GCC
1314 * to generate a branch instead. I don't barrier() because
1315 * we don't actually need a barrier, and if this function
1316 * ever gets inlined it will generate worse code.
1322 static inline u64 vgettsc(cycle_t *cycle_now)
1325 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1327 *cycle_now = read_tsc();
1329 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1330 return v * gtod->clock.mult;
1333 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1338 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1342 seq = read_seqcount_begin(>od->seq);
1343 mode = gtod->clock.vclock_mode;
1344 ts->tv_sec = gtod->monotonic_time_sec;
1345 ns = gtod->monotonic_time_snsec;
1346 ns += vgettsc(cycle_now);
1347 ns >>= gtod->clock.shift;
1348 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1349 timespec_add_ns(ts, ns);
1354 /* returns true if host is using tsc clocksource */
1355 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1359 /* checked again under seqlock below */
1360 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1363 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1366 monotonic_to_bootbased(&ts);
1367 *kernel_ns = timespec_to_ns(&ts);
1375 * Assuming a stable TSC across physical CPUS, and a stable TSC
1376 * across virtual CPUs, the following condition is possible.
1377 * Each numbered line represents an event visible to both
1378 * CPUs at the next numbered event.
1380 * "timespecX" represents host monotonic time. "tscX" represents
1383 * VCPU0 on CPU0 | VCPU1 on CPU1
1385 * 1. read timespec0,tsc0
1386 * 2. | timespec1 = timespec0 + N
1388 * 3. transition to guest | transition to guest
1389 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1390 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1391 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1393 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1396 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1398 * - 0 < N - M => M < N
1400 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1401 * always the case (the difference between two distinct xtime instances
1402 * might be smaller then the difference between corresponding TSC reads,
1403 * when updating guest vcpus pvclock areas).
1405 * To avoid that problem, do not allow visibility of distinct
1406 * system_timestamp/tsc_timestamp values simultaneously: use a master
1407 * copy of host monotonic time values. Update that master copy
1410 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1414 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1416 #ifdef CONFIG_X86_64
1417 struct kvm_arch *ka = &kvm->arch;
1419 bool host_tsc_clocksource, vcpus_matched;
1421 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1422 atomic_read(&kvm->online_vcpus));
1425 * If the host uses TSC clock, then passthrough TSC as stable
1428 host_tsc_clocksource = kvm_get_time_and_clockread(
1429 &ka->master_kernel_ns,
1430 &ka->master_cycle_now);
1432 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1434 if (ka->use_master_clock)
1435 atomic_set(&kvm_guest_has_master_clock, 1);
1437 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1438 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1443 static int kvm_guest_time_update(struct kvm_vcpu *v)
1445 unsigned long flags, this_tsc_khz;
1446 struct kvm_vcpu_arch *vcpu = &v->arch;
1447 struct kvm_arch *ka = &v->kvm->arch;
1448 s64 kernel_ns, max_kernel_ns;
1449 u64 tsc_timestamp, host_tsc;
1450 struct pvclock_vcpu_time_info guest_hv_clock;
1452 bool use_master_clock;
1458 * If the host uses TSC clock, then passthrough TSC as stable
1461 spin_lock(&ka->pvclock_gtod_sync_lock);
1462 use_master_clock = ka->use_master_clock;
1463 if (use_master_clock) {
1464 host_tsc = ka->master_cycle_now;
1465 kernel_ns = ka->master_kernel_ns;
1467 spin_unlock(&ka->pvclock_gtod_sync_lock);
1469 /* Keep irq disabled to prevent changes to the clock */
1470 local_irq_save(flags);
1471 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1472 if (unlikely(this_tsc_khz == 0)) {
1473 local_irq_restore(flags);
1474 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1477 if (!use_master_clock) {
1478 host_tsc = native_read_tsc();
1479 kernel_ns = get_kernel_ns();
1482 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1485 * We may have to catch up the TSC to match elapsed wall clock
1486 * time for two reasons, even if kvmclock is used.
1487 * 1) CPU could have been running below the maximum TSC rate
1488 * 2) Broken TSC compensation resets the base at each VCPU
1489 * entry to avoid unknown leaps of TSC even when running
1490 * again on the same CPU. This may cause apparent elapsed
1491 * time to disappear, and the guest to stand still or run
1494 if (vcpu->tsc_catchup) {
1495 u64 tsc = compute_guest_tsc(v, kernel_ns);
1496 if (tsc > tsc_timestamp) {
1497 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1498 tsc_timestamp = tsc;
1502 local_irq_restore(flags);
1504 if (!vcpu->pv_time_enabled)
1508 * Time as measured by the TSC may go backwards when resetting the base
1509 * tsc_timestamp. The reason for this is that the TSC resolution is
1510 * higher than the resolution of the other clock scales. Thus, many
1511 * possible measurments of the TSC correspond to one measurement of any
1512 * other clock, and so a spread of values is possible. This is not a
1513 * problem for the computation of the nanosecond clock; with TSC rates
1514 * around 1GHZ, there can only be a few cycles which correspond to one
1515 * nanosecond value, and any path through this code will inevitably
1516 * take longer than that. However, with the kernel_ns value itself,
1517 * the precision may be much lower, down to HZ granularity. If the
1518 * first sampling of TSC against kernel_ns ends in the low part of the
1519 * range, and the second in the high end of the range, we can get:
1521 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1523 * As the sampling errors potentially range in the thousands of cycles,
1524 * it is possible such a time value has already been observed by the
1525 * guest. To protect against this, we must compute the system time as
1526 * observed by the guest and ensure the new system time is greater.
1529 if (vcpu->hv_clock.tsc_timestamp) {
1530 max_kernel_ns = vcpu->last_guest_tsc -
1531 vcpu->hv_clock.tsc_timestamp;
1532 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1533 vcpu->hv_clock.tsc_to_system_mul,
1534 vcpu->hv_clock.tsc_shift);
1535 max_kernel_ns += vcpu->last_kernel_ns;
1538 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1539 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1540 &vcpu->hv_clock.tsc_shift,
1541 &vcpu->hv_clock.tsc_to_system_mul);
1542 vcpu->hw_tsc_khz = this_tsc_khz;
1545 /* with a master <monotonic time, tsc value> tuple,
1546 * pvclock clock reads always increase at the (scaled) rate
1547 * of guest TSC - no need to deal with sampling errors.
1549 if (!use_master_clock) {
1550 if (max_kernel_ns > kernel_ns)
1551 kernel_ns = max_kernel_ns;
1553 /* With all the info we got, fill in the values */
1554 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1555 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1556 vcpu->last_kernel_ns = kernel_ns;
1557 vcpu->last_guest_tsc = tsc_timestamp;
1560 * The interface expects us to write an even number signaling that the
1561 * update is finished. Since the guest won't see the intermediate
1562 * state, we just increase by 2 at the end.
1564 vcpu->hv_clock.version += 2;
1566 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1567 &guest_hv_clock, sizeof(guest_hv_clock))))
1570 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1571 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1573 if (vcpu->pvclock_set_guest_stopped_request) {
1574 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1575 vcpu->pvclock_set_guest_stopped_request = false;
1578 /* If the host uses TSC clocksource, then it is stable */
1579 if (use_master_clock)
1580 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1582 vcpu->hv_clock.flags = pvclock_flags;
1584 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1586 sizeof(vcpu->hv_clock));
1590 static bool msr_mtrr_valid(unsigned msr)
1593 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1594 case MSR_MTRRfix64K_00000:
1595 case MSR_MTRRfix16K_80000:
1596 case MSR_MTRRfix16K_A0000:
1597 case MSR_MTRRfix4K_C0000:
1598 case MSR_MTRRfix4K_C8000:
1599 case MSR_MTRRfix4K_D0000:
1600 case MSR_MTRRfix4K_D8000:
1601 case MSR_MTRRfix4K_E0000:
1602 case MSR_MTRRfix4K_E8000:
1603 case MSR_MTRRfix4K_F0000:
1604 case MSR_MTRRfix4K_F8000:
1605 case MSR_MTRRdefType:
1606 case MSR_IA32_CR_PAT:
1614 static bool valid_pat_type(unsigned t)
1616 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1619 static bool valid_mtrr_type(unsigned t)
1621 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1624 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1628 if (!msr_mtrr_valid(msr))
1631 if (msr == MSR_IA32_CR_PAT) {
1632 for (i = 0; i < 8; i++)
1633 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1636 } else if (msr == MSR_MTRRdefType) {
1639 return valid_mtrr_type(data & 0xff);
1640 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1641 for (i = 0; i < 8 ; i++)
1642 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1647 /* variable MTRRs */
1648 return valid_mtrr_type(data & 0xff);
1651 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1653 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1655 if (!mtrr_valid(vcpu, msr, data))
1658 if (msr == MSR_MTRRdefType) {
1659 vcpu->arch.mtrr_state.def_type = data;
1660 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1661 } else if (msr == MSR_MTRRfix64K_00000)
1663 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1664 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1665 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1666 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1667 else if (msr == MSR_IA32_CR_PAT)
1668 vcpu->arch.pat = data;
1669 else { /* Variable MTRRs */
1670 int idx, is_mtrr_mask;
1673 idx = (msr - 0x200) / 2;
1674 is_mtrr_mask = msr - 0x200 - 2 * idx;
1677 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1680 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1684 kvm_mmu_reset_context(vcpu);
1688 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1690 u64 mcg_cap = vcpu->arch.mcg_cap;
1691 unsigned bank_num = mcg_cap & 0xff;
1694 case MSR_IA32_MCG_STATUS:
1695 vcpu->arch.mcg_status = data;
1697 case MSR_IA32_MCG_CTL:
1698 if (!(mcg_cap & MCG_CTL_P))
1700 if (data != 0 && data != ~(u64)0)
1702 vcpu->arch.mcg_ctl = data;
1705 if (msr >= MSR_IA32_MC0_CTL &&
1706 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1707 u32 offset = msr - MSR_IA32_MC0_CTL;
1708 /* only 0 or all 1s can be written to IA32_MCi_CTL
1709 * some Linux kernels though clear bit 10 in bank 4 to
1710 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1711 * this to avoid an uncatched #GP in the guest
1713 if ((offset & 0x3) == 0 &&
1714 data != 0 && (data | (1 << 10)) != ~(u64)0)
1716 vcpu->arch.mce_banks[offset] = data;
1724 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1726 struct kvm *kvm = vcpu->kvm;
1727 int lm = is_long_mode(vcpu);
1728 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1729 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1730 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1731 : kvm->arch.xen_hvm_config.blob_size_32;
1732 u32 page_num = data & ~PAGE_MASK;
1733 u64 page_addr = data & PAGE_MASK;
1738 if (page_num >= blob_size)
1741 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1746 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1755 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1757 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1760 static bool kvm_hv_msr_partition_wide(u32 msr)
1764 case HV_X64_MSR_GUEST_OS_ID:
1765 case HV_X64_MSR_HYPERCALL:
1773 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1775 struct kvm *kvm = vcpu->kvm;
1778 case HV_X64_MSR_GUEST_OS_ID:
1779 kvm->arch.hv_guest_os_id = data;
1780 /* setting guest os id to zero disables hypercall page */
1781 if (!kvm->arch.hv_guest_os_id)
1782 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1784 case HV_X64_MSR_HYPERCALL: {
1789 /* if guest os id is not set hypercall should remain disabled */
1790 if (!kvm->arch.hv_guest_os_id)
1792 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1793 kvm->arch.hv_hypercall = data;
1796 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1797 addr = gfn_to_hva(kvm, gfn);
1798 if (kvm_is_error_hva(addr))
1800 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1801 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1802 if (__copy_to_user((void __user *)addr, instructions, 4))
1804 kvm->arch.hv_hypercall = data;
1808 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1809 "data 0x%llx\n", msr, data);
1815 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1818 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1821 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1822 vcpu->arch.hv_vapic = data;
1825 addr = gfn_to_hva(vcpu->kvm, data >>
1826 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1827 if (kvm_is_error_hva(addr))
1829 if (__clear_user((void __user *)addr, PAGE_SIZE))
1831 vcpu->arch.hv_vapic = data;
1834 case HV_X64_MSR_EOI:
1835 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1836 case HV_X64_MSR_ICR:
1837 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1838 case HV_X64_MSR_TPR:
1839 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1841 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1842 "data 0x%llx\n", msr, data);
1849 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1851 gpa_t gpa = data & ~0x3f;
1853 /* Bits 2:5 are reserved, Should be zero */
1857 vcpu->arch.apf.msr_val = data;
1859 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1860 kvm_clear_async_pf_completion_queue(vcpu);
1861 kvm_async_pf_hash_reset(vcpu);
1865 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1869 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1870 kvm_async_pf_wakeup_all(vcpu);
1874 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1876 vcpu->arch.pv_time_enabled = false;
1879 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1883 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1886 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1887 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1888 vcpu->arch.st.accum_steal = delta;
1891 static void record_steal_time(struct kvm_vcpu *vcpu)
1893 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1896 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1897 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1900 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1901 vcpu->arch.st.steal.version += 2;
1902 vcpu->arch.st.accum_steal = 0;
1904 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1905 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1908 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1911 u32 msr = msr_info->index;
1912 u64 data = msr_info->data;
1915 case MSR_AMD64_NB_CFG:
1916 case MSR_IA32_UCODE_REV:
1917 case MSR_IA32_UCODE_WRITE:
1918 case MSR_VM_HSAVE_PA:
1919 case MSR_AMD64_PATCH_LOADER:
1920 case MSR_AMD64_BU_CFG2:
1924 return set_efer(vcpu, data);
1926 data &= ~(u64)0x40; /* ignore flush filter disable */
1927 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1928 data &= ~(u64)0x8; /* ignore TLB cache disable */
1930 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1935 case MSR_FAM10H_MMIO_CONF_BASE:
1937 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1942 case MSR_IA32_DEBUGCTLMSR:
1944 /* We support the non-activated case already */
1946 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1947 /* Values other than LBR and BTF are vendor-specific,
1948 thus reserved and should throw a #GP */
1951 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1954 case 0x200 ... 0x2ff:
1955 return set_msr_mtrr(vcpu, msr, data);
1956 case MSR_IA32_APICBASE:
1957 kvm_set_apic_base(vcpu, data);
1959 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1960 return kvm_x2apic_msr_write(vcpu, msr, data);
1961 case MSR_IA32_TSCDEADLINE:
1962 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1964 case MSR_IA32_TSC_ADJUST:
1965 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1966 if (!msr_info->host_initiated) {
1967 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1968 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1970 vcpu->arch.ia32_tsc_adjust_msr = data;
1973 case MSR_IA32_MISC_ENABLE:
1974 vcpu->arch.ia32_misc_enable_msr = data;
1976 case MSR_KVM_WALL_CLOCK_NEW:
1977 case MSR_KVM_WALL_CLOCK:
1978 vcpu->kvm->arch.wall_clock = data;
1979 kvm_write_wall_clock(vcpu->kvm, data);
1981 case MSR_KVM_SYSTEM_TIME_NEW:
1982 case MSR_KVM_SYSTEM_TIME: {
1984 kvmclock_reset(vcpu);
1986 vcpu->arch.time = data;
1987 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1989 /* we verify if the enable bit is set... */
1993 gpa_offset = data & ~(PAGE_MASK | 1);
1995 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1996 &vcpu->arch.pv_time, data & ~1ULL,
1997 sizeof(struct pvclock_vcpu_time_info)))
1998 vcpu->arch.pv_time_enabled = false;
2000 vcpu->arch.pv_time_enabled = true;
2004 case MSR_KVM_ASYNC_PF_EN:
2005 if (kvm_pv_enable_async_pf(vcpu, data))
2008 case MSR_KVM_STEAL_TIME:
2010 if (unlikely(!sched_info_on()))
2013 if (data & KVM_STEAL_RESERVED_MASK)
2016 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2017 data & KVM_STEAL_VALID_BITS,
2018 sizeof(struct kvm_steal_time)))
2021 vcpu->arch.st.msr_val = data;
2023 if (!(data & KVM_MSR_ENABLED))
2026 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2029 accumulate_steal_time(vcpu);
2032 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2035 case MSR_KVM_PV_EOI_EN:
2036 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2040 case MSR_IA32_MCG_CTL:
2041 case MSR_IA32_MCG_STATUS:
2042 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2043 return set_msr_mce(vcpu, msr, data);
2045 /* Performance counters are not protected by a CPUID bit,
2046 * so we should check all of them in the generic path for the sake of
2047 * cross vendor migration.
2048 * Writing a zero into the event select MSRs disables them,
2049 * which we perfectly emulate ;-). Any other value should be at least
2050 * reported, some guests depend on them.
2052 case MSR_K7_EVNTSEL0:
2053 case MSR_K7_EVNTSEL1:
2054 case MSR_K7_EVNTSEL2:
2055 case MSR_K7_EVNTSEL3:
2057 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2058 "0x%x data 0x%llx\n", msr, data);
2060 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2061 * so we ignore writes to make it happy.
2063 case MSR_K7_PERFCTR0:
2064 case MSR_K7_PERFCTR1:
2065 case MSR_K7_PERFCTR2:
2066 case MSR_K7_PERFCTR3:
2067 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2068 "0x%x data 0x%llx\n", msr, data);
2070 case MSR_P6_PERFCTR0:
2071 case MSR_P6_PERFCTR1:
2073 case MSR_P6_EVNTSEL0:
2074 case MSR_P6_EVNTSEL1:
2075 if (kvm_pmu_msr(vcpu, msr))
2076 return kvm_pmu_set_msr(vcpu, msr_info);
2078 if (pr || data != 0)
2079 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2080 "0x%x data 0x%llx\n", msr, data);
2082 case MSR_K7_CLK_CTL:
2084 * Ignore all writes to this no longer documented MSR.
2085 * Writes are only relevant for old K7 processors,
2086 * all pre-dating SVM, but a recommended workaround from
2087 * AMD for these chips. It is possible to specify the
2088 * affected processor models on the command line, hence
2089 * the need to ignore the workaround.
2092 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2093 if (kvm_hv_msr_partition_wide(msr)) {
2095 mutex_lock(&vcpu->kvm->lock);
2096 r = set_msr_hyperv_pw(vcpu, msr, data);
2097 mutex_unlock(&vcpu->kvm->lock);
2100 return set_msr_hyperv(vcpu, msr, data);
2102 case MSR_IA32_BBL_CR_CTL3:
2103 /* Drop writes to this legacy MSR -- see rdmsr
2104 * counterpart for further detail.
2106 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2108 case MSR_AMD64_OSVW_ID_LENGTH:
2109 if (!guest_cpuid_has_osvw(vcpu))
2111 vcpu->arch.osvw.length = data;
2113 case MSR_AMD64_OSVW_STATUS:
2114 if (!guest_cpuid_has_osvw(vcpu))
2116 vcpu->arch.osvw.status = data;
2119 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2120 return xen_hvm_config(vcpu, data);
2121 if (kvm_pmu_msr(vcpu, msr))
2122 return kvm_pmu_set_msr(vcpu, msr_info);
2124 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2128 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2135 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2139 * Reads an msr value (of 'msr_index') into 'pdata'.
2140 * Returns 0 on success, non-0 otherwise.
2141 * Assumes vcpu_load() was already called.
2143 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2145 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2148 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2150 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2152 if (!msr_mtrr_valid(msr))
2155 if (msr == MSR_MTRRdefType)
2156 *pdata = vcpu->arch.mtrr_state.def_type +
2157 (vcpu->arch.mtrr_state.enabled << 10);
2158 else if (msr == MSR_MTRRfix64K_00000)
2160 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2161 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2162 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2163 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2164 else if (msr == MSR_IA32_CR_PAT)
2165 *pdata = vcpu->arch.pat;
2166 else { /* Variable MTRRs */
2167 int idx, is_mtrr_mask;
2170 idx = (msr - 0x200) / 2;
2171 is_mtrr_mask = msr - 0x200 - 2 * idx;
2174 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2177 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2184 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2187 u64 mcg_cap = vcpu->arch.mcg_cap;
2188 unsigned bank_num = mcg_cap & 0xff;
2191 case MSR_IA32_P5_MC_ADDR:
2192 case MSR_IA32_P5_MC_TYPE:
2195 case MSR_IA32_MCG_CAP:
2196 data = vcpu->arch.mcg_cap;
2198 case MSR_IA32_MCG_CTL:
2199 if (!(mcg_cap & MCG_CTL_P))
2201 data = vcpu->arch.mcg_ctl;
2203 case MSR_IA32_MCG_STATUS:
2204 data = vcpu->arch.mcg_status;
2207 if (msr >= MSR_IA32_MC0_CTL &&
2208 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2209 u32 offset = msr - MSR_IA32_MC0_CTL;
2210 data = vcpu->arch.mce_banks[offset];
2219 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2222 struct kvm *kvm = vcpu->kvm;
2225 case HV_X64_MSR_GUEST_OS_ID:
2226 data = kvm->arch.hv_guest_os_id;
2228 case HV_X64_MSR_HYPERCALL:
2229 data = kvm->arch.hv_hypercall;
2232 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2240 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2245 case HV_X64_MSR_VP_INDEX: {
2248 kvm_for_each_vcpu(r, v, vcpu->kvm)
2253 case HV_X64_MSR_EOI:
2254 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2255 case HV_X64_MSR_ICR:
2256 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2257 case HV_X64_MSR_TPR:
2258 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2259 case HV_X64_MSR_APIC_ASSIST_PAGE:
2260 data = vcpu->arch.hv_vapic;
2263 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2270 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2275 case MSR_IA32_PLATFORM_ID:
2276 case MSR_IA32_EBL_CR_POWERON:
2277 case MSR_IA32_DEBUGCTLMSR:
2278 case MSR_IA32_LASTBRANCHFROMIP:
2279 case MSR_IA32_LASTBRANCHTOIP:
2280 case MSR_IA32_LASTINTFROMIP:
2281 case MSR_IA32_LASTINTTOIP:
2284 case MSR_VM_HSAVE_PA:
2285 case MSR_K7_EVNTSEL0:
2286 case MSR_K7_PERFCTR0:
2287 case MSR_K8_INT_PENDING_MSG:
2288 case MSR_AMD64_NB_CFG:
2289 case MSR_FAM10H_MMIO_CONF_BASE:
2290 case MSR_AMD64_BU_CFG2:
2293 case MSR_P6_PERFCTR0:
2294 case MSR_P6_PERFCTR1:
2295 case MSR_P6_EVNTSEL0:
2296 case MSR_P6_EVNTSEL1:
2297 if (kvm_pmu_msr(vcpu, msr))
2298 return kvm_pmu_get_msr(vcpu, msr, pdata);
2301 case MSR_IA32_UCODE_REV:
2302 data = 0x100000000ULL;
2305 data = 0x500 | KVM_NR_VAR_MTRR;
2307 case 0x200 ... 0x2ff:
2308 return get_msr_mtrr(vcpu, msr, pdata);
2309 case 0xcd: /* fsb frequency */
2313 * MSR_EBC_FREQUENCY_ID
2314 * Conservative value valid for even the basic CPU models.
2315 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2316 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2317 * and 266MHz for model 3, or 4. Set Core Clock
2318 * Frequency to System Bus Frequency Ratio to 1 (bits
2319 * 31:24) even though these are only valid for CPU
2320 * models > 2, however guests may end up dividing or
2321 * multiplying by zero otherwise.
2323 case MSR_EBC_FREQUENCY_ID:
2326 case MSR_IA32_APICBASE:
2327 data = kvm_get_apic_base(vcpu);
2329 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2330 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2332 case MSR_IA32_TSCDEADLINE:
2333 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2335 case MSR_IA32_TSC_ADJUST:
2336 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2338 case MSR_IA32_MISC_ENABLE:
2339 data = vcpu->arch.ia32_misc_enable_msr;
2341 case MSR_IA32_PERF_STATUS:
2342 /* TSC increment by tick */
2344 /* CPU multiplier */
2345 data |= (((uint64_t)4ULL) << 40);
2348 data = vcpu->arch.efer;
2350 case MSR_KVM_WALL_CLOCK:
2351 case MSR_KVM_WALL_CLOCK_NEW:
2352 data = vcpu->kvm->arch.wall_clock;
2354 case MSR_KVM_SYSTEM_TIME:
2355 case MSR_KVM_SYSTEM_TIME_NEW:
2356 data = vcpu->arch.time;
2358 case MSR_KVM_ASYNC_PF_EN:
2359 data = vcpu->arch.apf.msr_val;
2361 case MSR_KVM_STEAL_TIME:
2362 data = vcpu->arch.st.msr_val;
2364 case MSR_KVM_PV_EOI_EN:
2365 data = vcpu->arch.pv_eoi.msr_val;
2367 case MSR_IA32_P5_MC_ADDR:
2368 case MSR_IA32_P5_MC_TYPE:
2369 case MSR_IA32_MCG_CAP:
2370 case MSR_IA32_MCG_CTL:
2371 case MSR_IA32_MCG_STATUS:
2372 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2373 return get_msr_mce(vcpu, msr, pdata);
2374 case MSR_K7_CLK_CTL:
2376 * Provide expected ramp-up count for K7. All other
2377 * are set to zero, indicating minimum divisors for
2380 * This prevents guest kernels on AMD host with CPU
2381 * type 6, model 8 and higher from exploding due to
2382 * the rdmsr failing.
2386 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2387 if (kvm_hv_msr_partition_wide(msr)) {
2389 mutex_lock(&vcpu->kvm->lock);
2390 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2391 mutex_unlock(&vcpu->kvm->lock);
2394 return get_msr_hyperv(vcpu, msr, pdata);
2396 case MSR_IA32_BBL_CR_CTL3:
2397 /* This legacy MSR exists but isn't fully documented in current
2398 * silicon. It is however accessed by winxp in very narrow
2399 * scenarios where it sets bit #19, itself documented as
2400 * a "reserved" bit. Best effort attempt to source coherent
2401 * read data here should the balance of the register be
2402 * interpreted by the guest:
2404 * L2 cache control register 3: 64GB range, 256KB size,
2405 * enabled, latency 0x1, configured
2409 case MSR_AMD64_OSVW_ID_LENGTH:
2410 if (!guest_cpuid_has_osvw(vcpu))
2412 data = vcpu->arch.osvw.length;
2414 case MSR_AMD64_OSVW_STATUS:
2415 if (!guest_cpuid_has_osvw(vcpu))
2417 data = vcpu->arch.osvw.status;
2420 if (kvm_pmu_msr(vcpu, msr))
2421 return kvm_pmu_get_msr(vcpu, msr, pdata);
2423 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2426 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2434 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2437 * Read or write a bunch of msrs. All parameters are kernel addresses.
2439 * @return number of msrs set successfully.
2441 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2442 struct kvm_msr_entry *entries,
2443 int (*do_msr)(struct kvm_vcpu *vcpu,
2444 unsigned index, u64 *data))
2448 idx = srcu_read_lock(&vcpu->kvm->srcu);
2449 for (i = 0; i < msrs->nmsrs; ++i)
2450 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2452 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2458 * Read or write a bunch of msrs. Parameters are user addresses.
2460 * @return number of msrs set successfully.
2462 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2463 int (*do_msr)(struct kvm_vcpu *vcpu,
2464 unsigned index, u64 *data),
2467 struct kvm_msrs msrs;
2468 struct kvm_msr_entry *entries;
2473 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2477 if (msrs.nmsrs >= MAX_IO_MSRS)
2480 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2481 entries = memdup_user(user_msrs->entries, size);
2482 if (IS_ERR(entries)) {
2483 r = PTR_ERR(entries);
2487 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2492 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2503 int kvm_dev_ioctl_check_extension(long ext)
2508 case KVM_CAP_IRQCHIP:
2510 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2511 case KVM_CAP_SET_TSS_ADDR:
2512 case KVM_CAP_EXT_CPUID:
2513 case KVM_CAP_CLOCKSOURCE:
2515 case KVM_CAP_NOP_IO_DELAY:
2516 case KVM_CAP_MP_STATE:
2517 case KVM_CAP_SYNC_MMU:
2518 case KVM_CAP_USER_NMI:
2519 case KVM_CAP_REINJECT_CONTROL:
2520 case KVM_CAP_IRQ_INJECT_STATUS:
2522 case KVM_CAP_IOEVENTFD:
2524 case KVM_CAP_PIT_STATE2:
2525 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2526 case KVM_CAP_XEN_HVM:
2527 case KVM_CAP_ADJUST_CLOCK:
2528 case KVM_CAP_VCPU_EVENTS:
2529 case KVM_CAP_HYPERV:
2530 case KVM_CAP_HYPERV_VAPIC:
2531 case KVM_CAP_HYPERV_SPIN:
2532 case KVM_CAP_PCI_SEGMENT:
2533 case KVM_CAP_DEBUGREGS:
2534 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2536 case KVM_CAP_ASYNC_PF:
2537 case KVM_CAP_GET_TSC_KHZ:
2538 case KVM_CAP_KVMCLOCK_CTRL:
2539 case KVM_CAP_READONLY_MEM:
2540 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2541 case KVM_CAP_ASSIGN_DEV_IRQ:
2542 case KVM_CAP_PCI_2_3:
2546 case KVM_CAP_COALESCED_MMIO:
2547 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2550 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2552 case KVM_CAP_NR_VCPUS:
2553 r = KVM_SOFT_MAX_VCPUS;
2555 case KVM_CAP_MAX_VCPUS:
2558 case KVM_CAP_NR_MEMSLOTS:
2559 r = KVM_USER_MEM_SLOTS;
2561 case KVM_CAP_PV_MMU: /* obsolete */
2564 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2566 r = iommu_present(&pci_bus_type);
2570 r = KVM_MAX_MCE_BANKS;
2575 case KVM_CAP_TSC_CONTROL:
2576 r = kvm_has_tsc_control;
2578 case KVM_CAP_TSC_DEADLINE_TIMER:
2579 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2589 long kvm_arch_dev_ioctl(struct file *filp,
2590 unsigned int ioctl, unsigned long arg)
2592 void __user *argp = (void __user *)arg;
2596 case KVM_GET_MSR_INDEX_LIST: {
2597 struct kvm_msr_list __user *user_msr_list = argp;
2598 struct kvm_msr_list msr_list;
2602 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2605 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2606 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2609 if (n < msr_list.nmsrs)
2612 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2613 num_msrs_to_save * sizeof(u32)))
2615 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2617 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2622 case KVM_GET_SUPPORTED_CPUID: {
2623 struct kvm_cpuid2 __user *cpuid_arg = argp;
2624 struct kvm_cpuid2 cpuid;
2627 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2629 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2630 cpuid_arg->entries);
2635 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2640 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2643 mce_cap = KVM_MCE_CAP_SUPPORTED;
2645 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2657 static void wbinvd_ipi(void *garbage)
2662 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2664 return vcpu->kvm->arch.iommu_domain &&
2665 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2668 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2670 /* Address WBINVD may be executed by guest */
2671 if (need_emulate_wbinvd(vcpu)) {
2672 if (kvm_x86_ops->has_wbinvd_exit())
2673 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2674 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2675 smp_call_function_single(vcpu->cpu,
2676 wbinvd_ipi, NULL, 1);
2679 kvm_x86_ops->vcpu_load(vcpu, cpu);
2681 /* Apply any externally detected TSC adjustments (due to suspend) */
2682 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2683 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2684 vcpu->arch.tsc_offset_adjustment = 0;
2685 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2688 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2689 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2690 native_read_tsc() - vcpu->arch.last_host_tsc;
2692 mark_tsc_unstable("KVM discovered backwards TSC");
2693 if (check_tsc_unstable()) {
2694 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2695 vcpu->arch.last_guest_tsc);
2696 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2697 vcpu->arch.tsc_catchup = 1;
2700 * On a host with synchronized TSC, there is no need to update
2701 * kvmclock on vcpu->cpu migration
2703 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2704 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2705 if (vcpu->cpu != cpu)
2706 kvm_migrate_timers(vcpu);
2710 accumulate_steal_time(vcpu);
2711 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2714 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2716 kvm_x86_ops->vcpu_put(vcpu);
2717 kvm_put_guest_fpu(vcpu);
2718 vcpu->arch.last_host_tsc = native_read_tsc();
2721 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2722 struct kvm_lapic_state *s)
2724 kvm_x86_ops->sync_pir_to_irr(vcpu);
2725 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2730 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2731 struct kvm_lapic_state *s)
2733 kvm_apic_post_state_restore(vcpu, s);
2734 update_cr8_intercept(vcpu);
2739 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2740 struct kvm_interrupt *irq)
2742 if (irq->irq >= KVM_NR_INTERRUPTS)
2744 if (irqchip_in_kernel(vcpu->kvm))
2747 kvm_queue_interrupt(vcpu, irq->irq, false);
2748 kvm_make_request(KVM_REQ_EVENT, vcpu);
2753 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2755 kvm_inject_nmi(vcpu);
2760 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2761 struct kvm_tpr_access_ctl *tac)
2765 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2769 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2773 unsigned bank_num = mcg_cap & 0xff, bank;
2776 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2778 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2781 vcpu->arch.mcg_cap = mcg_cap;
2782 /* Init IA32_MCG_CTL to all 1s */
2783 if (mcg_cap & MCG_CTL_P)
2784 vcpu->arch.mcg_ctl = ~(u64)0;
2785 /* Init IA32_MCi_CTL to all 1s */
2786 for (bank = 0; bank < bank_num; bank++)
2787 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2792 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2793 struct kvm_x86_mce *mce)
2795 u64 mcg_cap = vcpu->arch.mcg_cap;
2796 unsigned bank_num = mcg_cap & 0xff;
2797 u64 *banks = vcpu->arch.mce_banks;
2799 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2802 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2803 * reporting is disabled
2805 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2806 vcpu->arch.mcg_ctl != ~(u64)0)
2808 banks += 4 * mce->bank;
2810 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2811 * reporting is disabled for the bank
2813 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2815 if (mce->status & MCI_STATUS_UC) {
2816 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2817 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2818 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2821 if (banks[1] & MCI_STATUS_VAL)
2822 mce->status |= MCI_STATUS_OVER;
2823 banks[2] = mce->addr;
2824 banks[3] = mce->misc;
2825 vcpu->arch.mcg_status = mce->mcg_status;
2826 banks[1] = mce->status;
2827 kvm_queue_exception(vcpu, MC_VECTOR);
2828 } else if (!(banks[1] & MCI_STATUS_VAL)
2829 || !(banks[1] & MCI_STATUS_UC)) {
2830 if (banks[1] & MCI_STATUS_VAL)
2831 mce->status |= MCI_STATUS_OVER;
2832 banks[2] = mce->addr;
2833 banks[3] = mce->misc;
2834 banks[1] = mce->status;
2836 banks[1] |= MCI_STATUS_OVER;
2840 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2841 struct kvm_vcpu_events *events)
2844 events->exception.injected =
2845 vcpu->arch.exception.pending &&
2846 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2847 events->exception.nr = vcpu->arch.exception.nr;
2848 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2849 events->exception.pad = 0;
2850 events->exception.error_code = vcpu->arch.exception.error_code;
2852 events->interrupt.injected =
2853 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2854 events->interrupt.nr = vcpu->arch.interrupt.nr;
2855 events->interrupt.soft = 0;
2856 events->interrupt.shadow =
2857 kvm_x86_ops->get_interrupt_shadow(vcpu,
2858 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2860 events->nmi.injected = vcpu->arch.nmi_injected;
2861 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2862 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2863 events->nmi.pad = 0;
2865 events->sipi_vector = 0; /* never valid when reporting to user space */
2867 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2868 | KVM_VCPUEVENT_VALID_SHADOW);
2869 memset(&events->reserved, 0, sizeof(events->reserved));
2872 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2873 struct kvm_vcpu_events *events)
2875 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2876 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2877 | KVM_VCPUEVENT_VALID_SHADOW))
2881 vcpu->arch.exception.pending = events->exception.injected;
2882 vcpu->arch.exception.nr = events->exception.nr;
2883 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2884 vcpu->arch.exception.error_code = events->exception.error_code;
2886 vcpu->arch.interrupt.pending = events->interrupt.injected;
2887 vcpu->arch.interrupt.nr = events->interrupt.nr;
2888 vcpu->arch.interrupt.soft = events->interrupt.soft;
2889 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2890 kvm_x86_ops->set_interrupt_shadow(vcpu,
2891 events->interrupt.shadow);
2893 vcpu->arch.nmi_injected = events->nmi.injected;
2894 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2895 vcpu->arch.nmi_pending = events->nmi.pending;
2896 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2898 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2899 kvm_vcpu_has_lapic(vcpu))
2900 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2902 kvm_make_request(KVM_REQ_EVENT, vcpu);
2907 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2908 struct kvm_debugregs *dbgregs)
2910 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2911 dbgregs->dr6 = vcpu->arch.dr6;
2912 dbgregs->dr7 = vcpu->arch.dr7;
2914 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2917 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2918 struct kvm_debugregs *dbgregs)
2923 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2924 vcpu->arch.dr6 = dbgregs->dr6;
2925 vcpu->arch.dr7 = dbgregs->dr7;
2930 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2931 struct kvm_xsave *guest_xsave)
2934 memcpy(guest_xsave->region,
2935 &vcpu->arch.guest_fpu.state->xsave,
2938 memcpy(guest_xsave->region,
2939 &vcpu->arch.guest_fpu.state->fxsave,
2940 sizeof(struct i387_fxsave_struct));
2941 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2946 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2947 struct kvm_xsave *guest_xsave)
2950 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2953 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2954 guest_xsave->region, xstate_size);
2956 if (xstate_bv & ~XSTATE_FPSSE)
2958 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2959 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2964 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2965 struct kvm_xcrs *guest_xcrs)
2967 if (!cpu_has_xsave) {
2968 guest_xcrs->nr_xcrs = 0;
2972 guest_xcrs->nr_xcrs = 1;
2973 guest_xcrs->flags = 0;
2974 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2975 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2978 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2979 struct kvm_xcrs *guest_xcrs)
2986 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2989 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2990 /* Only support XCR0 currently */
2991 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2992 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2993 guest_xcrs->xcrs[0].value);
3002 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3003 * stopped by the hypervisor. This function will be called from the host only.
3004 * EINVAL is returned when the host attempts to set the flag for a guest that
3005 * does not support pv clocks.
3007 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3009 if (!vcpu->arch.pv_time_enabled)
3011 vcpu->arch.pvclock_set_guest_stopped_request = true;
3012 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3016 long kvm_arch_vcpu_ioctl(struct file *filp,
3017 unsigned int ioctl, unsigned long arg)
3019 struct kvm_vcpu *vcpu = filp->private_data;
3020 void __user *argp = (void __user *)arg;
3023 struct kvm_lapic_state *lapic;
3024 struct kvm_xsave *xsave;
3025 struct kvm_xcrs *xcrs;
3031 case KVM_GET_LAPIC: {
3033 if (!vcpu->arch.apic)
3035 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3040 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3044 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3049 case KVM_SET_LAPIC: {
3051 if (!vcpu->arch.apic)
3053 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3054 if (IS_ERR(u.lapic))
3055 return PTR_ERR(u.lapic);
3057 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3060 case KVM_INTERRUPT: {
3061 struct kvm_interrupt irq;
3064 if (copy_from_user(&irq, argp, sizeof irq))
3066 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3070 r = kvm_vcpu_ioctl_nmi(vcpu);
3073 case KVM_SET_CPUID: {
3074 struct kvm_cpuid __user *cpuid_arg = argp;
3075 struct kvm_cpuid cpuid;
3078 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3080 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3083 case KVM_SET_CPUID2: {
3084 struct kvm_cpuid2 __user *cpuid_arg = argp;
3085 struct kvm_cpuid2 cpuid;
3088 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3090 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3091 cpuid_arg->entries);
3094 case KVM_GET_CPUID2: {
3095 struct kvm_cpuid2 __user *cpuid_arg = argp;
3096 struct kvm_cpuid2 cpuid;
3099 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3101 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3102 cpuid_arg->entries);
3106 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3112 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3115 r = msr_io(vcpu, argp, do_set_msr, 0);
3117 case KVM_TPR_ACCESS_REPORTING: {
3118 struct kvm_tpr_access_ctl tac;
3121 if (copy_from_user(&tac, argp, sizeof tac))
3123 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3127 if (copy_to_user(argp, &tac, sizeof tac))
3132 case KVM_SET_VAPIC_ADDR: {
3133 struct kvm_vapic_addr va;
3136 if (!irqchip_in_kernel(vcpu->kvm))
3139 if (copy_from_user(&va, argp, sizeof va))
3141 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3144 case KVM_X86_SETUP_MCE: {
3148 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3150 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3153 case KVM_X86_SET_MCE: {
3154 struct kvm_x86_mce mce;
3157 if (copy_from_user(&mce, argp, sizeof mce))
3159 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3162 case KVM_GET_VCPU_EVENTS: {
3163 struct kvm_vcpu_events events;
3165 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3168 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3173 case KVM_SET_VCPU_EVENTS: {
3174 struct kvm_vcpu_events events;
3177 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3180 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3183 case KVM_GET_DEBUGREGS: {
3184 struct kvm_debugregs dbgregs;
3186 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3189 if (copy_to_user(argp, &dbgregs,
3190 sizeof(struct kvm_debugregs)))
3195 case KVM_SET_DEBUGREGS: {
3196 struct kvm_debugregs dbgregs;
3199 if (copy_from_user(&dbgregs, argp,
3200 sizeof(struct kvm_debugregs)))
3203 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3206 case KVM_GET_XSAVE: {
3207 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3212 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3215 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3220 case KVM_SET_XSAVE: {
3221 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3222 if (IS_ERR(u.xsave))
3223 return PTR_ERR(u.xsave);
3225 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3228 case KVM_GET_XCRS: {
3229 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3234 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3237 if (copy_to_user(argp, u.xcrs,
3238 sizeof(struct kvm_xcrs)))
3243 case KVM_SET_XCRS: {
3244 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3246 return PTR_ERR(u.xcrs);
3248 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3251 case KVM_SET_TSC_KHZ: {
3255 user_tsc_khz = (u32)arg;
3257 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3260 if (user_tsc_khz == 0)
3261 user_tsc_khz = tsc_khz;
3263 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3268 case KVM_GET_TSC_KHZ: {
3269 r = vcpu->arch.virtual_tsc_khz;
3272 case KVM_KVMCLOCK_CTRL: {
3273 r = kvm_set_guest_paused(vcpu);
3284 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3286 return VM_FAULT_SIGBUS;
3289 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3293 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3295 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3299 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3302 kvm->arch.ept_identity_map_addr = ident_addr;
3306 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3307 u32 kvm_nr_mmu_pages)
3309 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3312 mutex_lock(&kvm->slots_lock);
3314 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3315 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3317 mutex_unlock(&kvm->slots_lock);
3321 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3323 return kvm->arch.n_max_mmu_pages;
3326 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3331 switch (chip->chip_id) {
3332 case KVM_IRQCHIP_PIC_MASTER:
3333 memcpy(&chip->chip.pic,
3334 &pic_irqchip(kvm)->pics[0],
3335 sizeof(struct kvm_pic_state));
3337 case KVM_IRQCHIP_PIC_SLAVE:
3338 memcpy(&chip->chip.pic,
3339 &pic_irqchip(kvm)->pics[1],
3340 sizeof(struct kvm_pic_state));
3342 case KVM_IRQCHIP_IOAPIC:
3343 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3352 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3357 switch (chip->chip_id) {
3358 case KVM_IRQCHIP_PIC_MASTER:
3359 spin_lock(&pic_irqchip(kvm)->lock);
3360 memcpy(&pic_irqchip(kvm)->pics[0],
3362 sizeof(struct kvm_pic_state));
3363 spin_unlock(&pic_irqchip(kvm)->lock);
3365 case KVM_IRQCHIP_PIC_SLAVE:
3366 spin_lock(&pic_irqchip(kvm)->lock);
3367 memcpy(&pic_irqchip(kvm)->pics[1],
3369 sizeof(struct kvm_pic_state));
3370 spin_unlock(&pic_irqchip(kvm)->lock);
3372 case KVM_IRQCHIP_IOAPIC:
3373 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3379 kvm_pic_update_irq(pic_irqchip(kvm));
3383 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3387 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3388 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3389 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3393 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3397 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3398 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3399 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3400 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3404 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3408 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3409 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3410 sizeof(ps->channels));
3411 ps->flags = kvm->arch.vpit->pit_state.flags;
3412 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3413 memset(&ps->reserved, 0, sizeof(ps->reserved));
3417 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3419 int r = 0, start = 0;
3420 u32 prev_legacy, cur_legacy;
3421 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3422 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3423 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3424 if (!prev_legacy && cur_legacy)
3426 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3427 sizeof(kvm->arch.vpit->pit_state.channels));
3428 kvm->arch.vpit->pit_state.flags = ps->flags;
3429 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3430 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3434 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3435 struct kvm_reinject_control *control)
3437 if (!kvm->arch.vpit)
3439 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3440 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3441 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3446 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3447 * @kvm: kvm instance
3448 * @log: slot id and address to which we copy the log
3450 * We need to keep it in mind that VCPU threads can write to the bitmap
3451 * concurrently. So, to avoid losing data, we keep the following order for
3454 * 1. Take a snapshot of the bit and clear it if needed.
3455 * 2. Write protect the corresponding page.
3456 * 3. Flush TLB's if needed.
3457 * 4. Copy the snapshot to the userspace.
3459 * Between 2 and 3, the guest may write to the page using the remaining TLB
3460 * entry. This is not a problem because the page will be reported dirty at
3461 * step 4 using the snapshot taken before and step 3 ensures that successive
3462 * writes will be logged for the next call.
3464 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3467 struct kvm_memory_slot *memslot;
3469 unsigned long *dirty_bitmap;
3470 unsigned long *dirty_bitmap_buffer;
3471 bool is_dirty = false;
3473 mutex_lock(&kvm->slots_lock);
3476 if (log->slot >= KVM_USER_MEM_SLOTS)
3479 memslot = id_to_memslot(kvm->memslots, log->slot);
3481 dirty_bitmap = memslot->dirty_bitmap;
3486 n = kvm_dirty_bitmap_bytes(memslot);
3488 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3489 memset(dirty_bitmap_buffer, 0, n);
3491 spin_lock(&kvm->mmu_lock);
3493 for (i = 0; i < n / sizeof(long); i++) {
3497 if (!dirty_bitmap[i])
3502 mask = xchg(&dirty_bitmap[i], 0);
3503 dirty_bitmap_buffer[i] = mask;
3505 offset = i * BITS_PER_LONG;
3506 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3509 kvm_flush_remote_tlbs(kvm);
3511 spin_unlock(&kvm->mmu_lock);
3514 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3519 mutex_unlock(&kvm->slots_lock);
3523 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3526 if (!irqchip_in_kernel(kvm))
3529 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3530 irq_event->irq, irq_event->level,
3535 long kvm_arch_vm_ioctl(struct file *filp,
3536 unsigned int ioctl, unsigned long arg)
3538 struct kvm *kvm = filp->private_data;
3539 void __user *argp = (void __user *)arg;
3542 * This union makes it completely explicit to gcc-3.x
3543 * that these two variables' stack usage should be
3544 * combined, not added together.
3547 struct kvm_pit_state ps;
3548 struct kvm_pit_state2 ps2;
3549 struct kvm_pit_config pit_config;
3553 case KVM_SET_TSS_ADDR:
3554 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3556 case KVM_SET_IDENTITY_MAP_ADDR: {
3560 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3562 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3565 case KVM_SET_NR_MMU_PAGES:
3566 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3568 case KVM_GET_NR_MMU_PAGES:
3569 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3571 case KVM_CREATE_IRQCHIP: {
3572 struct kvm_pic *vpic;
3574 mutex_lock(&kvm->lock);
3577 goto create_irqchip_unlock;
3579 if (atomic_read(&kvm->online_vcpus))
3580 goto create_irqchip_unlock;
3582 vpic = kvm_create_pic(kvm);
3584 r = kvm_ioapic_init(kvm);
3586 mutex_lock(&kvm->slots_lock);
3587 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3589 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3591 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3593 mutex_unlock(&kvm->slots_lock);
3595 goto create_irqchip_unlock;
3598 goto create_irqchip_unlock;
3600 kvm->arch.vpic = vpic;
3602 r = kvm_setup_default_irq_routing(kvm);
3604 mutex_lock(&kvm->slots_lock);
3605 mutex_lock(&kvm->irq_lock);
3606 kvm_ioapic_destroy(kvm);
3607 kvm_destroy_pic(kvm);
3608 mutex_unlock(&kvm->irq_lock);
3609 mutex_unlock(&kvm->slots_lock);
3611 create_irqchip_unlock:
3612 mutex_unlock(&kvm->lock);
3615 case KVM_CREATE_PIT:
3616 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3618 case KVM_CREATE_PIT2:
3620 if (copy_from_user(&u.pit_config, argp,
3621 sizeof(struct kvm_pit_config)))
3624 mutex_lock(&kvm->slots_lock);
3627 goto create_pit_unlock;
3629 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3633 mutex_unlock(&kvm->slots_lock);
3635 case KVM_GET_IRQCHIP: {
3636 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3637 struct kvm_irqchip *chip;
3639 chip = memdup_user(argp, sizeof(*chip));
3646 if (!irqchip_in_kernel(kvm))
3647 goto get_irqchip_out;
3648 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3650 goto get_irqchip_out;
3652 if (copy_to_user(argp, chip, sizeof *chip))
3653 goto get_irqchip_out;
3659 case KVM_SET_IRQCHIP: {
3660 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3661 struct kvm_irqchip *chip;
3663 chip = memdup_user(argp, sizeof(*chip));
3670 if (!irqchip_in_kernel(kvm))
3671 goto set_irqchip_out;
3672 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3674 goto set_irqchip_out;
3682 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3685 if (!kvm->arch.vpit)
3687 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3691 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3698 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3701 if (!kvm->arch.vpit)
3703 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3706 case KVM_GET_PIT2: {
3708 if (!kvm->arch.vpit)
3710 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3714 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3719 case KVM_SET_PIT2: {
3721 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3724 if (!kvm->arch.vpit)
3726 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3729 case KVM_REINJECT_CONTROL: {
3730 struct kvm_reinject_control control;
3732 if (copy_from_user(&control, argp, sizeof(control)))
3734 r = kvm_vm_ioctl_reinject(kvm, &control);
3737 case KVM_XEN_HVM_CONFIG: {
3739 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3740 sizeof(struct kvm_xen_hvm_config)))
3743 if (kvm->arch.xen_hvm_config.flags)
3748 case KVM_SET_CLOCK: {
3749 struct kvm_clock_data user_ns;
3754 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3762 local_irq_disable();
3763 now_ns = get_kernel_ns();
3764 delta = user_ns.clock - now_ns;
3766 kvm->arch.kvmclock_offset = delta;
3769 case KVM_GET_CLOCK: {
3770 struct kvm_clock_data user_ns;
3773 local_irq_disable();
3774 now_ns = get_kernel_ns();
3775 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3778 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3781 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3794 static void kvm_init_msr_list(void)
3799 /* skip the first msrs in the list. KVM-specific */
3800 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3801 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3804 msrs_to_save[j] = msrs_to_save[i];
3807 num_msrs_to_save = j;
3810 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3818 if (!(vcpu->arch.apic &&
3819 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3820 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3831 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3838 if (!(vcpu->arch.apic &&
3839 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3840 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3842 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3852 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3853 struct kvm_segment *var, int seg)
3855 kvm_x86_ops->set_segment(vcpu, var, seg);
3858 void kvm_get_segment(struct kvm_vcpu *vcpu,
3859 struct kvm_segment *var, int seg)
3861 kvm_x86_ops->get_segment(vcpu, var, seg);
3864 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3867 struct x86_exception exception;
3869 BUG_ON(!mmu_is_nested(vcpu));
3871 /* NPT walks are always user-walks */
3872 access |= PFERR_USER_MASK;
3873 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3878 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3879 struct x86_exception *exception)
3881 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3882 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3885 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3886 struct x86_exception *exception)
3888 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3889 access |= PFERR_FETCH_MASK;
3890 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3893 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3894 struct x86_exception *exception)
3896 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3897 access |= PFERR_WRITE_MASK;
3898 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3901 /* uses this to access any guest's mapped memory without checking CPL */
3902 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3903 struct x86_exception *exception)
3905 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3908 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3909 struct kvm_vcpu *vcpu, u32 access,
3910 struct x86_exception *exception)
3913 int r = X86EMUL_CONTINUE;
3916 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3918 unsigned offset = addr & (PAGE_SIZE-1);
3919 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3922 if (gpa == UNMAPPED_GVA)
3923 return X86EMUL_PROPAGATE_FAULT;
3924 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3926 r = X86EMUL_IO_NEEDED;
3938 /* used for instruction fetching */
3939 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3940 gva_t addr, void *val, unsigned int bytes,
3941 struct x86_exception *exception)
3943 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3944 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3946 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3947 access | PFERR_FETCH_MASK,
3951 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3952 gva_t addr, void *val, unsigned int bytes,
3953 struct x86_exception *exception)
3955 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3956 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3958 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3961 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3963 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3964 gva_t addr, void *val, unsigned int bytes,
3965 struct x86_exception *exception)
3967 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3968 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3971 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3972 gva_t addr, void *val,
3974 struct x86_exception *exception)
3976 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3978 int r = X86EMUL_CONTINUE;
3981 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3984 unsigned offset = addr & (PAGE_SIZE-1);
3985 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3988 if (gpa == UNMAPPED_GVA)
3989 return X86EMUL_PROPAGATE_FAULT;
3990 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3992 r = X86EMUL_IO_NEEDED;
4003 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4005 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4006 gpa_t *gpa, struct x86_exception *exception,
4009 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4010 | (write ? PFERR_WRITE_MASK : 0);
4012 if (vcpu_match_mmio_gva(vcpu, gva)
4013 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4014 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4015 (gva & (PAGE_SIZE - 1));
4016 trace_vcpu_match_mmio(gva, *gpa, write, false);
4020 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4022 if (*gpa == UNMAPPED_GVA)
4025 /* For APIC access vmexit */
4026 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4029 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4030 trace_vcpu_match_mmio(gva, *gpa, write, true);
4037 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4038 const void *val, int bytes)
4042 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4045 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4049 struct read_write_emulator_ops {
4050 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4052 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4053 void *val, int bytes);
4054 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4055 int bytes, void *val);
4056 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4057 void *val, int bytes);
4061 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4063 if (vcpu->mmio_read_completed) {
4064 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4065 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4066 vcpu->mmio_read_completed = 0;
4073 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4074 void *val, int bytes)
4076 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4079 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4080 void *val, int bytes)
4082 return emulator_write_phys(vcpu, gpa, val, bytes);
4085 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4087 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4088 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4091 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4092 void *val, int bytes)
4094 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4095 return X86EMUL_IO_NEEDED;
4098 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4099 void *val, int bytes)
4101 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4103 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4104 return X86EMUL_CONTINUE;
4107 static const struct read_write_emulator_ops read_emultor = {
4108 .read_write_prepare = read_prepare,
4109 .read_write_emulate = read_emulate,
4110 .read_write_mmio = vcpu_mmio_read,
4111 .read_write_exit_mmio = read_exit_mmio,
4114 static const struct read_write_emulator_ops write_emultor = {
4115 .read_write_emulate = write_emulate,
4116 .read_write_mmio = write_mmio,
4117 .read_write_exit_mmio = write_exit_mmio,
4121 static int emulator_read_write_onepage(unsigned long addr, void *val,
4123 struct x86_exception *exception,
4124 struct kvm_vcpu *vcpu,
4125 const struct read_write_emulator_ops *ops)
4129 bool write = ops->write;
4130 struct kvm_mmio_fragment *frag;
4132 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4135 return X86EMUL_PROPAGATE_FAULT;
4137 /* For APIC access vmexit */
4141 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4142 return X86EMUL_CONTINUE;
4146 * Is this MMIO handled locally?
4148 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4149 if (handled == bytes)
4150 return X86EMUL_CONTINUE;
4156 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4157 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4161 return X86EMUL_CONTINUE;
4164 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4165 void *val, unsigned int bytes,
4166 struct x86_exception *exception,
4167 const struct read_write_emulator_ops *ops)
4169 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4173 if (ops->read_write_prepare &&
4174 ops->read_write_prepare(vcpu, val, bytes))
4175 return X86EMUL_CONTINUE;
4177 vcpu->mmio_nr_fragments = 0;
4179 /* Crossing a page boundary? */
4180 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4183 now = -addr & ~PAGE_MASK;
4184 rc = emulator_read_write_onepage(addr, val, now, exception,
4187 if (rc != X86EMUL_CONTINUE)
4194 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4196 if (rc != X86EMUL_CONTINUE)
4199 if (!vcpu->mmio_nr_fragments)
4202 gpa = vcpu->mmio_fragments[0].gpa;
4204 vcpu->mmio_needed = 1;
4205 vcpu->mmio_cur_fragment = 0;
4207 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4208 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4209 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4210 vcpu->run->mmio.phys_addr = gpa;
4212 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4215 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4219 struct x86_exception *exception)
4221 return emulator_read_write(ctxt, addr, val, bytes,
4222 exception, &read_emultor);
4225 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4229 struct x86_exception *exception)
4231 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4232 exception, &write_emultor);
4235 #define CMPXCHG_TYPE(t, ptr, old, new) \
4236 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4238 #ifdef CONFIG_X86_64
4239 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4241 # define CMPXCHG64(ptr, old, new) \
4242 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4245 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4250 struct x86_exception *exception)
4252 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4258 /* guests cmpxchg8b have to be emulated atomically */
4259 if (bytes > 8 || (bytes & (bytes - 1)))
4262 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4264 if (gpa == UNMAPPED_GVA ||
4265 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4268 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4271 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4272 if (is_error_page(page))
4275 kaddr = kmap_atomic(page);
4276 kaddr += offset_in_page(gpa);
4279 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4282 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4285 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4288 exchanged = CMPXCHG64(kaddr, old, new);
4293 kunmap_atomic(kaddr);
4294 kvm_release_page_dirty(page);
4297 return X86EMUL_CMPXCHG_FAILED;
4299 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4301 return X86EMUL_CONTINUE;
4304 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4306 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4309 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4311 /* TODO: String I/O for in kernel device */
4314 if (vcpu->arch.pio.in)
4315 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4316 vcpu->arch.pio.size, pd);
4318 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4319 vcpu->arch.pio.port, vcpu->arch.pio.size,
4324 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4325 unsigned short port, void *val,
4326 unsigned int count, bool in)
4328 trace_kvm_pio(!in, port, size, count);
4330 vcpu->arch.pio.port = port;
4331 vcpu->arch.pio.in = in;
4332 vcpu->arch.pio.count = count;
4333 vcpu->arch.pio.size = size;
4335 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4336 vcpu->arch.pio.count = 0;
4340 vcpu->run->exit_reason = KVM_EXIT_IO;
4341 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4342 vcpu->run->io.size = size;
4343 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4344 vcpu->run->io.count = count;
4345 vcpu->run->io.port = port;
4350 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4351 int size, unsigned short port, void *val,
4354 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4357 if (vcpu->arch.pio.count)
4360 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4363 memcpy(val, vcpu->arch.pio_data, size * count);
4364 vcpu->arch.pio.count = 0;
4371 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4372 int size, unsigned short port,
4373 const void *val, unsigned int count)
4375 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4377 memcpy(vcpu->arch.pio_data, val, size * count);
4378 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4381 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4383 return kvm_x86_ops->get_segment_base(vcpu, seg);
4386 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4388 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4391 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4393 if (!need_emulate_wbinvd(vcpu))
4394 return X86EMUL_CONTINUE;
4396 if (kvm_x86_ops->has_wbinvd_exit()) {
4397 int cpu = get_cpu();
4399 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4400 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4401 wbinvd_ipi, NULL, 1);
4403 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4406 return X86EMUL_CONTINUE;
4408 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4410 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4412 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4415 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4417 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4420 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4423 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4426 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4428 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4431 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4433 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4434 unsigned long value;
4438 value = kvm_read_cr0(vcpu);
4441 value = vcpu->arch.cr2;
4444 value = kvm_read_cr3(vcpu);
4447 value = kvm_read_cr4(vcpu);
4450 value = kvm_get_cr8(vcpu);
4453 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4460 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4462 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4467 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4470 vcpu->arch.cr2 = val;
4473 res = kvm_set_cr3(vcpu, val);
4476 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4479 res = kvm_set_cr8(vcpu, val);
4482 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4489 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4491 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4494 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4496 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4499 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4501 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4504 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4506 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4509 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4511 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4514 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4516 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4519 static unsigned long emulator_get_cached_segment_base(
4520 struct x86_emulate_ctxt *ctxt, int seg)
4522 return get_segment_base(emul_to_vcpu(ctxt), seg);
4525 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4526 struct desc_struct *desc, u32 *base3,
4529 struct kvm_segment var;
4531 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4532 *selector = var.selector;
4535 memset(desc, 0, sizeof(*desc));
4541 set_desc_limit(desc, var.limit);
4542 set_desc_base(desc, (unsigned long)var.base);
4543 #ifdef CONFIG_X86_64
4545 *base3 = var.base >> 32;
4547 desc->type = var.type;
4549 desc->dpl = var.dpl;
4550 desc->p = var.present;
4551 desc->avl = var.avl;
4559 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4560 struct desc_struct *desc, u32 base3,
4563 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4564 struct kvm_segment var;
4566 var.selector = selector;
4567 var.base = get_desc_base(desc);
4568 #ifdef CONFIG_X86_64
4569 var.base |= ((u64)base3) << 32;
4571 var.limit = get_desc_limit(desc);
4573 var.limit = (var.limit << 12) | 0xfff;
4574 var.type = desc->type;
4575 var.present = desc->p;
4576 var.dpl = desc->dpl;
4581 var.avl = desc->avl;
4582 var.present = desc->p;
4583 var.unusable = !var.present;
4586 kvm_set_segment(vcpu, &var, seg);
4590 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4591 u32 msr_index, u64 *pdata)
4593 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4596 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4597 u32 msr_index, u64 data)
4599 struct msr_data msr;
4602 msr.index = msr_index;
4603 msr.host_initiated = false;
4604 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4607 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4608 u32 pmc, u64 *pdata)
4610 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4613 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4615 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4618 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4621 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4623 * CR0.TS may reference the host fpu state, not the guest fpu state,
4624 * so it may be clear at this point.
4629 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4634 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4635 struct x86_instruction_info *info,
4636 enum x86_intercept_stage stage)
4638 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4641 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4642 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4644 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4647 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4649 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4652 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4654 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4657 static const struct x86_emulate_ops emulate_ops = {
4658 .read_gpr = emulator_read_gpr,
4659 .write_gpr = emulator_write_gpr,
4660 .read_std = kvm_read_guest_virt_system,
4661 .write_std = kvm_write_guest_virt_system,
4662 .fetch = kvm_fetch_guest_virt,
4663 .read_emulated = emulator_read_emulated,
4664 .write_emulated = emulator_write_emulated,
4665 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4666 .invlpg = emulator_invlpg,
4667 .pio_in_emulated = emulator_pio_in_emulated,
4668 .pio_out_emulated = emulator_pio_out_emulated,
4669 .get_segment = emulator_get_segment,
4670 .set_segment = emulator_set_segment,
4671 .get_cached_segment_base = emulator_get_cached_segment_base,
4672 .get_gdt = emulator_get_gdt,
4673 .get_idt = emulator_get_idt,
4674 .set_gdt = emulator_set_gdt,
4675 .set_idt = emulator_set_idt,
4676 .get_cr = emulator_get_cr,
4677 .set_cr = emulator_set_cr,
4678 .set_rflags = emulator_set_rflags,
4679 .cpl = emulator_get_cpl,
4680 .get_dr = emulator_get_dr,
4681 .set_dr = emulator_set_dr,
4682 .set_msr = emulator_set_msr,
4683 .get_msr = emulator_get_msr,
4684 .read_pmc = emulator_read_pmc,
4685 .halt = emulator_halt,
4686 .wbinvd = emulator_wbinvd,
4687 .fix_hypercall = emulator_fix_hypercall,
4688 .get_fpu = emulator_get_fpu,
4689 .put_fpu = emulator_put_fpu,
4690 .intercept = emulator_intercept,
4691 .get_cpuid = emulator_get_cpuid,
4694 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4696 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4698 * an sti; sti; sequence only disable interrupts for the first
4699 * instruction. So, if the last instruction, be it emulated or
4700 * not, left the system with the INT_STI flag enabled, it
4701 * means that the last instruction is an sti. We should not
4702 * leave the flag on in this case. The same goes for mov ss
4704 if (!(int_shadow & mask))
4705 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4708 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4710 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4711 if (ctxt->exception.vector == PF_VECTOR)
4712 kvm_propagate_fault(vcpu, &ctxt->exception);
4713 else if (ctxt->exception.error_code_valid)
4714 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4715 ctxt->exception.error_code);
4717 kvm_queue_exception(vcpu, ctxt->exception.vector);
4720 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4722 memset(&ctxt->twobyte, 0,
4723 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4725 ctxt->fetch.start = 0;
4726 ctxt->fetch.end = 0;
4727 ctxt->io_read.pos = 0;
4728 ctxt->io_read.end = 0;
4729 ctxt->mem_read.pos = 0;
4730 ctxt->mem_read.end = 0;
4733 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4735 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4738 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4740 ctxt->eflags = kvm_get_rflags(vcpu);
4741 ctxt->eip = kvm_rip_read(vcpu);
4742 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4743 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4744 cs_l ? X86EMUL_MODE_PROT64 :
4745 cs_db ? X86EMUL_MODE_PROT32 :
4746 X86EMUL_MODE_PROT16;
4747 ctxt->guest_mode = is_guest_mode(vcpu);
4749 init_decode_cache(ctxt);
4750 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4753 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4755 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4758 init_emulate_ctxt(vcpu);
4762 ctxt->_eip = ctxt->eip + inc_eip;
4763 ret = emulate_int_real(ctxt, irq);
4765 if (ret != X86EMUL_CONTINUE)
4766 return EMULATE_FAIL;
4768 ctxt->eip = ctxt->_eip;
4769 kvm_rip_write(vcpu, ctxt->eip);
4770 kvm_set_rflags(vcpu, ctxt->eflags);
4772 if (irq == NMI_VECTOR)
4773 vcpu->arch.nmi_pending = 0;
4775 vcpu->arch.interrupt.pending = false;
4777 return EMULATE_DONE;
4779 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4781 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4783 int r = EMULATE_DONE;
4785 ++vcpu->stat.insn_emulation_fail;
4786 trace_kvm_emulate_insn_failed(vcpu);
4787 if (!is_guest_mode(vcpu)) {
4788 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4789 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4790 vcpu->run->internal.ndata = 0;
4793 kvm_queue_exception(vcpu, UD_VECTOR);
4798 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4799 bool write_fault_to_shadow_pgtable,
4805 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4808 if (!vcpu->arch.mmu.direct_map) {
4810 * Write permission should be allowed since only
4811 * write access need to be emulated.
4813 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4816 * If the mapping is invalid in guest, let cpu retry
4817 * it to generate fault.
4819 if (gpa == UNMAPPED_GVA)
4824 * Do not retry the unhandleable instruction if it faults on the
4825 * readonly host memory, otherwise it will goto a infinite loop:
4826 * retry instruction -> write #PF -> emulation fail -> retry
4827 * instruction -> ...
4829 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4832 * If the instruction failed on the error pfn, it can not be fixed,
4833 * report the error to userspace.
4835 if (is_error_noslot_pfn(pfn))
4838 kvm_release_pfn_clean(pfn);
4840 /* The instructions are well-emulated on direct mmu. */
4841 if (vcpu->arch.mmu.direct_map) {
4842 unsigned int indirect_shadow_pages;
4844 spin_lock(&vcpu->kvm->mmu_lock);
4845 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4846 spin_unlock(&vcpu->kvm->mmu_lock);
4848 if (indirect_shadow_pages)
4849 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4855 * if emulation was due to access to shadowed page table
4856 * and it failed try to unshadow page and re-enter the
4857 * guest to let CPU execute the instruction.
4859 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4862 * If the access faults on its page table, it can not
4863 * be fixed by unprotecting shadow page and it should
4864 * be reported to userspace.
4866 return !write_fault_to_shadow_pgtable;
4869 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4870 unsigned long cr2, int emulation_type)
4872 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4873 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4875 last_retry_eip = vcpu->arch.last_retry_eip;
4876 last_retry_addr = vcpu->arch.last_retry_addr;
4879 * If the emulation is caused by #PF and it is non-page_table
4880 * writing instruction, it means the VM-EXIT is caused by shadow
4881 * page protected, we can zap the shadow page and retry this
4882 * instruction directly.
4884 * Note: if the guest uses a non-page-table modifying instruction
4885 * on the PDE that points to the instruction, then we will unmap
4886 * the instruction and go to an infinite loop. So, we cache the
4887 * last retried eip and the last fault address, if we meet the eip
4888 * and the address again, we can break out of the potential infinite
4891 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4893 if (!(emulation_type & EMULTYPE_RETRY))
4896 if (x86_page_table_writing_insn(ctxt))
4899 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4902 vcpu->arch.last_retry_eip = ctxt->eip;
4903 vcpu->arch.last_retry_addr = cr2;
4905 if (!vcpu->arch.mmu.direct_map)
4906 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4908 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4913 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4914 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4916 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4923 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4924 bool writeback = true;
4925 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
4928 * Clear write_fault_to_shadow_pgtable here to ensure it is
4931 vcpu->arch.write_fault_to_shadow_pgtable = false;
4932 kvm_clear_exception_queue(vcpu);
4934 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4935 init_emulate_ctxt(vcpu);
4936 ctxt->interruptibility = 0;
4937 ctxt->have_exception = false;
4938 ctxt->perm_ok = false;
4940 ctxt->only_vendor_specific_insn
4941 = emulation_type & EMULTYPE_TRAP_UD;
4943 r = x86_decode_insn(ctxt, insn, insn_len);
4945 trace_kvm_emulate_insn_start(vcpu);
4946 ++vcpu->stat.insn_emulation;
4947 if (r != EMULATION_OK) {
4948 if (emulation_type & EMULTYPE_TRAP_UD)
4949 return EMULATE_FAIL;
4950 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4952 return EMULATE_DONE;
4953 if (emulation_type & EMULTYPE_SKIP)
4954 return EMULATE_FAIL;
4955 return handle_emulation_failure(vcpu);
4959 if (emulation_type & EMULTYPE_SKIP) {
4960 kvm_rip_write(vcpu, ctxt->_eip);
4961 return EMULATE_DONE;
4964 if (retry_instruction(ctxt, cr2, emulation_type))
4965 return EMULATE_DONE;
4967 /* this is needed for vmware backdoor interface to work since it
4968 changes registers values during IO operation */
4969 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4970 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4971 emulator_invalidate_register_cache(ctxt);
4975 r = x86_emulate_insn(ctxt);
4977 if (r == EMULATION_INTERCEPTED)
4978 return EMULATE_DONE;
4980 if (r == EMULATION_FAILED) {
4981 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4983 return EMULATE_DONE;
4985 return handle_emulation_failure(vcpu);
4988 if (ctxt->have_exception) {
4989 inject_emulated_exception(vcpu);
4991 } else if (vcpu->arch.pio.count) {
4992 if (!vcpu->arch.pio.in)
4993 vcpu->arch.pio.count = 0;
4996 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4998 r = EMULATE_DO_MMIO;
4999 } else if (vcpu->mmio_needed) {
5000 if (!vcpu->mmio_is_write)
5002 r = EMULATE_DO_MMIO;
5003 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5004 } else if (r == EMULATION_RESTART)
5010 toggle_interruptibility(vcpu, ctxt->interruptibility);
5011 kvm_set_rflags(vcpu, ctxt->eflags);
5012 kvm_make_request(KVM_REQ_EVENT, vcpu);
5013 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5014 kvm_rip_write(vcpu, ctxt->eip);
5016 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5020 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5022 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5024 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5025 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5026 size, port, &val, 1);
5027 /* do not return to emulator after return from userspace */
5028 vcpu->arch.pio.count = 0;
5031 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5033 static void tsc_bad(void *info)
5035 __this_cpu_write(cpu_tsc_khz, 0);
5038 static void tsc_khz_changed(void *data)
5040 struct cpufreq_freqs *freq = data;
5041 unsigned long khz = 0;
5045 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5046 khz = cpufreq_quick_get(raw_smp_processor_id());
5049 __this_cpu_write(cpu_tsc_khz, khz);
5052 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5055 struct cpufreq_freqs *freq = data;
5057 struct kvm_vcpu *vcpu;
5058 int i, send_ipi = 0;
5061 * We allow guests to temporarily run on slowing clocks,
5062 * provided we notify them after, or to run on accelerating
5063 * clocks, provided we notify them before. Thus time never
5066 * However, we have a problem. We can't atomically update
5067 * the frequency of a given CPU from this function; it is
5068 * merely a notifier, which can be called from any CPU.
5069 * Changing the TSC frequency at arbitrary points in time
5070 * requires a recomputation of local variables related to
5071 * the TSC for each VCPU. We must flag these local variables
5072 * to be updated and be sure the update takes place with the
5073 * new frequency before any guests proceed.
5075 * Unfortunately, the combination of hotplug CPU and frequency
5076 * change creates an intractable locking scenario; the order
5077 * of when these callouts happen is undefined with respect to
5078 * CPU hotplug, and they can race with each other. As such,
5079 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5080 * undefined; you can actually have a CPU frequency change take
5081 * place in between the computation of X and the setting of the
5082 * variable. To protect against this problem, all updates of
5083 * the per_cpu tsc_khz variable are done in an interrupt
5084 * protected IPI, and all callers wishing to update the value
5085 * must wait for a synchronous IPI to complete (which is trivial
5086 * if the caller is on the CPU already). This establishes the
5087 * necessary total order on variable updates.
5089 * Note that because a guest time update may take place
5090 * anytime after the setting of the VCPU's request bit, the
5091 * correct TSC value must be set before the request. However,
5092 * to ensure the update actually makes it to any guest which
5093 * starts running in hardware virtualization between the set
5094 * and the acquisition of the spinlock, we must also ping the
5095 * CPU after setting the request bit.
5099 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5101 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5104 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5106 raw_spin_lock(&kvm_lock);
5107 list_for_each_entry(kvm, &vm_list, vm_list) {
5108 kvm_for_each_vcpu(i, vcpu, kvm) {
5109 if (vcpu->cpu != freq->cpu)
5111 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5112 if (vcpu->cpu != smp_processor_id())
5116 raw_spin_unlock(&kvm_lock);
5118 if (freq->old < freq->new && send_ipi) {
5120 * We upscale the frequency. Must make the guest
5121 * doesn't see old kvmclock values while running with
5122 * the new frequency, otherwise we risk the guest sees
5123 * time go backwards.
5125 * In case we update the frequency for another cpu
5126 * (which might be in guest context) send an interrupt
5127 * to kick the cpu out of guest context. Next time
5128 * guest context is entered kvmclock will be updated,
5129 * so the guest will not see stale values.
5131 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5136 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5137 .notifier_call = kvmclock_cpufreq_notifier
5140 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5141 unsigned long action, void *hcpu)
5143 unsigned int cpu = (unsigned long)hcpu;
5147 case CPU_DOWN_FAILED:
5148 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5150 case CPU_DOWN_PREPARE:
5151 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5157 static struct notifier_block kvmclock_cpu_notifier_block = {
5158 .notifier_call = kvmclock_cpu_notifier,
5159 .priority = -INT_MAX
5162 static void kvm_timer_init(void)
5166 max_tsc_khz = tsc_khz;
5167 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5168 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5169 #ifdef CONFIG_CPU_FREQ
5170 struct cpufreq_policy policy;
5171 memset(&policy, 0, sizeof(policy));
5173 cpufreq_get_policy(&policy, cpu);
5174 if (policy.cpuinfo.max_freq)
5175 max_tsc_khz = policy.cpuinfo.max_freq;
5178 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5179 CPUFREQ_TRANSITION_NOTIFIER);
5181 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5182 for_each_online_cpu(cpu)
5183 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5186 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5188 int kvm_is_in_guest(void)
5190 return __this_cpu_read(current_vcpu) != NULL;
5193 static int kvm_is_user_mode(void)
5197 if (__this_cpu_read(current_vcpu))
5198 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5200 return user_mode != 0;
5203 static unsigned long kvm_get_guest_ip(void)
5205 unsigned long ip = 0;
5207 if (__this_cpu_read(current_vcpu))
5208 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5213 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5214 .is_in_guest = kvm_is_in_guest,
5215 .is_user_mode = kvm_is_user_mode,
5216 .get_guest_ip = kvm_get_guest_ip,
5219 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5221 __this_cpu_write(current_vcpu, vcpu);
5223 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5225 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5227 __this_cpu_write(current_vcpu, NULL);
5229 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5231 static void kvm_set_mmio_spte_mask(void)
5234 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5237 * Set the reserved bits and the present bit of an paging-structure
5238 * entry to generate page fault with PFER.RSV = 1.
5240 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5243 #ifdef CONFIG_X86_64
5245 * If reserved bit is not supported, clear the present bit to disable
5248 if (maxphyaddr == 52)
5252 kvm_mmu_set_mmio_spte_mask(mask);
5255 #ifdef CONFIG_X86_64
5256 static void pvclock_gtod_update_fn(struct work_struct *work)
5260 struct kvm_vcpu *vcpu;
5263 raw_spin_lock(&kvm_lock);
5264 list_for_each_entry(kvm, &vm_list, vm_list)
5265 kvm_for_each_vcpu(i, vcpu, kvm)
5266 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5267 atomic_set(&kvm_guest_has_master_clock, 0);
5268 raw_spin_unlock(&kvm_lock);
5271 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5274 * Notification about pvclock gtod data update.
5276 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5279 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5280 struct timekeeper *tk = priv;
5282 update_pvclock_gtod(tk);
5284 /* disable master clock if host does not trust, or does not
5285 * use, TSC clocksource
5287 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5288 atomic_read(&kvm_guest_has_master_clock) != 0)
5289 queue_work(system_long_wq, &pvclock_gtod_work);
5294 static struct notifier_block pvclock_gtod_notifier = {
5295 .notifier_call = pvclock_gtod_notify,
5299 int kvm_arch_init(void *opaque)
5302 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5305 printk(KERN_ERR "kvm: already loaded the other module\n");
5310 if (!ops->cpu_has_kvm_support()) {
5311 printk(KERN_ERR "kvm: no hardware support\n");
5315 if (ops->disabled_by_bios()) {
5316 printk(KERN_ERR "kvm: disabled by bios\n");
5322 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5324 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5328 r = kvm_mmu_module_init();
5330 goto out_free_percpu;
5332 kvm_set_mmio_spte_mask();
5333 kvm_init_msr_list();
5336 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5337 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5341 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5344 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5347 #ifdef CONFIG_X86_64
5348 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5354 free_percpu(shared_msrs);
5359 void kvm_arch_exit(void)
5361 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5363 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5364 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5365 CPUFREQ_TRANSITION_NOTIFIER);
5366 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5367 #ifdef CONFIG_X86_64
5368 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5371 kvm_mmu_module_exit();
5372 free_percpu(shared_msrs);
5375 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5377 ++vcpu->stat.halt_exits;
5378 if (irqchip_in_kernel(vcpu->kvm)) {
5379 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5382 vcpu->run->exit_reason = KVM_EXIT_HLT;
5386 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5388 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5390 u64 param, ingpa, outgpa, ret;
5391 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5392 bool fast, longmode;
5396 * hypercall generates UD from non zero cpl and real mode
5399 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5400 kvm_queue_exception(vcpu, UD_VECTOR);
5404 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5405 longmode = is_long_mode(vcpu) && cs_l == 1;
5408 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5409 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5410 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5411 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5412 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5413 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5415 #ifdef CONFIG_X86_64
5417 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5418 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5419 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5423 code = param & 0xffff;
5424 fast = (param >> 16) & 0x1;
5425 rep_cnt = (param >> 32) & 0xfff;
5426 rep_idx = (param >> 48) & 0xfff;
5428 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5431 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5432 kvm_vcpu_on_spin(vcpu);
5435 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5439 ret = res | (((u64)rep_done & 0xfff) << 32);
5441 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5443 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5444 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5450 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5452 unsigned long nr, a0, a1, a2, a3, ret;
5455 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5456 return kvm_hv_hypercall(vcpu);
5458 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5459 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5460 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5461 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5462 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5464 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5466 if (!is_long_mode(vcpu)) {
5474 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5480 case KVM_HC_VAPIC_POLL_IRQ:
5488 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5489 ++vcpu->stat.hypercalls;
5492 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5494 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5496 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5497 char instruction[3];
5498 unsigned long rip = kvm_rip_read(vcpu);
5501 * Blow out the MMU to ensure that no other VCPU has an active mapping
5502 * to ensure that the updated hypercall appears atomically across all
5505 kvm_mmu_zap_all(vcpu->kvm);
5507 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5509 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5513 * Check if userspace requested an interrupt window, and that the
5514 * interrupt window is open.
5516 * No need to exit to userspace if we already have an interrupt queued.
5518 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5520 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5521 vcpu->run->request_interrupt_window &&
5522 kvm_arch_interrupt_allowed(vcpu));
5525 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5527 struct kvm_run *kvm_run = vcpu->run;
5529 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5530 kvm_run->cr8 = kvm_get_cr8(vcpu);
5531 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5532 if (irqchip_in_kernel(vcpu->kvm))
5533 kvm_run->ready_for_interrupt_injection = 1;
5535 kvm_run->ready_for_interrupt_injection =
5536 kvm_arch_interrupt_allowed(vcpu) &&
5537 !kvm_cpu_has_interrupt(vcpu) &&
5538 !kvm_event_needs_reinjection(vcpu);
5541 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5545 if (!kvm_x86_ops->update_cr8_intercept)
5548 if (!vcpu->arch.apic)
5551 if (!vcpu->arch.apic->vapic_addr)
5552 max_irr = kvm_lapic_find_highest_irr(vcpu);
5559 tpr = kvm_lapic_get_cr8(vcpu);
5561 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5564 static void inject_pending_event(struct kvm_vcpu *vcpu)
5566 /* try to reinject previous events if any */
5567 if (vcpu->arch.exception.pending) {
5568 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5569 vcpu->arch.exception.has_error_code,
5570 vcpu->arch.exception.error_code);
5571 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5572 vcpu->arch.exception.has_error_code,
5573 vcpu->arch.exception.error_code,
5574 vcpu->arch.exception.reinject);
5578 if (vcpu->arch.nmi_injected) {
5579 kvm_x86_ops->set_nmi(vcpu);
5583 if (vcpu->arch.interrupt.pending) {
5584 kvm_x86_ops->set_irq(vcpu);
5588 /* try to inject new event if pending */
5589 if (vcpu->arch.nmi_pending) {
5590 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5591 --vcpu->arch.nmi_pending;
5592 vcpu->arch.nmi_injected = true;
5593 kvm_x86_ops->set_nmi(vcpu);
5595 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5596 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5597 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5599 kvm_x86_ops->set_irq(vcpu);
5604 static void process_nmi(struct kvm_vcpu *vcpu)
5609 * x86 is limited to one NMI running, and one NMI pending after it.
5610 * If an NMI is already in progress, limit further NMIs to just one.
5611 * Otherwise, allow two (and we'll inject the first one immediately).
5613 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5616 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5617 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5618 kvm_make_request(KVM_REQ_EVENT, vcpu);
5621 static void kvm_gen_update_masterclock(struct kvm *kvm)
5623 #ifdef CONFIG_X86_64
5625 struct kvm_vcpu *vcpu;
5626 struct kvm_arch *ka = &kvm->arch;
5628 spin_lock(&ka->pvclock_gtod_sync_lock);
5629 kvm_make_mclock_inprogress_request(kvm);
5630 /* no guest entries from this point */
5631 pvclock_update_vm_gtod_copy(kvm);
5633 kvm_for_each_vcpu(i, vcpu, kvm)
5634 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5636 /* guest entries allowed */
5637 kvm_for_each_vcpu(i, vcpu, kvm)
5638 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5640 spin_unlock(&ka->pvclock_gtod_sync_lock);
5644 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5646 u64 eoi_exit_bitmap[4];
5649 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5652 memset(eoi_exit_bitmap, 0, 32);
5655 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5656 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5657 kvm_apic_update_tmr(vcpu, tmr);
5660 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5663 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5664 vcpu->run->request_interrupt_window;
5665 bool req_immediate_exit = false;
5667 if (vcpu->requests) {
5668 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5669 kvm_mmu_unload(vcpu);
5670 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5671 __kvm_migrate_timers(vcpu);
5672 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5673 kvm_gen_update_masterclock(vcpu->kvm);
5674 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5675 r = kvm_guest_time_update(vcpu);
5679 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5680 kvm_mmu_sync_roots(vcpu);
5681 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5682 kvm_x86_ops->tlb_flush(vcpu);
5683 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5684 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5688 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5689 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5693 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5694 vcpu->fpu_active = 0;
5695 kvm_x86_ops->fpu_deactivate(vcpu);
5697 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5698 /* Page is swapped out. Do synthetic halt */
5699 vcpu->arch.apf.halted = true;
5703 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5704 record_steal_time(vcpu);
5705 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5707 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5708 kvm_handle_pmu_event(vcpu);
5709 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5710 kvm_deliver_pmi(vcpu);
5711 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5712 vcpu_scan_ioapic(vcpu);
5715 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5716 kvm_apic_accept_events(vcpu);
5717 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5722 inject_pending_event(vcpu);
5724 /* enable NMI/IRQ window open exits if needed */
5725 if (vcpu->arch.nmi_pending)
5726 req_immediate_exit =
5727 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5728 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5729 req_immediate_exit =
5730 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5732 if (kvm_lapic_enabled(vcpu)) {
5734 * Update architecture specific hints for APIC
5735 * virtual interrupt delivery.
5737 if (kvm_x86_ops->hwapic_irr_update)
5738 kvm_x86_ops->hwapic_irr_update(vcpu,
5739 kvm_lapic_find_highest_irr(vcpu));
5740 update_cr8_intercept(vcpu);
5741 kvm_lapic_sync_to_vapic(vcpu);
5745 r = kvm_mmu_reload(vcpu);
5747 goto cancel_injection;
5752 kvm_x86_ops->prepare_guest_switch(vcpu);
5753 if (vcpu->fpu_active)
5754 kvm_load_guest_fpu(vcpu);
5755 kvm_load_guest_xcr0(vcpu);
5757 vcpu->mode = IN_GUEST_MODE;
5759 /* We should set ->mode before check ->requests,
5760 * see the comment in make_all_cpus_request.
5764 local_irq_disable();
5766 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5767 || need_resched() || signal_pending(current)) {
5768 vcpu->mode = OUTSIDE_GUEST_MODE;
5773 goto cancel_injection;
5776 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5778 if (req_immediate_exit)
5779 smp_send_reschedule(vcpu->cpu);
5783 if (unlikely(vcpu->arch.switch_db_regs)) {
5785 set_debugreg(vcpu->arch.eff_db[0], 0);
5786 set_debugreg(vcpu->arch.eff_db[1], 1);
5787 set_debugreg(vcpu->arch.eff_db[2], 2);
5788 set_debugreg(vcpu->arch.eff_db[3], 3);
5791 trace_kvm_entry(vcpu->vcpu_id);
5792 kvm_x86_ops->run(vcpu);
5795 * If the guest has used debug registers, at least dr7
5796 * will be disabled while returning to the host.
5797 * If we don't have active breakpoints in the host, we don't
5798 * care about the messed up debug address registers. But if
5799 * we have some of them active, restore the old state.
5801 if (hw_breakpoint_active())
5802 hw_breakpoint_restore();
5804 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5807 vcpu->mode = OUTSIDE_GUEST_MODE;
5810 /* Interrupt is enabled by handle_external_intr() */
5811 kvm_x86_ops->handle_external_intr(vcpu);
5816 * We must have an instruction between local_irq_enable() and
5817 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5818 * the interrupt shadow. The stat.exits increment will do nicely.
5819 * But we need to prevent reordering, hence this barrier():
5827 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5830 * Profile KVM exit RIPs:
5832 if (unlikely(prof_on == KVM_PROFILING)) {
5833 unsigned long rip = kvm_rip_read(vcpu);
5834 profile_hit(KVM_PROFILING, (void *)rip);
5837 if (unlikely(vcpu->arch.tsc_always_catchup))
5838 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5840 if (vcpu->arch.apic_attention)
5841 kvm_lapic_sync_from_vapic(vcpu);
5843 r = kvm_x86_ops->handle_exit(vcpu);
5847 kvm_x86_ops->cancel_injection(vcpu);
5848 if (unlikely(vcpu->arch.apic_attention))
5849 kvm_lapic_sync_from_vapic(vcpu);
5855 static int __vcpu_run(struct kvm_vcpu *vcpu)
5858 struct kvm *kvm = vcpu->kvm;
5860 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5864 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5865 !vcpu->arch.apf.halted)
5866 r = vcpu_enter_guest(vcpu);
5868 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5869 kvm_vcpu_block(vcpu);
5870 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5871 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5872 kvm_apic_accept_events(vcpu);
5873 switch(vcpu->arch.mp_state) {
5874 case KVM_MP_STATE_HALTED:
5875 vcpu->arch.mp_state =
5876 KVM_MP_STATE_RUNNABLE;
5877 case KVM_MP_STATE_RUNNABLE:
5878 vcpu->arch.apf.halted = false;
5880 case KVM_MP_STATE_INIT_RECEIVED:
5892 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5893 if (kvm_cpu_has_pending_timer(vcpu))
5894 kvm_inject_pending_timer_irqs(vcpu);
5896 if (dm_request_for_irq_injection(vcpu)) {
5898 vcpu->run->exit_reason = KVM_EXIT_INTR;
5899 ++vcpu->stat.request_irq_exits;
5902 kvm_check_async_pf_completion(vcpu);
5904 if (signal_pending(current)) {
5906 vcpu->run->exit_reason = KVM_EXIT_INTR;
5907 ++vcpu->stat.signal_exits;
5909 if (need_resched()) {
5910 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5912 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5916 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5921 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5924 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5925 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5926 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5927 if (r != EMULATE_DONE)
5932 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5934 BUG_ON(!vcpu->arch.pio.count);
5936 return complete_emulated_io(vcpu);
5940 * Implements the following, as a state machine:
5944 * for each mmio piece in the fragment
5952 * for each mmio piece in the fragment
5957 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5959 struct kvm_run *run = vcpu->run;
5960 struct kvm_mmio_fragment *frag;
5963 BUG_ON(!vcpu->mmio_needed);
5965 /* Complete previous fragment */
5966 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
5967 len = min(8u, frag->len);
5968 if (!vcpu->mmio_is_write)
5969 memcpy(frag->data, run->mmio.data, len);
5971 if (frag->len <= 8) {
5972 /* Switch to the next fragment. */
5974 vcpu->mmio_cur_fragment++;
5976 /* Go forward to the next mmio piece. */
5982 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5983 vcpu->mmio_needed = 0;
5984 if (vcpu->mmio_is_write)
5986 vcpu->mmio_read_completed = 1;
5987 return complete_emulated_io(vcpu);
5990 run->exit_reason = KVM_EXIT_MMIO;
5991 run->mmio.phys_addr = frag->gpa;
5992 if (vcpu->mmio_is_write)
5993 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
5994 run->mmio.len = min(8u, frag->len);
5995 run->mmio.is_write = vcpu->mmio_is_write;
5996 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6001 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6006 if (!tsk_used_math(current) && init_fpu(current))
6009 if (vcpu->sigset_active)
6010 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6012 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6013 kvm_vcpu_block(vcpu);
6014 kvm_apic_accept_events(vcpu);
6015 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6020 /* re-sync apic's tpr */
6021 if (!irqchip_in_kernel(vcpu->kvm)) {
6022 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6028 if (unlikely(vcpu->arch.complete_userspace_io)) {
6029 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6030 vcpu->arch.complete_userspace_io = NULL;
6035 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6037 r = __vcpu_run(vcpu);
6040 post_kvm_run_save(vcpu);
6041 if (vcpu->sigset_active)
6042 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6047 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6049 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6051 * We are here if userspace calls get_regs() in the middle of
6052 * instruction emulation. Registers state needs to be copied
6053 * back from emulation context to vcpu. Userspace shouldn't do
6054 * that usually, but some bad designed PV devices (vmware
6055 * backdoor interface) need this to work
6057 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6058 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6060 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6061 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6062 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6063 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6064 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6065 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6066 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6067 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6068 #ifdef CONFIG_X86_64
6069 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6070 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6071 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6072 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6073 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6074 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6075 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6076 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6079 regs->rip = kvm_rip_read(vcpu);
6080 regs->rflags = kvm_get_rflags(vcpu);
6085 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6087 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6088 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6090 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6091 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6092 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6093 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6094 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6095 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6096 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6097 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6098 #ifdef CONFIG_X86_64
6099 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6100 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6101 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6102 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6103 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6104 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6105 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6106 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6109 kvm_rip_write(vcpu, regs->rip);
6110 kvm_set_rflags(vcpu, regs->rflags);
6112 vcpu->arch.exception.pending = false;
6114 kvm_make_request(KVM_REQ_EVENT, vcpu);
6119 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6121 struct kvm_segment cs;
6123 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6127 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6129 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6130 struct kvm_sregs *sregs)
6134 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6135 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6136 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6137 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6138 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6139 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6141 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6142 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6144 kvm_x86_ops->get_idt(vcpu, &dt);
6145 sregs->idt.limit = dt.size;
6146 sregs->idt.base = dt.address;
6147 kvm_x86_ops->get_gdt(vcpu, &dt);
6148 sregs->gdt.limit = dt.size;
6149 sregs->gdt.base = dt.address;
6151 sregs->cr0 = kvm_read_cr0(vcpu);
6152 sregs->cr2 = vcpu->arch.cr2;
6153 sregs->cr3 = kvm_read_cr3(vcpu);
6154 sregs->cr4 = kvm_read_cr4(vcpu);
6155 sregs->cr8 = kvm_get_cr8(vcpu);
6156 sregs->efer = vcpu->arch.efer;
6157 sregs->apic_base = kvm_get_apic_base(vcpu);
6159 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6161 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6162 set_bit(vcpu->arch.interrupt.nr,
6163 (unsigned long *)sregs->interrupt_bitmap);
6168 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6169 struct kvm_mp_state *mp_state)
6171 kvm_apic_accept_events(vcpu);
6172 mp_state->mp_state = vcpu->arch.mp_state;
6176 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6177 struct kvm_mp_state *mp_state)
6179 if (!kvm_vcpu_has_lapic(vcpu) &&
6180 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6183 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6184 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6185 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6187 vcpu->arch.mp_state = mp_state->mp_state;
6188 kvm_make_request(KVM_REQ_EVENT, vcpu);
6192 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6193 int reason, bool has_error_code, u32 error_code)
6195 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6198 init_emulate_ctxt(vcpu);
6200 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6201 has_error_code, error_code);
6204 return EMULATE_FAIL;
6206 kvm_rip_write(vcpu, ctxt->eip);
6207 kvm_set_rflags(vcpu, ctxt->eflags);
6208 kvm_make_request(KVM_REQ_EVENT, vcpu);
6209 return EMULATE_DONE;
6211 EXPORT_SYMBOL_GPL(kvm_task_switch);
6213 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6214 struct kvm_sregs *sregs)
6216 int mmu_reset_needed = 0;
6217 int pending_vec, max_bits, idx;
6220 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6223 dt.size = sregs->idt.limit;
6224 dt.address = sregs->idt.base;
6225 kvm_x86_ops->set_idt(vcpu, &dt);
6226 dt.size = sregs->gdt.limit;
6227 dt.address = sregs->gdt.base;
6228 kvm_x86_ops->set_gdt(vcpu, &dt);
6230 vcpu->arch.cr2 = sregs->cr2;
6231 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6232 vcpu->arch.cr3 = sregs->cr3;
6233 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6235 kvm_set_cr8(vcpu, sregs->cr8);
6237 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6238 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6239 kvm_set_apic_base(vcpu, sregs->apic_base);
6241 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6242 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6243 vcpu->arch.cr0 = sregs->cr0;
6245 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6246 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6247 if (sregs->cr4 & X86_CR4_OSXSAVE)
6248 kvm_update_cpuid(vcpu);
6250 idx = srcu_read_lock(&vcpu->kvm->srcu);
6251 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6252 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6253 mmu_reset_needed = 1;
6255 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6257 if (mmu_reset_needed)
6258 kvm_mmu_reset_context(vcpu);
6260 max_bits = KVM_NR_INTERRUPTS;
6261 pending_vec = find_first_bit(
6262 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6263 if (pending_vec < max_bits) {
6264 kvm_queue_interrupt(vcpu, pending_vec, false);
6265 pr_debug("Set back pending irq %d\n", pending_vec);
6268 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6269 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6270 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6271 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6272 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6273 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6275 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6276 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6278 update_cr8_intercept(vcpu);
6280 /* Older userspace won't unhalt the vcpu on reset. */
6281 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6282 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6284 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6286 kvm_make_request(KVM_REQ_EVENT, vcpu);
6291 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6292 struct kvm_guest_debug *dbg)
6294 unsigned long rflags;
6297 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6299 if (vcpu->arch.exception.pending)
6301 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6302 kvm_queue_exception(vcpu, DB_VECTOR);
6304 kvm_queue_exception(vcpu, BP_VECTOR);
6308 * Read rflags as long as potentially injected trace flags are still
6311 rflags = kvm_get_rflags(vcpu);
6313 vcpu->guest_debug = dbg->control;
6314 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6315 vcpu->guest_debug = 0;
6317 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6318 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6319 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6320 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6322 for (i = 0; i < KVM_NR_DB_REGS; i++)
6323 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6325 kvm_update_dr7(vcpu);
6327 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6328 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6329 get_segment_base(vcpu, VCPU_SREG_CS);
6332 * Trigger an rflags update that will inject or remove the trace
6335 kvm_set_rflags(vcpu, rflags);
6337 kvm_x86_ops->update_db_bp_intercept(vcpu);
6347 * Translate a guest virtual address to a guest physical address.
6349 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6350 struct kvm_translation *tr)
6352 unsigned long vaddr = tr->linear_address;
6356 idx = srcu_read_lock(&vcpu->kvm->srcu);
6357 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6358 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6359 tr->physical_address = gpa;
6360 tr->valid = gpa != UNMAPPED_GVA;
6367 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6369 struct i387_fxsave_struct *fxsave =
6370 &vcpu->arch.guest_fpu.state->fxsave;
6372 memcpy(fpu->fpr, fxsave->st_space, 128);
6373 fpu->fcw = fxsave->cwd;
6374 fpu->fsw = fxsave->swd;
6375 fpu->ftwx = fxsave->twd;
6376 fpu->last_opcode = fxsave->fop;
6377 fpu->last_ip = fxsave->rip;
6378 fpu->last_dp = fxsave->rdp;
6379 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6384 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6386 struct i387_fxsave_struct *fxsave =
6387 &vcpu->arch.guest_fpu.state->fxsave;
6389 memcpy(fxsave->st_space, fpu->fpr, 128);
6390 fxsave->cwd = fpu->fcw;
6391 fxsave->swd = fpu->fsw;
6392 fxsave->twd = fpu->ftwx;
6393 fxsave->fop = fpu->last_opcode;
6394 fxsave->rip = fpu->last_ip;
6395 fxsave->rdp = fpu->last_dp;
6396 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6401 int fx_init(struct kvm_vcpu *vcpu)
6405 err = fpu_alloc(&vcpu->arch.guest_fpu);
6409 fpu_finit(&vcpu->arch.guest_fpu);
6412 * Ensure guest xcr0 is valid for loading
6414 vcpu->arch.xcr0 = XSTATE_FP;
6416 vcpu->arch.cr0 |= X86_CR0_ET;
6420 EXPORT_SYMBOL_GPL(fx_init);
6422 static void fx_free(struct kvm_vcpu *vcpu)
6424 fpu_free(&vcpu->arch.guest_fpu);
6427 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6429 if (vcpu->guest_fpu_loaded)
6433 * Restore all possible states in the guest,
6434 * and assume host would use all available bits.
6435 * Guest xcr0 would be loaded later.
6437 kvm_put_guest_xcr0(vcpu);
6438 vcpu->guest_fpu_loaded = 1;
6439 __kernel_fpu_begin();
6440 fpu_restore_checking(&vcpu->arch.guest_fpu);
6444 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6446 kvm_put_guest_xcr0(vcpu);
6448 if (!vcpu->guest_fpu_loaded)
6451 vcpu->guest_fpu_loaded = 0;
6452 fpu_save_init(&vcpu->arch.guest_fpu);
6454 ++vcpu->stat.fpu_reload;
6455 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6459 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6461 kvmclock_reset(vcpu);
6463 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6465 kvm_x86_ops->vcpu_free(vcpu);
6468 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6471 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6472 printk_once(KERN_WARNING
6473 "kvm: SMP vm created on host with unstable TSC; "
6474 "guest TSC will not be reliable\n");
6475 return kvm_x86_ops->vcpu_create(kvm, id);
6478 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6482 vcpu->arch.mtrr_state.have_fixed = 1;
6483 r = vcpu_load(vcpu);
6486 kvm_vcpu_reset(vcpu);
6487 r = kvm_mmu_setup(vcpu);
6493 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6496 struct msr_data msr;
6498 r = vcpu_load(vcpu);
6502 msr.index = MSR_IA32_TSC;
6503 msr.host_initiated = true;
6504 kvm_write_tsc(vcpu, &msr);
6510 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6513 vcpu->arch.apf.msr_val = 0;
6515 r = vcpu_load(vcpu);
6517 kvm_mmu_unload(vcpu);
6521 kvm_x86_ops->vcpu_free(vcpu);
6524 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6526 atomic_set(&vcpu->arch.nmi_queued, 0);
6527 vcpu->arch.nmi_pending = 0;
6528 vcpu->arch.nmi_injected = false;
6530 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6531 vcpu->arch.dr6 = DR6_FIXED_1;
6532 vcpu->arch.dr7 = DR7_FIXED_1;
6533 kvm_update_dr7(vcpu);
6535 kvm_make_request(KVM_REQ_EVENT, vcpu);
6536 vcpu->arch.apf.msr_val = 0;
6537 vcpu->arch.st.msr_val = 0;
6539 kvmclock_reset(vcpu);
6541 kvm_clear_async_pf_completion_queue(vcpu);
6542 kvm_async_pf_hash_reset(vcpu);
6543 vcpu->arch.apf.halted = false;
6545 kvm_pmu_reset(vcpu);
6547 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6548 vcpu->arch.regs_avail = ~0;
6549 vcpu->arch.regs_dirty = ~0;
6551 kvm_x86_ops->vcpu_reset(vcpu);
6554 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6556 struct kvm_segment cs;
6558 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6559 cs.selector = vector << 8;
6560 cs.base = vector << 12;
6561 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6562 kvm_rip_write(vcpu, 0);
6565 int kvm_arch_hardware_enable(void *garbage)
6568 struct kvm_vcpu *vcpu;
6573 bool stable, backwards_tsc = false;
6575 kvm_shared_msr_cpu_online();
6576 ret = kvm_x86_ops->hardware_enable(garbage);
6580 local_tsc = native_read_tsc();
6581 stable = !check_tsc_unstable();
6582 list_for_each_entry(kvm, &vm_list, vm_list) {
6583 kvm_for_each_vcpu(i, vcpu, kvm) {
6584 if (!stable && vcpu->cpu == smp_processor_id())
6585 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6586 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6587 backwards_tsc = true;
6588 if (vcpu->arch.last_host_tsc > max_tsc)
6589 max_tsc = vcpu->arch.last_host_tsc;
6595 * Sometimes, even reliable TSCs go backwards. This happens on
6596 * platforms that reset TSC during suspend or hibernate actions, but
6597 * maintain synchronization. We must compensate. Fortunately, we can
6598 * detect that condition here, which happens early in CPU bringup,
6599 * before any KVM threads can be running. Unfortunately, we can't
6600 * bring the TSCs fully up to date with real time, as we aren't yet far
6601 * enough into CPU bringup that we know how much real time has actually
6602 * elapsed; our helper function, get_kernel_ns() will be using boot
6603 * variables that haven't been updated yet.
6605 * So we simply find the maximum observed TSC above, then record the
6606 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6607 * the adjustment will be applied. Note that we accumulate
6608 * adjustments, in case multiple suspend cycles happen before some VCPU
6609 * gets a chance to run again. In the event that no KVM threads get a
6610 * chance to run, we will miss the entire elapsed period, as we'll have
6611 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6612 * loose cycle time. This isn't too big a deal, since the loss will be
6613 * uniform across all VCPUs (not to mention the scenario is extremely
6614 * unlikely). It is possible that a second hibernate recovery happens
6615 * much faster than a first, causing the observed TSC here to be
6616 * smaller; this would require additional padding adjustment, which is
6617 * why we set last_host_tsc to the local tsc observed here.
6619 * N.B. - this code below runs only on platforms with reliable TSC,
6620 * as that is the only way backwards_tsc is set above. Also note
6621 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6622 * have the same delta_cyc adjustment applied if backwards_tsc
6623 * is detected. Note further, this adjustment is only done once,
6624 * as we reset last_host_tsc on all VCPUs to stop this from being
6625 * called multiple times (one for each physical CPU bringup).
6627 * Platforms with unreliable TSCs don't have to deal with this, they
6628 * will be compensated by the logic in vcpu_load, which sets the TSC to
6629 * catchup mode. This will catchup all VCPUs to real time, but cannot
6630 * guarantee that they stay in perfect synchronization.
6632 if (backwards_tsc) {
6633 u64 delta_cyc = max_tsc - local_tsc;
6634 list_for_each_entry(kvm, &vm_list, vm_list) {
6635 kvm_for_each_vcpu(i, vcpu, kvm) {
6636 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6637 vcpu->arch.last_host_tsc = local_tsc;
6638 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6643 * We have to disable TSC offset matching.. if you were
6644 * booting a VM while issuing an S4 host suspend....
6645 * you may have some problem. Solving this issue is
6646 * left as an exercise to the reader.
6648 kvm->arch.last_tsc_nsec = 0;
6649 kvm->arch.last_tsc_write = 0;
6656 void kvm_arch_hardware_disable(void *garbage)
6658 kvm_x86_ops->hardware_disable(garbage);
6659 drop_user_return_notifiers(garbage);
6662 int kvm_arch_hardware_setup(void)
6664 return kvm_x86_ops->hardware_setup();
6667 void kvm_arch_hardware_unsetup(void)
6669 kvm_x86_ops->hardware_unsetup();
6672 void kvm_arch_check_processor_compat(void *rtn)
6674 kvm_x86_ops->check_processor_compatibility(rtn);
6677 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6679 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6682 struct static_key kvm_no_apic_vcpu __read_mostly;
6684 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6690 BUG_ON(vcpu->kvm == NULL);
6693 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6694 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6695 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6697 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6699 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6704 vcpu->arch.pio_data = page_address(page);
6706 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6708 r = kvm_mmu_create(vcpu);
6710 goto fail_free_pio_data;
6712 if (irqchip_in_kernel(kvm)) {
6713 r = kvm_create_lapic(vcpu);
6715 goto fail_mmu_destroy;
6717 static_key_slow_inc(&kvm_no_apic_vcpu);
6719 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6721 if (!vcpu->arch.mce_banks) {
6723 goto fail_free_lapic;
6725 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6727 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6729 goto fail_free_mce_banks;
6734 goto fail_free_wbinvd_dirty_mask;
6736 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6737 vcpu->arch.pv_time_enabled = false;
6738 kvm_async_pf_hash_reset(vcpu);
6742 fail_free_wbinvd_dirty_mask:
6743 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6744 fail_free_mce_banks:
6745 kfree(vcpu->arch.mce_banks);
6747 kvm_free_lapic(vcpu);
6749 kvm_mmu_destroy(vcpu);
6751 free_page((unsigned long)vcpu->arch.pio_data);
6756 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6760 kvm_pmu_destroy(vcpu);
6761 kfree(vcpu->arch.mce_banks);
6762 kvm_free_lapic(vcpu);
6763 idx = srcu_read_lock(&vcpu->kvm->srcu);
6764 kvm_mmu_destroy(vcpu);
6765 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6766 free_page((unsigned long)vcpu->arch.pio_data);
6767 if (!irqchip_in_kernel(vcpu->kvm))
6768 static_key_slow_dec(&kvm_no_apic_vcpu);
6771 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6776 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6777 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6779 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6780 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6781 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6782 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6783 &kvm->arch.irq_sources_bitmap);
6785 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6786 mutex_init(&kvm->arch.apic_map_lock);
6787 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6789 pvclock_update_vm_gtod_copy(kvm);
6794 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6797 r = vcpu_load(vcpu);
6799 kvm_mmu_unload(vcpu);
6803 static void kvm_free_vcpus(struct kvm *kvm)
6806 struct kvm_vcpu *vcpu;
6809 * Unpin any mmu pages first.
6811 kvm_for_each_vcpu(i, vcpu, kvm) {
6812 kvm_clear_async_pf_completion_queue(vcpu);
6813 kvm_unload_vcpu_mmu(vcpu);
6815 kvm_for_each_vcpu(i, vcpu, kvm)
6816 kvm_arch_vcpu_free(vcpu);
6818 mutex_lock(&kvm->lock);
6819 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6820 kvm->vcpus[i] = NULL;
6822 atomic_set(&kvm->online_vcpus, 0);
6823 mutex_unlock(&kvm->lock);
6826 void kvm_arch_sync_events(struct kvm *kvm)
6828 kvm_free_all_assigned_devices(kvm);
6832 void kvm_arch_destroy_vm(struct kvm *kvm)
6834 if (current->mm == kvm->mm) {
6836 * Free memory regions allocated on behalf of userspace,
6837 * unless the the memory map has changed due to process exit
6840 struct kvm_userspace_memory_region mem;
6841 memset(&mem, 0, sizeof(mem));
6842 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
6843 kvm_set_memory_region(kvm, &mem);
6845 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
6846 kvm_set_memory_region(kvm, &mem);
6848 mem.slot = TSS_PRIVATE_MEMSLOT;
6849 kvm_set_memory_region(kvm, &mem);
6851 kvm_iommu_unmap_guest(kvm);
6852 kfree(kvm->arch.vpic);
6853 kfree(kvm->arch.vioapic);
6854 kvm_free_vcpus(kvm);
6855 if (kvm->arch.apic_access_page)
6856 put_page(kvm->arch.apic_access_page);
6857 if (kvm->arch.ept_identity_pagetable)
6858 put_page(kvm->arch.ept_identity_pagetable);
6859 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
6862 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6863 struct kvm_memory_slot *dont)
6867 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6868 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6869 kvm_kvfree(free->arch.rmap[i]);
6870 free->arch.rmap[i] = NULL;
6875 if (!dont || free->arch.lpage_info[i - 1] !=
6876 dont->arch.lpage_info[i - 1]) {
6877 kvm_kvfree(free->arch.lpage_info[i - 1]);
6878 free->arch.lpage_info[i - 1] = NULL;
6883 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6887 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6892 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6893 slot->base_gfn, level) + 1;
6895 slot->arch.rmap[i] =
6896 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6897 if (!slot->arch.rmap[i])
6902 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6903 sizeof(*slot->arch.lpage_info[i - 1]));
6904 if (!slot->arch.lpage_info[i - 1])
6907 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6908 slot->arch.lpage_info[i - 1][0].write_count = 1;
6909 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6910 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
6911 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6913 * If the gfn and userspace address are not aligned wrt each
6914 * other, or if explicitly asked to, disable large page
6915 * support for this slot
6917 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6918 !kvm_largepages_enabled()) {
6921 for (j = 0; j < lpages; ++j)
6922 slot->arch.lpage_info[i - 1][j].write_count = 1;
6929 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6930 kvm_kvfree(slot->arch.rmap[i]);
6931 slot->arch.rmap[i] = NULL;
6935 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6936 slot->arch.lpage_info[i - 1] = NULL;
6941 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6942 struct kvm_memory_slot *memslot,
6943 struct kvm_userspace_memory_region *mem,
6944 enum kvm_mr_change change)
6947 * Only private memory slots need to be mapped here since
6948 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
6950 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
6951 unsigned long userspace_addr;
6954 * MAP_SHARED to prevent internal slot pages from being moved
6957 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
6958 PROT_READ | PROT_WRITE,
6959 MAP_SHARED | MAP_ANONYMOUS, 0);
6961 if (IS_ERR((void *)userspace_addr))
6962 return PTR_ERR((void *)userspace_addr);
6964 memslot->userspace_addr = userspace_addr;
6970 void kvm_arch_commit_memory_region(struct kvm *kvm,
6971 struct kvm_userspace_memory_region *mem,
6972 const struct kvm_memory_slot *old,
6973 enum kvm_mr_change change)
6976 int nr_mmu_pages = 0;
6978 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
6981 ret = vm_munmap(old->userspace_addr,
6982 old->npages * PAGE_SIZE);
6985 "kvm_vm_ioctl_set_memory_region: "
6986 "failed to munmap memory\n");
6989 if (!kvm->arch.n_requested_mmu_pages)
6990 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6993 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6995 * Write protect all pages for dirty logging.
6996 * Existing largepage mappings are destroyed here and new ones will
6997 * not be created until the end of the logging.
6999 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7000 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7002 * If memory slot is created, or moved, we need to clear all
7005 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
7006 kvm_mmu_zap_mmio_sptes(kvm);
7007 kvm_reload_remote_mmus(kvm);
7011 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7013 kvm_mmu_zap_all(kvm);
7014 kvm_reload_remote_mmus(kvm);
7017 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7018 struct kvm_memory_slot *slot)
7020 kvm_arch_flush_shadow_all(kvm);
7023 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7025 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7026 !vcpu->arch.apf.halted)
7027 || !list_empty_careful(&vcpu->async_pf.done)
7028 || kvm_apic_has_events(vcpu)
7029 || atomic_read(&vcpu->arch.nmi_queued) ||
7030 (kvm_arch_interrupt_allowed(vcpu) &&
7031 kvm_cpu_has_interrupt(vcpu));
7034 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7036 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7039 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7041 return kvm_x86_ops->interrupt_allowed(vcpu);
7044 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7046 unsigned long current_rip = kvm_rip_read(vcpu) +
7047 get_segment_base(vcpu, VCPU_SREG_CS);
7049 return current_rip == linear_rip;
7051 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7053 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7055 unsigned long rflags;
7057 rflags = kvm_x86_ops->get_rflags(vcpu);
7058 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7059 rflags &= ~X86_EFLAGS_TF;
7062 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7064 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7066 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7067 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7068 rflags |= X86_EFLAGS_TF;
7069 kvm_x86_ops->set_rflags(vcpu, rflags);
7070 kvm_make_request(KVM_REQ_EVENT, vcpu);
7072 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7074 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7078 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7079 is_error_page(work->page))
7082 r = kvm_mmu_reload(vcpu);
7086 if (!vcpu->arch.mmu.direct_map &&
7087 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7090 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7093 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7095 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7098 static inline u32 kvm_async_pf_next_probe(u32 key)
7100 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7103 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7105 u32 key = kvm_async_pf_hash_fn(gfn);
7107 while (vcpu->arch.apf.gfns[key] != ~0)
7108 key = kvm_async_pf_next_probe(key);
7110 vcpu->arch.apf.gfns[key] = gfn;
7113 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7116 u32 key = kvm_async_pf_hash_fn(gfn);
7118 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7119 (vcpu->arch.apf.gfns[key] != gfn &&
7120 vcpu->arch.apf.gfns[key] != ~0); i++)
7121 key = kvm_async_pf_next_probe(key);
7126 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7128 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7131 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7135 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7137 vcpu->arch.apf.gfns[i] = ~0;
7139 j = kvm_async_pf_next_probe(j);
7140 if (vcpu->arch.apf.gfns[j] == ~0)
7142 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7144 * k lies cyclically in ]i,j]
7146 * |....j i.k.| or |.k..j i...|
7148 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7149 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7154 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7157 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7161 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7162 struct kvm_async_pf *work)
7164 struct x86_exception fault;
7166 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7167 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7169 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7170 (vcpu->arch.apf.send_user_only &&
7171 kvm_x86_ops->get_cpl(vcpu) == 0))
7172 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7173 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7174 fault.vector = PF_VECTOR;
7175 fault.error_code_valid = true;
7176 fault.error_code = 0;
7177 fault.nested_page_fault = false;
7178 fault.address = work->arch.token;
7179 kvm_inject_page_fault(vcpu, &fault);
7183 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7184 struct kvm_async_pf *work)
7186 struct x86_exception fault;
7188 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7189 if (is_error_page(work->page))
7190 work->arch.token = ~0; /* broadcast wakeup */
7192 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7194 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7195 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7196 fault.vector = PF_VECTOR;
7197 fault.error_code_valid = true;
7198 fault.error_code = 0;
7199 fault.nested_page_fault = false;
7200 fault.address = work->arch.token;
7201 kvm_inject_page_fault(vcpu, &fault);
7203 vcpu->arch.apf.halted = false;
7204 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7207 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7209 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7212 return !kvm_event_needs_reinjection(vcpu) &&
7213 kvm_x86_ops->interrupt_allowed(vcpu);
7216 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7217 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7218 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7219 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7220 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7221 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7222 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7223 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7224 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7225 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7226 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7227 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);