2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
53 #define CREATE_TRACE_POINTS
56 #include <asm/debugreg.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109 #define KVM_NR_SHARED_MSRS 16
111 struct kvm_shared_msrs_global {
113 u32 msrs[KVM_NR_SHARED_MSRS];
116 struct kvm_shared_msrs {
117 struct user_return_notifier urn;
119 struct kvm_shared_msr_values {
122 } values[KVM_NR_SHARED_MSRS];
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141 { "hypercalls", VCPU_STAT(hypercalls) },
142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149 { "irq_injections", VCPU_STAT(irq_injections) },
150 { "nmi_injections", VCPU_STAT(nmi_injections) },
151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158 { "mmu_unsync", VM_STAT(mmu_unsync) },
159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160 { "largepages", VM_STAT(lpages) },
164 u64 __read_mostly host_xcr0;
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
175 static void kvm_on_user_return(struct user_return_notifier *urn)
178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
180 struct kvm_shared_msr_values *values;
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
193 static void shared_msr_update(unsigned slot, u32 msr)
196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
220 static void kvm_shared_msr_cpu_online(void)
224 for (i = 0; i < shared_msrs_global.nr; ++i)
225 shared_msr_update(i, shared_msrs_global.msrs[i]);
228 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
234 if (((value ^ smsr->values[slot].curr) & mask) == 0)
236 smsr->values[slot].curr = value;
237 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
248 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
250 static void drop_user_return_notifiers(void)
252 unsigned int cpu = smp_processor_id();
253 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
255 if (smsr->registered)
256 kvm_on_user_return(&smsr->urn);
259 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
261 return vcpu->arch.apic_base;
263 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
265 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
267 /* TODO: reserve bits check */
268 kvm_lapic_set_base(vcpu, data);
270 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
272 asmlinkage void kvm_spurious_fault(void)
274 /* Fault while not rebooting. We want the trace. */
277 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
279 #define EXCPT_BENIGN 0
280 #define EXCPT_CONTRIBUTORY 1
283 static int exception_class(int vector)
293 return EXCPT_CONTRIBUTORY;
300 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
301 unsigned nr, bool has_error, u32 error_code,
307 kvm_make_request(KVM_REQ_EVENT, vcpu);
309 if (!vcpu->arch.exception.pending) {
311 vcpu->arch.exception.pending = true;
312 vcpu->arch.exception.has_error_code = has_error;
313 vcpu->arch.exception.nr = nr;
314 vcpu->arch.exception.error_code = error_code;
315 vcpu->arch.exception.reinject = reinject;
319 /* to check exception */
320 prev_nr = vcpu->arch.exception.nr;
321 if (prev_nr == DF_VECTOR) {
322 /* triple fault -> shutdown */
323 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
326 class1 = exception_class(prev_nr);
327 class2 = exception_class(nr);
328 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
329 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
330 /* generate double fault per SDM Table 5-5 */
331 vcpu->arch.exception.pending = true;
332 vcpu->arch.exception.has_error_code = true;
333 vcpu->arch.exception.nr = DF_VECTOR;
334 vcpu->arch.exception.error_code = 0;
336 /* replace previous exception with a new one in a hope
337 that instruction re-execution will regenerate lost
342 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
344 kvm_multiple_exception(vcpu, nr, false, 0, false);
346 EXPORT_SYMBOL_GPL(kvm_queue_exception);
348 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
350 kvm_multiple_exception(vcpu, nr, false, 0, true);
352 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
354 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
357 kvm_inject_gp(vcpu, 0);
359 kvm_x86_ops->skip_emulated_instruction(vcpu);
361 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
363 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
365 ++vcpu->stat.pf_guest;
366 vcpu->arch.cr2 = fault->address;
367 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
369 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
371 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
373 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
374 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
376 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
379 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
381 atomic_inc(&vcpu->arch.nmi_queued);
382 kvm_make_request(KVM_REQ_NMI, vcpu);
384 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
386 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
388 kvm_multiple_exception(vcpu, nr, true, error_code, false);
390 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
392 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
394 kvm_multiple_exception(vcpu, nr, true, error_code, true);
396 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
399 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
400 * a #GP and return false.
402 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
404 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
406 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
409 EXPORT_SYMBOL_GPL(kvm_require_cpl);
412 * This function will be used to read from the physical memory of the currently
413 * running guest. The difference to kvm_read_guest_page is that this function
414 * can read from guest physical or from the guest's guest physical memory.
416 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
417 gfn_t ngfn, void *data, int offset, int len,
423 ngpa = gfn_to_gpa(ngfn);
424 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
425 if (real_gfn == UNMAPPED_GVA)
428 real_gfn = gpa_to_gfn(real_gfn);
430 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
432 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
434 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
435 void *data, int offset, int len, u32 access)
437 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
438 data, offset, len, access);
442 * Load the pae pdptrs. Return true is they are all valid.
444 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
446 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
447 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
450 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
452 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
453 offset * sizeof(u64), sizeof(pdpte),
454 PFERR_USER_MASK|PFERR_WRITE_MASK);
459 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
460 if (is_present_gpte(pdpte[i]) &&
461 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
468 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
469 __set_bit(VCPU_EXREG_PDPTR,
470 (unsigned long *)&vcpu->arch.regs_avail);
471 __set_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_dirty);
477 EXPORT_SYMBOL_GPL(load_pdptrs);
479 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
481 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
487 if (is_long_mode(vcpu) || !is_pae(vcpu))
490 if (!test_bit(VCPU_EXREG_PDPTR,
491 (unsigned long *)&vcpu->arch.regs_avail))
494 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
495 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
496 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
497 PFERR_USER_MASK | PFERR_WRITE_MASK);
500 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
506 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
508 unsigned long old_cr0 = kvm_read_cr0(vcpu);
509 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
510 X86_CR0_CD | X86_CR0_NW;
515 if (cr0 & 0xffffffff00000000UL)
519 cr0 &= ~CR0_RESERVED_BITS;
521 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
524 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
527 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
529 if ((vcpu->arch.efer & EFER_LME)) {
534 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
539 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
544 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
547 kvm_x86_ops->set_cr0(vcpu, cr0);
549 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
550 kvm_clear_async_pf_completion_queue(vcpu);
551 kvm_async_pf_hash_reset(vcpu);
554 if ((cr0 ^ old_cr0) & update_bits)
555 kvm_mmu_reset_context(vcpu);
558 EXPORT_SYMBOL_GPL(kvm_set_cr0);
560 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
562 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
564 EXPORT_SYMBOL_GPL(kvm_lmsw);
566 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
568 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
569 !vcpu->guest_xcr0_loaded) {
570 /* kvm_set_xcr() also depends on this */
571 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
572 vcpu->guest_xcr0_loaded = 1;
576 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
578 if (vcpu->guest_xcr0_loaded) {
579 if (vcpu->arch.xcr0 != host_xcr0)
580 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
581 vcpu->guest_xcr0_loaded = 0;
585 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
589 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
590 if (index != XCR_XFEATURE_ENABLED_MASK)
593 if (!(xcr0 & XSTATE_FP))
595 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
597 if (xcr0 & ~host_xcr0)
599 kvm_put_guest_xcr0(vcpu);
600 vcpu->arch.xcr0 = xcr0;
604 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
606 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
607 __kvm_set_xcr(vcpu, index, xcr)) {
608 kvm_inject_gp(vcpu, 0);
613 EXPORT_SYMBOL_GPL(kvm_set_xcr);
615 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
617 unsigned long old_cr4 = kvm_read_cr4(vcpu);
618 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
619 X86_CR4_PAE | X86_CR4_SMEP;
620 if (cr4 & CR4_RESERVED_BITS)
623 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
626 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
629 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
632 if (is_long_mode(vcpu)) {
633 if (!(cr4 & X86_CR4_PAE))
635 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
636 && ((cr4 ^ old_cr4) & pdptr_bits)
637 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
641 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
642 if (!guest_cpuid_has_pcid(vcpu))
645 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
646 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
650 if (kvm_x86_ops->set_cr4(vcpu, cr4))
653 if (((cr4 ^ old_cr4) & pdptr_bits) ||
654 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
655 kvm_mmu_reset_context(vcpu);
657 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
658 kvm_update_cpuid(vcpu);
662 EXPORT_SYMBOL_GPL(kvm_set_cr4);
664 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
666 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
667 kvm_mmu_sync_roots(vcpu);
668 kvm_mmu_flush_tlb(vcpu);
672 if (is_long_mode(vcpu)) {
673 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
674 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
677 if (cr3 & CR3_L_MODE_RESERVED_BITS)
681 if (cr3 & CR3_PAE_RESERVED_BITS)
683 if (is_paging(vcpu) &&
684 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
688 * We don't check reserved bits in nonpae mode, because
689 * this isn't enforced, and VMware depends on this.
694 * Does the new cr3 value map to physical memory? (Note, we
695 * catch an invalid cr3 even in real-mode, because it would
696 * cause trouble later on when we turn on paging anyway.)
698 * A real CPU would silently accept an invalid cr3 and would
699 * attempt to use it - with largely undefined (and often hard
700 * to debug) behavior on the guest side.
702 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
704 vcpu->arch.cr3 = cr3;
705 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
706 vcpu->arch.mmu.new_cr3(vcpu);
709 EXPORT_SYMBOL_GPL(kvm_set_cr3);
711 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
713 if (cr8 & CR8_RESERVED_BITS)
715 if (irqchip_in_kernel(vcpu->kvm))
716 kvm_lapic_set_tpr(vcpu, cr8);
718 vcpu->arch.cr8 = cr8;
721 EXPORT_SYMBOL_GPL(kvm_set_cr8);
723 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
725 if (irqchip_in_kernel(vcpu->kvm))
726 return kvm_lapic_get_cr8(vcpu);
728 return vcpu->arch.cr8;
730 EXPORT_SYMBOL_GPL(kvm_get_cr8);
732 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
736 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
737 dr7 = vcpu->arch.guest_debug_dr7;
739 dr7 = vcpu->arch.dr7;
740 kvm_x86_ops->set_dr7(vcpu, dr7);
741 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
744 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
748 vcpu->arch.db[dr] = val;
749 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
750 vcpu->arch.eff_db[dr] = val;
753 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
757 if (val & 0xffffffff00000000ULL)
759 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
762 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
766 if (val & 0xffffffff00000000ULL)
768 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
769 kvm_update_dr7(vcpu);
776 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
780 res = __kvm_set_dr(vcpu, dr, val);
782 kvm_queue_exception(vcpu, UD_VECTOR);
784 kvm_inject_gp(vcpu, 0);
788 EXPORT_SYMBOL_GPL(kvm_set_dr);
790 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
794 *val = vcpu->arch.db[dr];
797 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
801 *val = vcpu->arch.dr6;
804 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
808 *val = vcpu->arch.dr7;
815 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
817 if (_kvm_get_dr(vcpu, dr, val)) {
818 kvm_queue_exception(vcpu, UD_VECTOR);
823 EXPORT_SYMBOL_GPL(kvm_get_dr);
825 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
827 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
831 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
834 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
835 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
838 EXPORT_SYMBOL_GPL(kvm_rdpmc);
841 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
842 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
844 * This list is modified at module load time to reflect the
845 * capabilities of the host cpu. This capabilities test skips MSRs that are
846 * kvm-specific. Those are put in the beginning of the list.
849 #define KVM_SAVE_MSRS_BEGIN 10
850 static u32 msrs_to_save[] = {
851 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
852 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
853 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
854 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
856 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
859 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
861 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
864 static unsigned num_msrs_to_save;
866 static const u32 emulated_msrs[] = {
868 MSR_IA32_TSCDEADLINE,
869 MSR_IA32_MISC_ENABLE,
874 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
876 if (efer & efer_reserved_bits)
879 if (efer & EFER_FFXSR) {
880 struct kvm_cpuid_entry2 *feat;
882 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
883 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
887 if (efer & EFER_SVME) {
888 struct kvm_cpuid_entry2 *feat;
890 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
891 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
897 EXPORT_SYMBOL_GPL(kvm_valid_efer);
899 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
901 u64 old_efer = vcpu->arch.efer;
903 if (!kvm_valid_efer(vcpu, efer))
907 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
911 efer |= vcpu->arch.efer & EFER_LMA;
913 kvm_x86_ops->set_efer(vcpu, efer);
915 /* Update reserved bits */
916 if ((efer ^ old_efer) & EFER_NX)
917 kvm_mmu_reset_context(vcpu);
922 void kvm_enable_efer_bits(u64 mask)
924 efer_reserved_bits &= ~mask;
926 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
929 * Writes msr value into into the appropriate "register".
930 * Returns 0 on success, non-0 otherwise.
931 * Assumes vcpu_load() was already called.
933 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
935 switch (msr->index) {
938 case MSR_KERNEL_GS_BASE:
941 if (is_noncanonical_address(msr->data))
944 case MSR_IA32_SYSENTER_EIP:
945 case MSR_IA32_SYSENTER_ESP:
947 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
948 * non-canonical address is written on Intel but not on
949 * AMD (which ignores the top 32-bits, because it does
950 * not implement 64-bit SYSENTER).
952 * 64-bit code should hence be able to write a non-canonical
953 * value on AMD. Making the address canonical ensures that
954 * vmentry does not fail on Intel after writing a non-canonical
955 * value, and that something deterministic happens if the guest
956 * invokes 64-bit SYSENTER.
958 msr->data = get_canonical(msr->data);
960 return kvm_x86_ops->set_msr(vcpu, msr);
962 EXPORT_SYMBOL_GPL(kvm_set_msr);
965 * Adapt set_msr() to msr_io()'s calling convention
967 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
973 msr.host_initiated = true;
974 return kvm_set_msr(vcpu, &msr);
978 struct pvclock_gtod_data {
981 struct { /* extract of a clocksource struct */
989 /* open coded 'struct timespec' */
990 u64 monotonic_time_snsec;
991 time_t monotonic_time_sec;
994 static struct pvclock_gtod_data pvclock_gtod_data;
996 static void update_pvclock_gtod(struct timekeeper *tk)
998 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1000 write_seqcount_begin(&vdata->seq);
1002 /* copy pvclock gtod data */
1003 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1004 vdata->clock.cycle_last = tk->clock->cycle_last;
1005 vdata->clock.mask = tk->clock->mask;
1006 vdata->clock.mult = tk->mult;
1007 vdata->clock.shift = tk->shift;
1009 vdata->monotonic_time_sec = tk->xtime_sec
1010 + tk->wall_to_monotonic.tv_sec;
1011 vdata->monotonic_time_snsec = tk->xtime_nsec
1012 + (tk->wall_to_monotonic.tv_nsec
1014 while (vdata->monotonic_time_snsec >=
1015 (((u64)NSEC_PER_SEC) << tk->shift)) {
1016 vdata->monotonic_time_snsec -=
1017 ((u64)NSEC_PER_SEC) << tk->shift;
1018 vdata->monotonic_time_sec++;
1021 write_seqcount_end(&vdata->seq);
1026 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1030 struct pvclock_wall_clock wc;
1031 struct timespec boot;
1036 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1041 ++version; /* first time write, random junk */
1045 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1048 * The guest calculates current wall clock time by adding
1049 * system time (updated by kvm_guest_time_update below) to the
1050 * wall clock specified here. guest system time equals host
1051 * system time for us, thus we must fill in host boot time here.
1055 if (kvm->arch.kvmclock_offset) {
1056 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1057 boot = timespec_sub(boot, ts);
1059 wc.sec = boot.tv_sec;
1060 wc.nsec = boot.tv_nsec;
1061 wc.version = version;
1063 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1066 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1069 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1071 uint32_t quotient, remainder;
1073 /* Don't try to replace with do_div(), this one calculates
1074 * "(dividend << 32) / divisor" */
1076 : "=a" (quotient), "=d" (remainder)
1077 : "0" (0), "1" (dividend), "r" (divisor) );
1081 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1082 s8 *pshift, u32 *pmultiplier)
1089 tps64 = base_khz * 1000LL;
1090 scaled64 = scaled_khz * 1000LL;
1091 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1096 tps32 = (uint32_t)tps64;
1097 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1098 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1106 *pmultiplier = div_frac(scaled64, tps32);
1108 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1109 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1112 static inline u64 get_kernel_ns(void)
1116 WARN_ON(preemptible());
1118 monotonic_to_bootbased(&ts);
1119 return timespec_to_ns(&ts);
1122 #ifdef CONFIG_X86_64
1123 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1126 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1127 unsigned long max_tsc_khz;
1129 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1131 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1132 vcpu->arch.virtual_tsc_shift);
1135 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1137 u64 v = (u64)khz * (1000000 + ppm);
1142 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1144 u32 thresh_lo, thresh_hi;
1145 int use_scaling = 0;
1147 /* tsc_khz can be zero if TSC calibration fails */
1148 if (this_tsc_khz == 0)
1151 /* Compute a scale to convert nanoseconds in TSC cycles */
1152 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1153 &vcpu->arch.virtual_tsc_shift,
1154 &vcpu->arch.virtual_tsc_mult);
1155 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1158 * Compute the variation in TSC rate which is acceptable
1159 * within the range of tolerance and decide if the
1160 * rate being applied is within that bounds of the hardware
1161 * rate. If so, no scaling or compensation need be done.
1163 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1164 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1165 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1166 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1169 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1172 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1174 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1175 vcpu->arch.virtual_tsc_mult,
1176 vcpu->arch.virtual_tsc_shift);
1177 tsc += vcpu->arch.this_tsc_write;
1181 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1183 #ifdef CONFIG_X86_64
1185 bool do_request = false;
1186 struct kvm_arch *ka = &vcpu->kvm->arch;
1187 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1189 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1190 atomic_read(&vcpu->kvm->online_vcpus));
1192 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1193 if (!ka->use_master_clock)
1196 if (!vcpus_matched && ka->use_master_clock)
1200 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1202 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1203 atomic_read(&vcpu->kvm->online_vcpus),
1204 ka->use_master_clock, gtod->clock.vclock_mode);
1208 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1210 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1211 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1214 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1216 struct kvm *kvm = vcpu->kvm;
1217 u64 offset, ns, elapsed;
1218 unsigned long flags;
1221 u64 data = msr->data;
1223 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1224 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1225 ns = get_kernel_ns();
1226 elapsed = ns - kvm->arch.last_tsc_nsec;
1228 if (vcpu->arch.virtual_tsc_khz) {
1231 /* n.b - signed multiplication and division required */
1232 usdiff = data - kvm->arch.last_tsc_write;
1233 #ifdef CONFIG_X86_64
1234 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1236 /* do_div() only does unsigned */
1237 asm("1: idivl %[divisor]\n"
1238 "2: xor %%edx, %%edx\n"
1239 " movl $0, %[faulted]\n"
1241 ".section .fixup,\"ax\"\n"
1242 "4: movl $1, %[faulted]\n"
1246 _ASM_EXTABLE(1b, 4b)
1248 : "=A"(usdiff), [faulted] "=r" (faulted)
1249 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1252 do_div(elapsed, 1000);
1257 /* idivl overflow => difference is larger than USEC_PER_SEC */
1259 usdiff = USEC_PER_SEC;
1261 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1264 * Special case: TSC write with a small delta (1 second) of virtual
1265 * cycle time against real time is interpreted as an attempt to
1266 * synchronize the CPU.
1268 * For a reliable TSC, we can match TSC offsets, and for an unstable
1269 * TSC, we add elapsed time in this computation. We could let the
1270 * compensation code attempt to catch up if we fall behind, but
1271 * it's better to try to match offsets from the beginning.
1273 if (usdiff < USEC_PER_SEC &&
1274 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1275 if (!check_tsc_unstable()) {
1276 offset = kvm->arch.cur_tsc_offset;
1277 pr_debug("kvm: matched tsc offset for %llu\n", data);
1279 u64 delta = nsec_to_cycles(vcpu, elapsed);
1281 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1282 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1287 * We split periods of matched TSC writes into generations.
1288 * For each generation, we track the original measured
1289 * nanosecond time, offset, and write, so if TSCs are in
1290 * sync, we can match exact offset, and if not, we can match
1291 * exact software computation in compute_guest_tsc()
1293 * These values are tracked in kvm->arch.cur_xxx variables.
1295 kvm->arch.cur_tsc_generation++;
1296 kvm->arch.cur_tsc_nsec = ns;
1297 kvm->arch.cur_tsc_write = data;
1298 kvm->arch.cur_tsc_offset = offset;
1300 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1301 kvm->arch.cur_tsc_generation, data);
1305 * We also track th most recent recorded KHZ, write and time to
1306 * allow the matching interval to be extended at each write.
1308 kvm->arch.last_tsc_nsec = ns;
1309 kvm->arch.last_tsc_write = data;
1310 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1312 /* Reset of TSC must disable overshoot protection below */
1313 vcpu->arch.hv_clock.tsc_timestamp = 0;
1314 vcpu->arch.last_guest_tsc = data;
1316 /* Keep track of which generation this VCPU has synchronized to */
1317 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1318 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1319 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1321 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1322 update_ia32_tsc_adjust_msr(vcpu, offset);
1323 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1324 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1326 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1328 kvm->arch.nr_vcpus_matched_tsc++;
1330 kvm->arch.nr_vcpus_matched_tsc = 0;
1332 kvm_track_tsc_matching(vcpu);
1333 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1336 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1338 #ifdef CONFIG_X86_64
1340 static cycle_t read_tsc(void)
1346 * Empirically, a fence (of type that depends on the CPU)
1347 * before rdtsc is enough to ensure that rdtsc is ordered
1348 * with respect to loads. The various CPU manuals are unclear
1349 * as to whether rdtsc can be reordered with later loads,
1350 * but no one has ever seen it happen.
1353 ret = (cycle_t)vget_cycles();
1355 last = pvclock_gtod_data.clock.cycle_last;
1357 if (likely(ret >= last))
1361 * GCC likes to generate cmov here, but this branch is extremely
1362 * predictable (it's just a funciton of time and the likely is
1363 * very likely) and there's a data dependence, so force GCC
1364 * to generate a branch instead. I don't barrier() because
1365 * we don't actually need a barrier, and if this function
1366 * ever gets inlined it will generate worse code.
1372 static inline u64 vgettsc(cycle_t *cycle_now)
1375 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1377 *cycle_now = read_tsc();
1379 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1380 return v * gtod->clock.mult;
1383 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1388 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1392 seq = read_seqcount_begin(>od->seq);
1393 mode = gtod->clock.vclock_mode;
1394 ts->tv_sec = gtod->monotonic_time_sec;
1395 ns = gtod->monotonic_time_snsec;
1396 ns += vgettsc(cycle_now);
1397 ns >>= gtod->clock.shift;
1398 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1399 timespec_add_ns(ts, ns);
1404 /* returns true if host is using tsc clocksource */
1405 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1409 /* checked again under seqlock below */
1410 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1413 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1416 monotonic_to_bootbased(&ts);
1417 *kernel_ns = timespec_to_ns(&ts);
1425 * Assuming a stable TSC across physical CPUS, and a stable TSC
1426 * across virtual CPUs, the following condition is possible.
1427 * Each numbered line represents an event visible to both
1428 * CPUs at the next numbered event.
1430 * "timespecX" represents host monotonic time. "tscX" represents
1433 * VCPU0 on CPU0 | VCPU1 on CPU1
1435 * 1. read timespec0,tsc0
1436 * 2. | timespec1 = timespec0 + N
1438 * 3. transition to guest | transition to guest
1439 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1440 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1441 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1443 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1446 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1448 * - 0 < N - M => M < N
1450 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1451 * always the case (the difference between two distinct xtime instances
1452 * might be smaller then the difference between corresponding TSC reads,
1453 * when updating guest vcpus pvclock areas).
1455 * To avoid that problem, do not allow visibility of distinct
1456 * system_timestamp/tsc_timestamp values simultaneously: use a master
1457 * copy of host monotonic time values. Update that master copy
1460 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1464 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1466 #ifdef CONFIG_X86_64
1467 struct kvm_arch *ka = &kvm->arch;
1469 bool host_tsc_clocksource, vcpus_matched;
1471 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1472 atomic_read(&kvm->online_vcpus));
1475 * If the host uses TSC clock, then passthrough TSC as stable
1478 host_tsc_clocksource = kvm_get_time_and_clockread(
1479 &ka->master_kernel_ns,
1480 &ka->master_cycle_now);
1482 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1484 if (ka->use_master_clock)
1485 atomic_set(&kvm_guest_has_master_clock, 1);
1487 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1488 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1493 static int kvm_guest_time_update(struct kvm_vcpu *v)
1495 unsigned long flags, this_tsc_khz;
1496 struct kvm_vcpu_arch *vcpu = &v->arch;
1497 struct kvm_arch *ka = &v->kvm->arch;
1498 s64 kernel_ns, max_kernel_ns;
1499 u64 tsc_timestamp, host_tsc;
1500 struct pvclock_vcpu_time_info guest_hv_clock;
1502 bool use_master_clock;
1508 * If the host uses TSC clock, then passthrough TSC as stable
1511 spin_lock(&ka->pvclock_gtod_sync_lock);
1512 use_master_clock = ka->use_master_clock;
1513 if (use_master_clock) {
1514 host_tsc = ka->master_cycle_now;
1515 kernel_ns = ka->master_kernel_ns;
1517 spin_unlock(&ka->pvclock_gtod_sync_lock);
1519 /* Keep irq disabled to prevent changes to the clock */
1520 local_irq_save(flags);
1521 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1522 if (unlikely(this_tsc_khz == 0)) {
1523 local_irq_restore(flags);
1524 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1527 if (!use_master_clock) {
1528 host_tsc = native_read_tsc();
1529 kernel_ns = get_kernel_ns();
1532 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1535 * We may have to catch up the TSC to match elapsed wall clock
1536 * time for two reasons, even if kvmclock is used.
1537 * 1) CPU could have been running below the maximum TSC rate
1538 * 2) Broken TSC compensation resets the base at each VCPU
1539 * entry to avoid unknown leaps of TSC even when running
1540 * again on the same CPU. This may cause apparent elapsed
1541 * time to disappear, and the guest to stand still or run
1544 if (vcpu->tsc_catchup) {
1545 u64 tsc = compute_guest_tsc(v, kernel_ns);
1546 if (tsc > tsc_timestamp) {
1547 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1548 tsc_timestamp = tsc;
1552 local_irq_restore(flags);
1554 if (!vcpu->pv_time_enabled)
1558 * Time as measured by the TSC may go backwards when resetting the base
1559 * tsc_timestamp. The reason for this is that the TSC resolution is
1560 * higher than the resolution of the other clock scales. Thus, many
1561 * possible measurments of the TSC correspond to one measurement of any
1562 * other clock, and so a spread of values is possible. This is not a
1563 * problem for the computation of the nanosecond clock; with TSC rates
1564 * around 1GHZ, there can only be a few cycles which correspond to one
1565 * nanosecond value, and any path through this code will inevitably
1566 * take longer than that. However, with the kernel_ns value itself,
1567 * the precision may be much lower, down to HZ granularity. If the
1568 * first sampling of TSC against kernel_ns ends in the low part of the
1569 * range, and the second in the high end of the range, we can get:
1571 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1573 * As the sampling errors potentially range in the thousands of cycles,
1574 * it is possible such a time value has already been observed by the
1575 * guest. To protect against this, we must compute the system time as
1576 * observed by the guest and ensure the new system time is greater.
1579 if (vcpu->hv_clock.tsc_timestamp) {
1580 max_kernel_ns = vcpu->last_guest_tsc -
1581 vcpu->hv_clock.tsc_timestamp;
1582 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1583 vcpu->hv_clock.tsc_to_system_mul,
1584 vcpu->hv_clock.tsc_shift);
1585 max_kernel_ns += vcpu->last_kernel_ns;
1588 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1589 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1590 &vcpu->hv_clock.tsc_shift,
1591 &vcpu->hv_clock.tsc_to_system_mul);
1592 vcpu->hw_tsc_khz = this_tsc_khz;
1595 /* with a master <monotonic time, tsc value> tuple,
1596 * pvclock clock reads always increase at the (scaled) rate
1597 * of guest TSC - no need to deal with sampling errors.
1599 if (!use_master_clock) {
1600 if (max_kernel_ns > kernel_ns)
1601 kernel_ns = max_kernel_ns;
1603 /* With all the info we got, fill in the values */
1604 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1605 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1606 vcpu->last_kernel_ns = kernel_ns;
1607 vcpu->last_guest_tsc = tsc_timestamp;
1610 * The interface expects us to write an even number signaling that the
1611 * update is finished. Since the guest won't see the intermediate
1612 * state, we just increase by 2 at the end.
1614 vcpu->hv_clock.version += 2;
1616 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1617 &guest_hv_clock, sizeof(guest_hv_clock))))
1620 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1621 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1623 if (vcpu->pvclock_set_guest_stopped_request) {
1624 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1625 vcpu->pvclock_set_guest_stopped_request = false;
1628 /* If the host uses TSC clocksource, then it is stable */
1629 if (use_master_clock)
1630 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1632 vcpu->hv_clock.flags = pvclock_flags;
1634 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1636 sizeof(vcpu->hv_clock));
1640 static bool msr_mtrr_valid(unsigned msr)
1643 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1644 case MSR_MTRRfix64K_00000:
1645 case MSR_MTRRfix16K_80000:
1646 case MSR_MTRRfix16K_A0000:
1647 case MSR_MTRRfix4K_C0000:
1648 case MSR_MTRRfix4K_C8000:
1649 case MSR_MTRRfix4K_D0000:
1650 case MSR_MTRRfix4K_D8000:
1651 case MSR_MTRRfix4K_E0000:
1652 case MSR_MTRRfix4K_E8000:
1653 case MSR_MTRRfix4K_F0000:
1654 case MSR_MTRRfix4K_F8000:
1655 case MSR_MTRRdefType:
1656 case MSR_IA32_CR_PAT:
1664 static bool valid_pat_type(unsigned t)
1666 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1669 static bool valid_mtrr_type(unsigned t)
1671 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1674 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1678 if (!msr_mtrr_valid(msr))
1681 if (msr == MSR_IA32_CR_PAT) {
1682 for (i = 0; i < 8; i++)
1683 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1686 } else if (msr == MSR_MTRRdefType) {
1689 return valid_mtrr_type(data & 0xff);
1690 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1691 for (i = 0; i < 8 ; i++)
1692 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1697 /* variable MTRRs */
1698 return valid_mtrr_type(data & 0xff);
1701 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1703 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1705 if (!mtrr_valid(vcpu, msr, data))
1708 if (msr == MSR_MTRRdefType) {
1709 vcpu->arch.mtrr_state.def_type = data;
1710 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1711 } else if (msr == MSR_MTRRfix64K_00000)
1713 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1714 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1715 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1716 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1717 else if (msr == MSR_IA32_CR_PAT)
1718 vcpu->arch.pat = data;
1719 else { /* Variable MTRRs */
1720 int idx, is_mtrr_mask;
1723 idx = (msr - 0x200) / 2;
1724 is_mtrr_mask = msr - 0x200 - 2 * idx;
1727 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1730 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1734 kvm_mmu_reset_context(vcpu);
1738 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1740 u64 mcg_cap = vcpu->arch.mcg_cap;
1741 unsigned bank_num = mcg_cap & 0xff;
1744 case MSR_IA32_MCG_STATUS:
1745 vcpu->arch.mcg_status = data;
1747 case MSR_IA32_MCG_CTL:
1748 if (!(mcg_cap & MCG_CTL_P))
1750 if (data != 0 && data != ~(u64)0)
1752 vcpu->arch.mcg_ctl = data;
1755 if (msr >= MSR_IA32_MC0_CTL &&
1756 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1757 u32 offset = msr - MSR_IA32_MC0_CTL;
1758 /* only 0 or all 1s can be written to IA32_MCi_CTL
1759 * some Linux kernels though clear bit 10 in bank 4 to
1760 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1761 * this to avoid an uncatched #GP in the guest
1763 if ((offset & 0x3) == 0 &&
1764 data != 0 && (data | (1 << 10)) != ~(u64)0)
1766 vcpu->arch.mce_banks[offset] = data;
1774 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1776 struct kvm *kvm = vcpu->kvm;
1777 int lm = is_long_mode(vcpu);
1778 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1779 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1780 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1781 : kvm->arch.xen_hvm_config.blob_size_32;
1782 u32 page_num = data & ~PAGE_MASK;
1783 u64 page_addr = data & PAGE_MASK;
1788 if (page_num >= blob_size)
1791 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1796 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1805 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1807 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1810 static bool kvm_hv_msr_partition_wide(u32 msr)
1814 case HV_X64_MSR_GUEST_OS_ID:
1815 case HV_X64_MSR_HYPERCALL:
1823 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1825 struct kvm *kvm = vcpu->kvm;
1828 case HV_X64_MSR_GUEST_OS_ID:
1829 kvm->arch.hv_guest_os_id = data;
1830 /* setting guest os id to zero disables hypercall page */
1831 if (!kvm->arch.hv_guest_os_id)
1832 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1834 case HV_X64_MSR_HYPERCALL: {
1839 /* if guest os id is not set hypercall should remain disabled */
1840 if (!kvm->arch.hv_guest_os_id)
1842 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1843 kvm->arch.hv_hypercall = data;
1846 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1847 addr = gfn_to_hva(kvm, gfn);
1848 if (kvm_is_error_hva(addr))
1850 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1851 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1852 if (__copy_to_user((void __user *)addr, instructions, 4))
1854 kvm->arch.hv_hypercall = data;
1858 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1859 "data 0x%llx\n", msr, data);
1865 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1868 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1871 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1872 vcpu->arch.hv_vapic = data;
1875 addr = gfn_to_hva(vcpu->kvm, data >>
1876 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1877 if (kvm_is_error_hva(addr))
1879 if (__clear_user((void __user *)addr, PAGE_SIZE))
1881 vcpu->arch.hv_vapic = data;
1884 case HV_X64_MSR_EOI:
1885 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1886 case HV_X64_MSR_ICR:
1887 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1888 case HV_X64_MSR_TPR:
1889 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1891 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1892 "data 0x%llx\n", msr, data);
1899 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1901 gpa_t gpa = data & ~0x3f;
1903 /* Bits 2:5 are reserved, Should be zero */
1907 vcpu->arch.apf.msr_val = data;
1909 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1910 kvm_clear_async_pf_completion_queue(vcpu);
1911 kvm_async_pf_hash_reset(vcpu);
1915 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1919 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1920 kvm_async_pf_wakeup_all(vcpu);
1924 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1926 vcpu->arch.pv_time_enabled = false;
1929 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1933 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1936 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1937 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1938 vcpu->arch.st.accum_steal = delta;
1941 static void record_steal_time(struct kvm_vcpu *vcpu)
1943 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1946 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1947 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1950 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1951 vcpu->arch.st.steal.version += 2;
1952 vcpu->arch.st.accum_steal = 0;
1954 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1955 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1958 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1961 u32 msr = msr_info->index;
1962 u64 data = msr_info->data;
1965 case MSR_AMD64_NB_CFG:
1966 case MSR_IA32_UCODE_REV:
1967 case MSR_IA32_UCODE_WRITE:
1968 case MSR_VM_HSAVE_PA:
1969 case MSR_AMD64_PATCH_LOADER:
1970 case MSR_AMD64_BU_CFG2:
1974 return set_efer(vcpu, data);
1976 data &= ~(u64)0x40; /* ignore flush filter disable */
1977 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1978 data &= ~(u64)0x8; /* ignore TLB cache disable */
1980 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1985 case MSR_FAM10H_MMIO_CONF_BASE:
1987 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1992 case MSR_IA32_DEBUGCTLMSR:
1994 /* We support the non-activated case already */
1996 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1997 /* Values other than LBR and BTF are vendor-specific,
1998 thus reserved and should throw a #GP */
2001 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2004 case 0x200 ... 0x2ff:
2005 return set_msr_mtrr(vcpu, msr, data);
2006 case MSR_IA32_APICBASE:
2007 kvm_set_apic_base(vcpu, data);
2009 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2010 return kvm_x2apic_msr_write(vcpu, msr, data);
2011 case MSR_IA32_TSCDEADLINE:
2012 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2014 case MSR_IA32_TSC_ADJUST:
2015 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2016 if (!msr_info->host_initiated) {
2017 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2018 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2020 vcpu->arch.ia32_tsc_adjust_msr = data;
2023 case MSR_IA32_MISC_ENABLE:
2024 vcpu->arch.ia32_misc_enable_msr = data;
2026 case MSR_KVM_WALL_CLOCK_NEW:
2027 case MSR_KVM_WALL_CLOCK:
2028 vcpu->kvm->arch.wall_clock = data;
2029 kvm_write_wall_clock(vcpu->kvm, data);
2031 case MSR_KVM_SYSTEM_TIME_NEW:
2032 case MSR_KVM_SYSTEM_TIME: {
2034 kvmclock_reset(vcpu);
2036 vcpu->arch.time = data;
2037 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2039 /* we verify if the enable bit is set... */
2043 gpa_offset = data & ~(PAGE_MASK | 1);
2045 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2046 &vcpu->arch.pv_time, data & ~1ULL,
2047 sizeof(struct pvclock_vcpu_time_info)))
2048 vcpu->arch.pv_time_enabled = false;
2050 vcpu->arch.pv_time_enabled = true;
2054 case MSR_KVM_ASYNC_PF_EN:
2055 if (kvm_pv_enable_async_pf(vcpu, data))
2058 case MSR_KVM_STEAL_TIME:
2060 if (unlikely(!sched_info_on()))
2063 if (data & KVM_STEAL_RESERVED_MASK)
2066 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2067 data & KVM_STEAL_VALID_BITS,
2068 sizeof(struct kvm_steal_time)))
2071 vcpu->arch.st.msr_val = data;
2073 if (!(data & KVM_MSR_ENABLED))
2076 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2079 accumulate_steal_time(vcpu);
2082 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2085 case MSR_KVM_PV_EOI_EN:
2086 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2090 case MSR_IA32_MCG_CTL:
2091 case MSR_IA32_MCG_STATUS:
2092 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2093 return set_msr_mce(vcpu, msr, data);
2095 /* Performance counters are not protected by a CPUID bit,
2096 * so we should check all of them in the generic path for the sake of
2097 * cross vendor migration.
2098 * Writing a zero into the event select MSRs disables them,
2099 * which we perfectly emulate ;-). Any other value should be at least
2100 * reported, some guests depend on them.
2102 case MSR_K7_EVNTSEL0:
2103 case MSR_K7_EVNTSEL1:
2104 case MSR_K7_EVNTSEL2:
2105 case MSR_K7_EVNTSEL3:
2107 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2108 "0x%x data 0x%llx\n", msr, data);
2110 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2111 * so we ignore writes to make it happy.
2113 case MSR_K7_PERFCTR0:
2114 case MSR_K7_PERFCTR1:
2115 case MSR_K7_PERFCTR2:
2116 case MSR_K7_PERFCTR3:
2117 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2118 "0x%x data 0x%llx\n", msr, data);
2120 case MSR_P6_PERFCTR0:
2121 case MSR_P6_PERFCTR1:
2123 case MSR_P6_EVNTSEL0:
2124 case MSR_P6_EVNTSEL1:
2125 if (kvm_pmu_msr(vcpu, msr))
2126 return kvm_pmu_set_msr(vcpu, msr_info);
2128 if (pr || data != 0)
2129 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2130 "0x%x data 0x%llx\n", msr, data);
2132 case MSR_K7_CLK_CTL:
2134 * Ignore all writes to this no longer documented MSR.
2135 * Writes are only relevant for old K7 processors,
2136 * all pre-dating SVM, but a recommended workaround from
2137 * AMD for these chips. It is possible to specify the
2138 * affected processor models on the command line, hence
2139 * the need to ignore the workaround.
2142 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2143 if (kvm_hv_msr_partition_wide(msr)) {
2145 mutex_lock(&vcpu->kvm->lock);
2146 r = set_msr_hyperv_pw(vcpu, msr, data);
2147 mutex_unlock(&vcpu->kvm->lock);
2150 return set_msr_hyperv(vcpu, msr, data);
2152 case MSR_IA32_BBL_CR_CTL3:
2153 /* Drop writes to this legacy MSR -- see rdmsr
2154 * counterpart for further detail.
2156 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2158 case MSR_AMD64_OSVW_ID_LENGTH:
2159 if (!guest_cpuid_has_osvw(vcpu))
2161 vcpu->arch.osvw.length = data;
2163 case MSR_AMD64_OSVW_STATUS:
2164 if (!guest_cpuid_has_osvw(vcpu))
2166 vcpu->arch.osvw.status = data;
2169 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2170 return xen_hvm_config(vcpu, data);
2171 if (kvm_pmu_msr(vcpu, msr))
2172 return kvm_pmu_set_msr(vcpu, msr_info);
2174 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2178 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2185 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2189 * Reads an msr value (of 'msr_index') into 'pdata'.
2190 * Returns 0 on success, non-0 otherwise.
2191 * Assumes vcpu_load() was already called.
2193 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2195 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2198 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2200 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2202 if (!msr_mtrr_valid(msr))
2205 if (msr == MSR_MTRRdefType)
2206 *pdata = vcpu->arch.mtrr_state.def_type +
2207 (vcpu->arch.mtrr_state.enabled << 10);
2208 else if (msr == MSR_MTRRfix64K_00000)
2210 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2211 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2212 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2213 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2214 else if (msr == MSR_IA32_CR_PAT)
2215 *pdata = vcpu->arch.pat;
2216 else { /* Variable MTRRs */
2217 int idx, is_mtrr_mask;
2220 idx = (msr - 0x200) / 2;
2221 is_mtrr_mask = msr - 0x200 - 2 * idx;
2224 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2227 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2234 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2237 u64 mcg_cap = vcpu->arch.mcg_cap;
2238 unsigned bank_num = mcg_cap & 0xff;
2241 case MSR_IA32_P5_MC_ADDR:
2242 case MSR_IA32_P5_MC_TYPE:
2245 case MSR_IA32_MCG_CAP:
2246 data = vcpu->arch.mcg_cap;
2248 case MSR_IA32_MCG_CTL:
2249 if (!(mcg_cap & MCG_CTL_P))
2251 data = vcpu->arch.mcg_ctl;
2253 case MSR_IA32_MCG_STATUS:
2254 data = vcpu->arch.mcg_status;
2257 if (msr >= MSR_IA32_MC0_CTL &&
2258 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2259 u32 offset = msr - MSR_IA32_MC0_CTL;
2260 data = vcpu->arch.mce_banks[offset];
2269 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2272 struct kvm *kvm = vcpu->kvm;
2275 case HV_X64_MSR_GUEST_OS_ID:
2276 data = kvm->arch.hv_guest_os_id;
2278 case HV_X64_MSR_HYPERCALL:
2279 data = kvm->arch.hv_hypercall;
2282 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2290 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2295 case HV_X64_MSR_VP_INDEX: {
2298 kvm_for_each_vcpu(r, v, vcpu->kvm)
2303 case HV_X64_MSR_EOI:
2304 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2305 case HV_X64_MSR_ICR:
2306 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2307 case HV_X64_MSR_TPR:
2308 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2309 case HV_X64_MSR_APIC_ASSIST_PAGE:
2310 data = vcpu->arch.hv_vapic;
2313 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2320 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2325 case MSR_IA32_PLATFORM_ID:
2326 case MSR_IA32_EBL_CR_POWERON:
2327 case MSR_IA32_DEBUGCTLMSR:
2328 case MSR_IA32_LASTBRANCHFROMIP:
2329 case MSR_IA32_LASTBRANCHTOIP:
2330 case MSR_IA32_LASTINTFROMIP:
2331 case MSR_IA32_LASTINTTOIP:
2334 case MSR_VM_HSAVE_PA:
2335 case MSR_K7_EVNTSEL0:
2336 case MSR_K7_PERFCTR0:
2337 case MSR_K8_INT_PENDING_MSG:
2338 case MSR_AMD64_NB_CFG:
2339 case MSR_FAM10H_MMIO_CONF_BASE:
2340 case MSR_AMD64_BU_CFG2:
2343 case MSR_P6_PERFCTR0:
2344 case MSR_P6_PERFCTR1:
2345 case MSR_P6_EVNTSEL0:
2346 case MSR_P6_EVNTSEL1:
2347 if (kvm_pmu_msr(vcpu, msr))
2348 return kvm_pmu_get_msr(vcpu, msr, pdata);
2351 case MSR_IA32_UCODE_REV:
2352 data = 0x100000000ULL;
2355 data = 0x500 | KVM_NR_VAR_MTRR;
2357 case 0x200 ... 0x2ff:
2358 return get_msr_mtrr(vcpu, msr, pdata);
2359 case 0xcd: /* fsb frequency */
2363 * MSR_EBC_FREQUENCY_ID
2364 * Conservative value valid for even the basic CPU models.
2365 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2366 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2367 * and 266MHz for model 3, or 4. Set Core Clock
2368 * Frequency to System Bus Frequency Ratio to 1 (bits
2369 * 31:24) even though these are only valid for CPU
2370 * models > 2, however guests may end up dividing or
2371 * multiplying by zero otherwise.
2373 case MSR_EBC_FREQUENCY_ID:
2376 case MSR_IA32_APICBASE:
2377 data = kvm_get_apic_base(vcpu);
2379 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2380 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2382 case MSR_IA32_TSCDEADLINE:
2383 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2385 case MSR_IA32_TSC_ADJUST:
2386 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2388 case MSR_IA32_MISC_ENABLE:
2389 data = vcpu->arch.ia32_misc_enable_msr;
2391 case MSR_IA32_PERF_STATUS:
2392 /* TSC increment by tick */
2394 /* CPU multiplier */
2395 data |= (((uint64_t)4ULL) << 40);
2398 data = vcpu->arch.efer;
2400 case MSR_KVM_WALL_CLOCK:
2401 case MSR_KVM_WALL_CLOCK_NEW:
2402 data = vcpu->kvm->arch.wall_clock;
2404 case MSR_KVM_SYSTEM_TIME:
2405 case MSR_KVM_SYSTEM_TIME_NEW:
2406 data = vcpu->arch.time;
2408 case MSR_KVM_ASYNC_PF_EN:
2409 data = vcpu->arch.apf.msr_val;
2411 case MSR_KVM_STEAL_TIME:
2412 data = vcpu->arch.st.msr_val;
2414 case MSR_KVM_PV_EOI_EN:
2415 data = vcpu->arch.pv_eoi.msr_val;
2417 case MSR_IA32_P5_MC_ADDR:
2418 case MSR_IA32_P5_MC_TYPE:
2419 case MSR_IA32_MCG_CAP:
2420 case MSR_IA32_MCG_CTL:
2421 case MSR_IA32_MCG_STATUS:
2422 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2423 return get_msr_mce(vcpu, msr, pdata);
2424 case MSR_K7_CLK_CTL:
2426 * Provide expected ramp-up count for K7. All other
2427 * are set to zero, indicating minimum divisors for
2430 * This prevents guest kernels on AMD host with CPU
2431 * type 6, model 8 and higher from exploding due to
2432 * the rdmsr failing.
2436 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2437 if (kvm_hv_msr_partition_wide(msr)) {
2439 mutex_lock(&vcpu->kvm->lock);
2440 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2441 mutex_unlock(&vcpu->kvm->lock);
2444 return get_msr_hyperv(vcpu, msr, pdata);
2446 case MSR_IA32_BBL_CR_CTL3:
2447 /* This legacy MSR exists but isn't fully documented in current
2448 * silicon. It is however accessed by winxp in very narrow
2449 * scenarios where it sets bit #19, itself documented as
2450 * a "reserved" bit. Best effort attempt to source coherent
2451 * read data here should the balance of the register be
2452 * interpreted by the guest:
2454 * L2 cache control register 3: 64GB range, 256KB size,
2455 * enabled, latency 0x1, configured
2459 case MSR_AMD64_OSVW_ID_LENGTH:
2460 if (!guest_cpuid_has_osvw(vcpu))
2462 data = vcpu->arch.osvw.length;
2464 case MSR_AMD64_OSVW_STATUS:
2465 if (!guest_cpuid_has_osvw(vcpu))
2467 data = vcpu->arch.osvw.status;
2470 if (kvm_pmu_msr(vcpu, msr))
2471 return kvm_pmu_get_msr(vcpu, msr, pdata);
2473 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2476 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2484 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2487 * Read or write a bunch of msrs. All parameters are kernel addresses.
2489 * @return number of msrs set successfully.
2491 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2492 struct kvm_msr_entry *entries,
2493 int (*do_msr)(struct kvm_vcpu *vcpu,
2494 unsigned index, u64 *data))
2498 idx = srcu_read_lock(&vcpu->kvm->srcu);
2499 for (i = 0; i < msrs->nmsrs; ++i)
2500 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2502 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2508 * Read or write a bunch of msrs. Parameters are user addresses.
2510 * @return number of msrs set successfully.
2512 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2513 int (*do_msr)(struct kvm_vcpu *vcpu,
2514 unsigned index, u64 *data),
2517 struct kvm_msrs msrs;
2518 struct kvm_msr_entry *entries;
2523 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2527 if (msrs.nmsrs >= MAX_IO_MSRS)
2530 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2531 entries = memdup_user(user_msrs->entries, size);
2532 if (IS_ERR(entries)) {
2533 r = PTR_ERR(entries);
2537 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2542 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2553 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2558 case KVM_CAP_IRQCHIP:
2560 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2561 case KVM_CAP_SET_TSS_ADDR:
2562 case KVM_CAP_EXT_CPUID:
2563 case KVM_CAP_EXT_EMUL_CPUID:
2564 case KVM_CAP_CLOCKSOURCE:
2566 case KVM_CAP_NOP_IO_DELAY:
2567 case KVM_CAP_MP_STATE:
2568 case KVM_CAP_SYNC_MMU:
2569 case KVM_CAP_USER_NMI:
2570 case KVM_CAP_REINJECT_CONTROL:
2571 case KVM_CAP_IRQ_INJECT_STATUS:
2573 case KVM_CAP_IOEVENTFD:
2575 case KVM_CAP_PIT_STATE2:
2576 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2577 case KVM_CAP_XEN_HVM:
2578 case KVM_CAP_ADJUST_CLOCK:
2579 case KVM_CAP_VCPU_EVENTS:
2580 case KVM_CAP_HYPERV:
2581 case KVM_CAP_HYPERV_VAPIC:
2582 case KVM_CAP_HYPERV_SPIN:
2583 case KVM_CAP_PCI_SEGMENT:
2584 case KVM_CAP_DEBUGREGS:
2585 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2587 case KVM_CAP_ASYNC_PF:
2588 case KVM_CAP_GET_TSC_KHZ:
2589 case KVM_CAP_KVMCLOCK_CTRL:
2590 case KVM_CAP_READONLY_MEM:
2591 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2592 case KVM_CAP_ASSIGN_DEV_IRQ:
2593 case KVM_CAP_PCI_2_3:
2597 case KVM_CAP_COALESCED_MMIO:
2598 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2601 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2603 case KVM_CAP_NR_VCPUS:
2604 r = KVM_SOFT_MAX_VCPUS;
2606 case KVM_CAP_MAX_VCPUS:
2609 case KVM_CAP_NR_MEMSLOTS:
2610 r = KVM_USER_MEM_SLOTS;
2612 case KVM_CAP_PV_MMU: /* obsolete */
2615 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2617 r = iommu_present(&pci_bus_type);
2621 r = KVM_MAX_MCE_BANKS;
2626 case KVM_CAP_TSC_CONTROL:
2627 r = kvm_has_tsc_control;
2629 case KVM_CAP_TSC_DEADLINE_TIMER:
2630 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2640 long kvm_arch_dev_ioctl(struct file *filp,
2641 unsigned int ioctl, unsigned long arg)
2643 void __user *argp = (void __user *)arg;
2647 case KVM_GET_MSR_INDEX_LIST: {
2648 struct kvm_msr_list __user *user_msr_list = argp;
2649 struct kvm_msr_list msr_list;
2653 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2656 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2657 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2660 if (n < msr_list.nmsrs)
2663 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2664 num_msrs_to_save * sizeof(u32)))
2666 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2668 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2673 case KVM_GET_SUPPORTED_CPUID:
2674 case KVM_GET_EMULATED_CPUID: {
2675 struct kvm_cpuid2 __user *cpuid_arg = argp;
2676 struct kvm_cpuid2 cpuid;
2679 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2682 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2688 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2693 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2696 mce_cap = KVM_MCE_CAP_SUPPORTED;
2698 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2710 static void wbinvd_ipi(void *garbage)
2715 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2717 return vcpu->kvm->arch.iommu_domain &&
2718 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2721 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2723 /* Address WBINVD may be executed by guest */
2724 if (need_emulate_wbinvd(vcpu)) {
2725 if (kvm_x86_ops->has_wbinvd_exit())
2726 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2727 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2728 smp_call_function_single(vcpu->cpu,
2729 wbinvd_ipi, NULL, 1);
2732 kvm_x86_ops->vcpu_load(vcpu, cpu);
2734 /* Apply any externally detected TSC adjustments (due to suspend) */
2735 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2736 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2737 vcpu->arch.tsc_offset_adjustment = 0;
2738 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2741 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2742 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2743 native_read_tsc() - vcpu->arch.last_host_tsc;
2745 mark_tsc_unstable("KVM discovered backwards TSC");
2746 if (check_tsc_unstable()) {
2747 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2748 vcpu->arch.last_guest_tsc);
2749 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2750 vcpu->arch.tsc_catchup = 1;
2753 * On a host with synchronized TSC, there is no need to update
2754 * kvmclock on vcpu->cpu migration
2756 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2757 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2758 if (vcpu->cpu != cpu)
2759 kvm_migrate_timers(vcpu);
2763 accumulate_steal_time(vcpu);
2764 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2767 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2769 kvm_x86_ops->vcpu_put(vcpu);
2770 kvm_put_guest_fpu(vcpu);
2771 vcpu->arch.last_host_tsc = native_read_tsc();
2774 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2775 struct kvm_lapic_state *s)
2777 kvm_x86_ops->sync_pir_to_irr(vcpu);
2778 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2783 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2784 struct kvm_lapic_state *s)
2786 kvm_apic_post_state_restore(vcpu, s);
2787 update_cr8_intercept(vcpu);
2792 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2793 struct kvm_interrupt *irq)
2795 if (irq->irq >= KVM_NR_INTERRUPTS)
2797 if (irqchip_in_kernel(vcpu->kvm))
2800 kvm_queue_interrupt(vcpu, irq->irq, false);
2801 kvm_make_request(KVM_REQ_EVENT, vcpu);
2806 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2808 kvm_inject_nmi(vcpu);
2813 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2814 struct kvm_tpr_access_ctl *tac)
2818 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2822 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2826 unsigned bank_num = mcg_cap & 0xff, bank;
2829 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2831 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2834 vcpu->arch.mcg_cap = mcg_cap;
2835 /* Init IA32_MCG_CTL to all 1s */
2836 if (mcg_cap & MCG_CTL_P)
2837 vcpu->arch.mcg_ctl = ~(u64)0;
2838 /* Init IA32_MCi_CTL to all 1s */
2839 for (bank = 0; bank < bank_num; bank++)
2840 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2845 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2846 struct kvm_x86_mce *mce)
2848 u64 mcg_cap = vcpu->arch.mcg_cap;
2849 unsigned bank_num = mcg_cap & 0xff;
2850 u64 *banks = vcpu->arch.mce_banks;
2852 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2855 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2856 * reporting is disabled
2858 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2859 vcpu->arch.mcg_ctl != ~(u64)0)
2861 banks += 4 * mce->bank;
2863 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2864 * reporting is disabled for the bank
2866 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2868 if (mce->status & MCI_STATUS_UC) {
2869 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2870 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2871 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2874 if (banks[1] & MCI_STATUS_VAL)
2875 mce->status |= MCI_STATUS_OVER;
2876 banks[2] = mce->addr;
2877 banks[3] = mce->misc;
2878 vcpu->arch.mcg_status = mce->mcg_status;
2879 banks[1] = mce->status;
2880 kvm_queue_exception(vcpu, MC_VECTOR);
2881 } else if (!(banks[1] & MCI_STATUS_VAL)
2882 || !(banks[1] & MCI_STATUS_UC)) {
2883 if (banks[1] & MCI_STATUS_VAL)
2884 mce->status |= MCI_STATUS_OVER;
2885 banks[2] = mce->addr;
2886 banks[3] = mce->misc;
2887 banks[1] = mce->status;
2889 banks[1] |= MCI_STATUS_OVER;
2893 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2894 struct kvm_vcpu_events *events)
2897 events->exception.injected =
2898 vcpu->arch.exception.pending &&
2899 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2900 events->exception.nr = vcpu->arch.exception.nr;
2901 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2902 events->exception.pad = 0;
2903 events->exception.error_code = vcpu->arch.exception.error_code;
2905 events->interrupt.injected =
2906 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2907 events->interrupt.nr = vcpu->arch.interrupt.nr;
2908 events->interrupt.soft = 0;
2909 events->interrupt.shadow =
2910 kvm_x86_ops->get_interrupt_shadow(vcpu,
2911 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2913 events->nmi.injected = vcpu->arch.nmi_injected;
2914 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2915 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2916 events->nmi.pad = 0;
2918 events->sipi_vector = 0; /* never valid when reporting to user space */
2920 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2921 | KVM_VCPUEVENT_VALID_SHADOW);
2922 memset(&events->reserved, 0, sizeof(events->reserved));
2925 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2926 struct kvm_vcpu_events *events)
2928 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2929 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2930 | KVM_VCPUEVENT_VALID_SHADOW))
2934 vcpu->arch.exception.pending = events->exception.injected;
2935 vcpu->arch.exception.nr = events->exception.nr;
2936 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2937 vcpu->arch.exception.error_code = events->exception.error_code;
2939 vcpu->arch.interrupt.pending = events->interrupt.injected;
2940 vcpu->arch.interrupt.nr = events->interrupt.nr;
2941 vcpu->arch.interrupt.soft = events->interrupt.soft;
2942 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2943 kvm_x86_ops->set_interrupt_shadow(vcpu,
2944 events->interrupt.shadow);
2946 vcpu->arch.nmi_injected = events->nmi.injected;
2947 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2948 vcpu->arch.nmi_pending = events->nmi.pending;
2949 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2951 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2952 kvm_vcpu_has_lapic(vcpu))
2953 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2955 kvm_make_request(KVM_REQ_EVENT, vcpu);
2960 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2961 struct kvm_debugregs *dbgregs)
2963 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2964 dbgregs->dr6 = vcpu->arch.dr6;
2965 dbgregs->dr7 = vcpu->arch.dr7;
2967 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2970 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2971 struct kvm_debugregs *dbgregs)
2976 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2977 vcpu->arch.dr6 = dbgregs->dr6;
2978 vcpu->arch.dr7 = dbgregs->dr7;
2983 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2984 struct kvm_xsave *guest_xsave)
2987 memcpy(guest_xsave->region,
2988 &vcpu->arch.guest_fpu.state->xsave,
2991 memcpy(guest_xsave->region,
2992 &vcpu->arch.guest_fpu.state->fxsave,
2993 sizeof(struct i387_fxsave_struct));
2994 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2999 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3000 struct kvm_xsave *guest_xsave)
3003 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3006 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3007 guest_xsave->region, xstate_size);
3009 if (xstate_bv & ~XSTATE_FPSSE)
3011 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3012 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3017 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3018 struct kvm_xcrs *guest_xcrs)
3020 if (!cpu_has_xsave) {
3021 guest_xcrs->nr_xcrs = 0;
3025 guest_xcrs->nr_xcrs = 1;
3026 guest_xcrs->flags = 0;
3027 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3028 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3031 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3032 struct kvm_xcrs *guest_xcrs)
3039 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3042 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3043 /* Only support XCR0 currently */
3044 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
3045 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3046 guest_xcrs->xcrs[0].value);
3055 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3056 * stopped by the hypervisor. This function will be called from the host only.
3057 * EINVAL is returned when the host attempts to set the flag for a guest that
3058 * does not support pv clocks.
3060 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3062 if (!vcpu->arch.pv_time_enabled)
3064 vcpu->arch.pvclock_set_guest_stopped_request = true;
3065 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3069 long kvm_arch_vcpu_ioctl(struct file *filp,
3070 unsigned int ioctl, unsigned long arg)
3072 struct kvm_vcpu *vcpu = filp->private_data;
3073 void __user *argp = (void __user *)arg;
3076 struct kvm_lapic_state *lapic;
3077 struct kvm_xsave *xsave;
3078 struct kvm_xcrs *xcrs;
3084 case KVM_GET_LAPIC: {
3086 if (!vcpu->arch.apic)
3088 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3093 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3097 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3102 case KVM_SET_LAPIC: {
3104 if (!vcpu->arch.apic)
3106 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3107 if (IS_ERR(u.lapic))
3108 return PTR_ERR(u.lapic);
3110 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3113 case KVM_INTERRUPT: {
3114 struct kvm_interrupt irq;
3117 if (copy_from_user(&irq, argp, sizeof irq))
3119 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3123 r = kvm_vcpu_ioctl_nmi(vcpu);
3126 case KVM_SET_CPUID: {
3127 struct kvm_cpuid __user *cpuid_arg = argp;
3128 struct kvm_cpuid cpuid;
3131 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3133 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3136 case KVM_SET_CPUID2: {
3137 struct kvm_cpuid2 __user *cpuid_arg = argp;
3138 struct kvm_cpuid2 cpuid;
3141 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3143 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3144 cpuid_arg->entries);
3147 case KVM_GET_CPUID2: {
3148 struct kvm_cpuid2 __user *cpuid_arg = argp;
3149 struct kvm_cpuid2 cpuid;
3152 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3154 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3155 cpuid_arg->entries);
3159 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3165 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3168 r = msr_io(vcpu, argp, do_set_msr, 0);
3170 case KVM_TPR_ACCESS_REPORTING: {
3171 struct kvm_tpr_access_ctl tac;
3174 if (copy_from_user(&tac, argp, sizeof tac))
3176 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3180 if (copy_to_user(argp, &tac, sizeof tac))
3185 case KVM_SET_VAPIC_ADDR: {
3186 struct kvm_vapic_addr va;
3189 if (!irqchip_in_kernel(vcpu->kvm))
3192 if (copy_from_user(&va, argp, sizeof va))
3194 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3197 case KVM_X86_SETUP_MCE: {
3201 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3203 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3206 case KVM_X86_SET_MCE: {
3207 struct kvm_x86_mce mce;
3210 if (copy_from_user(&mce, argp, sizeof mce))
3212 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3215 case KVM_GET_VCPU_EVENTS: {
3216 struct kvm_vcpu_events events;
3218 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3221 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3226 case KVM_SET_VCPU_EVENTS: {
3227 struct kvm_vcpu_events events;
3230 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3233 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3236 case KVM_GET_DEBUGREGS: {
3237 struct kvm_debugregs dbgregs;
3239 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3242 if (copy_to_user(argp, &dbgregs,
3243 sizeof(struct kvm_debugregs)))
3248 case KVM_SET_DEBUGREGS: {
3249 struct kvm_debugregs dbgregs;
3252 if (copy_from_user(&dbgregs, argp,
3253 sizeof(struct kvm_debugregs)))
3256 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3259 case KVM_GET_XSAVE: {
3260 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3265 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3268 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3273 case KVM_SET_XSAVE: {
3274 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3275 if (IS_ERR(u.xsave))
3276 return PTR_ERR(u.xsave);
3278 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3281 case KVM_GET_XCRS: {
3282 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3287 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3290 if (copy_to_user(argp, u.xcrs,
3291 sizeof(struct kvm_xcrs)))
3296 case KVM_SET_XCRS: {
3297 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3299 return PTR_ERR(u.xcrs);
3301 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3304 case KVM_SET_TSC_KHZ: {
3308 user_tsc_khz = (u32)arg;
3310 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3313 if (user_tsc_khz == 0)
3314 user_tsc_khz = tsc_khz;
3316 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3321 case KVM_GET_TSC_KHZ: {
3322 r = vcpu->arch.virtual_tsc_khz;
3325 case KVM_KVMCLOCK_CTRL: {
3326 r = kvm_set_guest_paused(vcpu);
3337 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3339 return VM_FAULT_SIGBUS;
3342 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3346 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3348 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3352 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3355 kvm->arch.ept_identity_map_addr = ident_addr;
3359 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3360 u32 kvm_nr_mmu_pages)
3362 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3365 mutex_lock(&kvm->slots_lock);
3367 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3368 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3370 mutex_unlock(&kvm->slots_lock);
3374 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3376 return kvm->arch.n_max_mmu_pages;
3379 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3384 switch (chip->chip_id) {
3385 case KVM_IRQCHIP_PIC_MASTER:
3386 memcpy(&chip->chip.pic,
3387 &pic_irqchip(kvm)->pics[0],
3388 sizeof(struct kvm_pic_state));
3390 case KVM_IRQCHIP_PIC_SLAVE:
3391 memcpy(&chip->chip.pic,
3392 &pic_irqchip(kvm)->pics[1],
3393 sizeof(struct kvm_pic_state));
3395 case KVM_IRQCHIP_IOAPIC:
3396 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3405 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3410 switch (chip->chip_id) {
3411 case KVM_IRQCHIP_PIC_MASTER:
3412 spin_lock(&pic_irqchip(kvm)->lock);
3413 memcpy(&pic_irqchip(kvm)->pics[0],
3415 sizeof(struct kvm_pic_state));
3416 spin_unlock(&pic_irqchip(kvm)->lock);
3418 case KVM_IRQCHIP_PIC_SLAVE:
3419 spin_lock(&pic_irqchip(kvm)->lock);
3420 memcpy(&pic_irqchip(kvm)->pics[1],
3422 sizeof(struct kvm_pic_state));
3423 spin_unlock(&pic_irqchip(kvm)->lock);
3425 case KVM_IRQCHIP_IOAPIC:
3426 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3432 kvm_pic_update_irq(pic_irqchip(kvm));
3436 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3440 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3441 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3442 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3446 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3450 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3451 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3452 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3453 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3457 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3461 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3462 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3463 sizeof(ps->channels));
3464 ps->flags = kvm->arch.vpit->pit_state.flags;
3465 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3466 memset(&ps->reserved, 0, sizeof(ps->reserved));
3470 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3472 int r = 0, start = 0;
3473 u32 prev_legacy, cur_legacy;
3474 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3475 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3476 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3477 if (!prev_legacy && cur_legacy)
3479 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3480 sizeof(kvm->arch.vpit->pit_state.channels));
3481 kvm->arch.vpit->pit_state.flags = ps->flags;
3482 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3483 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3487 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3488 struct kvm_reinject_control *control)
3490 if (!kvm->arch.vpit)
3492 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3493 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3494 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3499 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3500 * @kvm: kvm instance
3501 * @log: slot id and address to which we copy the log
3503 * We need to keep it in mind that VCPU threads can write to the bitmap
3504 * concurrently. So, to avoid losing data, we keep the following order for
3507 * 1. Take a snapshot of the bit and clear it if needed.
3508 * 2. Write protect the corresponding page.
3509 * 3. Flush TLB's if needed.
3510 * 4. Copy the snapshot to the userspace.
3512 * Between 2 and 3, the guest may write to the page using the remaining TLB
3513 * entry. This is not a problem because the page will be reported dirty at
3514 * step 4 using the snapshot taken before and step 3 ensures that successive
3515 * writes will be logged for the next call.
3517 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3520 struct kvm_memory_slot *memslot;
3522 unsigned long *dirty_bitmap;
3523 unsigned long *dirty_bitmap_buffer;
3524 bool is_dirty = false;
3526 mutex_lock(&kvm->slots_lock);
3529 if (log->slot >= KVM_USER_MEM_SLOTS)
3532 memslot = id_to_memslot(kvm->memslots, log->slot);
3534 dirty_bitmap = memslot->dirty_bitmap;
3539 n = kvm_dirty_bitmap_bytes(memslot);
3541 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3542 memset(dirty_bitmap_buffer, 0, n);
3544 spin_lock(&kvm->mmu_lock);
3546 for (i = 0; i < n / sizeof(long); i++) {
3550 if (!dirty_bitmap[i])
3555 mask = xchg(&dirty_bitmap[i], 0);
3556 dirty_bitmap_buffer[i] = mask;
3558 offset = i * BITS_PER_LONG;
3559 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3562 kvm_flush_remote_tlbs(kvm);
3564 spin_unlock(&kvm->mmu_lock);
3567 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3572 mutex_unlock(&kvm->slots_lock);
3576 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3579 if (!irqchip_in_kernel(kvm))
3582 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3583 irq_event->irq, irq_event->level,
3588 long kvm_arch_vm_ioctl(struct file *filp,
3589 unsigned int ioctl, unsigned long arg)
3591 struct kvm *kvm = filp->private_data;
3592 void __user *argp = (void __user *)arg;
3595 * This union makes it completely explicit to gcc-3.x
3596 * that these two variables' stack usage should be
3597 * combined, not added together.
3600 struct kvm_pit_state ps;
3601 struct kvm_pit_state2 ps2;
3602 struct kvm_pit_config pit_config;
3606 case KVM_SET_TSS_ADDR:
3607 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3609 case KVM_SET_IDENTITY_MAP_ADDR: {
3613 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3615 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3618 case KVM_SET_NR_MMU_PAGES:
3619 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3621 case KVM_GET_NR_MMU_PAGES:
3622 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3624 case KVM_CREATE_IRQCHIP: {
3625 struct kvm_pic *vpic;
3627 mutex_lock(&kvm->lock);
3630 goto create_irqchip_unlock;
3632 if (atomic_read(&kvm->online_vcpus))
3633 goto create_irqchip_unlock;
3635 vpic = kvm_create_pic(kvm);
3637 r = kvm_ioapic_init(kvm);
3639 mutex_lock(&kvm->slots_lock);
3640 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3642 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3644 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3646 mutex_unlock(&kvm->slots_lock);
3648 goto create_irqchip_unlock;
3651 goto create_irqchip_unlock;
3653 kvm->arch.vpic = vpic;
3655 r = kvm_setup_default_irq_routing(kvm);
3657 mutex_lock(&kvm->slots_lock);
3658 mutex_lock(&kvm->irq_lock);
3659 kvm_ioapic_destroy(kvm);
3660 kvm_destroy_pic(kvm);
3661 mutex_unlock(&kvm->irq_lock);
3662 mutex_unlock(&kvm->slots_lock);
3664 create_irqchip_unlock:
3665 mutex_unlock(&kvm->lock);
3668 case KVM_CREATE_PIT:
3669 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3671 case KVM_CREATE_PIT2:
3673 if (copy_from_user(&u.pit_config, argp,
3674 sizeof(struct kvm_pit_config)))
3677 mutex_lock(&kvm->slots_lock);
3680 goto create_pit_unlock;
3682 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3686 mutex_unlock(&kvm->slots_lock);
3688 case KVM_GET_IRQCHIP: {
3689 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3690 struct kvm_irqchip *chip;
3692 chip = memdup_user(argp, sizeof(*chip));
3699 if (!irqchip_in_kernel(kvm))
3700 goto get_irqchip_out;
3701 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3703 goto get_irqchip_out;
3705 if (copy_to_user(argp, chip, sizeof *chip))
3706 goto get_irqchip_out;
3712 case KVM_SET_IRQCHIP: {
3713 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3714 struct kvm_irqchip *chip;
3716 chip = memdup_user(argp, sizeof(*chip));
3723 if (!irqchip_in_kernel(kvm))
3724 goto set_irqchip_out;
3725 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3727 goto set_irqchip_out;
3735 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3738 if (!kvm->arch.vpit)
3740 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3744 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3751 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3754 if (!kvm->arch.vpit)
3756 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3759 case KVM_GET_PIT2: {
3761 if (!kvm->arch.vpit)
3763 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3767 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3772 case KVM_SET_PIT2: {
3774 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3777 if (!kvm->arch.vpit)
3779 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3782 case KVM_REINJECT_CONTROL: {
3783 struct kvm_reinject_control control;
3785 if (copy_from_user(&control, argp, sizeof(control)))
3787 r = kvm_vm_ioctl_reinject(kvm, &control);
3790 case KVM_XEN_HVM_CONFIG: {
3792 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3793 sizeof(struct kvm_xen_hvm_config)))
3796 if (kvm->arch.xen_hvm_config.flags)
3801 case KVM_SET_CLOCK: {
3802 struct kvm_clock_data user_ns;
3807 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3815 local_irq_disable();
3816 now_ns = get_kernel_ns();
3817 delta = user_ns.clock - now_ns;
3819 kvm->arch.kvmclock_offset = delta;
3822 case KVM_GET_CLOCK: {
3823 struct kvm_clock_data user_ns;
3826 local_irq_disable();
3827 now_ns = get_kernel_ns();
3828 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3831 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3834 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3847 static void kvm_init_msr_list(void)
3852 /* skip the first msrs in the list. KVM-specific */
3853 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3854 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3857 msrs_to_save[j] = msrs_to_save[i];
3860 num_msrs_to_save = j;
3863 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3871 if (!(vcpu->arch.apic &&
3872 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3873 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3884 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3891 if (!(vcpu->arch.apic &&
3892 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3893 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3895 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3905 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3906 struct kvm_segment *var, int seg)
3908 kvm_x86_ops->set_segment(vcpu, var, seg);
3911 void kvm_get_segment(struct kvm_vcpu *vcpu,
3912 struct kvm_segment *var, int seg)
3914 kvm_x86_ops->get_segment(vcpu, var, seg);
3917 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3920 struct x86_exception exception;
3922 BUG_ON(!mmu_is_nested(vcpu));
3924 /* NPT walks are always user-walks */
3925 access |= PFERR_USER_MASK;
3926 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3931 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3932 struct x86_exception *exception)
3934 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3935 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3938 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3939 struct x86_exception *exception)
3941 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3942 access |= PFERR_FETCH_MASK;
3943 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3946 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3947 struct x86_exception *exception)
3949 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3950 access |= PFERR_WRITE_MASK;
3951 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3954 /* uses this to access any guest's mapped memory without checking CPL */
3955 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3956 struct x86_exception *exception)
3958 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3961 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3962 struct kvm_vcpu *vcpu, u32 access,
3963 struct x86_exception *exception)
3966 int r = X86EMUL_CONTINUE;
3969 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3971 unsigned offset = addr & (PAGE_SIZE-1);
3972 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3975 if (gpa == UNMAPPED_GVA)
3976 return X86EMUL_PROPAGATE_FAULT;
3977 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3979 r = X86EMUL_IO_NEEDED;
3991 /* used for instruction fetching */
3992 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3993 gva_t addr, void *val, unsigned int bytes,
3994 struct x86_exception *exception)
3996 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3997 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3999 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4000 access | PFERR_FETCH_MASK,
4004 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4005 gva_t addr, void *val, unsigned int bytes,
4006 struct x86_exception *exception)
4008 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4009 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4011 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4014 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4016 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4017 gva_t addr, void *val, unsigned int bytes,
4018 struct x86_exception *exception)
4020 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4021 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4024 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4025 gva_t addr, void *val,
4027 struct x86_exception *exception)
4029 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4031 int r = X86EMUL_CONTINUE;
4034 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4037 unsigned offset = addr & (PAGE_SIZE-1);
4038 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4041 if (gpa == UNMAPPED_GVA)
4042 return X86EMUL_PROPAGATE_FAULT;
4043 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4045 r = X86EMUL_IO_NEEDED;
4056 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4058 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4059 gpa_t *gpa, struct x86_exception *exception,
4062 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4063 | (write ? PFERR_WRITE_MASK : 0);
4065 if (vcpu_match_mmio_gva(vcpu, gva)
4066 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4067 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4068 (gva & (PAGE_SIZE - 1));
4069 trace_vcpu_match_mmio(gva, *gpa, write, false);
4073 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4075 if (*gpa == UNMAPPED_GVA)
4078 /* For APIC access vmexit */
4079 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4082 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4083 trace_vcpu_match_mmio(gva, *gpa, write, true);
4090 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4091 const void *val, int bytes)
4095 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4098 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4102 struct read_write_emulator_ops {
4103 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4105 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4106 void *val, int bytes);
4107 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4108 int bytes, void *val);
4109 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4110 void *val, int bytes);
4114 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4116 if (vcpu->mmio_read_completed) {
4117 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4118 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4119 vcpu->mmio_read_completed = 0;
4126 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4127 void *val, int bytes)
4129 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4132 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4133 void *val, int bytes)
4135 return emulator_write_phys(vcpu, gpa, val, bytes);
4138 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4140 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4141 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4144 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4145 void *val, int bytes)
4147 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4148 return X86EMUL_IO_NEEDED;
4151 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4152 void *val, int bytes)
4154 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4156 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4157 return X86EMUL_CONTINUE;
4160 static const struct read_write_emulator_ops read_emultor = {
4161 .read_write_prepare = read_prepare,
4162 .read_write_emulate = read_emulate,
4163 .read_write_mmio = vcpu_mmio_read,
4164 .read_write_exit_mmio = read_exit_mmio,
4167 static const struct read_write_emulator_ops write_emultor = {
4168 .read_write_emulate = write_emulate,
4169 .read_write_mmio = write_mmio,
4170 .read_write_exit_mmio = write_exit_mmio,
4174 static int emulator_read_write_onepage(unsigned long addr, void *val,
4176 struct x86_exception *exception,
4177 struct kvm_vcpu *vcpu,
4178 const struct read_write_emulator_ops *ops)
4182 bool write = ops->write;
4183 struct kvm_mmio_fragment *frag;
4185 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4188 return X86EMUL_PROPAGATE_FAULT;
4190 /* For APIC access vmexit */
4194 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4195 return X86EMUL_CONTINUE;
4199 * Is this MMIO handled locally?
4201 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4202 if (handled == bytes)
4203 return X86EMUL_CONTINUE;
4209 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4210 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4214 return X86EMUL_CONTINUE;
4217 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4218 void *val, unsigned int bytes,
4219 struct x86_exception *exception,
4220 const struct read_write_emulator_ops *ops)
4222 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4226 if (ops->read_write_prepare &&
4227 ops->read_write_prepare(vcpu, val, bytes))
4228 return X86EMUL_CONTINUE;
4230 vcpu->mmio_nr_fragments = 0;
4232 /* Crossing a page boundary? */
4233 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4236 now = -addr & ~PAGE_MASK;
4237 rc = emulator_read_write_onepage(addr, val, now, exception,
4240 if (rc != X86EMUL_CONTINUE)
4247 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4249 if (rc != X86EMUL_CONTINUE)
4252 if (!vcpu->mmio_nr_fragments)
4255 gpa = vcpu->mmio_fragments[0].gpa;
4257 vcpu->mmio_needed = 1;
4258 vcpu->mmio_cur_fragment = 0;
4260 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4261 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4262 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4263 vcpu->run->mmio.phys_addr = gpa;
4265 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4268 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4272 struct x86_exception *exception)
4274 return emulator_read_write(ctxt, addr, val, bytes,
4275 exception, &read_emultor);
4278 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4282 struct x86_exception *exception)
4284 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4285 exception, &write_emultor);
4288 #define CMPXCHG_TYPE(t, ptr, old, new) \
4289 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4291 #ifdef CONFIG_X86_64
4292 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4294 # define CMPXCHG64(ptr, old, new) \
4295 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4298 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4303 struct x86_exception *exception)
4305 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4311 /* guests cmpxchg8b have to be emulated atomically */
4312 if (bytes > 8 || (bytes & (bytes - 1)))
4315 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4317 if (gpa == UNMAPPED_GVA ||
4318 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4321 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4324 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4325 if (is_error_page(page))
4328 kaddr = kmap_atomic(page);
4329 kaddr += offset_in_page(gpa);
4332 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4335 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4338 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4341 exchanged = CMPXCHG64(kaddr, old, new);
4346 kunmap_atomic(kaddr);
4347 kvm_release_page_dirty(page);
4350 return X86EMUL_CMPXCHG_FAILED;
4352 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4354 return X86EMUL_CONTINUE;
4357 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4359 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4362 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4364 /* TODO: String I/O for in kernel device */
4367 if (vcpu->arch.pio.in)
4368 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4369 vcpu->arch.pio.size, pd);
4371 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4372 vcpu->arch.pio.port, vcpu->arch.pio.size,
4377 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4378 unsigned short port, void *val,
4379 unsigned int count, bool in)
4381 trace_kvm_pio(!in, port, size, count);
4383 vcpu->arch.pio.port = port;
4384 vcpu->arch.pio.in = in;
4385 vcpu->arch.pio.count = count;
4386 vcpu->arch.pio.size = size;
4388 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4389 vcpu->arch.pio.count = 0;
4393 vcpu->run->exit_reason = KVM_EXIT_IO;
4394 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4395 vcpu->run->io.size = size;
4396 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4397 vcpu->run->io.count = count;
4398 vcpu->run->io.port = port;
4403 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4404 int size, unsigned short port, void *val,
4407 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4410 if (vcpu->arch.pio.count)
4413 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4416 memcpy(val, vcpu->arch.pio_data, size * count);
4417 vcpu->arch.pio.count = 0;
4424 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4425 int size, unsigned short port,
4426 const void *val, unsigned int count)
4428 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4430 memcpy(vcpu->arch.pio_data, val, size * count);
4431 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4434 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4436 return kvm_x86_ops->get_segment_base(vcpu, seg);
4439 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4441 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4444 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4446 if (!need_emulate_wbinvd(vcpu))
4447 return X86EMUL_CONTINUE;
4449 if (kvm_x86_ops->has_wbinvd_exit()) {
4450 int cpu = get_cpu();
4452 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4453 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4454 wbinvd_ipi, NULL, 1);
4456 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4459 return X86EMUL_CONTINUE;
4461 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4463 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4465 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4468 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4470 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4473 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4476 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4479 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4481 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4484 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4486 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4487 unsigned long value;
4491 value = kvm_read_cr0(vcpu);
4494 value = vcpu->arch.cr2;
4497 value = kvm_read_cr3(vcpu);
4500 value = kvm_read_cr4(vcpu);
4503 value = kvm_get_cr8(vcpu);
4506 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4513 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4515 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4520 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4523 vcpu->arch.cr2 = val;
4526 res = kvm_set_cr3(vcpu, val);
4529 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4532 res = kvm_set_cr8(vcpu, val);
4535 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4542 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4544 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4547 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4549 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4552 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4554 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4557 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4559 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4562 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4564 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4567 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4569 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4572 static unsigned long emulator_get_cached_segment_base(
4573 struct x86_emulate_ctxt *ctxt, int seg)
4575 return get_segment_base(emul_to_vcpu(ctxt), seg);
4578 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4579 struct desc_struct *desc, u32 *base3,
4582 struct kvm_segment var;
4584 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4585 *selector = var.selector;
4588 memset(desc, 0, sizeof(*desc));
4594 set_desc_limit(desc, var.limit);
4595 set_desc_base(desc, (unsigned long)var.base);
4596 #ifdef CONFIG_X86_64
4598 *base3 = var.base >> 32;
4600 desc->type = var.type;
4602 desc->dpl = var.dpl;
4603 desc->p = var.present;
4604 desc->avl = var.avl;
4612 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4613 struct desc_struct *desc, u32 base3,
4616 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4617 struct kvm_segment var;
4619 var.selector = selector;
4620 var.base = get_desc_base(desc);
4621 #ifdef CONFIG_X86_64
4622 var.base |= ((u64)base3) << 32;
4624 var.limit = get_desc_limit(desc);
4626 var.limit = (var.limit << 12) | 0xfff;
4627 var.type = desc->type;
4628 var.present = desc->p;
4629 var.dpl = desc->dpl;
4634 var.avl = desc->avl;
4635 var.present = desc->p;
4636 var.unusable = !var.present;
4639 kvm_set_segment(vcpu, &var, seg);
4643 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4644 u32 msr_index, u64 *pdata)
4646 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4649 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4650 u32 msr_index, u64 data)
4652 struct msr_data msr;
4655 msr.index = msr_index;
4656 msr.host_initiated = false;
4657 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4660 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4661 u32 pmc, u64 *pdata)
4663 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4666 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4668 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4671 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4674 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4676 * CR0.TS may reference the host fpu state, not the guest fpu state,
4677 * so it may be clear at this point.
4682 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4687 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4688 struct x86_instruction_info *info,
4689 enum x86_intercept_stage stage)
4691 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4694 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4695 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4697 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4700 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4702 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4705 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4707 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4710 static const struct x86_emulate_ops emulate_ops = {
4711 .read_gpr = emulator_read_gpr,
4712 .write_gpr = emulator_write_gpr,
4713 .read_std = kvm_read_guest_virt_system,
4714 .write_std = kvm_write_guest_virt_system,
4715 .fetch = kvm_fetch_guest_virt,
4716 .read_emulated = emulator_read_emulated,
4717 .write_emulated = emulator_write_emulated,
4718 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4719 .invlpg = emulator_invlpg,
4720 .pio_in_emulated = emulator_pio_in_emulated,
4721 .pio_out_emulated = emulator_pio_out_emulated,
4722 .get_segment = emulator_get_segment,
4723 .set_segment = emulator_set_segment,
4724 .get_cached_segment_base = emulator_get_cached_segment_base,
4725 .get_gdt = emulator_get_gdt,
4726 .get_idt = emulator_get_idt,
4727 .set_gdt = emulator_set_gdt,
4728 .set_idt = emulator_set_idt,
4729 .get_cr = emulator_get_cr,
4730 .set_cr = emulator_set_cr,
4731 .set_rflags = emulator_set_rflags,
4732 .cpl = emulator_get_cpl,
4733 .get_dr = emulator_get_dr,
4734 .set_dr = emulator_set_dr,
4735 .set_msr = emulator_set_msr,
4736 .get_msr = emulator_get_msr,
4737 .read_pmc = emulator_read_pmc,
4738 .halt = emulator_halt,
4739 .wbinvd = emulator_wbinvd,
4740 .fix_hypercall = emulator_fix_hypercall,
4741 .get_fpu = emulator_get_fpu,
4742 .put_fpu = emulator_put_fpu,
4743 .intercept = emulator_intercept,
4744 .get_cpuid = emulator_get_cpuid,
4747 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4749 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4751 * an sti; sti; sequence only disable interrupts for the first
4752 * instruction. So, if the last instruction, be it emulated or
4753 * not, left the system with the INT_STI flag enabled, it
4754 * means that the last instruction is an sti. We should not
4755 * leave the flag on in this case. The same goes for mov ss
4757 if (!(int_shadow & mask))
4758 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4761 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4763 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4764 if (ctxt->exception.vector == PF_VECTOR)
4765 kvm_propagate_fault(vcpu, &ctxt->exception);
4766 else if (ctxt->exception.error_code_valid)
4767 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4768 ctxt->exception.error_code);
4770 kvm_queue_exception(vcpu, ctxt->exception.vector);
4773 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4775 memset(&ctxt->twobyte, 0,
4776 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4778 ctxt->fetch.start = 0;
4779 ctxt->fetch.end = 0;
4780 ctxt->io_read.pos = 0;
4781 ctxt->io_read.end = 0;
4782 ctxt->mem_read.pos = 0;
4783 ctxt->mem_read.end = 0;
4786 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4788 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4791 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4793 ctxt->eflags = kvm_get_rflags(vcpu);
4794 ctxt->eip = kvm_rip_read(vcpu);
4795 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4796 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4797 cs_l ? X86EMUL_MODE_PROT64 :
4798 cs_db ? X86EMUL_MODE_PROT32 :
4799 X86EMUL_MODE_PROT16;
4800 ctxt->guest_mode = is_guest_mode(vcpu);
4802 init_decode_cache(ctxt);
4803 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4806 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4808 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4811 init_emulate_ctxt(vcpu);
4815 ctxt->_eip = ctxt->eip + inc_eip;
4816 ret = emulate_int_real(ctxt, irq);
4818 if (ret != X86EMUL_CONTINUE)
4819 return EMULATE_FAIL;
4821 ctxt->eip = ctxt->_eip;
4822 kvm_rip_write(vcpu, ctxt->eip);
4823 kvm_set_rflags(vcpu, ctxt->eflags);
4825 if (irq == NMI_VECTOR)
4826 vcpu->arch.nmi_pending = 0;
4828 vcpu->arch.interrupt.pending = false;
4830 return EMULATE_DONE;
4832 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4834 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4836 int r = EMULATE_DONE;
4838 ++vcpu->stat.insn_emulation_fail;
4839 trace_kvm_emulate_insn_failed(vcpu);
4840 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
4841 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4842 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4843 vcpu->run->internal.ndata = 0;
4846 kvm_queue_exception(vcpu, UD_VECTOR);
4851 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4852 bool write_fault_to_shadow_pgtable,
4858 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4861 if (!vcpu->arch.mmu.direct_map) {
4863 * Write permission should be allowed since only
4864 * write access need to be emulated.
4866 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4869 * If the mapping is invalid in guest, let cpu retry
4870 * it to generate fault.
4872 if (gpa == UNMAPPED_GVA)
4877 * Do not retry the unhandleable instruction if it faults on the
4878 * readonly host memory, otherwise it will goto a infinite loop:
4879 * retry instruction -> write #PF -> emulation fail -> retry
4880 * instruction -> ...
4882 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4885 * If the instruction failed on the error pfn, it can not be fixed,
4886 * report the error to userspace.
4888 if (is_error_noslot_pfn(pfn))
4891 kvm_release_pfn_clean(pfn);
4893 /* The instructions are well-emulated on direct mmu. */
4894 if (vcpu->arch.mmu.direct_map) {
4895 unsigned int indirect_shadow_pages;
4897 spin_lock(&vcpu->kvm->mmu_lock);
4898 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4899 spin_unlock(&vcpu->kvm->mmu_lock);
4901 if (indirect_shadow_pages)
4902 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4908 * if emulation was due to access to shadowed page table
4909 * and it failed try to unshadow page and re-enter the
4910 * guest to let CPU execute the instruction.
4912 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4915 * If the access faults on its page table, it can not
4916 * be fixed by unprotecting shadow page and it should
4917 * be reported to userspace.
4919 return !write_fault_to_shadow_pgtable;
4922 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4923 unsigned long cr2, int emulation_type)
4925 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4926 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4928 last_retry_eip = vcpu->arch.last_retry_eip;
4929 last_retry_addr = vcpu->arch.last_retry_addr;
4932 * If the emulation is caused by #PF and it is non-page_table
4933 * writing instruction, it means the VM-EXIT is caused by shadow
4934 * page protected, we can zap the shadow page and retry this
4935 * instruction directly.
4937 * Note: if the guest uses a non-page-table modifying instruction
4938 * on the PDE that points to the instruction, then we will unmap
4939 * the instruction and go to an infinite loop. So, we cache the
4940 * last retried eip and the last fault address, if we meet the eip
4941 * and the address again, we can break out of the potential infinite
4944 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4946 if (!(emulation_type & EMULTYPE_RETRY))
4949 if (x86_page_table_writing_insn(ctxt))
4952 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4955 vcpu->arch.last_retry_eip = ctxt->eip;
4956 vcpu->arch.last_retry_addr = cr2;
4958 if (!vcpu->arch.mmu.direct_map)
4959 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4961 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4966 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4967 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4969 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4976 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4977 bool writeback = true;
4978 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
4981 * Clear write_fault_to_shadow_pgtable here to ensure it is
4984 vcpu->arch.write_fault_to_shadow_pgtable = false;
4985 kvm_clear_exception_queue(vcpu);
4987 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4988 init_emulate_ctxt(vcpu);
4989 ctxt->interruptibility = 0;
4990 ctxt->have_exception = false;
4991 ctxt->perm_ok = false;
4993 ctxt->only_vendor_specific_insn
4994 = emulation_type & EMULTYPE_TRAP_UD;
4996 r = x86_decode_insn(ctxt, insn, insn_len);
4998 trace_kvm_emulate_insn_start(vcpu);
4999 ++vcpu->stat.insn_emulation;
5000 if (r != EMULATION_OK) {
5001 if (emulation_type & EMULTYPE_TRAP_UD)
5002 return EMULATE_FAIL;
5003 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5005 return EMULATE_DONE;
5006 if (emulation_type & EMULTYPE_SKIP)
5007 return EMULATE_FAIL;
5008 return handle_emulation_failure(vcpu);
5012 if (emulation_type & EMULTYPE_SKIP) {
5013 kvm_rip_write(vcpu, ctxt->_eip);
5014 return EMULATE_DONE;
5017 if (retry_instruction(ctxt, cr2, emulation_type))
5018 return EMULATE_DONE;
5020 /* this is needed for vmware backdoor interface to work since it
5021 changes registers values during IO operation */
5022 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5023 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5024 emulator_invalidate_register_cache(ctxt);
5028 r = x86_emulate_insn(ctxt);
5030 if (r == EMULATION_INTERCEPTED)
5031 return EMULATE_DONE;
5033 if (r == EMULATION_FAILED) {
5034 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5036 return EMULATE_DONE;
5038 return handle_emulation_failure(vcpu);
5041 if (ctxt->have_exception) {
5042 inject_emulated_exception(vcpu);
5044 } else if (vcpu->arch.pio.count) {
5045 if (!vcpu->arch.pio.in)
5046 vcpu->arch.pio.count = 0;
5049 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5051 r = EMULATE_DO_MMIO;
5052 } else if (vcpu->mmio_needed) {
5053 if (!vcpu->mmio_is_write)
5055 r = EMULATE_DO_MMIO;
5056 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5057 } else if (r == EMULATION_RESTART)
5063 toggle_interruptibility(vcpu, ctxt->interruptibility);
5064 kvm_set_rflags(vcpu, ctxt->eflags);
5065 kvm_make_request(KVM_REQ_EVENT, vcpu);
5066 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5067 kvm_rip_write(vcpu, ctxt->eip);
5069 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5073 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5075 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5077 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5078 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5079 size, port, &val, 1);
5080 /* do not return to emulator after return from userspace */
5081 vcpu->arch.pio.count = 0;
5084 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5086 static void tsc_bad(void *info)
5088 __this_cpu_write(cpu_tsc_khz, 0);
5091 static void tsc_khz_changed(void *data)
5093 struct cpufreq_freqs *freq = data;
5094 unsigned long khz = 0;
5098 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5099 khz = cpufreq_quick_get(raw_smp_processor_id());
5102 __this_cpu_write(cpu_tsc_khz, khz);
5105 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5108 struct cpufreq_freqs *freq = data;
5110 struct kvm_vcpu *vcpu;
5111 int i, send_ipi = 0;
5114 * We allow guests to temporarily run on slowing clocks,
5115 * provided we notify them after, or to run on accelerating
5116 * clocks, provided we notify them before. Thus time never
5119 * However, we have a problem. We can't atomically update
5120 * the frequency of a given CPU from this function; it is
5121 * merely a notifier, which can be called from any CPU.
5122 * Changing the TSC frequency at arbitrary points in time
5123 * requires a recomputation of local variables related to
5124 * the TSC for each VCPU. We must flag these local variables
5125 * to be updated and be sure the update takes place with the
5126 * new frequency before any guests proceed.
5128 * Unfortunately, the combination of hotplug CPU and frequency
5129 * change creates an intractable locking scenario; the order
5130 * of when these callouts happen is undefined with respect to
5131 * CPU hotplug, and they can race with each other. As such,
5132 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5133 * undefined; you can actually have a CPU frequency change take
5134 * place in between the computation of X and the setting of the
5135 * variable. To protect against this problem, all updates of
5136 * the per_cpu tsc_khz variable are done in an interrupt
5137 * protected IPI, and all callers wishing to update the value
5138 * must wait for a synchronous IPI to complete (which is trivial
5139 * if the caller is on the CPU already). This establishes the
5140 * necessary total order on variable updates.
5142 * Note that because a guest time update may take place
5143 * anytime after the setting of the VCPU's request bit, the
5144 * correct TSC value must be set before the request. However,
5145 * to ensure the update actually makes it to any guest which
5146 * starts running in hardware virtualization between the set
5147 * and the acquisition of the spinlock, we must also ping the
5148 * CPU after setting the request bit.
5152 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5154 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5157 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5159 spin_lock(&kvm_lock);
5160 list_for_each_entry(kvm, &vm_list, vm_list) {
5161 kvm_for_each_vcpu(i, vcpu, kvm) {
5162 if (vcpu->cpu != freq->cpu)
5164 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5165 if (vcpu->cpu != smp_processor_id())
5169 spin_unlock(&kvm_lock);
5171 if (freq->old < freq->new && send_ipi) {
5173 * We upscale the frequency. Must make the guest
5174 * doesn't see old kvmclock values while running with
5175 * the new frequency, otherwise we risk the guest sees
5176 * time go backwards.
5178 * In case we update the frequency for another cpu
5179 * (which might be in guest context) send an interrupt
5180 * to kick the cpu out of guest context. Next time
5181 * guest context is entered kvmclock will be updated,
5182 * so the guest will not see stale values.
5184 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5189 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5190 .notifier_call = kvmclock_cpufreq_notifier
5193 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5194 unsigned long action, void *hcpu)
5196 unsigned int cpu = (unsigned long)hcpu;
5200 case CPU_DOWN_FAILED:
5201 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5203 case CPU_DOWN_PREPARE:
5204 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5210 static struct notifier_block kvmclock_cpu_notifier_block = {
5211 .notifier_call = kvmclock_cpu_notifier,
5212 .priority = -INT_MAX
5215 static void kvm_timer_init(void)
5219 max_tsc_khz = tsc_khz;
5220 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5221 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5222 #ifdef CONFIG_CPU_FREQ
5223 struct cpufreq_policy policy;
5224 memset(&policy, 0, sizeof(policy));
5226 cpufreq_get_policy(&policy, cpu);
5227 if (policy.cpuinfo.max_freq)
5228 max_tsc_khz = policy.cpuinfo.max_freq;
5231 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5232 CPUFREQ_TRANSITION_NOTIFIER);
5234 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5235 for_each_online_cpu(cpu)
5236 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5239 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5241 int kvm_is_in_guest(void)
5243 return __this_cpu_read(current_vcpu) != NULL;
5246 static int kvm_is_user_mode(void)
5250 if (__this_cpu_read(current_vcpu))
5251 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5253 return user_mode != 0;
5256 static unsigned long kvm_get_guest_ip(void)
5258 unsigned long ip = 0;
5260 if (__this_cpu_read(current_vcpu))
5261 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5266 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5267 .is_in_guest = kvm_is_in_guest,
5268 .is_user_mode = kvm_is_user_mode,
5269 .get_guest_ip = kvm_get_guest_ip,
5272 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5274 __this_cpu_write(current_vcpu, vcpu);
5276 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5278 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5280 __this_cpu_write(current_vcpu, NULL);
5282 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5284 static void kvm_set_mmio_spte_mask(void)
5287 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5290 * Set the reserved bits and the present bit of an paging-structure
5291 * entry to generate page fault with PFER.RSV = 1.
5293 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5296 #ifdef CONFIG_X86_64
5298 * If reserved bit is not supported, clear the present bit to disable
5301 if (maxphyaddr == 52)
5305 kvm_mmu_set_mmio_spte_mask(mask);
5308 #ifdef CONFIG_X86_64
5309 static void pvclock_gtod_update_fn(struct work_struct *work)
5313 struct kvm_vcpu *vcpu;
5316 spin_lock(&kvm_lock);
5317 list_for_each_entry(kvm, &vm_list, vm_list)
5318 kvm_for_each_vcpu(i, vcpu, kvm)
5319 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5320 atomic_set(&kvm_guest_has_master_clock, 0);
5321 spin_unlock(&kvm_lock);
5324 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5327 * Notification about pvclock gtod data update.
5329 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5332 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5333 struct timekeeper *tk = priv;
5335 update_pvclock_gtod(tk);
5337 /* disable master clock if host does not trust, or does not
5338 * use, TSC clocksource
5340 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5341 atomic_read(&kvm_guest_has_master_clock) != 0)
5342 queue_work(system_long_wq, &pvclock_gtod_work);
5347 static struct notifier_block pvclock_gtod_notifier = {
5348 .notifier_call = pvclock_gtod_notify,
5352 int kvm_arch_init(void *opaque)
5355 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5358 printk(KERN_ERR "kvm: already loaded the other module\n");
5363 if (!ops->cpu_has_kvm_support()) {
5364 printk(KERN_ERR "kvm: no hardware support\n");
5368 if (ops->disabled_by_bios()) {
5369 printk(KERN_ERR "kvm: disabled by bios\n");
5375 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5377 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5381 r = kvm_mmu_module_init();
5383 goto out_free_percpu;
5385 kvm_set_mmio_spte_mask();
5386 kvm_init_msr_list();
5389 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5390 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5394 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5397 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5400 #ifdef CONFIG_X86_64
5401 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5407 free_percpu(shared_msrs);
5412 void kvm_arch_exit(void)
5414 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5416 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5417 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5418 CPUFREQ_TRANSITION_NOTIFIER);
5419 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5420 #ifdef CONFIG_X86_64
5421 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5424 kvm_mmu_module_exit();
5425 free_percpu(shared_msrs);
5428 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5430 ++vcpu->stat.halt_exits;
5431 if (irqchip_in_kernel(vcpu->kvm)) {
5432 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5435 vcpu->run->exit_reason = KVM_EXIT_HLT;
5439 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5441 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5443 u64 param, ingpa, outgpa, ret;
5444 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5445 bool fast, longmode;
5449 * hypercall generates UD from non zero cpl and real mode
5452 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5453 kvm_queue_exception(vcpu, UD_VECTOR);
5457 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5458 longmode = is_long_mode(vcpu) && cs_l == 1;
5461 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5462 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5463 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5464 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5465 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5466 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5468 #ifdef CONFIG_X86_64
5470 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5471 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5472 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5476 code = param & 0xffff;
5477 fast = (param >> 16) & 0x1;
5478 rep_cnt = (param >> 32) & 0xfff;
5479 rep_idx = (param >> 48) & 0xfff;
5481 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5484 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5485 kvm_vcpu_on_spin(vcpu);
5488 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5492 ret = res | (((u64)rep_done & 0xfff) << 32);
5494 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5496 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5497 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5503 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5505 unsigned long nr, a0, a1, a2, a3, ret;
5508 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5509 return kvm_hv_hypercall(vcpu);
5511 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5512 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5513 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5514 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5515 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5517 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5519 if (!is_long_mode(vcpu)) {
5527 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5533 case KVM_HC_VAPIC_POLL_IRQ:
5541 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5542 ++vcpu->stat.hypercalls;
5545 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5547 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5549 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5550 char instruction[3];
5551 unsigned long rip = kvm_rip_read(vcpu);
5554 * Blow out the MMU to ensure that no other VCPU has an active mapping
5555 * to ensure that the updated hypercall appears atomically across all
5558 kvm_mmu_zap_all(vcpu->kvm);
5560 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5562 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5566 * Check if userspace requested an interrupt window, and that the
5567 * interrupt window is open.
5569 * No need to exit to userspace if we already have an interrupt queued.
5571 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5573 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5574 vcpu->run->request_interrupt_window &&
5575 kvm_arch_interrupt_allowed(vcpu));
5578 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5580 struct kvm_run *kvm_run = vcpu->run;
5582 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5583 kvm_run->cr8 = kvm_get_cr8(vcpu);
5584 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5585 if (irqchip_in_kernel(vcpu->kvm))
5586 kvm_run->ready_for_interrupt_injection = 1;
5588 kvm_run->ready_for_interrupt_injection =
5589 kvm_arch_interrupt_allowed(vcpu) &&
5590 !kvm_cpu_has_interrupt(vcpu) &&
5591 !kvm_event_needs_reinjection(vcpu);
5594 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5598 if (!kvm_x86_ops->update_cr8_intercept)
5601 if (!vcpu->arch.apic)
5604 if (!vcpu->arch.apic->vapic_addr)
5605 max_irr = kvm_lapic_find_highest_irr(vcpu);
5612 tpr = kvm_lapic_get_cr8(vcpu);
5614 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5617 static void inject_pending_event(struct kvm_vcpu *vcpu)
5619 /* try to reinject previous events if any */
5620 if (vcpu->arch.exception.pending) {
5621 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5622 vcpu->arch.exception.has_error_code,
5623 vcpu->arch.exception.error_code);
5624 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5625 vcpu->arch.exception.has_error_code,
5626 vcpu->arch.exception.error_code,
5627 vcpu->arch.exception.reinject);
5631 if (vcpu->arch.nmi_injected) {
5632 kvm_x86_ops->set_nmi(vcpu);
5636 if (vcpu->arch.interrupt.pending) {
5637 kvm_x86_ops->set_irq(vcpu);
5641 /* try to inject new event if pending */
5642 if (vcpu->arch.nmi_pending) {
5643 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5644 --vcpu->arch.nmi_pending;
5645 vcpu->arch.nmi_injected = true;
5646 kvm_x86_ops->set_nmi(vcpu);
5648 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5649 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5650 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5652 kvm_x86_ops->set_irq(vcpu);
5657 static void process_nmi(struct kvm_vcpu *vcpu)
5662 * x86 is limited to one NMI running, and one NMI pending after it.
5663 * If an NMI is already in progress, limit further NMIs to just one.
5664 * Otherwise, allow two (and we'll inject the first one immediately).
5666 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5669 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5670 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5671 kvm_make_request(KVM_REQ_EVENT, vcpu);
5674 static void kvm_gen_update_masterclock(struct kvm *kvm)
5676 #ifdef CONFIG_X86_64
5678 struct kvm_vcpu *vcpu;
5679 struct kvm_arch *ka = &kvm->arch;
5681 spin_lock(&ka->pvclock_gtod_sync_lock);
5682 kvm_make_mclock_inprogress_request(kvm);
5683 /* no guest entries from this point */
5684 pvclock_update_vm_gtod_copy(kvm);
5686 kvm_for_each_vcpu(i, vcpu, kvm)
5687 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5689 /* guest entries allowed */
5690 kvm_for_each_vcpu(i, vcpu, kvm)
5691 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5693 spin_unlock(&ka->pvclock_gtod_sync_lock);
5697 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5699 u64 eoi_exit_bitmap[4];
5702 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5705 memset(eoi_exit_bitmap, 0, 32);
5708 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5709 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5710 kvm_apic_update_tmr(vcpu, tmr);
5713 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5716 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5717 vcpu->run->request_interrupt_window;
5718 bool req_immediate_exit = false;
5720 if (vcpu->requests) {
5721 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5722 kvm_mmu_unload(vcpu);
5723 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5724 __kvm_migrate_timers(vcpu);
5725 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5726 kvm_gen_update_masterclock(vcpu->kvm);
5727 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5728 r = kvm_guest_time_update(vcpu);
5732 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5733 kvm_mmu_sync_roots(vcpu);
5734 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5735 kvm_x86_ops->tlb_flush(vcpu);
5736 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5737 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5741 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5742 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5746 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5747 vcpu->fpu_active = 0;
5748 kvm_x86_ops->fpu_deactivate(vcpu);
5750 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5751 /* Page is swapped out. Do synthetic halt */
5752 vcpu->arch.apf.halted = true;
5756 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5757 record_steal_time(vcpu);
5758 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5760 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5761 kvm_handle_pmu_event(vcpu);
5762 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5763 kvm_deliver_pmi(vcpu);
5764 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5765 vcpu_scan_ioapic(vcpu);
5768 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5769 kvm_apic_accept_events(vcpu);
5770 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5775 inject_pending_event(vcpu);
5777 /* enable NMI/IRQ window open exits if needed */
5778 if (vcpu->arch.nmi_pending)
5779 req_immediate_exit =
5780 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5781 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5782 req_immediate_exit =
5783 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5785 if (kvm_lapic_enabled(vcpu)) {
5787 * Update architecture specific hints for APIC
5788 * virtual interrupt delivery.
5790 if (kvm_x86_ops->hwapic_irr_update)
5791 kvm_x86_ops->hwapic_irr_update(vcpu,
5792 kvm_lapic_find_highest_irr(vcpu));
5793 update_cr8_intercept(vcpu);
5794 kvm_lapic_sync_to_vapic(vcpu);
5798 r = kvm_mmu_reload(vcpu);
5800 goto cancel_injection;
5805 kvm_x86_ops->prepare_guest_switch(vcpu);
5806 if (vcpu->fpu_active)
5807 kvm_load_guest_fpu(vcpu);
5808 kvm_load_guest_xcr0(vcpu);
5810 vcpu->mode = IN_GUEST_MODE;
5812 /* We should set ->mode before check ->requests,
5813 * see the comment in make_all_cpus_request.
5817 local_irq_disable();
5819 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5820 || need_resched() || signal_pending(current)) {
5821 vcpu->mode = OUTSIDE_GUEST_MODE;
5826 goto cancel_injection;
5829 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5831 if (req_immediate_exit)
5832 smp_send_reschedule(vcpu->cpu);
5836 if (unlikely(vcpu->arch.switch_db_regs)) {
5838 set_debugreg(vcpu->arch.eff_db[0], 0);
5839 set_debugreg(vcpu->arch.eff_db[1], 1);
5840 set_debugreg(vcpu->arch.eff_db[2], 2);
5841 set_debugreg(vcpu->arch.eff_db[3], 3);
5844 trace_kvm_entry(vcpu->vcpu_id);
5845 kvm_x86_ops->run(vcpu);
5848 * If the guest has used debug registers, at least dr7
5849 * will be disabled while returning to the host.
5850 * If we don't have active breakpoints in the host, we don't
5851 * care about the messed up debug address registers. But if
5852 * we have some of them active, restore the old state.
5854 if (hw_breakpoint_active())
5855 hw_breakpoint_restore();
5857 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5860 vcpu->mode = OUTSIDE_GUEST_MODE;
5863 /* Interrupt is enabled by handle_external_intr() */
5864 kvm_x86_ops->handle_external_intr(vcpu);
5869 * We must have an instruction between local_irq_enable() and
5870 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5871 * the interrupt shadow. The stat.exits increment will do nicely.
5872 * But we need to prevent reordering, hence this barrier():
5880 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5883 * Profile KVM exit RIPs:
5885 if (unlikely(prof_on == KVM_PROFILING)) {
5886 unsigned long rip = kvm_rip_read(vcpu);
5887 profile_hit(KVM_PROFILING, (void *)rip);
5890 if (unlikely(vcpu->arch.tsc_always_catchup))
5891 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5893 if (vcpu->arch.apic_attention)
5894 kvm_lapic_sync_from_vapic(vcpu);
5896 r = kvm_x86_ops->handle_exit(vcpu);
5900 kvm_x86_ops->cancel_injection(vcpu);
5901 if (unlikely(vcpu->arch.apic_attention))
5902 kvm_lapic_sync_from_vapic(vcpu);
5908 static int __vcpu_run(struct kvm_vcpu *vcpu)
5911 struct kvm *kvm = vcpu->kvm;
5913 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5917 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5918 !vcpu->arch.apf.halted)
5919 r = vcpu_enter_guest(vcpu);
5921 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5922 kvm_vcpu_block(vcpu);
5923 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5924 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5925 kvm_apic_accept_events(vcpu);
5926 switch(vcpu->arch.mp_state) {
5927 case KVM_MP_STATE_HALTED:
5928 vcpu->arch.mp_state =
5929 KVM_MP_STATE_RUNNABLE;
5930 case KVM_MP_STATE_RUNNABLE:
5931 vcpu->arch.apf.halted = false;
5933 case KVM_MP_STATE_INIT_RECEIVED:
5945 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5946 if (kvm_cpu_has_pending_timer(vcpu))
5947 kvm_inject_pending_timer_irqs(vcpu);
5949 if (dm_request_for_irq_injection(vcpu)) {
5951 vcpu->run->exit_reason = KVM_EXIT_INTR;
5952 ++vcpu->stat.request_irq_exits;
5955 kvm_check_async_pf_completion(vcpu);
5957 if (signal_pending(current)) {
5959 vcpu->run->exit_reason = KVM_EXIT_INTR;
5960 ++vcpu->stat.signal_exits;
5962 if (need_resched()) {
5963 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5965 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5969 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5974 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5977 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5978 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5979 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5980 if (r != EMULATE_DONE)
5985 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5987 BUG_ON(!vcpu->arch.pio.count);
5989 return complete_emulated_io(vcpu);
5993 * Implements the following, as a state machine:
5997 * for each mmio piece in the fragment
6005 * for each mmio piece in the fragment
6010 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6012 struct kvm_run *run = vcpu->run;
6013 struct kvm_mmio_fragment *frag;
6016 BUG_ON(!vcpu->mmio_needed);
6018 /* Complete previous fragment */
6019 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6020 len = min(8u, frag->len);
6021 if (!vcpu->mmio_is_write)
6022 memcpy(frag->data, run->mmio.data, len);
6024 if (frag->len <= 8) {
6025 /* Switch to the next fragment. */
6027 vcpu->mmio_cur_fragment++;
6029 /* Go forward to the next mmio piece. */
6035 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6036 vcpu->mmio_needed = 0;
6037 if (vcpu->mmio_is_write)
6039 vcpu->mmio_read_completed = 1;
6040 return complete_emulated_io(vcpu);
6043 run->exit_reason = KVM_EXIT_MMIO;
6044 run->mmio.phys_addr = frag->gpa;
6045 if (vcpu->mmio_is_write)
6046 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6047 run->mmio.len = min(8u, frag->len);
6048 run->mmio.is_write = vcpu->mmio_is_write;
6049 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6054 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6059 if (!tsk_used_math(current) && init_fpu(current))
6062 if (vcpu->sigset_active)
6063 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6065 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6066 kvm_vcpu_block(vcpu);
6067 kvm_apic_accept_events(vcpu);
6068 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6073 /* re-sync apic's tpr */
6074 if (!irqchip_in_kernel(vcpu->kvm)) {
6075 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6081 if (unlikely(vcpu->arch.complete_userspace_io)) {
6082 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6083 vcpu->arch.complete_userspace_io = NULL;
6088 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6090 r = __vcpu_run(vcpu);
6093 post_kvm_run_save(vcpu);
6094 if (vcpu->sigset_active)
6095 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6100 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6102 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6104 * We are here if userspace calls get_regs() in the middle of
6105 * instruction emulation. Registers state needs to be copied
6106 * back from emulation context to vcpu. Userspace shouldn't do
6107 * that usually, but some bad designed PV devices (vmware
6108 * backdoor interface) need this to work
6110 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6111 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6113 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6114 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6115 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6116 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6117 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6118 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6119 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6120 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6121 #ifdef CONFIG_X86_64
6122 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6123 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6124 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6125 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6126 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6127 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6128 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6129 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6132 regs->rip = kvm_rip_read(vcpu);
6133 regs->rflags = kvm_get_rflags(vcpu);
6138 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6140 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6141 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6143 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6144 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6145 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6146 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6147 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6148 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6149 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6150 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6151 #ifdef CONFIG_X86_64
6152 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6153 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6154 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6155 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6156 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6157 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6158 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6159 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6162 kvm_rip_write(vcpu, regs->rip);
6163 kvm_set_rflags(vcpu, regs->rflags);
6165 vcpu->arch.exception.pending = false;
6167 kvm_make_request(KVM_REQ_EVENT, vcpu);
6172 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6174 struct kvm_segment cs;
6176 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6180 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6182 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6183 struct kvm_sregs *sregs)
6187 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6188 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6189 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6190 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6191 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6192 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6194 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6195 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6197 kvm_x86_ops->get_idt(vcpu, &dt);
6198 sregs->idt.limit = dt.size;
6199 sregs->idt.base = dt.address;
6200 kvm_x86_ops->get_gdt(vcpu, &dt);
6201 sregs->gdt.limit = dt.size;
6202 sregs->gdt.base = dt.address;
6204 sregs->cr0 = kvm_read_cr0(vcpu);
6205 sregs->cr2 = vcpu->arch.cr2;
6206 sregs->cr3 = kvm_read_cr3(vcpu);
6207 sregs->cr4 = kvm_read_cr4(vcpu);
6208 sregs->cr8 = kvm_get_cr8(vcpu);
6209 sregs->efer = vcpu->arch.efer;
6210 sregs->apic_base = kvm_get_apic_base(vcpu);
6212 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6214 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6215 set_bit(vcpu->arch.interrupt.nr,
6216 (unsigned long *)sregs->interrupt_bitmap);
6221 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6222 struct kvm_mp_state *mp_state)
6224 kvm_apic_accept_events(vcpu);
6225 mp_state->mp_state = vcpu->arch.mp_state;
6229 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6230 struct kvm_mp_state *mp_state)
6232 if (!kvm_vcpu_has_lapic(vcpu) &&
6233 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6236 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6237 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6238 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6240 vcpu->arch.mp_state = mp_state->mp_state;
6241 kvm_make_request(KVM_REQ_EVENT, vcpu);
6245 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6246 int reason, bool has_error_code, u32 error_code)
6248 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6251 init_emulate_ctxt(vcpu);
6253 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6254 has_error_code, error_code);
6257 return EMULATE_FAIL;
6259 kvm_rip_write(vcpu, ctxt->eip);
6260 kvm_set_rflags(vcpu, ctxt->eflags);
6261 kvm_make_request(KVM_REQ_EVENT, vcpu);
6262 return EMULATE_DONE;
6264 EXPORT_SYMBOL_GPL(kvm_task_switch);
6266 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6267 struct kvm_sregs *sregs)
6269 int mmu_reset_needed = 0;
6270 int pending_vec, max_bits, idx;
6273 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6276 dt.size = sregs->idt.limit;
6277 dt.address = sregs->idt.base;
6278 kvm_x86_ops->set_idt(vcpu, &dt);
6279 dt.size = sregs->gdt.limit;
6280 dt.address = sregs->gdt.base;
6281 kvm_x86_ops->set_gdt(vcpu, &dt);
6283 vcpu->arch.cr2 = sregs->cr2;
6284 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6285 vcpu->arch.cr3 = sregs->cr3;
6286 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6288 kvm_set_cr8(vcpu, sregs->cr8);
6290 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6291 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6292 kvm_set_apic_base(vcpu, sregs->apic_base);
6294 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6295 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6296 vcpu->arch.cr0 = sregs->cr0;
6298 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6299 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6300 if (sregs->cr4 & X86_CR4_OSXSAVE)
6301 kvm_update_cpuid(vcpu);
6303 idx = srcu_read_lock(&vcpu->kvm->srcu);
6304 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6305 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6306 mmu_reset_needed = 1;
6308 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6310 if (mmu_reset_needed)
6311 kvm_mmu_reset_context(vcpu);
6313 max_bits = KVM_NR_INTERRUPTS;
6314 pending_vec = find_first_bit(
6315 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6316 if (pending_vec < max_bits) {
6317 kvm_queue_interrupt(vcpu, pending_vec, false);
6318 pr_debug("Set back pending irq %d\n", pending_vec);
6321 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6322 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6323 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6324 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6325 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6326 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6328 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6329 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6331 update_cr8_intercept(vcpu);
6333 /* Older userspace won't unhalt the vcpu on reset. */
6334 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6335 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6337 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6339 kvm_make_request(KVM_REQ_EVENT, vcpu);
6344 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6345 struct kvm_guest_debug *dbg)
6347 unsigned long rflags;
6350 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6352 if (vcpu->arch.exception.pending)
6354 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6355 kvm_queue_exception(vcpu, DB_VECTOR);
6357 kvm_queue_exception(vcpu, BP_VECTOR);
6361 * Read rflags as long as potentially injected trace flags are still
6364 rflags = kvm_get_rflags(vcpu);
6366 vcpu->guest_debug = dbg->control;
6367 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6368 vcpu->guest_debug = 0;
6370 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6371 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6372 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6373 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6375 for (i = 0; i < KVM_NR_DB_REGS; i++)
6376 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6378 kvm_update_dr7(vcpu);
6380 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6381 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6382 get_segment_base(vcpu, VCPU_SREG_CS);
6385 * Trigger an rflags update that will inject or remove the trace
6388 kvm_set_rflags(vcpu, rflags);
6390 kvm_x86_ops->update_db_bp_intercept(vcpu);
6400 * Translate a guest virtual address to a guest physical address.
6402 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6403 struct kvm_translation *tr)
6405 unsigned long vaddr = tr->linear_address;
6409 idx = srcu_read_lock(&vcpu->kvm->srcu);
6410 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6411 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6412 tr->physical_address = gpa;
6413 tr->valid = gpa != UNMAPPED_GVA;
6420 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6422 struct i387_fxsave_struct *fxsave =
6423 &vcpu->arch.guest_fpu.state->fxsave;
6425 memcpy(fpu->fpr, fxsave->st_space, 128);
6426 fpu->fcw = fxsave->cwd;
6427 fpu->fsw = fxsave->swd;
6428 fpu->ftwx = fxsave->twd;
6429 fpu->last_opcode = fxsave->fop;
6430 fpu->last_ip = fxsave->rip;
6431 fpu->last_dp = fxsave->rdp;
6432 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6437 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6439 struct i387_fxsave_struct *fxsave =
6440 &vcpu->arch.guest_fpu.state->fxsave;
6442 memcpy(fxsave->st_space, fpu->fpr, 128);
6443 fxsave->cwd = fpu->fcw;
6444 fxsave->swd = fpu->fsw;
6445 fxsave->twd = fpu->ftwx;
6446 fxsave->fop = fpu->last_opcode;
6447 fxsave->rip = fpu->last_ip;
6448 fxsave->rdp = fpu->last_dp;
6449 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6454 int fx_init(struct kvm_vcpu *vcpu)
6458 err = fpu_alloc(&vcpu->arch.guest_fpu);
6462 fpu_finit(&vcpu->arch.guest_fpu);
6465 * Ensure guest xcr0 is valid for loading
6467 vcpu->arch.xcr0 = XSTATE_FP;
6469 vcpu->arch.cr0 |= X86_CR0_ET;
6473 EXPORT_SYMBOL_GPL(fx_init);
6475 static void fx_free(struct kvm_vcpu *vcpu)
6477 fpu_free(&vcpu->arch.guest_fpu);
6480 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6482 if (vcpu->guest_fpu_loaded)
6486 * Restore all possible states in the guest,
6487 * and assume host would use all available bits.
6488 * Guest xcr0 would be loaded later.
6490 kvm_put_guest_xcr0(vcpu);
6491 vcpu->guest_fpu_loaded = 1;
6492 __kernel_fpu_begin();
6493 fpu_restore_checking(&vcpu->arch.guest_fpu);
6497 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6499 kvm_put_guest_xcr0(vcpu);
6501 if (!vcpu->guest_fpu_loaded)
6504 vcpu->guest_fpu_loaded = 0;
6505 fpu_save_init(&vcpu->arch.guest_fpu);
6507 ++vcpu->stat.fpu_reload;
6508 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6512 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6514 kvmclock_reset(vcpu);
6516 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6518 kvm_x86_ops->vcpu_free(vcpu);
6521 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6524 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6525 printk_once(KERN_WARNING
6526 "kvm: SMP vm created on host with unstable TSC; "
6527 "guest TSC will not be reliable\n");
6528 return kvm_x86_ops->vcpu_create(kvm, id);
6531 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6535 vcpu->arch.mtrr_state.have_fixed = 1;
6536 r = vcpu_load(vcpu);
6539 kvm_vcpu_reset(vcpu);
6540 r = kvm_mmu_setup(vcpu);
6546 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6549 struct msr_data msr;
6551 r = vcpu_load(vcpu);
6555 msr.index = MSR_IA32_TSC;
6556 msr.host_initiated = true;
6557 kvm_write_tsc(vcpu, &msr);
6563 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6566 vcpu->arch.apf.msr_val = 0;
6568 r = vcpu_load(vcpu);
6570 kvm_mmu_unload(vcpu);
6574 kvm_x86_ops->vcpu_free(vcpu);
6577 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6579 atomic_set(&vcpu->arch.nmi_queued, 0);
6580 vcpu->arch.nmi_pending = 0;
6581 vcpu->arch.nmi_injected = false;
6583 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6584 vcpu->arch.dr6 = DR6_FIXED_1;
6585 vcpu->arch.dr7 = DR7_FIXED_1;
6586 kvm_update_dr7(vcpu);
6588 kvm_make_request(KVM_REQ_EVENT, vcpu);
6589 vcpu->arch.apf.msr_val = 0;
6590 vcpu->arch.st.msr_val = 0;
6592 kvmclock_reset(vcpu);
6594 kvm_clear_async_pf_completion_queue(vcpu);
6595 kvm_async_pf_hash_reset(vcpu);
6596 vcpu->arch.apf.halted = false;
6598 kvm_pmu_reset(vcpu);
6600 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6601 vcpu->arch.regs_avail = ~0;
6602 vcpu->arch.regs_dirty = ~0;
6604 kvm_x86_ops->vcpu_reset(vcpu);
6607 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6609 struct kvm_segment cs;
6611 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6612 cs.selector = vector << 8;
6613 cs.base = vector << 12;
6614 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6615 kvm_rip_write(vcpu, 0);
6618 int kvm_arch_hardware_enable(void)
6621 struct kvm_vcpu *vcpu;
6626 bool stable, backwards_tsc = false;
6628 kvm_shared_msr_cpu_online();
6629 ret = kvm_x86_ops->hardware_enable();
6633 local_tsc = native_read_tsc();
6634 stable = !check_tsc_unstable();
6635 list_for_each_entry(kvm, &vm_list, vm_list) {
6636 kvm_for_each_vcpu(i, vcpu, kvm) {
6637 if (!stable && vcpu->cpu == smp_processor_id())
6638 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6639 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6640 backwards_tsc = true;
6641 if (vcpu->arch.last_host_tsc > max_tsc)
6642 max_tsc = vcpu->arch.last_host_tsc;
6648 * Sometimes, even reliable TSCs go backwards. This happens on
6649 * platforms that reset TSC during suspend or hibernate actions, but
6650 * maintain synchronization. We must compensate. Fortunately, we can
6651 * detect that condition here, which happens early in CPU bringup,
6652 * before any KVM threads can be running. Unfortunately, we can't
6653 * bring the TSCs fully up to date with real time, as we aren't yet far
6654 * enough into CPU bringup that we know how much real time has actually
6655 * elapsed; our helper function, get_kernel_ns() will be using boot
6656 * variables that haven't been updated yet.
6658 * So we simply find the maximum observed TSC above, then record the
6659 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6660 * the adjustment will be applied. Note that we accumulate
6661 * adjustments, in case multiple suspend cycles happen before some VCPU
6662 * gets a chance to run again. In the event that no KVM threads get a
6663 * chance to run, we will miss the entire elapsed period, as we'll have
6664 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6665 * loose cycle time. This isn't too big a deal, since the loss will be
6666 * uniform across all VCPUs (not to mention the scenario is extremely
6667 * unlikely). It is possible that a second hibernate recovery happens
6668 * much faster than a first, causing the observed TSC here to be
6669 * smaller; this would require additional padding adjustment, which is
6670 * why we set last_host_tsc to the local tsc observed here.
6672 * N.B. - this code below runs only on platforms with reliable TSC,
6673 * as that is the only way backwards_tsc is set above. Also note
6674 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6675 * have the same delta_cyc adjustment applied if backwards_tsc
6676 * is detected. Note further, this adjustment is only done once,
6677 * as we reset last_host_tsc on all VCPUs to stop this from being
6678 * called multiple times (one for each physical CPU bringup).
6680 * Platforms with unreliable TSCs don't have to deal with this, they
6681 * will be compensated by the logic in vcpu_load, which sets the TSC to
6682 * catchup mode. This will catchup all VCPUs to real time, but cannot
6683 * guarantee that they stay in perfect synchronization.
6685 if (backwards_tsc) {
6686 u64 delta_cyc = max_tsc - local_tsc;
6687 list_for_each_entry(kvm, &vm_list, vm_list) {
6688 kvm_for_each_vcpu(i, vcpu, kvm) {
6689 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6690 vcpu->arch.last_host_tsc = local_tsc;
6691 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6696 * We have to disable TSC offset matching.. if you were
6697 * booting a VM while issuing an S4 host suspend....
6698 * you may have some problem. Solving this issue is
6699 * left as an exercise to the reader.
6701 kvm->arch.last_tsc_nsec = 0;
6702 kvm->arch.last_tsc_write = 0;
6709 void kvm_arch_hardware_disable(void)
6711 kvm_x86_ops->hardware_disable();
6712 drop_user_return_notifiers();
6715 int kvm_arch_hardware_setup(void)
6717 return kvm_x86_ops->hardware_setup();
6720 void kvm_arch_hardware_unsetup(void)
6722 kvm_x86_ops->hardware_unsetup();
6725 void kvm_arch_check_processor_compat(void *rtn)
6727 kvm_x86_ops->check_processor_compatibility(rtn);
6730 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6732 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6735 struct static_key kvm_no_apic_vcpu __read_mostly;
6737 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6743 BUG_ON(vcpu->kvm == NULL);
6746 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6747 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6748 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6750 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6752 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6757 vcpu->arch.pio_data = page_address(page);
6759 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6761 r = kvm_mmu_create(vcpu);
6763 goto fail_free_pio_data;
6765 if (irqchip_in_kernel(kvm)) {
6766 r = kvm_create_lapic(vcpu);
6768 goto fail_mmu_destroy;
6770 static_key_slow_inc(&kvm_no_apic_vcpu);
6772 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6774 if (!vcpu->arch.mce_banks) {
6776 goto fail_free_lapic;
6778 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6780 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6782 goto fail_free_mce_banks;
6787 goto fail_free_wbinvd_dirty_mask;
6789 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6790 vcpu->arch.pv_time_enabled = false;
6791 kvm_async_pf_hash_reset(vcpu);
6795 fail_free_wbinvd_dirty_mask:
6796 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6797 fail_free_mce_banks:
6798 kfree(vcpu->arch.mce_banks);
6800 kvm_free_lapic(vcpu);
6802 kvm_mmu_destroy(vcpu);
6804 free_page((unsigned long)vcpu->arch.pio_data);
6809 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6813 kvm_pmu_destroy(vcpu);
6814 kfree(vcpu->arch.mce_banks);
6815 kvm_free_lapic(vcpu);
6816 idx = srcu_read_lock(&vcpu->kvm->srcu);
6817 kvm_mmu_destroy(vcpu);
6818 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6819 free_page((unsigned long)vcpu->arch.pio_data);
6820 if (!irqchip_in_kernel(vcpu->kvm))
6821 static_key_slow_dec(&kvm_no_apic_vcpu);
6824 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
6828 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6833 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6834 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6836 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6837 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6838 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6839 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6840 &kvm->arch.irq_sources_bitmap);
6842 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6843 mutex_init(&kvm->arch.apic_map_lock);
6844 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6846 pvclock_update_vm_gtod_copy(kvm);
6851 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6854 r = vcpu_load(vcpu);
6856 kvm_mmu_unload(vcpu);
6860 static void kvm_free_vcpus(struct kvm *kvm)
6863 struct kvm_vcpu *vcpu;
6866 * Unpin any mmu pages first.
6868 kvm_for_each_vcpu(i, vcpu, kvm) {
6869 kvm_clear_async_pf_completion_queue(vcpu);
6870 kvm_unload_vcpu_mmu(vcpu);
6872 kvm_for_each_vcpu(i, vcpu, kvm)
6873 kvm_arch_vcpu_free(vcpu);
6875 mutex_lock(&kvm->lock);
6876 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6877 kvm->vcpus[i] = NULL;
6879 atomic_set(&kvm->online_vcpus, 0);
6880 mutex_unlock(&kvm->lock);
6883 void kvm_arch_sync_events(struct kvm *kvm)
6885 kvm_free_all_assigned_devices(kvm);
6889 void kvm_arch_destroy_vm(struct kvm *kvm)
6891 if (current->mm == kvm->mm) {
6893 * Free memory regions allocated on behalf of userspace,
6894 * unless the the memory map has changed due to process exit
6897 struct kvm_userspace_memory_region mem;
6898 memset(&mem, 0, sizeof(mem));
6899 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
6900 kvm_set_memory_region(kvm, &mem);
6902 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
6903 kvm_set_memory_region(kvm, &mem);
6905 mem.slot = TSS_PRIVATE_MEMSLOT;
6906 kvm_set_memory_region(kvm, &mem);
6908 kvm_iommu_unmap_guest(kvm);
6909 kfree(kvm->arch.vpic);
6910 kfree(kvm->arch.vioapic);
6911 kvm_free_vcpus(kvm);
6912 if (kvm->arch.apic_access_page)
6913 put_page(kvm->arch.apic_access_page);
6914 if (kvm->arch.ept_identity_pagetable)
6915 put_page(kvm->arch.ept_identity_pagetable);
6916 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
6919 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
6920 struct kvm_memory_slot *dont)
6924 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6925 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6926 kvm_kvfree(free->arch.rmap[i]);
6927 free->arch.rmap[i] = NULL;
6932 if (!dont || free->arch.lpage_info[i - 1] !=
6933 dont->arch.lpage_info[i - 1]) {
6934 kvm_kvfree(free->arch.lpage_info[i - 1]);
6935 free->arch.lpage_info[i - 1] = NULL;
6940 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
6941 unsigned long npages)
6945 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6950 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6951 slot->base_gfn, level) + 1;
6953 slot->arch.rmap[i] =
6954 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6955 if (!slot->arch.rmap[i])
6960 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6961 sizeof(*slot->arch.lpage_info[i - 1]));
6962 if (!slot->arch.lpage_info[i - 1])
6965 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6966 slot->arch.lpage_info[i - 1][0].write_count = 1;
6967 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6968 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
6969 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6971 * If the gfn and userspace address are not aligned wrt each
6972 * other, or if explicitly asked to, disable large page
6973 * support for this slot
6975 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6976 !kvm_largepages_enabled()) {
6979 for (j = 0; j < lpages; ++j)
6980 slot->arch.lpage_info[i - 1][j].write_count = 1;
6987 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6988 kvm_kvfree(slot->arch.rmap[i]);
6989 slot->arch.rmap[i] = NULL;
6993 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6994 slot->arch.lpage_info[i - 1] = NULL;
6999 void kvm_arch_memslots_updated(struct kvm *kvm)
7003 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7004 struct kvm_memory_slot *memslot,
7005 struct kvm_userspace_memory_region *mem,
7006 enum kvm_mr_change change)
7009 * Only private memory slots need to be mapped here since
7010 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7012 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7013 unsigned long userspace_addr;
7016 * MAP_SHARED to prevent internal slot pages from being moved
7019 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7020 PROT_READ | PROT_WRITE,
7021 MAP_SHARED | MAP_ANONYMOUS, 0);
7023 if (IS_ERR((void *)userspace_addr))
7024 return PTR_ERR((void *)userspace_addr);
7026 memslot->userspace_addr = userspace_addr;
7032 void kvm_arch_commit_memory_region(struct kvm *kvm,
7033 struct kvm_userspace_memory_region *mem,
7034 const struct kvm_memory_slot *old,
7035 enum kvm_mr_change change)
7038 int nr_mmu_pages = 0;
7040 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7043 ret = vm_munmap(old->userspace_addr,
7044 old->npages * PAGE_SIZE);
7047 "kvm_vm_ioctl_set_memory_region: "
7048 "failed to munmap memory\n");
7051 if (!kvm->arch.n_requested_mmu_pages)
7052 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7055 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7057 * Write protect all pages for dirty logging.
7058 * Existing largepage mappings are destroyed here and new ones will
7059 * not be created until the end of the logging.
7061 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7062 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7064 * If memory slot is created, or moved, we need to clear all
7067 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
7068 kvm_mmu_zap_mmio_sptes(kvm);
7069 kvm_reload_remote_mmus(kvm);
7073 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7075 kvm_mmu_zap_all(kvm);
7076 kvm_reload_remote_mmus(kvm);
7079 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7080 struct kvm_memory_slot *slot)
7082 kvm_arch_flush_shadow_all(kvm);
7085 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7087 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7088 !vcpu->arch.apf.halted)
7089 || !list_empty_careful(&vcpu->async_pf.done)
7090 || kvm_apic_has_events(vcpu)
7091 || atomic_read(&vcpu->arch.nmi_queued) ||
7092 (kvm_arch_interrupt_allowed(vcpu) &&
7093 kvm_cpu_has_interrupt(vcpu));
7096 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7098 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7101 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7103 return kvm_x86_ops->interrupt_allowed(vcpu);
7106 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7108 unsigned long current_rip = kvm_rip_read(vcpu) +
7109 get_segment_base(vcpu, VCPU_SREG_CS);
7111 return current_rip == linear_rip;
7113 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7115 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7117 unsigned long rflags;
7119 rflags = kvm_x86_ops->get_rflags(vcpu);
7120 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7121 rflags &= ~X86_EFLAGS_TF;
7124 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7126 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7128 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7129 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7130 rflags |= X86_EFLAGS_TF;
7131 kvm_x86_ops->set_rflags(vcpu, rflags);
7132 kvm_make_request(KVM_REQ_EVENT, vcpu);
7134 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7136 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7140 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7144 r = kvm_mmu_reload(vcpu);
7148 if (!vcpu->arch.mmu.direct_map &&
7149 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7152 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7155 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7157 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7160 static inline u32 kvm_async_pf_next_probe(u32 key)
7162 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7165 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7167 u32 key = kvm_async_pf_hash_fn(gfn);
7169 while (vcpu->arch.apf.gfns[key] != ~0)
7170 key = kvm_async_pf_next_probe(key);
7172 vcpu->arch.apf.gfns[key] = gfn;
7175 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7178 u32 key = kvm_async_pf_hash_fn(gfn);
7180 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7181 (vcpu->arch.apf.gfns[key] != gfn &&
7182 vcpu->arch.apf.gfns[key] != ~0); i++)
7183 key = kvm_async_pf_next_probe(key);
7188 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7190 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7193 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7197 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7199 vcpu->arch.apf.gfns[i] = ~0;
7201 j = kvm_async_pf_next_probe(j);
7202 if (vcpu->arch.apf.gfns[j] == ~0)
7204 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7206 * k lies cyclically in ]i,j]
7208 * |....j i.k.| or |.k..j i...|
7210 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7211 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7216 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7219 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7223 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7224 struct kvm_async_pf *work)
7226 struct x86_exception fault;
7228 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7229 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7231 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7232 (vcpu->arch.apf.send_user_only &&
7233 kvm_x86_ops->get_cpl(vcpu) == 0))
7234 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7235 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7236 fault.vector = PF_VECTOR;
7237 fault.error_code_valid = true;
7238 fault.error_code = 0;
7239 fault.nested_page_fault = false;
7240 fault.address = work->arch.token;
7241 kvm_inject_page_fault(vcpu, &fault);
7245 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7246 struct kvm_async_pf *work)
7248 struct x86_exception fault;
7250 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7251 if (work->wakeup_all)
7252 work->arch.token = ~0; /* broadcast wakeup */
7254 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7256 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7257 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7258 fault.vector = PF_VECTOR;
7259 fault.error_code_valid = true;
7260 fault.error_code = 0;
7261 fault.nested_page_fault = false;
7262 fault.address = work->arch.token;
7263 kvm_inject_page_fault(vcpu, &fault);
7265 vcpu->arch.apf.halted = false;
7266 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7269 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7271 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7274 return !kvm_event_needs_reinjection(vcpu) &&
7275 kvm_x86_ops->interrupt_allowed(vcpu);
7278 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7279 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7280 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7281 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7282 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7283 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7284 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7285 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7286 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7287 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7288 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7289 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);