2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
53 #define CREATE_TRACE_POINTS
56 #include <asm/debugreg.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109 static bool backwards_tsc_observed = false;
111 #define KVM_NR_SHARED_MSRS 16
113 struct kvm_shared_msrs_global {
115 u32 msrs[KVM_NR_SHARED_MSRS];
118 struct kvm_shared_msrs {
119 struct user_return_notifier urn;
121 struct kvm_shared_msr_values {
124 } values[KVM_NR_SHARED_MSRS];
127 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
128 static struct kvm_shared_msrs __percpu *shared_msrs;
130 struct kvm_stats_debugfs_item debugfs_entries[] = {
131 { "pf_fixed", VCPU_STAT(pf_fixed) },
132 { "pf_guest", VCPU_STAT(pf_guest) },
133 { "tlb_flush", VCPU_STAT(tlb_flush) },
134 { "invlpg", VCPU_STAT(invlpg) },
135 { "exits", VCPU_STAT(exits) },
136 { "io_exits", VCPU_STAT(io_exits) },
137 { "mmio_exits", VCPU_STAT(mmio_exits) },
138 { "signal_exits", VCPU_STAT(signal_exits) },
139 { "irq_window", VCPU_STAT(irq_window_exits) },
140 { "nmi_window", VCPU_STAT(nmi_window_exits) },
141 { "halt_exits", VCPU_STAT(halt_exits) },
142 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
143 { "hypercalls", VCPU_STAT(hypercalls) },
144 { "request_irq", VCPU_STAT(request_irq_exits) },
145 { "irq_exits", VCPU_STAT(irq_exits) },
146 { "host_state_reload", VCPU_STAT(host_state_reload) },
147 { "efer_reload", VCPU_STAT(efer_reload) },
148 { "fpu_reload", VCPU_STAT(fpu_reload) },
149 { "insn_emulation", VCPU_STAT(insn_emulation) },
150 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
151 { "irq_injections", VCPU_STAT(irq_injections) },
152 { "nmi_injections", VCPU_STAT(nmi_injections) },
153 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
154 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
155 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
156 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
157 { "mmu_flooded", VM_STAT(mmu_flooded) },
158 { "mmu_recycled", VM_STAT(mmu_recycled) },
159 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
160 { "mmu_unsync", VM_STAT(mmu_unsync) },
161 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
162 { "largepages", VM_STAT(lpages) },
166 u64 __read_mostly host_xcr0;
168 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
170 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
173 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
174 vcpu->arch.apf.gfns[i] = ~0;
177 static void kvm_on_user_return(struct user_return_notifier *urn)
180 struct kvm_shared_msrs *locals
181 = container_of(urn, struct kvm_shared_msrs, urn);
182 struct kvm_shared_msr_values *values;
184 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
185 values = &locals->values[slot];
186 if (values->host != values->curr) {
187 wrmsrl(shared_msrs_global.msrs[slot], values->host);
188 values->curr = values->host;
191 locals->registered = false;
192 user_return_notifier_unregister(urn);
195 static void shared_msr_update(unsigned slot, u32 msr)
198 unsigned int cpu = smp_processor_id();
199 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
201 /* only read, and nobody should modify it at this time,
202 * so don't need lock */
203 if (slot >= shared_msrs_global.nr) {
204 printk(KERN_ERR "kvm: invalid MSR slot!");
207 rdmsrl_safe(msr, &value);
208 smsr->values[slot].host = value;
209 smsr->values[slot].curr = value;
212 void kvm_define_shared_msr(unsigned slot, u32 msr)
214 if (slot >= shared_msrs_global.nr)
215 shared_msrs_global.nr = slot + 1;
216 shared_msrs_global.msrs[slot] = msr;
217 /* we need ensured the shared_msr_global have been updated */
220 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
222 static void kvm_shared_msr_cpu_online(void)
226 for (i = 0; i < shared_msrs_global.nr; ++i)
227 shared_msr_update(i, shared_msrs_global.msrs[i]);
230 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
232 unsigned int cpu = smp_processor_id();
233 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
235 if (((value ^ smsr->values[slot].curr) & mask) == 0)
237 smsr->values[slot].curr = value;
238 wrmsrl(shared_msrs_global.msrs[slot], value);
239 if (!smsr->registered) {
240 smsr->urn.on_user_return = kvm_on_user_return;
241 user_return_notifier_register(&smsr->urn);
242 smsr->registered = true;
245 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
247 static void drop_user_return_notifiers(void *ignore)
249 unsigned int cpu = smp_processor_id();
250 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
252 if (smsr->registered)
253 kvm_on_user_return(&smsr->urn);
256 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
258 return vcpu->arch.apic_base;
260 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
262 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
264 u64 old_state = vcpu->arch.apic_base &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 new_state = msr_info->data &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
269 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
271 if (!msr_info->host_initiated &&
272 ((msr_info->data & reserved_bits) != 0 ||
273 new_state == X2APIC_ENABLE ||
274 (new_state == MSR_IA32_APICBASE_ENABLE &&
275 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
276 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
280 kvm_lapic_set_base(vcpu, msr_info->data);
283 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
285 asmlinkage __visible void kvm_spurious_fault(void)
287 /* Fault while not rebooting. We want the trace. */
290 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
292 #define EXCPT_BENIGN 0
293 #define EXCPT_CONTRIBUTORY 1
296 static int exception_class(int vector)
306 return EXCPT_CONTRIBUTORY;
313 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
314 unsigned nr, bool has_error, u32 error_code,
320 kvm_make_request(KVM_REQ_EVENT, vcpu);
322 if (!vcpu->arch.exception.pending) {
324 vcpu->arch.exception.pending = true;
325 vcpu->arch.exception.has_error_code = has_error;
326 vcpu->arch.exception.nr = nr;
327 vcpu->arch.exception.error_code = error_code;
328 vcpu->arch.exception.reinject = reinject;
332 /* to check exception */
333 prev_nr = vcpu->arch.exception.nr;
334 if (prev_nr == DF_VECTOR) {
335 /* triple fault -> shutdown */
336 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
339 class1 = exception_class(prev_nr);
340 class2 = exception_class(nr);
341 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
342 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
343 /* generate double fault per SDM Table 5-5 */
344 vcpu->arch.exception.pending = true;
345 vcpu->arch.exception.has_error_code = true;
346 vcpu->arch.exception.nr = DF_VECTOR;
347 vcpu->arch.exception.error_code = 0;
349 /* replace previous exception with a new one in a hope
350 that instruction re-execution will regenerate lost
355 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
357 kvm_multiple_exception(vcpu, nr, false, 0, false);
359 EXPORT_SYMBOL_GPL(kvm_queue_exception);
361 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
363 kvm_multiple_exception(vcpu, nr, false, 0, true);
365 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
367 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
370 kvm_inject_gp(vcpu, 0);
372 kvm_x86_ops->skip_emulated_instruction(vcpu);
374 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
376 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
378 ++vcpu->stat.pf_guest;
379 vcpu->arch.cr2 = fault->address;
380 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
382 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
384 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
386 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
387 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
389 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
392 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
394 atomic_inc(&vcpu->arch.nmi_queued);
395 kvm_make_request(KVM_REQ_NMI, vcpu);
397 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
399 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
401 kvm_multiple_exception(vcpu, nr, true, error_code, false);
403 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
405 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
407 kvm_multiple_exception(vcpu, nr, true, error_code, true);
409 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
412 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
413 * a #GP and return false.
415 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
417 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
419 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
422 EXPORT_SYMBOL_GPL(kvm_require_cpl);
425 * This function will be used to read from the physical memory of the currently
426 * running guest. The difference to kvm_read_guest_page is that this function
427 * can read from guest physical or from the guest's guest physical memory.
429 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
430 gfn_t ngfn, void *data, int offset, int len,
436 ngpa = gfn_to_gpa(ngfn);
437 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
438 if (real_gfn == UNMAPPED_GVA)
441 real_gfn = gpa_to_gfn(real_gfn);
443 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
445 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
447 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
448 void *data, int offset, int len, u32 access)
450 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
451 data, offset, len, access);
455 * Load the pae pdptrs. Return true is they are all valid.
457 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
459 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
460 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
463 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
465 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
466 offset * sizeof(u64), sizeof(pdpte),
467 PFERR_USER_MASK|PFERR_WRITE_MASK);
472 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
473 if (is_present_gpte(pdpte[i]) &&
474 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
481 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail);
484 __set_bit(VCPU_EXREG_PDPTR,
485 (unsigned long *)&vcpu->arch.regs_dirty);
490 EXPORT_SYMBOL_GPL(load_pdptrs);
492 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
494 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
500 if (is_long_mode(vcpu) || !is_pae(vcpu))
503 if (!test_bit(VCPU_EXREG_PDPTR,
504 (unsigned long *)&vcpu->arch.regs_avail))
507 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
508 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
509 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
510 PFERR_USER_MASK | PFERR_WRITE_MASK);
513 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
519 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
521 unsigned long old_cr0 = kvm_read_cr0(vcpu);
522 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
523 X86_CR0_CD | X86_CR0_NW;
528 if (cr0 & 0xffffffff00000000UL)
532 cr0 &= ~CR0_RESERVED_BITS;
534 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
537 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
540 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
542 if ((vcpu->arch.efer & EFER_LME)) {
547 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
552 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
557 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
560 kvm_x86_ops->set_cr0(vcpu, cr0);
562 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
563 kvm_clear_async_pf_completion_queue(vcpu);
564 kvm_async_pf_hash_reset(vcpu);
567 if ((cr0 ^ old_cr0) & update_bits)
568 kvm_mmu_reset_context(vcpu);
571 EXPORT_SYMBOL_GPL(kvm_set_cr0);
573 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
575 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
577 EXPORT_SYMBOL_GPL(kvm_lmsw);
579 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
581 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
582 !vcpu->guest_xcr0_loaded) {
583 /* kvm_set_xcr() also depends on this */
584 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
585 vcpu->guest_xcr0_loaded = 1;
589 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
591 if (vcpu->guest_xcr0_loaded) {
592 if (vcpu->arch.xcr0 != host_xcr0)
593 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
594 vcpu->guest_xcr0_loaded = 0;
598 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
601 u64 old_xcr0 = vcpu->arch.xcr0;
604 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
605 if (index != XCR_XFEATURE_ENABLED_MASK)
607 if (!(xcr0 & XSTATE_FP))
609 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
613 * Do not allow the guest to set bits that we do not support
614 * saving. However, xcr0 bit 0 is always set, even if the
615 * emulated CPU does not support XSAVE (see fx_init).
617 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
618 if (xcr0 & ~valid_bits)
621 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
624 kvm_put_guest_xcr0(vcpu);
625 vcpu->arch.xcr0 = xcr0;
627 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
628 kvm_update_cpuid(vcpu);
632 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
634 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
635 __kvm_set_xcr(vcpu, index, xcr)) {
636 kvm_inject_gp(vcpu, 0);
641 EXPORT_SYMBOL_GPL(kvm_set_xcr);
643 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
645 unsigned long old_cr4 = kvm_read_cr4(vcpu);
646 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
647 X86_CR4_PAE | X86_CR4_SMEP;
648 if (cr4 & CR4_RESERVED_BITS)
651 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
654 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
657 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
660 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
663 if (is_long_mode(vcpu)) {
664 if (!(cr4 & X86_CR4_PAE))
666 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
667 && ((cr4 ^ old_cr4) & pdptr_bits)
668 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
672 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
673 if (!guest_cpuid_has_pcid(vcpu))
676 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
677 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
681 if (kvm_x86_ops->set_cr4(vcpu, cr4))
684 if (((cr4 ^ old_cr4) & pdptr_bits) ||
685 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
686 kvm_mmu_reset_context(vcpu);
688 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
689 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
691 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
692 kvm_update_cpuid(vcpu);
696 EXPORT_SYMBOL_GPL(kvm_set_cr4);
698 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
700 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
701 kvm_mmu_sync_roots(vcpu);
702 kvm_mmu_flush_tlb(vcpu);
706 if (is_long_mode(vcpu)) {
707 if (cr3 & CR3_L_MODE_RESERVED_BITS)
709 } else if (is_pae(vcpu) && is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
713 vcpu->arch.cr3 = cr3;
714 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
715 kvm_mmu_new_cr3(vcpu);
718 EXPORT_SYMBOL_GPL(kvm_set_cr3);
720 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
722 if (cr8 & CR8_RESERVED_BITS)
724 if (irqchip_in_kernel(vcpu->kvm))
725 kvm_lapic_set_tpr(vcpu, cr8);
727 vcpu->arch.cr8 = cr8;
730 EXPORT_SYMBOL_GPL(kvm_set_cr8);
732 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
734 if (irqchip_in_kernel(vcpu->kvm))
735 return kvm_lapic_get_cr8(vcpu);
737 return vcpu->arch.cr8;
739 EXPORT_SYMBOL_GPL(kvm_get_cr8);
741 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
743 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
744 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
747 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
751 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
752 dr7 = vcpu->arch.guest_debug_dr7;
754 dr7 = vcpu->arch.dr7;
755 kvm_x86_ops->set_dr7(vcpu, dr7);
756 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
757 if (dr7 & DR7_BP_EN_MASK)
758 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
761 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
765 vcpu->arch.db[dr] = val;
766 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
767 vcpu->arch.eff_db[dr] = val;
770 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
774 if (val & 0xffffffff00000000ULL)
776 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
777 kvm_update_dr6(vcpu);
780 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
784 if (val & 0xffffffff00000000ULL)
786 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
787 kvm_update_dr7(vcpu);
794 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
798 res = __kvm_set_dr(vcpu, dr, val);
800 kvm_queue_exception(vcpu, UD_VECTOR);
802 kvm_inject_gp(vcpu, 0);
806 EXPORT_SYMBOL_GPL(kvm_set_dr);
808 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
812 *val = vcpu->arch.db[dr];
815 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
819 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
820 *val = vcpu->arch.dr6;
822 *val = kvm_x86_ops->get_dr6(vcpu);
825 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
829 *val = vcpu->arch.dr7;
836 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
838 if (_kvm_get_dr(vcpu, dr, val)) {
839 kvm_queue_exception(vcpu, UD_VECTOR);
844 EXPORT_SYMBOL_GPL(kvm_get_dr);
846 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
848 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
852 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
855 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
856 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
859 EXPORT_SYMBOL_GPL(kvm_rdpmc);
862 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
863 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
865 * This list is modified at module load time to reflect the
866 * capabilities of the host cpu. This capabilities test skips MSRs that are
867 * kvm-specific. Those are put in the beginning of the list.
870 #define KVM_SAVE_MSRS_BEGIN 12
871 static u32 msrs_to_save[] = {
872 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
873 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
874 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
875 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
876 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
878 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
881 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
883 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
884 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
887 static unsigned num_msrs_to_save;
889 static const u32 emulated_msrs[] = {
891 MSR_IA32_TSCDEADLINE,
892 MSR_IA32_MISC_ENABLE,
897 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
899 if (efer & efer_reserved_bits)
902 if (efer & EFER_FFXSR) {
903 struct kvm_cpuid_entry2 *feat;
905 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
906 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
910 if (efer & EFER_SVME) {
911 struct kvm_cpuid_entry2 *feat;
913 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
914 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
920 EXPORT_SYMBOL_GPL(kvm_valid_efer);
922 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
924 u64 old_efer = vcpu->arch.efer;
926 if (!kvm_valid_efer(vcpu, efer))
930 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
934 efer |= vcpu->arch.efer & EFER_LMA;
936 kvm_x86_ops->set_efer(vcpu, efer);
938 /* Update reserved bits */
939 if ((efer ^ old_efer) & EFER_NX)
940 kvm_mmu_reset_context(vcpu);
945 void kvm_enable_efer_bits(u64 mask)
947 efer_reserved_bits &= ~mask;
949 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
953 * Writes msr value into into the appropriate "register".
954 * Returns 0 on success, non-0 otherwise.
955 * Assumes vcpu_load() was already called.
957 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
959 return kvm_x86_ops->set_msr(vcpu, msr);
963 * Adapt set_msr() to msr_io()'s calling convention
965 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
971 msr.host_initiated = true;
972 return kvm_set_msr(vcpu, &msr);
976 struct pvclock_gtod_data {
979 struct { /* extract of a clocksource struct */
987 /* open coded 'struct timespec' */
988 u64 monotonic_time_snsec;
989 time_t monotonic_time_sec;
992 static struct pvclock_gtod_data pvclock_gtod_data;
994 static void update_pvclock_gtod(struct timekeeper *tk)
996 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
998 write_seqcount_begin(&vdata->seq);
1000 /* copy pvclock gtod data */
1001 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1002 vdata->clock.cycle_last = tk->clock->cycle_last;
1003 vdata->clock.mask = tk->clock->mask;
1004 vdata->clock.mult = tk->mult;
1005 vdata->clock.shift = tk->shift;
1007 vdata->monotonic_time_sec = tk->xtime_sec
1008 + tk->wall_to_monotonic.tv_sec;
1009 vdata->monotonic_time_snsec = tk->xtime_nsec
1010 + (tk->wall_to_monotonic.tv_nsec
1012 while (vdata->monotonic_time_snsec >=
1013 (((u64)NSEC_PER_SEC) << tk->shift)) {
1014 vdata->monotonic_time_snsec -=
1015 ((u64)NSEC_PER_SEC) << tk->shift;
1016 vdata->monotonic_time_sec++;
1019 write_seqcount_end(&vdata->seq);
1024 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1028 struct pvclock_wall_clock wc;
1029 struct timespec boot;
1034 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1039 ++version; /* first time write, random junk */
1043 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1046 * The guest calculates current wall clock time by adding
1047 * system time (updated by kvm_guest_time_update below) to the
1048 * wall clock specified here. guest system time equals host
1049 * system time for us, thus we must fill in host boot time here.
1053 if (kvm->arch.kvmclock_offset) {
1054 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1055 boot = timespec_sub(boot, ts);
1057 wc.sec = boot.tv_sec;
1058 wc.nsec = boot.tv_nsec;
1059 wc.version = version;
1061 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1064 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1067 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1069 uint32_t quotient, remainder;
1071 /* Don't try to replace with do_div(), this one calculates
1072 * "(dividend << 32) / divisor" */
1074 : "=a" (quotient), "=d" (remainder)
1075 : "0" (0), "1" (dividend), "r" (divisor) );
1079 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1080 s8 *pshift, u32 *pmultiplier)
1087 tps64 = base_khz * 1000LL;
1088 scaled64 = scaled_khz * 1000LL;
1089 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1094 tps32 = (uint32_t)tps64;
1095 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1096 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1104 *pmultiplier = div_frac(scaled64, tps32);
1106 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1107 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1110 static inline u64 get_kernel_ns(void)
1115 monotonic_to_bootbased(&ts);
1116 return timespec_to_ns(&ts);
1119 #ifdef CONFIG_X86_64
1120 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1123 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1124 unsigned long max_tsc_khz;
1126 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1128 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1129 vcpu->arch.virtual_tsc_shift);
1132 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1134 u64 v = (u64)khz * (1000000 + ppm);
1139 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1141 u32 thresh_lo, thresh_hi;
1142 int use_scaling = 0;
1144 /* tsc_khz can be zero if TSC calibration fails */
1145 if (this_tsc_khz == 0)
1148 /* Compute a scale to convert nanoseconds in TSC cycles */
1149 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1150 &vcpu->arch.virtual_tsc_shift,
1151 &vcpu->arch.virtual_tsc_mult);
1152 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1155 * Compute the variation in TSC rate which is acceptable
1156 * within the range of tolerance and decide if the
1157 * rate being applied is within that bounds of the hardware
1158 * rate. If so, no scaling or compensation need be done.
1160 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1161 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1162 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1163 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1166 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1169 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1171 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1172 vcpu->arch.virtual_tsc_mult,
1173 vcpu->arch.virtual_tsc_shift);
1174 tsc += vcpu->arch.this_tsc_write;
1178 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1180 #ifdef CONFIG_X86_64
1182 bool do_request = false;
1183 struct kvm_arch *ka = &vcpu->kvm->arch;
1184 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1186 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1187 atomic_read(&vcpu->kvm->online_vcpus));
1189 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1190 if (!ka->use_master_clock)
1193 if (!vcpus_matched && ka->use_master_clock)
1197 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1199 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1200 atomic_read(&vcpu->kvm->online_vcpus),
1201 ka->use_master_clock, gtod->clock.vclock_mode);
1205 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1207 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1208 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1211 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1213 struct kvm *kvm = vcpu->kvm;
1214 u64 offset, ns, elapsed;
1215 unsigned long flags;
1218 u64 data = msr->data;
1220 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1221 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1222 ns = get_kernel_ns();
1223 elapsed = ns - kvm->arch.last_tsc_nsec;
1225 if (vcpu->arch.virtual_tsc_khz) {
1228 /* n.b - signed multiplication and division required */
1229 usdiff = data - kvm->arch.last_tsc_write;
1230 #ifdef CONFIG_X86_64
1231 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1233 /* do_div() only does unsigned */
1234 asm("1: idivl %[divisor]\n"
1235 "2: xor %%edx, %%edx\n"
1236 " movl $0, %[faulted]\n"
1238 ".section .fixup,\"ax\"\n"
1239 "4: movl $1, %[faulted]\n"
1243 _ASM_EXTABLE(1b, 4b)
1245 : "=A"(usdiff), [faulted] "=r" (faulted)
1246 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1249 do_div(elapsed, 1000);
1254 /* idivl overflow => difference is larger than USEC_PER_SEC */
1256 usdiff = USEC_PER_SEC;
1258 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1261 * Special case: TSC write with a small delta (1 second) of virtual
1262 * cycle time against real time is interpreted as an attempt to
1263 * synchronize the CPU.
1265 * For a reliable TSC, we can match TSC offsets, and for an unstable
1266 * TSC, we add elapsed time in this computation. We could let the
1267 * compensation code attempt to catch up if we fall behind, but
1268 * it's better to try to match offsets from the beginning.
1270 if (usdiff < USEC_PER_SEC &&
1271 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1272 if (!check_tsc_unstable()) {
1273 offset = kvm->arch.cur_tsc_offset;
1274 pr_debug("kvm: matched tsc offset for %llu\n", data);
1276 u64 delta = nsec_to_cycles(vcpu, elapsed);
1278 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1279 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1284 * We split periods of matched TSC writes into generations.
1285 * For each generation, we track the original measured
1286 * nanosecond time, offset, and write, so if TSCs are in
1287 * sync, we can match exact offset, and if not, we can match
1288 * exact software computation in compute_guest_tsc()
1290 * These values are tracked in kvm->arch.cur_xxx variables.
1292 kvm->arch.cur_tsc_generation++;
1293 kvm->arch.cur_tsc_nsec = ns;
1294 kvm->arch.cur_tsc_write = data;
1295 kvm->arch.cur_tsc_offset = offset;
1297 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1298 kvm->arch.cur_tsc_generation, data);
1302 * We also track th most recent recorded KHZ, write and time to
1303 * allow the matching interval to be extended at each write.
1305 kvm->arch.last_tsc_nsec = ns;
1306 kvm->arch.last_tsc_write = data;
1307 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1309 vcpu->arch.last_guest_tsc = data;
1311 /* Keep track of which generation this VCPU has synchronized to */
1312 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1313 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1314 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1316 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1317 update_ia32_tsc_adjust_msr(vcpu, offset);
1318 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1319 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1321 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1323 kvm->arch.nr_vcpus_matched_tsc++;
1325 kvm->arch.nr_vcpus_matched_tsc = 0;
1327 kvm_track_tsc_matching(vcpu);
1328 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1331 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1333 #ifdef CONFIG_X86_64
1335 static cycle_t read_tsc(void)
1341 * Empirically, a fence (of type that depends on the CPU)
1342 * before rdtsc is enough to ensure that rdtsc is ordered
1343 * with respect to loads. The various CPU manuals are unclear
1344 * as to whether rdtsc can be reordered with later loads,
1345 * but no one has ever seen it happen.
1348 ret = (cycle_t)vget_cycles();
1350 last = pvclock_gtod_data.clock.cycle_last;
1352 if (likely(ret >= last))
1356 * GCC likes to generate cmov here, but this branch is extremely
1357 * predictable (it's just a funciton of time and the likely is
1358 * very likely) and there's a data dependence, so force GCC
1359 * to generate a branch instead. I don't barrier() because
1360 * we don't actually need a barrier, and if this function
1361 * ever gets inlined it will generate worse code.
1367 static inline u64 vgettsc(cycle_t *cycle_now)
1370 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1372 *cycle_now = read_tsc();
1374 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1375 return v * gtod->clock.mult;
1378 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1383 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1387 seq = read_seqcount_begin(>od->seq);
1388 mode = gtod->clock.vclock_mode;
1389 ts->tv_sec = gtod->monotonic_time_sec;
1390 ns = gtod->monotonic_time_snsec;
1391 ns += vgettsc(cycle_now);
1392 ns >>= gtod->clock.shift;
1393 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1394 timespec_add_ns(ts, ns);
1399 /* returns true if host is using tsc clocksource */
1400 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1404 /* checked again under seqlock below */
1405 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1408 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1411 monotonic_to_bootbased(&ts);
1412 *kernel_ns = timespec_to_ns(&ts);
1420 * Assuming a stable TSC across physical CPUS, and a stable TSC
1421 * across virtual CPUs, the following condition is possible.
1422 * Each numbered line represents an event visible to both
1423 * CPUs at the next numbered event.
1425 * "timespecX" represents host monotonic time. "tscX" represents
1428 * VCPU0 on CPU0 | VCPU1 on CPU1
1430 * 1. read timespec0,tsc0
1431 * 2. | timespec1 = timespec0 + N
1433 * 3. transition to guest | transition to guest
1434 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1435 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1436 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1438 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1441 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1443 * - 0 < N - M => M < N
1445 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1446 * always the case (the difference between two distinct xtime instances
1447 * might be smaller then the difference between corresponding TSC reads,
1448 * when updating guest vcpus pvclock areas).
1450 * To avoid that problem, do not allow visibility of distinct
1451 * system_timestamp/tsc_timestamp values simultaneously: use a master
1452 * copy of host monotonic time values. Update that master copy
1455 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1459 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1461 #ifdef CONFIG_X86_64
1462 struct kvm_arch *ka = &kvm->arch;
1464 bool host_tsc_clocksource, vcpus_matched;
1466 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1467 atomic_read(&kvm->online_vcpus));
1470 * If the host uses TSC clock, then passthrough TSC as stable
1473 host_tsc_clocksource = kvm_get_time_and_clockread(
1474 &ka->master_kernel_ns,
1475 &ka->master_cycle_now);
1477 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1478 && !backwards_tsc_observed;
1480 if (ka->use_master_clock)
1481 atomic_set(&kvm_guest_has_master_clock, 1);
1483 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1484 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1489 static void kvm_gen_update_masterclock(struct kvm *kvm)
1491 #ifdef CONFIG_X86_64
1493 struct kvm_vcpu *vcpu;
1494 struct kvm_arch *ka = &kvm->arch;
1496 spin_lock(&ka->pvclock_gtod_sync_lock);
1497 kvm_make_mclock_inprogress_request(kvm);
1498 /* no guest entries from this point */
1499 pvclock_update_vm_gtod_copy(kvm);
1501 kvm_for_each_vcpu(i, vcpu, kvm)
1502 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1504 /* guest entries allowed */
1505 kvm_for_each_vcpu(i, vcpu, kvm)
1506 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1508 spin_unlock(&ka->pvclock_gtod_sync_lock);
1512 static int kvm_guest_time_update(struct kvm_vcpu *v)
1514 unsigned long flags, this_tsc_khz;
1515 struct kvm_vcpu_arch *vcpu = &v->arch;
1516 struct kvm_arch *ka = &v->kvm->arch;
1518 u64 tsc_timestamp, host_tsc;
1519 struct pvclock_vcpu_time_info guest_hv_clock;
1521 bool use_master_clock;
1527 * If the host uses TSC clock, then passthrough TSC as stable
1530 spin_lock(&ka->pvclock_gtod_sync_lock);
1531 use_master_clock = ka->use_master_clock;
1532 if (use_master_clock) {
1533 host_tsc = ka->master_cycle_now;
1534 kernel_ns = ka->master_kernel_ns;
1536 spin_unlock(&ka->pvclock_gtod_sync_lock);
1538 /* Keep irq disabled to prevent changes to the clock */
1539 local_irq_save(flags);
1540 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1541 if (unlikely(this_tsc_khz == 0)) {
1542 local_irq_restore(flags);
1543 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1546 if (!use_master_clock) {
1547 host_tsc = native_read_tsc();
1548 kernel_ns = get_kernel_ns();
1551 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1554 * We may have to catch up the TSC to match elapsed wall clock
1555 * time for two reasons, even if kvmclock is used.
1556 * 1) CPU could have been running below the maximum TSC rate
1557 * 2) Broken TSC compensation resets the base at each VCPU
1558 * entry to avoid unknown leaps of TSC even when running
1559 * again on the same CPU. This may cause apparent elapsed
1560 * time to disappear, and the guest to stand still or run
1563 if (vcpu->tsc_catchup) {
1564 u64 tsc = compute_guest_tsc(v, kernel_ns);
1565 if (tsc > tsc_timestamp) {
1566 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1567 tsc_timestamp = tsc;
1571 local_irq_restore(flags);
1573 if (!vcpu->pv_time_enabled)
1576 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1577 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1578 &vcpu->hv_clock.tsc_shift,
1579 &vcpu->hv_clock.tsc_to_system_mul);
1580 vcpu->hw_tsc_khz = this_tsc_khz;
1583 /* With all the info we got, fill in the values */
1584 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1585 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1586 vcpu->last_guest_tsc = tsc_timestamp;
1589 * The interface expects us to write an even number signaling that the
1590 * update is finished. Since the guest won't see the intermediate
1591 * state, we just increase by 2 at the end.
1593 vcpu->hv_clock.version += 2;
1595 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1596 &guest_hv_clock, sizeof(guest_hv_clock))))
1599 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1600 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1602 if (vcpu->pvclock_set_guest_stopped_request) {
1603 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1604 vcpu->pvclock_set_guest_stopped_request = false;
1607 /* If the host uses TSC clocksource, then it is stable */
1608 if (use_master_clock)
1609 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1611 vcpu->hv_clock.flags = pvclock_flags;
1613 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1615 sizeof(vcpu->hv_clock));
1620 * kvmclock updates which are isolated to a given vcpu, such as
1621 * vcpu->cpu migration, should not allow system_timestamp from
1622 * the rest of the vcpus to remain static. Otherwise ntp frequency
1623 * correction applies to one vcpu's system_timestamp but not
1626 * So in those cases, request a kvmclock update for all vcpus.
1627 * We need to rate-limit these requests though, as they can
1628 * considerably slow guests that have a large number of vcpus.
1629 * The time for a remote vcpu to update its kvmclock is bound
1630 * by the delay we use to rate-limit the updates.
1633 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1635 static void kvmclock_update_fn(struct work_struct *work)
1638 struct delayed_work *dwork = to_delayed_work(work);
1639 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1640 kvmclock_update_work);
1641 struct kvm *kvm = container_of(ka, struct kvm, arch);
1642 struct kvm_vcpu *vcpu;
1644 kvm_for_each_vcpu(i, vcpu, kvm) {
1645 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1646 kvm_vcpu_kick(vcpu);
1650 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1652 struct kvm *kvm = v->kvm;
1654 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1655 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1656 KVMCLOCK_UPDATE_DELAY);
1659 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1661 static void kvmclock_sync_fn(struct work_struct *work)
1663 struct delayed_work *dwork = to_delayed_work(work);
1664 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1665 kvmclock_sync_work);
1666 struct kvm *kvm = container_of(ka, struct kvm, arch);
1668 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1669 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1670 KVMCLOCK_SYNC_PERIOD);
1673 static bool msr_mtrr_valid(unsigned msr)
1676 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1677 case MSR_MTRRfix64K_00000:
1678 case MSR_MTRRfix16K_80000:
1679 case MSR_MTRRfix16K_A0000:
1680 case MSR_MTRRfix4K_C0000:
1681 case MSR_MTRRfix4K_C8000:
1682 case MSR_MTRRfix4K_D0000:
1683 case MSR_MTRRfix4K_D8000:
1684 case MSR_MTRRfix4K_E0000:
1685 case MSR_MTRRfix4K_E8000:
1686 case MSR_MTRRfix4K_F0000:
1687 case MSR_MTRRfix4K_F8000:
1688 case MSR_MTRRdefType:
1689 case MSR_IA32_CR_PAT:
1697 static bool valid_pat_type(unsigned t)
1699 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1702 static bool valid_mtrr_type(unsigned t)
1704 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1707 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1711 if (!msr_mtrr_valid(msr))
1714 if (msr == MSR_IA32_CR_PAT) {
1715 for (i = 0; i < 8; i++)
1716 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1719 } else if (msr == MSR_MTRRdefType) {
1722 return valid_mtrr_type(data & 0xff);
1723 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1724 for (i = 0; i < 8 ; i++)
1725 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1730 /* variable MTRRs */
1731 return valid_mtrr_type(data & 0xff);
1734 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1736 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1738 if (!mtrr_valid(vcpu, msr, data))
1741 if (msr == MSR_MTRRdefType) {
1742 vcpu->arch.mtrr_state.def_type = data;
1743 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1744 } else if (msr == MSR_MTRRfix64K_00000)
1746 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1747 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1748 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1749 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1750 else if (msr == MSR_IA32_CR_PAT)
1751 vcpu->arch.pat = data;
1752 else { /* Variable MTRRs */
1753 int idx, is_mtrr_mask;
1756 idx = (msr - 0x200) / 2;
1757 is_mtrr_mask = msr - 0x200 - 2 * idx;
1760 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1763 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1767 kvm_mmu_reset_context(vcpu);
1771 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1773 u64 mcg_cap = vcpu->arch.mcg_cap;
1774 unsigned bank_num = mcg_cap & 0xff;
1777 case MSR_IA32_MCG_STATUS:
1778 vcpu->arch.mcg_status = data;
1780 case MSR_IA32_MCG_CTL:
1781 if (!(mcg_cap & MCG_CTL_P))
1783 if (data != 0 && data != ~(u64)0)
1785 vcpu->arch.mcg_ctl = data;
1788 if (msr >= MSR_IA32_MC0_CTL &&
1789 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1790 u32 offset = msr - MSR_IA32_MC0_CTL;
1791 /* only 0 or all 1s can be written to IA32_MCi_CTL
1792 * some Linux kernels though clear bit 10 in bank 4 to
1793 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1794 * this to avoid an uncatched #GP in the guest
1796 if ((offset & 0x3) == 0 &&
1797 data != 0 && (data | (1 << 10)) != ~(u64)0)
1799 vcpu->arch.mce_banks[offset] = data;
1807 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1809 struct kvm *kvm = vcpu->kvm;
1810 int lm = is_long_mode(vcpu);
1811 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1812 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1813 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1814 : kvm->arch.xen_hvm_config.blob_size_32;
1815 u32 page_num = data & ~PAGE_MASK;
1816 u64 page_addr = data & PAGE_MASK;
1821 if (page_num >= blob_size)
1824 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1829 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1838 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1840 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1843 static bool kvm_hv_msr_partition_wide(u32 msr)
1847 case HV_X64_MSR_GUEST_OS_ID:
1848 case HV_X64_MSR_HYPERCALL:
1849 case HV_X64_MSR_REFERENCE_TSC:
1850 case HV_X64_MSR_TIME_REF_COUNT:
1858 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1860 struct kvm *kvm = vcpu->kvm;
1863 case HV_X64_MSR_GUEST_OS_ID:
1864 kvm->arch.hv_guest_os_id = data;
1865 /* setting guest os id to zero disables hypercall page */
1866 if (!kvm->arch.hv_guest_os_id)
1867 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1869 case HV_X64_MSR_HYPERCALL: {
1874 /* if guest os id is not set hypercall should remain disabled */
1875 if (!kvm->arch.hv_guest_os_id)
1877 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1878 kvm->arch.hv_hypercall = data;
1881 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1882 addr = gfn_to_hva(kvm, gfn);
1883 if (kvm_is_error_hva(addr))
1885 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1886 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1887 if (__copy_to_user((void __user *)addr, instructions, 4))
1889 kvm->arch.hv_hypercall = data;
1890 mark_page_dirty(kvm, gfn);
1893 case HV_X64_MSR_REFERENCE_TSC: {
1895 HV_REFERENCE_TSC_PAGE tsc_ref;
1896 memset(&tsc_ref, 0, sizeof(tsc_ref));
1897 kvm->arch.hv_tsc_page = data;
1898 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1900 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1901 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
1902 &tsc_ref, sizeof(tsc_ref)))
1904 mark_page_dirty(kvm, gfn);
1908 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1909 "data 0x%llx\n", msr, data);
1915 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1918 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1922 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1923 vcpu->arch.hv_vapic = data;
1924 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1928 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1929 addr = gfn_to_hva(vcpu->kvm, gfn);
1930 if (kvm_is_error_hva(addr))
1932 if (__clear_user((void __user *)addr, PAGE_SIZE))
1934 vcpu->arch.hv_vapic = data;
1935 mark_page_dirty(vcpu->kvm, gfn);
1936 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1940 case HV_X64_MSR_EOI:
1941 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1942 case HV_X64_MSR_ICR:
1943 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1944 case HV_X64_MSR_TPR:
1945 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1947 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1948 "data 0x%llx\n", msr, data);
1955 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1957 gpa_t gpa = data & ~0x3f;
1959 /* Bits 2:5 are reserved, Should be zero */
1963 vcpu->arch.apf.msr_val = data;
1965 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1966 kvm_clear_async_pf_completion_queue(vcpu);
1967 kvm_async_pf_hash_reset(vcpu);
1971 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1975 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1976 kvm_async_pf_wakeup_all(vcpu);
1980 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1982 vcpu->arch.pv_time_enabled = false;
1985 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1989 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1992 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1993 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1994 vcpu->arch.st.accum_steal = delta;
1997 static void record_steal_time(struct kvm_vcpu *vcpu)
1999 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2002 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2003 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2006 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2007 vcpu->arch.st.steal.version += 2;
2008 vcpu->arch.st.accum_steal = 0;
2010 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2011 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2014 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2017 u32 msr = msr_info->index;
2018 u64 data = msr_info->data;
2021 case MSR_AMD64_NB_CFG:
2022 case MSR_IA32_UCODE_REV:
2023 case MSR_IA32_UCODE_WRITE:
2024 case MSR_VM_HSAVE_PA:
2025 case MSR_AMD64_PATCH_LOADER:
2026 case MSR_AMD64_BU_CFG2:
2030 return set_efer(vcpu, data);
2032 data &= ~(u64)0x40; /* ignore flush filter disable */
2033 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2034 data &= ~(u64)0x8; /* ignore TLB cache disable */
2036 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2041 case MSR_FAM10H_MMIO_CONF_BASE:
2043 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2048 case MSR_IA32_DEBUGCTLMSR:
2050 /* We support the non-activated case already */
2052 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2053 /* Values other than LBR and BTF are vendor-specific,
2054 thus reserved and should throw a #GP */
2057 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2060 case 0x200 ... 0x2ff:
2061 return set_msr_mtrr(vcpu, msr, data);
2062 case MSR_IA32_APICBASE:
2063 return kvm_set_apic_base(vcpu, msr_info);
2064 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2065 return kvm_x2apic_msr_write(vcpu, msr, data);
2066 case MSR_IA32_TSCDEADLINE:
2067 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2069 case MSR_IA32_TSC_ADJUST:
2070 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2071 if (!msr_info->host_initiated) {
2072 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2073 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2075 vcpu->arch.ia32_tsc_adjust_msr = data;
2078 case MSR_IA32_MISC_ENABLE:
2079 vcpu->arch.ia32_misc_enable_msr = data;
2081 case MSR_KVM_WALL_CLOCK_NEW:
2082 case MSR_KVM_WALL_CLOCK:
2083 vcpu->kvm->arch.wall_clock = data;
2084 kvm_write_wall_clock(vcpu->kvm, data);
2086 case MSR_KVM_SYSTEM_TIME_NEW:
2087 case MSR_KVM_SYSTEM_TIME: {
2089 kvmclock_reset(vcpu);
2091 vcpu->arch.time = data;
2092 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2094 /* we verify if the enable bit is set... */
2098 gpa_offset = data & ~(PAGE_MASK | 1);
2100 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2101 &vcpu->arch.pv_time, data & ~1ULL,
2102 sizeof(struct pvclock_vcpu_time_info)))
2103 vcpu->arch.pv_time_enabled = false;
2105 vcpu->arch.pv_time_enabled = true;
2109 case MSR_KVM_ASYNC_PF_EN:
2110 if (kvm_pv_enable_async_pf(vcpu, data))
2113 case MSR_KVM_STEAL_TIME:
2115 if (unlikely(!sched_info_on()))
2118 if (data & KVM_STEAL_RESERVED_MASK)
2121 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2122 data & KVM_STEAL_VALID_BITS,
2123 sizeof(struct kvm_steal_time)))
2126 vcpu->arch.st.msr_val = data;
2128 if (!(data & KVM_MSR_ENABLED))
2131 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2134 accumulate_steal_time(vcpu);
2137 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2140 case MSR_KVM_PV_EOI_EN:
2141 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2145 case MSR_IA32_MCG_CTL:
2146 case MSR_IA32_MCG_STATUS:
2147 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2148 return set_msr_mce(vcpu, msr, data);
2150 /* Performance counters are not protected by a CPUID bit,
2151 * so we should check all of them in the generic path for the sake of
2152 * cross vendor migration.
2153 * Writing a zero into the event select MSRs disables them,
2154 * which we perfectly emulate ;-). Any other value should be at least
2155 * reported, some guests depend on them.
2157 case MSR_K7_EVNTSEL0:
2158 case MSR_K7_EVNTSEL1:
2159 case MSR_K7_EVNTSEL2:
2160 case MSR_K7_EVNTSEL3:
2162 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2163 "0x%x data 0x%llx\n", msr, data);
2165 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2166 * so we ignore writes to make it happy.
2168 case MSR_K7_PERFCTR0:
2169 case MSR_K7_PERFCTR1:
2170 case MSR_K7_PERFCTR2:
2171 case MSR_K7_PERFCTR3:
2172 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2173 "0x%x data 0x%llx\n", msr, data);
2175 case MSR_P6_PERFCTR0:
2176 case MSR_P6_PERFCTR1:
2178 case MSR_P6_EVNTSEL0:
2179 case MSR_P6_EVNTSEL1:
2180 if (kvm_pmu_msr(vcpu, msr))
2181 return kvm_pmu_set_msr(vcpu, msr_info);
2183 if (pr || data != 0)
2184 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2185 "0x%x data 0x%llx\n", msr, data);
2187 case MSR_K7_CLK_CTL:
2189 * Ignore all writes to this no longer documented MSR.
2190 * Writes are only relevant for old K7 processors,
2191 * all pre-dating SVM, but a recommended workaround from
2192 * AMD for these chips. It is possible to specify the
2193 * affected processor models on the command line, hence
2194 * the need to ignore the workaround.
2197 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2198 if (kvm_hv_msr_partition_wide(msr)) {
2200 mutex_lock(&vcpu->kvm->lock);
2201 r = set_msr_hyperv_pw(vcpu, msr, data);
2202 mutex_unlock(&vcpu->kvm->lock);
2205 return set_msr_hyperv(vcpu, msr, data);
2207 case MSR_IA32_BBL_CR_CTL3:
2208 /* Drop writes to this legacy MSR -- see rdmsr
2209 * counterpart for further detail.
2211 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2213 case MSR_AMD64_OSVW_ID_LENGTH:
2214 if (!guest_cpuid_has_osvw(vcpu))
2216 vcpu->arch.osvw.length = data;
2218 case MSR_AMD64_OSVW_STATUS:
2219 if (!guest_cpuid_has_osvw(vcpu))
2221 vcpu->arch.osvw.status = data;
2224 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2225 return xen_hvm_config(vcpu, data);
2226 if (kvm_pmu_msr(vcpu, msr))
2227 return kvm_pmu_set_msr(vcpu, msr_info);
2229 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2233 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2240 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2244 * Reads an msr value (of 'msr_index') into 'pdata'.
2245 * Returns 0 on success, non-0 otherwise.
2246 * Assumes vcpu_load() was already called.
2248 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2250 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2253 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2255 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2257 if (!msr_mtrr_valid(msr))
2260 if (msr == MSR_MTRRdefType)
2261 *pdata = vcpu->arch.mtrr_state.def_type +
2262 (vcpu->arch.mtrr_state.enabled << 10);
2263 else if (msr == MSR_MTRRfix64K_00000)
2265 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2266 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2267 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2268 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2269 else if (msr == MSR_IA32_CR_PAT)
2270 *pdata = vcpu->arch.pat;
2271 else { /* Variable MTRRs */
2272 int idx, is_mtrr_mask;
2275 idx = (msr - 0x200) / 2;
2276 is_mtrr_mask = msr - 0x200 - 2 * idx;
2279 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2282 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2289 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2292 u64 mcg_cap = vcpu->arch.mcg_cap;
2293 unsigned bank_num = mcg_cap & 0xff;
2296 case MSR_IA32_P5_MC_ADDR:
2297 case MSR_IA32_P5_MC_TYPE:
2300 case MSR_IA32_MCG_CAP:
2301 data = vcpu->arch.mcg_cap;
2303 case MSR_IA32_MCG_CTL:
2304 if (!(mcg_cap & MCG_CTL_P))
2306 data = vcpu->arch.mcg_ctl;
2308 case MSR_IA32_MCG_STATUS:
2309 data = vcpu->arch.mcg_status;
2312 if (msr >= MSR_IA32_MC0_CTL &&
2313 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2314 u32 offset = msr - MSR_IA32_MC0_CTL;
2315 data = vcpu->arch.mce_banks[offset];
2324 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2327 struct kvm *kvm = vcpu->kvm;
2330 case HV_X64_MSR_GUEST_OS_ID:
2331 data = kvm->arch.hv_guest_os_id;
2333 case HV_X64_MSR_HYPERCALL:
2334 data = kvm->arch.hv_hypercall;
2336 case HV_X64_MSR_TIME_REF_COUNT: {
2338 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2341 case HV_X64_MSR_REFERENCE_TSC:
2342 data = kvm->arch.hv_tsc_page;
2345 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2353 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2358 case HV_X64_MSR_VP_INDEX: {
2361 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2369 case HV_X64_MSR_EOI:
2370 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2371 case HV_X64_MSR_ICR:
2372 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2373 case HV_X64_MSR_TPR:
2374 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2375 case HV_X64_MSR_APIC_ASSIST_PAGE:
2376 data = vcpu->arch.hv_vapic;
2379 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2386 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2391 case MSR_IA32_PLATFORM_ID:
2392 case MSR_IA32_EBL_CR_POWERON:
2393 case MSR_IA32_DEBUGCTLMSR:
2394 case MSR_IA32_LASTBRANCHFROMIP:
2395 case MSR_IA32_LASTBRANCHTOIP:
2396 case MSR_IA32_LASTINTFROMIP:
2397 case MSR_IA32_LASTINTTOIP:
2400 case MSR_VM_HSAVE_PA:
2401 case MSR_K7_EVNTSEL0:
2402 case MSR_K7_PERFCTR0:
2403 case MSR_K8_INT_PENDING_MSG:
2404 case MSR_AMD64_NB_CFG:
2405 case MSR_FAM10H_MMIO_CONF_BASE:
2406 case MSR_AMD64_BU_CFG2:
2409 case MSR_P6_PERFCTR0:
2410 case MSR_P6_PERFCTR1:
2411 case MSR_P6_EVNTSEL0:
2412 case MSR_P6_EVNTSEL1:
2413 if (kvm_pmu_msr(vcpu, msr))
2414 return kvm_pmu_get_msr(vcpu, msr, pdata);
2417 case MSR_IA32_UCODE_REV:
2418 data = 0x100000000ULL;
2421 data = 0x500 | KVM_NR_VAR_MTRR;
2423 case 0x200 ... 0x2ff:
2424 return get_msr_mtrr(vcpu, msr, pdata);
2425 case 0xcd: /* fsb frequency */
2429 * MSR_EBC_FREQUENCY_ID
2430 * Conservative value valid for even the basic CPU models.
2431 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2432 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2433 * and 266MHz for model 3, or 4. Set Core Clock
2434 * Frequency to System Bus Frequency Ratio to 1 (bits
2435 * 31:24) even though these are only valid for CPU
2436 * models > 2, however guests may end up dividing or
2437 * multiplying by zero otherwise.
2439 case MSR_EBC_FREQUENCY_ID:
2442 case MSR_IA32_APICBASE:
2443 data = kvm_get_apic_base(vcpu);
2445 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2446 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2448 case MSR_IA32_TSCDEADLINE:
2449 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2451 case MSR_IA32_TSC_ADJUST:
2452 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2454 case MSR_IA32_MISC_ENABLE:
2455 data = vcpu->arch.ia32_misc_enable_msr;
2457 case MSR_IA32_PERF_STATUS:
2458 /* TSC increment by tick */
2460 /* CPU multiplier */
2461 data |= (((uint64_t)4ULL) << 40);
2464 data = vcpu->arch.efer;
2466 case MSR_KVM_WALL_CLOCK:
2467 case MSR_KVM_WALL_CLOCK_NEW:
2468 data = vcpu->kvm->arch.wall_clock;
2470 case MSR_KVM_SYSTEM_TIME:
2471 case MSR_KVM_SYSTEM_TIME_NEW:
2472 data = vcpu->arch.time;
2474 case MSR_KVM_ASYNC_PF_EN:
2475 data = vcpu->arch.apf.msr_val;
2477 case MSR_KVM_STEAL_TIME:
2478 data = vcpu->arch.st.msr_val;
2480 case MSR_KVM_PV_EOI_EN:
2481 data = vcpu->arch.pv_eoi.msr_val;
2483 case MSR_IA32_P5_MC_ADDR:
2484 case MSR_IA32_P5_MC_TYPE:
2485 case MSR_IA32_MCG_CAP:
2486 case MSR_IA32_MCG_CTL:
2487 case MSR_IA32_MCG_STATUS:
2488 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2489 return get_msr_mce(vcpu, msr, pdata);
2490 case MSR_K7_CLK_CTL:
2492 * Provide expected ramp-up count for K7. All other
2493 * are set to zero, indicating minimum divisors for
2496 * This prevents guest kernels on AMD host with CPU
2497 * type 6, model 8 and higher from exploding due to
2498 * the rdmsr failing.
2502 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2503 if (kvm_hv_msr_partition_wide(msr)) {
2505 mutex_lock(&vcpu->kvm->lock);
2506 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2507 mutex_unlock(&vcpu->kvm->lock);
2510 return get_msr_hyperv(vcpu, msr, pdata);
2512 case MSR_IA32_BBL_CR_CTL3:
2513 /* This legacy MSR exists but isn't fully documented in current
2514 * silicon. It is however accessed by winxp in very narrow
2515 * scenarios where it sets bit #19, itself documented as
2516 * a "reserved" bit. Best effort attempt to source coherent
2517 * read data here should the balance of the register be
2518 * interpreted by the guest:
2520 * L2 cache control register 3: 64GB range, 256KB size,
2521 * enabled, latency 0x1, configured
2525 case MSR_AMD64_OSVW_ID_LENGTH:
2526 if (!guest_cpuid_has_osvw(vcpu))
2528 data = vcpu->arch.osvw.length;
2530 case MSR_AMD64_OSVW_STATUS:
2531 if (!guest_cpuid_has_osvw(vcpu))
2533 data = vcpu->arch.osvw.status;
2536 if (kvm_pmu_msr(vcpu, msr))
2537 return kvm_pmu_get_msr(vcpu, msr, pdata);
2539 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2542 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2550 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2553 * Read or write a bunch of msrs. All parameters are kernel addresses.
2555 * @return number of msrs set successfully.
2557 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2558 struct kvm_msr_entry *entries,
2559 int (*do_msr)(struct kvm_vcpu *vcpu,
2560 unsigned index, u64 *data))
2564 idx = srcu_read_lock(&vcpu->kvm->srcu);
2565 for (i = 0; i < msrs->nmsrs; ++i)
2566 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2568 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2574 * Read or write a bunch of msrs. Parameters are user addresses.
2576 * @return number of msrs set successfully.
2578 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2579 int (*do_msr)(struct kvm_vcpu *vcpu,
2580 unsigned index, u64 *data),
2583 struct kvm_msrs msrs;
2584 struct kvm_msr_entry *entries;
2589 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2593 if (msrs.nmsrs >= MAX_IO_MSRS)
2596 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2597 entries = memdup_user(user_msrs->entries, size);
2598 if (IS_ERR(entries)) {
2599 r = PTR_ERR(entries);
2603 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2608 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2619 int kvm_dev_ioctl_check_extension(long ext)
2624 case KVM_CAP_IRQCHIP:
2626 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2627 case KVM_CAP_SET_TSS_ADDR:
2628 case KVM_CAP_EXT_CPUID:
2629 case KVM_CAP_EXT_EMUL_CPUID:
2630 case KVM_CAP_CLOCKSOURCE:
2632 case KVM_CAP_NOP_IO_DELAY:
2633 case KVM_CAP_MP_STATE:
2634 case KVM_CAP_SYNC_MMU:
2635 case KVM_CAP_USER_NMI:
2636 case KVM_CAP_REINJECT_CONTROL:
2637 case KVM_CAP_IRQ_INJECT_STATUS:
2639 case KVM_CAP_IOEVENTFD:
2640 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2642 case KVM_CAP_PIT_STATE2:
2643 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2644 case KVM_CAP_XEN_HVM:
2645 case KVM_CAP_ADJUST_CLOCK:
2646 case KVM_CAP_VCPU_EVENTS:
2647 case KVM_CAP_HYPERV:
2648 case KVM_CAP_HYPERV_VAPIC:
2649 case KVM_CAP_HYPERV_SPIN:
2650 case KVM_CAP_PCI_SEGMENT:
2651 case KVM_CAP_DEBUGREGS:
2652 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2654 case KVM_CAP_ASYNC_PF:
2655 case KVM_CAP_GET_TSC_KHZ:
2656 case KVM_CAP_KVMCLOCK_CTRL:
2657 case KVM_CAP_READONLY_MEM:
2658 case KVM_CAP_HYPERV_TIME:
2659 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2660 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2661 case KVM_CAP_ASSIGN_DEV_IRQ:
2662 case KVM_CAP_PCI_2_3:
2666 case KVM_CAP_COALESCED_MMIO:
2667 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2670 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2672 case KVM_CAP_NR_VCPUS:
2673 r = KVM_SOFT_MAX_VCPUS;
2675 case KVM_CAP_MAX_VCPUS:
2678 case KVM_CAP_NR_MEMSLOTS:
2679 r = KVM_USER_MEM_SLOTS;
2681 case KVM_CAP_PV_MMU: /* obsolete */
2684 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2686 r = iommu_present(&pci_bus_type);
2690 r = KVM_MAX_MCE_BANKS;
2695 case KVM_CAP_TSC_CONTROL:
2696 r = kvm_has_tsc_control;
2698 case KVM_CAP_TSC_DEADLINE_TIMER:
2699 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2709 long kvm_arch_dev_ioctl(struct file *filp,
2710 unsigned int ioctl, unsigned long arg)
2712 void __user *argp = (void __user *)arg;
2716 case KVM_GET_MSR_INDEX_LIST: {
2717 struct kvm_msr_list __user *user_msr_list = argp;
2718 struct kvm_msr_list msr_list;
2722 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2725 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2726 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2729 if (n < msr_list.nmsrs)
2732 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2733 num_msrs_to_save * sizeof(u32)))
2735 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2737 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2742 case KVM_GET_SUPPORTED_CPUID:
2743 case KVM_GET_EMULATED_CPUID: {
2744 struct kvm_cpuid2 __user *cpuid_arg = argp;
2745 struct kvm_cpuid2 cpuid;
2748 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2751 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2757 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2762 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2765 mce_cap = KVM_MCE_CAP_SUPPORTED;
2767 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2779 static void wbinvd_ipi(void *garbage)
2784 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2786 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2789 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2791 /* Address WBINVD may be executed by guest */
2792 if (need_emulate_wbinvd(vcpu)) {
2793 if (kvm_x86_ops->has_wbinvd_exit())
2794 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2795 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2796 smp_call_function_single(vcpu->cpu,
2797 wbinvd_ipi, NULL, 1);
2800 kvm_x86_ops->vcpu_load(vcpu, cpu);
2802 /* Apply any externally detected TSC adjustments (due to suspend) */
2803 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2804 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2805 vcpu->arch.tsc_offset_adjustment = 0;
2806 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2809 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2810 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2811 native_read_tsc() - vcpu->arch.last_host_tsc;
2813 mark_tsc_unstable("KVM discovered backwards TSC");
2814 if (check_tsc_unstable()) {
2815 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2816 vcpu->arch.last_guest_tsc);
2817 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2818 vcpu->arch.tsc_catchup = 1;
2821 * On a host with synchronized TSC, there is no need to update
2822 * kvmclock on vcpu->cpu migration
2824 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2825 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2826 if (vcpu->cpu != cpu)
2827 kvm_migrate_timers(vcpu);
2831 accumulate_steal_time(vcpu);
2832 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2835 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2837 kvm_x86_ops->vcpu_put(vcpu);
2838 kvm_put_guest_fpu(vcpu);
2839 vcpu->arch.last_host_tsc = native_read_tsc();
2842 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2843 struct kvm_lapic_state *s)
2845 kvm_x86_ops->sync_pir_to_irr(vcpu);
2846 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2851 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2852 struct kvm_lapic_state *s)
2854 kvm_apic_post_state_restore(vcpu, s);
2855 update_cr8_intercept(vcpu);
2860 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2861 struct kvm_interrupt *irq)
2863 if (irq->irq >= KVM_NR_INTERRUPTS)
2865 if (irqchip_in_kernel(vcpu->kvm))
2868 kvm_queue_interrupt(vcpu, irq->irq, false);
2869 kvm_make_request(KVM_REQ_EVENT, vcpu);
2874 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2876 kvm_inject_nmi(vcpu);
2881 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2882 struct kvm_tpr_access_ctl *tac)
2886 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2890 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2894 unsigned bank_num = mcg_cap & 0xff, bank;
2897 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2899 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2902 vcpu->arch.mcg_cap = mcg_cap;
2903 /* Init IA32_MCG_CTL to all 1s */
2904 if (mcg_cap & MCG_CTL_P)
2905 vcpu->arch.mcg_ctl = ~(u64)0;
2906 /* Init IA32_MCi_CTL to all 1s */
2907 for (bank = 0; bank < bank_num; bank++)
2908 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2913 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2914 struct kvm_x86_mce *mce)
2916 u64 mcg_cap = vcpu->arch.mcg_cap;
2917 unsigned bank_num = mcg_cap & 0xff;
2918 u64 *banks = vcpu->arch.mce_banks;
2920 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2923 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2924 * reporting is disabled
2926 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2927 vcpu->arch.mcg_ctl != ~(u64)0)
2929 banks += 4 * mce->bank;
2931 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2932 * reporting is disabled for the bank
2934 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2936 if (mce->status & MCI_STATUS_UC) {
2937 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2938 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2939 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2942 if (banks[1] & MCI_STATUS_VAL)
2943 mce->status |= MCI_STATUS_OVER;
2944 banks[2] = mce->addr;
2945 banks[3] = mce->misc;
2946 vcpu->arch.mcg_status = mce->mcg_status;
2947 banks[1] = mce->status;
2948 kvm_queue_exception(vcpu, MC_VECTOR);
2949 } else if (!(banks[1] & MCI_STATUS_VAL)
2950 || !(banks[1] & MCI_STATUS_UC)) {
2951 if (banks[1] & MCI_STATUS_VAL)
2952 mce->status |= MCI_STATUS_OVER;
2953 banks[2] = mce->addr;
2954 banks[3] = mce->misc;
2955 banks[1] = mce->status;
2957 banks[1] |= MCI_STATUS_OVER;
2961 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2962 struct kvm_vcpu_events *events)
2965 events->exception.injected =
2966 vcpu->arch.exception.pending &&
2967 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2968 events->exception.nr = vcpu->arch.exception.nr;
2969 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2970 events->exception.pad = 0;
2971 events->exception.error_code = vcpu->arch.exception.error_code;
2973 events->interrupt.injected =
2974 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2975 events->interrupt.nr = vcpu->arch.interrupt.nr;
2976 events->interrupt.soft = 0;
2977 events->interrupt.shadow =
2978 kvm_x86_ops->get_interrupt_shadow(vcpu,
2979 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2981 events->nmi.injected = vcpu->arch.nmi_injected;
2982 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2983 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2984 events->nmi.pad = 0;
2986 events->sipi_vector = 0; /* never valid when reporting to user space */
2988 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2989 | KVM_VCPUEVENT_VALID_SHADOW);
2990 memset(&events->reserved, 0, sizeof(events->reserved));
2993 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2994 struct kvm_vcpu_events *events)
2996 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2997 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2998 | KVM_VCPUEVENT_VALID_SHADOW))
3002 vcpu->arch.exception.pending = events->exception.injected;
3003 vcpu->arch.exception.nr = events->exception.nr;
3004 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3005 vcpu->arch.exception.error_code = events->exception.error_code;
3007 vcpu->arch.interrupt.pending = events->interrupt.injected;
3008 vcpu->arch.interrupt.nr = events->interrupt.nr;
3009 vcpu->arch.interrupt.soft = events->interrupt.soft;
3010 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3011 kvm_x86_ops->set_interrupt_shadow(vcpu,
3012 events->interrupt.shadow);
3014 vcpu->arch.nmi_injected = events->nmi.injected;
3015 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3016 vcpu->arch.nmi_pending = events->nmi.pending;
3017 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3019 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3020 kvm_vcpu_has_lapic(vcpu))
3021 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3023 kvm_make_request(KVM_REQ_EVENT, vcpu);
3028 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3029 struct kvm_debugregs *dbgregs)
3033 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3034 _kvm_get_dr(vcpu, 6, &val);
3036 dbgregs->dr7 = vcpu->arch.dr7;
3038 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3041 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3042 struct kvm_debugregs *dbgregs)
3047 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3048 vcpu->arch.dr6 = dbgregs->dr6;
3049 kvm_update_dr6(vcpu);
3050 vcpu->arch.dr7 = dbgregs->dr7;
3051 kvm_update_dr7(vcpu);
3056 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3057 struct kvm_xsave *guest_xsave)
3059 if (cpu_has_xsave) {
3060 memcpy(guest_xsave->region,
3061 &vcpu->arch.guest_fpu.state->xsave,
3062 vcpu->arch.guest_xstate_size);
3063 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3064 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3066 memcpy(guest_xsave->region,
3067 &vcpu->arch.guest_fpu.state->fxsave,
3068 sizeof(struct i387_fxsave_struct));
3069 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3074 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3075 struct kvm_xsave *guest_xsave)
3078 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3080 if (cpu_has_xsave) {
3082 * Here we allow setting states that are not present in
3083 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3084 * with old userspace.
3086 if (xstate_bv & ~kvm_supported_xcr0())
3088 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3089 guest_xsave->region, vcpu->arch.guest_xstate_size);
3091 if (xstate_bv & ~XSTATE_FPSSE)
3093 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3094 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3099 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3100 struct kvm_xcrs *guest_xcrs)
3102 if (!cpu_has_xsave) {
3103 guest_xcrs->nr_xcrs = 0;
3107 guest_xcrs->nr_xcrs = 1;
3108 guest_xcrs->flags = 0;
3109 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3110 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3113 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3114 struct kvm_xcrs *guest_xcrs)
3121 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3124 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3125 /* Only support XCR0 currently */
3126 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3127 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3128 guest_xcrs->xcrs[i].value);
3137 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3138 * stopped by the hypervisor. This function will be called from the host only.
3139 * EINVAL is returned when the host attempts to set the flag for a guest that
3140 * does not support pv clocks.
3142 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3144 if (!vcpu->arch.pv_time_enabled)
3146 vcpu->arch.pvclock_set_guest_stopped_request = true;
3147 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3151 long kvm_arch_vcpu_ioctl(struct file *filp,
3152 unsigned int ioctl, unsigned long arg)
3154 struct kvm_vcpu *vcpu = filp->private_data;
3155 void __user *argp = (void __user *)arg;
3158 struct kvm_lapic_state *lapic;
3159 struct kvm_xsave *xsave;
3160 struct kvm_xcrs *xcrs;
3166 case KVM_GET_LAPIC: {
3168 if (!vcpu->arch.apic)
3170 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3175 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3179 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3184 case KVM_SET_LAPIC: {
3186 if (!vcpu->arch.apic)
3188 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3189 if (IS_ERR(u.lapic))
3190 return PTR_ERR(u.lapic);
3192 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3195 case KVM_INTERRUPT: {
3196 struct kvm_interrupt irq;
3199 if (copy_from_user(&irq, argp, sizeof irq))
3201 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3205 r = kvm_vcpu_ioctl_nmi(vcpu);
3208 case KVM_SET_CPUID: {
3209 struct kvm_cpuid __user *cpuid_arg = argp;
3210 struct kvm_cpuid cpuid;
3213 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3215 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3218 case KVM_SET_CPUID2: {
3219 struct kvm_cpuid2 __user *cpuid_arg = argp;
3220 struct kvm_cpuid2 cpuid;
3223 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3225 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3226 cpuid_arg->entries);
3229 case KVM_GET_CPUID2: {
3230 struct kvm_cpuid2 __user *cpuid_arg = argp;
3231 struct kvm_cpuid2 cpuid;
3234 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3236 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3237 cpuid_arg->entries);
3241 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3247 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3250 r = msr_io(vcpu, argp, do_set_msr, 0);
3252 case KVM_TPR_ACCESS_REPORTING: {
3253 struct kvm_tpr_access_ctl tac;
3256 if (copy_from_user(&tac, argp, sizeof tac))
3258 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3262 if (copy_to_user(argp, &tac, sizeof tac))
3267 case KVM_SET_VAPIC_ADDR: {
3268 struct kvm_vapic_addr va;
3271 if (!irqchip_in_kernel(vcpu->kvm))
3274 if (copy_from_user(&va, argp, sizeof va))
3276 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3279 case KVM_X86_SETUP_MCE: {
3283 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3285 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3288 case KVM_X86_SET_MCE: {
3289 struct kvm_x86_mce mce;
3292 if (copy_from_user(&mce, argp, sizeof mce))
3294 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3297 case KVM_GET_VCPU_EVENTS: {
3298 struct kvm_vcpu_events events;
3300 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3303 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3308 case KVM_SET_VCPU_EVENTS: {
3309 struct kvm_vcpu_events events;
3312 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3315 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3318 case KVM_GET_DEBUGREGS: {
3319 struct kvm_debugregs dbgregs;
3321 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3324 if (copy_to_user(argp, &dbgregs,
3325 sizeof(struct kvm_debugregs)))
3330 case KVM_SET_DEBUGREGS: {
3331 struct kvm_debugregs dbgregs;
3334 if (copy_from_user(&dbgregs, argp,
3335 sizeof(struct kvm_debugregs)))
3338 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3341 case KVM_GET_XSAVE: {
3342 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3347 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3350 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3355 case KVM_SET_XSAVE: {
3356 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3357 if (IS_ERR(u.xsave))
3358 return PTR_ERR(u.xsave);
3360 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3363 case KVM_GET_XCRS: {
3364 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3369 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3372 if (copy_to_user(argp, u.xcrs,
3373 sizeof(struct kvm_xcrs)))
3378 case KVM_SET_XCRS: {
3379 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3381 return PTR_ERR(u.xcrs);
3383 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3386 case KVM_SET_TSC_KHZ: {
3390 user_tsc_khz = (u32)arg;
3392 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3395 if (user_tsc_khz == 0)
3396 user_tsc_khz = tsc_khz;
3398 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3403 case KVM_GET_TSC_KHZ: {
3404 r = vcpu->arch.virtual_tsc_khz;
3407 case KVM_KVMCLOCK_CTRL: {
3408 r = kvm_set_guest_paused(vcpu);
3419 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3421 return VM_FAULT_SIGBUS;
3424 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3428 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3430 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3434 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3437 kvm->arch.ept_identity_map_addr = ident_addr;
3441 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3442 u32 kvm_nr_mmu_pages)
3444 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3447 mutex_lock(&kvm->slots_lock);
3449 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3450 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3452 mutex_unlock(&kvm->slots_lock);
3456 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3458 return kvm->arch.n_max_mmu_pages;
3461 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3466 switch (chip->chip_id) {
3467 case KVM_IRQCHIP_PIC_MASTER:
3468 memcpy(&chip->chip.pic,
3469 &pic_irqchip(kvm)->pics[0],
3470 sizeof(struct kvm_pic_state));
3472 case KVM_IRQCHIP_PIC_SLAVE:
3473 memcpy(&chip->chip.pic,
3474 &pic_irqchip(kvm)->pics[1],
3475 sizeof(struct kvm_pic_state));
3477 case KVM_IRQCHIP_IOAPIC:
3478 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3487 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3492 switch (chip->chip_id) {
3493 case KVM_IRQCHIP_PIC_MASTER:
3494 spin_lock(&pic_irqchip(kvm)->lock);
3495 memcpy(&pic_irqchip(kvm)->pics[0],
3497 sizeof(struct kvm_pic_state));
3498 spin_unlock(&pic_irqchip(kvm)->lock);
3500 case KVM_IRQCHIP_PIC_SLAVE:
3501 spin_lock(&pic_irqchip(kvm)->lock);
3502 memcpy(&pic_irqchip(kvm)->pics[1],
3504 sizeof(struct kvm_pic_state));
3505 spin_unlock(&pic_irqchip(kvm)->lock);
3507 case KVM_IRQCHIP_IOAPIC:
3508 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3514 kvm_pic_update_irq(pic_irqchip(kvm));
3518 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3522 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3523 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3524 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3528 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3532 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3533 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3534 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3535 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3539 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3543 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3544 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3545 sizeof(ps->channels));
3546 ps->flags = kvm->arch.vpit->pit_state.flags;
3547 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3548 memset(&ps->reserved, 0, sizeof(ps->reserved));
3552 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3554 int r = 0, start = 0;
3555 u32 prev_legacy, cur_legacy;
3556 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3557 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3558 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3559 if (!prev_legacy && cur_legacy)
3561 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3562 sizeof(kvm->arch.vpit->pit_state.channels));
3563 kvm->arch.vpit->pit_state.flags = ps->flags;
3564 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3565 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3569 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3570 struct kvm_reinject_control *control)
3572 if (!kvm->arch.vpit)
3574 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3575 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3576 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3581 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3582 * @kvm: kvm instance
3583 * @log: slot id and address to which we copy the log
3585 * We need to keep it in mind that VCPU threads can write to the bitmap
3586 * concurrently. So, to avoid losing data, we keep the following order for
3589 * 1. Take a snapshot of the bit and clear it if needed.
3590 * 2. Write protect the corresponding page.
3591 * 3. Flush TLB's if needed.
3592 * 4. Copy the snapshot to the userspace.
3594 * Between 2 and 3, the guest may write to the page using the remaining TLB
3595 * entry. This is not a problem because the page will be reported dirty at
3596 * step 4 using the snapshot taken before and step 3 ensures that successive
3597 * writes will be logged for the next call.
3599 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3602 struct kvm_memory_slot *memslot;
3604 unsigned long *dirty_bitmap;
3605 unsigned long *dirty_bitmap_buffer;
3606 bool is_dirty = false;
3608 mutex_lock(&kvm->slots_lock);
3611 if (log->slot >= KVM_USER_MEM_SLOTS)
3614 memslot = id_to_memslot(kvm->memslots, log->slot);
3616 dirty_bitmap = memslot->dirty_bitmap;
3621 n = kvm_dirty_bitmap_bytes(memslot);
3623 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3624 memset(dirty_bitmap_buffer, 0, n);
3626 spin_lock(&kvm->mmu_lock);
3628 for (i = 0; i < n / sizeof(long); i++) {
3632 if (!dirty_bitmap[i])
3637 mask = xchg(&dirty_bitmap[i], 0);
3638 dirty_bitmap_buffer[i] = mask;
3640 offset = i * BITS_PER_LONG;
3641 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3644 spin_unlock(&kvm->mmu_lock);
3646 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3647 lockdep_assert_held(&kvm->slots_lock);
3650 * All the TLBs can be flushed out of mmu lock, see the comments in
3651 * kvm_mmu_slot_remove_write_access().
3654 kvm_flush_remote_tlbs(kvm);
3657 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3662 mutex_unlock(&kvm->slots_lock);
3666 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3669 if (!irqchip_in_kernel(kvm))
3672 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3673 irq_event->irq, irq_event->level,
3678 long kvm_arch_vm_ioctl(struct file *filp,
3679 unsigned int ioctl, unsigned long arg)
3681 struct kvm *kvm = filp->private_data;
3682 void __user *argp = (void __user *)arg;
3685 * This union makes it completely explicit to gcc-3.x
3686 * that these two variables' stack usage should be
3687 * combined, not added together.
3690 struct kvm_pit_state ps;
3691 struct kvm_pit_state2 ps2;
3692 struct kvm_pit_config pit_config;
3696 case KVM_SET_TSS_ADDR:
3697 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3699 case KVM_SET_IDENTITY_MAP_ADDR: {
3703 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3705 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3708 case KVM_SET_NR_MMU_PAGES:
3709 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3711 case KVM_GET_NR_MMU_PAGES:
3712 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3714 case KVM_CREATE_IRQCHIP: {
3715 struct kvm_pic *vpic;
3717 mutex_lock(&kvm->lock);
3720 goto create_irqchip_unlock;
3722 if (atomic_read(&kvm->online_vcpus))
3723 goto create_irqchip_unlock;
3725 vpic = kvm_create_pic(kvm);
3727 r = kvm_ioapic_init(kvm);
3729 mutex_lock(&kvm->slots_lock);
3730 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3732 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3734 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3736 mutex_unlock(&kvm->slots_lock);
3738 goto create_irqchip_unlock;
3741 goto create_irqchip_unlock;
3743 kvm->arch.vpic = vpic;
3745 r = kvm_setup_default_irq_routing(kvm);
3747 mutex_lock(&kvm->slots_lock);
3748 mutex_lock(&kvm->irq_lock);
3749 kvm_ioapic_destroy(kvm);
3750 kvm_destroy_pic(kvm);
3751 mutex_unlock(&kvm->irq_lock);
3752 mutex_unlock(&kvm->slots_lock);
3754 create_irqchip_unlock:
3755 mutex_unlock(&kvm->lock);
3758 case KVM_CREATE_PIT:
3759 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3761 case KVM_CREATE_PIT2:
3763 if (copy_from_user(&u.pit_config, argp,
3764 sizeof(struct kvm_pit_config)))
3767 mutex_lock(&kvm->slots_lock);
3770 goto create_pit_unlock;
3772 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3776 mutex_unlock(&kvm->slots_lock);
3778 case KVM_GET_IRQCHIP: {
3779 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3780 struct kvm_irqchip *chip;
3782 chip = memdup_user(argp, sizeof(*chip));
3789 if (!irqchip_in_kernel(kvm))
3790 goto get_irqchip_out;
3791 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3793 goto get_irqchip_out;
3795 if (copy_to_user(argp, chip, sizeof *chip))
3796 goto get_irqchip_out;
3802 case KVM_SET_IRQCHIP: {
3803 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3804 struct kvm_irqchip *chip;
3806 chip = memdup_user(argp, sizeof(*chip));
3813 if (!irqchip_in_kernel(kvm))
3814 goto set_irqchip_out;
3815 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3817 goto set_irqchip_out;
3825 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3828 if (!kvm->arch.vpit)
3830 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3834 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3841 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3844 if (!kvm->arch.vpit)
3846 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3849 case KVM_GET_PIT2: {
3851 if (!kvm->arch.vpit)
3853 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3857 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3862 case KVM_SET_PIT2: {
3864 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3867 if (!kvm->arch.vpit)
3869 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3872 case KVM_REINJECT_CONTROL: {
3873 struct kvm_reinject_control control;
3875 if (copy_from_user(&control, argp, sizeof(control)))
3877 r = kvm_vm_ioctl_reinject(kvm, &control);
3880 case KVM_XEN_HVM_CONFIG: {
3882 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3883 sizeof(struct kvm_xen_hvm_config)))
3886 if (kvm->arch.xen_hvm_config.flags)
3891 case KVM_SET_CLOCK: {
3892 struct kvm_clock_data user_ns;
3897 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3905 local_irq_disable();
3906 now_ns = get_kernel_ns();
3907 delta = user_ns.clock - now_ns;
3909 kvm->arch.kvmclock_offset = delta;
3910 kvm_gen_update_masterclock(kvm);
3913 case KVM_GET_CLOCK: {
3914 struct kvm_clock_data user_ns;
3917 local_irq_disable();
3918 now_ns = get_kernel_ns();
3919 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3922 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3925 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3938 static void kvm_init_msr_list(void)
3943 /* skip the first msrs in the list. KVM-specific */
3944 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3945 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3949 * Even MSRs that are valid in the host may not be exposed
3950 * to the guests in some cases. We could work around this
3951 * in VMX with the generic MSR save/load machinery, but it
3952 * is not really worthwhile since it will really only
3953 * happen with nested virtualization.
3955 switch (msrs_to_save[i]) {
3956 case MSR_IA32_BNDCFGS:
3957 if (!kvm_x86_ops->mpx_supported())
3965 msrs_to_save[j] = msrs_to_save[i];
3968 num_msrs_to_save = j;
3971 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3979 if (!(vcpu->arch.apic &&
3980 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3981 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3992 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3999 if (!(vcpu->arch.apic &&
4000 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4001 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4003 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4013 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4014 struct kvm_segment *var, int seg)
4016 kvm_x86_ops->set_segment(vcpu, var, seg);
4019 void kvm_get_segment(struct kvm_vcpu *vcpu,
4020 struct kvm_segment *var, int seg)
4022 kvm_x86_ops->get_segment(vcpu, var, seg);
4025 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
4028 struct x86_exception exception;
4030 BUG_ON(!mmu_is_nested(vcpu));
4032 /* NPT walks are always user-walks */
4033 access |= PFERR_USER_MASK;
4034 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
4039 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4040 struct x86_exception *exception)
4042 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4043 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4046 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4047 struct x86_exception *exception)
4049 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4050 access |= PFERR_FETCH_MASK;
4051 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4054 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4055 struct x86_exception *exception)
4057 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4058 access |= PFERR_WRITE_MASK;
4059 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4062 /* uses this to access any guest's mapped memory without checking CPL */
4063 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4064 struct x86_exception *exception)
4066 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4069 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4070 struct kvm_vcpu *vcpu, u32 access,
4071 struct x86_exception *exception)
4074 int r = X86EMUL_CONTINUE;
4077 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4079 unsigned offset = addr & (PAGE_SIZE-1);
4080 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4083 if (gpa == UNMAPPED_GVA)
4084 return X86EMUL_PROPAGATE_FAULT;
4085 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4087 r = X86EMUL_IO_NEEDED;
4099 /* used for instruction fetching */
4100 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4101 gva_t addr, void *val, unsigned int bytes,
4102 struct x86_exception *exception)
4104 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4105 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4107 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4108 access | PFERR_FETCH_MASK,
4112 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4113 gva_t addr, void *val, unsigned int bytes,
4114 struct x86_exception *exception)
4116 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4117 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4119 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4122 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4124 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4125 gva_t addr, void *val, unsigned int bytes,
4126 struct x86_exception *exception)
4128 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4129 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4132 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4133 gva_t addr, void *val,
4135 struct x86_exception *exception)
4137 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4139 int r = X86EMUL_CONTINUE;
4142 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4145 unsigned offset = addr & (PAGE_SIZE-1);
4146 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4149 if (gpa == UNMAPPED_GVA)
4150 return X86EMUL_PROPAGATE_FAULT;
4151 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4153 r = X86EMUL_IO_NEEDED;
4164 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4166 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4167 gpa_t *gpa, struct x86_exception *exception,
4170 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4171 | (write ? PFERR_WRITE_MASK : 0);
4173 if (vcpu_match_mmio_gva(vcpu, gva)
4174 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4175 vcpu->arch.access, access)) {
4176 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4177 (gva & (PAGE_SIZE - 1));
4178 trace_vcpu_match_mmio(gva, *gpa, write, false);
4182 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4184 if (*gpa == UNMAPPED_GVA)
4187 /* For APIC access vmexit */
4188 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4191 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4192 trace_vcpu_match_mmio(gva, *gpa, write, true);
4199 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4200 const void *val, int bytes)
4204 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4207 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4211 struct read_write_emulator_ops {
4212 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4214 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4215 void *val, int bytes);
4216 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4217 int bytes, void *val);
4218 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4219 void *val, int bytes);
4223 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4225 if (vcpu->mmio_read_completed) {
4226 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4227 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4228 vcpu->mmio_read_completed = 0;
4235 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4236 void *val, int bytes)
4238 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4241 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4242 void *val, int bytes)
4244 return emulator_write_phys(vcpu, gpa, val, bytes);
4247 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4249 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4250 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4253 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4254 void *val, int bytes)
4256 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4257 return X86EMUL_IO_NEEDED;
4260 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4261 void *val, int bytes)
4263 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4265 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4266 return X86EMUL_CONTINUE;
4269 static const struct read_write_emulator_ops read_emultor = {
4270 .read_write_prepare = read_prepare,
4271 .read_write_emulate = read_emulate,
4272 .read_write_mmio = vcpu_mmio_read,
4273 .read_write_exit_mmio = read_exit_mmio,
4276 static const struct read_write_emulator_ops write_emultor = {
4277 .read_write_emulate = write_emulate,
4278 .read_write_mmio = write_mmio,
4279 .read_write_exit_mmio = write_exit_mmio,
4283 static int emulator_read_write_onepage(unsigned long addr, void *val,
4285 struct x86_exception *exception,
4286 struct kvm_vcpu *vcpu,
4287 const struct read_write_emulator_ops *ops)
4291 bool write = ops->write;
4292 struct kvm_mmio_fragment *frag;
4294 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4297 return X86EMUL_PROPAGATE_FAULT;
4299 /* For APIC access vmexit */
4303 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4304 return X86EMUL_CONTINUE;
4308 * Is this MMIO handled locally?
4310 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4311 if (handled == bytes)
4312 return X86EMUL_CONTINUE;
4318 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4319 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4323 return X86EMUL_CONTINUE;
4326 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4327 void *val, unsigned int bytes,
4328 struct x86_exception *exception,
4329 const struct read_write_emulator_ops *ops)
4331 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4335 if (ops->read_write_prepare &&
4336 ops->read_write_prepare(vcpu, val, bytes))
4337 return X86EMUL_CONTINUE;
4339 vcpu->mmio_nr_fragments = 0;
4341 /* Crossing a page boundary? */
4342 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4345 now = -addr & ~PAGE_MASK;
4346 rc = emulator_read_write_onepage(addr, val, now, exception,
4349 if (rc != X86EMUL_CONTINUE)
4356 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4358 if (rc != X86EMUL_CONTINUE)
4361 if (!vcpu->mmio_nr_fragments)
4364 gpa = vcpu->mmio_fragments[0].gpa;
4366 vcpu->mmio_needed = 1;
4367 vcpu->mmio_cur_fragment = 0;
4369 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4370 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4371 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4372 vcpu->run->mmio.phys_addr = gpa;
4374 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4377 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4381 struct x86_exception *exception)
4383 return emulator_read_write(ctxt, addr, val, bytes,
4384 exception, &read_emultor);
4387 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4391 struct x86_exception *exception)
4393 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4394 exception, &write_emultor);
4397 #define CMPXCHG_TYPE(t, ptr, old, new) \
4398 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4400 #ifdef CONFIG_X86_64
4401 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4403 # define CMPXCHG64(ptr, old, new) \
4404 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4407 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4412 struct x86_exception *exception)
4414 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4420 /* guests cmpxchg8b have to be emulated atomically */
4421 if (bytes > 8 || (bytes & (bytes - 1)))
4424 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4426 if (gpa == UNMAPPED_GVA ||
4427 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4430 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4433 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4434 if (is_error_page(page))
4437 kaddr = kmap_atomic(page);
4438 kaddr += offset_in_page(gpa);
4441 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4444 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4447 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4450 exchanged = CMPXCHG64(kaddr, old, new);
4455 kunmap_atomic(kaddr);
4456 kvm_release_page_dirty(page);
4459 return X86EMUL_CMPXCHG_FAILED;
4461 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4462 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4464 return X86EMUL_CONTINUE;
4467 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4469 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4472 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4474 /* TODO: String I/O for in kernel device */
4477 if (vcpu->arch.pio.in)
4478 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4479 vcpu->arch.pio.size, pd);
4481 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4482 vcpu->arch.pio.port, vcpu->arch.pio.size,
4487 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4488 unsigned short port, void *val,
4489 unsigned int count, bool in)
4491 vcpu->arch.pio.port = port;
4492 vcpu->arch.pio.in = in;
4493 vcpu->arch.pio.count = count;
4494 vcpu->arch.pio.size = size;
4496 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4497 vcpu->arch.pio.count = 0;
4501 vcpu->run->exit_reason = KVM_EXIT_IO;
4502 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4503 vcpu->run->io.size = size;
4504 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4505 vcpu->run->io.count = count;
4506 vcpu->run->io.port = port;
4511 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4512 int size, unsigned short port, void *val,
4515 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4518 if (vcpu->arch.pio.count)
4521 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4524 memcpy(val, vcpu->arch.pio_data, size * count);
4525 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4526 vcpu->arch.pio.count = 0;
4533 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4534 int size, unsigned short port,
4535 const void *val, unsigned int count)
4537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4539 memcpy(vcpu->arch.pio_data, val, size * count);
4540 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4541 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4544 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4546 return kvm_x86_ops->get_segment_base(vcpu, seg);
4549 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4551 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4554 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4556 if (!need_emulate_wbinvd(vcpu))
4557 return X86EMUL_CONTINUE;
4559 if (kvm_x86_ops->has_wbinvd_exit()) {
4560 int cpu = get_cpu();
4562 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4563 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4564 wbinvd_ipi, NULL, 1);
4566 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4569 return X86EMUL_CONTINUE;
4571 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4573 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4575 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4578 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4580 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4583 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4586 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4589 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4591 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4594 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4596 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4597 unsigned long value;
4601 value = kvm_read_cr0(vcpu);
4604 value = vcpu->arch.cr2;
4607 value = kvm_read_cr3(vcpu);
4610 value = kvm_read_cr4(vcpu);
4613 value = kvm_get_cr8(vcpu);
4616 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4623 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4625 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4630 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4633 vcpu->arch.cr2 = val;
4636 res = kvm_set_cr3(vcpu, val);
4639 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4642 res = kvm_set_cr8(vcpu, val);
4645 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4652 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4654 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4657 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4659 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4662 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4664 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4667 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4669 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4672 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4674 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4677 static unsigned long emulator_get_cached_segment_base(
4678 struct x86_emulate_ctxt *ctxt, int seg)
4680 return get_segment_base(emul_to_vcpu(ctxt), seg);
4683 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4684 struct desc_struct *desc, u32 *base3,
4687 struct kvm_segment var;
4689 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4690 *selector = var.selector;
4693 memset(desc, 0, sizeof(*desc));
4699 set_desc_limit(desc, var.limit);
4700 set_desc_base(desc, (unsigned long)var.base);
4701 #ifdef CONFIG_X86_64
4703 *base3 = var.base >> 32;
4705 desc->type = var.type;
4707 desc->dpl = var.dpl;
4708 desc->p = var.present;
4709 desc->avl = var.avl;
4717 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4718 struct desc_struct *desc, u32 base3,
4721 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4722 struct kvm_segment var;
4724 var.selector = selector;
4725 var.base = get_desc_base(desc);
4726 #ifdef CONFIG_X86_64
4727 var.base |= ((u64)base3) << 32;
4729 var.limit = get_desc_limit(desc);
4731 var.limit = (var.limit << 12) | 0xfff;
4732 var.type = desc->type;
4733 var.present = desc->p;
4734 var.dpl = desc->dpl;
4739 var.avl = desc->avl;
4740 var.present = desc->p;
4741 var.unusable = !var.present;
4744 kvm_set_segment(vcpu, &var, seg);
4748 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4749 u32 msr_index, u64 *pdata)
4751 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4754 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4755 u32 msr_index, u64 data)
4757 struct msr_data msr;
4760 msr.index = msr_index;
4761 msr.host_initiated = false;
4762 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4765 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4766 u32 pmc, u64 *pdata)
4768 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4771 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4773 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4776 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4779 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4781 * CR0.TS may reference the host fpu state, not the guest fpu state,
4782 * so it may be clear at this point.
4787 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4792 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4793 struct x86_instruction_info *info,
4794 enum x86_intercept_stage stage)
4796 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4799 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4800 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4802 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4805 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4807 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4810 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4812 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4815 static const struct x86_emulate_ops emulate_ops = {
4816 .read_gpr = emulator_read_gpr,
4817 .write_gpr = emulator_write_gpr,
4818 .read_std = kvm_read_guest_virt_system,
4819 .write_std = kvm_write_guest_virt_system,
4820 .fetch = kvm_fetch_guest_virt,
4821 .read_emulated = emulator_read_emulated,
4822 .write_emulated = emulator_write_emulated,
4823 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4824 .invlpg = emulator_invlpg,
4825 .pio_in_emulated = emulator_pio_in_emulated,
4826 .pio_out_emulated = emulator_pio_out_emulated,
4827 .get_segment = emulator_get_segment,
4828 .set_segment = emulator_set_segment,
4829 .get_cached_segment_base = emulator_get_cached_segment_base,
4830 .get_gdt = emulator_get_gdt,
4831 .get_idt = emulator_get_idt,
4832 .set_gdt = emulator_set_gdt,
4833 .set_idt = emulator_set_idt,
4834 .get_cr = emulator_get_cr,
4835 .set_cr = emulator_set_cr,
4836 .cpl = emulator_get_cpl,
4837 .get_dr = emulator_get_dr,
4838 .set_dr = emulator_set_dr,
4839 .set_msr = emulator_set_msr,
4840 .get_msr = emulator_get_msr,
4841 .read_pmc = emulator_read_pmc,
4842 .halt = emulator_halt,
4843 .wbinvd = emulator_wbinvd,
4844 .fix_hypercall = emulator_fix_hypercall,
4845 .get_fpu = emulator_get_fpu,
4846 .put_fpu = emulator_put_fpu,
4847 .intercept = emulator_intercept,
4848 .get_cpuid = emulator_get_cpuid,
4851 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4853 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4855 * an sti; sti; sequence only disable interrupts for the first
4856 * instruction. So, if the last instruction, be it emulated or
4857 * not, left the system with the INT_STI flag enabled, it
4858 * means that the last instruction is an sti. We should not
4859 * leave the flag on in this case. The same goes for mov ss
4861 if (!(int_shadow & mask))
4862 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4865 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4867 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4868 if (ctxt->exception.vector == PF_VECTOR)
4869 kvm_propagate_fault(vcpu, &ctxt->exception);
4870 else if (ctxt->exception.error_code_valid)
4871 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4872 ctxt->exception.error_code);
4874 kvm_queue_exception(vcpu, ctxt->exception.vector);
4877 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4879 memset(&ctxt->opcode_len, 0,
4880 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4882 ctxt->fetch.start = 0;
4883 ctxt->fetch.end = 0;
4884 ctxt->io_read.pos = 0;
4885 ctxt->io_read.end = 0;
4886 ctxt->mem_read.pos = 0;
4887 ctxt->mem_read.end = 0;
4890 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4892 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4895 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4897 ctxt->eflags = kvm_get_rflags(vcpu);
4898 ctxt->eip = kvm_rip_read(vcpu);
4899 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4900 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4901 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
4902 cs_db ? X86EMUL_MODE_PROT32 :
4903 X86EMUL_MODE_PROT16;
4904 ctxt->guest_mode = is_guest_mode(vcpu);
4906 init_decode_cache(ctxt);
4907 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4910 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4912 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4915 init_emulate_ctxt(vcpu);
4919 ctxt->_eip = ctxt->eip + inc_eip;
4920 ret = emulate_int_real(ctxt, irq);
4922 if (ret != X86EMUL_CONTINUE)
4923 return EMULATE_FAIL;
4925 ctxt->eip = ctxt->_eip;
4926 kvm_rip_write(vcpu, ctxt->eip);
4927 kvm_set_rflags(vcpu, ctxt->eflags);
4929 if (irq == NMI_VECTOR)
4930 vcpu->arch.nmi_pending = 0;
4932 vcpu->arch.interrupt.pending = false;
4934 return EMULATE_DONE;
4936 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4938 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4940 int r = EMULATE_DONE;
4942 ++vcpu->stat.insn_emulation_fail;
4943 trace_kvm_emulate_insn_failed(vcpu);
4944 if (!is_guest_mode(vcpu)) {
4945 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4946 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4947 vcpu->run->internal.ndata = 0;
4950 kvm_queue_exception(vcpu, UD_VECTOR);
4955 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4956 bool write_fault_to_shadow_pgtable,
4962 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4965 if (!vcpu->arch.mmu.direct_map) {
4967 * Write permission should be allowed since only
4968 * write access need to be emulated.
4970 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4973 * If the mapping is invalid in guest, let cpu retry
4974 * it to generate fault.
4976 if (gpa == UNMAPPED_GVA)
4981 * Do not retry the unhandleable instruction if it faults on the
4982 * readonly host memory, otherwise it will goto a infinite loop:
4983 * retry instruction -> write #PF -> emulation fail -> retry
4984 * instruction -> ...
4986 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4989 * If the instruction failed on the error pfn, it can not be fixed,
4990 * report the error to userspace.
4992 if (is_error_noslot_pfn(pfn))
4995 kvm_release_pfn_clean(pfn);
4997 /* The instructions are well-emulated on direct mmu. */
4998 if (vcpu->arch.mmu.direct_map) {
4999 unsigned int indirect_shadow_pages;
5001 spin_lock(&vcpu->kvm->mmu_lock);
5002 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5003 spin_unlock(&vcpu->kvm->mmu_lock);
5005 if (indirect_shadow_pages)
5006 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5012 * if emulation was due to access to shadowed page table
5013 * and it failed try to unshadow page and re-enter the
5014 * guest to let CPU execute the instruction.
5016 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5019 * If the access faults on its page table, it can not
5020 * be fixed by unprotecting shadow page and it should
5021 * be reported to userspace.
5023 return !write_fault_to_shadow_pgtable;
5026 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5027 unsigned long cr2, int emulation_type)
5029 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5030 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5032 last_retry_eip = vcpu->arch.last_retry_eip;
5033 last_retry_addr = vcpu->arch.last_retry_addr;
5036 * If the emulation is caused by #PF and it is non-page_table
5037 * writing instruction, it means the VM-EXIT is caused by shadow
5038 * page protected, we can zap the shadow page and retry this
5039 * instruction directly.
5041 * Note: if the guest uses a non-page-table modifying instruction
5042 * on the PDE that points to the instruction, then we will unmap
5043 * the instruction and go to an infinite loop. So, we cache the
5044 * last retried eip and the last fault address, if we meet the eip
5045 * and the address again, we can break out of the potential infinite
5048 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5050 if (!(emulation_type & EMULTYPE_RETRY))
5053 if (x86_page_table_writing_insn(ctxt))
5056 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5059 vcpu->arch.last_retry_eip = ctxt->eip;
5060 vcpu->arch.last_retry_addr = cr2;
5062 if (!vcpu->arch.mmu.direct_map)
5063 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5065 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5070 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5071 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5073 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5082 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5083 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5088 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5090 struct kvm_run *kvm_run = vcpu->run;
5093 * Use the "raw" value to see if TF was passed to the processor.
5094 * Note that the new value of the flags has not been saved yet.
5096 * This is correct even for TF set by the guest, because "the
5097 * processor will not generate this exception after the instruction
5098 * that sets the TF flag".
5100 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5102 if (unlikely(rflags & X86_EFLAGS_TF)) {
5103 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5104 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5105 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5106 kvm_run->debug.arch.exception = DB_VECTOR;
5107 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5108 *r = EMULATE_USER_EXIT;
5110 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5112 * "Certain debug exceptions may clear bit 0-3. The
5113 * remaining contents of the DR6 register are never
5114 * cleared by the processor".
5116 vcpu->arch.dr6 &= ~15;
5117 vcpu->arch.dr6 |= DR6_BS;
5118 kvm_queue_exception(vcpu, DB_VECTOR);
5123 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5125 struct kvm_run *kvm_run = vcpu->run;
5126 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5129 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5130 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5131 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5132 vcpu->arch.guest_debug_dr7,
5136 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5137 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5138 get_segment_base(vcpu, VCPU_SREG_CS);
5140 kvm_run->debug.arch.exception = DB_VECTOR;
5141 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5142 *r = EMULATE_USER_EXIT;
5147 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5148 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5153 vcpu->arch.dr6 &= ~15;
5154 vcpu->arch.dr6 |= dr6;
5155 kvm_queue_exception(vcpu, DB_VECTOR);
5164 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5171 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5172 bool writeback = true;
5173 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5176 * Clear write_fault_to_shadow_pgtable here to ensure it is
5179 vcpu->arch.write_fault_to_shadow_pgtable = false;
5180 kvm_clear_exception_queue(vcpu);
5182 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5183 init_emulate_ctxt(vcpu);
5186 * We will reenter on the same instruction since
5187 * we do not set complete_userspace_io. This does not
5188 * handle watchpoints yet, those would be handled in
5191 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5194 ctxt->interruptibility = 0;
5195 ctxt->have_exception = false;
5196 ctxt->perm_ok = false;
5198 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5200 r = x86_decode_insn(ctxt, insn, insn_len);
5202 trace_kvm_emulate_insn_start(vcpu);
5203 ++vcpu->stat.insn_emulation;
5204 if (r != EMULATION_OK) {
5205 if (emulation_type & EMULTYPE_TRAP_UD)
5206 return EMULATE_FAIL;
5207 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5209 return EMULATE_DONE;
5210 if (emulation_type & EMULTYPE_SKIP)
5211 return EMULATE_FAIL;
5212 return handle_emulation_failure(vcpu);
5216 if (emulation_type & EMULTYPE_SKIP) {
5217 kvm_rip_write(vcpu, ctxt->_eip);
5218 return EMULATE_DONE;
5221 if (retry_instruction(ctxt, cr2, emulation_type))
5222 return EMULATE_DONE;
5224 /* this is needed for vmware backdoor interface to work since it
5225 changes registers values during IO operation */
5226 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5227 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5228 emulator_invalidate_register_cache(ctxt);
5232 r = x86_emulate_insn(ctxt);
5234 if (r == EMULATION_INTERCEPTED)
5235 return EMULATE_DONE;
5237 if (r == EMULATION_FAILED) {
5238 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5240 return EMULATE_DONE;
5242 return handle_emulation_failure(vcpu);
5245 if (ctxt->have_exception) {
5246 inject_emulated_exception(vcpu);
5248 } else if (vcpu->arch.pio.count) {
5249 if (!vcpu->arch.pio.in) {
5250 /* FIXME: return into emulator if single-stepping. */
5251 vcpu->arch.pio.count = 0;
5254 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5256 r = EMULATE_USER_EXIT;
5257 } else if (vcpu->mmio_needed) {
5258 if (!vcpu->mmio_is_write)
5260 r = EMULATE_USER_EXIT;
5261 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5262 } else if (r == EMULATION_RESTART)
5268 toggle_interruptibility(vcpu, ctxt->interruptibility);
5269 kvm_make_request(KVM_REQ_EVENT, vcpu);
5270 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5271 kvm_rip_write(vcpu, ctxt->eip);
5272 if (r == EMULATE_DONE)
5273 kvm_vcpu_check_singlestep(vcpu, &r);
5274 kvm_set_rflags(vcpu, ctxt->eflags);
5276 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5280 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5282 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5284 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5285 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5286 size, port, &val, 1);
5287 /* do not return to emulator after return from userspace */
5288 vcpu->arch.pio.count = 0;
5291 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5293 static void tsc_bad(void *info)
5295 __this_cpu_write(cpu_tsc_khz, 0);
5298 static void tsc_khz_changed(void *data)
5300 struct cpufreq_freqs *freq = data;
5301 unsigned long khz = 0;
5305 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5306 khz = cpufreq_quick_get(raw_smp_processor_id());
5309 __this_cpu_write(cpu_tsc_khz, khz);
5312 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5315 struct cpufreq_freqs *freq = data;
5317 struct kvm_vcpu *vcpu;
5318 int i, send_ipi = 0;
5321 * We allow guests to temporarily run on slowing clocks,
5322 * provided we notify them after, or to run on accelerating
5323 * clocks, provided we notify them before. Thus time never
5326 * However, we have a problem. We can't atomically update
5327 * the frequency of a given CPU from this function; it is
5328 * merely a notifier, which can be called from any CPU.
5329 * Changing the TSC frequency at arbitrary points in time
5330 * requires a recomputation of local variables related to
5331 * the TSC for each VCPU. We must flag these local variables
5332 * to be updated and be sure the update takes place with the
5333 * new frequency before any guests proceed.
5335 * Unfortunately, the combination of hotplug CPU and frequency
5336 * change creates an intractable locking scenario; the order
5337 * of when these callouts happen is undefined with respect to
5338 * CPU hotplug, and they can race with each other. As such,
5339 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5340 * undefined; you can actually have a CPU frequency change take
5341 * place in between the computation of X and the setting of the
5342 * variable. To protect against this problem, all updates of
5343 * the per_cpu tsc_khz variable are done in an interrupt
5344 * protected IPI, and all callers wishing to update the value
5345 * must wait for a synchronous IPI to complete (which is trivial
5346 * if the caller is on the CPU already). This establishes the
5347 * necessary total order on variable updates.
5349 * Note that because a guest time update may take place
5350 * anytime after the setting of the VCPU's request bit, the
5351 * correct TSC value must be set before the request. However,
5352 * to ensure the update actually makes it to any guest which
5353 * starts running in hardware virtualization between the set
5354 * and the acquisition of the spinlock, we must also ping the
5355 * CPU after setting the request bit.
5359 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5361 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5364 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5366 spin_lock(&kvm_lock);
5367 list_for_each_entry(kvm, &vm_list, vm_list) {
5368 kvm_for_each_vcpu(i, vcpu, kvm) {
5369 if (vcpu->cpu != freq->cpu)
5371 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5372 if (vcpu->cpu != smp_processor_id())
5376 spin_unlock(&kvm_lock);
5378 if (freq->old < freq->new && send_ipi) {
5380 * We upscale the frequency. Must make the guest
5381 * doesn't see old kvmclock values while running with
5382 * the new frequency, otherwise we risk the guest sees
5383 * time go backwards.
5385 * In case we update the frequency for another cpu
5386 * (which might be in guest context) send an interrupt
5387 * to kick the cpu out of guest context. Next time
5388 * guest context is entered kvmclock will be updated,
5389 * so the guest will not see stale values.
5391 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5396 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5397 .notifier_call = kvmclock_cpufreq_notifier
5400 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5401 unsigned long action, void *hcpu)
5403 unsigned int cpu = (unsigned long)hcpu;
5407 case CPU_DOWN_FAILED:
5408 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5410 case CPU_DOWN_PREPARE:
5411 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5417 static struct notifier_block kvmclock_cpu_notifier_block = {
5418 .notifier_call = kvmclock_cpu_notifier,
5419 .priority = -INT_MAX
5422 static void kvm_timer_init(void)
5426 max_tsc_khz = tsc_khz;
5428 cpu_notifier_register_begin();
5429 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5430 #ifdef CONFIG_CPU_FREQ
5431 struct cpufreq_policy policy;
5432 memset(&policy, 0, sizeof(policy));
5434 cpufreq_get_policy(&policy, cpu);
5435 if (policy.cpuinfo.max_freq)
5436 max_tsc_khz = policy.cpuinfo.max_freq;
5439 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5440 CPUFREQ_TRANSITION_NOTIFIER);
5442 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5443 for_each_online_cpu(cpu)
5444 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5446 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5447 cpu_notifier_register_done();
5451 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5453 int kvm_is_in_guest(void)
5455 return __this_cpu_read(current_vcpu) != NULL;
5458 static int kvm_is_user_mode(void)
5462 if (__this_cpu_read(current_vcpu))
5463 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5465 return user_mode != 0;
5468 static unsigned long kvm_get_guest_ip(void)
5470 unsigned long ip = 0;
5472 if (__this_cpu_read(current_vcpu))
5473 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5478 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5479 .is_in_guest = kvm_is_in_guest,
5480 .is_user_mode = kvm_is_user_mode,
5481 .get_guest_ip = kvm_get_guest_ip,
5484 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5486 __this_cpu_write(current_vcpu, vcpu);
5488 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5490 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5492 __this_cpu_write(current_vcpu, NULL);
5494 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5496 static void kvm_set_mmio_spte_mask(void)
5499 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5502 * Set the reserved bits and the present bit of an paging-structure
5503 * entry to generate page fault with PFER.RSV = 1.
5505 /* Mask the reserved physical address bits. */
5506 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5508 /* Bit 62 is always reserved for 32bit host. */
5509 mask |= 0x3ull << 62;
5511 /* Set the present bit. */
5514 #ifdef CONFIG_X86_64
5516 * If reserved bit is not supported, clear the present bit to disable
5519 if (maxphyaddr == 52)
5523 kvm_mmu_set_mmio_spte_mask(mask);
5526 #ifdef CONFIG_X86_64
5527 static void pvclock_gtod_update_fn(struct work_struct *work)
5531 struct kvm_vcpu *vcpu;
5534 spin_lock(&kvm_lock);
5535 list_for_each_entry(kvm, &vm_list, vm_list)
5536 kvm_for_each_vcpu(i, vcpu, kvm)
5537 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5538 atomic_set(&kvm_guest_has_master_clock, 0);
5539 spin_unlock(&kvm_lock);
5542 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5545 * Notification about pvclock gtod data update.
5547 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5550 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5551 struct timekeeper *tk = priv;
5553 update_pvclock_gtod(tk);
5555 /* disable master clock if host does not trust, or does not
5556 * use, TSC clocksource
5558 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5559 atomic_read(&kvm_guest_has_master_clock) != 0)
5560 queue_work(system_long_wq, &pvclock_gtod_work);
5565 static struct notifier_block pvclock_gtod_notifier = {
5566 .notifier_call = pvclock_gtod_notify,
5570 int kvm_arch_init(void *opaque)
5573 struct kvm_x86_ops *ops = opaque;
5576 printk(KERN_ERR "kvm: already loaded the other module\n");
5581 if (!ops->cpu_has_kvm_support()) {
5582 printk(KERN_ERR "kvm: no hardware support\n");
5586 if (ops->disabled_by_bios()) {
5587 printk(KERN_ERR "kvm: disabled by bios\n");
5593 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5595 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5599 r = kvm_mmu_module_init();
5601 goto out_free_percpu;
5603 kvm_set_mmio_spte_mask();
5606 kvm_init_msr_list();
5608 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5609 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5613 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5616 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5619 #ifdef CONFIG_X86_64
5620 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5626 free_percpu(shared_msrs);
5631 void kvm_arch_exit(void)
5633 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5635 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5636 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5637 CPUFREQ_TRANSITION_NOTIFIER);
5638 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5639 #ifdef CONFIG_X86_64
5640 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5643 kvm_mmu_module_exit();
5644 free_percpu(shared_msrs);
5647 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5649 ++vcpu->stat.halt_exits;
5650 if (irqchip_in_kernel(vcpu->kvm)) {
5651 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5654 vcpu->run->exit_reason = KVM_EXIT_HLT;
5658 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5660 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5662 u64 param, ingpa, outgpa, ret;
5663 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5664 bool fast, longmode;
5668 * hypercall generates UD from non zero cpl and real mode
5671 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5672 kvm_queue_exception(vcpu, UD_VECTOR);
5676 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5677 longmode = is_long_mode(vcpu) && cs_l == 1;
5680 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5681 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5682 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5683 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5684 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5685 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5687 #ifdef CONFIG_X86_64
5689 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5690 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5691 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5695 code = param & 0xffff;
5696 fast = (param >> 16) & 0x1;
5697 rep_cnt = (param >> 32) & 0xfff;
5698 rep_idx = (param >> 48) & 0xfff;
5700 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5703 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5704 kvm_vcpu_on_spin(vcpu);
5707 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5711 ret = res | (((u64)rep_done & 0xfff) << 32);
5713 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5715 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5716 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5723 * kvm_pv_kick_cpu_op: Kick a vcpu.
5725 * @apicid - apicid of vcpu to be kicked.
5727 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5729 struct kvm_lapic_irq lapic_irq;
5731 lapic_irq.shorthand = 0;
5732 lapic_irq.dest_mode = 0;
5733 lapic_irq.dest_id = apicid;
5735 lapic_irq.delivery_mode = APIC_DM_REMRD;
5736 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5739 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5741 unsigned long nr, a0, a1, a2, a3, ret;
5744 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5745 return kvm_hv_hypercall(vcpu);
5747 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5748 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5749 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5750 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5751 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5753 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5755 if (!is_long_mode(vcpu)) {
5763 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5769 case KVM_HC_VAPIC_POLL_IRQ:
5772 case KVM_HC_KICK_CPU:
5773 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5781 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5782 ++vcpu->stat.hypercalls;
5785 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5787 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5789 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5790 char instruction[3];
5791 unsigned long rip = kvm_rip_read(vcpu);
5793 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5795 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5799 * Check if userspace requested an interrupt window, and that the
5800 * interrupt window is open.
5802 * No need to exit to userspace if we already have an interrupt queued.
5804 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5806 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5807 vcpu->run->request_interrupt_window &&
5808 kvm_arch_interrupt_allowed(vcpu));
5811 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5813 struct kvm_run *kvm_run = vcpu->run;
5815 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5816 kvm_run->cr8 = kvm_get_cr8(vcpu);
5817 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5818 if (irqchip_in_kernel(vcpu->kvm))
5819 kvm_run->ready_for_interrupt_injection = 1;
5821 kvm_run->ready_for_interrupt_injection =
5822 kvm_arch_interrupt_allowed(vcpu) &&
5823 !kvm_cpu_has_interrupt(vcpu) &&
5824 !kvm_event_needs_reinjection(vcpu);
5827 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5831 if (!kvm_x86_ops->update_cr8_intercept)
5834 if (!vcpu->arch.apic)
5837 if (!vcpu->arch.apic->vapic_addr)
5838 max_irr = kvm_lapic_find_highest_irr(vcpu);
5845 tpr = kvm_lapic_get_cr8(vcpu);
5847 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5850 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5854 /* try to reinject previous events if any */
5855 if (vcpu->arch.exception.pending) {
5856 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5857 vcpu->arch.exception.has_error_code,
5858 vcpu->arch.exception.error_code);
5859 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5860 vcpu->arch.exception.has_error_code,
5861 vcpu->arch.exception.error_code,
5862 vcpu->arch.exception.reinject);
5866 if (vcpu->arch.nmi_injected) {
5867 kvm_x86_ops->set_nmi(vcpu);
5871 if (vcpu->arch.interrupt.pending) {
5872 kvm_x86_ops->set_irq(vcpu);
5876 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5877 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5882 /* try to inject new event if pending */
5883 if (vcpu->arch.nmi_pending) {
5884 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5885 --vcpu->arch.nmi_pending;
5886 vcpu->arch.nmi_injected = true;
5887 kvm_x86_ops->set_nmi(vcpu);
5889 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5890 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5891 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5893 kvm_x86_ops->set_irq(vcpu);
5899 static void process_nmi(struct kvm_vcpu *vcpu)
5904 * x86 is limited to one NMI running, and one NMI pending after it.
5905 * If an NMI is already in progress, limit further NMIs to just one.
5906 * Otherwise, allow two (and we'll inject the first one immediately).
5908 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5911 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5912 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5913 kvm_make_request(KVM_REQ_EVENT, vcpu);
5916 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5918 u64 eoi_exit_bitmap[4];
5921 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5924 memset(eoi_exit_bitmap, 0, 32);
5927 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5928 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5929 kvm_apic_update_tmr(vcpu, tmr);
5933 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5934 * exiting to the userspace. Otherwise, the value will be returned to the
5937 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5940 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5941 vcpu->run->request_interrupt_window;
5942 bool req_immediate_exit = false;
5944 if (vcpu->requests) {
5945 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5946 kvm_mmu_unload(vcpu);
5947 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5948 __kvm_migrate_timers(vcpu);
5949 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5950 kvm_gen_update_masterclock(vcpu->kvm);
5951 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5952 kvm_gen_kvmclock_update(vcpu);
5953 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5954 r = kvm_guest_time_update(vcpu);
5958 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5959 kvm_mmu_sync_roots(vcpu);
5960 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5961 kvm_x86_ops->tlb_flush(vcpu);
5962 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5963 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5967 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5968 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5972 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5973 vcpu->fpu_active = 0;
5974 kvm_x86_ops->fpu_deactivate(vcpu);
5976 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5977 /* Page is swapped out. Do synthetic halt */
5978 vcpu->arch.apf.halted = true;
5982 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5983 record_steal_time(vcpu);
5984 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5986 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5987 kvm_handle_pmu_event(vcpu);
5988 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5989 kvm_deliver_pmi(vcpu);
5990 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5991 vcpu_scan_ioapic(vcpu);
5994 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5995 kvm_apic_accept_events(vcpu);
5996 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6001 if (inject_pending_event(vcpu, req_int_win) != 0)
6002 req_immediate_exit = true;
6003 /* enable NMI/IRQ window open exits if needed */
6004 else if (vcpu->arch.nmi_pending)
6005 kvm_x86_ops->enable_nmi_window(vcpu);
6006 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6007 kvm_x86_ops->enable_irq_window(vcpu);
6009 if (kvm_lapic_enabled(vcpu)) {
6011 * Update architecture specific hints for APIC
6012 * virtual interrupt delivery.
6014 if (kvm_x86_ops->hwapic_irr_update)
6015 kvm_x86_ops->hwapic_irr_update(vcpu,
6016 kvm_lapic_find_highest_irr(vcpu));
6017 update_cr8_intercept(vcpu);
6018 kvm_lapic_sync_to_vapic(vcpu);
6022 r = kvm_mmu_reload(vcpu);
6024 goto cancel_injection;
6029 kvm_x86_ops->prepare_guest_switch(vcpu);
6030 if (vcpu->fpu_active)
6031 kvm_load_guest_fpu(vcpu);
6032 kvm_load_guest_xcr0(vcpu);
6034 vcpu->mode = IN_GUEST_MODE;
6036 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6038 /* We should set ->mode before check ->requests,
6039 * see the comment in make_all_cpus_request.
6041 smp_mb__after_srcu_read_unlock();
6043 local_irq_disable();
6045 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6046 || need_resched() || signal_pending(current)) {
6047 vcpu->mode = OUTSIDE_GUEST_MODE;
6051 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6053 goto cancel_injection;
6056 if (req_immediate_exit)
6057 smp_send_reschedule(vcpu->cpu);
6061 if (unlikely(vcpu->arch.switch_db_regs)) {
6063 set_debugreg(vcpu->arch.eff_db[0], 0);
6064 set_debugreg(vcpu->arch.eff_db[1], 1);
6065 set_debugreg(vcpu->arch.eff_db[2], 2);
6066 set_debugreg(vcpu->arch.eff_db[3], 3);
6067 set_debugreg(vcpu->arch.dr6, 6);
6070 trace_kvm_entry(vcpu->vcpu_id);
6071 kvm_x86_ops->run(vcpu);
6074 * Do this here before restoring debug registers on the host. And
6075 * since we do this before handling the vmexit, a DR access vmexit
6076 * can (a) read the correct value of the debug registers, (b) set
6077 * KVM_DEBUGREG_WONT_EXIT again.
6079 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6082 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6083 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6084 for (i = 0; i < KVM_NR_DB_REGS; i++)
6085 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6089 * If the guest has used debug registers, at least dr7
6090 * will be disabled while returning to the host.
6091 * If we don't have active breakpoints in the host, we don't
6092 * care about the messed up debug address registers. But if
6093 * we have some of them active, restore the old state.
6095 if (hw_breakpoint_active())
6096 hw_breakpoint_restore();
6098 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6101 vcpu->mode = OUTSIDE_GUEST_MODE;
6104 /* Interrupt is enabled by handle_external_intr() */
6105 kvm_x86_ops->handle_external_intr(vcpu);
6110 * We must have an instruction between local_irq_enable() and
6111 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6112 * the interrupt shadow. The stat.exits increment will do nicely.
6113 * But we need to prevent reordering, hence this barrier():
6121 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6124 * Profile KVM exit RIPs:
6126 if (unlikely(prof_on == KVM_PROFILING)) {
6127 unsigned long rip = kvm_rip_read(vcpu);
6128 profile_hit(KVM_PROFILING, (void *)rip);
6131 if (unlikely(vcpu->arch.tsc_always_catchup))
6132 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6134 if (vcpu->arch.apic_attention)
6135 kvm_lapic_sync_from_vapic(vcpu);
6137 r = kvm_x86_ops->handle_exit(vcpu);
6141 kvm_x86_ops->cancel_injection(vcpu);
6142 if (unlikely(vcpu->arch.apic_attention))
6143 kvm_lapic_sync_from_vapic(vcpu);
6149 static int __vcpu_run(struct kvm_vcpu *vcpu)
6152 struct kvm *kvm = vcpu->kvm;
6154 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6158 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6159 !vcpu->arch.apf.halted)
6160 r = vcpu_enter_guest(vcpu);
6162 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6163 kvm_vcpu_block(vcpu);
6164 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6165 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6166 kvm_apic_accept_events(vcpu);
6167 switch(vcpu->arch.mp_state) {
6168 case KVM_MP_STATE_HALTED:
6169 vcpu->arch.pv.pv_unhalted = false;
6170 vcpu->arch.mp_state =
6171 KVM_MP_STATE_RUNNABLE;
6172 case KVM_MP_STATE_RUNNABLE:
6173 vcpu->arch.apf.halted = false;
6175 case KVM_MP_STATE_INIT_RECEIVED:
6187 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6188 if (kvm_cpu_has_pending_timer(vcpu))
6189 kvm_inject_pending_timer_irqs(vcpu);
6191 if (dm_request_for_irq_injection(vcpu)) {
6193 vcpu->run->exit_reason = KVM_EXIT_INTR;
6194 ++vcpu->stat.request_irq_exits;
6197 kvm_check_async_pf_completion(vcpu);
6199 if (signal_pending(current)) {
6201 vcpu->run->exit_reason = KVM_EXIT_INTR;
6202 ++vcpu->stat.signal_exits;
6204 if (need_resched()) {
6205 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6207 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6211 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6216 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6219 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6220 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6221 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6222 if (r != EMULATE_DONE)
6227 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6229 BUG_ON(!vcpu->arch.pio.count);
6231 return complete_emulated_io(vcpu);
6235 * Implements the following, as a state machine:
6239 * for each mmio piece in the fragment
6247 * for each mmio piece in the fragment
6252 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6254 struct kvm_run *run = vcpu->run;
6255 struct kvm_mmio_fragment *frag;
6258 BUG_ON(!vcpu->mmio_needed);
6260 /* Complete previous fragment */
6261 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6262 len = min(8u, frag->len);
6263 if (!vcpu->mmio_is_write)
6264 memcpy(frag->data, run->mmio.data, len);
6266 if (frag->len <= 8) {
6267 /* Switch to the next fragment. */
6269 vcpu->mmio_cur_fragment++;
6271 /* Go forward to the next mmio piece. */
6277 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6278 vcpu->mmio_needed = 0;
6280 /* FIXME: return into emulator if single-stepping. */
6281 if (vcpu->mmio_is_write)
6283 vcpu->mmio_read_completed = 1;
6284 return complete_emulated_io(vcpu);
6287 run->exit_reason = KVM_EXIT_MMIO;
6288 run->mmio.phys_addr = frag->gpa;
6289 if (vcpu->mmio_is_write)
6290 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6291 run->mmio.len = min(8u, frag->len);
6292 run->mmio.is_write = vcpu->mmio_is_write;
6293 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6298 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6303 if (!tsk_used_math(current) && init_fpu(current))
6306 if (vcpu->sigset_active)
6307 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6309 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6310 kvm_vcpu_block(vcpu);
6311 kvm_apic_accept_events(vcpu);
6312 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6317 /* re-sync apic's tpr */
6318 if (!irqchip_in_kernel(vcpu->kvm)) {
6319 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6325 if (unlikely(vcpu->arch.complete_userspace_io)) {
6326 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6327 vcpu->arch.complete_userspace_io = NULL;
6332 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6334 r = __vcpu_run(vcpu);
6337 post_kvm_run_save(vcpu);
6338 if (vcpu->sigset_active)
6339 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6344 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6346 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6348 * We are here if userspace calls get_regs() in the middle of
6349 * instruction emulation. Registers state needs to be copied
6350 * back from emulation context to vcpu. Userspace shouldn't do
6351 * that usually, but some bad designed PV devices (vmware
6352 * backdoor interface) need this to work
6354 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6355 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6357 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6358 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6359 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6360 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6361 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6362 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6363 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6364 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6365 #ifdef CONFIG_X86_64
6366 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6367 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6368 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6369 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6370 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6371 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6372 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6373 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6376 regs->rip = kvm_rip_read(vcpu);
6377 regs->rflags = kvm_get_rflags(vcpu);
6382 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6384 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6385 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6387 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6388 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6389 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6390 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6391 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6392 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6393 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6394 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6395 #ifdef CONFIG_X86_64
6396 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6397 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6398 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6399 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6400 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6401 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6402 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6403 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6406 kvm_rip_write(vcpu, regs->rip);
6407 kvm_set_rflags(vcpu, regs->rflags);
6409 vcpu->arch.exception.pending = false;
6411 kvm_make_request(KVM_REQ_EVENT, vcpu);
6416 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6418 struct kvm_segment cs;
6420 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6424 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6426 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6427 struct kvm_sregs *sregs)
6431 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6432 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6433 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6434 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6435 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6436 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6438 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6439 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6441 kvm_x86_ops->get_idt(vcpu, &dt);
6442 sregs->idt.limit = dt.size;
6443 sregs->idt.base = dt.address;
6444 kvm_x86_ops->get_gdt(vcpu, &dt);
6445 sregs->gdt.limit = dt.size;
6446 sregs->gdt.base = dt.address;
6448 sregs->cr0 = kvm_read_cr0(vcpu);
6449 sregs->cr2 = vcpu->arch.cr2;
6450 sregs->cr3 = kvm_read_cr3(vcpu);
6451 sregs->cr4 = kvm_read_cr4(vcpu);
6452 sregs->cr8 = kvm_get_cr8(vcpu);
6453 sregs->efer = vcpu->arch.efer;
6454 sregs->apic_base = kvm_get_apic_base(vcpu);
6456 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6458 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6459 set_bit(vcpu->arch.interrupt.nr,
6460 (unsigned long *)sregs->interrupt_bitmap);
6465 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6466 struct kvm_mp_state *mp_state)
6468 kvm_apic_accept_events(vcpu);
6469 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6470 vcpu->arch.pv.pv_unhalted)
6471 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6473 mp_state->mp_state = vcpu->arch.mp_state;
6478 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6479 struct kvm_mp_state *mp_state)
6481 if (!kvm_vcpu_has_lapic(vcpu) &&
6482 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6485 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6486 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6487 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6489 vcpu->arch.mp_state = mp_state->mp_state;
6490 kvm_make_request(KVM_REQ_EVENT, vcpu);
6494 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6495 int reason, bool has_error_code, u32 error_code)
6497 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6500 init_emulate_ctxt(vcpu);
6502 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6503 has_error_code, error_code);
6506 return EMULATE_FAIL;
6508 kvm_rip_write(vcpu, ctxt->eip);
6509 kvm_set_rflags(vcpu, ctxt->eflags);
6510 kvm_make_request(KVM_REQ_EVENT, vcpu);
6511 return EMULATE_DONE;
6513 EXPORT_SYMBOL_GPL(kvm_task_switch);
6515 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6516 struct kvm_sregs *sregs)
6518 struct msr_data apic_base_msr;
6519 int mmu_reset_needed = 0;
6520 int pending_vec, max_bits, idx;
6523 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6526 dt.size = sregs->idt.limit;
6527 dt.address = sregs->idt.base;
6528 kvm_x86_ops->set_idt(vcpu, &dt);
6529 dt.size = sregs->gdt.limit;
6530 dt.address = sregs->gdt.base;
6531 kvm_x86_ops->set_gdt(vcpu, &dt);
6533 vcpu->arch.cr2 = sregs->cr2;
6534 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6535 vcpu->arch.cr3 = sregs->cr3;
6536 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6538 kvm_set_cr8(vcpu, sregs->cr8);
6540 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6541 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6542 apic_base_msr.data = sregs->apic_base;
6543 apic_base_msr.host_initiated = true;
6544 kvm_set_apic_base(vcpu, &apic_base_msr);
6546 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6547 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6548 vcpu->arch.cr0 = sregs->cr0;
6550 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6551 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6552 if (sregs->cr4 & X86_CR4_OSXSAVE)
6553 kvm_update_cpuid(vcpu);
6555 idx = srcu_read_lock(&vcpu->kvm->srcu);
6556 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6557 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6558 mmu_reset_needed = 1;
6560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6562 if (mmu_reset_needed)
6563 kvm_mmu_reset_context(vcpu);
6565 max_bits = KVM_NR_INTERRUPTS;
6566 pending_vec = find_first_bit(
6567 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6568 if (pending_vec < max_bits) {
6569 kvm_queue_interrupt(vcpu, pending_vec, false);
6570 pr_debug("Set back pending irq %d\n", pending_vec);
6573 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6574 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6575 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6576 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6577 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6578 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6580 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6581 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6583 update_cr8_intercept(vcpu);
6585 /* Older userspace won't unhalt the vcpu on reset. */
6586 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6587 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6589 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6591 kvm_make_request(KVM_REQ_EVENT, vcpu);
6596 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6597 struct kvm_guest_debug *dbg)
6599 unsigned long rflags;
6602 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6604 if (vcpu->arch.exception.pending)
6606 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6607 kvm_queue_exception(vcpu, DB_VECTOR);
6609 kvm_queue_exception(vcpu, BP_VECTOR);
6613 * Read rflags as long as potentially injected trace flags are still
6616 rflags = kvm_get_rflags(vcpu);
6618 vcpu->guest_debug = dbg->control;
6619 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6620 vcpu->guest_debug = 0;
6622 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6623 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6624 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6625 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6627 for (i = 0; i < KVM_NR_DB_REGS; i++)
6628 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6630 kvm_update_dr7(vcpu);
6632 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6633 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6634 get_segment_base(vcpu, VCPU_SREG_CS);
6637 * Trigger an rflags update that will inject or remove the trace
6640 kvm_set_rflags(vcpu, rflags);
6642 kvm_x86_ops->update_db_bp_intercept(vcpu);
6652 * Translate a guest virtual address to a guest physical address.
6654 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6655 struct kvm_translation *tr)
6657 unsigned long vaddr = tr->linear_address;
6661 idx = srcu_read_lock(&vcpu->kvm->srcu);
6662 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6663 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6664 tr->physical_address = gpa;
6665 tr->valid = gpa != UNMAPPED_GVA;
6672 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6674 struct i387_fxsave_struct *fxsave =
6675 &vcpu->arch.guest_fpu.state->fxsave;
6677 memcpy(fpu->fpr, fxsave->st_space, 128);
6678 fpu->fcw = fxsave->cwd;
6679 fpu->fsw = fxsave->swd;
6680 fpu->ftwx = fxsave->twd;
6681 fpu->last_opcode = fxsave->fop;
6682 fpu->last_ip = fxsave->rip;
6683 fpu->last_dp = fxsave->rdp;
6684 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6689 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6691 struct i387_fxsave_struct *fxsave =
6692 &vcpu->arch.guest_fpu.state->fxsave;
6694 memcpy(fxsave->st_space, fpu->fpr, 128);
6695 fxsave->cwd = fpu->fcw;
6696 fxsave->swd = fpu->fsw;
6697 fxsave->twd = fpu->ftwx;
6698 fxsave->fop = fpu->last_opcode;
6699 fxsave->rip = fpu->last_ip;
6700 fxsave->rdp = fpu->last_dp;
6701 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6706 int fx_init(struct kvm_vcpu *vcpu)
6710 err = fpu_alloc(&vcpu->arch.guest_fpu);
6714 fpu_finit(&vcpu->arch.guest_fpu);
6717 * Ensure guest xcr0 is valid for loading
6719 vcpu->arch.xcr0 = XSTATE_FP;
6721 vcpu->arch.cr0 |= X86_CR0_ET;
6725 EXPORT_SYMBOL_GPL(fx_init);
6727 static void fx_free(struct kvm_vcpu *vcpu)
6729 fpu_free(&vcpu->arch.guest_fpu);
6732 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6734 if (vcpu->guest_fpu_loaded)
6738 * Restore all possible states in the guest,
6739 * and assume host would use all available bits.
6740 * Guest xcr0 would be loaded later.
6742 kvm_put_guest_xcr0(vcpu);
6743 vcpu->guest_fpu_loaded = 1;
6744 __kernel_fpu_begin();
6745 fpu_restore_checking(&vcpu->arch.guest_fpu);
6749 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6751 kvm_put_guest_xcr0(vcpu);
6753 if (!vcpu->guest_fpu_loaded)
6756 vcpu->guest_fpu_loaded = 0;
6757 fpu_save_init(&vcpu->arch.guest_fpu);
6759 ++vcpu->stat.fpu_reload;
6760 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6764 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6766 kvmclock_reset(vcpu);
6768 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6770 kvm_x86_ops->vcpu_free(vcpu);
6773 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6776 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6777 printk_once(KERN_WARNING
6778 "kvm: SMP vm created on host with unstable TSC; "
6779 "guest TSC will not be reliable\n");
6780 return kvm_x86_ops->vcpu_create(kvm, id);
6783 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6787 vcpu->arch.mtrr_state.have_fixed = 1;
6788 r = vcpu_load(vcpu);
6791 kvm_vcpu_reset(vcpu);
6792 kvm_mmu_setup(vcpu);
6798 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6801 struct msr_data msr;
6802 struct kvm *kvm = vcpu->kvm;
6804 r = vcpu_load(vcpu);
6808 msr.index = MSR_IA32_TSC;
6809 msr.host_initiated = true;
6810 kvm_write_tsc(vcpu, &msr);
6813 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6814 KVMCLOCK_SYNC_PERIOD);
6819 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6822 vcpu->arch.apf.msr_val = 0;
6824 r = vcpu_load(vcpu);
6826 kvm_mmu_unload(vcpu);
6830 kvm_x86_ops->vcpu_free(vcpu);
6833 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6835 atomic_set(&vcpu->arch.nmi_queued, 0);
6836 vcpu->arch.nmi_pending = 0;
6837 vcpu->arch.nmi_injected = false;
6839 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6840 vcpu->arch.dr6 = DR6_FIXED_1;
6841 kvm_update_dr6(vcpu);
6842 vcpu->arch.dr7 = DR7_FIXED_1;
6843 kvm_update_dr7(vcpu);
6845 kvm_make_request(KVM_REQ_EVENT, vcpu);
6846 vcpu->arch.apf.msr_val = 0;
6847 vcpu->arch.st.msr_val = 0;
6849 kvmclock_reset(vcpu);
6851 kvm_clear_async_pf_completion_queue(vcpu);
6852 kvm_async_pf_hash_reset(vcpu);
6853 vcpu->arch.apf.halted = false;
6855 kvm_pmu_reset(vcpu);
6857 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6858 vcpu->arch.regs_avail = ~0;
6859 vcpu->arch.regs_dirty = ~0;
6861 kvm_x86_ops->vcpu_reset(vcpu);
6864 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6866 struct kvm_segment cs;
6868 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6869 cs.selector = vector << 8;
6870 cs.base = vector << 12;
6871 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6872 kvm_rip_write(vcpu, 0);
6875 int kvm_arch_hardware_enable(void *garbage)
6878 struct kvm_vcpu *vcpu;
6883 bool stable, backwards_tsc = false;
6885 kvm_shared_msr_cpu_online();
6886 ret = kvm_x86_ops->hardware_enable(garbage);
6890 local_tsc = native_read_tsc();
6891 stable = !check_tsc_unstable();
6892 list_for_each_entry(kvm, &vm_list, vm_list) {
6893 kvm_for_each_vcpu(i, vcpu, kvm) {
6894 if (!stable && vcpu->cpu == smp_processor_id())
6895 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6896 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6897 backwards_tsc = true;
6898 if (vcpu->arch.last_host_tsc > max_tsc)
6899 max_tsc = vcpu->arch.last_host_tsc;
6905 * Sometimes, even reliable TSCs go backwards. This happens on
6906 * platforms that reset TSC during suspend or hibernate actions, but
6907 * maintain synchronization. We must compensate. Fortunately, we can
6908 * detect that condition here, which happens early in CPU bringup,
6909 * before any KVM threads can be running. Unfortunately, we can't
6910 * bring the TSCs fully up to date with real time, as we aren't yet far
6911 * enough into CPU bringup that we know how much real time has actually
6912 * elapsed; our helper function, get_kernel_ns() will be using boot
6913 * variables that haven't been updated yet.
6915 * So we simply find the maximum observed TSC above, then record the
6916 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6917 * the adjustment will be applied. Note that we accumulate
6918 * adjustments, in case multiple suspend cycles happen before some VCPU
6919 * gets a chance to run again. In the event that no KVM threads get a
6920 * chance to run, we will miss the entire elapsed period, as we'll have
6921 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6922 * loose cycle time. This isn't too big a deal, since the loss will be
6923 * uniform across all VCPUs (not to mention the scenario is extremely
6924 * unlikely). It is possible that a second hibernate recovery happens
6925 * much faster than a first, causing the observed TSC here to be
6926 * smaller; this would require additional padding adjustment, which is
6927 * why we set last_host_tsc to the local tsc observed here.
6929 * N.B. - this code below runs only on platforms with reliable TSC,
6930 * as that is the only way backwards_tsc is set above. Also note
6931 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6932 * have the same delta_cyc adjustment applied if backwards_tsc
6933 * is detected. Note further, this adjustment is only done once,
6934 * as we reset last_host_tsc on all VCPUs to stop this from being
6935 * called multiple times (one for each physical CPU bringup).
6937 * Platforms with unreliable TSCs don't have to deal with this, they
6938 * will be compensated by the logic in vcpu_load, which sets the TSC to
6939 * catchup mode. This will catchup all VCPUs to real time, but cannot
6940 * guarantee that they stay in perfect synchronization.
6942 if (backwards_tsc) {
6943 u64 delta_cyc = max_tsc - local_tsc;
6944 backwards_tsc_observed = true;
6945 list_for_each_entry(kvm, &vm_list, vm_list) {
6946 kvm_for_each_vcpu(i, vcpu, kvm) {
6947 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6948 vcpu->arch.last_host_tsc = local_tsc;
6949 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6954 * We have to disable TSC offset matching.. if you were
6955 * booting a VM while issuing an S4 host suspend....
6956 * you may have some problem. Solving this issue is
6957 * left as an exercise to the reader.
6959 kvm->arch.last_tsc_nsec = 0;
6960 kvm->arch.last_tsc_write = 0;
6967 void kvm_arch_hardware_disable(void *garbage)
6969 kvm_x86_ops->hardware_disable(garbage);
6970 drop_user_return_notifiers(garbage);
6973 int kvm_arch_hardware_setup(void)
6975 return kvm_x86_ops->hardware_setup();
6978 void kvm_arch_hardware_unsetup(void)
6980 kvm_x86_ops->hardware_unsetup();
6983 void kvm_arch_check_processor_compat(void *rtn)
6985 kvm_x86_ops->check_processor_compatibility(rtn);
6988 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6990 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6993 struct static_key kvm_no_apic_vcpu __read_mostly;
6995 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7001 BUG_ON(vcpu->kvm == NULL);
7004 vcpu->arch.pv.pv_unhalted = false;
7005 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7006 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
7007 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7009 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7011 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7016 vcpu->arch.pio_data = page_address(page);
7018 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7020 r = kvm_mmu_create(vcpu);
7022 goto fail_free_pio_data;
7024 if (irqchip_in_kernel(kvm)) {
7025 r = kvm_create_lapic(vcpu);
7027 goto fail_mmu_destroy;
7029 static_key_slow_inc(&kvm_no_apic_vcpu);
7031 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7033 if (!vcpu->arch.mce_banks) {
7035 goto fail_free_lapic;
7037 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7039 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7041 goto fail_free_mce_banks;
7046 goto fail_free_wbinvd_dirty_mask;
7048 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7049 vcpu->arch.pv_time_enabled = false;
7051 vcpu->arch.guest_supported_xcr0 = 0;
7052 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7054 kvm_async_pf_hash_reset(vcpu);
7058 fail_free_wbinvd_dirty_mask:
7059 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7060 fail_free_mce_banks:
7061 kfree(vcpu->arch.mce_banks);
7063 kvm_free_lapic(vcpu);
7065 kvm_mmu_destroy(vcpu);
7067 free_page((unsigned long)vcpu->arch.pio_data);
7072 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7076 kvm_pmu_destroy(vcpu);
7077 kfree(vcpu->arch.mce_banks);
7078 kvm_free_lapic(vcpu);
7079 idx = srcu_read_lock(&vcpu->kvm->srcu);
7080 kvm_mmu_destroy(vcpu);
7081 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7082 free_page((unsigned long)vcpu->arch.pio_data);
7083 if (!irqchip_in_kernel(vcpu->kvm))
7084 static_key_slow_dec(&kvm_no_apic_vcpu);
7087 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7092 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7093 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7094 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7095 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7097 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7098 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7099 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7100 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7101 &kvm->arch.irq_sources_bitmap);
7103 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7104 mutex_init(&kvm->arch.apic_map_lock);
7105 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7107 pvclock_update_vm_gtod_copy(kvm);
7109 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7110 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7115 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7118 r = vcpu_load(vcpu);
7120 kvm_mmu_unload(vcpu);
7124 static void kvm_free_vcpus(struct kvm *kvm)
7127 struct kvm_vcpu *vcpu;
7130 * Unpin any mmu pages first.
7132 kvm_for_each_vcpu(i, vcpu, kvm) {
7133 kvm_clear_async_pf_completion_queue(vcpu);
7134 kvm_unload_vcpu_mmu(vcpu);
7136 kvm_for_each_vcpu(i, vcpu, kvm)
7137 kvm_arch_vcpu_free(vcpu);
7139 mutex_lock(&kvm->lock);
7140 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7141 kvm->vcpus[i] = NULL;
7143 atomic_set(&kvm->online_vcpus, 0);
7144 mutex_unlock(&kvm->lock);
7147 void kvm_arch_sync_events(struct kvm *kvm)
7149 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7150 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7151 kvm_free_all_assigned_devices(kvm);
7155 void kvm_arch_destroy_vm(struct kvm *kvm)
7157 if (current->mm == kvm->mm) {
7159 * Free memory regions allocated on behalf of userspace,
7160 * unless the the memory map has changed due to process exit
7163 struct kvm_userspace_memory_region mem;
7164 memset(&mem, 0, sizeof(mem));
7165 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7166 kvm_set_memory_region(kvm, &mem);
7168 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7169 kvm_set_memory_region(kvm, &mem);
7171 mem.slot = TSS_PRIVATE_MEMSLOT;
7172 kvm_set_memory_region(kvm, &mem);
7174 kvm_iommu_unmap_guest(kvm);
7175 kfree(kvm->arch.vpic);
7176 kfree(kvm->arch.vioapic);
7177 kvm_free_vcpus(kvm);
7178 if (kvm->arch.apic_access_page)
7179 put_page(kvm->arch.apic_access_page);
7180 if (kvm->arch.ept_identity_pagetable)
7181 put_page(kvm->arch.ept_identity_pagetable);
7182 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7185 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7186 struct kvm_memory_slot *dont)
7190 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7191 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7192 kvm_kvfree(free->arch.rmap[i]);
7193 free->arch.rmap[i] = NULL;
7198 if (!dont || free->arch.lpage_info[i - 1] !=
7199 dont->arch.lpage_info[i - 1]) {
7200 kvm_kvfree(free->arch.lpage_info[i - 1]);
7201 free->arch.lpage_info[i - 1] = NULL;
7206 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7207 unsigned long npages)
7211 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7216 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7217 slot->base_gfn, level) + 1;
7219 slot->arch.rmap[i] =
7220 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7221 if (!slot->arch.rmap[i])
7226 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7227 sizeof(*slot->arch.lpage_info[i - 1]));
7228 if (!slot->arch.lpage_info[i - 1])
7231 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7232 slot->arch.lpage_info[i - 1][0].write_count = 1;
7233 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7234 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7235 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7237 * If the gfn and userspace address are not aligned wrt each
7238 * other, or if explicitly asked to, disable large page
7239 * support for this slot
7241 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7242 !kvm_largepages_enabled()) {
7245 for (j = 0; j < lpages; ++j)
7246 slot->arch.lpage_info[i - 1][j].write_count = 1;
7253 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7254 kvm_kvfree(slot->arch.rmap[i]);
7255 slot->arch.rmap[i] = NULL;
7259 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7260 slot->arch.lpage_info[i - 1] = NULL;
7265 void kvm_arch_memslots_updated(struct kvm *kvm)
7268 * memslots->generation has been incremented.
7269 * mmio generation may have reached its maximum value.
7271 kvm_mmu_invalidate_mmio_sptes(kvm);
7274 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7275 struct kvm_memory_slot *memslot,
7276 struct kvm_userspace_memory_region *mem,
7277 enum kvm_mr_change change)
7280 * Only private memory slots need to be mapped here since
7281 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7283 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7284 unsigned long userspace_addr;
7287 * MAP_SHARED to prevent internal slot pages from being moved
7290 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7291 PROT_READ | PROT_WRITE,
7292 MAP_SHARED | MAP_ANONYMOUS, 0);
7294 if (IS_ERR((void *)userspace_addr))
7295 return PTR_ERR((void *)userspace_addr);
7297 memslot->userspace_addr = userspace_addr;
7303 void kvm_arch_commit_memory_region(struct kvm *kvm,
7304 struct kvm_userspace_memory_region *mem,
7305 const struct kvm_memory_slot *old,
7306 enum kvm_mr_change change)
7309 int nr_mmu_pages = 0;
7311 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7314 ret = vm_munmap(old->userspace_addr,
7315 old->npages * PAGE_SIZE);
7318 "kvm_vm_ioctl_set_memory_region: "
7319 "failed to munmap memory\n");
7322 if (!kvm->arch.n_requested_mmu_pages)
7323 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7326 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7328 * Write protect all pages for dirty logging.
7330 * All the sptes including the large sptes which point to this
7331 * slot are set to readonly. We can not create any new large
7332 * spte on this slot until the end of the logging.
7334 * See the comments in fast_page_fault().
7336 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7337 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7340 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7342 kvm_mmu_invalidate_zap_all_pages(kvm);
7345 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7346 struct kvm_memory_slot *slot)
7348 kvm_mmu_invalidate_zap_all_pages(kvm);
7351 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7353 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7354 kvm_x86_ops->check_nested_events(vcpu, false);
7356 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7357 !vcpu->arch.apf.halted)
7358 || !list_empty_careful(&vcpu->async_pf.done)
7359 || kvm_apic_has_events(vcpu)
7360 || vcpu->arch.pv.pv_unhalted
7361 || atomic_read(&vcpu->arch.nmi_queued) ||
7362 (kvm_arch_interrupt_allowed(vcpu) &&
7363 kvm_cpu_has_interrupt(vcpu));
7366 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7368 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7371 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7373 return kvm_x86_ops->interrupt_allowed(vcpu);
7376 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7378 unsigned long current_rip = kvm_rip_read(vcpu) +
7379 get_segment_base(vcpu, VCPU_SREG_CS);
7381 return current_rip == linear_rip;
7383 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7385 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7387 unsigned long rflags;
7389 rflags = kvm_x86_ops->get_rflags(vcpu);
7390 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7391 rflags &= ~X86_EFLAGS_TF;
7394 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7396 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7398 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7399 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7400 rflags |= X86_EFLAGS_TF;
7401 kvm_x86_ops->set_rflags(vcpu, rflags);
7402 kvm_make_request(KVM_REQ_EVENT, vcpu);
7404 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7406 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7410 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7414 r = kvm_mmu_reload(vcpu);
7418 if (!vcpu->arch.mmu.direct_map &&
7419 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7422 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7425 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7427 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7430 static inline u32 kvm_async_pf_next_probe(u32 key)
7432 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7435 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7437 u32 key = kvm_async_pf_hash_fn(gfn);
7439 while (vcpu->arch.apf.gfns[key] != ~0)
7440 key = kvm_async_pf_next_probe(key);
7442 vcpu->arch.apf.gfns[key] = gfn;
7445 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7448 u32 key = kvm_async_pf_hash_fn(gfn);
7450 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7451 (vcpu->arch.apf.gfns[key] != gfn &&
7452 vcpu->arch.apf.gfns[key] != ~0); i++)
7453 key = kvm_async_pf_next_probe(key);
7458 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7460 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7463 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7467 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7469 vcpu->arch.apf.gfns[i] = ~0;
7471 j = kvm_async_pf_next_probe(j);
7472 if (vcpu->arch.apf.gfns[j] == ~0)
7474 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7476 * k lies cyclically in ]i,j]
7478 * |....j i.k.| or |.k..j i...|
7480 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7481 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7486 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7489 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7493 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7494 struct kvm_async_pf *work)
7496 struct x86_exception fault;
7498 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7499 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7501 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7502 (vcpu->arch.apf.send_user_only &&
7503 kvm_x86_ops->get_cpl(vcpu) == 0))
7504 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7505 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7506 fault.vector = PF_VECTOR;
7507 fault.error_code_valid = true;
7508 fault.error_code = 0;
7509 fault.nested_page_fault = false;
7510 fault.address = work->arch.token;
7511 kvm_inject_page_fault(vcpu, &fault);
7515 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7516 struct kvm_async_pf *work)
7518 struct x86_exception fault;
7520 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7521 if (work->wakeup_all)
7522 work->arch.token = ~0; /* broadcast wakeup */
7524 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7526 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7527 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7528 fault.vector = PF_VECTOR;
7529 fault.error_code_valid = true;
7530 fault.error_code = 0;
7531 fault.nested_page_fault = false;
7532 fault.address = work->arch.token;
7533 kvm_inject_page_fault(vcpu, &fault);
7535 vcpu->arch.apf.halted = false;
7536 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7539 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7541 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7544 return !kvm_event_needs_reinjection(vcpu) &&
7545 kvm_x86_ops->interrupt_allowed(vcpu);
7548 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7550 atomic_inc(&kvm->arch.noncoherent_dma_count);
7552 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7554 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7556 atomic_dec(&kvm->arch.noncoherent_dma_count);
7558 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7560 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7562 return atomic_read(&kvm->arch.noncoherent_dma_count);
7564 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);