2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
53 #define CREATE_TRACE_POINTS
56 #include <asm/debugreg.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92 struct kvm_x86_ops *kvm_x86_ops;
93 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95 static bool ignore_msrs = 0;
96 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98 unsigned int min_timer_period_us = 500;
99 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101 bool kvm_has_tsc_control;
102 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103 u32 kvm_max_guest_tsc_khz;
104 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107 static u32 tsc_tolerance_ppm = 250;
108 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110 static bool backwards_tsc_observed = false;
112 #define KVM_NR_SHARED_MSRS 16
114 struct kvm_shared_msrs_global {
116 u32 msrs[KVM_NR_SHARED_MSRS];
119 struct kvm_shared_msrs {
120 struct user_return_notifier urn;
122 struct kvm_shared_msr_values {
125 } values[KVM_NR_SHARED_MSRS];
128 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
129 static struct kvm_shared_msrs __percpu *shared_msrs;
131 struct kvm_stats_debugfs_item debugfs_entries[] = {
132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
144 { "hypercalls", VCPU_STAT(hypercalls) },
145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
152 { "irq_injections", VCPU_STAT(irq_injections) },
153 { "nmi_injections", VCPU_STAT(nmi_injections) },
154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
161 { "mmu_unsync", VM_STAT(mmu_unsync) },
162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
163 { "largepages", VM_STAT(lpages) },
167 u64 __read_mostly host_xcr0;
169 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
171 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
178 static void kvm_on_user_return(struct user_return_notifier *urn)
181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
183 struct kvm_shared_msr_values *values;
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
196 static void shared_msr_update(unsigned slot, u32 msr)
199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
213 void kvm_define_shared_msr(unsigned slot, u32 msr)
215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
222 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
224 static void kvm_shared_msr_cpu_online(void)
228 for (i = 0; i < shared_msrs_global.nr; ++i)
229 shared_msr_update(i, shared_msrs_global.msrs[i]);
232 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
237 if (((value ^ smsr->values[slot].curr) & mask) == 0)
239 smsr->values[slot].curr = value;
240 wrmsrl(shared_msrs_global.msrs[slot], value);
241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
247 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
249 static void drop_user_return_notifiers(void)
251 unsigned int cpu = smp_processor_id();
252 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
254 if (smsr->registered)
255 kvm_on_user_return(&smsr->urn);
258 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
260 return vcpu->arch.apic_base;
262 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
264 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
266 u64 old_state = vcpu->arch.apic_base &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 new_state = msr_info->data &
269 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
270 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
271 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
273 if (!msr_info->host_initiated &&
274 ((msr_info->data & reserved_bits) != 0 ||
275 new_state == X2APIC_ENABLE ||
276 (new_state == MSR_IA32_APICBASE_ENABLE &&
277 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
278 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
282 kvm_lapic_set_base(vcpu, msr_info->data);
285 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
287 asmlinkage __visible void kvm_spurious_fault(void)
289 /* Fault while not rebooting. We want the trace. */
292 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
294 #define EXCPT_BENIGN 0
295 #define EXCPT_CONTRIBUTORY 1
298 static int exception_class(int vector)
308 return EXCPT_CONTRIBUTORY;
315 #define EXCPT_FAULT 0
317 #define EXCPT_ABORT 2
318 #define EXCPT_INTERRUPT 3
320 static int exception_type(int vector)
324 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
325 return EXCPT_INTERRUPT;
329 /* #DB is trap, as instruction watchpoints are handled elsewhere */
330 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
333 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
336 /* Reserved exceptions will result in fault */
340 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
341 unsigned nr, bool has_error, u32 error_code,
347 kvm_make_request(KVM_REQ_EVENT, vcpu);
349 if (!vcpu->arch.exception.pending) {
351 vcpu->arch.exception.pending = true;
352 vcpu->arch.exception.has_error_code = has_error;
353 vcpu->arch.exception.nr = nr;
354 vcpu->arch.exception.error_code = error_code;
355 vcpu->arch.exception.reinject = reinject;
359 /* to check exception */
360 prev_nr = vcpu->arch.exception.nr;
361 if (prev_nr == DF_VECTOR) {
362 /* triple fault -> shutdown */
363 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
366 class1 = exception_class(prev_nr);
367 class2 = exception_class(nr);
368 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
369 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
370 /* generate double fault per SDM Table 5-5 */
371 vcpu->arch.exception.pending = true;
372 vcpu->arch.exception.has_error_code = true;
373 vcpu->arch.exception.nr = DF_VECTOR;
374 vcpu->arch.exception.error_code = 0;
376 /* replace previous exception with a new one in a hope
377 that instruction re-execution will regenerate lost
382 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
384 kvm_multiple_exception(vcpu, nr, false, 0, false);
386 EXPORT_SYMBOL_GPL(kvm_queue_exception);
388 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
390 kvm_multiple_exception(vcpu, nr, false, 0, true);
392 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
394 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
397 kvm_inject_gp(vcpu, 0);
399 kvm_x86_ops->skip_emulated_instruction(vcpu);
401 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
403 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
405 ++vcpu->stat.pf_guest;
406 vcpu->arch.cr2 = fault->address;
407 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
409 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
411 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
413 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
414 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
416 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
418 return fault->nested_page_fault;
421 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
423 atomic_inc(&vcpu->arch.nmi_queued);
424 kvm_make_request(KVM_REQ_NMI, vcpu);
426 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
428 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
430 kvm_multiple_exception(vcpu, nr, true, error_code, false);
432 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
434 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
436 kvm_multiple_exception(vcpu, nr, true, error_code, true);
438 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
441 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
442 * a #GP and return false.
444 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
446 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
448 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
451 EXPORT_SYMBOL_GPL(kvm_require_cpl);
454 * This function will be used to read from the physical memory of the currently
455 * running guest. The difference to kvm_read_guest_page is that this function
456 * can read from guest physical or from the guest's guest physical memory.
458 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
459 gfn_t ngfn, void *data, int offset, int len,
462 struct x86_exception exception;
466 ngpa = gfn_to_gpa(ngfn);
467 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
468 if (real_gfn == UNMAPPED_GVA)
471 real_gfn = gpa_to_gfn(real_gfn);
473 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
475 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
477 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
478 void *data, int offset, int len, u32 access)
480 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
481 data, offset, len, access);
485 * Load the pae pdptrs. Return true is they are all valid.
487 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
489 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
490 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
493 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
495 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
496 offset * sizeof(u64), sizeof(pdpte),
497 PFERR_USER_MASK|PFERR_WRITE_MASK);
502 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
503 if (is_present_gpte(pdpte[i]) &&
504 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
511 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
512 __set_bit(VCPU_EXREG_PDPTR,
513 (unsigned long *)&vcpu->arch.regs_avail);
514 __set_bit(VCPU_EXREG_PDPTR,
515 (unsigned long *)&vcpu->arch.regs_dirty);
520 EXPORT_SYMBOL_GPL(load_pdptrs);
522 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
524 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
530 if (is_long_mode(vcpu) || !is_pae(vcpu))
533 if (!test_bit(VCPU_EXREG_PDPTR,
534 (unsigned long *)&vcpu->arch.regs_avail))
537 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
538 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
539 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
540 PFERR_USER_MASK | PFERR_WRITE_MASK);
543 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
549 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
551 unsigned long old_cr0 = kvm_read_cr0(vcpu);
552 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
553 X86_CR0_CD | X86_CR0_NW;
558 if (cr0 & 0xffffffff00000000UL)
562 cr0 &= ~CR0_RESERVED_BITS;
564 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
567 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
570 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
572 if ((vcpu->arch.efer & EFER_LME)) {
577 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
582 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
587 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
590 kvm_x86_ops->set_cr0(vcpu, cr0);
592 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
593 kvm_clear_async_pf_completion_queue(vcpu);
594 kvm_async_pf_hash_reset(vcpu);
597 if ((cr0 ^ old_cr0) & update_bits)
598 kvm_mmu_reset_context(vcpu);
601 EXPORT_SYMBOL_GPL(kvm_set_cr0);
603 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
605 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
607 EXPORT_SYMBOL_GPL(kvm_lmsw);
609 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
611 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
612 !vcpu->guest_xcr0_loaded) {
613 /* kvm_set_xcr() also depends on this */
614 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
615 vcpu->guest_xcr0_loaded = 1;
619 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
621 if (vcpu->guest_xcr0_loaded) {
622 if (vcpu->arch.xcr0 != host_xcr0)
623 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
624 vcpu->guest_xcr0_loaded = 0;
628 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631 u64 old_xcr0 = vcpu->arch.xcr0;
634 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
635 if (index != XCR_XFEATURE_ENABLED_MASK)
637 if (!(xcr0 & XSTATE_FP))
639 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
643 * Do not allow the guest to set bits that we do not support
644 * saving. However, xcr0 bit 0 is always set, even if the
645 * emulated CPU does not support XSAVE (see fx_init).
647 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
648 if (xcr0 & ~valid_bits)
651 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
654 kvm_put_guest_xcr0(vcpu);
655 vcpu->arch.xcr0 = xcr0;
657 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
658 kvm_update_cpuid(vcpu);
662 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
664 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
665 __kvm_set_xcr(vcpu, index, xcr)) {
666 kvm_inject_gp(vcpu, 0);
671 EXPORT_SYMBOL_GPL(kvm_set_xcr);
673 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
675 unsigned long old_cr4 = kvm_read_cr4(vcpu);
676 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
677 X86_CR4_PAE | X86_CR4_SMEP;
678 if (cr4 & CR4_RESERVED_BITS)
681 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
684 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
687 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
690 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
693 if (is_long_mode(vcpu)) {
694 if (!(cr4 & X86_CR4_PAE))
696 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
697 && ((cr4 ^ old_cr4) & pdptr_bits)
698 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
702 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
703 if (!guest_cpuid_has_pcid(vcpu))
706 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
707 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
711 if (kvm_x86_ops->set_cr4(vcpu, cr4))
714 if (((cr4 ^ old_cr4) & pdptr_bits) ||
715 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
716 kvm_mmu_reset_context(vcpu);
718 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
719 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
721 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
722 kvm_update_cpuid(vcpu);
726 EXPORT_SYMBOL_GPL(kvm_set_cr4);
728 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
730 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
731 kvm_mmu_sync_roots(vcpu);
732 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
736 if (is_long_mode(vcpu)) {
737 if (cr3 & CR3_L_MODE_RESERVED_BITS)
739 } else if (is_pae(vcpu) && is_paging(vcpu) &&
740 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
743 vcpu->arch.cr3 = cr3;
744 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
745 kvm_mmu_new_cr3(vcpu);
748 EXPORT_SYMBOL_GPL(kvm_set_cr3);
750 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
752 if (cr8 & CR8_RESERVED_BITS)
754 if (irqchip_in_kernel(vcpu->kvm))
755 kvm_lapic_set_tpr(vcpu, cr8);
757 vcpu->arch.cr8 = cr8;
760 EXPORT_SYMBOL_GPL(kvm_set_cr8);
762 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
764 if (irqchip_in_kernel(vcpu->kvm))
765 return kvm_lapic_get_cr8(vcpu);
767 return vcpu->arch.cr8;
769 EXPORT_SYMBOL_GPL(kvm_get_cr8);
771 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
773 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
774 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
777 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
781 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
782 dr7 = vcpu->arch.guest_debug_dr7;
784 dr7 = vcpu->arch.dr7;
785 kvm_x86_ops->set_dr7(vcpu, dr7);
786 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
787 if (dr7 & DR7_BP_EN_MASK)
788 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
791 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
793 u64 fixed = DR6_FIXED_1;
795 if (!guest_cpuid_has_rtm(vcpu))
800 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
804 vcpu->arch.db[dr] = val;
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
806 vcpu->arch.eff_db[dr] = val;
809 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
813 if (val & 0xffffffff00000000ULL)
815 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
816 kvm_update_dr6(vcpu);
819 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
823 if (val & 0xffffffff00000000ULL)
825 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
826 kvm_update_dr7(vcpu);
833 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
837 res = __kvm_set_dr(vcpu, dr, val);
839 kvm_queue_exception(vcpu, UD_VECTOR);
841 kvm_inject_gp(vcpu, 0);
845 EXPORT_SYMBOL_GPL(kvm_set_dr);
847 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
851 *val = vcpu->arch.db[dr];
854 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
858 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
859 *val = vcpu->arch.dr6;
861 *val = kvm_x86_ops->get_dr6(vcpu);
864 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
868 *val = vcpu->arch.dr7;
875 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
877 if (_kvm_get_dr(vcpu, dr, val)) {
878 kvm_queue_exception(vcpu, UD_VECTOR);
883 EXPORT_SYMBOL_GPL(kvm_get_dr);
885 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
887 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
891 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
894 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
895 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
898 EXPORT_SYMBOL_GPL(kvm_rdpmc);
901 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
902 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
904 * This list is modified at module load time to reflect the
905 * capabilities of the host cpu. This capabilities test skips MSRs that are
906 * kvm-specific. Those are put in the beginning of the list.
909 #define KVM_SAVE_MSRS_BEGIN 12
910 static u32 msrs_to_save[] = {
911 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
912 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
913 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
914 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
915 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
917 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
920 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
922 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
923 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
926 static unsigned num_msrs_to_save;
928 static const u32 emulated_msrs[] = {
930 MSR_IA32_TSCDEADLINE,
931 MSR_IA32_MISC_ENABLE,
936 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
938 if (efer & efer_reserved_bits)
941 if (efer & EFER_FFXSR) {
942 struct kvm_cpuid_entry2 *feat;
944 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
945 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
949 if (efer & EFER_SVME) {
950 struct kvm_cpuid_entry2 *feat;
952 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
953 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
959 EXPORT_SYMBOL_GPL(kvm_valid_efer);
961 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
963 u64 old_efer = vcpu->arch.efer;
965 if (!kvm_valid_efer(vcpu, efer))
969 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
973 efer |= vcpu->arch.efer & EFER_LMA;
975 kvm_x86_ops->set_efer(vcpu, efer);
977 /* Update reserved bits */
978 if ((efer ^ old_efer) & EFER_NX)
979 kvm_mmu_reset_context(vcpu);
984 void kvm_enable_efer_bits(u64 mask)
986 efer_reserved_bits &= ~mask;
988 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
992 * Writes msr value into into the appropriate "register".
993 * Returns 0 on success, non-0 otherwise.
994 * Assumes vcpu_load() was already called.
996 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
998 return kvm_x86_ops->set_msr(vcpu, msr);
1002 * Adapt set_msr() to msr_io()'s calling convention
1004 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1006 struct msr_data msr;
1010 msr.host_initiated = true;
1011 return kvm_set_msr(vcpu, &msr);
1014 #ifdef CONFIG_X86_64
1015 struct pvclock_gtod_data {
1018 struct { /* extract of a clocksource struct */
1030 static struct pvclock_gtod_data pvclock_gtod_data;
1032 static void update_pvclock_gtod(struct timekeeper *tk)
1034 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1037 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
1039 write_seqcount_begin(&vdata->seq);
1041 /* copy pvclock gtod data */
1042 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1043 vdata->clock.cycle_last = tk->tkr.cycle_last;
1044 vdata->clock.mask = tk->tkr.mask;
1045 vdata->clock.mult = tk->tkr.mult;
1046 vdata->clock.shift = tk->tkr.shift;
1048 vdata->boot_ns = boot_ns;
1049 vdata->nsec_base = tk->tkr.xtime_nsec;
1051 write_seqcount_end(&vdata->seq);
1056 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1060 struct pvclock_wall_clock wc;
1061 struct timespec boot;
1066 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1071 ++version; /* first time write, random junk */
1075 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1078 * The guest calculates current wall clock time by adding
1079 * system time (updated by kvm_guest_time_update below) to the
1080 * wall clock specified here. guest system time equals host
1081 * system time for us, thus we must fill in host boot time here.
1085 if (kvm->arch.kvmclock_offset) {
1086 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1087 boot = timespec_sub(boot, ts);
1089 wc.sec = boot.tv_sec;
1090 wc.nsec = boot.tv_nsec;
1091 wc.version = version;
1093 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1096 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1099 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1101 uint32_t quotient, remainder;
1103 /* Don't try to replace with do_div(), this one calculates
1104 * "(dividend << 32) / divisor" */
1106 : "=a" (quotient), "=d" (remainder)
1107 : "0" (0), "1" (dividend), "r" (divisor) );
1111 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1112 s8 *pshift, u32 *pmultiplier)
1119 tps64 = base_khz * 1000LL;
1120 scaled64 = scaled_khz * 1000LL;
1121 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1126 tps32 = (uint32_t)tps64;
1127 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1128 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1136 *pmultiplier = div_frac(scaled64, tps32);
1138 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1139 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1142 static inline u64 get_kernel_ns(void)
1144 return ktime_get_boot_ns();
1147 #ifdef CONFIG_X86_64
1148 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1151 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1152 unsigned long max_tsc_khz;
1154 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1156 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1157 vcpu->arch.virtual_tsc_shift);
1160 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1162 u64 v = (u64)khz * (1000000 + ppm);
1167 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1169 u32 thresh_lo, thresh_hi;
1170 int use_scaling = 0;
1172 /* tsc_khz can be zero if TSC calibration fails */
1173 if (this_tsc_khz == 0)
1176 /* Compute a scale to convert nanoseconds in TSC cycles */
1177 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1178 &vcpu->arch.virtual_tsc_shift,
1179 &vcpu->arch.virtual_tsc_mult);
1180 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1183 * Compute the variation in TSC rate which is acceptable
1184 * within the range of tolerance and decide if the
1185 * rate being applied is within that bounds of the hardware
1186 * rate. If so, no scaling or compensation need be done.
1188 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1189 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1190 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1191 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1194 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1197 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1199 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1200 vcpu->arch.virtual_tsc_mult,
1201 vcpu->arch.virtual_tsc_shift);
1202 tsc += vcpu->arch.this_tsc_write;
1206 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1208 #ifdef CONFIG_X86_64
1210 bool do_request = false;
1211 struct kvm_arch *ka = &vcpu->kvm->arch;
1212 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1214 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1215 atomic_read(&vcpu->kvm->online_vcpus));
1217 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1218 if (!ka->use_master_clock)
1221 if (!vcpus_matched && ka->use_master_clock)
1225 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1227 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1228 atomic_read(&vcpu->kvm->online_vcpus),
1229 ka->use_master_clock, gtod->clock.vclock_mode);
1233 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1235 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1236 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1239 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1241 struct kvm *kvm = vcpu->kvm;
1242 u64 offset, ns, elapsed;
1243 unsigned long flags;
1246 bool already_matched;
1247 u64 data = msr->data;
1249 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1250 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1251 ns = get_kernel_ns();
1252 elapsed = ns - kvm->arch.last_tsc_nsec;
1254 if (vcpu->arch.virtual_tsc_khz) {
1257 /* n.b - signed multiplication and division required */
1258 usdiff = data - kvm->arch.last_tsc_write;
1259 #ifdef CONFIG_X86_64
1260 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1262 /* do_div() only does unsigned */
1263 asm("1: idivl %[divisor]\n"
1264 "2: xor %%edx, %%edx\n"
1265 " movl $0, %[faulted]\n"
1267 ".section .fixup,\"ax\"\n"
1268 "4: movl $1, %[faulted]\n"
1272 _ASM_EXTABLE(1b, 4b)
1274 : "=A"(usdiff), [faulted] "=r" (faulted)
1275 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1278 do_div(elapsed, 1000);
1283 /* idivl overflow => difference is larger than USEC_PER_SEC */
1285 usdiff = USEC_PER_SEC;
1287 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1290 * Special case: TSC write with a small delta (1 second) of virtual
1291 * cycle time against real time is interpreted as an attempt to
1292 * synchronize the CPU.
1294 * For a reliable TSC, we can match TSC offsets, and for an unstable
1295 * TSC, we add elapsed time in this computation. We could let the
1296 * compensation code attempt to catch up if we fall behind, but
1297 * it's better to try to match offsets from the beginning.
1299 if (usdiff < USEC_PER_SEC &&
1300 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1301 if (!check_tsc_unstable()) {
1302 offset = kvm->arch.cur_tsc_offset;
1303 pr_debug("kvm: matched tsc offset for %llu\n", data);
1305 u64 delta = nsec_to_cycles(vcpu, elapsed);
1307 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1308 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1311 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1314 * We split periods of matched TSC writes into generations.
1315 * For each generation, we track the original measured
1316 * nanosecond time, offset, and write, so if TSCs are in
1317 * sync, we can match exact offset, and if not, we can match
1318 * exact software computation in compute_guest_tsc()
1320 * These values are tracked in kvm->arch.cur_xxx variables.
1322 kvm->arch.cur_tsc_generation++;
1323 kvm->arch.cur_tsc_nsec = ns;
1324 kvm->arch.cur_tsc_write = data;
1325 kvm->arch.cur_tsc_offset = offset;
1327 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1328 kvm->arch.cur_tsc_generation, data);
1332 * We also track th most recent recorded KHZ, write and time to
1333 * allow the matching interval to be extended at each write.
1335 kvm->arch.last_tsc_nsec = ns;
1336 kvm->arch.last_tsc_write = data;
1337 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1339 vcpu->arch.last_guest_tsc = data;
1341 /* Keep track of which generation this VCPU has synchronized to */
1342 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1343 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1344 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1346 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1347 update_ia32_tsc_adjust_msr(vcpu, offset);
1348 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1349 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1351 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1353 kvm->arch.nr_vcpus_matched_tsc = 0;
1354 } else if (!already_matched) {
1355 kvm->arch.nr_vcpus_matched_tsc++;
1358 kvm_track_tsc_matching(vcpu);
1359 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1362 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1364 #ifdef CONFIG_X86_64
1366 static cycle_t read_tsc(void)
1372 * Empirically, a fence (of type that depends on the CPU)
1373 * before rdtsc is enough to ensure that rdtsc is ordered
1374 * with respect to loads. The various CPU manuals are unclear
1375 * as to whether rdtsc can be reordered with later loads,
1376 * but no one has ever seen it happen.
1379 ret = (cycle_t)vget_cycles();
1381 last = pvclock_gtod_data.clock.cycle_last;
1383 if (likely(ret >= last))
1387 * GCC likes to generate cmov here, but this branch is extremely
1388 * predictable (it's just a funciton of time and the likely is
1389 * very likely) and there's a data dependence, so force GCC
1390 * to generate a branch instead. I don't barrier() because
1391 * we don't actually need a barrier, and if this function
1392 * ever gets inlined it will generate worse code.
1398 static inline u64 vgettsc(cycle_t *cycle_now)
1401 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1403 *cycle_now = read_tsc();
1405 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1406 return v * gtod->clock.mult;
1409 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1411 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1417 seq = read_seqcount_begin(>od->seq);
1418 mode = gtod->clock.vclock_mode;
1419 ns = gtod->nsec_base;
1420 ns += vgettsc(cycle_now);
1421 ns >>= gtod->clock.shift;
1422 ns += gtod->boot_ns;
1423 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1429 /* returns true if host is using tsc clocksource */
1430 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1432 /* checked again under seqlock below */
1433 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1436 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1442 * Assuming a stable TSC across physical CPUS, and a stable TSC
1443 * across virtual CPUs, the following condition is possible.
1444 * Each numbered line represents an event visible to both
1445 * CPUs at the next numbered event.
1447 * "timespecX" represents host monotonic time. "tscX" represents
1450 * VCPU0 on CPU0 | VCPU1 on CPU1
1452 * 1. read timespec0,tsc0
1453 * 2. | timespec1 = timespec0 + N
1455 * 3. transition to guest | transition to guest
1456 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1457 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1458 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1460 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1463 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1465 * - 0 < N - M => M < N
1467 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1468 * always the case (the difference between two distinct xtime instances
1469 * might be smaller then the difference between corresponding TSC reads,
1470 * when updating guest vcpus pvclock areas).
1472 * To avoid that problem, do not allow visibility of distinct
1473 * system_timestamp/tsc_timestamp values simultaneously: use a master
1474 * copy of host monotonic time values. Update that master copy
1477 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1481 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1483 #ifdef CONFIG_X86_64
1484 struct kvm_arch *ka = &kvm->arch;
1486 bool host_tsc_clocksource, vcpus_matched;
1488 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1489 atomic_read(&kvm->online_vcpus));
1492 * If the host uses TSC clock, then passthrough TSC as stable
1495 host_tsc_clocksource = kvm_get_time_and_clockread(
1496 &ka->master_kernel_ns,
1497 &ka->master_cycle_now);
1499 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1500 && !backwards_tsc_observed;
1502 if (ka->use_master_clock)
1503 atomic_set(&kvm_guest_has_master_clock, 1);
1505 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1506 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1511 static void kvm_gen_update_masterclock(struct kvm *kvm)
1513 #ifdef CONFIG_X86_64
1515 struct kvm_vcpu *vcpu;
1516 struct kvm_arch *ka = &kvm->arch;
1518 spin_lock(&ka->pvclock_gtod_sync_lock);
1519 kvm_make_mclock_inprogress_request(kvm);
1520 /* no guest entries from this point */
1521 pvclock_update_vm_gtod_copy(kvm);
1523 kvm_for_each_vcpu(i, vcpu, kvm)
1524 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1526 /* guest entries allowed */
1527 kvm_for_each_vcpu(i, vcpu, kvm)
1528 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1530 spin_unlock(&ka->pvclock_gtod_sync_lock);
1534 static int kvm_guest_time_update(struct kvm_vcpu *v)
1536 unsigned long flags, this_tsc_khz;
1537 struct kvm_vcpu_arch *vcpu = &v->arch;
1538 struct kvm_arch *ka = &v->kvm->arch;
1540 u64 tsc_timestamp, host_tsc;
1541 struct pvclock_vcpu_time_info guest_hv_clock;
1543 bool use_master_clock;
1549 * If the host uses TSC clock, then passthrough TSC as stable
1552 spin_lock(&ka->pvclock_gtod_sync_lock);
1553 use_master_clock = ka->use_master_clock;
1554 if (use_master_clock) {
1555 host_tsc = ka->master_cycle_now;
1556 kernel_ns = ka->master_kernel_ns;
1558 spin_unlock(&ka->pvclock_gtod_sync_lock);
1560 /* Keep irq disabled to prevent changes to the clock */
1561 local_irq_save(flags);
1562 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1563 if (unlikely(this_tsc_khz == 0)) {
1564 local_irq_restore(flags);
1565 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1568 if (!use_master_clock) {
1569 host_tsc = native_read_tsc();
1570 kernel_ns = get_kernel_ns();
1573 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1576 * We may have to catch up the TSC to match elapsed wall clock
1577 * time for two reasons, even if kvmclock is used.
1578 * 1) CPU could have been running below the maximum TSC rate
1579 * 2) Broken TSC compensation resets the base at each VCPU
1580 * entry to avoid unknown leaps of TSC even when running
1581 * again on the same CPU. This may cause apparent elapsed
1582 * time to disappear, and the guest to stand still or run
1585 if (vcpu->tsc_catchup) {
1586 u64 tsc = compute_guest_tsc(v, kernel_ns);
1587 if (tsc > tsc_timestamp) {
1588 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1589 tsc_timestamp = tsc;
1593 local_irq_restore(flags);
1595 if (!vcpu->pv_time_enabled)
1598 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1599 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1600 &vcpu->hv_clock.tsc_shift,
1601 &vcpu->hv_clock.tsc_to_system_mul);
1602 vcpu->hw_tsc_khz = this_tsc_khz;
1605 /* With all the info we got, fill in the values */
1606 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1607 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1608 vcpu->last_guest_tsc = tsc_timestamp;
1611 * The interface expects us to write an even number signaling that the
1612 * update is finished. Since the guest won't see the intermediate
1613 * state, we just increase by 2 at the end.
1615 vcpu->hv_clock.version += 2;
1617 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1618 &guest_hv_clock, sizeof(guest_hv_clock))))
1621 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1622 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1624 if (vcpu->pvclock_set_guest_stopped_request) {
1625 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1626 vcpu->pvclock_set_guest_stopped_request = false;
1629 /* If the host uses TSC clocksource, then it is stable */
1630 if (use_master_clock)
1631 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1633 vcpu->hv_clock.flags = pvclock_flags;
1635 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1637 sizeof(vcpu->hv_clock));
1642 * kvmclock updates which are isolated to a given vcpu, such as
1643 * vcpu->cpu migration, should not allow system_timestamp from
1644 * the rest of the vcpus to remain static. Otherwise ntp frequency
1645 * correction applies to one vcpu's system_timestamp but not
1648 * So in those cases, request a kvmclock update for all vcpus.
1649 * We need to rate-limit these requests though, as they can
1650 * considerably slow guests that have a large number of vcpus.
1651 * The time for a remote vcpu to update its kvmclock is bound
1652 * by the delay we use to rate-limit the updates.
1655 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1657 static void kvmclock_update_fn(struct work_struct *work)
1660 struct delayed_work *dwork = to_delayed_work(work);
1661 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1662 kvmclock_update_work);
1663 struct kvm *kvm = container_of(ka, struct kvm, arch);
1664 struct kvm_vcpu *vcpu;
1666 kvm_for_each_vcpu(i, vcpu, kvm) {
1667 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1668 kvm_vcpu_kick(vcpu);
1672 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1674 struct kvm *kvm = v->kvm;
1676 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1677 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1678 KVMCLOCK_UPDATE_DELAY);
1681 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1683 static void kvmclock_sync_fn(struct work_struct *work)
1685 struct delayed_work *dwork = to_delayed_work(work);
1686 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1687 kvmclock_sync_work);
1688 struct kvm *kvm = container_of(ka, struct kvm, arch);
1690 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1691 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1692 KVMCLOCK_SYNC_PERIOD);
1695 static bool msr_mtrr_valid(unsigned msr)
1698 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1699 case MSR_MTRRfix64K_00000:
1700 case MSR_MTRRfix16K_80000:
1701 case MSR_MTRRfix16K_A0000:
1702 case MSR_MTRRfix4K_C0000:
1703 case MSR_MTRRfix4K_C8000:
1704 case MSR_MTRRfix4K_D0000:
1705 case MSR_MTRRfix4K_D8000:
1706 case MSR_MTRRfix4K_E0000:
1707 case MSR_MTRRfix4K_E8000:
1708 case MSR_MTRRfix4K_F0000:
1709 case MSR_MTRRfix4K_F8000:
1710 case MSR_MTRRdefType:
1711 case MSR_IA32_CR_PAT:
1719 static bool valid_pat_type(unsigned t)
1721 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1724 static bool valid_mtrr_type(unsigned t)
1726 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1729 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1734 if (!msr_mtrr_valid(msr))
1737 if (msr == MSR_IA32_CR_PAT) {
1738 for (i = 0; i < 8; i++)
1739 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1742 } else if (msr == MSR_MTRRdefType) {
1745 return valid_mtrr_type(data & 0xff);
1746 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1747 for (i = 0; i < 8 ; i++)
1748 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1753 /* variable MTRRs */
1754 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1756 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1757 if ((msr & 1) == 0) {
1759 if (!valid_mtrr_type(data & 0xff))
1766 kvm_inject_gp(vcpu, 0);
1772 EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
1774 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1776 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1778 if (!kvm_mtrr_valid(vcpu, msr, data))
1781 if (msr == MSR_MTRRdefType) {
1782 vcpu->arch.mtrr_state.def_type = data;
1783 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1784 } else if (msr == MSR_MTRRfix64K_00000)
1786 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1787 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1788 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1789 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1790 else if (msr == MSR_IA32_CR_PAT)
1791 vcpu->arch.pat = data;
1792 else { /* Variable MTRRs */
1793 int idx, is_mtrr_mask;
1796 idx = (msr - 0x200) / 2;
1797 is_mtrr_mask = msr - 0x200 - 2 * idx;
1800 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1803 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1807 kvm_mmu_reset_context(vcpu);
1811 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1813 u64 mcg_cap = vcpu->arch.mcg_cap;
1814 unsigned bank_num = mcg_cap & 0xff;
1817 case MSR_IA32_MCG_STATUS:
1818 vcpu->arch.mcg_status = data;
1820 case MSR_IA32_MCG_CTL:
1821 if (!(mcg_cap & MCG_CTL_P))
1823 if (data != 0 && data != ~(u64)0)
1825 vcpu->arch.mcg_ctl = data;
1828 if (msr >= MSR_IA32_MC0_CTL &&
1829 msr < MSR_IA32_MCx_CTL(bank_num)) {
1830 u32 offset = msr - MSR_IA32_MC0_CTL;
1831 /* only 0 or all 1s can be written to IA32_MCi_CTL
1832 * some Linux kernels though clear bit 10 in bank 4 to
1833 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1834 * this to avoid an uncatched #GP in the guest
1836 if ((offset & 0x3) == 0 &&
1837 data != 0 && (data | (1 << 10)) != ~(u64)0)
1839 vcpu->arch.mce_banks[offset] = data;
1847 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1849 struct kvm *kvm = vcpu->kvm;
1850 int lm = is_long_mode(vcpu);
1851 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1852 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1853 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1854 : kvm->arch.xen_hvm_config.blob_size_32;
1855 u32 page_num = data & ~PAGE_MASK;
1856 u64 page_addr = data & PAGE_MASK;
1861 if (page_num >= blob_size)
1864 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1869 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1878 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1880 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1883 static bool kvm_hv_msr_partition_wide(u32 msr)
1887 case HV_X64_MSR_GUEST_OS_ID:
1888 case HV_X64_MSR_HYPERCALL:
1889 case HV_X64_MSR_REFERENCE_TSC:
1890 case HV_X64_MSR_TIME_REF_COUNT:
1898 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1900 struct kvm *kvm = vcpu->kvm;
1903 case HV_X64_MSR_GUEST_OS_ID:
1904 kvm->arch.hv_guest_os_id = data;
1905 /* setting guest os id to zero disables hypercall page */
1906 if (!kvm->arch.hv_guest_os_id)
1907 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1909 case HV_X64_MSR_HYPERCALL: {
1914 /* if guest os id is not set hypercall should remain disabled */
1915 if (!kvm->arch.hv_guest_os_id)
1917 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1918 kvm->arch.hv_hypercall = data;
1921 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1922 addr = gfn_to_hva(kvm, gfn);
1923 if (kvm_is_error_hva(addr))
1925 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1926 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1927 if (__copy_to_user((void __user *)addr, instructions, 4))
1929 kvm->arch.hv_hypercall = data;
1930 mark_page_dirty(kvm, gfn);
1933 case HV_X64_MSR_REFERENCE_TSC: {
1935 HV_REFERENCE_TSC_PAGE tsc_ref;
1936 memset(&tsc_ref, 0, sizeof(tsc_ref));
1937 kvm->arch.hv_tsc_page = data;
1938 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1940 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1941 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
1942 &tsc_ref, sizeof(tsc_ref)))
1944 mark_page_dirty(kvm, gfn);
1948 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1949 "data 0x%llx\n", msr, data);
1955 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1958 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1962 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1963 vcpu->arch.hv_vapic = data;
1964 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1968 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1969 addr = gfn_to_hva(vcpu->kvm, gfn);
1970 if (kvm_is_error_hva(addr))
1972 if (__clear_user((void __user *)addr, PAGE_SIZE))
1974 vcpu->arch.hv_vapic = data;
1975 mark_page_dirty(vcpu->kvm, gfn);
1976 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1980 case HV_X64_MSR_EOI:
1981 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1982 case HV_X64_MSR_ICR:
1983 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1984 case HV_X64_MSR_TPR:
1985 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1987 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1988 "data 0x%llx\n", msr, data);
1995 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1997 gpa_t gpa = data & ~0x3f;
1999 /* Bits 2:5 are reserved, Should be zero */
2003 vcpu->arch.apf.msr_val = data;
2005 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2006 kvm_clear_async_pf_completion_queue(vcpu);
2007 kvm_async_pf_hash_reset(vcpu);
2011 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2015 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2016 kvm_async_pf_wakeup_all(vcpu);
2020 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2022 vcpu->arch.pv_time_enabled = false;
2025 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2029 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2032 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2033 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2034 vcpu->arch.st.accum_steal = delta;
2037 static void record_steal_time(struct kvm_vcpu *vcpu)
2039 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2042 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2043 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2046 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2047 vcpu->arch.st.steal.version += 2;
2048 vcpu->arch.st.accum_steal = 0;
2050 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2051 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2054 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2057 u32 msr = msr_info->index;
2058 u64 data = msr_info->data;
2061 case MSR_AMD64_NB_CFG:
2062 case MSR_IA32_UCODE_REV:
2063 case MSR_IA32_UCODE_WRITE:
2064 case MSR_VM_HSAVE_PA:
2065 case MSR_AMD64_PATCH_LOADER:
2066 case MSR_AMD64_BU_CFG2:
2070 return set_efer(vcpu, data);
2072 data &= ~(u64)0x40; /* ignore flush filter disable */
2073 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2074 data &= ~(u64)0x8; /* ignore TLB cache disable */
2075 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2077 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2082 case MSR_FAM10H_MMIO_CONF_BASE:
2084 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2089 case MSR_IA32_DEBUGCTLMSR:
2091 /* We support the non-activated case already */
2093 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2094 /* Values other than LBR and BTF are vendor-specific,
2095 thus reserved and should throw a #GP */
2098 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2101 case 0x200 ... 0x2ff:
2102 return set_msr_mtrr(vcpu, msr, data);
2103 case MSR_IA32_APICBASE:
2104 return kvm_set_apic_base(vcpu, msr_info);
2105 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2106 return kvm_x2apic_msr_write(vcpu, msr, data);
2107 case MSR_IA32_TSCDEADLINE:
2108 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2110 case MSR_IA32_TSC_ADJUST:
2111 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2112 if (!msr_info->host_initiated) {
2113 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2114 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2116 vcpu->arch.ia32_tsc_adjust_msr = data;
2119 case MSR_IA32_MISC_ENABLE:
2120 vcpu->arch.ia32_misc_enable_msr = data;
2122 case MSR_KVM_WALL_CLOCK_NEW:
2123 case MSR_KVM_WALL_CLOCK:
2124 vcpu->kvm->arch.wall_clock = data;
2125 kvm_write_wall_clock(vcpu->kvm, data);
2127 case MSR_KVM_SYSTEM_TIME_NEW:
2128 case MSR_KVM_SYSTEM_TIME: {
2130 kvmclock_reset(vcpu);
2132 vcpu->arch.time = data;
2133 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2135 /* we verify if the enable bit is set... */
2139 gpa_offset = data & ~(PAGE_MASK | 1);
2141 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2142 &vcpu->arch.pv_time, data & ~1ULL,
2143 sizeof(struct pvclock_vcpu_time_info)))
2144 vcpu->arch.pv_time_enabled = false;
2146 vcpu->arch.pv_time_enabled = true;
2150 case MSR_KVM_ASYNC_PF_EN:
2151 if (kvm_pv_enable_async_pf(vcpu, data))
2154 case MSR_KVM_STEAL_TIME:
2156 if (unlikely(!sched_info_on()))
2159 if (data & KVM_STEAL_RESERVED_MASK)
2162 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2163 data & KVM_STEAL_VALID_BITS,
2164 sizeof(struct kvm_steal_time)))
2167 vcpu->arch.st.msr_val = data;
2169 if (!(data & KVM_MSR_ENABLED))
2172 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2175 accumulate_steal_time(vcpu);
2178 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2181 case MSR_KVM_PV_EOI_EN:
2182 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2186 case MSR_IA32_MCG_CTL:
2187 case MSR_IA32_MCG_STATUS:
2188 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2189 return set_msr_mce(vcpu, msr, data);
2191 /* Performance counters are not protected by a CPUID bit,
2192 * so we should check all of them in the generic path for the sake of
2193 * cross vendor migration.
2194 * Writing a zero into the event select MSRs disables them,
2195 * which we perfectly emulate ;-). Any other value should be at least
2196 * reported, some guests depend on them.
2198 case MSR_K7_EVNTSEL0:
2199 case MSR_K7_EVNTSEL1:
2200 case MSR_K7_EVNTSEL2:
2201 case MSR_K7_EVNTSEL3:
2203 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2204 "0x%x data 0x%llx\n", msr, data);
2206 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2207 * so we ignore writes to make it happy.
2209 case MSR_K7_PERFCTR0:
2210 case MSR_K7_PERFCTR1:
2211 case MSR_K7_PERFCTR2:
2212 case MSR_K7_PERFCTR3:
2213 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2214 "0x%x data 0x%llx\n", msr, data);
2216 case MSR_P6_PERFCTR0:
2217 case MSR_P6_PERFCTR1:
2219 case MSR_P6_EVNTSEL0:
2220 case MSR_P6_EVNTSEL1:
2221 if (kvm_pmu_msr(vcpu, msr))
2222 return kvm_pmu_set_msr(vcpu, msr_info);
2224 if (pr || data != 0)
2225 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2226 "0x%x data 0x%llx\n", msr, data);
2228 case MSR_K7_CLK_CTL:
2230 * Ignore all writes to this no longer documented MSR.
2231 * Writes are only relevant for old K7 processors,
2232 * all pre-dating SVM, but a recommended workaround from
2233 * AMD for these chips. It is possible to specify the
2234 * affected processor models on the command line, hence
2235 * the need to ignore the workaround.
2238 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2239 if (kvm_hv_msr_partition_wide(msr)) {
2241 mutex_lock(&vcpu->kvm->lock);
2242 r = set_msr_hyperv_pw(vcpu, msr, data);
2243 mutex_unlock(&vcpu->kvm->lock);
2246 return set_msr_hyperv(vcpu, msr, data);
2248 case MSR_IA32_BBL_CR_CTL3:
2249 /* Drop writes to this legacy MSR -- see rdmsr
2250 * counterpart for further detail.
2252 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2254 case MSR_AMD64_OSVW_ID_LENGTH:
2255 if (!guest_cpuid_has_osvw(vcpu))
2257 vcpu->arch.osvw.length = data;
2259 case MSR_AMD64_OSVW_STATUS:
2260 if (!guest_cpuid_has_osvw(vcpu))
2262 vcpu->arch.osvw.status = data;
2265 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2266 return xen_hvm_config(vcpu, data);
2267 if (kvm_pmu_msr(vcpu, msr))
2268 return kvm_pmu_set_msr(vcpu, msr_info);
2270 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2274 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2281 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2285 * Reads an msr value (of 'msr_index') into 'pdata'.
2286 * Returns 0 on success, non-0 otherwise.
2287 * Assumes vcpu_load() was already called.
2289 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2291 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2294 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2296 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2298 if (!msr_mtrr_valid(msr))
2301 if (msr == MSR_MTRRdefType)
2302 *pdata = vcpu->arch.mtrr_state.def_type +
2303 (vcpu->arch.mtrr_state.enabled << 10);
2304 else if (msr == MSR_MTRRfix64K_00000)
2306 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2307 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2308 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2309 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2310 else if (msr == MSR_IA32_CR_PAT)
2311 *pdata = vcpu->arch.pat;
2312 else { /* Variable MTRRs */
2313 int idx, is_mtrr_mask;
2316 idx = (msr - 0x200) / 2;
2317 is_mtrr_mask = msr - 0x200 - 2 * idx;
2320 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2323 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2330 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2333 u64 mcg_cap = vcpu->arch.mcg_cap;
2334 unsigned bank_num = mcg_cap & 0xff;
2337 case MSR_IA32_P5_MC_ADDR:
2338 case MSR_IA32_P5_MC_TYPE:
2341 case MSR_IA32_MCG_CAP:
2342 data = vcpu->arch.mcg_cap;
2344 case MSR_IA32_MCG_CTL:
2345 if (!(mcg_cap & MCG_CTL_P))
2347 data = vcpu->arch.mcg_ctl;
2349 case MSR_IA32_MCG_STATUS:
2350 data = vcpu->arch.mcg_status;
2353 if (msr >= MSR_IA32_MC0_CTL &&
2354 msr < MSR_IA32_MCx_CTL(bank_num)) {
2355 u32 offset = msr - MSR_IA32_MC0_CTL;
2356 data = vcpu->arch.mce_banks[offset];
2365 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2368 struct kvm *kvm = vcpu->kvm;
2371 case HV_X64_MSR_GUEST_OS_ID:
2372 data = kvm->arch.hv_guest_os_id;
2374 case HV_X64_MSR_HYPERCALL:
2375 data = kvm->arch.hv_hypercall;
2377 case HV_X64_MSR_TIME_REF_COUNT: {
2379 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2382 case HV_X64_MSR_REFERENCE_TSC:
2383 data = kvm->arch.hv_tsc_page;
2386 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2394 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2399 case HV_X64_MSR_VP_INDEX: {
2402 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2410 case HV_X64_MSR_EOI:
2411 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2412 case HV_X64_MSR_ICR:
2413 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2414 case HV_X64_MSR_TPR:
2415 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2416 case HV_X64_MSR_APIC_ASSIST_PAGE:
2417 data = vcpu->arch.hv_vapic;
2420 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2427 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2432 case MSR_IA32_PLATFORM_ID:
2433 case MSR_IA32_EBL_CR_POWERON:
2434 case MSR_IA32_DEBUGCTLMSR:
2435 case MSR_IA32_LASTBRANCHFROMIP:
2436 case MSR_IA32_LASTBRANCHTOIP:
2437 case MSR_IA32_LASTINTFROMIP:
2438 case MSR_IA32_LASTINTTOIP:
2441 case MSR_VM_HSAVE_PA:
2442 case MSR_K7_EVNTSEL0:
2443 case MSR_K7_EVNTSEL1:
2444 case MSR_K7_EVNTSEL2:
2445 case MSR_K7_EVNTSEL3:
2446 case MSR_K7_PERFCTR0:
2447 case MSR_K7_PERFCTR1:
2448 case MSR_K7_PERFCTR2:
2449 case MSR_K7_PERFCTR3:
2450 case MSR_K8_INT_PENDING_MSG:
2451 case MSR_AMD64_NB_CFG:
2452 case MSR_FAM10H_MMIO_CONF_BASE:
2453 case MSR_AMD64_BU_CFG2:
2456 case MSR_P6_PERFCTR0:
2457 case MSR_P6_PERFCTR1:
2458 case MSR_P6_EVNTSEL0:
2459 case MSR_P6_EVNTSEL1:
2460 if (kvm_pmu_msr(vcpu, msr))
2461 return kvm_pmu_get_msr(vcpu, msr, pdata);
2464 case MSR_IA32_UCODE_REV:
2465 data = 0x100000000ULL;
2468 data = 0x500 | KVM_NR_VAR_MTRR;
2470 case 0x200 ... 0x2ff:
2471 return get_msr_mtrr(vcpu, msr, pdata);
2472 case 0xcd: /* fsb frequency */
2476 * MSR_EBC_FREQUENCY_ID
2477 * Conservative value valid for even the basic CPU models.
2478 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2479 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2480 * and 266MHz for model 3, or 4. Set Core Clock
2481 * Frequency to System Bus Frequency Ratio to 1 (bits
2482 * 31:24) even though these are only valid for CPU
2483 * models > 2, however guests may end up dividing or
2484 * multiplying by zero otherwise.
2486 case MSR_EBC_FREQUENCY_ID:
2489 case MSR_IA32_APICBASE:
2490 data = kvm_get_apic_base(vcpu);
2492 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2493 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2495 case MSR_IA32_TSCDEADLINE:
2496 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2498 case MSR_IA32_TSC_ADJUST:
2499 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2501 case MSR_IA32_MISC_ENABLE:
2502 data = vcpu->arch.ia32_misc_enable_msr;
2504 case MSR_IA32_PERF_STATUS:
2505 /* TSC increment by tick */
2507 /* CPU multiplier */
2508 data |= (((uint64_t)4ULL) << 40);
2511 data = vcpu->arch.efer;
2513 case MSR_KVM_WALL_CLOCK:
2514 case MSR_KVM_WALL_CLOCK_NEW:
2515 data = vcpu->kvm->arch.wall_clock;
2517 case MSR_KVM_SYSTEM_TIME:
2518 case MSR_KVM_SYSTEM_TIME_NEW:
2519 data = vcpu->arch.time;
2521 case MSR_KVM_ASYNC_PF_EN:
2522 data = vcpu->arch.apf.msr_val;
2524 case MSR_KVM_STEAL_TIME:
2525 data = vcpu->arch.st.msr_val;
2527 case MSR_KVM_PV_EOI_EN:
2528 data = vcpu->arch.pv_eoi.msr_val;
2530 case MSR_IA32_P5_MC_ADDR:
2531 case MSR_IA32_P5_MC_TYPE:
2532 case MSR_IA32_MCG_CAP:
2533 case MSR_IA32_MCG_CTL:
2534 case MSR_IA32_MCG_STATUS:
2535 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2536 return get_msr_mce(vcpu, msr, pdata);
2537 case MSR_K7_CLK_CTL:
2539 * Provide expected ramp-up count for K7. All other
2540 * are set to zero, indicating minimum divisors for
2543 * This prevents guest kernels on AMD host with CPU
2544 * type 6, model 8 and higher from exploding due to
2545 * the rdmsr failing.
2549 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2550 if (kvm_hv_msr_partition_wide(msr)) {
2552 mutex_lock(&vcpu->kvm->lock);
2553 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2554 mutex_unlock(&vcpu->kvm->lock);
2557 return get_msr_hyperv(vcpu, msr, pdata);
2559 case MSR_IA32_BBL_CR_CTL3:
2560 /* This legacy MSR exists but isn't fully documented in current
2561 * silicon. It is however accessed by winxp in very narrow
2562 * scenarios where it sets bit #19, itself documented as
2563 * a "reserved" bit. Best effort attempt to source coherent
2564 * read data here should the balance of the register be
2565 * interpreted by the guest:
2567 * L2 cache control register 3: 64GB range, 256KB size,
2568 * enabled, latency 0x1, configured
2572 case MSR_AMD64_OSVW_ID_LENGTH:
2573 if (!guest_cpuid_has_osvw(vcpu))
2575 data = vcpu->arch.osvw.length;
2577 case MSR_AMD64_OSVW_STATUS:
2578 if (!guest_cpuid_has_osvw(vcpu))
2580 data = vcpu->arch.osvw.status;
2583 if (kvm_pmu_msr(vcpu, msr))
2584 return kvm_pmu_get_msr(vcpu, msr, pdata);
2586 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2589 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2597 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2600 * Read or write a bunch of msrs. All parameters are kernel addresses.
2602 * @return number of msrs set successfully.
2604 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2605 struct kvm_msr_entry *entries,
2606 int (*do_msr)(struct kvm_vcpu *vcpu,
2607 unsigned index, u64 *data))
2611 idx = srcu_read_lock(&vcpu->kvm->srcu);
2612 for (i = 0; i < msrs->nmsrs; ++i)
2613 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2615 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2621 * Read or write a bunch of msrs. Parameters are user addresses.
2623 * @return number of msrs set successfully.
2625 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2626 int (*do_msr)(struct kvm_vcpu *vcpu,
2627 unsigned index, u64 *data),
2630 struct kvm_msrs msrs;
2631 struct kvm_msr_entry *entries;
2636 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2640 if (msrs.nmsrs >= MAX_IO_MSRS)
2643 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2644 entries = memdup_user(user_msrs->entries, size);
2645 if (IS_ERR(entries)) {
2646 r = PTR_ERR(entries);
2650 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2655 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2666 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2671 case KVM_CAP_IRQCHIP:
2673 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2674 case KVM_CAP_SET_TSS_ADDR:
2675 case KVM_CAP_EXT_CPUID:
2676 case KVM_CAP_EXT_EMUL_CPUID:
2677 case KVM_CAP_CLOCKSOURCE:
2679 case KVM_CAP_NOP_IO_DELAY:
2680 case KVM_CAP_MP_STATE:
2681 case KVM_CAP_SYNC_MMU:
2682 case KVM_CAP_USER_NMI:
2683 case KVM_CAP_REINJECT_CONTROL:
2684 case KVM_CAP_IRQ_INJECT_STATUS:
2686 case KVM_CAP_IOEVENTFD:
2687 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2689 case KVM_CAP_PIT_STATE2:
2690 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2691 case KVM_CAP_XEN_HVM:
2692 case KVM_CAP_ADJUST_CLOCK:
2693 case KVM_CAP_VCPU_EVENTS:
2694 case KVM_CAP_HYPERV:
2695 case KVM_CAP_HYPERV_VAPIC:
2696 case KVM_CAP_HYPERV_SPIN:
2697 case KVM_CAP_PCI_SEGMENT:
2698 case KVM_CAP_DEBUGREGS:
2699 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2701 case KVM_CAP_ASYNC_PF:
2702 case KVM_CAP_GET_TSC_KHZ:
2703 case KVM_CAP_KVMCLOCK_CTRL:
2704 case KVM_CAP_READONLY_MEM:
2705 case KVM_CAP_HYPERV_TIME:
2706 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2707 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2708 case KVM_CAP_ASSIGN_DEV_IRQ:
2709 case KVM_CAP_PCI_2_3:
2713 case KVM_CAP_COALESCED_MMIO:
2714 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2717 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2719 case KVM_CAP_NR_VCPUS:
2720 r = KVM_SOFT_MAX_VCPUS;
2722 case KVM_CAP_MAX_VCPUS:
2725 case KVM_CAP_NR_MEMSLOTS:
2726 r = KVM_USER_MEM_SLOTS;
2728 case KVM_CAP_PV_MMU: /* obsolete */
2731 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2733 r = iommu_present(&pci_bus_type);
2737 r = KVM_MAX_MCE_BANKS;
2742 case KVM_CAP_TSC_CONTROL:
2743 r = kvm_has_tsc_control;
2745 case KVM_CAP_TSC_DEADLINE_TIMER:
2746 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2756 long kvm_arch_dev_ioctl(struct file *filp,
2757 unsigned int ioctl, unsigned long arg)
2759 void __user *argp = (void __user *)arg;
2763 case KVM_GET_MSR_INDEX_LIST: {
2764 struct kvm_msr_list __user *user_msr_list = argp;
2765 struct kvm_msr_list msr_list;
2769 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2772 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2773 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2776 if (n < msr_list.nmsrs)
2779 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2780 num_msrs_to_save * sizeof(u32)))
2782 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2784 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2789 case KVM_GET_SUPPORTED_CPUID:
2790 case KVM_GET_EMULATED_CPUID: {
2791 struct kvm_cpuid2 __user *cpuid_arg = argp;
2792 struct kvm_cpuid2 cpuid;
2795 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2798 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2804 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2809 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2812 mce_cap = KVM_MCE_CAP_SUPPORTED;
2814 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2826 static void wbinvd_ipi(void *garbage)
2831 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2833 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2836 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2838 /* Address WBINVD may be executed by guest */
2839 if (need_emulate_wbinvd(vcpu)) {
2840 if (kvm_x86_ops->has_wbinvd_exit())
2841 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2842 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2843 smp_call_function_single(vcpu->cpu,
2844 wbinvd_ipi, NULL, 1);
2847 kvm_x86_ops->vcpu_load(vcpu, cpu);
2849 /* Apply any externally detected TSC adjustments (due to suspend) */
2850 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2851 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2852 vcpu->arch.tsc_offset_adjustment = 0;
2853 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2856 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2857 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2858 native_read_tsc() - vcpu->arch.last_host_tsc;
2860 mark_tsc_unstable("KVM discovered backwards TSC");
2861 if (check_tsc_unstable()) {
2862 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2863 vcpu->arch.last_guest_tsc);
2864 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2865 vcpu->arch.tsc_catchup = 1;
2868 * On a host with synchronized TSC, there is no need to update
2869 * kvmclock on vcpu->cpu migration
2871 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2872 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2873 if (vcpu->cpu != cpu)
2874 kvm_migrate_timers(vcpu);
2878 accumulate_steal_time(vcpu);
2879 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2882 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2884 kvm_x86_ops->vcpu_put(vcpu);
2885 kvm_put_guest_fpu(vcpu);
2886 vcpu->arch.last_host_tsc = native_read_tsc();
2889 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2890 struct kvm_lapic_state *s)
2892 kvm_x86_ops->sync_pir_to_irr(vcpu);
2893 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2898 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2899 struct kvm_lapic_state *s)
2901 kvm_apic_post_state_restore(vcpu, s);
2902 update_cr8_intercept(vcpu);
2907 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2908 struct kvm_interrupt *irq)
2910 if (irq->irq >= KVM_NR_INTERRUPTS)
2912 if (irqchip_in_kernel(vcpu->kvm))
2915 kvm_queue_interrupt(vcpu, irq->irq, false);
2916 kvm_make_request(KVM_REQ_EVENT, vcpu);
2921 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2923 kvm_inject_nmi(vcpu);
2928 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2929 struct kvm_tpr_access_ctl *tac)
2933 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2937 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2941 unsigned bank_num = mcg_cap & 0xff, bank;
2944 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2946 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2949 vcpu->arch.mcg_cap = mcg_cap;
2950 /* Init IA32_MCG_CTL to all 1s */
2951 if (mcg_cap & MCG_CTL_P)
2952 vcpu->arch.mcg_ctl = ~(u64)0;
2953 /* Init IA32_MCi_CTL to all 1s */
2954 for (bank = 0; bank < bank_num; bank++)
2955 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2960 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2961 struct kvm_x86_mce *mce)
2963 u64 mcg_cap = vcpu->arch.mcg_cap;
2964 unsigned bank_num = mcg_cap & 0xff;
2965 u64 *banks = vcpu->arch.mce_banks;
2967 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2970 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2971 * reporting is disabled
2973 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2974 vcpu->arch.mcg_ctl != ~(u64)0)
2976 banks += 4 * mce->bank;
2978 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2979 * reporting is disabled for the bank
2981 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2983 if (mce->status & MCI_STATUS_UC) {
2984 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2985 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2986 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2989 if (banks[1] & MCI_STATUS_VAL)
2990 mce->status |= MCI_STATUS_OVER;
2991 banks[2] = mce->addr;
2992 banks[3] = mce->misc;
2993 vcpu->arch.mcg_status = mce->mcg_status;
2994 banks[1] = mce->status;
2995 kvm_queue_exception(vcpu, MC_VECTOR);
2996 } else if (!(banks[1] & MCI_STATUS_VAL)
2997 || !(banks[1] & MCI_STATUS_UC)) {
2998 if (banks[1] & MCI_STATUS_VAL)
2999 mce->status |= MCI_STATUS_OVER;
3000 banks[2] = mce->addr;
3001 banks[3] = mce->misc;
3002 banks[1] = mce->status;
3004 banks[1] |= MCI_STATUS_OVER;
3008 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3009 struct kvm_vcpu_events *events)
3012 events->exception.injected =
3013 vcpu->arch.exception.pending &&
3014 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3015 events->exception.nr = vcpu->arch.exception.nr;
3016 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3017 events->exception.pad = 0;
3018 events->exception.error_code = vcpu->arch.exception.error_code;
3020 events->interrupt.injected =
3021 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3022 events->interrupt.nr = vcpu->arch.interrupt.nr;
3023 events->interrupt.soft = 0;
3024 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3026 events->nmi.injected = vcpu->arch.nmi_injected;
3027 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3028 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3029 events->nmi.pad = 0;
3031 events->sipi_vector = 0; /* never valid when reporting to user space */
3033 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3034 | KVM_VCPUEVENT_VALID_SHADOW);
3035 memset(&events->reserved, 0, sizeof(events->reserved));
3038 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3039 struct kvm_vcpu_events *events)
3041 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3042 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3043 | KVM_VCPUEVENT_VALID_SHADOW))
3047 vcpu->arch.exception.pending = events->exception.injected;
3048 vcpu->arch.exception.nr = events->exception.nr;
3049 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3050 vcpu->arch.exception.error_code = events->exception.error_code;
3052 vcpu->arch.interrupt.pending = events->interrupt.injected;
3053 vcpu->arch.interrupt.nr = events->interrupt.nr;
3054 vcpu->arch.interrupt.soft = events->interrupt.soft;
3055 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3056 kvm_x86_ops->set_interrupt_shadow(vcpu,
3057 events->interrupt.shadow);
3059 vcpu->arch.nmi_injected = events->nmi.injected;
3060 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3061 vcpu->arch.nmi_pending = events->nmi.pending;
3062 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3064 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3065 kvm_vcpu_has_lapic(vcpu))
3066 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3068 kvm_make_request(KVM_REQ_EVENT, vcpu);
3073 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3074 struct kvm_debugregs *dbgregs)
3078 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3079 _kvm_get_dr(vcpu, 6, &val);
3081 dbgregs->dr7 = vcpu->arch.dr7;
3083 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3086 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3087 struct kvm_debugregs *dbgregs)
3092 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3093 vcpu->arch.dr6 = dbgregs->dr6;
3094 kvm_update_dr6(vcpu);
3095 vcpu->arch.dr7 = dbgregs->dr7;
3096 kvm_update_dr7(vcpu);
3101 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3102 struct kvm_xsave *guest_xsave)
3104 if (cpu_has_xsave) {
3105 memcpy(guest_xsave->region,
3106 &vcpu->arch.guest_fpu.state->xsave,
3107 vcpu->arch.guest_xstate_size);
3108 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3109 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3111 memcpy(guest_xsave->region,
3112 &vcpu->arch.guest_fpu.state->fxsave,
3113 sizeof(struct i387_fxsave_struct));
3114 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3119 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3120 struct kvm_xsave *guest_xsave)
3123 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3125 if (cpu_has_xsave) {
3127 * Here we allow setting states that are not present in
3128 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3129 * with old userspace.
3131 if (xstate_bv & ~kvm_supported_xcr0())
3133 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3134 guest_xsave->region, vcpu->arch.guest_xstate_size);
3136 if (xstate_bv & ~XSTATE_FPSSE)
3138 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3139 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3144 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3145 struct kvm_xcrs *guest_xcrs)
3147 if (!cpu_has_xsave) {
3148 guest_xcrs->nr_xcrs = 0;
3152 guest_xcrs->nr_xcrs = 1;
3153 guest_xcrs->flags = 0;
3154 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3155 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3158 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3159 struct kvm_xcrs *guest_xcrs)
3166 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3169 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3170 /* Only support XCR0 currently */
3171 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3172 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3173 guest_xcrs->xcrs[i].value);
3182 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3183 * stopped by the hypervisor. This function will be called from the host only.
3184 * EINVAL is returned when the host attempts to set the flag for a guest that
3185 * does not support pv clocks.
3187 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3189 if (!vcpu->arch.pv_time_enabled)
3191 vcpu->arch.pvclock_set_guest_stopped_request = true;
3192 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3196 long kvm_arch_vcpu_ioctl(struct file *filp,
3197 unsigned int ioctl, unsigned long arg)
3199 struct kvm_vcpu *vcpu = filp->private_data;
3200 void __user *argp = (void __user *)arg;
3203 struct kvm_lapic_state *lapic;
3204 struct kvm_xsave *xsave;
3205 struct kvm_xcrs *xcrs;
3211 case KVM_GET_LAPIC: {
3213 if (!vcpu->arch.apic)
3215 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3220 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3224 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3229 case KVM_SET_LAPIC: {
3231 if (!vcpu->arch.apic)
3233 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3234 if (IS_ERR(u.lapic))
3235 return PTR_ERR(u.lapic);
3237 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3240 case KVM_INTERRUPT: {
3241 struct kvm_interrupt irq;
3244 if (copy_from_user(&irq, argp, sizeof irq))
3246 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3250 r = kvm_vcpu_ioctl_nmi(vcpu);
3253 case KVM_SET_CPUID: {
3254 struct kvm_cpuid __user *cpuid_arg = argp;
3255 struct kvm_cpuid cpuid;
3258 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3260 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3263 case KVM_SET_CPUID2: {
3264 struct kvm_cpuid2 __user *cpuid_arg = argp;
3265 struct kvm_cpuid2 cpuid;
3268 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3270 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3271 cpuid_arg->entries);
3274 case KVM_GET_CPUID2: {
3275 struct kvm_cpuid2 __user *cpuid_arg = argp;
3276 struct kvm_cpuid2 cpuid;
3279 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3281 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3282 cpuid_arg->entries);
3286 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3292 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3295 r = msr_io(vcpu, argp, do_set_msr, 0);
3297 case KVM_TPR_ACCESS_REPORTING: {
3298 struct kvm_tpr_access_ctl tac;
3301 if (copy_from_user(&tac, argp, sizeof tac))
3303 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3307 if (copy_to_user(argp, &tac, sizeof tac))
3312 case KVM_SET_VAPIC_ADDR: {
3313 struct kvm_vapic_addr va;
3316 if (!irqchip_in_kernel(vcpu->kvm))
3319 if (copy_from_user(&va, argp, sizeof va))
3321 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3324 case KVM_X86_SETUP_MCE: {
3328 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3330 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3333 case KVM_X86_SET_MCE: {
3334 struct kvm_x86_mce mce;
3337 if (copy_from_user(&mce, argp, sizeof mce))
3339 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3342 case KVM_GET_VCPU_EVENTS: {
3343 struct kvm_vcpu_events events;
3345 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3348 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3353 case KVM_SET_VCPU_EVENTS: {
3354 struct kvm_vcpu_events events;
3357 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3360 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3363 case KVM_GET_DEBUGREGS: {
3364 struct kvm_debugregs dbgregs;
3366 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3369 if (copy_to_user(argp, &dbgregs,
3370 sizeof(struct kvm_debugregs)))
3375 case KVM_SET_DEBUGREGS: {
3376 struct kvm_debugregs dbgregs;
3379 if (copy_from_user(&dbgregs, argp,
3380 sizeof(struct kvm_debugregs)))
3383 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3386 case KVM_GET_XSAVE: {
3387 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3392 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3395 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3400 case KVM_SET_XSAVE: {
3401 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3402 if (IS_ERR(u.xsave))
3403 return PTR_ERR(u.xsave);
3405 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3408 case KVM_GET_XCRS: {
3409 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3414 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3417 if (copy_to_user(argp, u.xcrs,
3418 sizeof(struct kvm_xcrs)))
3423 case KVM_SET_XCRS: {
3424 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3426 return PTR_ERR(u.xcrs);
3428 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3431 case KVM_SET_TSC_KHZ: {
3435 user_tsc_khz = (u32)arg;
3437 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3440 if (user_tsc_khz == 0)
3441 user_tsc_khz = tsc_khz;
3443 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3448 case KVM_GET_TSC_KHZ: {
3449 r = vcpu->arch.virtual_tsc_khz;
3452 case KVM_KVMCLOCK_CTRL: {
3453 r = kvm_set_guest_paused(vcpu);
3464 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3466 return VM_FAULT_SIGBUS;
3469 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3473 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3475 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3479 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3482 kvm->arch.ept_identity_map_addr = ident_addr;
3486 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3487 u32 kvm_nr_mmu_pages)
3489 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3492 mutex_lock(&kvm->slots_lock);
3494 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3495 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3497 mutex_unlock(&kvm->slots_lock);
3501 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3503 return kvm->arch.n_max_mmu_pages;
3506 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3511 switch (chip->chip_id) {
3512 case KVM_IRQCHIP_PIC_MASTER:
3513 memcpy(&chip->chip.pic,
3514 &pic_irqchip(kvm)->pics[0],
3515 sizeof(struct kvm_pic_state));
3517 case KVM_IRQCHIP_PIC_SLAVE:
3518 memcpy(&chip->chip.pic,
3519 &pic_irqchip(kvm)->pics[1],
3520 sizeof(struct kvm_pic_state));
3522 case KVM_IRQCHIP_IOAPIC:
3523 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3532 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3537 switch (chip->chip_id) {
3538 case KVM_IRQCHIP_PIC_MASTER:
3539 spin_lock(&pic_irqchip(kvm)->lock);
3540 memcpy(&pic_irqchip(kvm)->pics[0],
3542 sizeof(struct kvm_pic_state));
3543 spin_unlock(&pic_irqchip(kvm)->lock);
3545 case KVM_IRQCHIP_PIC_SLAVE:
3546 spin_lock(&pic_irqchip(kvm)->lock);
3547 memcpy(&pic_irqchip(kvm)->pics[1],
3549 sizeof(struct kvm_pic_state));
3550 spin_unlock(&pic_irqchip(kvm)->lock);
3552 case KVM_IRQCHIP_IOAPIC:
3553 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3559 kvm_pic_update_irq(pic_irqchip(kvm));
3563 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3567 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3568 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3569 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3573 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3577 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3578 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3579 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3580 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3584 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3588 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3589 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3590 sizeof(ps->channels));
3591 ps->flags = kvm->arch.vpit->pit_state.flags;
3592 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3593 memset(&ps->reserved, 0, sizeof(ps->reserved));
3597 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3599 int r = 0, start = 0;
3600 u32 prev_legacy, cur_legacy;
3601 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3602 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3603 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3604 if (!prev_legacy && cur_legacy)
3606 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3607 sizeof(kvm->arch.vpit->pit_state.channels));
3608 kvm->arch.vpit->pit_state.flags = ps->flags;
3609 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3610 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3614 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3615 struct kvm_reinject_control *control)
3617 if (!kvm->arch.vpit)
3619 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3620 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3621 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3626 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3627 * @kvm: kvm instance
3628 * @log: slot id and address to which we copy the log
3630 * We need to keep it in mind that VCPU threads can write to the bitmap
3631 * concurrently. So, to avoid losing data, we keep the following order for
3634 * 1. Take a snapshot of the bit and clear it if needed.
3635 * 2. Write protect the corresponding page.
3636 * 3. Flush TLB's if needed.
3637 * 4. Copy the snapshot to the userspace.
3639 * Between 2 and 3, the guest may write to the page using the remaining TLB
3640 * entry. This is not a problem because the page will be reported dirty at
3641 * step 4 using the snapshot taken before and step 3 ensures that successive
3642 * writes will be logged for the next call.
3644 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3647 struct kvm_memory_slot *memslot;
3649 unsigned long *dirty_bitmap;
3650 unsigned long *dirty_bitmap_buffer;
3651 bool is_dirty = false;
3653 mutex_lock(&kvm->slots_lock);
3656 if (log->slot >= KVM_USER_MEM_SLOTS)
3659 memslot = id_to_memslot(kvm->memslots, log->slot);
3661 dirty_bitmap = memslot->dirty_bitmap;
3666 n = kvm_dirty_bitmap_bytes(memslot);
3668 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3669 memset(dirty_bitmap_buffer, 0, n);
3671 spin_lock(&kvm->mmu_lock);
3673 for (i = 0; i < n / sizeof(long); i++) {
3677 if (!dirty_bitmap[i])
3682 mask = xchg(&dirty_bitmap[i], 0);
3683 dirty_bitmap_buffer[i] = mask;
3685 offset = i * BITS_PER_LONG;
3686 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3689 spin_unlock(&kvm->mmu_lock);
3691 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3692 lockdep_assert_held(&kvm->slots_lock);
3695 * All the TLBs can be flushed out of mmu lock, see the comments in
3696 * kvm_mmu_slot_remove_write_access().
3699 kvm_flush_remote_tlbs(kvm);
3702 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3707 mutex_unlock(&kvm->slots_lock);
3711 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3714 if (!irqchip_in_kernel(kvm))
3717 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3718 irq_event->irq, irq_event->level,
3723 long kvm_arch_vm_ioctl(struct file *filp,
3724 unsigned int ioctl, unsigned long arg)
3726 struct kvm *kvm = filp->private_data;
3727 void __user *argp = (void __user *)arg;
3730 * This union makes it completely explicit to gcc-3.x
3731 * that these two variables' stack usage should be
3732 * combined, not added together.
3735 struct kvm_pit_state ps;
3736 struct kvm_pit_state2 ps2;
3737 struct kvm_pit_config pit_config;
3741 case KVM_SET_TSS_ADDR:
3742 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3744 case KVM_SET_IDENTITY_MAP_ADDR: {
3748 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3750 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3753 case KVM_SET_NR_MMU_PAGES:
3754 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3756 case KVM_GET_NR_MMU_PAGES:
3757 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3759 case KVM_CREATE_IRQCHIP: {
3760 struct kvm_pic *vpic;
3762 mutex_lock(&kvm->lock);
3765 goto create_irqchip_unlock;
3767 if (atomic_read(&kvm->online_vcpus))
3768 goto create_irqchip_unlock;
3770 vpic = kvm_create_pic(kvm);
3772 r = kvm_ioapic_init(kvm);
3774 mutex_lock(&kvm->slots_lock);
3775 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3777 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3779 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3781 mutex_unlock(&kvm->slots_lock);
3783 goto create_irqchip_unlock;
3786 goto create_irqchip_unlock;
3788 kvm->arch.vpic = vpic;
3790 r = kvm_setup_default_irq_routing(kvm);
3792 mutex_lock(&kvm->slots_lock);
3793 mutex_lock(&kvm->irq_lock);
3794 kvm_ioapic_destroy(kvm);
3795 kvm_destroy_pic(kvm);
3796 mutex_unlock(&kvm->irq_lock);
3797 mutex_unlock(&kvm->slots_lock);
3799 create_irqchip_unlock:
3800 mutex_unlock(&kvm->lock);
3803 case KVM_CREATE_PIT:
3804 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3806 case KVM_CREATE_PIT2:
3808 if (copy_from_user(&u.pit_config, argp,
3809 sizeof(struct kvm_pit_config)))
3812 mutex_lock(&kvm->slots_lock);
3815 goto create_pit_unlock;
3817 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3821 mutex_unlock(&kvm->slots_lock);
3823 case KVM_GET_IRQCHIP: {
3824 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3825 struct kvm_irqchip *chip;
3827 chip = memdup_user(argp, sizeof(*chip));
3834 if (!irqchip_in_kernel(kvm))
3835 goto get_irqchip_out;
3836 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3838 goto get_irqchip_out;
3840 if (copy_to_user(argp, chip, sizeof *chip))
3841 goto get_irqchip_out;
3847 case KVM_SET_IRQCHIP: {
3848 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3849 struct kvm_irqchip *chip;
3851 chip = memdup_user(argp, sizeof(*chip));
3858 if (!irqchip_in_kernel(kvm))
3859 goto set_irqchip_out;
3860 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3862 goto set_irqchip_out;
3870 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3873 if (!kvm->arch.vpit)
3875 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3879 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3886 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3889 if (!kvm->arch.vpit)
3891 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3894 case KVM_GET_PIT2: {
3896 if (!kvm->arch.vpit)
3898 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3902 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3907 case KVM_SET_PIT2: {
3909 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3912 if (!kvm->arch.vpit)
3914 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3917 case KVM_REINJECT_CONTROL: {
3918 struct kvm_reinject_control control;
3920 if (copy_from_user(&control, argp, sizeof(control)))
3922 r = kvm_vm_ioctl_reinject(kvm, &control);
3925 case KVM_XEN_HVM_CONFIG: {
3927 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3928 sizeof(struct kvm_xen_hvm_config)))
3931 if (kvm->arch.xen_hvm_config.flags)
3936 case KVM_SET_CLOCK: {
3937 struct kvm_clock_data user_ns;
3942 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3950 local_irq_disable();
3951 now_ns = get_kernel_ns();
3952 delta = user_ns.clock - now_ns;
3954 kvm->arch.kvmclock_offset = delta;
3955 kvm_gen_update_masterclock(kvm);
3958 case KVM_GET_CLOCK: {
3959 struct kvm_clock_data user_ns;
3962 local_irq_disable();
3963 now_ns = get_kernel_ns();
3964 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3967 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3970 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3983 static void kvm_init_msr_list(void)
3988 /* skip the first msrs in the list. KVM-specific */
3989 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3990 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3994 * Even MSRs that are valid in the host may not be exposed
3995 * to the guests in some cases. We could work around this
3996 * in VMX with the generic MSR save/load machinery, but it
3997 * is not really worthwhile since it will really only
3998 * happen with nested virtualization.
4000 switch (msrs_to_save[i]) {
4001 case MSR_IA32_BNDCFGS:
4002 if (!kvm_x86_ops->mpx_supported())
4010 msrs_to_save[j] = msrs_to_save[i];
4013 num_msrs_to_save = j;
4016 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4024 if (!(vcpu->arch.apic &&
4025 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4026 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4037 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4044 if (!(vcpu->arch.apic &&
4045 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4046 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4048 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4058 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4059 struct kvm_segment *var, int seg)
4061 kvm_x86_ops->set_segment(vcpu, var, seg);
4064 void kvm_get_segment(struct kvm_vcpu *vcpu,
4065 struct kvm_segment *var, int seg)
4067 kvm_x86_ops->get_segment(vcpu, var, seg);
4070 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4071 struct x86_exception *exception)
4075 BUG_ON(!mmu_is_nested(vcpu));
4077 /* NPT walks are always user-walks */
4078 access |= PFERR_USER_MASK;
4079 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4084 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4085 struct x86_exception *exception)
4087 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4088 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4091 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4092 struct x86_exception *exception)
4094 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4095 access |= PFERR_FETCH_MASK;
4096 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4099 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4100 struct x86_exception *exception)
4102 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4103 access |= PFERR_WRITE_MASK;
4104 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4107 /* uses this to access any guest's mapped memory without checking CPL */
4108 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4109 struct x86_exception *exception)
4111 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4114 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4115 struct kvm_vcpu *vcpu, u32 access,
4116 struct x86_exception *exception)
4119 int r = X86EMUL_CONTINUE;
4122 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4124 unsigned offset = addr & (PAGE_SIZE-1);
4125 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4128 if (gpa == UNMAPPED_GVA)
4129 return X86EMUL_PROPAGATE_FAULT;
4130 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4133 r = X86EMUL_IO_NEEDED;
4145 /* used for instruction fetching */
4146 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4147 gva_t addr, void *val, unsigned int bytes,
4148 struct x86_exception *exception)
4150 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4151 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4155 /* Inline kvm_read_guest_virt_helper for speed. */
4156 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4158 if (unlikely(gpa == UNMAPPED_GVA))
4159 return X86EMUL_PROPAGATE_FAULT;
4161 offset = addr & (PAGE_SIZE-1);
4162 if (WARN_ON(offset + bytes > PAGE_SIZE))
4163 bytes = (unsigned)PAGE_SIZE - offset;
4164 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4166 if (unlikely(ret < 0))
4167 return X86EMUL_IO_NEEDED;
4169 return X86EMUL_CONTINUE;
4172 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4173 gva_t addr, void *val, unsigned int bytes,
4174 struct x86_exception *exception)
4176 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4177 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4179 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4182 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4184 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4185 gva_t addr, void *val, unsigned int bytes,
4186 struct x86_exception *exception)
4188 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4189 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4192 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4193 gva_t addr, void *val,
4195 struct x86_exception *exception)
4197 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4199 int r = X86EMUL_CONTINUE;
4202 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4205 unsigned offset = addr & (PAGE_SIZE-1);
4206 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4209 if (gpa == UNMAPPED_GVA)
4210 return X86EMUL_PROPAGATE_FAULT;
4211 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4213 r = X86EMUL_IO_NEEDED;
4224 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4226 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4227 gpa_t *gpa, struct x86_exception *exception,
4230 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4231 | (write ? PFERR_WRITE_MASK : 0);
4233 if (vcpu_match_mmio_gva(vcpu, gva)
4234 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4235 vcpu->arch.access, access)) {
4236 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4237 (gva & (PAGE_SIZE - 1));
4238 trace_vcpu_match_mmio(gva, *gpa, write, false);
4242 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4244 if (*gpa == UNMAPPED_GVA)
4247 /* For APIC access vmexit */
4248 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4251 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4252 trace_vcpu_match_mmio(gva, *gpa, write, true);
4259 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4260 const void *val, int bytes)
4264 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4267 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4271 struct read_write_emulator_ops {
4272 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4274 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4275 void *val, int bytes);
4276 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4277 int bytes, void *val);
4278 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4279 void *val, int bytes);
4283 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4285 if (vcpu->mmio_read_completed) {
4286 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4287 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4288 vcpu->mmio_read_completed = 0;
4295 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4296 void *val, int bytes)
4298 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4301 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4302 void *val, int bytes)
4304 return emulator_write_phys(vcpu, gpa, val, bytes);
4307 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4309 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4310 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4313 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4314 void *val, int bytes)
4316 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4317 return X86EMUL_IO_NEEDED;
4320 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4321 void *val, int bytes)
4323 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4325 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4326 return X86EMUL_CONTINUE;
4329 static const struct read_write_emulator_ops read_emultor = {
4330 .read_write_prepare = read_prepare,
4331 .read_write_emulate = read_emulate,
4332 .read_write_mmio = vcpu_mmio_read,
4333 .read_write_exit_mmio = read_exit_mmio,
4336 static const struct read_write_emulator_ops write_emultor = {
4337 .read_write_emulate = write_emulate,
4338 .read_write_mmio = write_mmio,
4339 .read_write_exit_mmio = write_exit_mmio,
4343 static int emulator_read_write_onepage(unsigned long addr, void *val,
4345 struct x86_exception *exception,
4346 struct kvm_vcpu *vcpu,
4347 const struct read_write_emulator_ops *ops)
4351 bool write = ops->write;
4352 struct kvm_mmio_fragment *frag;
4354 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4357 return X86EMUL_PROPAGATE_FAULT;
4359 /* For APIC access vmexit */
4363 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4364 return X86EMUL_CONTINUE;
4368 * Is this MMIO handled locally?
4370 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4371 if (handled == bytes)
4372 return X86EMUL_CONTINUE;
4378 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4379 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4383 return X86EMUL_CONTINUE;
4386 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4387 void *val, unsigned int bytes,
4388 struct x86_exception *exception,
4389 const struct read_write_emulator_ops *ops)
4391 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4395 if (ops->read_write_prepare &&
4396 ops->read_write_prepare(vcpu, val, bytes))
4397 return X86EMUL_CONTINUE;
4399 vcpu->mmio_nr_fragments = 0;
4401 /* Crossing a page boundary? */
4402 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4405 now = -addr & ~PAGE_MASK;
4406 rc = emulator_read_write_onepage(addr, val, now, exception,
4409 if (rc != X86EMUL_CONTINUE)
4416 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4418 if (rc != X86EMUL_CONTINUE)
4421 if (!vcpu->mmio_nr_fragments)
4424 gpa = vcpu->mmio_fragments[0].gpa;
4426 vcpu->mmio_needed = 1;
4427 vcpu->mmio_cur_fragment = 0;
4429 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4430 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4431 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4432 vcpu->run->mmio.phys_addr = gpa;
4434 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4437 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4441 struct x86_exception *exception)
4443 return emulator_read_write(ctxt, addr, val, bytes,
4444 exception, &read_emultor);
4447 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4451 struct x86_exception *exception)
4453 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4454 exception, &write_emultor);
4457 #define CMPXCHG_TYPE(t, ptr, old, new) \
4458 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4460 #ifdef CONFIG_X86_64
4461 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4463 # define CMPXCHG64(ptr, old, new) \
4464 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4467 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4472 struct x86_exception *exception)
4474 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4480 /* guests cmpxchg8b have to be emulated atomically */
4481 if (bytes > 8 || (bytes & (bytes - 1)))
4484 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4486 if (gpa == UNMAPPED_GVA ||
4487 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4490 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4493 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4494 if (is_error_page(page))
4497 kaddr = kmap_atomic(page);
4498 kaddr += offset_in_page(gpa);
4501 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4504 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4507 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4510 exchanged = CMPXCHG64(kaddr, old, new);
4515 kunmap_atomic(kaddr);
4516 kvm_release_page_dirty(page);
4519 return X86EMUL_CMPXCHG_FAILED;
4521 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4522 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4524 return X86EMUL_CONTINUE;
4527 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4529 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4532 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4534 /* TODO: String I/O for in kernel device */
4537 if (vcpu->arch.pio.in)
4538 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4539 vcpu->arch.pio.size, pd);
4541 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4542 vcpu->arch.pio.port, vcpu->arch.pio.size,
4547 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4548 unsigned short port, void *val,
4549 unsigned int count, bool in)
4551 vcpu->arch.pio.port = port;
4552 vcpu->arch.pio.in = in;
4553 vcpu->arch.pio.count = count;
4554 vcpu->arch.pio.size = size;
4556 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4557 vcpu->arch.pio.count = 0;
4561 vcpu->run->exit_reason = KVM_EXIT_IO;
4562 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4563 vcpu->run->io.size = size;
4564 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4565 vcpu->run->io.count = count;
4566 vcpu->run->io.port = port;
4571 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4572 int size, unsigned short port, void *val,
4575 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4578 if (vcpu->arch.pio.count)
4581 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4584 memcpy(val, vcpu->arch.pio_data, size * count);
4585 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4586 vcpu->arch.pio.count = 0;
4593 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4594 int size, unsigned short port,
4595 const void *val, unsigned int count)
4597 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4599 memcpy(vcpu->arch.pio_data, val, size * count);
4600 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4601 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4604 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4606 return kvm_x86_ops->get_segment_base(vcpu, seg);
4609 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4611 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4614 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4616 if (!need_emulate_wbinvd(vcpu))
4617 return X86EMUL_CONTINUE;
4619 if (kvm_x86_ops->has_wbinvd_exit()) {
4620 int cpu = get_cpu();
4622 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4623 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4624 wbinvd_ipi, NULL, 1);
4626 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4629 return X86EMUL_CONTINUE;
4631 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4633 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4635 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4638 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4640 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4643 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4646 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4649 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4651 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4654 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4656 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4657 unsigned long value;
4661 value = kvm_read_cr0(vcpu);
4664 value = vcpu->arch.cr2;
4667 value = kvm_read_cr3(vcpu);
4670 value = kvm_read_cr4(vcpu);
4673 value = kvm_get_cr8(vcpu);
4676 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4683 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4685 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4690 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4693 vcpu->arch.cr2 = val;
4696 res = kvm_set_cr3(vcpu, val);
4699 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4702 res = kvm_set_cr8(vcpu, val);
4705 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4712 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4714 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4717 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4719 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4722 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4724 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4727 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4729 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4732 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4734 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4737 static unsigned long emulator_get_cached_segment_base(
4738 struct x86_emulate_ctxt *ctxt, int seg)
4740 return get_segment_base(emul_to_vcpu(ctxt), seg);
4743 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4744 struct desc_struct *desc, u32 *base3,
4747 struct kvm_segment var;
4749 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4750 *selector = var.selector;
4753 memset(desc, 0, sizeof(*desc));
4759 set_desc_limit(desc, var.limit);
4760 set_desc_base(desc, (unsigned long)var.base);
4761 #ifdef CONFIG_X86_64
4763 *base3 = var.base >> 32;
4765 desc->type = var.type;
4767 desc->dpl = var.dpl;
4768 desc->p = var.present;
4769 desc->avl = var.avl;
4777 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4778 struct desc_struct *desc, u32 base3,
4781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4782 struct kvm_segment var;
4784 var.selector = selector;
4785 var.base = get_desc_base(desc);
4786 #ifdef CONFIG_X86_64
4787 var.base |= ((u64)base3) << 32;
4789 var.limit = get_desc_limit(desc);
4791 var.limit = (var.limit << 12) | 0xfff;
4792 var.type = desc->type;
4793 var.dpl = desc->dpl;
4798 var.avl = desc->avl;
4799 var.present = desc->p;
4800 var.unusable = !var.present;
4803 kvm_set_segment(vcpu, &var, seg);
4807 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4808 u32 msr_index, u64 *pdata)
4810 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4813 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4814 u32 msr_index, u64 data)
4816 struct msr_data msr;
4819 msr.index = msr_index;
4820 msr.host_initiated = false;
4821 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4824 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4827 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4830 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4831 u32 pmc, u64 *pdata)
4833 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4836 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4838 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4841 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4844 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4846 * CR0.TS may reference the host fpu state, not the guest fpu state,
4847 * so it may be clear at this point.
4852 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4857 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4858 struct x86_instruction_info *info,
4859 enum x86_intercept_stage stage)
4861 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4864 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4865 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4867 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4870 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4872 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4875 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4877 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4880 static const struct x86_emulate_ops emulate_ops = {
4881 .read_gpr = emulator_read_gpr,
4882 .write_gpr = emulator_write_gpr,
4883 .read_std = kvm_read_guest_virt_system,
4884 .write_std = kvm_write_guest_virt_system,
4885 .fetch = kvm_fetch_guest_virt,
4886 .read_emulated = emulator_read_emulated,
4887 .write_emulated = emulator_write_emulated,
4888 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4889 .invlpg = emulator_invlpg,
4890 .pio_in_emulated = emulator_pio_in_emulated,
4891 .pio_out_emulated = emulator_pio_out_emulated,
4892 .get_segment = emulator_get_segment,
4893 .set_segment = emulator_set_segment,
4894 .get_cached_segment_base = emulator_get_cached_segment_base,
4895 .get_gdt = emulator_get_gdt,
4896 .get_idt = emulator_get_idt,
4897 .set_gdt = emulator_set_gdt,
4898 .set_idt = emulator_set_idt,
4899 .get_cr = emulator_get_cr,
4900 .set_cr = emulator_set_cr,
4901 .cpl = emulator_get_cpl,
4902 .get_dr = emulator_get_dr,
4903 .set_dr = emulator_set_dr,
4904 .set_msr = emulator_set_msr,
4905 .get_msr = emulator_get_msr,
4906 .check_pmc = emulator_check_pmc,
4907 .read_pmc = emulator_read_pmc,
4908 .halt = emulator_halt,
4909 .wbinvd = emulator_wbinvd,
4910 .fix_hypercall = emulator_fix_hypercall,
4911 .get_fpu = emulator_get_fpu,
4912 .put_fpu = emulator_put_fpu,
4913 .intercept = emulator_intercept,
4914 .get_cpuid = emulator_get_cpuid,
4917 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4919 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
4921 * an sti; sti; sequence only disable interrupts for the first
4922 * instruction. So, if the last instruction, be it emulated or
4923 * not, left the system with the INT_STI flag enabled, it
4924 * means that the last instruction is an sti. We should not
4925 * leave the flag on in this case. The same goes for mov ss
4927 if (int_shadow & mask)
4929 if (unlikely(int_shadow || mask)) {
4930 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4932 kvm_make_request(KVM_REQ_EVENT, vcpu);
4936 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
4938 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4939 if (ctxt->exception.vector == PF_VECTOR)
4940 return kvm_propagate_fault(vcpu, &ctxt->exception);
4942 if (ctxt->exception.error_code_valid)
4943 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4944 ctxt->exception.error_code);
4946 kvm_queue_exception(vcpu, ctxt->exception.vector);
4950 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4952 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4955 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4957 ctxt->eflags = kvm_get_rflags(vcpu);
4958 ctxt->eip = kvm_rip_read(vcpu);
4959 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4960 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4961 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
4962 cs_db ? X86EMUL_MODE_PROT32 :
4963 X86EMUL_MODE_PROT16;
4964 ctxt->guest_mode = is_guest_mode(vcpu);
4966 init_decode_cache(ctxt);
4967 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4970 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4972 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4975 init_emulate_ctxt(vcpu);
4979 ctxt->_eip = ctxt->eip + inc_eip;
4980 ret = emulate_int_real(ctxt, irq);
4982 if (ret != X86EMUL_CONTINUE)
4983 return EMULATE_FAIL;
4985 ctxt->eip = ctxt->_eip;
4986 kvm_rip_write(vcpu, ctxt->eip);
4987 kvm_set_rflags(vcpu, ctxt->eflags);
4989 if (irq == NMI_VECTOR)
4990 vcpu->arch.nmi_pending = 0;
4992 vcpu->arch.interrupt.pending = false;
4994 return EMULATE_DONE;
4996 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4998 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5000 int r = EMULATE_DONE;
5002 ++vcpu->stat.insn_emulation_fail;
5003 trace_kvm_emulate_insn_failed(vcpu);
5004 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5005 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5006 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5007 vcpu->run->internal.ndata = 0;
5010 kvm_queue_exception(vcpu, UD_VECTOR);
5015 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5016 bool write_fault_to_shadow_pgtable,
5022 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5025 if (!vcpu->arch.mmu.direct_map) {
5027 * Write permission should be allowed since only
5028 * write access need to be emulated.
5030 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5033 * If the mapping is invalid in guest, let cpu retry
5034 * it to generate fault.
5036 if (gpa == UNMAPPED_GVA)
5041 * Do not retry the unhandleable instruction if it faults on the
5042 * readonly host memory, otherwise it will goto a infinite loop:
5043 * retry instruction -> write #PF -> emulation fail -> retry
5044 * instruction -> ...
5046 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5049 * If the instruction failed on the error pfn, it can not be fixed,
5050 * report the error to userspace.
5052 if (is_error_noslot_pfn(pfn))
5055 kvm_release_pfn_clean(pfn);
5057 /* The instructions are well-emulated on direct mmu. */
5058 if (vcpu->arch.mmu.direct_map) {
5059 unsigned int indirect_shadow_pages;
5061 spin_lock(&vcpu->kvm->mmu_lock);
5062 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5063 spin_unlock(&vcpu->kvm->mmu_lock);
5065 if (indirect_shadow_pages)
5066 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5072 * if emulation was due to access to shadowed page table
5073 * and it failed try to unshadow page and re-enter the
5074 * guest to let CPU execute the instruction.
5076 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5079 * If the access faults on its page table, it can not
5080 * be fixed by unprotecting shadow page and it should
5081 * be reported to userspace.
5083 return !write_fault_to_shadow_pgtable;
5086 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5087 unsigned long cr2, int emulation_type)
5089 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5090 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5092 last_retry_eip = vcpu->arch.last_retry_eip;
5093 last_retry_addr = vcpu->arch.last_retry_addr;
5096 * If the emulation is caused by #PF and it is non-page_table
5097 * writing instruction, it means the VM-EXIT is caused by shadow
5098 * page protected, we can zap the shadow page and retry this
5099 * instruction directly.
5101 * Note: if the guest uses a non-page-table modifying instruction
5102 * on the PDE that points to the instruction, then we will unmap
5103 * the instruction and go to an infinite loop. So, we cache the
5104 * last retried eip and the last fault address, if we meet the eip
5105 * and the address again, we can break out of the potential infinite
5108 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5110 if (!(emulation_type & EMULTYPE_RETRY))
5113 if (x86_page_table_writing_insn(ctxt))
5116 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5119 vcpu->arch.last_retry_eip = ctxt->eip;
5120 vcpu->arch.last_retry_addr = cr2;
5122 if (!vcpu->arch.mmu.direct_map)
5123 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5125 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5130 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5131 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5133 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5142 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5143 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5148 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5150 struct kvm_run *kvm_run = vcpu->run;
5153 * rflags is the old, "raw" value of the flags. The new value has
5154 * not been saved yet.
5156 * This is correct even for TF set by the guest, because "the
5157 * processor will not generate this exception after the instruction
5158 * that sets the TF flag".
5160 if (unlikely(rflags & X86_EFLAGS_TF)) {
5161 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5162 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5164 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5165 kvm_run->debug.arch.exception = DB_VECTOR;
5166 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5167 *r = EMULATE_USER_EXIT;
5169 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5171 * "Certain debug exceptions may clear bit 0-3. The
5172 * remaining contents of the DR6 register are never
5173 * cleared by the processor".
5175 vcpu->arch.dr6 &= ~15;
5176 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5177 kvm_queue_exception(vcpu, DB_VECTOR);
5182 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5184 struct kvm_run *kvm_run = vcpu->run;
5185 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5188 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5189 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5190 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5191 vcpu->arch.guest_debug_dr7,
5195 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5196 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5197 get_segment_base(vcpu, VCPU_SREG_CS);
5199 kvm_run->debug.arch.exception = DB_VECTOR;
5200 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5201 *r = EMULATE_USER_EXIT;
5206 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5207 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5208 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5213 vcpu->arch.dr6 &= ~15;
5214 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5215 kvm_queue_exception(vcpu, DB_VECTOR);
5224 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5231 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5232 bool writeback = true;
5233 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5236 * Clear write_fault_to_shadow_pgtable here to ensure it is
5239 vcpu->arch.write_fault_to_shadow_pgtable = false;
5240 kvm_clear_exception_queue(vcpu);
5242 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5243 init_emulate_ctxt(vcpu);
5246 * We will reenter on the same instruction since
5247 * we do not set complete_userspace_io. This does not
5248 * handle watchpoints yet, those would be handled in
5251 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5254 ctxt->interruptibility = 0;
5255 ctxt->have_exception = false;
5256 ctxt->exception.vector = -1;
5257 ctxt->perm_ok = false;
5259 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5261 r = x86_decode_insn(ctxt, insn, insn_len);
5263 trace_kvm_emulate_insn_start(vcpu);
5264 ++vcpu->stat.insn_emulation;
5265 if (r != EMULATION_OK) {
5266 if (emulation_type & EMULTYPE_TRAP_UD)
5267 return EMULATE_FAIL;
5268 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5270 return EMULATE_DONE;
5271 if (emulation_type & EMULTYPE_SKIP)
5272 return EMULATE_FAIL;
5273 return handle_emulation_failure(vcpu);
5277 if (emulation_type & EMULTYPE_SKIP) {
5278 kvm_rip_write(vcpu, ctxt->_eip);
5279 if (ctxt->eflags & X86_EFLAGS_RF)
5280 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5281 return EMULATE_DONE;
5284 if (retry_instruction(ctxt, cr2, emulation_type))
5285 return EMULATE_DONE;
5287 /* this is needed for vmware backdoor interface to work since it
5288 changes registers values during IO operation */
5289 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5290 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5291 emulator_invalidate_register_cache(ctxt);
5295 r = x86_emulate_insn(ctxt);
5297 if (r == EMULATION_INTERCEPTED)
5298 return EMULATE_DONE;
5300 if (r == EMULATION_FAILED) {
5301 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5303 return EMULATE_DONE;
5305 return handle_emulation_failure(vcpu);
5308 if (ctxt->have_exception) {
5310 if (inject_emulated_exception(vcpu))
5312 } else if (vcpu->arch.pio.count) {
5313 if (!vcpu->arch.pio.in) {
5314 /* FIXME: return into emulator if single-stepping. */
5315 vcpu->arch.pio.count = 0;
5318 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5320 r = EMULATE_USER_EXIT;
5321 } else if (vcpu->mmio_needed) {
5322 if (!vcpu->mmio_is_write)
5324 r = EMULATE_USER_EXIT;
5325 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5326 } else if (r == EMULATION_RESTART)
5332 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5333 toggle_interruptibility(vcpu, ctxt->interruptibility);
5334 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5335 kvm_rip_write(vcpu, ctxt->eip);
5336 if (r == EMULATE_DONE)
5337 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5338 __kvm_set_rflags(vcpu, ctxt->eflags);
5341 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5342 * do nothing, and it will be requested again as soon as
5343 * the shadow expires. But we still need to check here,
5344 * because POPF has no interrupt shadow.
5346 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5347 kvm_make_request(KVM_REQ_EVENT, vcpu);
5349 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5353 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5355 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5357 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5358 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5359 size, port, &val, 1);
5360 /* do not return to emulator after return from userspace */
5361 vcpu->arch.pio.count = 0;
5364 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5366 static void tsc_bad(void *info)
5368 __this_cpu_write(cpu_tsc_khz, 0);
5371 static void tsc_khz_changed(void *data)
5373 struct cpufreq_freqs *freq = data;
5374 unsigned long khz = 0;
5378 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5379 khz = cpufreq_quick_get(raw_smp_processor_id());
5382 __this_cpu_write(cpu_tsc_khz, khz);
5385 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5388 struct cpufreq_freqs *freq = data;
5390 struct kvm_vcpu *vcpu;
5391 int i, send_ipi = 0;
5394 * We allow guests to temporarily run on slowing clocks,
5395 * provided we notify them after, or to run on accelerating
5396 * clocks, provided we notify them before. Thus time never
5399 * However, we have a problem. We can't atomically update
5400 * the frequency of a given CPU from this function; it is
5401 * merely a notifier, which can be called from any CPU.
5402 * Changing the TSC frequency at arbitrary points in time
5403 * requires a recomputation of local variables related to
5404 * the TSC for each VCPU. We must flag these local variables
5405 * to be updated and be sure the update takes place with the
5406 * new frequency before any guests proceed.
5408 * Unfortunately, the combination of hotplug CPU and frequency
5409 * change creates an intractable locking scenario; the order
5410 * of when these callouts happen is undefined with respect to
5411 * CPU hotplug, and they can race with each other. As such,
5412 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5413 * undefined; you can actually have a CPU frequency change take
5414 * place in between the computation of X and the setting of the
5415 * variable. To protect against this problem, all updates of
5416 * the per_cpu tsc_khz variable are done in an interrupt
5417 * protected IPI, and all callers wishing to update the value
5418 * must wait for a synchronous IPI to complete (which is trivial
5419 * if the caller is on the CPU already). This establishes the
5420 * necessary total order on variable updates.
5422 * Note that because a guest time update may take place
5423 * anytime after the setting of the VCPU's request bit, the
5424 * correct TSC value must be set before the request. However,
5425 * to ensure the update actually makes it to any guest which
5426 * starts running in hardware virtualization between the set
5427 * and the acquisition of the spinlock, we must also ping the
5428 * CPU after setting the request bit.
5432 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5434 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5437 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5439 spin_lock(&kvm_lock);
5440 list_for_each_entry(kvm, &vm_list, vm_list) {
5441 kvm_for_each_vcpu(i, vcpu, kvm) {
5442 if (vcpu->cpu != freq->cpu)
5444 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5445 if (vcpu->cpu != smp_processor_id())
5449 spin_unlock(&kvm_lock);
5451 if (freq->old < freq->new && send_ipi) {
5453 * We upscale the frequency. Must make the guest
5454 * doesn't see old kvmclock values while running with
5455 * the new frequency, otherwise we risk the guest sees
5456 * time go backwards.
5458 * In case we update the frequency for another cpu
5459 * (which might be in guest context) send an interrupt
5460 * to kick the cpu out of guest context. Next time
5461 * guest context is entered kvmclock will be updated,
5462 * so the guest will not see stale values.
5464 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5469 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5470 .notifier_call = kvmclock_cpufreq_notifier
5473 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5474 unsigned long action, void *hcpu)
5476 unsigned int cpu = (unsigned long)hcpu;
5480 case CPU_DOWN_FAILED:
5481 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5483 case CPU_DOWN_PREPARE:
5484 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5490 static struct notifier_block kvmclock_cpu_notifier_block = {
5491 .notifier_call = kvmclock_cpu_notifier,
5492 .priority = -INT_MAX
5495 static void kvm_timer_init(void)
5499 max_tsc_khz = tsc_khz;
5501 cpu_notifier_register_begin();
5502 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5503 #ifdef CONFIG_CPU_FREQ
5504 struct cpufreq_policy policy;
5505 memset(&policy, 0, sizeof(policy));
5507 cpufreq_get_policy(&policy, cpu);
5508 if (policy.cpuinfo.max_freq)
5509 max_tsc_khz = policy.cpuinfo.max_freq;
5512 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5513 CPUFREQ_TRANSITION_NOTIFIER);
5515 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5516 for_each_online_cpu(cpu)
5517 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5519 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5520 cpu_notifier_register_done();
5524 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5526 int kvm_is_in_guest(void)
5528 return __this_cpu_read(current_vcpu) != NULL;
5531 static int kvm_is_user_mode(void)
5535 if (__this_cpu_read(current_vcpu))
5536 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5538 return user_mode != 0;
5541 static unsigned long kvm_get_guest_ip(void)
5543 unsigned long ip = 0;
5545 if (__this_cpu_read(current_vcpu))
5546 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5551 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5552 .is_in_guest = kvm_is_in_guest,
5553 .is_user_mode = kvm_is_user_mode,
5554 .get_guest_ip = kvm_get_guest_ip,
5557 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5559 __this_cpu_write(current_vcpu, vcpu);
5561 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5563 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5565 __this_cpu_write(current_vcpu, NULL);
5567 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5569 static void kvm_set_mmio_spte_mask(void)
5572 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5575 * Set the reserved bits and the present bit of an paging-structure
5576 * entry to generate page fault with PFER.RSV = 1.
5578 /* Mask the reserved physical address bits. */
5579 mask = rsvd_bits(maxphyaddr, 51);
5581 /* Bit 62 is always reserved for 32bit host. */
5582 mask |= 0x3ull << 62;
5584 /* Set the present bit. */
5587 #ifdef CONFIG_X86_64
5589 * If reserved bit is not supported, clear the present bit to disable
5592 if (maxphyaddr == 52)
5596 kvm_mmu_set_mmio_spte_mask(mask);
5599 #ifdef CONFIG_X86_64
5600 static void pvclock_gtod_update_fn(struct work_struct *work)
5604 struct kvm_vcpu *vcpu;
5607 spin_lock(&kvm_lock);
5608 list_for_each_entry(kvm, &vm_list, vm_list)
5609 kvm_for_each_vcpu(i, vcpu, kvm)
5610 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5611 atomic_set(&kvm_guest_has_master_clock, 0);
5612 spin_unlock(&kvm_lock);
5615 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5618 * Notification about pvclock gtod data update.
5620 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5623 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5624 struct timekeeper *tk = priv;
5626 update_pvclock_gtod(tk);
5628 /* disable master clock if host does not trust, or does not
5629 * use, TSC clocksource
5631 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5632 atomic_read(&kvm_guest_has_master_clock) != 0)
5633 queue_work(system_long_wq, &pvclock_gtod_work);
5638 static struct notifier_block pvclock_gtod_notifier = {
5639 .notifier_call = pvclock_gtod_notify,
5643 int kvm_arch_init(void *opaque)
5646 struct kvm_x86_ops *ops = opaque;
5649 printk(KERN_ERR "kvm: already loaded the other module\n");
5654 if (!ops->cpu_has_kvm_support()) {
5655 printk(KERN_ERR "kvm: no hardware support\n");
5659 if (ops->disabled_by_bios()) {
5660 printk(KERN_ERR "kvm: disabled by bios\n");
5666 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5668 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5672 r = kvm_mmu_module_init();
5674 goto out_free_percpu;
5676 kvm_set_mmio_spte_mask();
5679 kvm_init_msr_list();
5681 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5682 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5686 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5689 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5692 #ifdef CONFIG_X86_64
5693 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5699 free_percpu(shared_msrs);
5704 void kvm_arch_exit(void)
5706 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5708 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5709 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5710 CPUFREQ_TRANSITION_NOTIFIER);
5711 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5712 #ifdef CONFIG_X86_64
5713 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5716 kvm_mmu_module_exit();
5717 free_percpu(shared_msrs);
5720 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5722 ++vcpu->stat.halt_exits;
5723 if (irqchip_in_kernel(vcpu->kvm)) {
5724 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5727 vcpu->run->exit_reason = KVM_EXIT_HLT;
5731 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5733 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5735 u64 param, ingpa, outgpa, ret;
5736 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5737 bool fast, longmode;
5740 * hypercall generates UD from non zero cpl and real mode
5743 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5744 kvm_queue_exception(vcpu, UD_VECTOR);
5748 longmode = is_64_bit_mode(vcpu);
5751 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5752 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5753 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5754 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5755 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5756 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5758 #ifdef CONFIG_X86_64
5760 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5761 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5762 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5766 code = param & 0xffff;
5767 fast = (param >> 16) & 0x1;
5768 rep_cnt = (param >> 32) & 0xfff;
5769 rep_idx = (param >> 48) & 0xfff;
5771 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5774 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5775 kvm_vcpu_on_spin(vcpu);
5778 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5782 ret = res | (((u64)rep_done & 0xfff) << 32);
5784 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5786 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5787 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5794 * kvm_pv_kick_cpu_op: Kick a vcpu.
5796 * @apicid - apicid of vcpu to be kicked.
5798 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5800 struct kvm_lapic_irq lapic_irq;
5802 lapic_irq.shorthand = 0;
5803 lapic_irq.dest_mode = 0;
5804 lapic_irq.dest_id = apicid;
5806 lapic_irq.delivery_mode = APIC_DM_REMRD;
5807 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5810 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5812 unsigned long nr, a0, a1, a2, a3, ret;
5813 int op_64_bit, r = 1;
5815 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5816 return kvm_hv_hypercall(vcpu);
5818 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5819 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5820 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5821 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5822 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5824 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5826 op_64_bit = is_64_bit_mode(vcpu);
5835 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5841 case KVM_HC_VAPIC_POLL_IRQ:
5844 case KVM_HC_KICK_CPU:
5845 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5855 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5856 ++vcpu->stat.hypercalls;
5859 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5861 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5863 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5864 char instruction[3];
5865 unsigned long rip = kvm_rip_read(vcpu);
5867 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5869 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5873 * Check if userspace requested an interrupt window, and that the
5874 * interrupt window is open.
5876 * No need to exit to userspace if we already have an interrupt queued.
5878 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5880 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5881 vcpu->run->request_interrupt_window &&
5882 kvm_arch_interrupt_allowed(vcpu));
5885 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5887 struct kvm_run *kvm_run = vcpu->run;
5889 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5890 kvm_run->cr8 = kvm_get_cr8(vcpu);
5891 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5892 if (irqchip_in_kernel(vcpu->kvm))
5893 kvm_run->ready_for_interrupt_injection = 1;
5895 kvm_run->ready_for_interrupt_injection =
5896 kvm_arch_interrupt_allowed(vcpu) &&
5897 !kvm_cpu_has_interrupt(vcpu) &&
5898 !kvm_event_needs_reinjection(vcpu);
5901 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5905 if (!kvm_x86_ops->update_cr8_intercept)
5908 if (!vcpu->arch.apic)
5911 if (!vcpu->arch.apic->vapic_addr)
5912 max_irr = kvm_lapic_find_highest_irr(vcpu);
5919 tpr = kvm_lapic_get_cr8(vcpu);
5921 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5924 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5928 /* try to reinject previous events if any */
5929 if (vcpu->arch.exception.pending) {
5930 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5931 vcpu->arch.exception.has_error_code,
5932 vcpu->arch.exception.error_code);
5934 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5935 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5938 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5939 vcpu->arch.exception.has_error_code,
5940 vcpu->arch.exception.error_code,
5941 vcpu->arch.exception.reinject);
5945 if (vcpu->arch.nmi_injected) {
5946 kvm_x86_ops->set_nmi(vcpu);
5950 if (vcpu->arch.interrupt.pending) {
5951 kvm_x86_ops->set_irq(vcpu);
5955 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5956 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5961 /* try to inject new event if pending */
5962 if (vcpu->arch.nmi_pending) {
5963 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5964 --vcpu->arch.nmi_pending;
5965 vcpu->arch.nmi_injected = true;
5966 kvm_x86_ops->set_nmi(vcpu);
5968 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5970 * Because interrupts can be injected asynchronously, we are
5971 * calling check_nested_events again here to avoid a race condition.
5972 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5973 * proposal and current concerns. Perhaps we should be setting
5974 * KVM_REQ_EVENT only on certain events and not unconditionally?
5976 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5977 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5981 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5982 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5984 kvm_x86_ops->set_irq(vcpu);
5990 static void process_nmi(struct kvm_vcpu *vcpu)
5995 * x86 is limited to one NMI running, and one NMI pending after it.
5996 * If an NMI is already in progress, limit further NMIs to just one.
5997 * Otherwise, allow two (and we'll inject the first one immediately).
5999 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6002 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6003 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6004 kvm_make_request(KVM_REQ_EVENT, vcpu);
6007 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6009 u64 eoi_exit_bitmap[4];
6012 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6015 memset(eoi_exit_bitmap, 0, 32);
6018 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
6019 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6020 kvm_apic_update_tmr(vcpu, tmr);
6023 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6025 ++vcpu->stat.tlb_flush;
6026 kvm_x86_ops->tlb_flush(vcpu);
6029 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6031 struct page *page = NULL;
6033 if (!irqchip_in_kernel(vcpu->kvm))
6036 if (!kvm_x86_ops->set_apic_access_page_addr)
6039 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6040 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6043 * Do not pin apic access page in memory, the MMU notifier
6044 * will call us again if it is migrated or swapped out.
6048 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6050 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6051 unsigned long address)
6054 * The physical address of apic access page is stored in the VMCS.
6055 * Update it when it becomes invalid.
6057 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6058 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6062 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6063 * exiting to the userspace. Otherwise, the value will be returned to the
6066 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6069 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
6070 vcpu->run->request_interrupt_window;
6071 bool req_immediate_exit = false;
6073 if (vcpu->requests) {
6074 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6075 kvm_mmu_unload(vcpu);
6076 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6077 __kvm_migrate_timers(vcpu);
6078 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6079 kvm_gen_update_masterclock(vcpu->kvm);
6080 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6081 kvm_gen_kvmclock_update(vcpu);
6082 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6083 r = kvm_guest_time_update(vcpu);
6087 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6088 kvm_mmu_sync_roots(vcpu);
6089 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6090 kvm_vcpu_flush_tlb(vcpu);
6091 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6092 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6096 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6097 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6101 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6102 vcpu->fpu_active = 0;
6103 kvm_x86_ops->fpu_deactivate(vcpu);
6105 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6106 /* Page is swapped out. Do synthetic halt */
6107 vcpu->arch.apf.halted = true;
6111 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6112 record_steal_time(vcpu);
6113 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6115 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6116 kvm_handle_pmu_event(vcpu);
6117 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6118 kvm_deliver_pmi(vcpu);
6119 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6120 vcpu_scan_ioapic(vcpu);
6121 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6122 kvm_vcpu_reload_apic_access_page(vcpu);
6125 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6126 kvm_apic_accept_events(vcpu);
6127 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6132 if (inject_pending_event(vcpu, req_int_win) != 0)
6133 req_immediate_exit = true;
6134 /* enable NMI/IRQ window open exits if needed */
6135 else if (vcpu->arch.nmi_pending)
6136 kvm_x86_ops->enable_nmi_window(vcpu);
6137 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6138 kvm_x86_ops->enable_irq_window(vcpu);
6140 if (kvm_lapic_enabled(vcpu)) {
6142 * Update architecture specific hints for APIC
6143 * virtual interrupt delivery.
6145 if (kvm_x86_ops->hwapic_irr_update)
6146 kvm_x86_ops->hwapic_irr_update(vcpu,
6147 kvm_lapic_find_highest_irr(vcpu));
6148 update_cr8_intercept(vcpu);
6149 kvm_lapic_sync_to_vapic(vcpu);
6153 r = kvm_mmu_reload(vcpu);
6155 goto cancel_injection;
6160 kvm_x86_ops->prepare_guest_switch(vcpu);
6161 if (vcpu->fpu_active)
6162 kvm_load_guest_fpu(vcpu);
6163 kvm_load_guest_xcr0(vcpu);
6165 vcpu->mode = IN_GUEST_MODE;
6167 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6169 /* We should set ->mode before check ->requests,
6170 * see the comment in make_all_cpus_request.
6172 smp_mb__after_srcu_read_unlock();
6174 local_irq_disable();
6176 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6177 || need_resched() || signal_pending(current)) {
6178 vcpu->mode = OUTSIDE_GUEST_MODE;
6182 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6184 goto cancel_injection;
6187 if (req_immediate_exit)
6188 smp_send_reschedule(vcpu->cpu);
6192 if (unlikely(vcpu->arch.switch_db_regs)) {
6194 set_debugreg(vcpu->arch.eff_db[0], 0);
6195 set_debugreg(vcpu->arch.eff_db[1], 1);
6196 set_debugreg(vcpu->arch.eff_db[2], 2);
6197 set_debugreg(vcpu->arch.eff_db[3], 3);
6198 set_debugreg(vcpu->arch.dr6, 6);
6201 trace_kvm_entry(vcpu->vcpu_id);
6202 kvm_x86_ops->run(vcpu);
6205 * Do this here before restoring debug registers on the host. And
6206 * since we do this before handling the vmexit, a DR access vmexit
6207 * can (a) read the correct value of the debug registers, (b) set
6208 * KVM_DEBUGREG_WONT_EXIT again.
6210 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6213 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6214 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6215 for (i = 0; i < KVM_NR_DB_REGS; i++)
6216 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6220 * If the guest has used debug registers, at least dr7
6221 * will be disabled while returning to the host.
6222 * If we don't have active breakpoints in the host, we don't
6223 * care about the messed up debug address registers. But if
6224 * we have some of them active, restore the old state.
6226 if (hw_breakpoint_active())
6227 hw_breakpoint_restore();
6229 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6232 vcpu->mode = OUTSIDE_GUEST_MODE;
6235 /* Interrupt is enabled by handle_external_intr() */
6236 kvm_x86_ops->handle_external_intr(vcpu);
6241 * We must have an instruction between local_irq_enable() and
6242 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6243 * the interrupt shadow. The stat.exits increment will do nicely.
6244 * But we need to prevent reordering, hence this barrier():
6252 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6255 * Profile KVM exit RIPs:
6257 if (unlikely(prof_on == KVM_PROFILING)) {
6258 unsigned long rip = kvm_rip_read(vcpu);
6259 profile_hit(KVM_PROFILING, (void *)rip);
6262 if (unlikely(vcpu->arch.tsc_always_catchup))
6263 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6265 if (vcpu->arch.apic_attention)
6266 kvm_lapic_sync_from_vapic(vcpu);
6268 r = kvm_x86_ops->handle_exit(vcpu);
6272 kvm_x86_ops->cancel_injection(vcpu);
6273 if (unlikely(vcpu->arch.apic_attention))
6274 kvm_lapic_sync_from_vapic(vcpu);
6280 static int __vcpu_run(struct kvm_vcpu *vcpu)
6283 struct kvm *kvm = vcpu->kvm;
6285 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6289 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6290 !vcpu->arch.apf.halted)
6291 r = vcpu_enter_guest(vcpu);
6293 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6294 kvm_vcpu_block(vcpu);
6295 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6296 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6297 kvm_apic_accept_events(vcpu);
6298 switch(vcpu->arch.mp_state) {
6299 case KVM_MP_STATE_HALTED:
6300 vcpu->arch.pv.pv_unhalted = false;
6301 vcpu->arch.mp_state =
6302 KVM_MP_STATE_RUNNABLE;
6303 case KVM_MP_STATE_RUNNABLE:
6304 vcpu->arch.apf.halted = false;
6306 case KVM_MP_STATE_INIT_RECEIVED:
6318 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6319 if (kvm_cpu_has_pending_timer(vcpu))
6320 kvm_inject_pending_timer_irqs(vcpu);
6322 if (dm_request_for_irq_injection(vcpu)) {
6324 vcpu->run->exit_reason = KVM_EXIT_INTR;
6325 ++vcpu->stat.request_irq_exits;
6328 kvm_check_async_pf_completion(vcpu);
6330 if (signal_pending(current)) {
6332 vcpu->run->exit_reason = KVM_EXIT_INTR;
6333 ++vcpu->stat.signal_exits;
6335 if (need_resched()) {
6336 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6338 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6342 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6347 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6350 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6351 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6352 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6353 if (r != EMULATE_DONE)
6358 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6360 BUG_ON(!vcpu->arch.pio.count);
6362 return complete_emulated_io(vcpu);
6366 * Implements the following, as a state machine:
6370 * for each mmio piece in the fragment
6378 * for each mmio piece in the fragment
6383 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6385 struct kvm_run *run = vcpu->run;
6386 struct kvm_mmio_fragment *frag;
6389 BUG_ON(!vcpu->mmio_needed);
6391 /* Complete previous fragment */
6392 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6393 len = min(8u, frag->len);
6394 if (!vcpu->mmio_is_write)
6395 memcpy(frag->data, run->mmio.data, len);
6397 if (frag->len <= 8) {
6398 /* Switch to the next fragment. */
6400 vcpu->mmio_cur_fragment++;
6402 /* Go forward to the next mmio piece. */
6408 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6409 vcpu->mmio_needed = 0;
6411 /* FIXME: return into emulator if single-stepping. */
6412 if (vcpu->mmio_is_write)
6414 vcpu->mmio_read_completed = 1;
6415 return complete_emulated_io(vcpu);
6418 run->exit_reason = KVM_EXIT_MMIO;
6419 run->mmio.phys_addr = frag->gpa;
6420 if (vcpu->mmio_is_write)
6421 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6422 run->mmio.len = min(8u, frag->len);
6423 run->mmio.is_write = vcpu->mmio_is_write;
6424 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6429 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6434 if (!tsk_used_math(current) && init_fpu(current))
6437 if (vcpu->sigset_active)
6438 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6440 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6441 kvm_vcpu_block(vcpu);
6442 kvm_apic_accept_events(vcpu);
6443 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6448 /* re-sync apic's tpr */
6449 if (!irqchip_in_kernel(vcpu->kvm)) {
6450 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6456 if (unlikely(vcpu->arch.complete_userspace_io)) {
6457 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6458 vcpu->arch.complete_userspace_io = NULL;
6463 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6465 r = __vcpu_run(vcpu);
6468 post_kvm_run_save(vcpu);
6469 if (vcpu->sigset_active)
6470 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6475 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6477 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6479 * We are here if userspace calls get_regs() in the middle of
6480 * instruction emulation. Registers state needs to be copied
6481 * back from emulation context to vcpu. Userspace shouldn't do
6482 * that usually, but some bad designed PV devices (vmware
6483 * backdoor interface) need this to work
6485 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6486 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6488 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6489 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6490 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6491 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6492 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6493 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6494 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6495 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6496 #ifdef CONFIG_X86_64
6497 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6498 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6499 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6500 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6501 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6502 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6503 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6504 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6507 regs->rip = kvm_rip_read(vcpu);
6508 regs->rflags = kvm_get_rflags(vcpu);
6513 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6515 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6516 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6518 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6519 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6520 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6521 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6522 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6523 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6524 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6525 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6526 #ifdef CONFIG_X86_64
6527 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6528 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6529 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6530 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6531 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6532 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6533 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6534 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6537 kvm_rip_write(vcpu, regs->rip);
6538 kvm_set_rflags(vcpu, regs->rflags);
6540 vcpu->arch.exception.pending = false;
6542 kvm_make_request(KVM_REQ_EVENT, vcpu);
6547 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6549 struct kvm_segment cs;
6551 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6555 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6557 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6558 struct kvm_sregs *sregs)
6562 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6563 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6564 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6565 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6566 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6567 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6569 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6570 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6572 kvm_x86_ops->get_idt(vcpu, &dt);
6573 sregs->idt.limit = dt.size;
6574 sregs->idt.base = dt.address;
6575 kvm_x86_ops->get_gdt(vcpu, &dt);
6576 sregs->gdt.limit = dt.size;
6577 sregs->gdt.base = dt.address;
6579 sregs->cr0 = kvm_read_cr0(vcpu);
6580 sregs->cr2 = vcpu->arch.cr2;
6581 sregs->cr3 = kvm_read_cr3(vcpu);
6582 sregs->cr4 = kvm_read_cr4(vcpu);
6583 sregs->cr8 = kvm_get_cr8(vcpu);
6584 sregs->efer = vcpu->arch.efer;
6585 sregs->apic_base = kvm_get_apic_base(vcpu);
6587 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6589 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6590 set_bit(vcpu->arch.interrupt.nr,
6591 (unsigned long *)sregs->interrupt_bitmap);
6596 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6597 struct kvm_mp_state *mp_state)
6599 kvm_apic_accept_events(vcpu);
6600 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6601 vcpu->arch.pv.pv_unhalted)
6602 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6604 mp_state->mp_state = vcpu->arch.mp_state;
6609 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6610 struct kvm_mp_state *mp_state)
6612 if (!kvm_vcpu_has_lapic(vcpu) &&
6613 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6616 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6617 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6618 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6620 vcpu->arch.mp_state = mp_state->mp_state;
6621 kvm_make_request(KVM_REQ_EVENT, vcpu);
6625 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6626 int reason, bool has_error_code, u32 error_code)
6628 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6631 init_emulate_ctxt(vcpu);
6633 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6634 has_error_code, error_code);
6637 return EMULATE_FAIL;
6639 kvm_rip_write(vcpu, ctxt->eip);
6640 kvm_set_rflags(vcpu, ctxt->eflags);
6641 kvm_make_request(KVM_REQ_EVENT, vcpu);
6642 return EMULATE_DONE;
6644 EXPORT_SYMBOL_GPL(kvm_task_switch);
6646 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6647 struct kvm_sregs *sregs)
6649 struct msr_data apic_base_msr;
6650 int mmu_reset_needed = 0;
6651 int pending_vec, max_bits, idx;
6654 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6657 dt.size = sregs->idt.limit;
6658 dt.address = sregs->idt.base;
6659 kvm_x86_ops->set_idt(vcpu, &dt);
6660 dt.size = sregs->gdt.limit;
6661 dt.address = sregs->gdt.base;
6662 kvm_x86_ops->set_gdt(vcpu, &dt);
6664 vcpu->arch.cr2 = sregs->cr2;
6665 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6666 vcpu->arch.cr3 = sregs->cr3;
6667 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6669 kvm_set_cr8(vcpu, sregs->cr8);
6671 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6672 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6673 apic_base_msr.data = sregs->apic_base;
6674 apic_base_msr.host_initiated = true;
6675 kvm_set_apic_base(vcpu, &apic_base_msr);
6677 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6678 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6679 vcpu->arch.cr0 = sregs->cr0;
6681 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6682 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6683 if (sregs->cr4 & X86_CR4_OSXSAVE)
6684 kvm_update_cpuid(vcpu);
6686 idx = srcu_read_lock(&vcpu->kvm->srcu);
6687 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6688 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6689 mmu_reset_needed = 1;
6691 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6693 if (mmu_reset_needed)
6694 kvm_mmu_reset_context(vcpu);
6696 max_bits = KVM_NR_INTERRUPTS;
6697 pending_vec = find_first_bit(
6698 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6699 if (pending_vec < max_bits) {
6700 kvm_queue_interrupt(vcpu, pending_vec, false);
6701 pr_debug("Set back pending irq %d\n", pending_vec);
6704 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6705 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6706 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6707 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6708 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6709 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6711 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6712 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6714 update_cr8_intercept(vcpu);
6716 /* Older userspace won't unhalt the vcpu on reset. */
6717 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6718 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6720 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6722 kvm_make_request(KVM_REQ_EVENT, vcpu);
6727 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6728 struct kvm_guest_debug *dbg)
6730 unsigned long rflags;
6733 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6735 if (vcpu->arch.exception.pending)
6737 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6738 kvm_queue_exception(vcpu, DB_VECTOR);
6740 kvm_queue_exception(vcpu, BP_VECTOR);
6744 * Read rflags as long as potentially injected trace flags are still
6747 rflags = kvm_get_rflags(vcpu);
6749 vcpu->guest_debug = dbg->control;
6750 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6751 vcpu->guest_debug = 0;
6753 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6754 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6755 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6756 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6758 for (i = 0; i < KVM_NR_DB_REGS; i++)
6759 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6761 kvm_update_dr7(vcpu);
6763 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6764 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6765 get_segment_base(vcpu, VCPU_SREG_CS);
6768 * Trigger an rflags update that will inject or remove the trace
6771 kvm_set_rflags(vcpu, rflags);
6773 kvm_x86_ops->update_db_bp_intercept(vcpu);
6783 * Translate a guest virtual address to a guest physical address.
6785 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6786 struct kvm_translation *tr)
6788 unsigned long vaddr = tr->linear_address;
6792 idx = srcu_read_lock(&vcpu->kvm->srcu);
6793 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6794 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6795 tr->physical_address = gpa;
6796 tr->valid = gpa != UNMAPPED_GVA;
6803 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6805 struct i387_fxsave_struct *fxsave =
6806 &vcpu->arch.guest_fpu.state->fxsave;
6808 memcpy(fpu->fpr, fxsave->st_space, 128);
6809 fpu->fcw = fxsave->cwd;
6810 fpu->fsw = fxsave->swd;
6811 fpu->ftwx = fxsave->twd;
6812 fpu->last_opcode = fxsave->fop;
6813 fpu->last_ip = fxsave->rip;
6814 fpu->last_dp = fxsave->rdp;
6815 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6820 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6822 struct i387_fxsave_struct *fxsave =
6823 &vcpu->arch.guest_fpu.state->fxsave;
6825 memcpy(fxsave->st_space, fpu->fpr, 128);
6826 fxsave->cwd = fpu->fcw;
6827 fxsave->swd = fpu->fsw;
6828 fxsave->twd = fpu->ftwx;
6829 fxsave->fop = fpu->last_opcode;
6830 fxsave->rip = fpu->last_ip;
6831 fxsave->rdp = fpu->last_dp;
6832 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6837 int fx_init(struct kvm_vcpu *vcpu)
6841 err = fpu_alloc(&vcpu->arch.guest_fpu);
6845 fpu_finit(&vcpu->arch.guest_fpu);
6848 * Ensure guest xcr0 is valid for loading
6850 vcpu->arch.xcr0 = XSTATE_FP;
6852 vcpu->arch.cr0 |= X86_CR0_ET;
6856 EXPORT_SYMBOL_GPL(fx_init);
6858 static void fx_free(struct kvm_vcpu *vcpu)
6860 fpu_free(&vcpu->arch.guest_fpu);
6863 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6865 if (vcpu->guest_fpu_loaded)
6869 * Restore all possible states in the guest,
6870 * and assume host would use all available bits.
6871 * Guest xcr0 would be loaded later.
6873 kvm_put_guest_xcr0(vcpu);
6874 vcpu->guest_fpu_loaded = 1;
6875 __kernel_fpu_begin();
6876 fpu_restore_checking(&vcpu->arch.guest_fpu);
6880 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6882 kvm_put_guest_xcr0(vcpu);
6884 if (!vcpu->guest_fpu_loaded)
6887 vcpu->guest_fpu_loaded = 0;
6888 fpu_save_init(&vcpu->arch.guest_fpu);
6890 ++vcpu->stat.fpu_reload;
6891 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6895 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6897 kvmclock_reset(vcpu);
6899 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6901 kvm_x86_ops->vcpu_free(vcpu);
6904 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6907 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6908 printk_once(KERN_WARNING
6909 "kvm: SMP vm created on host with unstable TSC; "
6910 "guest TSC will not be reliable\n");
6911 return kvm_x86_ops->vcpu_create(kvm, id);
6914 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6918 vcpu->arch.mtrr_state.have_fixed = 1;
6919 r = vcpu_load(vcpu);
6922 kvm_vcpu_reset(vcpu);
6923 kvm_mmu_setup(vcpu);
6929 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6932 struct msr_data msr;
6933 struct kvm *kvm = vcpu->kvm;
6935 r = vcpu_load(vcpu);
6939 msr.index = MSR_IA32_TSC;
6940 msr.host_initiated = true;
6941 kvm_write_tsc(vcpu, &msr);
6944 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6945 KVMCLOCK_SYNC_PERIOD);
6950 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6953 vcpu->arch.apf.msr_val = 0;
6955 r = vcpu_load(vcpu);
6957 kvm_mmu_unload(vcpu);
6961 kvm_x86_ops->vcpu_free(vcpu);
6964 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6966 atomic_set(&vcpu->arch.nmi_queued, 0);
6967 vcpu->arch.nmi_pending = 0;
6968 vcpu->arch.nmi_injected = false;
6969 kvm_clear_interrupt_queue(vcpu);
6970 kvm_clear_exception_queue(vcpu);
6972 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6973 vcpu->arch.dr6 = DR6_INIT;
6974 kvm_update_dr6(vcpu);
6975 vcpu->arch.dr7 = DR7_FIXED_1;
6976 kvm_update_dr7(vcpu);
6978 kvm_make_request(KVM_REQ_EVENT, vcpu);
6979 vcpu->arch.apf.msr_val = 0;
6980 vcpu->arch.st.msr_val = 0;
6982 kvmclock_reset(vcpu);
6984 kvm_clear_async_pf_completion_queue(vcpu);
6985 kvm_async_pf_hash_reset(vcpu);
6986 vcpu->arch.apf.halted = false;
6988 kvm_pmu_reset(vcpu);
6990 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6991 vcpu->arch.regs_avail = ~0;
6992 vcpu->arch.regs_dirty = ~0;
6994 kvm_x86_ops->vcpu_reset(vcpu);
6997 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6999 struct kvm_segment cs;
7001 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7002 cs.selector = vector << 8;
7003 cs.base = vector << 12;
7004 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7005 kvm_rip_write(vcpu, 0);
7008 int kvm_arch_hardware_enable(void)
7011 struct kvm_vcpu *vcpu;
7016 bool stable, backwards_tsc = false;
7018 kvm_shared_msr_cpu_online();
7019 ret = kvm_x86_ops->hardware_enable();
7023 local_tsc = native_read_tsc();
7024 stable = !check_tsc_unstable();
7025 list_for_each_entry(kvm, &vm_list, vm_list) {
7026 kvm_for_each_vcpu(i, vcpu, kvm) {
7027 if (!stable && vcpu->cpu == smp_processor_id())
7028 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7029 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7030 backwards_tsc = true;
7031 if (vcpu->arch.last_host_tsc > max_tsc)
7032 max_tsc = vcpu->arch.last_host_tsc;
7038 * Sometimes, even reliable TSCs go backwards. This happens on
7039 * platforms that reset TSC during suspend or hibernate actions, but
7040 * maintain synchronization. We must compensate. Fortunately, we can
7041 * detect that condition here, which happens early in CPU bringup,
7042 * before any KVM threads can be running. Unfortunately, we can't
7043 * bring the TSCs fully up to date with real time, as we aren't yet far
7044 * enough into CPU bringup that we know how much real time has actually
7045 * elapsed; our helper function, get_kernel_ns() will be using boot
7046 * variables that haven't been updated yet.
7048 * So we simply find the maximum observed TSC above, then record the
7049 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7050 * the adjustment will be applied. Note that we accumulate
7051 * adjustments, in case multiple suspend cycles happen before some VCPU
7052 * gets a chance to run again. In the event that no KVM threads get a
7053 * chance to run, we will miss the entire elapsed period, as we'll have
7054 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7055 * loose cycle time. This isn't too big a deal, since the loss will be
7056 * uniform across all VCPUs (not to mention the scenario is extremely
7057 * unlikely). It is possible that a second hibernate recovery happens
7058 * much faster than a first, causing the observed TSC here to be
7059 * smaller; this would require additional padding adjustment, which is
7060 * why we set last_host_tsc to the local tsc observed here.
7062 * N.B. - this code below runs only on platforms with reliable TSC,
7063 * as that is the only way backwards_tsc is set above. Also note
7064 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7065 * have the same delta_cyc adjustment applied if backwards_tsc
7066 * is detected. Note further, this adjustment is only done once,
7067 * as we reset last_host_tsc on all VCPUs to stop this from being
7068 * called multiple times (one for each physical CPU bringup).
7070 * Platforms with unreliable TSCs don't have to deal with this, they
7071 * will be compensated by the logic in vcpu_load, which sets the TSC to
7072 * catchup mode. This will catchup all VCPUs to real time, but cannot
7073 * guarantee that they stay in perfect synchronization.
7075 if (backwards_tsc) {
7076 u64 delta_cyc = max_tsc - local_tsc;
7077 backwards_tsc_observed = true;
7078 list_for_each_entry(kvm, &vm_list, vm_list) {
7079 kvm_for_each_vcpu(i, vcpu, kvm) {
7080 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7081 vcpu->arch.last_host_tsc = local_tsc;
7082 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7086 * We have to disable TSC offset matching.. if you were
7087 * booting a VM while issuing an S4 host suspend....
7088 * you may have some problem. Solving this issue is
7089 * left as an exercise to the reader.
7091 kvm->arch.last_tsc_nsec = 0;
7092 kvm->arch.last_tsc_write = 0;
7099 void kvm_arch_hardware_disable(void)
7101 kvm_x86_ops->hardware_disable();
7102 drop_user_return_notifiers();
7105 int kvm_arch_hardware_setup(void)
7107 return kvm_x86_ops->hardware_setup();
7110 void kvm_arch_hardware_unsetup(void)
7112 kvm_x86_ops->hardware_unsetup();
7115 void kvm_arch_check_processor_compat(void *rtn)
7117 kvm_x86_ops->check_processor_compatibility(rtn);
7120 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7122 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7125 struct static_key kvm_no_apic_vcpu __read_mostly;
7127 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7133 BUG_ON(vcpu->kvm == NULL);
7136 vcpu->arch.pv.pv_unhalted = false;
7137 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7138 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
7139 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7141 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7143 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7148 vcpu->arch.pio_data = page_address(page);
7150 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7152 r = kvm_mmu_create(vcpu);
7154 goto fail_free_pio_data;
7156 if (irqchip_in_kernel(kvm)) {
7157 r = kvm_create_lapic(vcpu);
7159 goto fail_mmu_destroy;
7161 static_key_slow_inc(&kvm_no_apic_vcpu);
7163 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7165 if (!vcpu->arch.mce_banks) {
7167 goto fail_free_lapic;
7169 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7171 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7173 goto fail_free_mce_banks;
7178 goto fail_free_wbinvd_dirty_mask;
7180 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7181 vcpu->arch.pv_time_enabled = false;
7183 vcpu->arch.guest_supported_xcr0 = 0;
7184 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7186 kvm_async_pf_hash_reset(vcpu);
7190 fail_free_wbinvd_dirty_mask:
7191 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7192 fail_free_mce_banks:
7193 kfree(vcpu->arch.mce_banks);
7195 kvm_free_lapic(vcpu);
7197 kvm_mmu_destroy(vcpu);
7199 free_page((unsigned long)vcpu->arch.pio_data);
7204 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7208 kvm_pmu_destroy(vcpu);
7209 kfree(vcpu->arch.mce_banks);
7210 kvm_free_lapic(vcpu);
7211 idx = srcu_read_lock(&vcpu->kvm->srcu);
7212 kvm_mmu_destroy(vcpu);
7213 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7214 free_page((unsigned long)vcpu->arch.pio_data);
7215 if (!irqchip_in_kernel(vcpu->kvm))
7216 static_key_slow_dec(&kvm_no_apic_vcpu);
7219 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7221 kvm_x86_ops->sched_in(vcpu, cpu);
7224 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7229 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7230 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7231 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7232 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7234 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7235 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7236 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7237 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7238 &kvm->arch.irq_sources_bitmap);
7240 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7241 mutex_init(&kvm->arch.apic_map_lock);
7242 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7244 pvclock_update_vm_gtod_copy(kvm);
7246 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7247 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7252 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7255 r = vcpu_load(vcpu);
7257 kvm_mmu_unload(vcpu);
7261 static void kvm_free_vcpus(struct kvm *kvm)
7264 struct kvm_vcpu *vcpu;
7267 * Unpin any mmu pages first.
7269 kvm_for_each_vcpu(i, vcpu, kvm) {
7270 kvm_clear_async_pf_completion_queue(vcpu);
7271 kvm_unload_vcpu_mmu(vcpu);
7273 kvm_for_each_vcpu(i, vcpu, kvm)
7274 kvm_arch_vcpu_free(vcpu);
7276 mutex_lock(&kvm->lock);
7277 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7278 kvm->vcpus[i] = NULL;
7280 atomic_set(&kvm->online_vcpus, 0);
7281 mutex_unlock(&kvm->lock);
7284 void kvm_arch_sync_events(struct kvm *kvm)
7286 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7287 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7288 kvm_free_all_assigned_devices(kvm);
7292 void kvm_arch_destroy_vm(struct kvm *kvm)
7294 if (current->mm == kvm->mm) {
7296 * Free memory regions allocated on behalf of userspace,
7297 * unless the the memory map has changed due to process exit
7300 struct kvm_userspace_memory_region mem;
7301 memset(&mem, 0, sizeof(mem));
7302 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7303 kvm_set_memory_region(kvm, &mem);
7305 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7306 kvm_set_memory_region(kvm, &mem);
7308 mem.slot = TSS_PRIVATE_MEMSLOT;
7309 kvm_set_memory_region(kvm, &mem);
7311 kvm_iommu_unmap_guest(kvm);
7312 kfree(kvm->arch.vpic);
7313 kfree(kvm->arch.vioapic);
7314 kvm_free_vcpus(kvm);
7315 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7318 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7319 struct kvm_memory_slot *dont)
7323 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7324 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7325 kvm_kvfree(free->arch.rmap[i]);
7326 free->arch.rmap[i] = NULL;
7331 if (!dont || free->arch.lpage_info[i - 1] !=
7332 dont->arch.lpage_info[i - 1]) {
7333 kvm_kvfree(free->arch.lpage_info[i - 1]);
7334 free->arch.lpage_info[i - 1] = NULL;
7339 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7340 unsigned long npages)
7344 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7349 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7350 slot->base_gfn, level) + 1;
7352 slot->arch.rmap[i] =
7353 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7354 if (!slot->arch.rmap[i])
7359 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7360 sizeof(*slot->arch.lpage_info[i - 1]));
7361 if (!slot->arch.lpage_info[i - 1])
7364 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7365 slot->arch.lpage_info[i - 1][0].write_count = 1;
7366 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7367 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7368 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7370 * If the gfn and userspace address are not aligned wrt each
7371 * other, or if explicitly asked to, disable large page
7372 * support for this slot
7374 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7375 !kvm_largepages_enabled()) {
7378 for (j = 0; j < lpages; ++j)
7379 slot->arch.lpage_info[i - 1][j].write_count = 1;
7386 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7387 kvm_kvfree(slot->arch.rmap[i]);
7388 slot->arch.rmap[i] = NULL;
7392 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7393 slot->arch.lpage_info[i - 1] = NULL;
7398 void kvm_arch_memslots_updated(struct kvm *kvm)
7401 * memslots->generation has been incremented.
7402 * mmio generation may have reached its maximum value.
7404 kvm_mmu_invalidate_mmio_sptes(kvm);
7407 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7408 struct kvm_memory_slot *memslot,
7409 struct kvm_userspace_memory_region *mem,
7410 enum kvm_mr_change change)
7413 * Only private memory slots need to be mapped here since
7414 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7416 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7417 unsigned long userspace_addr;
7420 * MAP_SHARED to prevent internal slot pages from being moved
7423 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7424 PROT_READ | PROT_WRITE,
7425 MAP_SHARED | MAP_ANONYMOUS, 0);
7427 if (IS_ERR((void *)userspace_addr))
7428 return PTR_ERR((void *)userspace_addr);
7430 memslot->userspace_addr = userspace_addr;
7436 void kvm_arch_commit_memory_region(struct kvm *kvm,
7437 struct kvm_userspace_memory_region *mem,
7438 const struct kvm_memory_slot *old,
7439 enum kvm_mr_change change)
7442 int nr_mmu_pages = 0;
7444 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7447 ret = vm_munmap(old->userspace_addr,
7448 old->npages * PAGE_SIZE);
7451 "kvm_vm_ioctl_set_memory_region: "
7452 "failed to munmap memory\n");
7455 if (!kvm->arch.n_requested_mmu_pages)
7456 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7459 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7461 * Write protect all pages for dirty logging.
7463 * All the sptes including the large sptes which point to this
7464 * slot are set to readonly. We can not create any new large
7465 * spte on this slot until the end of the logging.
7467 * See the comments in fast_page_fault().
7469 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7470 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7473 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7475 kvm_mmu_invalidate_zap_all_pages(kvm);
7478 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7479 struct kvm_memory_slot *slot)
7481 kvm_mmu_invalidate_zap_all_pages(kvm);
7484 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7486 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7487 kvm_x86_ops->check_nested_events(vcpu, false);
7489 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7490 !vcpu->arch.apf.halted)
7491 || !list_empty_careful(&vcpu->async_pf.done)
7492 || kvm_apic_has_events(vcpu)
7493 || vcpu->arch.pv.pv_unhalted
7494 || atomic_read(&vcpu->arch.nmi_queued) ||
7495 (kvm_arch_interrupt_allowed(vcpu) &&
7496 kvm_cpu_has_interrupt(vcpu));
7499 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7501 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7504 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7506 return kvm_x86_ops->interrupt_allowed(vcpu);
7509 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7511 unsigned long current_rip = kvm_rip_read(vcpu) +
7512 get_segment_base(vcpu, VCPU_SREG_CS);
7514 return current_rip == linear_rip;
7516 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7518 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7520 unsigned long rflags;
7522 rflags = kvm_x86_ops->get_rflags(vcpu);
7523 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7524 rflags &= ~X86_EFLAGS_TF;
7527 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7529 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7531 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7532 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7533 rflags |= X86_EFLAGS_TF;
7534 kvm_x86_ops->set_rflags(vcpu, rflags);
7537 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7539 __kvm_set_rflags(vcpu, rflags);
7540 kvm_make_request(KVM_REQ_EVENT, vcpu);
7542 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7544 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7548 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7552 r = kvm_mmu_reload(vcpu);
7556 if (!vcpu->arch.mmu.direct_map &&
7557 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7560 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7563 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7565 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7568 static inline u32 kvm_async_pf_next_probe(u32 key)
7570 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7573 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7575 u32 key = kvm_async_pf_hash_fn(gfn);
7577 while (vcpu->arch.apf.gfns[key] != ~0)
7578 key = kvm_async_pf_next_probe(key);
7580 vcpu->arch.apf.gfns[key] = gfn;
7583 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7586 u32 key = kvm_async_pf_hash_fn(gfn);
7588 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7589 (vcpu->arch.apf.gfns[key] != gfn &&
7590 vcpu->arch.apf.gfns[key] != ~0); i++)
7591 key = kvm_async_pf_next_probe(key);
7596 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7598 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7601 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7605 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7607 vcpu->arch.apf.gfns[i] = ~0;
7609 j = kvm_async_pf_next_probe(j);
7610 if (vcpu->arch.apf.gfns[j] == ~0)
7612 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7614 * k lies cyclically in ]i,j]
7616 * |....j i.k.| or |.k..j i...|
7618 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7619 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7624 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7627 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7631 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7632 struct kvm_async_pf *work)
7634 struct x86_exception fault;
7636 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7637 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7639 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7640 (vcpu->arch.apf.send_user_only &&
7641 kvm_x86_ops->get_cpl(vcpu) == 0))
7642 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7643 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7644 fault.vector = PF_VECTOR;
7645 fault.error_code_valid = true;
7646 fault.error_code = 0;
7647 fault.nested_page_fault = false;
7648 fault.address = work->arch.token;
7649 kvm_inject_page_fault(vcpu, &fault);
7653 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7654 struct kvm_async_pf *work)
7656 struct x86_exception fault;
7658 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7659 if (work->wakeup_all)
7660 work->arch.token = ~0; /* broadcast wakeup */
7662 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7664 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7665 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7666 fault.vector = PF_VECTOR;
7667 fault.error_code_valid = true;
7668 fault.error_code = 0;
7669 fault.nested_page_fault = false;
7670 fault.address = work->arch.token;
7671 kvm_inject_page_fault(vcpu, &fault);
7673 vcpu->arch.apf.halted = false;
7674 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7677 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7679 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7682 return !kvm_event_needs_reinjection(vcpu) &&
7683 kvm_x86_ops->interrupt_allowed(vcpu);
7686 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7688 atomic_inc(&kvm->arch.noncoherent_dma_count);
7690 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7692 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7694 atomic_dec(&kvm->arch.noncoherent_dma_count);
7696 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7698 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7700 return atomic_read(&kvm->arch.noncoherent_dma_count);
7702 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7704 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7705 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7706 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7707 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7708 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7709 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7710 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7711 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7712 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7713 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7714 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7715 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7716 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7717 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);