2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
30 #include "assigned-dev.h"
32 #include <linux/clocksource.h>
33 #include <linux/interrupt.h>
34 #include <linux/kvm.h>
36 #include <linux/vmalloc.h>
37 #include <linux/module.h>
38 #include <linux/mman.h>
39 #include <linux/highmem.h>
40 #include <linux/iommu.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/cpufreq.h>
43 #include <linux/user-return-notifier.h>
44 #include <linux/srcu.h>
45 #include <linux/slab.h>
46 #include <linux/perf_event.h>
47 #include <linux/uaccess.h>
48 #include <linux/hash.h>
49 #include <linux/pci.h>
50 #include <linux/timekeeper_internal.h>
51 #include <linux/pvclock_gtod.h>
52 #include <trace/events/kvm.h>
54 #define CREATE_TRACE_POINTS
57 #include <asm/debugreg.h>
62 #include <linux/kernel_stat.h>
63 #include <asm/fpu/internal.h> /* Ugh! */
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92 struct kvm_x86_ops *kvm_x86_ops;
93 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95 static bool ignore_msrs = 0;
96 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98 unsigned int min_timer_period_us = 500;
99 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101 bool kvm_has_tsc_control;
102 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103 u32 kvm_max_guest_tsc_khz;
104 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107 static u32 tsc_tolerance_ppm = 250;
108 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
111 unsigned int lapic_timer_advance_ns = 0;
112 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114 static bool backwards_tsc_observed = false;
116 #define KVM_NR_SHARED_MSRS 16
118 struct kvm_shared_msrs_global {
120 u32 msrs[KVM_NR_SHARED_MSRS];
123 struct kvm_shared_msrs {
124 struct user_return_notifier urn;
126 struct kvm_shared_msr_values {
129 } values[KVM_NR_SHARED_MSRS];
132 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
133 static struct kvm_shared_msrs __percpu *shared_msrs;
135 struct kvm_stats_debugfs_item debugfs_entries[] = {
136 { "pf_fixed", VCPU_STAT(pf_fixed) },
137 { "pf_guest", VCPU_STAT(pf_guest) },
138 { "tlb_flush", VCPU_STAT(tlb_flush) },
139 { "invlpg", VCPU_STAT(invlpg) },
140 { "exits", VCPU_STAT(exits) },
141 { "io_exits", VCPU_STAT(io_exits) },
142 { "mmio_exits", VCPU_STAT(mmio_exits) },
143 { "signal_exits", VCPU_STAT(signal_exits) },
144 { "irq_window", VCPU_STAT(irq_window_exits) },
145 { "nmi_window", VCPU_STAT(nmi_window_exits) },
146 { "halt_exits", VCPU_STAT(halt_exits) },
147 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
148 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
149 { "hypercalls", VCPU_STAT(hypercalls) },
150 { "request_irq", VCPU_STAT(request_irq_exits) },
151 { "irq_exits", VCPU_STAT(irq_exits) },
152 { "host_state_reload", VCPU_STAT(host_state_reload) },
153 { "efer_reload", VCPU_STAT(efer_reload) },
154 { "fpu_reload", VCPU_STAT(fpu_reload) },
155 { "insn_emulation", VCPU_STAT(insn_emulation) },
156 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
157 { "irq_injections", VCPU_STAT(irq_injections) },
158 { "nmi_injections", VCPU_STAT(nmi_injections) },
159 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
160 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
161 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
162 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
163 { "mmu_flooded", VM_STAT(mmu_flooded) },
164 { "mmu_recycled", VM_STAT(mmu_recycled) },
165 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
166 { "mmu_unsync", VM_STAT(mmu_unsync) },
167 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
168 { "largepages", VM_STAT(lpages) },
172 u64 __read_mostly host_xcr0;
174 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
176 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
179 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
180 vcpu->arch.apf.gfns[i] = ~0;
183 static void kvm_on_user_return(struct user_return_notifier *urn)
186 struct kvm_shared_msrs *locals
187 = container_of(urn, struct kvm_shared_msrs, urn);
188 struct kvm_shared_msr_values *values;
190 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
191 values = &locals->values[slot];
192 if (values->host != values->curr) {
193 wrmsrl(shared_msrs_global.msrs[slot], values->host);
194 values->curr = values->host;
197 locals->registered = false;
198 user_return_notifier_unregister(urn);
201 static void shared_msr_update(unsigned slot, u32 msr)
204 unsigned int cpu = smp_processor_id();
205 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
207 /* only read, and nobody should modify it at this time,
208 * so don't need lock */
209 if (slot >= shared_msrs_global.nr) {
210 printk(KERN_ERR "kvm: invalid MSR slot!");
213 rdmsrl_safe(msr, &value);
214 smsr->values[slot].host = value;
215 smsr->values[slot].curr = value;
218 void kvm_define_shared_msr(unsigned slot, u32 msr)
220 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
221 if (slot >= shared_msrs_global.nr)
222 shared_msrs_global.nr = slot + 1;
223 shared_msrs_global.msrs[slot] = msr;
224 /* we need ensured the shared_msr_global have been updated */
227 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
229 static void kvm_shared_msr_cpu_online(void)
233 for (i = 0; i < shared_msrs_global.nr; ++i)
234 shared_msr_update(i, shared_msrs_global.msrs[i]);
237 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
243 if (((value ^ smsr->values[slot].curr) & mask) == 0)
245 smsr->values[slot].curr = value;
246 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (!smsr->registered) {
251 smsr->urn.on_user_return = kvm_on_user_return;
252 user_return_notifier_register(&smsr->urn);
253 smsr->registered = true;
257 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
259 static void drop_user_return_notifiers(void)
261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
264 if (smsr->registered)
265 kvm_on_user_return(&smsr->urn);
268 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
270 return vcpu->arch.apic_base;
272 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
274 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
276 u64 old_state = vcpu->arch.apic_base &
277 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
278 u64 new_state = msr_info->data &
279 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
280 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
281 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
283 if (!msr_info->host_initiated &&
284 ((msr_info->data & reserved_bits) != 0 ||
285 new_state == X2APIC_ENABLE ||
286 (new_state == MSR_IA32_APICBASE_ENABLE &&
287 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
288 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 kvm_lapic_set_base(vcpu, msr_info->data);
295 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
297 asmlinkage __visible void kvm_spurious_fault(void)
299 /* Fault while not rebooting. We want the trace. */
302 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
304 #define EXCPT_BENIGN 0
305 #define EXCPT_CONTRIBUTORY 1
308 static int exception_class(int vector)
318 return EXCPT_CONTRIBUTORY;
325 #define EXCPT_FAULT 0
327 #define EXCPT_ABORT 2
328 #define EXCPT_INTERRUPT 3
330 static int exception_type(int vector)
334 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
335 return EXCPT_INTERRUPT;
339 /* #DB is trap, as instruction watchpoints are handled elsewhere */
340 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
343 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
346 /* Reserved exceptions will result in fault */
350 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
351 unsigned nr, bool has_error, u32 error_code,
357 kvm_make_request(KVM_REQ_EVENT, vcpu);
359 if (!vcpu->arch.exception.pending) {
361 if (has_error && !is_protmode(vcpu))
363 vcpu->arch.exception.pending = true;
364 vcpu->arch.exception.has_error_code = has_error;
365 vcpu->arch.exception.nr = nr;
366 vcpu->arch.exception.error_code = error_code;
367 vcpu->arch.exception.reinject = reinject;
371 /* to check exception */
372 prev_nr = vcpu->arch.exception.nr;
373 if (prev_nr == DF_VECTOR) {
374 /* triple fault -> shutdown */
375 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
378 class1 = exception_class(prev_nr);
379 class2 = exception_class(nr);
380 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
381 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
382 /* generate double fault per SDM Table 5-5 */
383 vcpu->arch.exception.pending = true;
384 vcpu->arch.exception.has_error_code = true;
385 vcpu->arch.exception.nr = DF_VECTOR;
386 vcpu->arch.exception.error_code = 0;
388 /* replace previous exception with a new one in a hope
389 that instruction re-execution will regenerate lost
394 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396 kvm_multiple_exception(vcpu, nr, false, 0, false);
398 EXPORT_SYMBOL_GPL(kvm_queue_exception);
400 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
402 kvm_multiple_exception(vcpu, nr, false, 0, true);
404 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
406 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
409 kvm_inject_gp(vcpu, 0);
411 kvm_x86_ops->skip_emulated_instruction(vcpu);
413 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
415 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
417 ++vcpu->stat.pf_guest;
418 vcpu->arch.cr2 = fault->address;
419 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
421 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
423 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
425 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
426 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
428 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
430 return fault->nested_page_fault;
433 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
435 atomic_inc(&vcpu->arch.nmi_queued);
436 kvm_make_request(KVM_REQ_NMI, vcpu);
438 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
440 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442 kvm_multiple_exception(vcpu, nr, true, error_code, false);
444 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
446 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
448 kvm_multiple_exception(vcpu, nr, true, error_code, true);
450 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
453 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
454 * a #GP and return false.
456 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
458 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
460 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
463 EXPORT_SYMBOL_GPL(kvm_require_cpl);
465 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
467 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
470 kvm_queue_exception(vcpu, UD_VECTOR);
473 EXPORT_SYMBOL_GPL(kvm_require_dr);
476 * This function will be used to read from the physical memory of the currently
477 * running guest. The difference to kvm_read_guest_page is that this function
478 * can read from guest physical or from the guest's guest physical memory.
480 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
481 gfn_t ngfn, void *data, int offset, int len,
484 struct x86_exception exception;
488 ngpa = gfn_to_gpa(ngfn);
489 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
490 if (real_gfn == UNMAPPED_GVA)
493 real_gfn = gpa_to_gfn(real_gfn);
495 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
497 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
499 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
500 void *data, int offset, int len, u32 access)
502 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
503 data, offset, len, access);
507 * Load the pae pdptrs. Return true is they are all valid.
509 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
511 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
512 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
515 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
517 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
518 offset * sizeof(u64), sizeof(pdpte),
519 PFERR_USER_MASK|PFERR_WRITE_MASK);
524 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
525 if (is_present_gpte(pdpte[i]) &&
526 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
533 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
534 __set_bit(VCPU_EXREG_PDPTR,
535 (unsigned long *)&vcpu->arch.regs_avail);
536 __set_bit(VCPU_EXREG_PDPTR,
537 (unsigned long *)&vcpu->arch.regs_dirty);
542 EXPORT_SYMBOL_GPL(load_pdptrs);
544 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
546 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
552 if (is_long_mode(vcpu) || !is_pae(vcpu))
555 if (!test_bit(VCPU_EXREG_PDPTR,
556 (unsigned long *)&vcpu->arch.regs_avail))
559 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
560 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
561 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
562 PFERR_USER_MASK | PFERR_WRITE_MASK);
565 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
571 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
573 unsigned long old_cr0 = kvm_read_cr0(vcpu);
574 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
575 X86_CR0_CD | X86_CR0_NW;
580 if (cr0 & 0xffffffff00000000UL)
584 cr0 &= ~CR0_RESERVED_BITS;
586 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
589 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
592 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
594 if ((vcpu->arch.efer & EFER_LME)) {
599 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
604 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
609 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
612 kvm_x86_ops->set_cr0(vcpu, cr0);
614 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
615 kvm_clear_async_pf_completion_queue(vcpu);
616 kvm_async_pf_hash_reset(vcpu);
619 if ((cr0 ^ old_cr0) & update_bits)
620 kvm_mmu_reset_context(vcpu);
623 EXPORT_SYMBOL_GPL(kvm_set_cr0);
625 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
627 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
629 EXPORT_SYMBOL_GPL(kvm_lmsw);
631 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
633 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
634 !vcpu->guest_xcr0_loaded) {
635 /* kvm_set_xcr() also depends on this */
636 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
637 vcpu->guest_xcr0_loaded = 1;
641 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
643 if (vcpu->guest_xcr0_loaded) {
644 if (vcpu->arch.xcr0 != host_xcr0)
645 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
646 vcpu->guest_xcr0_loaded = 0;
650 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
653 u64 old_xcr0 = vcpu->arch.xcr0;
656 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
657 if (index != XCR_XFEATURE_ENABLED_MASK)
659 if (!(xcr0 & XSTATE_FP))
661 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
665 * Do not allow the guest to set bits that we do not support
666 * saving. However, xcr0 bit 0 is always set, even if the
667 * emulated CPU does not support XSAVE (see fx_init).
669 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
670 if (xcr0 & ~valid_bits)
673 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
676 if (xcr0 & XSTATE_AVX512) {
677 if (!(xcr0 & XSTATE_YMM))
679 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
682 kvm_put_guest_xcr0(vcpu);
683 vcpu->arch.xcr0 = xcr0;
685 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
686 kvm_update_cpuid(vcpu);
690 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
692 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
693 __kvm_set_xcr(vcpu, index, xcr)) {
694 kvm_inject_gp(vcpu, 0);
699 EXPORT_SYMBOL_GPL(kvm_set_xcr);
701 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
703 unsigned long old_cr4 = kvm_read_cr4(vcpu);
704 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
705 X86_CR4_SMEP | X86_CR4_SMAP;
707 if (cr4 & CR4_RESERVED_BITS)
710 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
713 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
716 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
719 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
722 if (is_long_mode(vcpu)) {
723 if (!(cr4 & X86_CR4_PAE))
725 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
726 && ((cr4 ^ old_cr4) & pdptr_bits)
727 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
731 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
732 if (!guest_cpuid_has_pcid(vcpu))
735 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
736 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
740 if (kvm_x86_ops->set_cr4(vcpu, cr4))
743 if (((cr4 ^ old_cr4) & pdptr_bits) ||
744 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
745 kvm_mmu_reset_context(vcpu);
747 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
748 kvm_update_cpuid(vcpu);
752 EXPORT_SYMBOL_GPL(kvm_set_cr4);
754 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
757 cr3 &= ~CR3_PCID_INVD;
760 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
761 kvm_mmu_sync_roots(vcpu);
762 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
766 if (is_long_mode(vcpu)) {
767 if (cr3 & CR3_L_MODE_RESERVED_BITS)
769 } else if (is_pae(vcpu) && is_paging(vcpu) &&
770 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
773 vcpu->arch.cr3 = cr3;
774 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
775 kvm_mmu_new_cr3(vcpu);
778 EXPORT_SYMBOL_GPL(kvm_set_cr3);
780 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
782 if (cr8 & CR8_RESERVED_BITS)
784 if (irqchip_in_kernel(vcpu->kvm))
785 kvm_lapic_set_tpr(vcpu, cr8);
787 vcpu->arch.cr8 = cr8;
790 EXPORT_SYMBOL_GPL(kvm_set_cr8);
792 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
794 if (irqchip_in_kernel(vcpu->kvm))
795 return kvm_lapic_get_cr8(vcpu);
797 return vcpu->arch.cr8;
799 EXPORT_SYMBOL_GPL(kvm_get_cr8);
801 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
806 for (i = 0; i < KVM_NR_DB_REGS; i++)
807 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
808 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
812 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
814 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
815 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
818 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
822 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
823 dr7 = vcpu->arch.guest_debug_dr7;
825 dr7 = vcpu->arch.dr7;
826 kvm_x86_ops->set_dr7(vcpu, dr7);
827 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
828 if (dr7 & DR7_BP_EN_MASK)
829 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
832 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
834 u64 fixed = DR6_FIXED_1;
836 if (!guest_cpuid_has_rtm(vcpu))
841 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
845 vcpu->arch.db[dr] = val;
846 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
847 vcpu->arch.eff_db[dr] = val;
852 if (val & 0xffffffff00000000ULL)
854 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
855 kvm_update_dr6(vcpu);
860 if (val & 0xffffffff00000000ULL)
862 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
863 kvm_update_dr7(vcpu);
870 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
872 if (__kvm_set_dr(vcpu, dr, val)) {
873 kvm_inject_gp(vcpu, 0);
878 EXPORT_SYMBOL_GPL(kvm_set_dr);
880 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
884 *val = vcpu->arch.db[dr];
889 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
890 *val = vcpu->arch.dr6;
892 *val = kvm_x86_ops->get_dr6(vcpu);
897 *val = vcpu->arch.dr7;
902 EXPORT_SYMBOL_GPL(kvm_get_dr);
904 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
906 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
910 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
913 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
914 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
917 EXPORT_SYMBOL_GPL(kvm_rdpmc);
920 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
921 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
923 * This list is modified at module load time to reflect the
924 * capabilities of the host cpu. This capabilities test skips MSRs that are
925 * kvm-specific. Those are put in the beginning of the list.
928 #define KVM_SAVE_MSRS_BEGIN 12
929 static u32 msrs_to_save[] = {
930 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
931 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
932 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
933 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
934 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
936 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
939 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
941 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
942 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
945 static unsigned num_msrs_to_save;
947 static const u32 emulated_msrs[] = {
949 MSR_IA32_TSCDEADLINE,
950 MSR_IA32_MISC_ENABLE,
955 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
957 if (efer & efer_reserved_bits)
960 if (efer & EFER_FFXSR) {
961 struct kvm_cpuid_entry2 *feat;
963 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
964 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
968 if (efer & EFER_SVME) {
969 struct kvm_cpuid_entry2 *feat;
971 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
972 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
978 EXPORT_SYMBOL_GPL(kvm_valid_efer);
980 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
982 u64 old_efer = vcpu->arch.efer;
984 if (!kvm_valid_efer(vcpu, efer))
988 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
992 efer |= vcpu->arch.efer & EFER_LMA;
994 kvm_x86_ops->set_efer(vcpu, efer);
996 /* Update reserved bits */
997 if ((efer ^ old_efer) & EFER_NX)
998 kvm_mmu_reset_context(vcpu);
1003 void kvm_enable_efer_bits(u64 mask)
1005 efer_reserved_bits &= ~mask;
1007 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1010 * Writes msr value into into the appropriate "register".
1011 * Returns 0 on success, non-0 otherwise.
1012 * Assumes vcpu_load() was already called.
1014 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1016 switch (msr->index) {
1019 case MSR_KERNEL_GS_BASE:
1022 if (is_noncanonical_address(msr->data))
1025 case MSR_IA32_SYSENTER_EIP:
1026 case MSR_IA32_SYSENTER_ESP:
1028 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1029 * non-canonical address is written on Intel but not on
1030 * AMD (which ignores the top 32-bits, because it does
1031 * not implement 64-bit SYSENTER).
1033 * 64-bit code should hence be able to write a non-canonical
1034 * value on AMD. Making the address canonical ensures that
1035 * vmentry does not fail on Intel after writing a non-canonical
1036 * value, and that something deterministic happens if the guest
1037 * invokes 64-bit SYSENTER.
1039 msr->data = get_canonical(msr->data);
1041 return kvm_x86_ops->set_msr(vcpu, msr);
1043 EXPORT_SYMBOL_GPL(kvm_set_msr);
1046 * Adapt set_msr() to msr_io()'s calling convention
1048 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1050 struct msr_data msr;
1054 msr.host_initiated = true;
1055 return kvm_set_msr(vcpu, &msr);
1058 #ifdef CONFIG_X86_64
1059 struct pvclock_gtod_data {
1062 struct { /* extract of a clocksource struct */
1074 static struct pvclock_gtod_data pvclock_gtod_data;
1076 static void update_pvclock_gtod(struct timekeeper *tk)
1078 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1081 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1083 write_seqcount_begin(&vdata->seq);
1085 /* copy pvclock gtod data */
1086 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1087 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1088 vdata->clock.mask = tk->tkr_mono.mask;
1089 vdata->clock.mult = tk->tkr_mono.mult;
1090 vdata->clock.shift = tk->tkr_mono.shift;
1092 vdata->boot_ns = boot_ns;
1093 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1095 write_seqcount_end(&vdata->seq);
1099 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1102 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1103 * vcpu_enter_guest. This function is only called from
1104 * the physical CPU that is running vcpu.
1106 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1109 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1113 struct pvclock_wall_clock wc;
1114 struct timespec boot;
1119 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1124 ++version; /* first time write, random junk */
1128 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1131 * The guest calculates current wall clock time by adding
1132 * system time (updated by kvm_guest_time_update below) to the
1133 * wall clock specified here. guest system time equals host
1134 * system time for us, thus we must fill in host boot time here.
1138 if (kvm->arch.kvmclock_offset) {
1139 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1140 boot = timespec_sub(boot, ts);
1142 wc.sec = boot.tv_sec;
1143 wc.nsec = boot.tv_nsec;
1144 wc.version = version;
1146 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1149 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1152 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1154 uint32_t quotient, remainder;
1156 /* Don't try to replace with do_div(), this one calculates
1157 * "(dividend << 32) / divisor" */
1159 : "=a" (quotient), "=d" (remainder)
1160 : "0" (0), "1" (dividend), "r" (divisor) );
1164 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1165 s8 *pshift, u32 *pmultiplier)
1172 tps64 = base_khz * 1000LL;
1173 scaled64 = scaled_khz * 1000LL;
1174 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1179 tps32 = (uint32_t)tps64;
1180 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1181 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1189 *pmultiplier = div_frac(scaled64, tps32);
1191 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1192 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1195 static inline u64 get_kernel_ns(void)
1197 return ktime_get_boot_ns();
1200 #ifdef CONFIG_X86_64
1201 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1204 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1205 static unsigned long max_tsc_khz;
1207 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1209 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1210 vcpu->arch.virtual_tsc_shift);
1213 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1215 u64 v = (u64)khz * (1000000 + ppm);
1220 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1222 u32 thresh_lo, thresh_hi;
1223 int use_scaling = 0;
1225 /* tsc_khz can be zero if TSC calibration fails */
1226 if (this_tsc_khz == 0)
1229 /* Compute a scale to convert nanoseconds in TSC cycles */
1230 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1231 &vcpu->arch.virtual_tsc_shift,
1232 &vcpu->arch.virtual_tsc_mult);
1233 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1236 * Compute the variation in TSC rate which is acceptable
1237 * within the range of tolerance and decide if the
1238 * rate being applied is within that bounds of the hardware
1239 * rate. If so, no scaling or compensation need be done.
1241 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1242 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1243 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1244 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1247 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1250 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1252 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1253 vcpu->arch.virtual_tsc_mult,
1254 vcpu->arch.virtual_tsc_shift);
1255 tsc += vcpu->arch.this_tsc_write;
1259 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1261 #ifdef CONFIG_X86_64
1263 struct kvm_arch *ka = &vcpu->kvm->arch;
1264 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1266 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1267 atomic_read(&vcpu->kvm->online_vcpus));
1270 * Once the masterclock is enabled, always perform request in
1271 * order to update it.
1273 * In order to enable masterclock, the host clocksource must be TSC
1274 * and the vcpus need to have matched TSCs. When that happens,
1275 * perform request to enable masterclock.
1277 if (ka->use_master_clock ||
1278 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1279 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1281 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1282 atomic_read(&vcpu->kvm->online_vcpus),
1283 ka->use_master_clock, gtod->clock.vclock_mode);
1287 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1289 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1290 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1293 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1295 struct kvm *kvm = vcpu->kvm;
1296 u64 offset, ns, elapsed;
1297 unsigned long flags;
1300 bool already_matched;
1301 u64 data = msr->data;
1303 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1304 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1305 ns = get_kernel_ns();
1306 elapsed = ns - kvm->arch.last_tsc_nsec;
1308 if (vcpu->arch.virtual_tsc_khz) {
1311 /* n.b - signed multiplication and division required */
1312 usdiff = data - kvm->arch.last_tsc_write;
1313 #ifdef CONFIG_X86_64
1314 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1316 /* do_div() only does unsigned */
1317 asm("1: idivl %[divisor]\n"
1318 "2: xor %%edx, %%edx\n"
1319 " movl $0, %[faulted]\n"
1321 ".section .fixup,\"ax\"\n"
1322 "4: movl $1, %[faulted]\n"
1326 _ASM_EXTABLE(1b, 4b)
1328 : "=A"(usdiff), [faulted] "=r" (faulted)
1329 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1332 do_div(elapsed, 1000);
1337 /* idivl overflow => difference is larger than USEC_PER_SEC */
1339 usdiff = USEC_PER_SEC;
1341 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1344 * Special case: TSC write with a small delta (1 second) of virtual
1345 * cycle time against real time is interpreted as an attempt to
1346 * synchronize the CPU.
1348 * For a reliable TSC, we can match TSC offsets, and for an unstable
1349 * TSC, we add elapsed time in this computation. We could let the
1350 * compensation code attempt to catch up if we fall behind, but
1351 * it's better to try to match offsets from the beginning.
1353 if (usdiff < USEC_PER_SEC &&
1354 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1355 if (!check_tsc_unstable()) {
1356 offset = kvm->arch.cur_tsc_offset;
1357 pr_debug("kvm: matched tsc offset for %llu\n", data);
1359 u64 delta = nsec_to_cycles(vcpu, elapsed);
1361 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1362 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1365 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1368 * We split periods of matched TSC writes into generations.
1369 * For each generation, we track the original measured
1370 * nanosecond time, offset, and write, so if TSCs are in
1371 * sync, we can match exact offset, and if not, we can match
1372 * exact software computation in compute_guest_tsc()
1374 * These values are tracked in kvm->arch.cur_xxx variables.
1376 kvm->arch.cur_tsc_generation++;
1377 kvm->arch.cur_tsc_nsec = ns;
1378 kvm->arch.cur_tsc_write = data;
1379 kvm->arch.cur_tsc_offset = offset;
1381 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1382 kvm->arch.cur_tsc_generation, data);
1386 * We also track th most recent recorded KHZ, write and time to
1387 * allow the matching interval to be extended at each write.
1389 kvm->arch.last_tsc_nsec = ns;
1390 kvm->arch.last_tsc_write = data;
1391 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1393 vcpu->arch.last_guest_tsc = data;
1395 /* Keep track of which generation this VCPU has synchronized to */
1396 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1397 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1398 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1400 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1401 update_ia32_tsc_adjust_msr(vcpu, offset);
1402 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1403 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1405 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1407 kvm->arch.nr_vcpus_matched_tsc = 0;
1408 } else if (!already_matched) {
1409 kvm->arch.nr_vcpus_matched_tsc++;
1412 kvm_track_tsc_matching(vcpu);
1413 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1416 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1418 #ifdef CONFIG_X86_64
1420 static cycle_t read_tsc(void)
1426 * Empirically, a fence (of type that depends on the CPU)
1427 * before rdtsc is enough to ensure that rdtsc is ordered
1428 * with respect to loads. The various CPU manuals are unclear
1429 * as to whether rdtsc can be reordered with later loads,
1430 * but no one has ever seen it happen.
1433 ret = (cycle_t)vget_cycles();
1435 last = pvclock_gtod_data.clock.cycle_last;
1437 if (likely(ret >= last))
1441 * GCC likes to generate cmov here, but this branch is extremely
1442 * predictable (it's just a funciton of time and the likely is
1443 * very likely) and there's a data dependence, so force GCC
1444 * to generate a branch instead. I don't barrier() because
1445 * we don't actually need a barrier, and if this function
1446 * ever gets inlined it will generate worse code.
1452 static inline u64 vgettsc(cycle_t *cycle_now)
1455 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1457 *cycle_now = read_tsc();
1459 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1460 return v * gtod->clock.mult;
1463 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1465 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1471 seq = read_seqcount_begin(>od->seq);
1472 mode = gtod->clock.vclock_mode;
1473 ns = gtod->nsec_base;
1474 ns += vgettsc(cycle_now);
1475 ns >>= gtod->clock.shift;
1476 ns += gtod->boot_ns;
1477 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1483 /* returns true if host is using tsc clocksource */
1484 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1486 /* checked again under seqlock below */
1487 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1490 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1496 * Assuming a stable TSC across physical CPUS, and a stable TSC
1497 * across virtual CPUs, the following condition is possible.
1498 * Each numbered line represents an event visible to both
1499 * CPUs at the next numbered event.
1501 * "timespecX" represents host monotonic time. "tscX" represents
1504 * VCPU0 on CPU0 | VCPU1 on CPU1
1506 * 1. read timespec0,tsc0
1507 * 2. | timespec1 = timespec0 + N
1509 * 3. transition to guest | transition to guest
1510 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1511 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1512 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1514 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1517 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1519 * - 0 < N - M => M < N
1521 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1522 * always the case (the difference between two distinct xtime instances
1523 * might be smaller then the difference between corresponding TSC reads,
1524 * when updating guest vcpus pvclock areas).
1526 * To avoid that problem, do not allow visibility of distinct
1527 * system_timestamp/tsc_timestamp values simultaneously: use a master
1528 * copy of host monotonic time values. Update that master copy
1531 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1535 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1537 #ifdef CONFIG_X86_64
1538 struct kvm_arch *ka = &kvm->arch;
1540 bool host_tsc_clocksource, vcpus_matched;
1542 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1543 atomic_read(&kvm->online_vcpus));
1546 * If the host uses TSC clock, then passthrough TSC as stable
1549 host_tsc_clocksource = kvm_get_time_and_clockread(
1550 &ka->master_kernel_ns,
1551 &ka->master_cycle_now);
1553 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1554 && !backwards_tsc_observed
1555 && !ka->boot_vcpu_runs_old_kvmclock;
1557 if (ka->use_master_clock)
1558 atomic_set(&kvm_guest_has_master_clock, 1);
1560 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1561 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1566 static void kvm_gen_update_masterclock(struct kvm *kvm)
1568 #ifdef CONFIG_X86_64
1570 struct kvm_vcpu *vcpu;
1571 struct kvm_arch *ka = &kvm->arch;
1573 spin_lock(&ka->pvclock_gtod_sync_lock);
1574 kvm_make_mclock_inprogress_request(kvm);
1575 /* no guest entries from this point */
1576 pvclock_update_vm_gtod_copy(kvm);
1578 kvm_for_each_vcpu(i, vcpu, kvm)
1579 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1581 /* guest entries allowed */
1582 kvm_for_each_vcpu(i, vcpu, kvm)
1583 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1585 spin_unlock(&ka->pvclock_gtod_sync_lock);
1589 static int kvm_guest_time_update(struct kvm_vcpu *v)
1591 unsigned long flags, this_tsc_khz;
1592 struct kvm_vcpu_arch *vcpu = &v->arch;
1593 struct kvm_arch *ka = &v->kvm->arch;
1595 u64 tsc_timestamp, host_tsc;
1596 struct pvclock_vcpu_time_info guest_hv_clock;
1598 bool use_master_clock;
1604 * If the host uses TSC clock, then passthrough TSC as stable
1607 spin_lock(&ka->pvclock_gtod_sync_lock);
1608 use_master_clock = ka->use_master_clock;
1609 if (use_master_clock) {
1610 host_tsc = ka->master_cycle_now;
1611 kernel_ns = ka->master_kernel_ns;
1613 spin_unlock(&ka->pvclock_gtod_sync_lock);
1615 /* Keep irq disabled to prevent changes to the clock */
1616 local_irq_save(flags);
1617 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1618 if (unlikely(this_tsc_khz == 0)) {
1619 local_irq_restore(flags);
1620 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1623 if (!use_master_clock) {
1624 host_tsc = native_read_tsc();
1625 kernel_ns = get_kernel_ns();
1628 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1631 * We may have to catch up the TSC to match elapsed wall clock
1632 * time for two reasons, even if kvmclock is used.
1633 * 1) CPU could have been running below the maximum TSC rate
1634 * 2) Broken TSC compensation resets the base at each VCPU
1635 * entry to avoid unknown leaps of TSC even when running
1636 * again on the same CPU. This may cause apparent elapsed
1637 * time to disappear, and the guest to stand still or run
1640 if (vcpu->tsc_catchup) {
1641 u64 tsc = compute_guest_tsc(v, kernel_ns);
1642 if (tsc > tsc_timestamp) {
1643 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1644 tsc_timestamp = tsc;
1648 local_irq_restore(flags);
1650 if (!vcpu->pv_time_enabled)
1653 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1654 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1655 &vcpu->hv_clock.tsc_shift,
1656 &vcpu->hv_clock.tsc_to_system_mul);
1657 vcpu->hw_tsc_khz = this_tsc_khz;
1660 /* With all the info we got, fill in the values */
1661 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1662 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1663 vcpu->last_guest_tsc = tsc_timestamp;
1665 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1666 &guest_hv_clock, sizeof(guest_hv_clock))))
1669 /* This VCPU is paused, but it's legal for a guest to read another
1670 * VCPU's kvmclock, so we really have to follow the specification where
1671 * it says that version is odd if data is being modified, and even after
1674 * Version field updates must be kept separate. This is because
1675 * kvm_write_guest_cached might use a "rep movs" instruction, and
1676 * writes within a string instruction are weakly ordered. So there
1677 * are three writes overall.
1679 * As a small optimization, only write the version field in the first
1680 * and third write. The vcpu->pv_time cache is still valid, because the
1681 * version field is the first in the struct.
1683 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1685 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1686 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1688 sizeof(vcpu->hv_clock.version));
1692 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1693 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1695 if (vcpu->pvclock_set_guest_stopped_request) {
1696 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1697 vcpu->pvclock_set_guest_stopped_request = false;
1700 /* If the host uses TSC clocksource, then it is stable */
1701 if (use_master_clock)
1702 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1704 vcpu->hv_clock.flags = pvclock_flags;
1706 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1708 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1710 sizeof(vcpu->hv_clock));
1714 vcpu->hv_clock.version++;
1715 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1717 sizeof(vcpu->hv_clock.version));
1722 * kvmclock updates which are isolated to a given vcpu, such as
1723 * vcpu->cpu migration, should not allow system_timestamp from
1724 * the rest of the vcpus to remain static. Otherwise ntp frequency
1725 * correction applies to one vcpu's system_timestamp but not
1728 * So in those cases, request a kvmclock update for all vcpus.
1729 * We need to rate-limit these requests though, as they can
1730 * considerably slow guests that have a large number of vcpus.
1731 * The time for a remote vcpu to update its kvmclock is bound
1732 * by the delay we use to rate-limit the updates.
1735 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1737 static void kvmclock_update_fn(struct work_struct *work)
1740 struct delayed_work *dwork = to_delayed_work(work);
1741 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1742 kvmclock_update_work);
1743 struct kvm *kvm = container_of(ka, struct kvm, arch);
1744 struct kvm_vcpu *vcpu;
1746 kvm_for_each_vcpu(i, vcpu, kvm) {
1747 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1748 kvm_vcpu_kick(vcpu);
1752 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1754 struct kvm *kvm = v->kvm;
1756 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1757 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1758 KVMCLOCK_UPDATE_DELAY);
1761 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1763 static void kvmclock_sync_fn(struct work_struct *work)
1765 struct delayed_work *dwork = to_delayed_work(work);
1766 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1767 kvmclock_sync_work);
1768 struct kvm *kvm = container_of(ka, struct kvm, arch);
1770 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1771 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1772 KVMCLOCK_SYNC_PERIOD);
1775 static bool msr_mtrr_valid(unsigned msr)
1778 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1779 case MSR_MTRRfix64K_00000:
1780 case MSR_MTRRfix16K_80000:
1781 case MSR_MTRRfix16K_A0000:
1782 case MSR_MTRRfix4K_C0000:
1783 case MSR_MTRRfix4K_C8000:
1784 case MSR_MTRRfix4K_D0000:
1785 case MSR_MTRRfix4K_D8000:
1786 case MSR_MTRRfix4K_E0000:
1787 case MSR_MTRRfix4K_E8000:
1788 case MSR_MTRRfix4K_F0000:
1789 case MSR_MTRRfix4K_F8000:
1790 case MSR_MTRRdefType:
1791 case MSR_IA32_CR_PAT:
1799 static bool valid_pat_type(unsigned t)
1801 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1804 static bool valid_mtrr_type(unsigned t)
1806 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1809 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1814 if (!msr_mtrr_valid(msr))
1817 if (msr == MSR_IA32_CR_PAT) {
1818 for (i = 0; i < 8; i++)
1819 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1822 } else if (msr == MSR_MTRRdefType) {
1825 return valid_mtrr_type(data & 0xff);
1826 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1827 for (i = 0; i < 8 ; i++)
1828 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1833 /* variable MTRRs */
1834 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1836 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1837 if ((msr & 1) == 0) {
1839 if (!valid_mtrr_type(data & 0xff))
1846 kvm_inject_gp(vcpu, 0);
1852 EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
1854 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1856 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1858 if (!kvm_mtrr_valid(vcpu, msr, data))
1861 if (msr == MSR_MTRRdefType) {
1862 vcpu->arch.mtrr_state.def_type = data;
1863 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1864 } else if (msr == MSR_MTRRfix64K_00000)
1866 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1867 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1868 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1869 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1870 else if (msr == MSR_IA32_CR_PAT)
1871 vcpu->arch.pat = data;
1872 else { /* Variable MTRRs */
1873 int idx, is_mtrr_mask;
1876 idx = (msr - 0x200) / 2;
1877 is_mtrr_mask = msr - 0x200 - 2 * idx;
1880 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1883 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1887 kvm_mmu_reset_context(vcpu);
1891 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1893 u64 mcg_cap = vcpu->arch.mcg_cap;
1894 unsigned bank_num = mcg_cap & 0xff;
1897 case MSR_IA32_MCG_STATUS:
1898 vcpu->arch.mcg_status = data;
1900 case MSR_IA32_MCG_CTL:
1901 if (!(mcg_cap & MCG_CTL_P))
1903 if (data != 0 && data != ~(u64)0)
1905 vcpu->arch.mcg_ctl = data;
1908 if (msr >= MSR_IA32_MC0_CTL &&
1909 msr < MSR_IA32_MCx_CTL(bank_num)) {
1910 u32 offset = msr - MSR_IA32_MC0_CTL;
1911 /* only 0 or all 1s can be written to IA32_MCi_CTL
1912 * some Linux kernels though clear bit 10 in bank 4 to
1913 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1914 * this to avoid an uncatched #GP in the guest
1916 if ((offset & 0x3) == 0 &&
1917 data != 0 && (data | (1 << 10)) != ~(u64)0)
1919 vcpu->arch.mce_banks[offset] = data;
1927 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1929 struct kvm *kvm = vcpu->kvm;
1930 int lm = is_long_mode(vcpu);
1931 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1932 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1933 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1934 : kvm->arch.xen_hvm_config.blob_size_32;
1935 u32 page_num = data & ~PAGE_MASK;
1936 u64 page_addr = data & PAGE_MASK;
1941 if (page_num >= blob_size)
1944 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1949 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1958 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1960 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1963 static bool kvm_hv_msr_partition_wide(u32 msr)
1967 case HV_X64_MSR_GUEST_OS_ID:
1968 case HV_X64_MSR_HYPERCALL:
1969 case HV_X64_MSR_REFERENCE_TSC:
1970 case HV_X64_MSR_TIME_REF_COUNT:
1978 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1980 struct kvm *kvm = vcpu->kvm;
1983 case HV_X64_MSR_GUEST_OS_ID:
1984 kvm->arch.hv_guest_os_id = data;
1985 /* setting guest os id to zero disables hypercall page */
1986 if (!kvm->arch.hv_guest_os_id)
1987 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1989 case HV_X64_MSR_HYPERCALL: {
1994 /* if guest os id is not set hypercall should remain disabled */
1995 if (!kvm->arch.hv_guest_os_id)
1997 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1998 kvm->arch.hv_hypercall = data;
2001 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2002 addr = gfn_to_hva(kvm, gfn);
2003 if (kvm_is_error_hva(addr))
2005 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2006 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
2007 if (__copy_to_user((void __user *)addr, instructions, 4))
2009 kvm->arch.hv_hypercall = data;
2010 mark_page_dirty(kvm, gfn);
2013 case HV_X64_MSR_REFERENCE_TSC: {
2015 HV_REFERENCE_TSC_PAGE tsc_ref;
2016 memset(&tsc_ref, 0, sizeof(tsc_ref));
2017 kvm->arch.hv_tsc_page = data;
2018 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2020 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
2021 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
2022 &tsc_ref, sizeof(tsc_ref)))
2024 mark_page_dirty(kvm, gfn);
2028 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2029 "data 0x%llx\n", msr, data);
2035 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2038 case HV_X64_MSR_APIC_ASSIST_PAGE: {
2042 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2043 vcpu->arch.hv_vapic = data;
2044 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2048 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2049 addr = gfn_to_hva(vcpu->kvm, gfn);
2050 if (kvm_is_error_hva(addr))
2052 if (__clear_user((void __user *)addr, PAGE_SIZE))
2054 vcpu->arch.hv_vapic = data;
2055 mark_page_dirty(vcpu->kvm, gfn);
2056 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2060 case HV_X64_MSR_EOI:
2061 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2062 case HV_X64_MSR_ICR:
2063 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2064 case HV_X64_MSR_TPR:
2065 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2067 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2068 "data 0x%llx\n", msr, data);
2075 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2077 gpa_t gpa = data & ~0x3f;
2079 /* Bits 2:5 are reserved, Should be zero */
2083 vcpu->arch.apf.msr_val = data;
2085 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2086 kvm_clear_async_pf_completion_queue(vcpu);
2087 kvm_async_pf_hash_reset(vcpu);
2091 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2095 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2096 kvm_async_pf_wakeup_all(vcpu);
2100 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2102 vcpu->arch.pv_time_enabled = false;
2105 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2109 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2112 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2113 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2114 vcpu->arch.st.accum_steal = delta;
2117 static void record_steal_time(struct kvm_vcpu *vcpu)
2119 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2122 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2123 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2126 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2127 vcpu->arch.st.steal.version += 2;
2128 vcpu->arch.st.accum_steal = 0;
2130 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2131 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2134 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2137 u32 msr = msr_info->index;
2138 u64 data = msr_info->data;
2141 case MSR_AMD64_NB_CFG:
2142 case MSR_IA32_UCODE_REV:
2143 case MSR_IA32_UCODE_WRITE:
2144 case MSR_VM_HSAVE_PA:
2145 case MSR_AMD64_PATCH_LOADER:
2146 case MSR_AMD64_BU_CFG2:
2150 return set_efer(vcpu, data);
2152 data &= ~(u64)0x40; /* ignore flush filter disable */
2153 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2154 data &= ~(u64)0x8; /* ignore TLB cache disable */
2155 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2157 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2162 case MSR_FAM10H_MMIO_CONF_BASE:
2164 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2169 case MSR_IA32_DEBUGCTLMSR:
2171 /* We support the non-activated case already */
2173 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2174 /* Values other than LBR and BTF are vendor-specific,
2175 thus reserved and should throw a #GP */
2178 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2181 case 0x200 ... 0x2ff:
2182 return set_msr_mtrr(vcpu, msr, data);
2183 case MSR_IA32_APICBASE:
2184 return kvm_set_apic_base(vcpu, msr_info);
2185 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2186 return kvm_x2apic_msr_write(vcpu, msr, data);
2187 case MSR_IA32_TSCDEADLINE:
2188 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2190 case MSR_IA32_TSC_ADJUST:
2191 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2192 if (!msr_info->host_initiated) {
2193 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2194 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2196 vcpu->arch.ia32_tsc_adjust_msr = data;
2199 case MSR_IA32_MISC_ENABLE:
2200 vcpu->arch.ia32_misc_enable_msr = data;
2202 case MSR_KVM_WALL_CLOCK_NEW:
2203 case MSR_KVM_WALL_CLOCK:
2204 vcpu->kvm->arch.wall_clock = data;
2205 kvm_write_wall_clock(vcpu->kvm, data);
2207 case MSR_KVM_SYSTEM_TIME_NEW:
2208 case MSR_KVM_SYSTEM_TIME: {
2210 struct kvm_arch *ka = &vcpu->kvm->arch;
2212 kvmclock_reset(vcpu);
2214 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2215 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2217 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2218 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2221 ka->boot_vcpu_runs_old_kvmclock = tmp;
2224 vcpu->arch.time = data;
2225 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2227 /* we verify if the enable bit is set... */
2231 gpa_offset = data & ~(PAGE_MASK | 1);
2233 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2234 &vcpu->arch.pv_time, data & ~1ULL,
2235 sizeof(struct pvclock_vcpu_time_info)))
2236 vcpu->arch.pv_time_enabled = false;
2238 vcpu->arch.pv_time_enabled = true;
2242 case MSR_KVM_ASYNC_PF_EN:
2243 if (kvm_pv_enable_async_pf(vcpu, data))
2246 case MSR_KVM_STEAL_TIME:
2248 if (unlikely(!sched_info_on()))
2251 if (data & KVM_STEAL_RESERVED_MASK)
2254 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2255 data & KVM_STEAL_VALID_BITS,
2256 sizeof(struct kvm_steal_time)))
2259 vcpu->arch.st.msr_val = data;
2261 if (!(data & KVM_MSR_ENABLED))
2264 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2267 accumulate_steal_time(vcpu);
2270 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2273 case MSR_KVM_PV_EOI_EN:
2274 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2278 case MSR_IA32_MCG_CTL:
2279 case MSR_IA32_MCG_STATUS:
2280 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2281 return set_msr_mce(vcpu, msr, data);
2283 /* Performance counters are not protected by a CPUID bit,
2284 * so we should check all of them in the generic path for the sake of
2285 * cross vendor migration.
2286 * Writing a zero into the event select MSRs disables them,
2287 * which we perfectly emulate ;-). Any other value should be at least
2288 * reported, some guests depend on them.
2290 case MSR_K7_EVNTSEL0:
2291 case MSR_K7_EVNTSEL1:
2292 case MSR_K7_EVNTSEL2:
2293 case MSR_K7_EVNTSEL3:
2295 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2296 "0x%x data 0x%llx\n", msr, data);
2298 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2299 * so we ignore writes to make it happy.
2301 case MSR_K7_PERFCTR0:
2302 case MSR_K7_PERFCTR1:
2303 case MSR_K7_PERFCTR2:
2304 case MSR_K7_PERFCTR3:
2305 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2306 "0x%x data 0x%llx\n", msr, data);
2308 case MSR_P6_PERFCTR0:
2309 case MSR_P6_PERFCTR1:
2311 case MSR_P6_EVNTSEL0:
2312 case MSR_P6_EVNTSEL1:
2313 if (kvm_pmu_msr(vcpu, msr))
2314 return kvm_pmu_set_msr(vcpu, msr_info);
2316 if (pr || data != 0)
2317 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2318 "0x%x data 0x%llx\n", msr, data);
2320 case MSR_K7_CLK_CTL:
2322 * Ignore all writes to this no longer documented MSR.
2323 * Writes are only relevant for old K7 processors,
2324 * all pre-dating SVM, but a recommended workaround from
2325 * AMD for these chips. It is possible to specify the
2326 * affected processor models on the command line, hence
2327 * the need to ignore the workaround.
2330 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2331 if (kvm_hv_msr_partition_wide(msr)) {
2333 mutex_lock(&vcpu->kvm->lock);
2334 r = set_msr_hyperv_pw(vcpu, msr, data);
2335 mutex_unlock(&vcpu->kvm->lock);
2338 return set_msr_hyperv(vcpu, msr, data);
2340 case MSR_IA32_BBL_CR_CTL3:
2341 /* Drop writes to this legacy MSR -- see rdmsr
2342 * counterpart for further detail.
2344 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2346 case MSR_AMD64_OSVW_ID_LENGTH:
2347 if (!guest_cpuid_has_osvw(vcpu))
2349 vcpu->arch.osvw.length = data;
2351 case MSR_AMD64_OSVW_STATUS:
2352 if (!guest_cpuid_has_osvw(vcpu))
2354 vcpu->arch.osvw.status = data;
2357 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2358 return xen_hvm_config(vcpu, data);
2359 if (kvm_pmu_msr(vcpu, msr))
2360 return kvm_pmu_set_msr(vcpu, msr_info);
2362 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2366 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2373 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2377 * Reads an msr value (of 'msr_index') into 'pdata'.
2378 * Returns 0 on success, non-0 otherwise.
2379 * Assumes vcpu_load() was already called.
2381 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2383 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2385 EXPORT_SYMBOL_GPL(kvm_get_msr);
2387 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2389 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2391 if (!msr_mtrr_valid(msr))
2394 if (msr == MSR_MTRRdefType)
2395 *pdata = vcpu->arch.mtrr_state.def_type +
2396 (vcpu->arch.mtrr_state.enabled << 10);
2397 else if (msr == MSR_MTRRfix64K_00000)
2399 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2400 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2401 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2402 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2403 else if (msr == MSR_IA32_CR_PAT)
2404 *pdata = vcpu->arch.pat;
2405 else { /* Variable MTRRs */
2406 int idx, is_mtrr_mask;
2409 idx = (msr - 0x200) / 2;
2410 is_mtrr_mask = msr - 0x200 - 2 * idx;
2413 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2416 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2423 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2426 u64 mcg_cap = vcpu->arch.mcg_cap;
2427 unsigned bank_num = mcg_cap & 0xff;
2430 case MSR_IA32_P5_MC_ADDR:
2431 case MSR_IA32_P5_MC_TYPE:
2434 case MSR_IA32_MCG_CAP:
2435 data = vcpu->arch.mcg_cap;
2437 case MSR_IA32_MCG_CTL:
2438 if (!(mcg_cap & MCG_CTL_P))
2440 data = vcpu->arch.mcg_ctl;
2442 case MSR_IA32_MCG_STATUS:
2443 data = vcpu->arch.mcg_status;
2446 if (msr >= MSR_IA32_MC0_CTL &&
2447 msr < MSR_IA32_MCx_CTL(bank_num)) {
2448 u32 offset = msr - MSR_IA32_MC0_CTL;
2449 data = vcpu->arch.mce_banks[offset];
2458 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2461 struct kvm *kvm = vcpu->kvm;
2464 case HV_X64_MSR_GUEST_OS_ID:
2465 data = kvm->arch.hv_guest_os_id;
2467 case HV_X64_MSR_HYPERCALL:
2468 data = kvm->arch.hv_hypercall;
2470 case HV_X64_MSR_TIME_REF_COUNT: {
2472 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2475 case HV_X64_MSR_REFERENCE_TSC:
2476 data = kvm->arch.hv_tsc_page;
2479 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2487 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2492 case HV_X64_MSR_VP_INDEX: {
2495 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2503 case HV_X64_MSR_EOI:
2504 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2505 case HV_X64_MSR_ICR:
2506 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2507 case HV_X64_MSR_TPR:
2508 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2509 case HV_X64_MSR_APIC_ASSIST_PAGE:
2510 data = vcpu->arch.hv_vapic;
2513 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2520 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2525 case MSR_IA32_PLATFORM_ID:
2526 case MSR_IA32_EBL_CR_POWERON:
2527 case MSR_IA32_DEBUGCTLMSR:
2528 case MSR_IA32_LASTBRANCHFROMIP:
2529 case MSR_IA32_LASTBRANCHTOIP:
2530 case MSR_IA32_LASTINTFROMIP:
2531 case MSR_IA32_LASTINTTOIP:
2534 case MSR_VM_HSAVE_PA:
2535 case MSR_K7_EVNTSEL0:
2536 case MSR_K7_EVNTSEL1:
2537 case MSR_K7_EVNTSEL2:
2538 case MSR_K7_EVNTSEL3:
2539 case MSR_K7_PERFCTR0:
2540 case MSR_K7_PERFCTR1:
2541 case MSR_K7_PERFCTR2:
2542 case MSR_K7_PERFCTR3:
2543 case MSR_K8_INT_PENDING_MSG:
2544 case MSR_AMD64_NB_CFG:
2545 case MSR_FAM10H_MMIO_CONF_BASE:
2546 case MSR_AMD64_BU_CFG2:
2549 case MSR_P6_PERFCTR0:
2550 case MSR_P6_PERFCTR1:
2551 case MSR_P6_EVNTSEL0:
2552 case MSR_P6_EVNTSEL1:
2553 if (kvm_pmu_msr(vcpu, msr))
2554 return kvm_pmu_get_msr(vcpu, msr, pdata);
2557 case MSR_IA32_UCODE_REV:
2558 data = 0x100000000ULL;
2561 data = 0x500 | KVM_NR_VAR_MTRR;
2563 case 0x200 ... 0x2ff:
2564 return get_msr_mtrr(vcpu, msr, pdata);
2565 case 0xcd: /* fsb frequency */
2569 * MSR_EBC_FREQUENCY_ID
2570 * Conservative value valid for even the basic CPU models.
2571 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2572 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2573 * and 266MHz for model 3, or 4. Set Core Clock
2574 * Frequency to System Bus Frequency Ratio to 1 (bits
2575 * 31:24) even though these are only valid for CPU
2576 * models > 2, however guests may end up dividing or
2577 * multiplying by zero otherwise.
2579 case MSR_EBC_FREQUENCY_ID:
2582 case MSR_IA32_APICBASE:
2583 data = kvm_get_apic_base(vcpu);
2585 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2586 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2588 case MSR_IA32_TSCDEADLINE:
2589 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2591 case MSR_IA32_TSC_ADJUST:
2592 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2594 case MSR_IA32_MISC_ENABLE:
2595 data = vcpu->arch.ia32_misc_enable_msr;
2597 case MSR_IA32_PERF_STATUS:
2598 /* TSC increment by tick */
2600 /* CPU multiplier */
2601 data |= (((uint64_t)4ULL) << 40);
2604 data = vcpu->arch.efer;
2606 case MSR_KVM_WALL_CLOCK:
2607 case MSR_KVM_WALL_CLOCK_NEW:
2608 data = vcpu->kvm->arch.wall_clock;
2610 case MSR_KVM_SYSTEM_TIME:
2611 case MSR_KVM_SYSTEM_TIME_NEW:
2612 data = vcpu->arch.time;
2614 case MSR_KVM_ASYNC_PF_EN:
2615 data = vcpu->arch.apf.msr_val;
2617 case MSR_KVM_STEAL_TIME:
2618 data = vcpu->arch.st.msr_val;
2620 case MSR_KVM_PV_EOI_EN:
2621 data = vcpu->arch.pv_eoi.msr_val;
2623 case MSR_IA32_P5_MC_ADDR:
2624 case MSR_IA32_P5_MC_TYPE:
2625 case MSR_IA32_MCG_CAP:
2626 case MSR_IA32_MCG_CTL:
2627 case MSR_IA32_MCG_STATUS:
2628 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2629 return get_msr_mce(vcpu, msr, pdata);
2630 case MSR_K7_CLK_CTL:
2632 * Provide expected ramp-up count for K7. All other
2633 * are set to zero, indicating minimum divisors for
2636 * This prevents guest kernels on AMD host with CPU
2637 * type 6, model 8 and higher from exploding due to
2638 * the rdmsr failing.
2642 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2643 if (kvm_hv_msr_partition_wide(msr)) {
2645 mutex_lock(&vcpu->kvm->lock);
2646 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2647 mutex_unlock(&vcpu->kvm->lock);
2650 return get_msr_hyperv(vcpu, msr, pdata);
2652 case MSR_IA32_BBL_CR_CTL3:
2653 /* This legacy MSR exists but isn't fully documented in current
2654 * silicon. It is however accessed by winxp in very narrow
2655 * scenarios where it sets bit #19, itself documented as
2656 * a "reserved" bit. Best effort attempt to source coherent
2657 * read data here should the balance of the register be
2658 * interpreted by the guest:
2660 * L2 cache control register 3: 64GB range, 256KB size,
2661 * enabled, latency 0x1, configured
2665 case MSR_AMD64_OSVW_ID_LENGTH:
2666 if (!guest_cpuid_has_osvw(vcpu))
2668 data = vcpu->arch.osvw.length;
2670 case MSR_AMD64_OSVW_STATUS:
2671 if (!guest_cpuid_has_osvw(vcpu))
2673 data = vcpu->arch.osvw.status;
2676 if (kvm_pmu_msr(vcpu, msr))
2677 return kvm_pmu_get_msr(vcpu, msr, pdata);
2679 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2682 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2690 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2693 * Read or write a bunch of msrs. All parameters are kernel addresses.
2695 * @return number of msrs set successfully.
2697 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2698 struct kvm_msr_entry *entries,
2699 int (*do_msr)(struct kvm_vcpu *vcpu,
2700 unsigned index, u64 *data))
2704 idx = srcu_read_lock(&vcpu->kvm->srcu);
2705 for (i = 0; i < msrs->nmsrs; ++i)
2706 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2708 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2714 * Read or write a bunch of msrs. Parameters are user addresses.
2716 * @return number of msrs set successfully.
2718 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2719 int (*do_msr)(struct kvm_vcpu *vcpu,
2720 unsigned index, u64 *data),
2723 struct kvm_msrs msrs;
2724 struct kvm_msr_entry *entries;
2729 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2733 if (msrs.nmsrs >= MAX_IO_MSRS)
2736 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2737 entries = memdup_user(user_msrs->entries, size);
2738 if (IS_ERR(entries)) {
2739 r = PTR_ERR(entries);
2743 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2748 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2759 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2764 case KVM_CAP_IRQCHIP:
2766 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2767 case KVM_CAP_SET_TSS_ADDR:
2768 case KVM_CAP_EXT_CPUID:
2769 case KVM_CAP_EXT_EMUL_CPUID:
2770 case KVM_CAP_CLOCKSOURCE:
2772 case KVM_CAP_NOP_IO_DELAY:
2773 case KVM_CAP_MP_STATE:
2774 case KVM_CAP_SYNC_MMU:
2775 case KVM_CAP_USER_NMI:
2776 case KVM_CAP_REINJECT_CONTROL:
2777 case KVM_CAP_IRQ_INJECT_STATUS:
2778 case KVM_CAP_IOEVENTFD:
2779 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2781 case KVM_CAP_PIT_STATE2:
2782 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2783 case KVM_CAP_XEN_HVM:
2784 case KVM_CAP_ADJUST_CLOCK:
2785 case KVM_CAP_VCPU_EVENTS:
2786 case KVM_CAP_HYPERV:
2787 case KVM_CAP_HYPERV_VAPIC:
2788 case KVM_CAP_HYPERV_SPIN:
2789 case KVM_CAP_PCI_SEGMENT:
2790 case KVM_CAP_DEBUGREGS:
2791 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2793 case KVM_CAP_ASYNC_PF:
2794 case KVM_CAP_GET_TSC_KHZ:
2795 case KVM_CAP_KVMCLOCK_CTRL:
2796 case KVM_CAP_READONLY_MEM:
2797 case KVM_CAP_HYPERV_TIME:
2798 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2799 case KVM_CAP_TSC_DEADLINE_TIMER:
2800 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2801 case KVM_CAP_ASSIGN_DEV_IRQ:
2802 case KVM_CAP_PCI_2_3:
2806 case KVM_CAP_COALESCED_MMIO:
2807 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2810 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2812 case KVM_CAP_NR_VCPUS:
2813 r = KVM_SOFT_MAX_VCPUS;
2815 case KVM_CAP_MAX_VCPUS:
2818 case KVM_CAP_NR_MEMSLOTS:
2819 r = KVM_USER_MEM_SLOTS;
2821 case KVM_CAP_PV_MMU: /* obsolete */
2824 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2826 r = iommu_present(&pci_bus_type);
2830 r = KVM_MAX_MCE_BANKS;
2835 case KVM_CAP_TSC_CONTROL:
2836 r = kvm_has_tsc_control;
2846 long kvm_arch_dev_ioctl(struct file *filp,
2847 unsigned int ioctl, unsigned long arg)
2849 void __user *argp = (void __user *)arg;
2853 case KVM_GET_MSR_INDEX_LIST: {
2854 struct kvm_msr_list __user *user_msr_list = argp;
2855 struct kvm_msr_list msr_list;
2859 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2862 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2863 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2866 if (n < msr_list.nmsrs)
2869 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2870 num_msrs_to_save * sizeof(u32)))
2872 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2874 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2879 case KVM_GET_SUPPORTED_CPUID:
2880 case KVM_GET_EMULATED_CPUID: {
2881 struct kvm_cpuid2 __user *cpuid_arg = argp;
2882 struct kvm_cpuid2 cpuid;
2885 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2888 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2894 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2899 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2902 mce_cap = KVM_MCE_CAP_SUPPORTED;
2904 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2916 static void wbinvd_ipi(void *garbage)
2921 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2923 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2926 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2928 /* Address WBINVD may be executed by guest */
2929 if (need_emulate_wbinvd(vcpu)) {
2930 if (kvm_x86_ops->has_wbinvd_exit())
2931 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2932 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2933 smp_call_function_single(vcpu->cpu,
2934 wbinvd_ipi, NULL, 1);
2937 kvm_x86_ops->vcpu_load(vcpu, cpu);
2939 /* Apply any externally detected TSC adjustments (due to suspend) */
2940 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2941 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2942 vcpu->arch.tsc_offset_adjustment = 0;
2943 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2946 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2947 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2948 native_read_tsc() - vcpu->arch.last_host_tsc;
2950 mark_tsc_unstable("KVM discovered backwards TSC");
2951 if (check_tsc_unstable()) {
2952 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2953 vcpu->arch.last_guest_tsc);
2954 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2955 vcpu->arch.tsc_catchup = 1;
2958 * On a host with synchronized TSC, there is no need to update
2959 * kvmclock on vcpu->cpu migration
2961 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2962 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2963 if (vcpu->cpu != cpu)
2964 kvm_migrate_timers(vcpu);
2968 accumulate_steal_time(vcpu);
2969 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2972 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2974 kvm_x86_ops->vcpu_put(vcpu);
2975 kvm_put_guest_fpu(vcpu);
2976 vcpu->arch.last_host_tsc = native_read_tsc();
2979 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2980 struct kvm_lapic_state *s)
2982 kvm_x86_ops->sync_pir_to_irr(vcpu);
2983 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2988 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2989 struct kvm_lapic_state *s)
2991 kvm_apic_post_state_restore(vcpu, s);
2992 update_cr8_intercept(vcpu);
2997 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2998 struct kvm_interrupt *irq)
3000 if (irq->irq >= KVM_NR_INTERRUPTS)
3002 if (irqchip_in_kernel(vcpu->kvm))
3005 kvm_queue_interrupt(vcpu, irq->irq, false);
3006 kvm_make_request(KVM_REQ_EVENT, vcpu);
3011 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3013 kvm_inject_nmi(vcpu);
3018 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3019 struct kvm_tpr_access_ctl *tac)
3023 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3027 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3031 unsigned bank_num = mcg_cap & 0xff, bank;
3034 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3036 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3039 vcpu->arch.mcg_cap = mcg_cap;
3040 /* Init IA32_MCG_CTL to all 1s */
3041 if (mcg_cap & MCG_CTL_P)
3042 vcpu->arch.mcg_ctl = ~(u64)0;
3043 /* Init IA32_MCi_CTL to all 1s */
3044 for (bank = 0; bank < bank_num; bank++)
3045 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3050 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3051 struct kvm_x86_mce *mce)
3053 u64 mcg_cap = vcpu->arch.mcg_cap;
3054 unsigned bank_num = mcg_cap & 0xff;
3055 u64 *banks = vcpu->arch.mce_banks;
3057 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3060 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3061 * reporting is disabled
3063 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3064 vcpu->arch.mcg_ctl != ~(u64)0)
3066 banks += 4 * mce->bank;
3068 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3069 * reporting is disabled for the bank
3071 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3073 if (mce->status & MCI_STATUS_UC) {
3074 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3075 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3076 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3079 if (banks[1] & MCI_STATUS_VAL)
3080 mce->status |= MCI_STATUS_OVER;
3081 banks[2] = mce->addr;
3082 banks[3] = mce->misc;
3083 vcpu->arch.mcg_status = mce->mcg_status;
3084 banks[1] = mce->status;
3085 kvm_queue_exception(vcpu, MC_VECTOR);
3086 } else if (!(banks[1] & MCI_STATUS_VAL)
3087 || !(banks[1] & MCI_STATUS_UC)) {
3088 if (banks[1] & MCI_STATUS_VAL)
3089 mce->status |= MCI_STATUS_OVER;
3090 banks[2] = mce->addr;
3091 banks[3] = mce->misc;
3092 banks[1] = mce->status;
3094 banks[1] |= MCI_STATUS_OVER;
3098 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3099 struct kvm_vcpu_events *events)
3102 events->exception.injected =
3103 vcpu->arch.exception.pending &&
3104 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3105 events->exception.nr = vcpu->arch.exception.nr;
3106 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3107 events->exception.pad = 0;
3108 events->exception.error_code = vcpu->arch.exception.error_code;
3110 events->interrupt.injected =
3111 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3112 events->interrupt.nr = vcpu->arch.interrupt.nr;
3113 events->interrupt.soft = 0;
3114 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3116 events->nmi.injected = vcpu->arch.nmi_injected;
3117 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3118 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3119 events->nmi.pad = 0;
3121 events->sipi_vector = 0; /* never valid when reporting to user space */
3123 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3124 | KVM_VCPUEVENT_VALID_SHADOW);
3125 memset(&events->reserved, 0, sizeof(events->reserved));
3128 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3129 struct kvm_vcpu_events *events)
3131 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3132 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3133 | KVM_VCPUEVENT_VALID_SHADOW))
3137 vcpu->arch.exception.pending = events->exception.injected;
3138 vcpu->arch.exception.nr = events->exception.nr;
3139 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3140 vcpu->arch.exception.error_code = events->exception.error_code;
3142 vcpu->arch.interrupt.pending = events->interrupt.injected;
3143 vcpu->arch.interrupt.nr = events->interrupt.nr;
3144 vcpu->arch.interrupt.soft = events->interrupt.soft;
3145 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3146 kvm_x86_ops->set_interrupt_shadow(vcpu,
3147 events->interrupt.shadow);
3149 vcpu->arch.nmi_injected = events->nmi.injected;
3150 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3151 vcpu->arch.nmi_pending = events->nmi.pending;
3152 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3154 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3155 kvm_vcpu_has_lapic(vcpu))
3156 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3158 kvm_make_request(KVM_REQ_EVENT, vcpu);
3163 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3164 struct kvm_debugregs *dbgregs)
3168 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3169 kvm_get_dr(vcpu, 6, &val);
3171 dbgregs->dr7 = vcpu->arch.dr7;
3173 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3176 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3177 struct kvm_debugregs *dbgregs)
3182 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3183 kvm_update_dr0123(vcpu);
3184 vcpu->arch.dr6 = dbgregs->dr6;
3185 kvm_update_dr6(vcpu);
3186 vcpu->arch.dr7 = dbgregs->dr7;
3187 kvm_update_dr7(vcpu);
3192 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3194 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3196 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3197 u64 xstate_bv = xsave->header.xfeatures;
3201 * Copy legacy XSAVE area, to avoid complications with CPUID
3202 * leaves 0 and 1 in the loop below.
3204 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3207 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3210 * Copy each region from the possibly compacted offset to the
3211 * non-compacted offset.
3213 valid = xstate_bv & ~XSTATE_FPSSE;
3215 u64 feature = valid & -valid;
3216 int index = fls64(feature) - 1;
3217 void *src = get_xsave_addr(xsave, feature);
3220 u32 size, offset, ecx, edx;
3221 cpuid_count(XSTATE_CPUID, index,
3222 &size, &offset, &ecx, &edx);
3223 memcpy(dest + offset, src, size);
3230 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3232 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3233 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3237 * Copy legacy XSAVE area, to avoid complications with CPUID
3238 * leaves 0 and 1 in the loop below.
3240 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3242 /* Set XSTATE_BV and possibly XCOMP_BV. */
3243 xsave->header.xfeatures = xstate_bv;
3245 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3248 * Copy each region from the non-compacted offset to the
3249 * possibly compacted offset.
3251 valid = xstate_bv & ~XSTATE_FPSSE;
3253 u64 feature = valid & -valid;
3254 int index = fls64(feature) - 1;
3255 void *dest = get_xsave_addr(xsave, feature);
3258 u32 size, offset, ecx, edx;
3259 cpuid_count(XSTATE_CPUID, index,
3260 &size, &offset, &ecx, &edx);
3261 memcpy(dest, src + offset, size);
3269 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3270 struct kvm_xsave *guest_xsave)
3272 if (cpu_has_xsave) {
3273 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3274 fill_xsave((u8 *) guest_xsave->region, vcpu);
3276 memcpy(guest_xsave->region,
3277 &vcpu->arch.guest_fpu.state.fxsave,
3278 sizeof(struct fxregs_state));
3279 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3284 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3285 struct kvm_xsave *guest_xsave)
3288 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3290 if (cpu_has_xsave) {
3292 * Here we allow setting states that are not present in
3293 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3294 * with old userspace.
3296 if (xstate_bv & ~kvm_supported_xcr0())
3298 load_xsave(vcpu, (u8 *)guest_xsave->region);
3300 if (xstate_bv & ~XSTATE_FPSSE)
3302 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3303 guest_xsave->region, sizeof(struct fxregs_state));
3308 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3309 struct kvm_xcrs *guest_xcrs)
3311 if (!cpu_has_xsave) {
3312 guest_xcrs->nr_xcrs = 0;
3316 guest_xcrs->nr_xcrs = 1;
3317 guest_xcrs->flags = 0;
3318 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3319 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3322 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3323 struct kvm_xcrs *guest_xcrs)
3330 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3333 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3334 /* Only support XCR0 currently */
3335 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3336 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3337 guest_xcrs->xcrs[i].value);
3346 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3347 * stopped by the hypervisor. This function will be called from the host only.
3348 * EINVAL is returned when the host attempts to set the flag for a guest that
3349 * does not support pv clocks.
3351 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3353 if (!vcpu->arch.pv_time_enabled)
3355 vcpu->arch.pvclock_set_guest_stopped_request = true;
3356 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3360 long kvm_arch_vcpu_ioctl(struct file *filp,
3361 unsigned int ioctl, unsigned long arg)
3363 struct kvm_vcpu *vcpu = filp->private_data;
3364 void __user *argp = (void __user *)arg;
3367 struct kvm_lapic_state *lapic;
3368 struct kvm_xsave *xsave;
3369 struct kvm_xcrs *xcrs;
3375 case KVM_GET_LAPIC: {
3377 if (!vcpu->arch.apic)
3379 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3384 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3388 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3393 case KVM_SET_LAPIC: {
3395 if (!vcpu->arch.apic)
3397 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3398 if (IS_ERR(u.lapic))
3399 return PTR_ERR(u.lapic);
3401 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3404 case KVM_INTERRUPT: {
3405 struct kvm_interrupt irq;
3408 if (copy_from_user(&irq, argp, sizeof irq))
3410 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3414 r = kvm_vcpu_ioctl_nmi(vcpu);
3417 case KVM_SET_CPUID: {
3418 struct kvm_cpuid __user *cpuid_arg = argp;
3419 struct kvm_cpuid cpuid;
3422 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3424 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3427 case KVM_SET_CPUID2: {
3428 struct kvm_cpuid2 __user *cpuid_arg = argp;
3429 struct kvm_cpuid2 cpuid;
3432 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3434 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3435 cpuid_arg->entries);
3438 case KVM_GET_CPUID2: {
3439 struct kvm_cpuid2 __user *cpuid_arg = argp;
3440 struct kvm_cpuid2 cpuid;
3443 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3445 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3446 cpuid_arg->entries);
3450 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3456 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3459 r = msr_io(vcpu, argp, do_set_msr, 0);
3461 case KVM_TPR_ACCESS_REPORTING: {
3462 struct kvm_tpr_access_ctl tac;
3465 if (copy_from_user(&tac, argp, sizeof tac))
3467 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3471 if (copy_to_user(argp, &tac, sizeof tac))
3476 case KVM_SET_VAPIC_ADDR: {
3477 struct kvm_vapic_addr va;
3480 if (!irqchip_in_kernel(vcpu->kvm))
3483 if (copy_from_user(&va, argp, sizeof va))
3485 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3488 case KVM_X86_SETUP_MCE: {
3492 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3494 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3497 case KVM_X86_SET_MCE: {
3498 struct kvm_x86_mce mce;
3501 if (copy_from_user(&mce, argp, sizeof mce))
3503 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3506 case KVM_GET_VCPU_EVENTS: {
3507 struct kvm_vcpu_events events;
3509 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3512 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3517 case KVM_SET_VCPU_EVENTS: {
3518 struct kvm_vcpu_events events;
3521 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3524 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3527 case KVM_GET_DEBUGREGS: {
3528 struct kvm_debugregs dbgregs;
3530 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3533 if (copy_to_user(argp, &dbgregs,
3534 sizeof(struct kvm_debugregs)))
3539 case KVM_SET_DEBUGREGS: {
3540 struct kvm_debugregs dbgregs;
3543 if (copy_from_user(&dbgregs, argp,
3544 sizeof(struct kvm_debugregs)))
3547 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3550 case KVM_GET_XSAVE: {
3551 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3556 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3559 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3564 case KVM_SET_XSAVE: {
3565 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3566 if (IS_ERR(u.xsave))
3567 return PTR_ERR(u.xsave);
3569 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3572 case KVM_GET_XCRS: {
3573 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3578 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3581 if (copy_to_user(argp, u.xcrs,
3582 sizeof(struct kvm_xcrs)))
3587 case KVM_SET_XCRS: {
3588 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3590 return PTR_ERR(u.xcrs);
3592 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3595 case KVM_SET_TSC_KHZ: {
3599 user_tsc_khz = (u32)arg;
3601 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3604 if (user_tsc_khz == 0)
3605 user_tsc_khz = tsc_khz;
3607 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3612 case KVM_GET_TSC_KHZ: {
3613 r = vcpu->arch.virtual_tsc_khz;
3616 case KVM_KVMCLOCK_CTRL: {
3617 r = kvm_set_guest_paused(vcpu);
3628 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3630 return VM_FAULT_SIGBUS;
3633 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3637 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3639 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3643 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3646 kvm->arch.ept_identity_map_addr = ident_addr;
3650 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3651 u32 kvm_nr_mmu_pages)
3653 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3656 mutex_lock(&kvm->slots_lock);
3658 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3659 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3661 mutex_unlock(&kvm->slots_lock);
3665 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3667 return kvm->arch.n_max_mmu_pages;
3670 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3675 switch (chip->chip_id) {
3676 case KVM_IRQCHIP_PIC_MASTER:
3677 memcpy(&chip->chip.pic,
3678 &pic_irqchip(kvm)->pics[0],
3679 sizeof(struct kvm_pic_state));
3681 case KVM_IRQCHIP_PIC_SLAVE:
3682 memcpy(&chip->chip.pic,
3683 &pic_irqchip(kvm)->pics[1],
3684 sizeof(struct kvm_pic_state));
3686 case KVM_IRQCHIP_IOAPIC:
3687 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3696 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3701 switch (chip->chip_id) {
3702 case KVM_IRQCHIP_PIC_MASTER:
3703 spin_lock(&pic_irqchip(kvm)->lock);
3704 memcpy(&pic_irqchip(kvm)->pics[0],
3706 sizeof(struct kvm_pic_state));
3707 spin_unlock(&pic_irqchip(kvm)->lock);
3709 case KVM_IRQCHIP_PIC_SLAVE:
3710 spin_lock(&pic_irqchip(kvm)->lock);
3711 memcpy(&pic_irqchip(kvm)->pics[1],
3713 sizeof(struct kvm_pic_state));
3714 spin_unlock(&pic_irqchip(kvm)->lock);
3716 case KVM_IRQCHIP_IOAPIC:
3717 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3723 kvm_pic_update_irq(pic_irqchip(kvm));
3727 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3731 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3732 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3733 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3737 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3741 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3742 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3743 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3744 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3748 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3752 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3753 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3754 sizeof(ps->channels));
3755 ps->flags = kvm->arch.vpit->pit_state.flags;
3756 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3757 memset(&ps->reserved, 0, sizeof(ps->reserved));
3761 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3763 int r = 0, start = 0;
3764 u32 prev_legacy, cur_legacy;
3765 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3766 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3767 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3768 if (!prev_legacy && cur_legacy)
3770 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3771 sizeof(kvm->arch.vpit->pit_state.channels));
3772 kvm->arch.vpit->pit_state.flags = ps->flags;
3773 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3774 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3778 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3779 struct kvm_reinject_control *control)
3781 if (!kvm->arch.vpit)
3783 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3784 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3785 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3790 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3791 * @kvm: kvm instance
3792 * @log: slot id and address to which we copy the log
3794 * Steps 1-4 below provide general overview of dirty page logging. See
3795 * kvm_get_dirty_log_protect() function description for additional details.
3797 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3798 * always flush the TLB (step 4) even if previous step failed and the dirty
3799 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3800 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3801 * writes will be marked dirty for next log read.
3803 * 1. Take a snapshot of the bit and clear it if needed.
3804 * 2. Write protect the corresponding page.
3805 * 3. Copy the snapshot to the userspace.
3806 * 4. Flush TLB's if needed.
3808 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3810 bool is_dirty = false;
3813 mutex_lock(&kvm->slots_lock);
3816 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3818 if (kvm_x86_ops->flush_log_dirty)
3819 kvm_x86_ops->flush_log_dirty(kvm);
3821 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3824 * All the TLBs can be flushed out of mmu lock, see the comments in
3825 * kvm_mmu_slot_remove_write_access().
3827 lockdep_assert_held(&kvm->slots_lock);
3829 kvm_flush_remote_tlbs(kvm);
3831 mutex_unlock(&kvm->slots_lock);
3835 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3838 if (!irqchip_in_kernel(kvm))
3841 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3842 irq_event->irq, irq_event->level,
3847 long kvm_arch_vm_ioctl(struct file *filp,
3848 unsigned int ioctl, unsigned long arg)
3850 struct kvm *kvm = filp->private_data;
3851 void __user *argp = (void __user *)arg;
3854 * This union makes it completely explicit to gcc-3.x
3855 * that these two variables' stack usage should be
3856 * combined, not added together.
3859 struct kvm_pit_state ps;
3860 struct kvm_pit_state2 ps2;
3861 struct kvm_pit_config pit_config;
3865 case KVM_SET_TSS_ADDR:
3866 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3868 case KVM_SET_IDENTITY_MAP_ADDR: {
3872 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3874 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3877 case KVM_SET_NR_MMU_PAGES:
3878 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3880 case KVM_GET_NR_MMU_PAGES:
3881 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3883 case KVM_CREATE_IRQCHIP: {
3884 struct kvm_pic *vpic;
3886 mutex_lock(&kvm->lock);
3889 goto create_irqchip_unlock;
3891 if (atomic_read(&kvm->online_vcpus))
3892 goto create_irqchip_unlock;
3894 vpic = kvm_create_pic(kvm);
3896 r = kvm_ioapic_init(kvm);
3898 mutex_lock(&kvm->slots_lock);
3899 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3901 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3903 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3905 mutex_unlock(&kvm->slots_lock);
3907 goto create_irqchip_unlock;
3910 goto create_irqchip_unlock;
3912 kvm->arch.vpic = vpic;
3914 r = kvm_setup_default_irq_routing(kvm);
3916 mutex_lock(&kvm->slots_lock);
3917 mutex_lock(&kvm->irq_lock);
3918 kvm_ioapic_destroy(kvm);
3919 kvm_destroy_pic(kvm);
3920 mutex_unlock(&kvm->irq_lock);
3921 mutex_unlock(&kvm->slots_lock);
3923 create_irqchip_unlock:
3924 mutex_unlock(&kvm->lock);
3927 case KVM_CREATE_PIT:
3928 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3930 case KVM_CREATE_PIT2:
3932 if (copy_from_user(&u.pit_config, argp,
3933 sizeof(struct kvm_pit_config)))
3936 mutex_lock(&kvm->slots_lock);
3939 goto create_pit_unlock;
3941 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3945 mutex_unlock(&kvm->slots_lock);
3947 case KVM_GET_IRQCHIP: {
3948 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3949 struct kvm_irqchip *chip;
3951 chip = memdup_user(argp, sizeof(*chip));
3958 if (!irqchip_in_kernel(kvm))
3959 goto get_irqchip_out;
3960 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3962 goto get_irqchip_out;
3964 if (copy_to_user(argp, chip, sizeof *chip))
3965 goto get_irqchip_out;
3971 case KVM_SET_IRQCHIP: {
3972 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3973 struct kvm_irqchip *chip;
3975 chip = memdup_user(argp, sizeof(*chip));
3982 if (!irqchip_in_kernel(kvm))
3983 goto set_irqchip_out;
3984 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3986 goto set_irqchip_out;
3994 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3997 if (!kvm->arch.vpit)
3999 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4003 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4010 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4013 if (!kvm->arch.vpit)
4015 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4018 case KVM_GET_PIT2: {
4020 if (!kvm->arch.vpit)
4022 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4026 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4031 case KVM_SET_PIT2: {
4033 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4036 if (!kvm->arch.vpit)
4038 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4041 case KVM_REINJECT_CONTROL: {
4042 struct kvm_reinject_control control;
4044 if (copy_from_user(&control, argp, sizeof(control)))
4046 r = kvm_vm_ioctl_reinject(kvm, &control);
4049 case KVM_XEN_HVM_CONFIG: {
4051 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4052 sizeof(struct kvm_xen_hvm_config)))
4055 if (kvm->arch.xen_hvm_config.flags)
4060 case KVM_SET_CLOCK: {
4061 struct kvm_clock_data user_ns;
4066 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4074 local_irq_disable();
4075 now_ns = get_kernel_ns();
4076 delta = user_ns.clock - now_ns;
4078 kvm->arch.kvmclock_offset = delta;
4079 kvm_gen_update_masterclock(kvm);
4082 case KVM_GET_CLOCK: {
4083 struct kvm_clock_data user_ns;
4086 local_irq_disable();
4087 now_ns = get_kernel_ns();
4088 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4091 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4094 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4101 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4107 static void kvm_init_msr_list(void)
4112 /* skip the first msrs in the list. KVM-specific */
4113 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
4114 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4118 * Even MSRs that are valid in the host may not be exposed
4119 * to the guests in some cases. We could work around this
4120 * in VMX with the generic MSR save/load machinery, but it
4121 * is not really worthwhile since it will really only
4122 * happen with nested virtualization.
4124 switch (msrs_to_save[i]) {
4125 case MSR_IA32_BNDCFGS:
4126 if (!kvm_x86_ops->mpx_supported())
4134 msrs_to_save[j] = msrs_to_save[i];
4137 num_msrs_to_save = j;
4140 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4148 if (!(vcpu->arch.apic &&
4149 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4150 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4161 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4168 if (!(vcpu->arch.apic &&
4169 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4171 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4173 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4183 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4184 struct kvm_segment *var, int seg)
4186 kvm_x86_ops->set_segment(vcpu, var, seg);
4189 void kvm_get_segment(struct kvm_vcpu *vcpu,
4190 struct kvm_segment *var, int seg)
4192 kvm_x86_ops->get_segment(vcpu, var, seg);
4195 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4196 struct x86_exception *exception)
4200 BUG_ON(!mmu_is_nested(vcpu));
4202 /* NPT walks are always user-walks */
4203 access |= PFERR_USER_MASK;
4204 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4209 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4210 struct x86_exception *exception)
4212 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4213 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4216 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4217 struct x86_exception *exception)
4219 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4220 access |= PFERR_FETCH_MASK;
4221 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4224 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4225 struct x86_exception *exception)
4227 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4228 access |= PFERR_WRITE_MASK;
4229 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4232 /* uses this to access any guest's mapped memory without checking CPL */
4233 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4234 struct x86_exception *exception)
4236 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4239 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4240 struct kvm_vcpu *vcpu, u32 access,
4241 struct x86_exception *exception)
4244 int r = X86EMUL_CONTINUE;
4247 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4249 unsigned offset = addr & (PAGE_SIZE-1);
4250 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4253 if (gpa == UNMAPPED_GVA)
4254 return X86EMUL_PROPAGATE_FAULT;
4255 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4258 r = X86EMUL_IO_NEEDED;
4270 /* used for instruction fetching */
4271 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4272 gva_t addr, void *val, unsigned int bytes,
4273 struct x86_exception *exception)
4275 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4276 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4280 /* Inline kvm_read_guest_virt_helper for speed. */
4281 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4283 if (unlikely(gpa == UNMAPPED_GVA))
4284 return X86EMUL_PROPAGATE_FAULT;
4286 offset = addr & (PAGE_SIZE-1);
4287 if (WARN_ON(offset + bytes > PAGE_SIZE))
4288 bytes = (unsigned)PAGE_SIZE - offset;
4289 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4291 if (unlikely(ret < 0))
4292 return X86EMUL_IO_NEEDED;
4294 return X86EMUL_CONTINUE;
4297 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4298 gva_t addr, void *val, unsigned int bytes,
4299 struct x86_exception *exception)
4301 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4302 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4304 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4307 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4309 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4310 gva_t addr, void *val, unsigned int bytes,
4311 struct x86_exception *exception)
4313 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4314 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4317 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4318 gva_t addr, void *val,
4320 struct x86_exception *exception)
4322 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4324 int r = X86EMUL_CONTINUE;
4327 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4330 unsigned offset = addr & (PAGE_SIZE-1);
4331 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4334 if (gpa == UNMAPPED_GVA)
4335 return X86EMUL_PROPAGATE_FAULT;
4336 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4338 r = X86EMUL_IO_NEEDED;
4349 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4351 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4352 gpa_t *gpa, struct x86_exception *exception,
4355 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4356 | (write ? PFERR_WRITE_MASK : 0);
4358 if (vcpu_match_mmio_gva(vcpu, gva)
4359 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4360 vcpu->arch.access, access)) {
4361 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4362 (gva & (PAGE_SIZE - 1));
4363 trace_vcpu_match_mmio(gva, *gpa, write, false);
4367 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4369 if (*gpa == UNMAPPED_GVA)
4372 /* For APIC access vmexit */
4373 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4376 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4377 trace_vcpu_match_mmio(gva, *gpa, write, true);
4384 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4385 const void *val, int bytes)
4389 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4392 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4396 struct read_write_emulator_ops {
4397 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4399 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4400 void *val, int bytes);
4401 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4402 int bytes, void *val);
4403 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4404 void *val, int bytes);
4408 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4410 if (vcpu->mmio_read_completed) {
4411 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4412 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4413 vcpu->mmio_read_completed = 0;
4420 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4421 void *val, int bytes)
4423 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4426 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4427 void *val, int bytes)
4429 return emulator_write_phys(vcpu, gpa, val, bytes);
4432 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4434 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4435 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4438 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4439 void *val, int bytes)
4441 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4442 return X86EMUL_IO_NEEDED;
4445 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4446 void *val, int bytes)
4448 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4450 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4451 return X86EMUL_CONTINUE;
4454 static const struct read_write_emulator_ops read_emultor = {
4455 .read_write_prepare = read_prepare,
4456 .read_write_emulate = read_emulate,
4457 .read_write_mmio = vcpu_mmio_read,
4458 .read_write_exit_mmio = read_exit_mmio,
4461 static const struct read_write_emulator_ops write_emultor = {
4462 .read_write_emulate = write_emulate,
4463 .read_write_mmio = write_mmio,
4464 .read_write_exit_mmio = write_exit_mmio,
4468 static int emulator_read_write_onepage(unsigned long addr, void *val,
4470 struct x86_exception *exception,
4471 struct kvm_vcpu *vcpu,
4472 const struct read_write_emulator_ops *ops)
4476 bool write = ops->write;
4477 struct kvm_mmio_fragment *frag;
4479 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4482 return X86EMUL_PROPAGATE_FAULT;
4484 /* For APIC access vmexit */
4488 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4489 return X86EMUL_CONTINUE;
4493 * Is this MMIO handled locally?
4495 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4496 if (handled == bytes)
4497 return X86EMUL_CONTINUE;
4503 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4504 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4508 return X86EMUL_CONTINUE;
4511 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4513 void *val, unsigned int bytes,
4514 struct x86_exception *exception,
4515 const struct read_write_emulator_ops *ops)
4517 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4521 if (ops->read_write_prepare &&
4522 ops->read_write_prepare(vcpu, val, bytes))
4523 return X86EMUL_CONTINUE;
4525 vcpu->mmio_nr_fragments = 0;
4527 /* Crossing a page boundary? */
4528 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4531 now = -addr & ~PAGE_MASK;
4532 rc = emulator_read_write_onepage(addr, val, now, exception,
4535 if (rc != X86EMUL_CONTINUE)
4538 if (ctxt->mode != X86EMUL_MODE_PROT64)
4544 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4546 if (rc != X86EMUL_CONTINUE)
4549 if (!vcpu->mmio_nr_fragments)
4552 gpa = vcpu->mmio_fragments[0].gpa;
4554 vcpu->mmio_needed = 1;
4555 vcpu->mmio_cur_fragment = 0;
4557 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4558 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4559 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4560 vcpu->run->mmio.phys_addr = gpa;
4562 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4565 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4569 struct x86_exception *exception)
4571 return emulator_read_write(ctxt, addr, val, bytes,
4572 exception, &read_emultor);
4575 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4579 struct x86_exception *exception)
4581 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4582 exception, &write_emultor);
4585 #define CMPXCHG_TYPE(t, ptr, old, new) \
4586 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4588 #ifdef CONFIG_X86_64
4589 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4591 # define CMPXCHG64(ptr, old, new) \
4592 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4595 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4600 struct x86_exception *exception)
4602 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4608 /* guests cmpxchg8b have to be emulated atomically */
4609 if (bytes > 8 || (bytes & (bytes - 1)))
4612 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4614 if (gpa == UNMAPPED_GVA ||
4615 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4618 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4621 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4622 if (is_error_page(page))
4625 kaddr = kmap_atomic(page);
4626 kaddr += offset_in_page(gpa);
4629 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4632 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4635 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4638 exchanged = CMPXCHG64(kaddr, old, new);
4643 kunmap_atomic(kaddr);
4644 kvm_release_page_dirty(page);
4647 return X86EMUL_CMPXCHG_FAILED;
4649 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4650 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4652 return X86EMUL_CONTINUE;
4655 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4657 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4660 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4662 /* TODO: String I/O for in kernel device */
4665 if (vcpu->arch.pio.in)
4666 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4667 vcpu->arch.pio.size, pd);
4669 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4670 vcpu->arch.pio.port, vcpu->arch.pio.size,
4675 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4676 unsigned short port, void *val,
4677 unsigned int count, bool in)
4679 vcpu->arch.pio.port = port;
4680 vcpu->arch.pio.in = in;
4681 vcpu->arch.pio.count = count;
4682 vcpu->arch.pio.size = size;
4684 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4685 vcpu->arch.pio.count = 0;
4689 vcpu->run->exit_reason = KVM_EXIT_IO;
4690 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4691 vcpu->run->io.size = size;
4692 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4693 vcpu->run->io.count = count;
4694 vcpu->run->io.port = port;
4699 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4700 int size, unsigned short port, void *val,
4703 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4706 if (vcpu->arch.pio.count)
4709 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4712 memcpy(val, vcpu->arch.pio_data, size * count);
4713 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4714 vcpu->arch.pio.count = 0;
4721 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4722 int size, unsigned short port,
4723 const void *val, unsigned int count)
4725 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4727 memcpy(vcpu->arch.pio_data, val, size * count);
4728 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4729 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4732 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4734 return kvm_x86_ops->get_segment_base(vcpu, seg);
4737 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4739 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4742 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4744 if (!need_emulate_wbinvd(vcpu))
4745 return X86EMUL_CONTINUE;
4747 if (kvm_x86_ops->has_wbinvd_exit()) {
4748 int cpu = get_cpu();
4750 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4751 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4752 wbinvd_ipi, NULL, 1);
4754 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4757 return X86EMUL_CONTINUE;
4760 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4762 kvm_x86_ops->skip_emulated_instruction(vcpu);
4763 return kvm_emulate_wbinvd_noskip(vcpu);
4765 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4769 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4771 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4774 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4775 unsigned long *dest)
4777 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4780 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4781 unsigned long value)
4784 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4787 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4789 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4792 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4794 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4795 unsigned long value;
4799 value = kvm_read_cr0(vcpu);
4802 value = vcpu->arch.cr2;
4805 value = kvm_read_cr3(vcpu);
4808 value = kvm_read_cr4(vcpu);
4811 value = kvm_get_cr8(vcpu);
4814 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4821 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4823 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4828 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4831 vcpu->arch.cr2 = val;
4834 res = kvm_set_cr3(vcpu, val);
4837 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4840 res = kvm_set_cr8(vcpu, val);
4843 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4850 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4852 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4855 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4857 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4860 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4862 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4865 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4867 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4870 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4872 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4875 static unsigned long emulator_get_cached_segment_base(
4876 struct x86_emulate_ctxt *ctxt, int seg)
4878 return get_segment_base(emul_to_vcpu(ctxt), seg);
4881 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4882 struct desc_struct *desc, u32 *base3,
4885 struct kvm_segment var;
4887 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4888 *selector = var.selector;
4891 memset(desc, 0, sizeof(*desc));
4897 set_desc_limit(desc, var.limit);
4898 set_desc_base(desc, (unsigned long)var.base);
4899 #ifdef CONFIG_X86_64
4901 *base3 = var.base >> 32;
4903 desc->type = var.type;
4905 desc->dpl = var.dpl;
4906 desc->p = var.present;
4907 desc->avl = var.avl;
4915 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4916 struct desc_struct *desc, u32 base3,
4919 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4920 struct kvm_segment var;
4922 var.selector = selector;
4923 var.base = get_desc_base(desc);
4924 #ifdef CONFIG_X86_64
4925 var.base |= ((u64)base3) << 32;
4927 var.limit = get_desc_limit(desc);
4929 var.limit = (var.limit << 12) | 0xfff;
4930 var.type = desc->type;
4931 var.dpl = desc->dpl;
4936 var.avl = desc->avl;
4937 var.present = desc->p;
4938 var.unusable = !var.present;
4941 kvm_set_segment(vcpu, &var, seg);
4945 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4946 u32 msr_index, u64 *pdata)
4948 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4951 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4952 u32 msr_index, u64 data)
4954 struct msr_data msr;
4957 msr.index = msr_index;
4958 msr.host_initiated = false;
4959 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4962 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4965 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4968 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4969 u32 pmc, u64 *pdata)
4971 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4974 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4976 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4979 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4982 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4984 * CR0.TS may reference the host fpu state, not the guest fpu state,
4985 * so it may be clear at this point.
4990 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4995 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4996 struct x86_instruction_info *info,
4997 enum x86_intercept_stage stage)
4999 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5002 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5003 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5005 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5008 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5010 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5013 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5015 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5018 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5020 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5023 static const struct x86_emulate_ops emulate_ops = {
5024 .read_gpr = emulator_read_gpr,
5025 .write_gpr = emulator_write_gpr,
5026 .read_std = kvm_read_guest_virt_system,
5027 .write_std = kvm_write_guest_virt_system,
5028 .fetch = kvm_fetch_guest_virt,
5029 .read_emulated = emulator_read_emulated,
5030 .write_emulated = emulator_write_emulated,
5031 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5032 .invlpg = emulator_invlpg,
5033 .pio_in_emulated = emulator_pio_in_emulated,
5034 .pio_out_emulated = emulator_pio_out_emulated,
5035 .get_segment = emulator_get_segment,
5036 .set_segment = emulator_set_segment,
5037 .get_cached_segment_base = emulator_get_cached_segment_base,
5038 .get_gdt = emulator_get_gdt,
5039 .get_idt = emulator_get_idt,
5040 .set_gdt = emulator_set_gdt,
5041 .set_idt = emulator_set_idt,
5042 .get_cr = emulator_get_cr,
5043 .set_cr = emulator_set_cr,
5044 .cpl = emulator_get_cpl,
5045 .get_dr = emulator_get_dr,
5046 .set_dr = emulator_set_dr,
5047 .set_msr = emulator_set_msr,
5048 .get_msr = emulator_get_msr,
5049 .check_pmc = emulator_check_pmc,
5050 .read_pmc = emulator_read_pmc,
5051 .halt = emulator_halt,
5052 .wbinvd = emulator_wbinvd,
5053 .fix_hypercall = emulator_fix_hypercall,
5054 .get_fpu = emulator_get_fpu,
5055 .put_fpu = emulator_put_fpu,
5056 .intercept = emulator_intercept,
5057 .get_cpuid = emulator_get_cpuid,
5058 .set_nmi_mask = emulator_set_nmi_mask,
5061 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5063 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5065 * an sti; sti; sequence only disable interrupts for the first
5066 * instruction. So, if the last instruction, be it emulated or
5067 * not, left the system with the INT_STI flag enabled, it
5068 * means that the last instruction is an sti. We should not
5069 * leave the flag on in this case. The same goes for mov ss
5071 if (int_shadow & mask)
5073 if (unlikely(int_shadow || mask)) {
5074 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5076 kvm_make_request(KVM_REQ_EVENT, vcpu);
5080 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5082 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5083 if (ctxt->exception.vector == PF_VECTOR)
5084 return kvm_propagate_fault(vcpu, &ctxt->exception);
5086 if (ctxt->exception.error_code_valid)
5087 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5088 ctxt->exception.error_code);
5090 kvm_queue_exception(vcpu, ctxt->exception.vector);
5094 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5096 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5099 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5101 ctxt->eflags = kvm_get_rflags(vcpu);
5102 ctxt->eip = kvm_rip_read(vcpu);
5103 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5104 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5105 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5106 cs_db ? X86EMUL_MODE_PROT32 :
5107 X86EMUL_MODE_PROT16;
5108 ctxt->guest_mode = is_guest_mode(vcpu);
5110 init_decode_cache(ctxt);
5111 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5114 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5116 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5119 init_emulate_ctxt(vcpu);
5123 ctxt->_eip = ctxt->eip + inc_eip;
5124 ret = emulate_int_real(ctxt, irq);
5126 if (ret != X86EMUL_CONTINUE)
5127 return EMULATE_FAIL;
5129 ctxt->eip = ctxt->_eip;
5130 kvm_rip_write(vcpu, ctxt->eip);
5131 kvm_set_rflags(vcpu, ctxt->eflags);
5133 if (irq == NMI_VECTOR)
5134 vcpu->arch.nmi_pending = 0;
5136 vcpu->arch.interrupt.pending = false;
5138 return EMULATE_DONE;
5140 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5142 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5144 int r = EMULATE_DONE;
5146 ++vcpu->stat.insn_emulation_fail;
5147 trace_kvm_emulate_insn_failed(vcpu);
5148 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5149 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5150 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5151 vcpu->run->internal.ndata = 0;
5154 kvm_queue_exception(vcpu, UD_VECTOR);
5159 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5160 bool write_fault_to_shadow_pgtable,
5166 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5169 if (!vcpu->arch.mmu.direct_map) {
5171 * Write permission should be allowed since only
5172 * write access need to be emulated.
5174 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5177 * If the mapping is invalid in guest, let cpu retry
5178 * it to generate fault.
5180 if (gpa == UNMAPPED_GVA)
5185 * Do not retry the unhandleable instruction if it faults on the
5186 * readonly host memory, otherwise it will goto a infinite loop:
5187 * retry instruction -> write #PF -> emulation fail -> retry
5188 * instruction -> ...
5190 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5193 * If the instruction failed on the error pfn, it can not be fixed,
5194 * report the error to userspace.
5196 if (is_error_noslot_pfn(pfn))
5199 kvm_release_pfn_clean(pfn);
5201 /* The instructions are well-emulated on direct mmu. */
5202 if (vcpu->arch.mmu.direct_map) {
5203 unsigned int indirect_shadow_pages;
5205 spin_lock(&vcpu->kvm->mmu_lock);
5206 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5207 spin_unlock(&vcpu->kvm->mmu_lock);
5209 if (indirect_shadow_pages)
5210 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5216 * if emulation was due to access to shadowed page table
5217 * and it failed try to unshadow page and re-enter the
5218 * guest to let CPU execute the instruction.
5220 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5223 * If the access faults on its page table, it can not
5224 * be fixed by unprotecting shadow page and it should
5225 * be reported to userspace.
5227 return !write_fault_to_shadow_pgtable;
5230 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5231 unsigned long cr2, int emulation_type)
5233 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5234 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5236 last_retry_eip = vcpu->arch.last_retry_eip;
5237 last_retry_addr = vcpu->arch.last_retry_addr;
5240 * If the emulation is caused by #PF and it is non-page_table
5241 * writing instruction, it means the VM-EXIT is caused by shadow
5242 * page protected, we can zap the shadow page and retry this
5243 * instruction directly.
5245 * Note: if the guest uses a non-page-table modifying instruction
5246 * on the PDE that points to the instruction, then we will unmap
5247 * the instruction and go to an infinite loop. So, we cache the
5248 * last retried eip and the last fault address, if we meet the eip
5249 * and the address again, we can break out of the potential infinite
5252 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5254 if (!(emulation_type & EMULTYPE_RETRY))
5257 if (x86_page_table_writing_insn(ctxt))
5260 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5263 vcpu->arch.last_retry_eip = ctxt->eip;
5264 vcpu->arch.last_retry_addr = cr2;
5266 if (!vcpu->arch.mmu.direct_map)
5267 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5269 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5274 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5275 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5277 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5286 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5287 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5292 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5294 struct kvm_run *kvm_run = vcpu->run;
5297 * rflags is the old, "raw" value of the flags. The new value has
5298 * not been saved yet.
5300 * This is correct even for TF set by the guest, because "the
5301 * processor will not generate this exception after the instruction
5302 * that sets the TF flag".
5304 if (unlikely(rflags & X86_EFLAGS_TF)) {
5305 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5306 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5308 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5309 kvm_run->debug.arch.exception = DB_VECTOR;
5310 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5311 *r = EMULATE_USER_EXIT;
5313 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5315 * "Certain debug exceptions may clear bit 0-3. The
5316 * remaining contents of the DR6 register are never
5317 * cleared by the processor".
5319 vcpu->arch.dr6 &= ~15;
5320 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5321 kvm_queue_exception(vcpu, DB_VECTOR);
5326 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5328 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5329 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5330 struct kvm_run *kvm_run = vcpu->run;
5331 unsigned long eip = kvm_get_linear_rip(vcpu);
5332 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5333 vcpu->arch.guest_debug_dr7,
5337 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5338 kvm_run->debug.arch.pc = eip;
5339 kvm_run->debug.arch.exception = DB_VECTOR;
5340 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5341 *r = EMULATE_USER_EXIT;
5346 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5347 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5348 unsigned long eip = kvm_get_linear_rip(vcpu);
5349 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5354 vcpu->arch.dr6 &= ~15;
5355 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5356 kvm_queue_exception(vcpu, DB_VECTOR);
5365 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5372 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5373 bool writeback = true;
5374 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5377 * Clear write_fault_to_shadow_pgtable here to ensure it is
5380 vcpu->arch.write_fault_to_shadow_pgtable = false;
5381 kvm_clear_exception_queue(vcpu);
5383 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5384 init_emulate_ctxt(vcpu);
5387 * We will reenter on the same instruction since
5388 * we do not set complete_userspace_io. This does not
5389 * handle watchpoints yet, those would be handled in
5392 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5395 ctxt->interruptibility = 0;
5396 ctxt->have_exception = false;
5397 ctxt->exception.vector = -1;
5398 ctxt->perm_ok = false;
5400 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5402 r = x86_decode_insn(ctxt, insn, insn_len);
5404 trace_kvm_emulate_insn_start(vcpu);
5405 ++vcpu->stat.insn_emulation;
5406 if (r != EMULATION_OK) {
5407 if (emulation_type & EMULTYPE_TRAP_UD)
5408 return EMULATE_FAIL;
5409 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5411 return EMULATE_DONE;
5412 if (emulation_type & EMULTYPE_SKIP)
5413 return EMULATE_FAIL;
5414 return handle_emulation_failure(vcpu);
5418 if (emulation_type & EMULTYPE_SKIP) {
5419 kvm_rip_write(vcpu, ctxt->_eip);
5420 if (ctxt->eflags & X86_EFLAGS_RF)
5421 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5422 return EMULATE_DONE;
5425 if (retry_instruction(ctxt, cr2, emulation_type))
5426 return EMULATE_DONE;
5428 /* this is needed for vmware backdoor interface to work since it
5429 changes registers values during IO operation */
5430 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5431 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5432 emulator_invalidate_register_cache(ctxt);
5436 r = x86_emulate_insn(ctxt);
5438 if (r == EMULATION_INTERCEPTED)
5439 return EMULATE_DONE;
5441 if (r == EMULATION_FAILED) {
5442 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5444 return EMULATE_DONE;
5446 return handle_emulation_failure(vcpu);
5449 if (ctxt->have_exception) {
5451 if (inject_emulated_exception(vcpu))
5453 } else if (vcpu->arch.pio.count) {
5454 if (!vcpu->arch.pio.in) {
5455 /* FIXME: return into emulator if single-stepping. */
5456 vcpu->arch.pio.count = 0;
5459 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5461 r = EMULATE_USER_EXIT;
5462 } else if (vcpu->mmio_needed) {
5463 if (!vcpu->mmio_is_write)
5465 r = EMULATE_USER_EXIT;
5466 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5467 } else if (r == EMULATION_RESTART)
5473 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5474 toggle_interruptibility(vcpu, ctxt->interruptibility);
5475 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5476 kvm_rip_write(vcpu, ctxt->eip);
5477 if (r == EMULATE_DONE)
5478 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5479 if (!ctxt->have_exception ||
5480 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5481 __kvm_set_rflags(vcpu, ctxt->eflags);
5484 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5485 * do nothing, and it will be requested again as soon as
5486 * the shadow expires. But we still need to check here,
5487 * because POPF has no interrupt shadow.
5489 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5490 kvm_make_request(KVM_REQ_EVENT, vcpu);
5492 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5496 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5498 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5500 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5501 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5502 size, port, &val, 1);
5503 /* do not return to emulator after return from userspace */
5504 vcpu->arch.pio.count = 0;
5507 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5509 static void tsc_bad(void *info)
5511 __this_cpu_write(cpu_tsc_khz, 0);
5514 static void tsc_khz_changed(void *data)
5516 struct cpufreq_freqs *freq = data;
5517 unsigned long khz = 0;
5521 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5522 khz = cpufreq_quick_get(raw_smp_processor_id());
5525 __this_cpu_write(cpu_tsc_khz, khz);
5528 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5531 struct cpufreq_freqs *freq = data;
5533 struct kvm_vcpu *vcpu;
5534 int i, send_ipi = 0;
5537 * We allow guests to temporarily run on slowing clocks,
5538 * provided we notify them after, or to run on accelerating
5539 * clocks, provided we notify them before. Thus time never
5542 * However, we have a problem. We can't atomically update
5543 * the frequency of a given CPU from this function; it is
5544 * merely a notifier, which can be called from any CPU.
5545 * Changing the TSC frequency at arbitrary points in time
5546 * requires a recomputation of local variables related to
5547 * the TSC for each VCPU. We must flag these local variables
5548 * to be updated and be sure the update takes place with the
5549 * new frequency before any guests proceed.
5551 * Unfortunately, the combination of hotplug CPU and frequency
5552 * change creates an intractable locking scenario; the order
5553 * of when these callouts happen is undefined with respect to
5554 * CPU hotplug, and they can race with each other. As such,
5555 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5556 * undefined; you can actually have a CPU frequency change take
5557 * place in between the computation of X and the setting of the
5558 * variable. To protect against this problem, all updates of
5559 * the per_cpu tsc_khz variable are done in an interrupt
5560 * protected IPI, and all callers wishing to update the value
5561 * must wait for a synchronous IPI to complete (which is trivial
5562 * if the caller is on the CPU already). This establishes the
5563 * necessary total order on variable updates.
5565 * Note that because a guest time update may take place
5566 * anytime after the setting of the VCPU's request bit, the
5567 * correct TSC value must be set before the request. However,
5568 * to ensure the update actually makes it to any guest which
5569 * starts running in hardware virtualization between the set
5570 * and the acquisition of the spinlock, we must also ping the
5571 * CPU after setting the request bit.
5575 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5577 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5580 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5582 spin_lock(&kvm_lock);
5583 list_for_each_entry(kvm, &vm_list, vm_list) {
5584 kvm_for_each_vcpu(i, vcpu, kvm) {
5585 if (vcpu->cpu != freq->cpu)
5587 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5588 if (vcpu->cpu != smp_processor_id())
5592 spin_unlock(&kvm_lock);
5594 if (freq->old < freq->new && send_ipi) {
5596 * We upscale the frequency. Must make the guest
5597 * doesn't see old kvmclock values while running with
5598 * the new frequency, otherwise we risk the guest sees
5599 * time go backwards.
5601 * In case we update the frequency for another cpu
5602 * (which might be in guest context) send an interrupt
5603 * to kick the cpu out of guest context. Next time
5604 * guest context is entered kvmclock will be updated,
5605 * so the guest will not see stale values.
5607 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5612 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5613 .notifier_call = kvmclock_cpufreq_notifier
5616 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5617 unsigned long action, void *hcpu)
5619 unsigned int cpu = (unsigned long)hcpu;
5623 case CPU_DOWN_FAILED:
5624 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5626 case CPU_DOWN_PREPARE:
5627 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5633 static struct notifier_block kvmclock_cpu_notifier_block = {
5634 .notifier_call = kvmclock_cpu_notifier,
5635 .priority = -INT_MAX
5638 static void kvm_timer_init(void)
5642 max_tsc_khz = tsc_khz;
5644 cpu_notifier_register_begin();
5645 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5646 #ifdef CONFIG_CPU_FREQ
5647 struct cpufreq_policy policy;
5648 memset(&policy, 0, sizeof(policy));
5650 cpufreq_get_policy(&policy, cpu);
5651 if (policy.cpuinfo.max_freq)
5652 max_tsc_khz = policy.cpuinfo.max_freq;
5655 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5656 CPUFREQ_TRANSITION_NOTIFIER);
5658 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5659 for_each_online_cpu(cpu)
5660 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5662 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5663 cpu_notifier_register_done();
5667 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5669 int kvm_is_in_guest(void)
5671 return __this_cpu_read(current_vcpu) != NULL;
5674 static int kvm_is_user_mode(void)
5678 if (__this_cpu_read(current_vcpu))
5679 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5681 return user_mode != 0;
5684 static unsigned long kvm_get_guest_ip(void)
5686 unsigned long ip = 0;
5688 if (__this_cpu_read(current_vcpu))
5689 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5694 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5695 .is_in_guest = kvm_is_in_guest,
5696 .is_user_mode = kvm_is_user_mode,
5697 .get_guest_ip = kvm_get_guest_ip,
5700 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5702 __this_cpu_write(current_vcpu, vcpu);
5704 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5706 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5708 __this_cpu_write(current_vcpu, NULL);
5710 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5712 static void kvm_set_mmio_spte_mask(void)
5715 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5718 * Set the reserved bits and the present bit of an paging-structure
5719 * entry to generate page fault with PFER.RSV = 1.
5721 /* Mask the reserved physical address bits. */
5722 mask = rsvd_bits(maxphyaddr, 51);
5724 /* Bit 62 is always reserved for 32bit host. */
5725 mask |= 0x3ull << 62;
5727 /* Set the present bit. */
5730 #ifdef CONFIG_X86_64
5732 * If reserved bit is not supported, clear the present bit to disable
5735 if (maxphyaddr == 52)
5739 kvm_mmu_set_mmio_spte_mask(mask);
5742 #ifdef CONFIG_X86_64
5743 static void pvclock_gtod_update_fn(struct work_struct *work)
5747 struct kvm_vcpu *vcpu;
5750 spin_lock(&kvm_lock);
5751 list_for_each_entry(kvm, &vm_list, vm_list)
5752 kvm_for_each_vcpu(i, vcpu, kvm)
5753 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5754 atomic_set(&kvm_guest_has_master_clock, 0);
5755 spin_unlock(&kvm_lock);
5758 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5761 * Notification about pvclock gtod data update.
5763 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5766 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5767 struct timekeeper *tk = priv;
5769 update_pvclock_gtod(tk);
5771 /* disable master clock if host does not trust, or does not
5772 * use, TSC clocksource
5774 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5775 atomic_read(&kvm_guest_has_master_clock) != 0)
5776 queue_work(system_long_wq, &pvclock_gtod_work);
5781 static struct notifier_block pvclock_gtod_notifier = {
5782 .notifier_call = pvclock_gtod_notify,
5786 int kvm_arch_init(void *opaque)
5789 struct kvm_x86_ops *ops = opaque;
5792 printk(KERN_ERR "kvm: already loaded the other module\n");
5797 if (!ops->cpu_has_kvm_support()) {
5798 printk(KERN_ERR "kvm: no hardware support\n");
5802 if (ops->disabled_by_bios()) {
5803 printk(KERN_ERR "kvm: disabled by bios\n");
5809 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5811 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5815 r = kvm_mmu_module_init();
5817 goto out_free_percpu;
5819 kvm_set_mmio_spte_mask();
5823 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5824 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5828 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5831 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5834 #ifdef CONFIG_X86_64
5835 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5841 free_percpu(shared_msrs);
5846 void kvm_arch_exit(void)
5848 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5850 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5851 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5852 CPUFREQ_TRANSITION_NOTIFIER);
5853 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5854 #ifdef CONFIG_X86_64
5855 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5858 kvm_mmu_module_exit();
5859 free_percpu(shared_msrs);
5862 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5864 ++vcpu->stat.halt_exits;
5865 if (irqchip_in_kernel(vcpu->kvm)) {
5866 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5869 vcpu->run->exit_reason = KVM_EXIT_HLT;
5873 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5875 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5877 kvm_x86_ops->skip_emulated_instruction(vcpu);
5878 return kvm_vcpu_halt(vcpu);
5880 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5882 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5884 u64 param, ingpa, outgpa, ret;
5885 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5886 bool fast, longmode;
5889 * hypercall generates UD from non zero cpl and real mode
5892 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5893 kvm_queue_exception(vcpu, UD_VECTOR);
5897 longmode = is_64_bit_mode(vcpu);
5900 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5901 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5902 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5903 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5904 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5905 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5907 #ifdef CONFIG_X86_64
5909 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5910 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5911 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5915 code = param & 0xffff;
5916 fast = (param >> 16) & 0x1;
5917 rep_cnt = (param >> 32) & 0xfff;
5918 rep_idx = (param >> 48) & 0xfff;
5920 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5923 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5924 kvm_vcpu_on_spin(vcpu);
5927 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5931 ret = res | (((u64)rep_done & 0xfff) << 32);
5933 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5935 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5936 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5943 * kvm_pv_kick_cpu_op: Kick a vcpu.
5945 * @apicid - apicid of vcpu to be kicked.
5947 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5949 struct kvm_lapic_irq lapic_irq;
5951 lapic_irq.shorthand = 0;
5952 lapic_irq.dest_mode = 0;
5953 lapic_irq.dest_id = apicid;
5955 lapic_irq.delivery_mode = APIC_DM_REMRD;
5956 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5959 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5961 unsigned long nr, a0, a1, a2, a3, ret;
5962 int op_64_bit, r = 1;
5964 kvm_x86_ops->skip_emulated_instruction(vcpu);
5966 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5967 return kvm_hv_hypercall(vcpu);
5969 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5970 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5971 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5972 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5973 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5975 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5977 op_64_bit = is_64_bit_mode(vcpu);
5986 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5992 case KVM_HC_VAPIC_POLL_IRQ:
5995 case KVM_HC_KICK_CPU:
5996 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6006 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6007 ++vcpu->stat.hypercalls;
6010 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6012 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6014 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6015 char instruction[3];
6016 unsigned long rip = kvm_rip_read(vcpu);
6018 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6020 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
6024 * Check if userspace requested an interrupt window, and that the
6025 * interrupt window is open.
6027 * No need to exit to userspace if we already have an interrupt queued.
6029 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6031 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
6032 vcpu->run->request_interrupt_window &&
6033 kvm_arch_interrupt_allowed(vcpu));
6036 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6038 struct kvm_run *kvm_run = vcpu->run;
6040 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6041 kvm_run->cr8 = kvm_get_cr8(vcpu);
6042 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6043 if (irqchip_in_kernel(vcpu->kvm))
6044 kvm_run->ready_for_interrupt_injection = 1;
6046 kvm_run->ready_for_interrupt_injection =
6047 kvm_arch_interrupt_allowed(vcpu) &&
6048 !kvm_cpu_has_interrupt(vcpu) &&
6049 !kvm_event_needs_reinjection(vcpu);
6052 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6056 if (!kvm_x86_ops->update_cr8_intercept)
6059 if (!vcpu->arch.apic)
6062 if (!vcpu->arch.apic->vapic_addr)
6063 max_irr = kvm_lapic_find_highest_irr(vcpu);
6070 tpr = kvm_lapic_get_cr8(vcpu);
6072 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6075 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6079 /* try to reinject previous events if any */
6080 if (vcpu->arch.exception.pending) {
6081 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6082 vcpu->arch.exception.has_error_code,
6083 vcpu->arch.exception.error_code);
6085 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6086 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6089 if (vcpu->arch.exception.nr == DB_VECTOR &&
6090 (vcpu->arch.dr7 & DR7_GD)) {
6091 vcpu->arch.dr7 &= ~DR7_GD;
6092 kvm_update_dr7(vcpu);
6095 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6096 vcpu->arch.exception.has_error_code,
6097 vcpu->arch.exception.error_code,
6098 vcpu->arch.exception.reinject);
6102 if (vcpu->arch.nmi_injected) {
6103 kvm_x86_ops->set_nmi(vcpu);
6107 if (vcpu->arch.interrupt.pending) {
6108 kvm_x86_ops->set_irq(vcpu);
6112 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6113 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6118 /* try to inject new event if pending */
6119 if (vcpu->arch.nmi_pending) {
6120 if (kvm_x86_ops->nmi_allowed(vcpu)) {
6121 --vcpu->arch.nmi_pending;
6122 vcpu->arch.nmi_injected = true;
6123 kvm_x86_ops->set_nmi(vcpu);
6125 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6127 * Because interrupts can be injected asynchronously, we are
6128 * calling check_nested_events again here to avoid a race condition.
6129 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6130 * proposal and current concerns. Perhaps we should be setting
6131 * KVM_REQ_EVENT only on certain events and not unconditionally?
6133 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6134 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6138 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6139 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6141 kvm_x86_ops->set_irq(vcpu);
6147 static void process_nmi(struct kvm_vcpu *vcpu)
6152 * x86 is limited to one NMI running, and one NMI pending after it.
6153 * If an NMI is already in progress, limit further NMIs to just one.
6154 * Otherwise, allow two (and we'll inject the first one immediately).
6156 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6159 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6160 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6161 kvm_make_request(KVM_REQ_EVENT, vcpu);
6164 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6166 u64 eoi_exit_bitmap[4];
6169 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6172 memset(eoi_exit_bitmap, 0, 32);
6175 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
6176 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6177 kvm_apic_update_tmr(vcpu, tmr);
6180 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6182 ++vcpu->stat.tlb_flush;
6183 kvm_x86_ops->tlb_flush(vcpu);
6186 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6188 struct page *page = NULL;
6190 if (!irqchip_in_kernel(vcpu->kvm))
6193 if (!kvm_x86_ops->set_apic_access_page_addr)
6196 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6197 if (is_error_page(page))
6199 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6202 * Do not pin apic access page in memory, the MMU notifier
6203 * will call us again if it is migrated or swapped out.
6207 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6209 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6210 unsigned long address)
6213 * The physical address of apic access page is stored in the VMCS.
6214 * Update it when it becomes invalid.
6216 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6217 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6221 * Returns 1 to let vcpu_run() continue the guest execution loop without
6222 * exiting to the userspace. Otherwise, the value will be returned to the
6225 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6228 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
6229 vcpu->run->request_interrupt_window;
6230 bool req_immediate_exit = false;
6232 if (vcpu->requests) {
6233 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6234 kvm_mmu_unload(vcpu);
6235 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6236 __kvm_migrate_timers(vcpu);
6237 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6238 kvm_gen_update_masterclock(vcpu->kvm);
6239 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6240 kvm_gen_kvmclock_update(vcpu);
6241 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6242 r = kvm_guest_time_update(vcpu);
6246 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6247 kvm_mmu_sync_roots(vcpu);
6248 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6249 kvm_vcpu_flush_tlb(vcpu);
6250 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6251 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6255 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6256 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6260 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6261 vcpu->fpu_active = 0;
6262 kvm_x86_ops->fpu_deactivate(vcpu);
6264 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6265 /* Page is swapped out. Do synthetic halt */
6266 vcpu->arch.apf.halted = true;
6270 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6271 record_steal_time(vcpu);
6272 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6274 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6275 kvm_handle_pmu_event(vcpu);
6276 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6277 kvm_deliver_pmi(vcpu);
6278 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6279 vcpu_scan_ioapic(vcpu);
6280 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6281 kvm_vcpu_reload_apic_access_page(vcpu);
6284 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6285 kvm_apic_accept_events(vcpu);
6286 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6291 if (inject_pending_event(vcpu, req_int_win) != 0)
6292 req_immediate_exit = true;
6293 /* enable NMI/IRQ window open exits if needed */
6294 else if (vcpu->arch.nmi_pending)
6295 kvm_x86_ops->enable_nmi_window(vcpu);
6296 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6297 kvm_x86_ops->enable_irq_window(vcpu);
6299 if (kvm_lapic_enabled(vcpu)) {
6301 * Update architecture specific hints for APIC
6302 * virtual interrupt delivery.
6304 if (kvm_x86_ops->hwapic_irr_update)
6305 kvm_x86_ops->hwapic_irr_update(vcpu,
6306 kvm_lapic_find_highest_irr(vcpu));
6307 update_cr8_intercept(vcpu);
6308 kvm_lapic_sync_to_vapic(vcpu);
6312 r = kvm_mmu_reload(vcpu);
6314 goto cancel_injection;
6319 kvm_x86_ops->prepare_guest_switch(vcpu);
6320 if (vcpu->fpu_active)
6321 kvm_load_guest_fpu(vcpu);
6322 kvm_load_guest_xcr0(vcpu);
6324 vcpu->mode = IN_GUEST_MODE;
6326 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6328 /* We should set ->mode before check ->requests,
6329 * see the comment in make_all_cpus_request.
6331 smp_mb__after_srcu_read_unlock();
6333 local_irq_disable();
6335 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6336 || need_resched() || signal_pending(current)) {
6337 vcpu->mode = OUTSIDE_GUEST_MODE;
6341 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6343 goto cancel_injection;
6346 if (req_immediate_exit)
6347 smp_send_reschedule(vcpu->cpu);
6351 if (unlikely(vcpu->arch.switch_db_regs)) {
6353 set_debugreg(vcpu->arch.eff_db[0], 0);
6354 set_debugreg(vcpu->arch.eff_db[1], 1);
6355 set_debugreg(vcpu->arch.eff_db[2], 2);
6356 set_debugreg(vcpu->arch.eff_db[3], 3);
6357 set_debugreg(vcpu->arch.dr6, 6);
6358 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6361 trace_kvm_entry(vcpu->vcpu_id);
6362 wait_lapic_expire(vcpu);
6363 kvm_x86_ops->run(vcpu);
6366 * Do this here before restoring debug registers on the host. And
6367 * since we do this before handling the vmexit, a DR access vmexit
6368 * can (a) read the correct value of the debug registers, (b) set
6369 * KVM_DEBUGREG_WONT_EXIT again.
6371 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6374 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6375 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6376 for (i = 0; i < KVM_NR_DB_REGS; i++)
6377 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6381 * If the guest has used debug registers, at least dr7
6382 * will be disabled while returning to the host.
6383 * If we don't have active breakpoints in the host, we don't
6384 * care about the messed up debug address registers. But if
6385 * we have some of them active, restore the old state.
6387 if (hw_breakpoint_active())
6388 hw_breakpoint_restore();
6390 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6393 vcpu->mode = OUTSIDE_GUEST_MODE;
6396 /* Interrupt is enabled by handle_external_intr() */
6397 kvm_x86_ops->handle_external_intr(vcpu);
6402 * We must have an instruction between local_irq_enable() and
6403 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6404 * the interrupt shadow. The stat.exits increment will do nicely.
6405 * But we need to prevent reordering, hence this barrier():
6413 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6416 * Profile KVM exit RIPs:
6418 if (unlikely(prof_on == KVM_PROFILING)) {
6419 unsigned long rip = kvm_rip_read(vcpu);
6420 profile_hit(KVM_PROFILING, (void *)rip);
6423 if (unlikely(vcpu->arch.tsc_always_catchup))
6424 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6426 if (vcpu->arch.apic_attention)
6427 kvm_lapic_sync_from_vapic(vcpu);
6429 r = kvm_x86_ops->handle_exit(vcpu);
6433 kvm_x86_ops->cancel_injection(vcpu);
6434 if (unlikely(vcpu->arch.apic_attention))
6435 kvm_lapic_sync_from_vapic(vcpu);
6440 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6442 if (!kvm_arch_vcpu_runnable(vcpu)) {
6443 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6444 kvm_vcpu_block(vcpu);
6445 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6446 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6450 kvm_apic_accept_events(vcpu);
6451 switch(vcpu->arch.mp_state) {
6452 case KVM_MP_STATE_HALTED:
6453 vcpu->arch.pv.pv_unhalted = false;
6454 vcpu->arch.mp_state =
6455 KVM_MP_STATE_RUNNABLE;
6456 case KVM_MP_STATE_RUNNABLE:
6457 vcpu->arch.apf.halted = false;
6459 case KVM_MP_STATE_INIT_RECEIVED:
6468 static int vcpu_run(struct kvm_vcpu *vcpu)
6471 struct kvm *kvm = vcpu->kvm;
6473 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6476 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6477 !vcpu->arch.apf.halted)
6478 r = vcpu_enter_guest(vcpu);
6480 r = vcpu_block(kvm, vcpu);
6484 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6485 if (kvm_cpu_has_pending_timer(vcpu))
6486 kvm_inject_pending_timer_irqs(vcpu);
6488 if (dm_request_for_irq_injection(vcpu)) {
6490 vcpu->run->exit_reason = KVM_EXIT_INTR;
6491 ++vcpu->stat.request_irq_exits;
6495 kvm_check_async_pf_completion(vcpu);
6497 if (signal_pending(current)) {
6499 vcpu->run->exit_reason = KVM_EXIT_INTR;
6500 ++vcpu->stat.signal_exits;
6503 if (need_resched()) {
6504 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6506 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6510 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6515 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6518 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6519 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6520 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6521 if (r != EMULATE_DONE)
6526 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6528 BUG_ON(!vcpu->arch.pio.count);
6530 return complete_emulated_io(vcpu);
6534 * Implements the following, as a state machine:
6538 * for each mmio piece in the fragment
6546 * for each mmio piece in the fragment
6551 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6553 struct kvm_run *run = vcpu->run;
6554 struct kvm_mmio_fragment *frag;
6557 BUG_ON(!vcpu->mmio_needed);
6559 /* Complete previous fragment */
6560 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6561 len = min(8u, frag->len);
6562 if (!vcpu->mmio_is_write)
6563 memcpy(frag->data, run->mmio.data, len);
6565 if (frag->len <= 8) {
6566 /* Switch to the next fragment. */
6568 vcpu->mmio_cur_fragment++;
6570 /* Go forward to the next mmio piece. */
6576 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6577 vcpu->mmio_needed = 0;
6579 /* FIXME: return into emulator if single-stepping. */
6580 if (vcpu->mmio_is_write)
6582 vcpu->mmio_read_completed = 1;
6583 return complete_emulated_io(vcpu);
6586 run->exit_reason = KVM_EXIT_MMIO;
6587 run->mmio.phys_addr = frag->gpa;
6588 if (vcpu->mmio_is_write)
6589 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6590 run->mmio.len = min(8u, frag->len);
6591 run->mmio.is_write = vcpu->mmio_is_write;
6592 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6597 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6599 struct fpu *fpu = ¤t->thread.fpu;
6603 fpu__activate_curr(fpu);
6605 if (vcpu->sigset_active)
6606 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6608 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6609 kvm_vcpu_block(vcpu);
6610 kvm_apic_accept_events(vcpu);
6611 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6616 /* re-sync apic's tpr */
6617 if (!irqchip_in_kernel(vcpu->kvm)) {
6618 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6624 if (unlikely(vcpu->arch.complete_userspace_io)) {
6625 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6626 vcpu->arch.complete_userspace_io = NULL;
6631 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6636 post_kvm_run_save(vcpu);
6637 if (vcpu->sigset_active)
6638 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6643 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6645 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6647 * We are here if userspace calls get_regs() in the middle of
6648 * instruction emulation. Registers state needs to be copied
6649 * back from emulation context to vcpu. Userspace shouldn't do
6650 * that usually, but some bad designed PV devices (vmware
6651 * backdoor interface) need this to work
6653 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6654 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6656 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6657 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6658 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6659 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6660 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6661 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6662 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6663 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6664 #ifdef CONFIG_X86_64
6665 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6666 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6667 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6668 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6669 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6670 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6671 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6672 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6675 regs->rip = kvm_rip_read(vcpu);
6676 regs->rflags = kvm_get_rflags(vcpu);
6681 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6683 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6684 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6686 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6687 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6688 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6689 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6690 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6691 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6692 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6693 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6694 #ifdef CONFIG_X86_64
6695 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6696 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6697 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6698 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6699 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6700 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6701 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6702 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6705 kvm_rip_write(vcpu, regs->rip);
6706 kvm_set_rflags(vcpu, regs->rflags);
6708 vcpu->arch.exception.pending = false;
6710 kvm_make_request(KVM_REQ_EVENT, vcpu);
6715 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6717 struct kvm_segment cs;
6719 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6723 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6725 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6726 struct kvm_sregs *sregs)
6730 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6731 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6732 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6733 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6734 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6735 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6737 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6738 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6740 kvm_x86_ops->get_idt(vcpu, &dt);
6741 sregs->idt.limit = dt.size;
6742 sregs->idt.base = dt.address;
6743 kvm_x86_ops->get_gdt(vcpu, &dt);
6744 sregs->gdt.limit = dt.size;
6745 sregs->gdt.base = dt.address;
6747 sregs->cr0 = kvm_read_cr0(vcpu);
6748 sregs->cr2 = vcpu->arch.cr2;
6749 sregs->cr3 = kvm_read_cr3(vcpu);
6750 sregs->cr4 = kvm_read_cr4(vcpu);
6751 sregs->cr8 = kvm_get_cr8(vcpu);
6752 sregs->efer = vcpu->arch.efer;
6753 sregs->apic_base = kvm_get_apic_base(vcpu);
6755 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6757 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6758 set_bit(vcpu->arch.interrupt.nr,
6759 (unsigned long *)sregs->interrupt_bitmap);
6764 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6765 struct kvm_mp_state *mp_state)
6767 kvm_apic_accept_events(vcpu);
6768 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6769 vcpu->arch.pv.pv_unhalted)
6770 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6772 mp_state->mp_state = vcpu->arch.mp_state;
6777 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6778 struct kvm_mp_state *mp_state)
6780 if (!kvm_vcpu_has_lapic(vcpu) &&
6781 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6784 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6785 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6786 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6788 vcpu->arch.mp_state = mp_state->mp_state;
6789 kvm_make_request(KVM_REQ_EVENT, vcpu);
6793 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6794 int reason, bool has_error_code, u32 error_code)
6796 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6799 init_emulate_ctxt(vcpu);
6801 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6802 has_error_code, error_code);
6805 return EMULATE_FAIL;
6807 kvm_rip_write(vcpu, ctxt->eip);
6808 kvm_set_rflags(vcpu, ctxt->eflags);
6809 kvm_make_request(KVM_REQ_EVENT, vcpu);
6810 return EMULATE_DONE;
6812 EXPORT_SYMBOL_GPL(kvm_task_switch);
6814 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6815 struct kvm_sregs *sregs)
6817 struct msr_data apic_base_msr;
6818 int mmu_reset_needed = 0;
6819 int pending_vec, max_bits, idx;
6822 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6825 dt.size = sregs->idt.limit;
6826 dt.address = sregs->idt.base;
6827 kvm_x86_ops->set_idt(vcpu, &dt);
6828 dt.size = sregs->gdt.limit;
6829 dt.address = sregs->gdt.base;
6830 kvm_x86_ops->set_gdt(vcpu, &dt);
6832 vcpu->arch.cr2 = sregs->cr2;
6833 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6834 vcpu->arch.cr3 = sregs->cr3;
6835 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6837 kvm_set_cr8(vcpu, sregs->cr8);
6839 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6840 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6841 apic_base_msr.data = sregs->apic_base;
6842 apic_base_msr.host_initiated = true;
6843 kvm_set_apic_base(vcpu, &apic_base_msr);
6845 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6846 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6847 vcpu->arch.cr0 = sregs->cr0;
6849 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6850 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6851 if (sregs->cr4 & X86_CR4_OSXSAVE)
6852 kvm_update_cpuid(vcpu);
6854 idx = srcu_read_lock(&vcpu->kvm->srcu);
6855 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6856 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6857 mmu_reset_needed = 1;
6859 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6861 if (mmu_reset_needed)
6862 kvm_mmu_reset_context(vcpu);
6864 max_bits = KVM_NR_INTERRUPTS;
6865 pending_vec = find_first_bit(
6866 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6867 if (pending_vec < max_bits) {
6868 kvm_queue_interrupt(vcpu, pending_vec, false);
6869 pr_debug("Set back pending irq %d\n", pending_vec);
6872 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6873 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6874 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6875 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6876 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6877 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6879 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6880 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6882 update_cr8_intercept(vcpu);
6884 /* Older userspace won't unhalt the vcpu on reset. */
6885 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6886 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6888 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6890 kvm_make_request(KVM_REQ_EVENT, vcpu);
6895 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6896 struct kvm_guest_debug *dbg)
6898 unsigned long rflags;
6901 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6903 if (vcpu->arch.exception.pending)
6905 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6906 kvm_queue_exception(vcpu, DB_VECTOR);
6908 kvm_queue_exception(vcpu, BP_VECTOR);
6912 * Read rflags as long as potentially injected trace flags are still
6915 rflags = kvm_get_rflags(vcpu);
6917 vcpu->guest_debug = dbg->control;
6918 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6919 vcpu->guest_debug = 0;
6921 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6922 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6923 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6924 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6926 for (i = 0; i < KVM_NR_DB_REGS; i++)
6927 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6929 kvm_update_dr7(vcpu);
6931 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6932 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6933 get_segment_base(vcpu, VCPU_SREG_CS);
6936 * Trigger an rflags update that will inject or remove the trace
6939 kvm_set_rflags(vcpu, rflags);
6941 kvm_x86_ops->update_db_bp_intercept(vcpu);
6951 * Translate a guest virtual address to a guest physical address.
6953 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6954 struct kvm_translation *tr)
6956 unsigned long vaddr = tr->linear_address;
6960 idx = srcu_read_lock(&vcpu->kvm->srcu);
6961 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6962 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6963 tr->physical_address = gpa;
6964 tr->valid = gpa != UNMAPPED_GVA;
6971 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6973 struct fxregs_state *fxsave =
6974 &vcpu->arch.guest_fpu.state.fxsave;
6976 memcpy(fpu->fpr, fxsave->st_space, 128);
6977 fpu->fcw = fxsave->cwd;
6978 fpu->fsw = fxsave->swd;
6979 fpu->ftwx = fxsave->twd;
6980 fpu->last_opcode = fxsave->fop;
6981 fpu->last_ip = fxsave->rip;
6982 fpu->last_dp = fxsave->rdp;
6983 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6988 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6990 struct fxregs_state *fxsave =
6991 &vcpu->arch.guest_fpu.state.fxsave;
6993 memcpy(fxsave->st_space, fpu->fpr, 128);
6994 fxsave->cwd = fpu->fcw;
6995 fxsave->swd = fpu->fsw;
6996 fxsave->twd = fpu->ftwx;
6997 fxsave->fop = fpu->last_opcode;
6998 fxsave->rip = fpu->last_ip;
6999 fxsave->rdp = fpu->last_dp;
7000 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7005 static void fx_init(struct kvm_vcpu *vcpu)
7007 fpstate_init(&vcpu->arch.guest_fpu.state);
7009 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7010 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7013 * Ensure guest xcr0 is valid for loading
7015 vcpu->arch.xcr0 = XSTATE_FP;
7017 vcpu->arch.cr0 |= X86_CR0_ET;
7020 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7022 if (vcpu->guest_fpu_loaded)
7026 * Restore all possible states in the guest,
7027 * and assume host would use all available bits.
7028 * Guest xcr0 would be loaded later.
7030 kvm_put_guest_xcr0(vcpu);
7031 vcpu->guest_fpu_loaded = 1;
7032 __kernel_fpu_begin();
7033 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7037 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7039 kvm_put_guest_xcr0(vcpu);
7041 if (!vcpu->guest_fpu_loaded)
7044 vcpu->guest_fpu_loaded = 0;
7045 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7047 ++vcpu->stat.fpu_reload;
7048 if (!vcpu->arch.eager_fpu)
7049 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7054 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7056 kvmclock_reset(vcpu);
7058 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7059 kvm_x86_ops->vcpu_free(vcpu);
7062 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7065 struct kvm_vcpu *vcpu;
7067 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7068 printk_once(KERN_WARNING
7069 "kvm: SMP vm created on host with unstable TSC; "
7070 "guest TSC will not be reliable\n");
7072 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7075 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7076 * deactivated soon if it doesn't.
7078 kvm_x86_ops->fpu_activate(vcpu);
7082 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7086 vcpu->arch.mtrr_state.have_fixed = 1;
7087 r = vcpu_load(vcpu);
7090 kvm_vcpu_reset(vcpu);
7091 kvm_mmu_setup(vcpu);
7097 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7099 struct msr_data msr;
7100 struct kvm *kvm = vcpu->kvm;
7102 if (vcpu_load(vcpu))
7105 msr.index = MSR_IA32_TSC;
7106 msr.host_initiated = true;
7107 kvm_write_tsc(vcpu, &msr);
7110 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7111 KVMCLOCK_SYNC_PERIOD);
7114 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7117 vcpu->arch.apf.msr_val = 0;
7119 r = vcpu_load(vcpu);
7121 kvm_mmu_unload(vcpu);
7124 kvm_x86_ops->vcpu_free(vcpu);
7127 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
7129 atomic_set(&vcpu->arch.nmi_queued, 0);
7130 vcpu->arch.nmi_pending = 0;
7131 vcpu->arch.nmi_injected = false;
7132 kvm_clear_interrupt_queue(vcpu);
7133 kvm_clear_exception_queue(vcpu);
7135 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7136 kvm_update_dr0123(vcpu);
7137 vcpu->arch.dr6 = DR6_INIT;
7138 kvm_update_dr6(vcpu);
7139 vcpu->arch.dr7 = DR7_FIXED_1;
7140 kvm_update_dr7(vcpu);
7144 kvm_make_request(KVM_REQ_EVENT, vcpu);
7145 vcpu->arch.apf.msr_val = 0;
7146 vcpu->arch.st.msr_val = 0;
7148 kvmclock_reset(vcpu);
7150 kvm_clear_async_pf_completion_queue(vcpu);
7151 kvm_async_pf_hash_reset(vcpu);
7152 vcpu->arch.apf.halted = false;
7154 kvm_pmu_reset(vcpu);
7156 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7157 vcpu->arch.regs_avail = ~0;
7158 vcpu->arch.regs_dirty = ~0;
7160 kvm_x86_ops->vcpu_reset(vcpu);
7163 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7165 struct kvm_segment cs;
7167 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7168 cs.selector = vector << 8;
7169 cs.base = vector << 12;
7170 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7171 kvm_rip_write(vcpu, 0);
7174 int kvm_arch_hardware_enable(void)
7177 struct kvm_vcpu *vcpu;
7182 bool stable, backwards_tsc = false;
7184 kvm_shared_msr_cpu_online();
7185 ret = kvm_x86_ops->hardware_enable();
7189 local_tsc = native_read_tsc();
7190 stable = !check_tsc_unstable();
7191 list_for_each_entry(kvm, &vm_list, vm_list) {
7192 kvm_for_each_vcpu(i, vcpu, kvm) {
7193 if (!stable && vcpu->cpu == smp_processor_id())
7194 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7195 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7196 backwards_tsc = true;
7197 if (vcpu->arch.last_host_tsc > max_tsc)
7198 max_tsc = vcpu->arch.last_host_tsc;
7204 * Sometimes, even reliable TSCs go backwards. This happens on
7205 * platforms that reset TSC during suspend or hibernate actions, but
7206 * maintain synchronization. We must compensate. Fortunately, we can
7207 * detect that condition here, which happens early in CPU bringup,
7208 * before any KVM threads can be running. Unfortunately, we can't
7209 * bring the TSCs fully up to date with real time, as we aren't yet far
7210 * enough into CPU bringup that we know how much real time has actually
7211 * elapsed; our helper function, get_kernel_ns() will be using boot
7212 * variables that haven't been updated yet.
7214 * So we simply find the maximum observed TSC above, then record the
7215 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7216 * the adjustment will be applied. Note that we accumulate
7217 * adjustments, in case multiple suspend cycles happen before some VCPU
7218 * gets a chance to run again. In the event that no KVM threads get a
7219 * chance to run, we will miss the entire elapsed period, as we'll have
7220 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7221 * loose cycle time. This isn't too big a deal, since the loss will be
7222 * uniform across all VCPUs (not to mention the scenario is extremely
7223 * unlikely). It is possible that a second hibernate recovery happens
7224 * much faster than a first, causing the observed TSC here to be
7225 * smaller; this would require additional padding adjustment, which is
7226 * why we set last_host_tsc to the local tsc observed here.
7228 * N.B. - this code below runs only on platforms with reliable TSC,
7229 * as that is the only way backwards_tsc is set above. Also note
7230 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7231 * have the same delta_cyc adjustment applied if backwards_tsc
7232 * is detected. Note further, this adjustment is only done once,
7233 * as we reset last_host_tsc on all VCPUs to stop this from being
7234 * called multiple times (one for each physical CPU bringup).
7236 * Platforms with unreliable TSCs don't have to deal with this, they
7237 * will be compensated by the logic in vcpu_load, which sets the TSC to
7238 * catchup mode. This will catchup all VCPUs to real time, but cannot
7239 * guarantee that they stay in perfect synchronization.
7241 if (backwards_tsc) {
7242 u64 delta_cyc = max_tsc - local_tsc;
7243 backwards_tsc_observed = true;
7244 list_for_each_entry(kvm, &vm_list, vm_list) {
7245 kvm_for_each_vcpu(i, vcpu, kvm) {
7246 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7247 vcpu->arch.last_host_tsc = local_tsc;
7248 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7252 * We have to disable TSC offset matching.. if you were
7253 * booting a VM while issuing an S4 host suspend....
7254 * you may have some problem. Solving this issue is
7255 * left as an exercise to the reader.
7257 kvm->arch.last_tsc_nsec = 0;
7258 kvm->arch.last_tsc_write = 0;
7265 void kvm_arch_hardware_disable(void)
7267 kvm_x86_ops->hardware_disable();
7268 drop_user_return_notifiers();
7271 int kvm_arch_hardware_setup(void)
7275 r = kvm_x86_ops->hardware_setup();
7279 kvm_init_msr_list();
7283 void kvm_arch_hardware_unsetup(void)
7285 kvm_x86_ops->hardware_unsetup();
7288 void kvm_arch_check_processor_compat(void *rtn)
7290 kvm_x86_ops->check_processor_compatibility(rtn);
7293 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7295 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7298 struct static_key kvm_no_apic_vcpu __read_mostly;
7300 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7306 BUG_ON(vcpu->kvm == NULL);
7309 vcpu->arch.pv.pv_unhalted = false;
7310 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7311 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7312 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7314 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7316 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7321 vcpu->arch.pio_data = page_address(page);
7323 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7325 r = kvm_mmu_create(vcpu);
7327 goto fail_free_pio_data;
7329 if (irqchip_in_kernel(kvm)) {
7330 r = kvm_create_lapic(vcpu);
7332 goto fail_mmu_destroy;
7334 static_key_slow_inc(&kvm_no_apic_vcpu);
7336 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7338 if (!vcpu->arch.mce_banks) {
7340 goto fail_free_lapic;
7342 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7344 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7346 goto fail_free_mce_banks;
7351 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7352 vcpu->arch.pv_time_enabled = false;
7354 vcpu->arch.guest_supported_xcr0 = 0;
7355 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7357 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7359 kvm_async_pf_hash_reset(vcpu);
7364 fail_free_mce_banks:
7365 kfree(vcpu->arch.mce_banks);
7367 kvm_free_lapic(vcpu);
7369 kvm_mmu_destroy(vcpu);
7371 free_page((unsigned long)vcpu->arch.pio_data);
7376 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7380 kvm_pmu_destroy(vcpu);
7381 kfree(vcpu->arch.mce_banks);
7382 kvm_free_lapic(vcpu);
7383 idx = srcu_read_lock(&vcpu->kvm->srcu);
7384 kvm_mmu_destroy(vcpu);
7385 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7386 free_page((unsigned long)vcpu->arch.pio_data);
7387 if (!irqchip_in_kernel(vcpu->kvm))
7388 static_key_slow_dec(&kvm_no_apic_vcpu);
7391 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7393 kvm_x86_ops->sched_in(vcpu, cpu);
7396 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7401 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7402 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7403 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7404 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7405 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7407 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7408 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7409 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7410 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7411 &kvm->arch.irq_sources_bitmap);
7413 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7414 mutex_init(&kvm->arch.apic_map_lock);
7415 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7417 pvclock_update_vm_gtod_copy(kvm);
7419 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7420 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7425 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7428 r = vcpu_load(vcpu);
7430 kvm_mmu_unload(vcpu);
7434 static void kvm_free_vcpus(struct kvm *kvm)
7437 struct kvm_vcpu *vcpu;
7440 * Unpin any mmu pages first.
7442 kvm_for_each_vcpu(i, vcpu, kvm) {
7443 kvm_clear_async_pf_completion_queue(vcpu);
7444 kvm_unload_vcpu_mmu(vcpu);
7446 kvm_for_each_vcpu(i, vcpu, kvm)
7447 kvm_arch_vcpu_free(vcpu);
7449 mutex_lock(&kvm->lock);
7450 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7451 kvm->vcpus[i] = NULL;
7453 atomic_set(&kvm->online_vcpus, 0);
7454 mutex_unlock(&kvm->lock);
7457 void kvm_arch_sync_events(struct kvm *kvm)
7459 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7460 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7461 kvm_free_all_assigned_devices(kvm);
7465 void kvm_arch_destroy_vm(struct kvm *kvm)
7467 if (current->mm == kvm->mm) {
7469 * Free memory regions allocated on behalf of userspace,
7470 * unless the the memory map has changed due to process exit
7473 struct kvm_userspace_memory_region mem;
7474 memset(&mem, 0, sizeof(mem));
7475 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7476 kvm_set_memory_region(kvm, &mem);
7478 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7479 kvm_set_memory_region(kvm, &mem);
7481 mem.slot = TSS_PRIVATE_MEMSLOT;
7482 kvm_set_memory_region(kvm, &mem);
7484 kvm_iommu_unmap_guest(kvm);
7485 kfree(kvm->arch.vpic);
7486 kfree(kvm->arch.vioapic);
7487 kvm_free_vcpus(kvm);
7488 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7491 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7492 struct kvm_memory_slot *dont)
7496 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7497 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7498 kvfree(free->arch.rmap[i]);
7499 free->arch.rmap[i] = NULL;
7504 if (!dont || free->arch.lpage_info[i - 1] !=
7505 dont->arch.lpage_info[i - 1]) {
7506 kvfree(free->arch.lpage_info[i - 1]);
7507 free->arch.lpage_info[i - 1] = NULL;
7512 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7513 unsigned long npages)
7517 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7522 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7523 slot->base_gfn, level) + 1;
7525 slot->arch.rmap[i] =
7526 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7527 if (!slot->arch.rmap[i])
7532 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7533 sizeof(*slot->arch.lpage_info[i - 1]));
7534 if (!slot->arch.lpage_info[i - 1])
7537 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7538 slot->arch.lpage_info[i - 1][0].write_count = 1;
7539 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7540 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7541 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7543 * If the gfn and userspace address are not aligned wrt each
7544 * other, or if explicitly asked to, disable large page
7545 * support for this slot
7547 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7548 !kvm_largepages_enabled()) {
7551 for (j = 0; j < lpages; ++j)
7552 slot->arch.lpage_info[i - 1][j].write_count = 1;
7559 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7560 kvfree(slot->arch.rmap[i]);
7561 slot->arch.rmap[i] = NULL;
7565 kvfree(slot->arch.lpage_info[i - 1]);
7566 slot->arch.lpage_info[i - 1] = NULL;
7571 void kvm_arch_memslots_updated(struct kvm *kvm)
7574 * memslots->generation has been incremented.
7575 * mmio generation may have reached its maximum value.
7577 kvm_mmu_invalidate_mmio_sptes(kvm);
7580 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7581 struct kvm_memory_slot *memslot,
7582 struct kvm_userspace_memory_region *mem,
7583 enum kvm_mr_change change)
7586 * Only private memory slots need to be mapped here since
7587 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7589 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7590 unsigned long userspace_addr;
7593 * MAP_SHARED to prevent internal slot pages from being moved
7596 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7597 PROT_READ | PROT_WRITE,
7598 MAP_SHARED | MAP_ANONYMOUS, 0);
7600 if (IS_ERR((void *)userspace_addr))
7601 return PTR_ERR((void *)userspace_addr);
7603 memslot->userspace_addr = userspace_addr;
7609 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7610 struct kvm_memory_slot *new)
7612 /* Still write protect RO slot */
7613 if (new->flags & KVM_MEM_READONLY) {
7614 kvm_mmu_slot_remove_write_access(kvm, new);
7619 * Call kvm_x86_ops dirty logging hooks when they are valid.
7621 * kvm_x86_ops->slot_disable_log_dirty is called when:
7623 * - KVM_MR_CREATE with dirty logging is disabled
7624 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7626 * The reason is, in case of PML, we need to set D-bit for any slots
7627 * with dirty logging disabled in order to eliminate unnecessary GPA
7628 * logging in PML buffer (and potential PML buffer full VMEXT). This
7629 * guarantees leaving PML enabled during guest's lifetime won't have
7630 * any additonal overhead from PML when guest is running with dirty
7631 * logging disabled for memory slots.
7633 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7634 * to dirty logging mode.
7636 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7638 * In case of write protect:
7640 * Write protect all pages for dirty logging.
7642 * All the sptes including the large sptes which point to this
7643 * slot are set to readonly. We can not create any new large
7644 * spte on this slot until the end of the logging.
7646 * See the comments in fast_page_fault().
7648 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7649 if (kvm_x86_ops->slot_enable_log_dirty)
7650 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7652 kvm_mmu_slot_remove_write_access(kvm, new);
7654 if (kvm_x86_ops->slot_disable_log_dirty)
7655 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7659 void kvm_arch_commit_memory_region(struct kvm *kvm,
7660 struct kvm_userspace_memory_region *mem,
7661 const struct kvm_memory_slot *old,
7662 enum kvm_mr_change change)
7664 struct kvm_memory_slot *new;
7665 int nr_mmu_pages = 0;
7667 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7670 ret = vm_munmap(old->userspace_addr,
7671 old->npages * PAGE_SIZE);
7674 "kvm_vm_ioctl_set_memory_region: "
7675 "failed to munmap memory\n");
7678 if (!kvm->arch.n_requested_mmu_pages)
7679 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7682 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7684 /* It's OK to get 'new' slot here as it has already been installed */
7685 new = id_to_memslot(kvm->memslots, mem->slot);
7688 * Dirty logging tracks sptes in 4k granularity, meaning that large
7689 * sptes have to be split. If live migration is successful, the guest
7690 * in the source machine will be destroyed and large sptes will be
7691 * created in the destination. However, if the guest continues to run
7692 * in the source machine (for example if live migration fails), small
7693 * sptes will remain around and cause bad performance.
7695 * Scan sptes if dirty logging has been stopped, dropping those
7696 * which can be collapsed into a single large-page spte. Later
7697 * page faults will create the large-page sptes.
7699 if ((change != KVM_MR_DELETE) &&
7700 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7701 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7702 kvm_mmu_zap_collapsible_sptes(kvm, new);
7705 * Set up write protection and/or dirty logging for the new slot.
7707 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7708 * been zapped so no dirty logging staff is needed for old slot. For
7709 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7710 * new and it's also covered when dealing with the new slot.
7712 if (change != KVM_MR_DELETE)
7713 kvm_mmu_slot_apply_flags(kvm, new);
7716 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7718 kvm_mmu_invalidate_zap_all_pages(kvm);
7721 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7722 struct kvm_memory_slot *slot)
7724 kvm_mmu_invalidate_zap_all_pages(kvm);
7727 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7729 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7730 kvm_x86_ops->check_nested_events(vcpu, false);
7732 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7733 !vcpu->arch.apf.halted)
7734 || !list_empty_careful(&vcpu->async_pf.done)
7735 || kvm_apic_has_events(vcpu)
7736 || vcpu->arch.pv.pv_unhalted
7737 || atomic_read(&vcpu->arch.nmi_queued) ||
7738 (kvm_arch_interrupt_allowed(vcpu) &&
7739 kvm_cpu_has_interrupt(vcpu));
7742 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7744 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7747 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7749 return kvm_x86_ops->interrupt_allowed(vcpu);
7752 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
7754 if (is_64_bit_mode(vcpu))
7755 return kvm_rip_read(vcpu);
7756 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7757 kvm_rip_read(vcpu));
7759 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
7761 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7763 return kvm_get_linear_rip(vcpu) == linear_rip;
7765 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7767 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7769 unsigned long rflags;
7771 rflags = kvm_x86_ops->get_rflags(vcpu);
7772 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7773 rflags &= ~X86_EFLAGS_TF;
7776 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7778 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7780 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7781 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7782 rflags |= X86_EFLAGS_TF;
7783 kvm_x86_ops->set_rflags(vcpu, rflags);
7786 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7788 __kvm_set_rflags(vcpu, rflags);
7789 kvm_make_request(KVM_REQ_EVENT, vcpu);
7791 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7793 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7797 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7801 r = kvm_mmu_reload(vcpu);
7805 if (!vcpu->arch.mmu.direct_map &&
7806 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7809 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7812 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7814 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7817 static inline u32 kvm_async_pf_next_probe(u32 key)
7819 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7822 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7824 u32 key = kvm_async_pf_hash_fn(gfn);
7826 while (vcpu->arch.apf.gfns[key] != ~0)
7827 key = kvm_async_pf_next_probe(key);
7829 vcpu->arch.apf.gfns[key] = gfn;
7832 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7835 u32 key = kvm_async_pf_hash_fn(gfn);
7837 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7838 (vcpu->arch.apf.gfns[key] != gfn &&
7839 vcpu->arch.apf.gfns[key] != ~0); i++)
7840 key = kvm_async_pf_next_probe(key);
7845 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7847 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7850 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7854 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7856 vcpu->arch.apf.gfns[i] = ~0;
7858 j = kvm_async_pf_next_probe(j);
7859 if (vcpu->arch.apf.gfns[j] == ~0)
7861 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7863 * k lies cyclically in ]i,j]
7865 * |....j i.k.| or |.k..j i...|
7867 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7868 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7873 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7876 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7880 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7881 struct kvm_async_pf *work)
7883 struct x86_exception fault;
7885 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7886 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7888 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7889 (vcpu->arch.apf.send_user_only &&
7890 kvm_x86_ops->get_cpl(vcpu) == 0))
7891 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7892 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7893 fault.vector = PF_VECTOR;
7894 fault.error_code_valid = true;
7895 fault.error_code = 0;
7896 fault.nested_page_fault = false;
7897 fault.address = work->arch.token;
7898 kvm_inject_page_fault(vcpu, &fault);
7902 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7903 struct kvm_async_pf *work)
7905 struct x86_exception fault;
7907 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7908 if (work->wakeup_all)
7909 work->arch.token = ~0; /* broadcast wakeup */
7911 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7913 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7914 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7915 fault.vector = PF_VECTOR;
7916 fault.error_code_valid = true;
7917 fault.error_code = 0;
7918 fault.nested_page_fault = false;
7919 fault.address = work->arch.token;
7920 kvm_inject_page_fault(vcpu, &fault);
7922 vcpu->arch.apf.halted = false;
7923 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7926 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7928 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7931 return !kvm_event_needs_reinjection(vcpu) &&
7932 kvm_x86_ops->interrupt_allowed(vcpu);
7935 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7937 atomic_inc(&kvm->arch.noncoherent_dma_count);
7939 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7941 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7943 atomic_dec(&kvm->arch.noncoherent_dma_count);
7945 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7947 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7949 return atomic_read(&kvm->arch.noncoherent_dma_count);
7951 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7953 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7954 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7955 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7956 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7957 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7958 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7959 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7960 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7961 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7962 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7963 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7964 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7965 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7966 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
7967 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);