arch/x86/kvm/x86_emulate.c

   1 /******************************************************************************
   2  * x86_emulate.c
   3  *
   4  * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
   5  *
   6  * Copyright (c) 2005 Keir Fraser
   7  *
   8  * Linux coding style, mod r/m decoder, segment base fixes, real-mode
   9  * privileged instructions:
  10  *
  11  * Copyright (C) 2006 Qumranet
  12  *
  13  *   Avi Kivity <avi@qumranet.com>
  14  *   Yaniv Kamay <yaniv@qumranet.com>
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  *
  19  * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
  20  */
  21
  22 #ifndef __KERNEL__
  23 #include <stdio.h>
  24 #include <stdint.h>
  25 #include <public/xen.h>
  26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
  27 #else
  28 #include <linux/kvm_host.h>
  29 #define DPRINTF(x...) do {} while (0)
  30 #endif
  31 #include <linux/module.h>
  32 #include <asm/kvm_x86_emulate.h>
  33
  34 /*
  35  * Opcode effective-address decode tables.
  36  * Note that we only emulate instructions that have at least one memory
  37  * operand (excluding implicit stack references). We assume that stack
  38  * references and instruction fetches will never occur in special memory
  39  * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
  40  * not be handled.
  41  */
  42
  43 /* Operand sizes: 8-bit operands or specified/overridden size. */
  44 #define ByteOp      (1<<0)      /* 8-bit operands. */
  45 /* Destination operand type. */
  46 #define ImplicitOps (1<<1)      /* Implicit in opcode. No generic decode. */
  47 #define DstReg      (2<<1)      /* Register operand. */
  48 #define DstMem      (3<<1)      /* Memory operand. */
  49 #define DstMask     (3<<1)
  50 /* Source operand type. */
  51 #define SrcNone     (0<<3)      /* No source operand. */
  52 #define SrcImplicit (0<<3)      /* Source operand is implicit in the opcode. */
  53 #define SrcReg      (1<<3)      /* Register operand. */
  54 #define SrcMem      (2<<3)      /* Memory operand. */
  55 #define SrcMem16    (3<<3)      /* Memory operand (16-bit). */
  56 #define SrcMem32    (4<<3)      /* Memory operand (32-bit). */
  57 #define SrcImm      (5<<3)      /* Immediate operand. */
  58 #define SrcImmByte  (6<<3)      /* 8-bit sign-extended immediate operand. */
  59 #define SrcMask     (7<<3)
  60 /* Generic ModRM decode. */
  61 #define ModRM       (1<<6)
  62 /* Destination is only written; never read. */
  63 #define Mov         (1<<7)
  64 #define BitOp       (1<<8)
  65 #define MemAbs      (1<<9)      /* Memory operand is absolute displacement */
  66 #define String      (1<<10)     /* String instruction (rep capable) */
  67 #define Stack       (1<<11)     /* Stack instruction (push/pop) */
  68 #define Group       (1<<14)     /* Bits 3:5 of modrm byte extend opcode */
  69 #define GroupDual   (1<<15)     /* Alternate decoding of mod == 3 */
  70 #define GroupMask   0xff        /* Group number stored in bits 0:7 */
  71
  72 enum {
  73         Group1A, Group3_Byte, Group3,
  74 };
  75
  76 static u16 opcode_table[256] = {
  77         /* 0x00 - 0x07 */
  78         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  79         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  80         0, 0, 0, 0,
  81         /* 0x08 - 0x0F */
  82         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  83         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  84         0, 0, 0, 0,
  85         /* 0x10 - 0x17 */
  86         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  87         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  88         0, 0, 0, 0,
  89         /* 0x18 - 0x1F */
  90         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  91         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  92         0, 0, 0, 0,
  93         /* 0x20 - 0x27 */
  94         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  95         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
  96         SrcImmByte, SrcImm, 0, 0,
  97         /* 0x28 - 0x2F */
  98         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
  99         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
 100         0, 0, 0, 0,
 101         /* 0x30 - 0x37 */
 102         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
 103         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
 104         0, 0, 0, 0,
 105         /* 0x38 - 0x3F */
 106         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
 107         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
 108         0, 0, 0, 0,
 109         /* 0x40 - 0x47 */
 110         DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
 111         /* 0x48 - 0x4F */
 112         DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
 113         /* 0x50 - 0x57 */
 114         SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
 115         SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
 116         /* 0x58 - 0x5F */
 117         DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
 118         DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
 119         /* 0x60 - 0x67 */
 120         0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
 121         0, 0, 0, 0,
 122         /* 0x68 - 0x6F */
 123         0, 0, ImplicitOps | Mov | Stack, 0,
 124         SrcNone  | ByteOp  | ImplicitOps, SrcNone  | ImplicitOps, /* insb, insw/insd */
 125         SrcNone  | ByteOp  | ImplicitOps, SrcNone  | ImplicitOps, /* outsb, outsw/outsd */
 126         /* 0x70 - 0x77 */
 127         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 128         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 129         /* 0x78 - 0x7F */
 130         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 131         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 132         /* 0x80 - 0x87 */
 133         ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
 134         ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
 135         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
 136         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
 137         /* 0x88 - 0x8F */
 138         ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
 139         ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 140         0, ModRM | DstReg, 0, Group | Group1A,
 141         /* 0x90 - 0x9F */
 142         0, 0, 0, 0, 0, 0, 0, 0,
 143         0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
 144         /* 0xA0 - 0xA7 */
 145         ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
 146         ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
 147         ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
 148         ByteOp | ImplicitOps | String, ImplicitOps | String,
 149         /* 0xA8 - 0xAF */
 150         0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
 151         ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
 152         ByteOp | ImplicitOps | String, ImplicitOps | String,
 153         /* 0xB0 - 0xBF */
 154         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 155         /* 0xC0 - 0xC7 */
 156         ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
 157         0, ImplicitOps | Stack, 0, 0,
 158         ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
 159         /* 0xC8 - 0xCF */
 160         0, 0, 0, 0, 0, 0, 0, 0,
 161         /* 0xD0 - 0xD7 */
 162         ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
 163         ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
 164         0, 0, 0, 0,
 165         /* 0xD8 - 0xDF */
 166         0, 0, 0, 0, 0, 0, 0, 0,
 167         /* 0xE0 - 0xE7 */
 168         0, 0, 0, 0, 0, 0, 0, 0,
 169         /* 0xE8 - 0xEF */
 170         ImplicitOps | Stack, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps,
 171         0, 0, 0, 0,
 172         /* 0xF0 - 0xF7 */
 173         0, 0, 0, 0,
 174         ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
 175         /* 0xF8 - 0xFF */
 176         ImplicitOps, 0, ImplicitOps, ImplicitOps,
 177         0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
 178 };
 179
 180 static u16 twobyte_table[256] = {
 181         /* 0x00 - 0x0F */
 182         0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
 183         ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
 184         /* 0x10 - 0x1F */
 185         0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
 186         /* 0x20 - 0x2F */
 187         ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
 188         0, 0, 0, 0, 0, 0, 0, 0,
 189         /* 0x30 - 0x3F */
 190         ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 191         /* 0x40 - 0x47 */
 192         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 193         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 194         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 195         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 196         /* 0x48 - 0x4F */
 197         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 198         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 199         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 200         DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
 201         /* 0x50 - 0x5F */
 202         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 203         /* 0x60 - 0x6F */
 204         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 205         /* 0x70 - 0x7F */
 206         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 207         /* 0x80 - 0x8F */
 208         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 209         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 210         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 211         ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
 212         /* 0x90 - 0x9F */
 213         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 214         /* 0xA0 - 0xA7 */
 215         0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
 216         /* 0xA8 - 0xAF */
 217         0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
 218         /* 0xB0 - 0xB7 */
 219         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
 220             DstMem | SrcReg | ModRM | BitOp,
 221         0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
 222             DstReg | SrcMem16 | ModRM | Mov,
 223         /* 0xB8 - 0xBF */
 224         0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
 225         0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
 226             DstReg | SrcMem16 | ModRM | Mov,
 227         /* 0xC0 - 0xCF */
 228         0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
 229         0, 0, 0, 0, 0, 0, 0, 0,
 230         /* 0xD0 - 0xDF */
 231         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 232         /* 0xE0 - 0xEF */
 233         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 234         /* 0xF0 - 0xFF */
 235         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 236 };
 237
 238 static u16 group_table[] = {
 239         [Group1A*8] =
 240         DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
 241         [Group3_Byte*8] =
 242         ByteOp | SrcImm | DstMem | ModRM, 0,
 243         ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
 244         0, 0, 0, 0,
 245         [Group3*8] =
 246         DstMem | SrcImm | ModRM | SrcImm, 0,
 247         DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
 248         0, 0, 0, 0,
 249 };
 250
 251 static u16 group2_table[] = {
 252 };
 253
 254 /* EFLAGS bit definitions. */
 255 #define EFLG_OF (1<<11)
 256 #define EFLG_DF (1<<10)
 257 #define EFLG_SF (1<<7)
 258 #define EFLG_ZF (1<<6)
 259 #define EFLG_AF (1<<4)
 260 #define EFLG_PF (1<<2)
 261 #define EFLG_CF (1<<0)
 262
 263 /*
 264  * Instruction emulation:
 265  * Most instructions are emulated directly via a fragment of inline assembly
 266  * code. This allows us to save/restore EFLAGS and thus very easily pick up
 267  * any modified flags.
 268  */
 269
 270 #if defined(CONFIG_X86_64)
 271 #define _LO32 "k"               /* force 32-bit operand */
 272 #define _STK  "%%rsp"           /* stack pointer */
 273 #elif defined(__i386__)
 274 #define _LO32 ""                /* force 32-bit operand */
 275 #define _STK  "%%esp"           /* stack pointer */
 276 #endif
 277
 278 /*
 279  * These EFLAGS bits are restored from saved value during emulation, and
 280  * any changes are written back to the saved value after emulation.
 281  */
 282 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
 283
 284 /* Before executing instruction: restore necessary bits in EFLAGS. */
 285 #define _PRE_EFLAGS(_sav, _msk, _tmp)                                   \
 286         /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
 287         "movl %"_sav",%"_LO32 _tmp"; "                                  \
 288         "push %"_tmp"; "                                                \
 289         "push %"_tmp"; "                                                \
 290         "movl %"_msk",%"_LO32 _tmp"; "                                  \
 291         "andl %"_LO32 _tmp",("_STK"); "                                 \
 292         "pushf; "                                                       \
 293         "notl %"_LO32 _tmp"; "                                          \
 294         "andl %"_LO32 _tmp",("_STK"); "                                 \
 295         "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); "   \
 296         "pop  %"_tmp"; "                                                \
 297         "orl  %"_LO32 _tmp",("_STK"); "                                 \
 298         "popf; "                                                        \
 299         "pop  %"_sav"; "
 300
 301 /* After executing instruction: write-back necessary bits in EFLAGS. */
 302 #define _POST_EFLAGS(_sav, _msk, _tmp) \
 303         /* _sav |= EFLAGS & _msk; */            \
 304         "pushf; "                               \
 305         "pop  %"_tmp"; "                        \
 306         "andl %"_msk",%"_LO32 _tmp"; "          \
 307         "orl  %"_LO32 _tmp",%"_sav"; "
 308
 309 /* Raw emulation: instruction has two explicit operands. */
 310 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
 311         do {                                                                \
 312                 unsigned long _tmp;                                         \
 313                                                                             \
 314                 switch ((_dst).bytes) {                                     \
 315                 case 2:                                                     \
 316                         __asm__ __volatile__ (                              \
 317                                 _PRE_EFLAGS("0", "4", "2")                  \
 318                                 _op"w %"_wx"3,%1; "                         \
 319                                 _POST_EFLAGS("0", "4", "2")                 \
 320                                 : "=m" (_eflags), "=m" ((_dst).val),        \
 321                                   "=&r" (_tmp)                              \
 322                                 : _wy ((_src).val), "i" (EFLAGS_MASK));     \
 323                         break;                                              \
 324                 case 4:                                                     \
 325                         __asm__ __volatile__ (                              \
 326                                 _PRE_EFLAGS("0", "4", "2")                  \
 327                                 _op"l %"_lx"3,%1; "                         \
 328                                 _POST_EFLAGS("0", "4", "2")                 \
 329                                 : "=m" (_eflags), "=m" ((_dst).val),        \
 330                                   "=&r" (_tmp)                              \
 331                                 : _ly ((_src).val), "i" (EFLAGS_MASK));     \
 332                         break;                                              \
 333                 case 8:                                                     \
 334                         __emulate_2op_8byte(_op, _src, _dst,                \
 335                                             _eflags, _qx, _qy);             \
 336                         break;                                              \
 337                 }                                                           \
 338         } while (0)
 339
 340 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
 341         do {                                                                 \
 342                 unsigned long _tmp;                                          \
 343                 switch ((_dst).bytes) {                                      \
 344                 case 1:                                                      \
 345                         __asm__ __volatile__ (                               \
 346                                 _PRE_EFLAGS("0", "4", "2")                   \
 347                                 _op"b %"_bx"3,%1; "                          \
 348                                 _POST_EFLAGS("0", "4", "2")                  \
 349                                 : "=m" (_eflags), "=m" ((_dst).val),         \
 350                                   "=&r" (_tmp)                               \
 351                                 : _by ((_src).val), "i" (EFLAGS_MASK));      \
 352                         break;                                               \
 353                 default:                                                     \
 354                         __emulate_2op_nobyte(_op, _src, _dst, _eflags,       \
 355                                              _wx, _wy, _lx, _ly, _qx, _qy);  \
 356                         break;                                               \
 357                 }                                                            \
 358         } while (0)
 359
 360 /* Source operand is byte-sized and may be restricted to just %cl. */
 361 #define emulate_2op_SrcB(_op, _src, _dst, _eflags)                      \
 362         __emulate_2op(_op, _src, _dst, _eflags,                         \
 363                       "b", "c", "b", "c", "b", "c", "b", "c")
 364
 365 /* Source operand is byte, word, long or quad sized. */
 366 #define emulate_2op_SrcV(_op, _src, _dst, _eflags)                      \
 367         __emulate_2op(_op, _src, _dst, _eflags,                         \
 368                       "b", "q", "w", "r", _LO32, "r", "", "r")
 369
 370 /* Source operand is word, long or quad sized. */
 371 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags)               \
 372         __emulate_2op_nobyte(_op, _src, _dst, _eflags,                  \
 373                              "w", "r", _LO32, "r", "", "r")
 374
 375 /* Instruction has only one explicit operand (no source operand). */
 376 #define emulate_1op(_op, _dst, _eflags)                                    \
 377         do {                                                            \
 378                 unsigned long _tmp;                                     \
 379                                                                         \
 380                 switch ((_dst).bytes) {                                 \
 381                 case 1:                                                 \
 382                         __asm__ __volatile__ (                          \
 383                                 _PRE_EFLAGS("0", "3", "2")              \
 384                                 _op"b %1; "                             \
 385                                 _POST_EFLAGS("0", "3", "2")             \
 386                                 : "=m" (_eflags), "=m" ((_dst).val),    \
 387                                   "=&r" (_tmp)                          \
 388                                 : "i" (EFLAGS_MASK));                   \
 389                         break;                                          \
 390                 case 2:                                                 \
 391                         __asm__ __volatile__ (                          \
 392                                 _PRE_EFLAGS("0", "3", "2")              \
 393                                 _op"w %1; "                             \
 394                                 _POST_EFLAGS("0", "3", "2")             \
 395                                 : "=m" (_eflags), "=m" ((_dst).val),    \
 396                                   "=&r" (_tmp)                          \
 397                                 : "i" (EFLAGS_MASK));                   \
 398                         break;                                          \
 399                 case 4:                                                 \
 400                         __asm__ __volatile__ (                          \
 401                                 _PRE_EFLAGS("0", "3", "2")              \
 402                                 _op"l %1; "                             \
 403                                 _POST_EFLAGS("0", "3", "2")             \
 404                                 : "=m" (_eflags), "=m" ((_dst).val),    \
 405                                   "=&r" (_tmp)                          \
 406                                 : "i" (EFLAGS_MASK));                   \
 407                         break;                                          \
 408                 case 8:                                                 \
 409                         __emulate_1op_8byte(_op, _dst, _eflags);        \
 410                         break;                                          \
 411                 }                                                       \
 412         } while (0)
 413
 414 /* Emulate an instruction with quadword operands (x86/64 only). */
 415 #if defined(CONFIG_X86_64)
 416 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)           \
 417         do {                                                              \
 418                 __asm__ __volatile__ (                                    \
 419                         _PRE_EFLAGS("0", "4", "2")                        \
 420                         _op"q %"_qx"3,%1; "                               \
 421                         _POST_EFLAGS("0", "4", "2")                       \
 422                         : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
 423                         : _qy ((_src).val), "i" (EFLAGS_MASK));         \
 424         } while (0)
 425
 426 #define __emulate_1op_8byte(_op, _dst, _eflags)                           \
 427         do {                                                              \
 428                 __asm__ __volatile__ (                                    \
 429                         _PRE_EFLAGS("0", "3", "2")                        \
 430                         _op"q %1; "                                       \
 431                         _POST_EFLAGS("0", "3", "2")                       \
 432                         : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
 433                         : "i" (EFLAGS_MASK));                             \
 434         } while (0)
 435
 436 #elif defined(__i386__)
 437 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
 438 #define __emulate_1op_8byte(_op, _dst, _eflags)
 439 #endif                          /* __i386__ */
 440
 441 /* Fetch next part of the instruction being emulated. */
 442 #define insn_fetch(_type, _size, _eip)                                  \
 443 ({      unsigned long _x;                                               \
 444         rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size));            \
 445         if (rc != 0)                                                    \
 446                 goto done;                                              \
 447         (_eip) += (_size);                                              \
 448         (_type)_x;                                                      \
 449 })
 450
 451 /* Access/update address held in a register, based on addressing mode. */
 452 #define address_mask(reg)                                               \
 453         ((c->ad_bytes == sizeof(unsigned long)) ?                       \
 454                 (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1)))
 455 #define register_address(base, reg)                                     \
 456         ((base) + address_mask(reg))
 457 #define register_address_increment(reg, inc)                            \
 458         do {                                                            \
 459                 /* signed type ensures sign extension to long */        \
 460                 int _inc = (inc);                                       \
 461                 if (c->ad_bytes == sizeof(unsigned long))               \
 462                         (reg) += _inc;                                  \
 463                 else                                                    \
 464                         (reg) = ((reg) &                                \
 465                                  ~((1UL << (c->ad_bytes << 3)) - 1)) |  \
 466                                 (((reg) + _inc) &                       \
 467                                  ((1UL << (c->ad_bytes << 3)) - 1));    \
 468         } while (0)
 469
 470 #define JMP_REL(rel)                                                    \
 471         do {                                                            \
 472                 register_address_increment(c->eip, rel);                \
 473         } while (0)
 474
 475 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
 476                               struct x86_emulate_ops *ops,
 477                               unsigned long linear, u8 *dest)
 478 {
 479         struct fetch_cache *fc = &ctxt->decode.fetch;
 480         int rc;
 481         int size;
 482
 483         if (linear < fc->start || linear >= fc->end) {
 484                 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
 485                 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
 486                 if (rc)
 487                         return rc;
 488                 fc->start = linear;
 489                 fc->end = linear + size;
 490         }
 491         *dest = fc->data[linear - fc->start];
 492         return 0;
 493 }
 494
 495 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
 496                          struct x86_emulate_ops *ops,
 497                          unsigned long eip, void *dest, unsigned size)
 498 {
 499         int rc = 0;
 500
 501         eip += ctxt->cs_base;
 502         while (size--) {
 503                 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
 504                 if (rc)
 505                         return rc;
 506         }
 507         return 0;
 508 }
 509
 510 /*
 511  * Given the 'reg' portion of a ModRM byte, and a register block, return a
 512  * pointer into the block that addresses the relevant register.
 513  * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 514  */
 515 static void *decode_register(u8 modrm_reg, unsigned long *regs,
 516                              int highbyte_regs)
 517 {
 518         void *p;
 519
 520         p = &regs[modrm_reg];
 521         if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
 522                 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
 523         return p;
 524 }
 525
 526 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
 527                            struct x86_emulate_ops *ops,
 528                            void *ptr,
 529                            u16 *size, unsigned long *address, int op_bytes)
 530 {
 531         int rc;
 532
 533         if (op_bytes == 2)
 534                 op_bytes = 3;
 535         *address = 0;
 536         rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
 537                            ctxt->vcpu);
 538         if (rc)
 539                 return rc;
 540         rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
 541                            ctxt->vcpu);
 542         return rc;
 543 }
 544
 545 static int test_cc(unsigned int condition, unsigned int flags)
 546 {
 547         int rc = 0;
 548
 549         switch ((condition & 15) >> 1) {
 550         case 0: /* o */
 551                 rc |= (flags & EFLG_OF);
 552                 break;
 553         case 1: /* b/c/nae */
 554                 rc |= (flags & EFLG_CF);
 555                 break;
 556         case 2: /* z/e */
 557                 rc |= (flags & EFLG_ZF);
 558                 break;
 559         case 3: /* be/na */
 560                 rc |= (flags & (EFLG_CF|EFLG_ZF));
 561                 break;
 562         case 4: /* s */
 563                 rc |= (flags & EFLG_SF);
 564                 break;
 565         case 5: /* p/pe */
 566                 rc |= (flags & EFLG_PF);
 567                 break;
 568         case 7: /* le/ng */
 569                 rc |= (flags & EFLG_ZF);
 570                 /* fall through */
 571         case 6: /* l/nge */
 572                 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
 573                 break;
 574         }
 575
 576         /* Odd condition identifiers (lsb == 1) have inverted sense. */
 577         return (!!rc ^ (condition & 1));
 578 }
 579
 580 static void decode_register_operand(struct operand *op,
 581                                     struct decode_cache *c,
 582                                     int inhibit_bytereg)
 583 {
 584         unsigned reg = c->modrm_reg;
 585         int highbyte_regs = c->rex_prefix == 0;
 586
 587         if (!(c->d & ModRM))
 588                 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
 589         op->type = OP_REG;
 590         if ((c->d & ByteOp) && !inhibit_bytereg) {
 591                 op->ptr = decode_register(reg, c->regs, highbyte_regs);
 592                 op->val = *(u8 *)op->ptr;
 593                 op->bytes = 1;
 594         } else {
 595                 op->ptr = decode_register(reg, c->regs, 0);
 596                 op->bytes = c->op_bytes;
 597                 switch (op->bytes) {
 598                 case 2:
 599                         op->val = *(u16 *)op->ptr;
 600                         break;
 601                 case 4:
 602                         op->val = *(u32 *)op->ptr;
 603                         break;
 604                 case 8:
 605                         op->val = *(u64 *) op->ptr;
 606                         break;
 607                 }
 608         }
 609         op->orig_val = op->val;
 610 }
 611
 612 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
 613                         struct x86_emulate_ops *ops)
 614 {
 615         struct decode_cache *c = &ctxt->decode;
 616         u8 sib;
 617         int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
 618         int rc = 0;
 619
 620         if (c->rex_prefix) {
 621                 c->modrm_reg = (c->rex_prefix & 4) << 1;        /* REX.R */
 622                 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
 623                 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
 624         }
 625
 626         c->modrm = insn_fetch(u8, 1, c->eip);
 627         c->modrm_mod |= (c->modrm & 0xc0) >> 6;
 628         c->modrm_reg |= (c->modrm & 0x38) >> 3;
 629         c->modrm_rm |= (c->modrm & 0x07);
 630         c->modrm_ea = 0;
 631         c->use_modrm_ea = 1;
 632
 633         if (c->modrm_mod == 3) {
 634                 c->modrm_val = *(unsigned long *)
 635                         decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
 636                 return rc;
 637         }
 638
 639         if (c->ad_bytes == 2) {
 640                 unsigned bx = c->regs[VCPU_REGS_RBX];
 641                 unsigned bp = c->regs[VCPU_REGS_RBP];
 642                 unsigned si = c->regs[VCPU_REGS_RSI];
 643                 unsigned di = c->regs[VCPU_REGS_RDI];
 644
 645                 /* 16-bit ModR/M decode. */
 646                 switch (c->modrm_mod) {
 647                 case 0:
 648                         if (c->modrm_rm == 6)
 649                                 c->modrm_ea += insn_fetch(u16, 2, c->eip);
 650                         break;
 651                 case 1:
 652                         c->modrm_ea += insn_fetch(s8, 1, c->eip);
 653                         break;
 654                 case 2:
 655                         c->modrm_ea += insn_fetch(u16, 2, c->eip);
 656                         break;
 657                 }
 658                 switch (c->modrm_rm) {
 659                 case 0:
 660                         c->modrm_ea += bx + si;
 661                         break;
 662                 case 1:
 663                         c->modrm_ea += bx + di;
 664                         break;
 665                 case 2:
 666                         c->modrm_ea += bp + si;
 667                         break;
 668                 case 3:
 669                         c->modrm_ea += bp + di;
 670                         break;
 671                 case 4:
 672                         c->modrm_ea += si;
 673                         break;
 674                 case 5:
 675                         c->modrm_ea += di;
 676                         break;
 677                 case 6:
 678                         if (c->modrm_mod != 0)
 679                                 c->modrm_ea += bp;
 680                         break;
 681                 case 7:
 682                         c->modrm_ea += bx;
 683                         break;
 684                 }
 685                 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
 686                     (c->modrm_rm == 6 && c->modrm_mod != 0))
 687                         if (!c->override_base)
 688                                 c->override_base = &ctxt->ss_base;
 689                 c->modrm_ea = (u16)c->modrm_ea;
 690         } else {
 691                 /* 32/64-bit ModR/M decode. */
 692                 switch (c->modrm_rm) {
 693                 case 4:
 694                 case 12:
 695                         sib = insn_fetch(u8, 1, c->eip);
 696                         index_reg |= (sib >> 3) & 7;
 697                         base_reg |= sib & 7;
 698                         scale = sib >> 6;
 699
 700                         switch (base_reg) {
 701                         case 5:
 702                                 if (c->modrm_mod != 0)
 703                                         c->modrm_ea += c->regs[base_reg];
 704                                 else
 705                                         c->modrm_ea +=
 706                                                 insn_fetch(s32, 4, c->eip);
 707                                 break;
 708                         default:
 709                                 c->modrm_ea += c->regs[base_reg];
 710                         }
 711                         switch (index_reg) {
 712                         case 4:
 713                                 break;
 714                         default:
 715                                 c->modrm_ea += c->regs[index_reg] << scale;
 716                         }
 717                         break;
 718                 case 5:
 719                         if (c->modrm_mod != 0)
 720                                 c->modrm_ea += c->regs[c->modrm_rm];
 721                         else if (ctxt->mode == X86EMUL_MODE_PROT64)
 722                                 rip_relative = 1;
 723                         break;
 724                 default:
 725                         c->modrm_ea += c->regs[c->modrm_rm];
 726                         break;
 727                 }
 728                 switch (c->modrm_mod) {
 729                 case 0:
 730                         if (c->modrm_rm == 5)
 731                                 c->modrm_ea += insn_fetch(s32, 4, c->eip);
 732                         break;
 733                 case 1:
 734                         c->modrm_ea += insn_fetch(s8, 1, c->eip);
 735                         break;
 736                 case 2:
 737                         c->modrm_ea += insn_fetch(s32, 4, c->eip);
 738                         break;
 739                 }
 740         }
 741         if (rip_relative) {
 742                 c->modrm_ea += c->eip;
 743                 switch (c->d & SrcMask) {
 744                 case SrcImmByte:
 745                         c->modrm_ea += 1;
 746                         break;
 747                 case SrcImm:
 748                         if (c->d & ByteOp)
 749                                 c->modrm_ea += 1;
 750                         else
 751                                 if (c->op_bytes == 8)
 752                                         c->modrm_ea += 4;
 753                                 else
 754                                         c->modrm_ea += c->op_bytes;
 755                 }
 756         }
 757 done:
 758         return rc;
 759 }
 760
 761 static int decode_abs(struct x86_emulate_ctxt *ctxt,
 762                       struct x86_emulate_ops *ops)
 763 {
 764         struct decode_cache *c = &ctxt->decode;
 765         int rc = 0;
 766
 767         switch (c->ad_bytes) {
 768         case 2:
 769                 c->modrm_ea = insn_fetch(u16, 2, c->eip);
 770                 break;
 771         case 4:
 772                 c->modrm_ea = insn_fetch(u32, 4, c->eip);
 773                 break;
 774         case 8:
 775                 c->modrm_ea = insn_fetch(u64, 8, c->eip);
 776                 break;
 777         }
 778 done:
 779         return rc;
 780 }
 781
 782 int
 783 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
 784 {
 785         struct decode_cache *c = &ctxt->decode;
 786         int rc = 0;
 787         int mode = ctxt->mode;
 788         int def_op_bytes, def_ad_bytes, group;
 789
 790         /* Shadow copy of register state. Committed on successful emulation. */
 791
 792         memset(c, 0, sizeof(struct decode_cache));
 793         c->eip = ctxt->vcpu->arch.rip;
 794         memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
 795
 796         switch (mode) {
 797         case X86EMUL_MODE_REAL:
 798         case X86EMUL_MODE_PROT16:
 799                 def_op_bytes = def_ad_bytes = 2;
 800                 break;
 801         case X86EMUL_MODE_PROT32:
 802                 def_op_bytes = def_ad_bytes = 4;
 803                 break;
 804 #ifdef CONFIG_X86_64
 805         case X86EMUL_MODE_PROT64:
 806                 def_op_bytes = 4;
 807                 def_ad_bytes = 8;
 808                 break;
 809 #endif
 810         default:
 811                 return -1;
 812         }
 813
 814         c->op_bytes = def_op_bytes;
 815         c->ad_bytes = def_ad_bytes;
 816
 817         /* Legacy prefixes. */
 818         for (;;) {
 819                 switch (c->b = insn_fetch(u8, 1, c->eip)) {
 820                 case 0x66:      /* operand-size override */
 821                         /* switch between 2/4 bytes */
 822                         c->op_bytes = def_op_bytes ^ 6;
 823                         break;
 824                 case 0x67:      /* address-size override */
 825                         if (mode == X86EMUL_MODE_PROT64)
 826                                 /* switch between 4/8 bytes */
 827                                 c->ad_bytes = def_ad_bytes ^ 12;
 828                         else
 829                                 /* switch between 2/4 bytes */
 830                                 c->ad_bytes = def_ad_bytes ^ 6;
 831                         break;
 832                 case 0x2e:      /* CS override */
 833                         c->override_base = &ctxt->cs_base;
 834                         break;
 835                 case 0x3e:      /* DS override */
 836                         c->override_base = &ctxt->ds_base;
 837                         break;
 838                 case 0x26:      /* ES override */
 839                         c->override_base = &ctxt->es_base;
 840                         break;
 841                 case 0x64:      /* FS override */
 842                         c->override_base = &ctxt->fs_base;
 843                         break;
 844                 case 0x65:      /* GS override */
 845                         c->override_base = &ctxt->gs_base;
 846                         break;
 847                 case 0x36:      /* SS override */
 848                         c->override_base = &ctxt->ss_base;
 849                         break;
 850                 case 0x40 ... 0x4f: /* REX */
 851                         if (mode != X86EMUL_MODE_PROT64)
 852                                 goto done_prefixes;
 853                         c->rex_prefix = c->b;
 854                         continue;
 855                 case 0xf0:      /* LOCK */
 856                         c->lock_prefix = 1;
 857                         break;
 858                 case 0xf2:      /* REPNE/REPNZ */
 859                         c->rep_prefix = REPNE_PREFIX;
 860                         break;
 861                 case 0xf3:      /* REP/REPE/REPZ */
 862                         c->rep_prefix = REPE_PREFIX;
 863                         break;
 864                 default:
 865                         goto done_prefixes;
 866                 }
 867
 868                 /* Any legacy prefix after a REX prefix nullifies its effect. */
 869
 870                 c->rex_prefix = 0;
 871         }
 872
 873 done_prefixes:
 874
 875         /* REX prefix. */
 876         if (c->rex_prefix)
 877                 if (c->rex_prefix & 8)
 878                         c->op_bytes = 8;        /* REX.W */
 879
 880         /* Opcode byte(s). */
 881         c->d = opcode_table[c->b];
 882         if (c->d == 0) {
 883                 /* Two-byte opcode? */
 884                 if (c->b == 0x0f) {
 885                         c->twobyte = 1;
 886                         c->b = insn_fetch(u8, 1, c->eip);
 887                         c->d = twobyte_table[c->b];
 888                 }
 889         }
 890
 891         if (c->d & Group) {
 892                 group = c->d & GroupMask;
 893                 c->modrm = insn_fetch(u8, 1, c->eip);
 894                 --c->eip;
 895
 896                 group = (group << 3) + ((c->modrm >> 3) & 7);
 897                 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
 898                         c->d = group2_table[group];
 899                 else
 900                         c->d = group_table[group];
 901         }
 902
 903         /* Unrecognised? */
 904         if (c->d == 0) {
 905                 DPRINTF("Cannot emulate %02x\n", c->b);
 906                 return -1;
 907         }
 908
 909         if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
 910                 c->op_bytes = 8;
 911
 912         /* ModRM and SIB bytes. */
 913         if (c->d & ModRM)
 914                 rc = decode_modrm(ctxt, ops);
 915         else if (c->d & MemAbs)
 916                 rc = decode_abs(ctxt, ops);
 917         if (rc)
 918                 goto done;
 919
 920         if (!c->override_base)
 921                 c->override_base = &ctxt->ds_base;
 922         if (mode == X86EMUL_MODE_PROT64 &&
 923             c->override_base != &ctxt->fs_base &&
 924             c->override_base != &ctxt->gs_base)
 925                 c->override_base = NULL;
 926
 927         if (c->override_base)
 928                 c->modrm_ea += *c->override_base;
 929
 930         if (c->ad_bytes != 8)
 931                 c->modrm_ea = (u32)c->modrm_ea;
 932         /*
 933          * Decode and fetch the source operand: register, memory
 934          * or immediate.
 935          */
 936         switch (c->d & SrcMask) {
 937         case SrcNone:
 938                 break;
 939         case SrcReg:
 940                 decode_register_operand(&c->src, c, 0);
 941                 break;
 942         case SrcMem16:
 943                 c->src.bytes = 2;
 944                 goto srcmem_common;
 945         case SrcMem32:
 946                 c->src.bytes = 4;
 947                 goto srcmem_common;
 948         case SrcMem:
 949                 c->src.bytes = (c->d & ByteOp) ? 1 :
 950                                                            c->op_bytes;
 951                 /* Don't fetch the address for invlpg: it could be unmapped. */
 952                 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
 953                         break;
 954         srcmem_common:
 955                 /*
 956                  * For instructions with a ModR/M byte, switch to register
 957                  * access if Mod = 3.
 958                  */
 959                 if ((c->d & ModRM) && c->modrm_mod == 3) {
 960                         c->src.type = OP_REG;
 961                         break;
 962                 }
 963                 c->src.type = OP_MEM;
 964                 break;
 965         case SrcImm:
 966                 c->src.type = OP_IMM;
 967                 c->src.ptr = (unsigned long *)c->eip;
 968                 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
 969                 if (c->src.bytes == 8)
 970                         c->src.bytes = 4;
 971                 /* NB. Immediates are sign-extended as necessary. */
 972                 switch (c->src.bytes) {
 973                 case 1:
 974                         c->src.val = insn_fetch(s8, 1, c->eip);
 975                         break;
 976                 case 2:
 977                         c->src.val = insn_fetch(s16, 2, c->eip);
 978                         break;
 979                 case 4:
 980                         c->src.val = insn_fetch(s32, 4, c->eip);
 981                         break;
 982                 }
 983                 break;
 984         case SrcImmByte:
 985                 c->src.type = OP_IMM;
 986                 c->src.ptr = (unsigned long *)c->eip;
 987                 c->src.bytes = 1;
 988                 c->src.val = insn_fetch(s8, 1, c->eip);
 989                 break;
 990         }
 991
 992         /* Decode and fetch the destination operand: register or memory. */
 993         switch (c->d & DstMask) {
 994         case ImplicitOps:
 995                 /* Special instructions do their own operand decoding. */
 996                 return 0;
 997         case DstReg:
 998                 decode_register_operand(&c->dst, c,
 999                          c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1000                 break;
1001         case DstMem:
1002                 if ((c->d & ModRM) && c->modrm_mod == 3) {
1003                         c->dst.type = OP_REG;
1004                         break;
1005                 }
1006                 c->dst.type = OP_MEM;
1007                 break;
1008         }
1009
1010 done:
1011         return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1012 }
1013
1014 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1015 {
1016         struct decode_cache *c = &ctxt->decode;
1017
1018         c->dst.type  = OP_MEM;
1019         c->dst.bytes = c->op_bytes;
1020         c->dst.val = c->src.val;
1021         register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes);
1022         c->dst.ptr = (void *) register_address(ctxt->ss_base,
1023                                                c->regs[VCPU_REGS_RSP]);
1024 }
1025
1026 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1027                                 struct x86_emulate_ops *ops)
1028 {
1029         struct decode_cache *c = &ctxt->decode;
1030         int rc;
1031
1032         rc = ops->read_std(register_address(ctxt->ss_base,
1033                                             c->regs[VCPU_REGS_RSP]),
1034                            &c->dst.val, c->dst.bytes, ctxt->vcpu);
1035         if (rc != 0)
1036                 return rc;
1037
1038         register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes);
1039
1040         return 0;
1041 }
1042
1043 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1044 {
1045         struct decode_cache *c = &ctxt->decode;
1046         switch (c->modrm_reg) {
1047         case 0: /* rol */
1048                 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1049                 break;
1050         case 1: /* ror */
1051                 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1052                 break;
1053         case 2: /* rcl */
1054                 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1055                 break;
1056         case 3: /* rcr */
1057                 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1058                 break;
1059         case 4: /* sal/shl */
1060         case 6: /* sal/shl */
1061                 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1062                 break;
1063         case 5: /* shr */
1064                 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1065                 break;
1066         case 7: /* sar */
1067                 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1068                 break;
1069         }
1070 }
1071
1072 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1073                                struct x86_emulate_ops *ops)
1074 {
1075         struct decode_cache *c = &ctxt->decode;
1076         int rc = 0;
1077
1078         switch (c->modrm_reg) {
1079         case 0 ... 1:   /* test */
1080                 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1081                 break;
1082         case 2: /* not */
1083                 c->dst.val = ~c->dst.val;
1084                 break;
1085         case 3: /* neg */
1086                 emulate_1op("neg", c->dst, ctxt->eflags);
1087                 break;
1088         default:
1089                 DPRINTF("Cannot emulate %02x\n", c->b);
1090                 rc = X86EMUL_UNHANDLEABLE;
1091                 break;
1092         }
1093         return rc;
1094 }
1095
1096 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1097                                struct x86_emulate_ops *ops)
1098 {
1099         struct decode_cache *c = &ctxt->decode;
1100         int rc;
1101
1102         switch (c->modrm_reg) {
1103         case 0: /* inc */
1104                 emulate_1op("inc", c->dst, ctxt->eflags);
1105                 break;
1106         case 1: /* dec */
1107                 emulate_1op("dec", c->dst, ctxt->eflags);
1108                 break;
1109         case 4: /* jmp abs */
1110                 if (c->b == 0xff)
1111                         c->eip = c->dst.val;
1112                 else {
1113                         DPRINTF("Cannot emulate %02x\n", c->b);
1114                         return X86EMUL_UNHANDLEABLE;
1115                 }
1116                 break;
1117         case 6: /* push */
1118
1119                 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1120
1121                 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1122                         c->dst.bytes = 8;
1123                         rc = ops->read_std((unsigned long)c->dst.ptr,
1124                                            &c->dst.val, 8, ctxt->vcpu);
1125                         if (rc != 0)
1126                                 return rc;
1127                 }
1128                 register_address_increment(c->regs[VCPU_REGS_RSP],
1129                                            -c->dst.bytes);
1130                 rc = ops->write_emulated(register_address(ctxt->ss_base,
1131                                     c->regs[VCPU_REGS_RSP]), &c->dst.val,
1132                                     c->dst.bytes, ctxt->vcpu);
1133                 if (rc != 0)
1134                         return rc;
1135                 c->dst.type = OP_NONE;
1136                 break;
1137         default:
1138                 DPRINTF("Cannot emulate %02x\n", c->b);
1139                 return X86EMUL_UNHANDLEABLE;
1140         }
1141         return 0;
1142 }
1143
1144 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1145                                struct x86_emulate_ops *ops,
1146                                unsigned long memop)
1147 {
1148         struct decode_cache *c = &ctxt->decode;
1149         u64 old, new;
1150         int rc;
1151
1152         rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
1153         if (rc != 0)
1154                 return rc;
1155
1156         if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1157             ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1158
1159                 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1160                 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1161                 ctxt->eflags &= ~EFLG_ZF;
1162
1163         } else {
1164                 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1165                        (u32) c->regs[VCPU_REGS_RBX];
1166
1167                 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
1168                 if (rc != 0)
1169                         return rc;
1170                 ctxt->eflags |= EFLG_ZF;
1171         }
1172         return 0;
1173 }
1174
1175 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1176                             struct x86_emulate_ops *ops)
1177 {
1178         int rc;
1179         struct decode_cache *c = &ctxt->decode;
1180
1181         switch (c->dst.type) {
1182         case OP_REG:
1183                 /* The 4-byte case *is* correct:
1184                  * in 64-bit mode we zero-extend.
1185                  */
1186                 switch (c->dst.bytes) {
1187                 case 1:
1188                         *(u8 *)c->dst.ptr = (u8)c->dst.val;
1189                         break;
1190                 case 2:
1191                         *(u16 *)c->dst.ptr = (u16)c->dst.val;
1192                         break;
1193                 case 4:
1194                         *c->dst.ptr = (u32)c->dst.val;
1195                         break;  /* 64b: zero-ext */
1196                 case 8:
1197                         *c->dst.ptr = c->dst.val;
1198                         break;
1199                 }
1200                 break;
1201         case OP_MEM:
1202                 if (c->lock_prefix)
1203                         rc = ops->cmpxchg_emulated(
1204                                         (unsigned long)c->dst.ptr,
1205                                         &c->dst.orig_val,
1206                                         &c->dst.val,
1207                                         c->dst.bytes,
1208                                         ctxt->vcpu);
1209                 else
1210                         rc = ops->write_emulated(
1211                                         (unsigned long)c->dst.ptr,
1212                                         &c->dst.val,
1213                                         c->dst.bytes,
1214                                         ctxt->vcpu);
1215                 if (rc != 0)
1216                         return rc;
1217                 break;
1218         case OP_NONE:
1219                 /* no writeback */
1220                 break;
1221         default:
1222                 break;
1223         }
1224         return 0;
1225 }
1226
1227 int
1228 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1229 {
1230         unsigned long memop = 0;
1231         u64 msr_data;
1232         unsigned long saved_eip = 0;
1233         struct decode_cache *c = &ctxt->decode;
1234         int rc = 0;
1235
1236         /* Shadow copy of register state. Committed on successful emulation.
1237          * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1238          * modify them.
1239          */
1240
1241         memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
1242         saved_eip = c->eip;
1243
1244         if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
1245                 memop = c->modrm_ea;
1246
1247         if (c->rep_prefix && (c->d & String)) {
1248                 /* All REP prefixes have the same first termination condition */
1249                 if (c->regs[VCPU_REGS_RCX] == 0) {
1250                         ctxt->vcpu->arch.rip = c->eip;
1251                         goto done;
1252                 }
1253                 /* The second termination condition only applies for REPE
1254                  * and REPNE. Test if the repeat string operation prefix is
1255                  * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1256                  * corresponding termination condition according to:
1257                  *      - if REPE/REPZ and ZF = 0 then done
1258                  *      - if REPNE/REPNZ and ZF = 1 then done
1259                  */
1260                 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1261                                 (c->b == 0xae) || (c->b == 0xaf)) {
1262                         if ((c->rep_prefix == REPE_PREFIX) &&
1263                                 ((ctxt->eflags & EFLG_ZF) == 0)) {
1264                                         ctxt->vcpu->arch.rip = c->eip;
1265                                         goto done;
1266                         }
1267                         if ((c->rep_prefix == REPNE_PREFIX) &&
1268                                 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1269                                 ctxt->vcpu->arch.rip = c->eip;
1270                                 goto done;
1271                         }
1272                 }
1273                 c->regs[VCPU_REGS_RCX]--;
1274                 c->eip = ctxt->vcpu->arch.rip;
1275         }
1276
1277         if (c->src.type == OP_MEM) {
1278                 c->src.ptr = (unsigned long *)memop;
1279                 c->src.val = 0;
1280                 rc = ops->read_emulated((unsigned long)c->src.ptr,
1281                                         &c->src.val,
1282                                         c->src.bytes,
1283                                         ctxt->vcpu);
1284                 if (rc != 0)
1285                         goto done;
1286                 c->src.orig_val = c->src.val;
1287         }
1288
1289         if ((c->d & DstMask) == ImplicitOps)
1290                 goto special_insn;
1291
1292
1293         if (c->dst.type == OP_MEM) {
1294                 c->dst.ptr = (unsigned long *)memop;
1295                 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1296                 c->dst.val = 0;
1297                 if (c->d & BitOp) {
1298                         unsigned long mask = ~(c->dst.bytes * 8 - 1);
1299
1300                         c->dst.ptr = (void *)c->dst.ptr +
1301                                                    (c->src.val & mask) / 8;
1302                 }
1303                 if (!(c->d & Mov) &&
1304                                    /* optimisation - avoid slow emulated read */
1305                     ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1306                                            &c->dst.val,
1307                                           c->dst.bytes, ctxt->vcpu)) != 0))
1308                         goto done;
1309         }
1310         c->dst.orig_val = c->dst.val;
1311
1312 special_insn:
1313
1314         if (c->twobyte)
1315                 goto twobyte_insn;
1316
1317         switch (c->b) {
1318         case 0x00 ... 0x05:
1319               add:              /* add */
1320                 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1321                 break;
1322         case 0x08 ... 0x0d:
1323               or:               /* or */
1324                 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1325                 break;
1326         case 0x10 ... 0x15:
1327               adc:              /* adc */
1328                 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1329                 break;
1330         case 0x18 ... 0x1d:
1331               sbb:              /* sbb */
1332                 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1333                 break;
1334         case 0x20 ... 0x23:
1335               and:              /* and */
1336                 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1337                 break;
1338         case 0x24:              /* and al imm8 */
1339                 c->dst.type = OP_REG;
1340                 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1341                 c->dst.val = *(u8 *)c->dst.ptr;
1342                 c->dst.bytes = 1;
1343                 c->dst.orig_val = c->dst.val;
1344                 goto and;
1345         case 0x25:              /* and ax imm16, or eax imm32 */
1346                 c->dst.type = OP_REG;
1347                 c->dst.bytes = c->op_bytes;
1348                 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1349                 if (c->op_bytes == 2)
1350                         c->dst.val = *(u16 *)c->dst.ptr;
1351                 else
1352                         c->dst.val = *(u32 *)c->dst.ptr;
1353                 c->dst.orig_val = c->dst.val;
1354                 goto and;
1355         case 0x28 ... 0x2d:
1356               sub:              /* sub */
1357                 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1358                 break;
1359         case 0x30 ... 0x35:
1360               xor:              /* xor */
1361                 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1362                 break;
1363         case 0x38 ... 0x3d:
1364               cmp:              /* cmp */
1365                 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1366                 break;
1367         case 0x40 ... 0x47: /* inc r16/r32 */
1368                 emulate_1op("inc", c->dst, ctxt->eflags);
1369                 break;
1370         case 0x48 ... 0x4f: /* dec r16/r32 */
1371                 emulate_1op("dec", c->dst, ctxt->eflags);
1372                 break;
1373         case 0x50 ... 0x57:  /* push reg */
1374                 c->dst.type  = OP_MEM;
1375                 c->dst.bytes = c->op_bytes;
1376                 c->dst.val = c->src.val;
1377                 register_address_increment(c->regs[VCPU_REGS_RSP],
1378                                            -c->op_bytes);
1379                 c->dst.ptr = (void *) register_address(
1380                         ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
1381                 break;
1382         case 0x58 ... 0x5f: /* pop reg */
1383         pop_instruction:
1384                 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1385                         c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1386                         c->op_bytes, ctxt->vcpu)) != 0)
1387                         goto done;
1388
1389                 register_address_increment(c->regs[VCPU_REGS_RSP],
1390                                            c->op_bytes);
1391                 c->dst.type = OP_NONE;  /* Disable writeback. */
1392                 break;
1393         case 0x63:              /* movsxd */
1394                 if (ctxt->mode != X86EMUL_MODE_PROT64)
1395                         goto cannot_emulate;
1396                 c->dst.val = (s32) c->src.val;
1397                 break;
1398         case 0x6a: /* push imm8 */
1399                 c->src.val = 0L;
1400                 c->src.val = insn_fetch(s8, 1, c->eip);
1401                 emulate_push(ctxt);
1402                 break;
1403         case 0x6c:              /* insb */
1404         case 0x6d:              /* insw/insd */
1405                  if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1406                                 1,
1407                                 (c->d & ByteOp) ? 1 : c->op_bytes,
1408                                 c->rep_prefix ?
1409                                 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1410                                 (ctxt->eflags & EFLG_DF),
1411                                 register_address(ctxt->es_base,
1412                                                  c->regs[VCPU_REGS_RDI]),
1413                                 c->rep_prefix,
1414                                 c->regs[VCPU_REGS_RDX]) == 0) {
1415                         c->eip = saved_eip;
1416                         return -1;
1417                 }
1418                 return 0;
1419         case 0x6e:              /* outsb */
1420         case 0x6f:              /* outsw/outsd */
1421                 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1422                                 0,
1423                                 (c->d & ByteOp) ? 1 : c->op_bytes,
1424                                 c->rep_prefix ?
1425                                 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1426                                 (ctxt->eflags & EFLG_DF),
1427                                 register_address(c->override_base ?
1428                                                         *c->override_base :
1429                                                         ctxt->ds_base,
1430                                                  c->regs[VCPU_REGS_RSI]),
1431                                 c->rep_prefix,
1432                                 c->regs[VCPU_REGS_RDX]) == 0) {
1433                         c->eip = saved_eip;
1434                         return -1;
1435                 }
1436                 return 0;
1437         case 0x70 ... 0x7f: /* jcc (short) */ {
1438                 int rel = insn_fetch(s8, 1, c->eip);
1439
1440                 if (test_cc(c->b, ctxt->eflags))
1441                         JMP_REL(rel);
1442                 break;
1443         }
1444         case 0x80 ... 0x83:     /* Grp1 */
1445                 switch (c->modrm_reg) {
1446                 case 0:
1447                         goto add;
1448                 case 1:
1449                         goto or;
1450                 case 2:
1451                         goto adc;
1452                 case 3:
1453                         goto sbb;
1454                 case 4:
1455                         goto and;
1456                 case 5:
1457                         goto sub;
1458                 case 6:
1459                         goto xor;
1460                 case 7:
1461                         goto cmp;
1462                 }
1463                 break;
1464         case 0x84 ... 0x85:
1465                 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1466                 break;
1467         case 0x86 ... 0x87:     /* xchg */
1468                 /* Write back the register source. */
1469                 switch (c->dst.bytes) {
1470                 case 1:
1471                         *(u8 *) c->src.ptr = (u8) c->dst.val;
1472                         break;
1473                 case 2:
1474                         *(u16 *) c->src.ptr = (u16) c->dst.val;
1475                         break;
1476                 case 4:
1477                         *c->src.ptr = (u32) c->dst.val;
1478                         break;  /* 64b reg: zero-extend */
1479                 case 8:
1480                         *c->src.ptr = c->dst.val;
1481                         break;
1482                 }
1483                 /*
1484                  * Write back the memory destination with implicit LOCK
1485                  * prefix.
1486                  */
1487                 c->dst.val = c->src.val;
1488                 c->lock_prefix = 1;
1489                 break;
1490         case 0x88 ... 0x8b:     /* mov */
1491                 goto mov;
1492         case 0x8d: /* lea r16/r32, m */
1493                 c->dst.val = c->modrm_val;
1494                 break;
1495         case 0x8f:              /* pop (sole member of Grp1a) */
1496                 rc = emulate_grp1a(ctxt, ops);
1497                 if (rc != 0)
1498                         goto done;
1499                 break;
1500         case 0x9c: /* pushf */
1501                 c->src.val =  (unsigned long) ctxt->eflags;
1502                 emulate_push(ctxt);
1503                 break;
1504         case 0x9d: /* popf */
1505                 c->dst.ptr = (unsigned long *) &ctxt->eflags;
1506                 goto pop_instruction;
1507         case 0xa0 ... 0xa1:     /* mov */
1508                 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1509                 c->dst.val = c->src.val;
1510                 break;
1511         case 0xa2 ... 0xa3:     /* mov */
1512                 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1513                 break;
1514         case 0xa4 ... 0xa5:     /* movs */
1515                 c->dst.type = OP_MEM;
1516                 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1517                 c->dst.ptr = (unsigned long *)register_address(
1518                                                    ctxt->es_base,
1519                                                    c->regs[VCPU_REGS_RDI]);
1520                 if ((rc = ops->read_emulated(register_address(
1521                       c->override_base ? *c->override_base :
1522                                         ctxt->ds_base,
1523                                         c->regs[VCPU_REGS_RSI]),
1524                                         &c->dst.val,
1525                                         c->dst.bytes, ctxt->vcpu)) != 0)
1526                         goto done;
1527                 register_address_increment(c->regs[VCPU_REGS_RSI],
1528                                        (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1529                                                            : c->dst.bytes);
1530                 register_address_increment(c->regs[VCPU_REGS_RDI],
1531                                        (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1532                                                            : c->dst.bytes);
1533                 break;
1534         case 0xa6 ... 0xa7:     /* cmps */
1535                 c->src.type = OP_NONE; /* Disable writeback. */
1536                 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1537                 c->src.ptr = (unsigned long *)register_address(
1538                                 c->override_base ? *c->override_base :
1539                                                    ctxt->ds_base,
1540                                                    c->regs[VCPU_REGS_RSI]);
1541                 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1542                                                 &c->src.val,
1543                                                 c->src.bytes,
1544                                                 ctxt->vcpu)) != 0)
1545                         goto done;
1546
1547                 c->dst.type = OP_NONE; /* Disable writeback. */
1548                 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1549                 c->dst.ptr = (unsigned long *)register_address(
1550                                                    ctxt->es_base,
1551                                                    c->regs[VCPU_REGS_RDI]);
1552                 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1553                                                 &c->dst.val,
1554                                                 c->dst.bytes,
1555                                                 ctxt->vcpu)) != 0)
1556                         goto done;
1557
1558                 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1559
1560                 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1561
1562                 register_address_increment(c->regs[VCPU_REGS_RSI],
1563                                        (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1564                                                                   : c->src.bytes);
1565                 register_address_increment(c->regs[VCPU_REGS_RDI],
1566                                        (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1567                                                                   : c->dst.bytes);
1568
1569                 break;
1570         case 0xaa ... 0xab:     /* stos */
1571                 c->dst.type = OP_MEM;
1572                 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1573                 c->dst.ptr = (unsigned long *)register_address(
1574                                                    ctxt->es_base,
1575                                                    c->regs[VCPU_REGS_RDI]);
1576                 c->dst.val = c->regs[VCPU_REGS_RAX];
1577                 register_address_increment(c->regs[VCPU_REGS_RDI],
1578                                        (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1579                                                            : c->dst.bytes);
1580                 break;
1581         case 0xac ... 0xad:     /* lods */
1582                 c->dst.type = OP_REG;
1583                 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1584                 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1585                 if ((rc = ops->read_emulated(register_address(
1586                                 c->override_base ? *c->override_base :
1587                                                    ctxt->ds_base,
1588                                                  c->regs[VCPU_REGS_RSI]),
1589                                                  &c->dst.val,
1590                                                  c->dst.bytes,
1591                                                  ctxt->vcpu)) != 0)
1592                         goto done;
1593                 register_address_increment(c->regs[VCPU_REGS_RSI],
1594                                        (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1595                                                            : c->dst.bytes);
1596                 break;
1597         case 0xae ... 0xaf:     /* scas */
1598                 DPRINTF("Urk! I don't handle SCAS.\n");
1599                 goto cannot_emulate;
1600         case 0xc0 ... 0xc1:
1601                 emulate_grp2(ctxt);
1602                 break;
1603         case 0xc3: /* ret */
1604                 c->dst.ptr = &c->eip;
1605                 goto pop_instruction;
1606         case 0xc6 ... 0xc7:     /* mov (sole member of Grp11) */
1607         mov:
1608                 c->dst.val = c->src.val;
1609                 break;
1610         case 0xd0 ... 0xd1:     /* Grp2 */
1611                 c->src.val = 1;
1612                 emulate_grp2(ctxt);
1613                 break;
1614         case 0xd2 ... 0xd3:     /* Grp2 */
1615                 c->src.val = c->regs[VCPU_REGS_RCX];
1616                 emulate_grp2(ctxt);
1617                 break;
1618         case 0xe8: /* call (near) */ {
1619                 long int rel;
1620                 switch (c->op_bytes) {
1621                 case 2:
1622                         rel = insn_fetch(s16, 2, c->eip);
1623                         break;
1624                 case 4:
1625                         rel = insn_fetch(s32, 4, c->eip);
1626                         break;
1627                 default:
1628                         DPRINTF("Call: Invalid op_bytes\n");
1629                         goto cannot_emulate;
1630                 }
1631                 c->src.val = (unsigned long) c->eip;
1632                 JMP_REL(rel);
1633                 c->op_bytes = c->ad_bytes;
1634                 emulate_push(ctxt);
1635                 break;
1636         }
1637         case 0xe9: /* jmp rel */
1638         case 0xeb: /* jmp rel short */
1639                 JMP_REL(c->src.val);
1640                 c->dst.type = OP_NONE; /* Disable writeback. */
1641                 break;
1642         case 0xf4:              /* hlt */
1643                 ctxt->vcpu->arch.halt_request = 1;
1644                 goto done;
1645         case 0xf5:      /* cmc */
1646                 /* complement carry flag from eflags reg */
1647                 ctxt->eflags ^= EFLG_CF;
1648                 c->dst.type = OP_NONE;  /* Disable writeback. */
1649                 break;
1650         case 0xf6 ... 0xf7:     /* Grp3 */
1651                 rc = emulate_grp3(ctxt, ops);
1652                 if (rc != 0)
1653                         goto done;
1654                 break;
1655         case 0xf8: /* clc */
1656                 ctxt->eflags &= ~EFLG_CF;
1657                 c->dst.type = OP_NONE;  /* Disable writeback. */
1658                 break;
1659         case 0xfa: /* cli */
1660                 ctxt->eflags &= ~X86_EFLAGS_IF;
1661                 c->dst.type = OP_NONE;  /* Disable writeback. */
1662                 break;
1663         case 0xfb: /* sti */
1664                 ctxt->eflags |= X86_EFLAGS_IF;
1665                 c->dst.type = OP_NONE;  /* Disable writeback. */
1666                 break;
1667         case 0xfe ... 0xff:     /* Grp4/Grp5 */
1668                 rc = emulate_grp45(ctxt, ops);
1669                 if (rc != 0)
1670                         goto done;
1671                 break;
1672         }
1673
1674 writeback:
1675         rc = writeback(ctxt, ops);
1676         if (rc != 0)
1677                 goto done;
1678
1679         /* Commit shadow register state. */
1680         memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1681         ctxt->vcpu->arch.rip = c->eip;
1682
1683 done:
1684         if (rc == X86EMUL_UNHANDLEABLE) {
1685                 c->eip = saved_eip;
1686                 return -1;
1687         }
1688         return 0;
1689
1690 twobyte_insn:
1691         switch (c->b) {
1692         case 0x01: /* lgdt, lidt, lmsw */
1693                 switch (c->modrm_reg) {
1694                         u16 size;
1695                         unsigned long address;
1696
1697                 case 0: /* vmcall */
1698                         if (c->modrm_mod != 3 || c->modrm_rm != 1)
1699                                 goto cannot_emulate;
1700
1701                         rc = kvm_fix_hypercall(ctxt->vcpu);
1702                         if (rc)
1703                                 goto done;
1704
1705                         kvm_emulate_hypercall(ctxt->vcpu);
1706                         break;
1707                 case 2: /* lgdt */
1708                         rc = read_descriptor(ctxt, ops, c->src.ptr,
1709                                              &size, &address, c->op_bytes);
1710                         if (rc)
1711                                 goto done;
1712                         realmode_lgdt(ctxt->vcpu, size, address);
1713                         break;
1714                 case 3: /* lidt/vmmcall */
1715                         if (c->modrm_mod == 3 && c->modrm_rm == 1) {
1716                                 rc = kvm_fix_hypercall(ctxt->vcpu);
1717                                 if (rc)
1718                                         goto done;
1719                                 kvm_emulate_hypercall(ctxt->vcpu);
1720                         } else {
1721                                 rc = read_descriptor(ctxt, ops, c->src.ptr,
1722                                                      &size, &address,
1723                                                      c->op_bytes);
1724                                 if (rc)
1725                                         goto done;
1726                                 realmode_lidt(ctxt->vcpu, size, address);
1727                         }
1728                         break;
1729                 case 4: /* smsw */
1730                         if (c->modrm_mod != 3)
1731                                 goto cannot_emulate;
1732                         *(u16 *)&c->regs[c->modrm_rm]
1733                                 = realmode_get_cr(ctxt->vcpu, 0);
1734                         break;
1735                 case 6: /* lmsw */
1736                         if (c->modrm_mod != 3)
1737                                 goto cannot_emulate;
1738                         realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val,
1739                                                   &ctxt->eflags);
1740                         break;
1741                 case 7: /* invlpg*/
1742                         emulate_invlpg(ctxt->vcpu, memop);
1743                         break;
1744                 default:
1745                         goto cannot_emulate;
1746                 }
1747                 /* Disable writeback. */
1748                 c->dst.type = OP_NONE;
1749                 break;
1750         case 0x06:
1751                 emulate_clts(ctxt->vcpu);
1752                 c->dst.type = OP_NONE;
1753                 break;
1754         case 0x08:              /* invd */
1755         case 0x09:              /* wbinvd */
1756         case 0x0d:              /* GrpP (prefetch) */
1757         case 0x18:              /* Grp16 (prefetch/nop) */
1758                 c->dst.type = OP_NONE;
1759                 break;
1760         case 0x20: /* mov cr, reg */
1761                 if (c->modrm_mod != 3)
1762                         goto cannot_emulate;
1763                 c->regs[c->modrm_rm] =
1764                                 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1765                 c->dst.type = OP_NONE;  /* no writeback */
1766                 break;
1767         case 0x21: /* mov from dr to reg */
1768                 if (c->modrm_mod != 3)
1769                         goto cannot_emulate;
1770                 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
1771                 if (rc)
1772                         goto cannot_emulate;
1773                 c->dst.type = OP_NONE;  /* no writeback */
1774                 break;
1775         case 0x22: /* mov reg, cr */
1776                 if (c->modrm_mod != 3)
1777                         goto cannot_emulate;
1778                 realmode_set_cr(ctxt->vcpu,
1779                                 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1780                 c->dst.type = OP_NONE;
1781                 break;
1782         case 0x23: /* mov from reg to dr */
1783                 if (c->modrm_mod != 3)
1784                         goto cannot_emulate;
1785                 rc = emulator_set_dr(ctxt, c->modrm_reg,
1786                                      c->regs[c->modrm_rm]);
1787                 if (rc)
1788                         goto cannot_emulate;
1789                 c->dst.type = OP_NONE;  /* no writeback */
1790                 break;
1791         case 0x30:
1792                 /* wrmsr */
1793                 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1794                         | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1795                 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1796                 if (rc) {
1797                         kvm_inject_gp(ctxt->vcpu, 0);
1798                         c->eip = ctxt->vcpu->arch.rip;
1799                 }
1800                 rc = X86EMUL_CONTINUE;
1801                 c->dst.type = OP_NONE;
1802                 break;
1803         case 0x32:
1804                 /* rdmsr */
1805                 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1806                 if (rc) {
1807                         kvm_inject_gp(ctxt->vcpu, 0);
1808                         c->eip = ctxt->vcpu->arch.rip;
1809                 } else {
1810                         c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1811                         c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1812                 }
1813                 rc = X86EMUL_CONTINUE;
1814                 c->dst.type = OP_NONE;
1815                 break;
1816         case 0x40 ... 0x4f:     /* cmov */
1817                 c->dst.val = c->dst.orig_val = c->src.val;
1818                 if (!test_cc(c->b, ctxt->eflags))
1819                         c->dst.type = OP_NONE; /* no writeback */
1820                 break;
1821         case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1822                 long int rel;
1823
1824                 switch (c->op_bytes) {
1825                 case 2:
1826                         rel = insn_fetch(s16, 2, c->eip);
1827                         break;
1828                 case 4:
1829                         rel = insn_fetch(s32, 4, c->eip);
1830                         break;
1831                 case 8:
1832                         rel = insn_fetch(s64, 8, c->eip);
1833                         break;
1834                 default:
1835                         DPRINTF("jnz: Invalid op_bytes\n");
1836                         goto cannot_emulate;
1837                 }
1838                 if (test_cc(c->b, ctxt->eflags))
1839                         JMP_REL(rel);
1840                 c->dst.type = OP_NONE;
1841                 break;
1842         }
1843         case 0xa3:
1844               bt:               /* bt */
1845                 c->dst.type = OP_NONE;
1846                 /* only subword offset */
1847                 c->src.val &= (c->dst.bytes << 3) - 1;
1848                 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
1849                 break;
1850         case 0xab:
1851               bts:              /* bts */
1852                 /* only subword offset */
1853                 c->src.val &= (c->dst.bytes << 3) - 1;
1854                 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
1855                 break;
1856         case 0xb0 ... 0xb1:     /* cmpxchg */
1857                 /*
1858                  * Save real source value, then compare EAX against
1859                  * destination.
1860                  */
1861                 c->src.orig_val = c->src.val;
1862                 c->src.val = c->regs[VCPU_REGS_RAX];
1863                 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1864                 if (ctxt->eflags & EFLG_ZF) {
1865                         /* Success: write back to memory. */
1866                         c->dst.val = c->src.orig_val;
1867                 } else {
1868                         /* Failure: write the value we saw to EAX. */
1869                         c->dst.type = OP_REG;
1870                         c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1871                 }
1872                 break;
1873         case 0xb3:
1874               btr:              /* btr */
1875                 /* only subword offset */
1876                 c->src.val &= (c->dst.bytes << 3) - 1;
1877                 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
1878                 break;
1879         case 0xb6 ... 0xb7:     /* movzx */
1880                 c->dst.bytes = c->op_bytes;
1881                 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1882                                                        : (u16) c->src.val;
1883                 break;
1884         case 0xba:              /* Grp8 */
1885                 switch (c->modrm_reg & 3) {
1886                 case 0:
1887                         goto bt;
1888                 case 1:
1889                         goto bts;
1890                 case 2:
1891                         goto btr;
1892                 case 3:
1893                         goto btc;
1894                 }
1895                 break;
1896         case 0xbb:
1897               btc:              /* btc */
1898                 /* only subword offset */
1899                 c->src.val &= (c->dst.bytes << 3) - 1;
1900                 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
1901                 break;
1902         case 0xbe ... 0xbf:     /* movsx */
1903                 c->dst.bytes = c->op_bytes;
1904                 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1905                                                         (s16) c->src.val;
1906                 break;
1907         case 0xc3:              /* movnti */
1908                 c->dst.bytes = c->op_bytes;
1909                 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1910                                                         (u64) c->src.val;
1911                 break;
1912         case 0xc7:              /* Grp9 (cmpxchg8b) */
1913                 rc = emulate_grp9(ctxt, ops, memop);
1914                 if (rc != 0)
1915                         goto done;
1916                 c->dst.type = OP_NONE;
1917                 break;
1918         }
1919         goto writeback;
1920
1921 cannot_emulate:
1922         DPRINTF("Cannot emulate %02x\n", c->b);
1923         c->eip = saved_eip;
1924         return -1;
1925 }