1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * linux/arch/i386/kernel/voyager_smp.c
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
12 #include <linux/module.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/mc146818rtc.h>
17 #include <linux/cache.h>
18 #include <linux/interrupt.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/bootmem.h>
22 #include <linux/completion.h>
24 #include <asm/voyager.h>
27 #include <asm/pgalloc.h>
28 #include <asm/tlbflush.h>
29 #include <asm/arch_hooks.h>
31 /* TLB state -- visible externally, indexed physically */
32 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { &init_mm, 0 };
34 /* CPU IRQ affinity -- set to all ones initially */
35 static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned =
36 {[0 ... NR_CPUS-1] = ~0UL };
38 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
39 * indexed physically */
40 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
41 EXPORT_PER_CPU_SYMBOL(cpu_info);
43 /* physical ID of the CPU used to boot the system */
44 unsigned char boot_cpu_id;
46 /* The memory line addresses for the Quad CPIs */
47 struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
49 /* The masks for the Extended VIC processors, filled in by cat_init */
50 __u32 voyager_extended_vic_processors = 0;
52 /* Masks for the extended Quad processors which cannot be VIC booted */
53 __u32 voyager_allowed_boot_processors = 0;
55 /* The mask for the Quad Processors (both extended and non-extended) */
56 __u32 voyager_quad_processors = 0;
58 /* Total count of live CPUs, used in process.c to display
59 * the CPU information and in irq.c for the per CPU irq
60 * activity count. Finally exported by i386_ksyms.c */
61 static int voyager_extended_cpus = 1;
63 /* Have we found an SMP box - used by time.c to do the profiling
64 interrupt for timeslicing; do not set to 1 until the per CPU timer
65 interrupt is active */
66 int smp_found_config = 0;
68 /* Used for the invalidate map that's also checked in the spinlock */
69 static volatile unsigned long smp_invalidate_needed;
71 /* Bitmask of currently online CPUs - used by setup.c for
72 /proc/cpuinfo, visible externally but still physical */
73 cpumask_t cpu_online_map = CPU_MASK_NONE;
74 EXPORT_SYMBOL(cpu_online_map);
76 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
77 * by scheduler but indexed physically */
78 cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
80 /* The internal functions */
81 static void send_CPI(__u32 cpuset, __u8 cpi);
82 static void ack_CPI(__u8 cpi);
83 static int ack_QIC_CPI(__u8 cpi);
84 static void ack_special_QIC_CPI(__u8 cpi);
85 static void ack_VIC_CPI(__u8 cpi);
86 static void send_CPI_allbutself(__u8 cpi);
87 static void mask_vic_irq(unsigned int irq);
88 static void unmask_vic_irq(unsigned int irq);
89 static unsigned int startup_vic_irq(unsigned int irq);
90 static void enable_local_vic_irq(unsigned int irq);
91 static void disable_local_vic_irq(unsigned int irq);
92 static void before_handle_vic_irq(unsigned int irq);
93 static void after_handle_vic_irq(unsigned int irq);
94 static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
95 static void ack_vic_irq(unsigned int irq);
96 static void vic_enable_cpi(void);
97 static void do_boot_cpu(__u8 cpuid);
98 static void do_quad_bootstrap(void);
100 int hard_smp_processor_id(void);
101 int safe_smp_processor_id(void);
103 /* Inline functions */
104 static inline void send_one_QIC_CPI(__u8 cpu, __u8 cpi)
106 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
107 (smp_processor_id() << 16) + cpi;
110 static inline void send_QIC_CPI(__u32 cpuset, __u8 cpi)
114 for_each_online_cpu(cpu) {
115 if (cpuset & (1 << cpu)) {
117 if (!cpu_isset(cpu, cpu_online_map))
118 VDEBUG(("CPU%d sending cpi %d to CPU%d not in "
120 hard_smp_processor_id(), cpi, cpu));
122 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
127 static inline void wrapper_smp_local_timer_interrupt(void)
130 smp_local_timer_interrupt();
134 static inline void send_one_CPI(__u8 cpu, __u8 cpi)
136 if (voyager_quad_processors & (1 << cpu))
137 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
139 send_CPI(1 << cpu, cpi);
142 static inline void send_CPI_allbutself(__u8 cpi)
144 __u8 cpu = smp_processor_id();
145 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
149 static inline int is_cpu_quad(void)
151 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
152 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
155 static inline int is_cpu_extended(void)
157 __u8 cpu = hard_smp_processor_id();
159 return (voyager_extended_vic_processors & (1 << cpu));
162 static inline int is_cpu_vic_boot(void)
164 __u8 cpu = hard_smp_processor_id();
166 return (voyager_extended_vic_processors
167 & voyager_allowed_boot_processors & (1 << cpu));
170 static inline void ack_CPI(__u8 cpi)
173 case VIC_CPU_BOOT_CPI:
174 if (is_cpu_quad() && !is_cpu_vic_boot())
181 /* These are slightly strange. Even on the Quad card,
182 * They are vectored as VIC CPIs */
184 ack_special_QIC_CPI(cpi);
189 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
194 /* local variables */
196 /* The VIC IRQ descriptors -- these look almost identical to the
197 * 8259 IRQs except that masks and things must be kept per processor
199 static struct irq_chip vic_chip = {
201 .startup = startup_vic_irq,
202 .mask = mask_vic_irq,
203 .unmask = unmask_vic_irq,
204 .set_affinity = set_vic_irq_affinity,
207 /* used to count up as CPUs are brought on line (starts at 0) */
208 static int cpucount = 0;
210 /* steal a page from the bottom of memory for the trampoline and
211 * squirrel its address away here. This will be in kernel virtual
213 unsigned char *trampoline_base;
215 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
216 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
217 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
218 static DEFINE_PER_CPU(int, prof_counter) = 1;
220 /* the map used to check if a CPU has booted */
221 static __u32 cpu_booted_map;
223 /* the synchronize flag used to hold all secondary CPUs spinning in
224 * a tight loop until the boot sequence is ready for them */
225 static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
227 /* This is for the new dynamic CPU boot code */
228 cpumask_t cpu_callin_map = CPU_MASK_NONE;
229 cpumask_t cpu_callout_map = CPU_MASK_NONE;
230 cpumask_t cpu_possible_map = CPU_MASK_NONE;
231 EXPORT_SYMBOL(cpu_possible_map);
233 /* The per processor IRQ masks (these are usually kept in sync) */
234 static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
236 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
237 static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
239 /* Lock for enable/disable of VIC interrupts */
240 static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
242 /* The boot processor is correctly set up in PC mode when it
243 * comes up, but the secondaries need their master/slave 8259
244 * pairs initializing correctly */
246 /* Interrupt counters (per cpu) and total - used to try to
247 * even up the interrupt handling routines */
248 static long vic_intr_total = 0;
249 static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
250 static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
252 /* Since we can only use CPI0, we fake all the other CPIs */
253 static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
255 /* debugging routine to read the isr of the cpu's pic */
256 static inline __u16 vic_read_isr(void)
261 isr = inb(0xa0) << 8;
268 static __init void qic_setup(void)
270 if (!is_cpu_quad()) {
271 /* not a quad, no setup */
274 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
275 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
277 if (is_cpu_extended()) {
278 /* the QIC duplicate of the VIC base register */
279 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
280 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
282 /* FIXME: should set up the QIC timer and memory parity
283 * error vectors here */
287 static __init void vic_setup_pic(void)
289 outb(1, VIC_REDIRECT_REGISTER_1);
290 /* clear the claim registers for dynamic routing */
291 outb(0, VIC_CLAIM_REGISTER_0);
292 outb(0, VIC_CLAIM_REGISTER_1);
294 outb(0, VIC_PRIORITY_REGISTER);
295 /* Set the Primary and Secondary Microchannel vector
296 * bases to be the same as the ordinary interrupts
298 * FIXME: This would be more efficient using separate
300 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
301 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
302 /* Now initiallise the master PIC belonging to this CPU by
303 * sending the four ICWs */
305 /* ICW1: level triggered, ICW4 needed */
308 /* ICW2: vector base */
309 outb(FIRST_EXTERNAL_VECTOR, 0x21);
311 /* ICW3: slave at line 2 */
314 /* ICW4: 8086 mode */
317 /* now the same for the slave PIC */
319 /* ICW1: level trigger, ICW4 needed */
322 /* ICW2: slave vector base */
323 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
328 /* ICW4: 8086 mode */
332 static void do_quad_bootstrap(void)
334 if (is_cpu_quad() && is_cpu_vic_boot()) {
337 __u8 cpuid = hard_smp_processor_id();
339 local_irq_save(flags);
341 for (i = 0; i < 4; i++) {
342 /* FIXME: this would be >>3 &0x7 on the 32 way */
343 if (((cpuid >> 2) & 0x03) == i)
344 /* don't lower our own mask! */
347 /* masquerade as local Quad CPU */
348 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
349 /* enable the startup CPI */
350 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
352 outb(0, QIC_PROCESSOR_ID);
354 local_irq_restore(flags);
358 /* Set up all the basic stuff: read the SMP config and make all the
359 * SMP information reflect only the boot cpu. All others will be
360 * brought on-line later. */
361 void __init find_smp_config(void)
365 boot_cpu_id = hard_smp_processor_id();
367 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
369 /* initialize the CPU structures (moved from smp_boot_cpus) */
370 for (i = 0; i < NR_CPUS; i++) {
371 cpu_irq_affinity[i] = ~0;
373 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
375 /* The boot CPU must be extended */
376 voyager_extended_vic_processors = 1 << boot_cpu_id;
377 /* initially, all of the first 8 CPUs can boot */
378 voyager_allowed_boot_processors = 0xff;
379 /* set up everything for just this CPU, we can alter
380 * this as we start the other CPUs later */
381 /* now get the CPU disposition from the extended CMOS */
382 cpus_addr(phys_cpu_present_map)[0] =
383 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
384 cpus_addr(phys_cpu_present_map)[0] |=
385 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
386 cpus_addr(phys_cpu_present_map)[0] |=
387 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK +
389 cpus_addr(phys_cpu_present_map)[0] |=
390 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK +
392 cpu_possible_map = phys_cpu_present_map;
393 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n",
394 cpus_addr(phys_cpu_present_map)[0]);
395 /* Here we set up the VIC to enable SMP */
396 /* enable the CPIs by writing the base vector to their register */
397 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
398 outb(1, VIC_REDIRECT_REGISTER_1);
399 /* set the claim registers for static routing --- Boot CPU gets
400 * all interrupts untill all other CPUs started */
401 outb(0xff, VIC_CLAIM_REGISTER_0);
402 outb(0xff, VIC_CLAIM_REGISTER_1);
403 /* Set the Primary and Secondary Microchannel vector
404 * bases to be the same as the ordinary interrupts
406 * FIXME: This would be more efficient using separate
408 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
409 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
411 /* Finally tell the firmware that we're driving */
412 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
413 VOYAGER_SUS_IN_CONTROL_PORT);
415 current_thread_info()->cpu = boot_cpu_id;
416 x86_write_percpu(cpu_number, boot_cpu_id);
420 * The bootstrap kernel entry code has set these up. Save them
421 * for a given CPU, id is physical */
422 void __init smp_store_cpu_info(int id)
424 struct cpuinfo_x86 *c = &cpu_data(id);
428 identify_secondary_cpu(c);
431 /* set up the trampoline and return the physical address of the code */
432 unsigned long __init setup_trampoline(void)
434 /* these two are global symbols in trampoline.S */
435 extern const __u8 trampoline_end[];
436 extern const __u8 trampoline_data[];
438 memcpy(trampoline_base, trampoline_data,
439 trampoline_end - trampoline_data);
440 return virt_to_phys(trampoline_base);
443 /* Routine initially called when a non-boot CPU is brought online */
444 static void __init start_secondary(void *unused)
446 __u8 cpuid = hard_smp_processor_id();
450 /* OK, we're in the routine */
451 ack_CPI(VIC_CPU_BOOT_CPI);
453 /* setup the 8259 master slave pair belonging to this CPU ---
454 * we won't actually receive any until the boot CPU
455 * relinquishes it's static routing mask */
460 if (is_cpu_quad() && !is_cpu_vic_boot()) {
461 /* clear the boot CPI */
465 voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
466 printk("read dummy %d\n", dummy);
469 /* lower the mask to receive CPIs */
472 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
474 /* enable interrupts */
477 /* get our bogomips */
480 /* save our processor parameters */
481 smp_store_cpu_info(cpuid);
483 /* if we're a quad, we may need to bootstrap other CPUs */
486 /* FIXME: this is rather a poor hack to prevent the CPU
487 * activating softirqs while it's supposed to be waiting for
488 * permission to proceed. Without this, the new per CPU stuff
489 * in the softirqs will fail */
491 cpu_set(cpuid, cpu_callin_map);
493 /* signal that we're done */
496 while (!cpu_isset(cpuid, smp_commenced_mask))
502 cpu_set(cpuid, cpu_online_map);
507 /* Routine to kick start the given CPU and wait for it to report ready
508 * (or timeout in startup). When this routine returns, the requested
509 * CPU is either fully running and configured or known to be dead.
511 * We call this routine sequentially 1 CPU at a time, so no need for
514 static void __init do_boot_cpu(__u8 cpu)
516 struct task_struct *idle;
519 int quad_boot = (1 << cpu) & voyager_quad_processors
520 & ~(voyager_extended_vic_processors
521 & voyager_allowed_boot_processors);
523 /* This is the format of the CPI IDT gate (in real mode) which
524 * we're hijacking to boot the CPU */
533 __u32 *hijack_vector;
534 __u32 start_phys_address = setup_trampoline();
536 /* There's a clever trick to this: The linux trampoline is
537 * compiled to begin at absolute location zero, so make the
538 * address zero but have the data segment selector compensate
539 * for the actual address */
540 hijack_source.idt.Offset = start_phys_address & 0x000F;
541 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
544 alternatives_smp_switch(1);
546 idle = fork_idle(cpu);
548 panic("failed fork for CPU%d", cpu);
549 idle->thread.ip = (unsigned long)start_secondary;
550 /* init_tasks (in sched.c) is indexed logically */
551 stack_start.sp = (void *)idle->thread.sp;
554 per_cpu(current_task, cpu) = idle;
555 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
558 /* Note: Don't modify initial ss override */
559 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
560 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
561 hijack_source.idt.Offset, stack_start.sp));
563 /* init lowmem identity mapping */
564 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
565 min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
569 printk("CPU %d: non extended Quad boot\n", cpu);
572 phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE) * 4);
573 *hijack_vector = hijack_source.val;
575 printk("CPU%d: extended VIC boot\n", cpu);
578 phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE) * 4);
579 *hijack_vector = hijack_source.val;
580 /* VIC errata, may also receive interrupt at this address */
583 phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI +
584 VIC_DEFAULT_CPI_BASE) * 4);
585 *hijack_vector = hijack_source.val;
587 /* All non-boot CPUs start with interrupts fully masked. Need
588 * to lower the mask of the CPI we're about to send. We do
589 * this in the VIC by masquerading as the processor we're
590 * about to boot and lowering its interrupt mask */
591 local_irq_save(flags);
593 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
595 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
596 /* here we're altering registers belonging to `cpu' */
598 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
599 /* now go back to our original identity */
600 outb(boot_cpu_id, VIC_PROCESSOR_ID);
602 /* and boot the CPU */
604 send_CPI((1 << cpu), VIC_CPU_BOOT_CPI);
607 local_irq_restore(flags);
609 /* now wait for it to become ready (or timeout) */
610 for (timeout = 0; timeout < 50000; timeout++) {
615 /* reset the page table */
618 if (cpu_booted_map) {
619 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
620 cpu, smp_processor_id()));
622 printk("CPU%d: ", cpu);
623 print_cpu_info(&cpu_data(cpu));
625 cpu_set(cpu, cpu_callout_map);
626 cpu_set(cpu, cpu_present_map);
628 printk("CPU%d FAILED TO BOOT: ", cpu);
630 ((volatile unsigned char *)phys_to_virt(start_phys_address))
634 printk("Not responding.\n");
640 void __init smp_boot_cpus(void)
644 /* CAT BUS initialisation must be done after the memory */
645 /* FIXME: The L4 has a catbus too, it just needs to be
646 * accessed in a totally different way */
647 if (voyager_level == 5) {
650 /* now that the cat has probed the Voyager System Bus, sanity
651 * check the cpu map */
652 if (((voyager_quad_processors | voyager_extended_vic_processors)
653 & cpus_addr(phys_cpu_present_map)[0]) !=
654 cpus_addr(phys_cpu_present_map)[0]) {
656 printk("\n\n***WARNING*** "
657 "Sanity check of CPU present map FAILED\n");
659 } else if (voyager_level == 4)
660 voyager_extended_vic_processors =
661 cpus_addr(phys_cpu_present_map)[0];
663 /* this sets up the idle task to run on the current cpu */
664 voyager_extended_cpus = 1;
665 /* Remove the global_irq_holder setting, it triggers a BUG() on
666 * schedule at the moment */
667 //global_irq_holder = boot_cpu_id;
669 /* FIXME: Need to do something about this but currently only works
670 * on CPUs with a tsc which none of mine have.
671 smp_tune_scheduling();
673 smp_store_cpu_info(boot_cpu_id);
674 printk("CPU%d: ", boot_cpu_id);
675 print_cpu_info(&cpu_data(boot_cpu_id));
678 /* booting on a Quad CPU */
679 printk("VOYAGER SMP: Boot CPU is Quad\n");
684 /* enable our own CPIs */
687 cpu_set(boot_cpu_id, cpu_online_map);
688 cpu_set(boot_cpu_id, cpu_callout_map);
690 /* loop over all the extended VIC CPUs and boot them. The
691 * Quad CPUs must be bootstrapped by their extended VIC cpu */
692 for (i = 0; i < NR_CPUS; i++) {
693 if (i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
696 /* This udelay seems to be needed for the Quad boots
697 * don't remove unless you know what you're doing */
700 /* we could compute the total bogomips here, but why bother?,
701 * Code added from smpboot.c */
703 unsigned long bogosum = 0;
704 for (i = 0; i < NR_CPUS; i++)
705 if (cpu_isset(i, cpu_online_map))
706 bogosum += cpu_data(i).loops_per_jiffy;
707 printk(KERN_INFO "Total of %d processors activated "
708 "(%lu.%02lu BogoMIPS).\n",
709 cpucount + 1, bogosum / (500000 / HZ),
710 (bogosum / (5000 / HZ)) % 100);
712 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
713 printk("VOYAGER: Extended (interrupt handling CPUs): "
714 "%d, non-extended: %d\n", voyager_extended_cpus,
715 num_booting_cpus() - voyager_extended_cpus);
716 /* that's it, switch to symmetric mode */
717 outb(0, VIC_PRIORITY_REGISTER);
718 outb(0, VIC_CLAIM_REGISTER_0);
719 outb(0, VIC_CLAIM_REGISTER_1);
721 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
724 /* Reload the secondary CPUs task structure (this function does not
726 void __init initialize_secondary(void)
730 set_current(hard_get_current());
734 * We don't actually need to load the full TSS,
735 * basically just the stack pointer and the eip.
738 asm volatile ("movl %0,%%esp\n\t"
739 "jmp *%1"::"r" (current->thread.sp),
740 "r"(current->thread.ip));
743 /* handle a Voyager SYS_INT -- If we don't, the base board will
746 * System interrupts occur because some problem was detected on the
747 * various busses. To find out what you have to probe all the
748 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
749 void smp_vic_sys_interrupt(struct pt_regs *regs)
751 ack_CPI(VIC_SYS_INT);
752 printk("Voyager SYSTEM INTERRUPT\n");
755 /* Handle a voyager CMN_INT; These interrupts occur either because of
756 * a system status change or because a single bit memory error
757 * occurred. FIXME: At the moment, ignore all this. */
758 void smp_vic_cmn_interrupt(struct pt_regs *regs)
760 static __u8 in_cmn_int = 0;
761 static DEFINE_SPINLOCK(cmn_int_lock);
763 /* common ints are broadcast, so make sure we only do this once */
764 _raw_spin_lock(&cmn_int_lock);
769 _raw_spin_unlock(&cmn_int_lock);
771 VDEBUG(("Voyager COMMON INTERRUPT\n"));
773 if (voyager_level == 5)
774 voyager_cat_do_common_interrupt();
776 _raw_spin_lock(&cmn_int_lock);
779 _raw_spin_unlock(&cmn_int_lock);
780 ack_CPI(VIC_CMN_INT);
784 * Reschedule call back. Nothing to do, all the work is done
785 * automatically when we return from the interrupt. */
786 static void smp_reschedule_interrupt(void)
791 static struct mm_struct *flush_mm;
792 static unsigned long flush_va;
793 static DEFINE_SPINLOCK(tlbstate_lock);
796 * We cannot call mmdrop() because we are in interrupt context,
797 * instead update mm->cpu_vm_mask.
799 * We need to reload %cr3 since the page tables may be going
800 * away from under us..
802 static inline void voyager_leave_mm(unsigned long cpu)
804 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
806 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
807 load_cr3(swapper_pg_dir);
811 * Invalidate call-back
813 static void smp_invalidate_interrupt(void)
815 __u8 cpu = smp_processor_id();
817 if (!test_bit(cpu, &smp_invalidate_needed))
819 /* This will flood messages. Don't uncomment unless you see
820 * Problems with cross cpu invalidation
821 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
822 smp_processor_id()));
825 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
826 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
827 if (flush_va == TLB_FLUSH_ALL)
830 __flush_tlb_one(flush_va);
832 voyager_leave_mm(cpu);
834 smp_mb__before_clear_bit();
835 clear_bit(cpu, &smp_invalidate_needed);
836 smp_mb__after_clear_bit();
839 /* All the new flush operations for 2.4 */
841 /* This routine is called with a physical cpu mask */
843 voyager_flush_tlb_others(unsigned long cpumask, struct mm_struct *mm,
850 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
852 if (cpumask & (1 << smp_processor_id()))
857 spin_lock(&tlbstate_lock);
861 atomic_set_mask(cpumask, &smp_invalidate_needed);
863 * We have to send the CPI only to
866 send_CPI(cpumask, VIC_INVALIDATE_CPI);
868 while (smp_invalidate_needed) {
871 printk("***WARNING*** Stuck doing invalidate CPI "
872 "(CPU%d)\n", smp_processor_id());
877 /* Uncomment only to debug invalidation problems
878 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
883 spin_unlock(&tlbstate_lock);
886 void flush_tlb_current_task(void)
888 struct mm_struct *mm = current->mm;
889 unsigned long cpu_mask;
893 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
896 voyager_flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
901 void flush_tlb_mm(struct mm_struct *mm)
903 unsigned long cpu_mask;
907 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
909 if (current->active_mm == mm) {
913 voyager_leave_mm(smp_processor_id());
916 voyager_flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
921 void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
923 struct mm_struct *mm = vma->vm_mm;
924 unsigned long cpu_mask;
928 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
929 if (current->active_mm == mm) {
933 voyager_leave_mm(smp_processor_id());
937 voyager_flush_tlb_others(cpu_mask, mm, va);
942 EXPORT_SYMBOL(flush_tlb_page);
944 /* enable the requested IRQs */
945 static void smp_enable_irq_interrupt(void)
948 __u8 cpu = get_cpu();
950 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
951 vic_irq_enable_mask[cpu]));
953 spin_lock(&vic_irq_lock);
954 for (irq = 0; irq < 16; irq++) {
955 if (vic_irq_enable_mask[cpu] & (1 << irq))
956 enable_local_vic_irq(irq);
958 vic_irq_enable_mask[cpu] = 0;
959 spin_unlock(&vic_irq_lock);
961 put_cpu_no_resched();
967 static void smp_stop_cpu_function(void *dummy)
969 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
970 cpu_clear(smp_processor_id(), cpu_online_map);
976 static DEFINE_SPINLOCK(call_lock);
978 struct call_data_struct {
979 void (*func) (void *info);
981 volatile unsigned long started;
982 volatile unsigned long finished;
986 static struct call_data_struct *call_data;
988 /* execute a thread on a new CPU. The function to be called must be
989 * previously set up. This is used to schedule a function for
990 * execution on all CPUs - set up the function then broadcast a
991 * function_interrupt CPI to come here on each CPU */
992 static void smp_call_function_interrupt(void)
994 void (*func) (void *info) = call_data->func;
995 void *info = call_data->info;
996 /* must take copy of wait because call_data may be replaced
997 * unless the function is waiting for us to finish */
998 int wait = call_data->wait;
999 __u8 cpu = smp_processor_id();
1002 * Notify initiating CPU that I've grabbed the data and am
1003 * about to execute the function
1006 if (!test_and_clear_bit(cpu, &call_data->started)) {
1007 /* If the bit wasn't set, this could be a replay */
1008 printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion"
1009 " with no call pending\n", cpu);
1013 * At this point the info structure may be out of scope unless wait==1
1017 __get_cpu_var(irq_stat).irq_call_count++;
1021 clear_bit(cpu, &call_data->finished);
1026 voyager_smp_call_function_mask(cpumask_t cpumask,
1027 void (*func) (void *info), void *info, int wait)
1029 struct call_data_struct data;
1030 u32 mask = cpus_addr(cpumask)[0];
1032 mask &= ~(1 << smp_processor_id());
1037 /* Can deadlock when called with interrupts disabled */
1038 WARN_ON(irqs_disabled());
1042 data.started = mask;
1045 data.finished = mask;
1047 spin_lock(&call_lock);
1050 /* Send a message to all other CPUs and wait for them to respond */
1051 send_CPI(mask, VIC_CALL_FUNCTION_CPI);
1053 /* Wait for response */
1054 while (data.started)
1058 while (data.finished)
1061 spin_unlock(&call_lock);
1066 /* Sorry about the name. In an APIC based system, the APICs
1067 * themselves are programmed to send a timer interrupt. This is used
1068 * by linux to reschedule the processor. Voyager doesn't have this,
1069 * so we use the system clock to interrupt one processor, which in
1070 * turn, broadcasts a timer CPI to all the others --- we receive that
1071 * CPI here. We don't use this actually for counting so losing
1072 * ticks doesn't matter
1074 * FIXME: For those CPUs which actually have a local APIC, we could
1075 * try to use it to trigger this interrupt instead of having to
1076 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1077 * no local APIC, so I can't do this
1079 * This function is currently a placeholder and is unused in the code */
1080 void smp_apic_timer_interrupt(struct pt_regs *regs)
1082 struct pt_regs *old_regs = set_irq_regs(regs);
1083 wrapper_smp_local_timer_interrupt();
1084 set_irq_regs(old_regs);
1087 /* All of the QUAD interrupt GATES */
1088 void smp_qic_timer_interrupt(struct pt_regs *regs)
1090 struct pt_regs *old_regs = set_irq_regs(regs);
1091 ack_QIC_CPI(QIC_TIMER_CPI);
1092 wrapper_smp_local_timer_interrupt();
1093 set_irq_regs(old_regs);
1096 void smp_qic_invalidate_interrupt(struct pt_regs *regs)
1098 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1099 smp_invalidate_interrupt();
1102 void smp_qic_reschedule_interrupt(struct pt_regs *regs)
1104 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1105 smp_reschedule_interrupt();
1108 void smp_qic_enable_irq_interrupt(struct pt_regs *regs)
1110 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1111 smp_enable_irq_interrupt();
1114 void smp_qic_call_function_interrupt(struct pt_regs *regs)
1116 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1117 smp_call_function_interrupt();
1120 void smp_vic_cpi_interrupt(struct pt_regs *regs)
1122 struct pt_regs *old_regs = set_irq_regs(regs);
1123 __u8 cpu = smp_processor_id();
1126 ack_QIC_CPI(VIC_CPI_LEVEL0);
1128 ack_VIC_CPI(VIC_CPI_LEVEL0);
1130 if (test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1131 wrapper_smp_local_timer_interrupt();
1132 if (test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1133 smp_invalidate_interrupt();
1134 if (test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1135 smp_reschedule_interrupt();
1136 if (test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1137 smp_enable_irq_interrupt();
1138 if (test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1139 smp_call_function_interrupt();
1140 set_irq_regs(old_regs);
1143 static void do_flush_tlb_all(void *info)
1145 unsigned long cpu = smp_processor_id();
1148 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1149 voyager_leave_mm(cpu);
1152 /* flush the TLB of every active CPU in the system */
1153 void flush_tlb_all(void)
1155 on_each_cpu(do_flush_tlb_all, 0, 1, 1);
1158 /* used to set up the trampoline for other CPUs when the memory manager
1160 void __init smp_alloc_memory(void)
1162 trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE);
1163 if (__pa(trampoline_base) >= 0x93000)
1167 /* send a reschedule CPI to one CPU by physical CPU number*/
1168 static void voyager_smp_send_reschedule(int cpu)
1170 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1173 int hard_smp_processor_id(void)
1176 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1177 if ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1178 return cpumask & 0x1F;
1180 for (i = 0; i < 8; i++) {
1181 if (cpumask & (1 << i))
1184 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1188 int safe_smp_processor_id(void)
1190 return hard_smp_processor_id();
1193 /* broadcast a halt to all other CPUs */
1194 static void voyager_smp_send_stop(void)
1196 smp_call_function(smp_stop_cpu_function, NULL, 1, 1);
1199 /* this function is triggered in time.c when a clock tick fires
1200 * we need to re-broadcast the tick to all CPUs */
1201 void smp_vic_timer_interrupt(void)
1203 send_CPI_allbutself(VIC_TIMER_CPI);
1204 smp_local_timer_interrupt();
1207 /* local (per CPU) timer interrupt. It does both profiling and
1208 * process statistics/rescheduling.
1210 * We do profiling in every local tick, statistics/rescheduling
1211 * happen only every 'profiling multiplier' ticks. The default
1212 * multiplier is 1 and it can be changed by writing the new multiplier
1213 * value into /proc/profile.
1215 void smp_local_timer_interrupt(void)
1217 int cpu = smp_processor_id();
1220 profile_tick(CPU_PROFILING);
1221 if (--per_cpu(prof_counter, cpu) <= 0) {
1223 * The multiplier may have changed since the last time we got
1224 * to this point as a result of the user writing to
1225 * /proc/profile. In this case we need to adjust the APIC
1226 * timer accordingly.
1228 * Interrupts are already masked off at this point.
1230 per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
1231 if (per_cpu(prof_counter, cpu) !=
1232 per_cpu(prof_old_multiplier, cpu)) {
1233 /* FIXME: need to update the vic timer tick here */
1234 per_cpu(prof_old_multiplier, cpu) =
1235 per_cpu(prof_counter, cpu);
1238 update_process_times(user_mode_vm(get_irq_regs()));
1241 if (((1 << cpu) & voyager_extended_vic_processors) == 0)
1242 /* only extended VIC processors participate in
1243 * interrupt distribution */
1247 * We take the 'long' return path, and there every subsystem
1248 * grabs the appropriate locks (kernel lock/ irq lock).
1250 * we might want to decouple profiling from the 'long path',
1251 * and do the profiling totally in assembly.
1253 * Currently this isn't too much of an issue (performance wise),
1254 * we can take more than 100K local irqs per second on a 100 MHz P5.
1257 if ((++vic_tick[cpu] & 0x7) != 0)
1259 /* get here every 16 ticks (about every 1/6 of a second) */
1261 /* Change our priority to give someone else a chance at getting
1262 * the IRQ. The algorithm goes like this:
1264 * In the VIC, the dynamically routed interrupt is always
1265 * handled by the lowest priority eligible (i.e. receiving
1266 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1267 * lowest processor number gets it.
1269 * The priority of a CPU is controlled by a special per-CPU
1270 * VIC priority register which is 3 bits wide 0 being lowest
1271 * and 7 highest priority..
1273 * Therefore we subtract the average number of interrupts from
1274 * the number we've fielded. If this number is negative, we
1275 * lower the activity count and if it is positive, we raise
1278 * I'm afraid this still leads to odd looking interrupt counts:
1279 * the totals are all roughly equal, but the individual ones
1280 * look rather skewed.
1282 * FIXME: This algorithm is total crap when mixed with SMP
1283 * affinity code since we now try to even up the interrupt
1284 * counts when an affinity binding is keeping them on a
1286 weight = (vic_intr_count[cpu] * voyager_extended_cpus
1287 - vic_intr_total) >> 4;
1294 outb((__u8) weight, VIC_PRIORITY_REGISTER);
1296 #ifdef VOYAGER_DEBUG
1297 if ((vic_tick[cpu] & 0xFFF) == 0) {
1298 /* print this message roughly every 25 secs */
1299 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1300 cpu, vic_tick[cpu], weight);
1305 /* setup the profiling timer */
1306 int setup_profiling_timer(unsigned int multiplier)
1314 * Set the new multiplier for each CPU. CPUs don't start using the
1315 * new values until the next timer interrupt in which they do process
1318 for (i = 0; i < NR_CPUS; ++i)
1319 per_cpu(prof_multiplier, i) = multiplier;
1324 /* This is a bit of a mess, but forced on us by the genirq changes
1325 * there's no genirq handler that really does what voyager wants
1326 * so hack it up with the simple IRQ handler */
1327 static void handle_vic_irq(unsigned int irq, struct irq_desc *desc)
1329 before_handle_vic_irq(irq);
1330 handle_simple_irq(irq, desc);
1331 after_handle_vic_irq(irq);
1334 /* The CPIs are handled in the per cpu 8259s, so they must be
1335 * enabled to be received: FIX: enabling the CPIs in the early
1336 * boot sequence interferes with bug checking; enable them later
1338 #define VIC_SET_GATE(cpi, vector) \
1339 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1340 #define QIC_SET_GATE(cpi, vector) \
1341 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1343 void __init smp_intr_init(void)
1347 /* initialize the per cpu irq mask to all disabled */
1348 for (i = 0; i < NR_CPUS; i++)
1349 vic_irq_mask[i] = 0xFFFF;
1351 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1353 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1354 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1356 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1357 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1358 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1359 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1360 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1362 /* now put the VIC descriptor into the first 48 IRQs
1364 * This is for later: first 16 correspond to PC IRQs; next 16
1365 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1366 for (i = 0; i < 48; i++)
1367 set_irq_chip_and_handler(i, &vic_chip, handle_vic_irq);
1370 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1371 * processor to receive CPI */
1372 static void send_CPI(__u32 cpuset, __u8 cpi)
1375 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1377 if (cpi < VIC_START_FAKE_CPI) {
1378 /* fake CPI are only used for booting, so send to the
1379 * extended quads as well---Quads must be VIC booted */
1380 outb((__u8) (cpuset), VIC_CPI_Registers[cpi]);
1384 send_QIC_CPI(quad_cpuset, cpi);
1385 cpuset &= ~quad_cpuset;
1386 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1389 for_each_online_cpu(cpu) {
1390 if (cpuset & (1 << cpu))
1391 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1394 outb((__u8) cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1397 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1398 * set the cache line to shared by reading it.
1400 * DON'T make this inline otherwise the cache line read will be
1403 static int ack_QIC_CPI(__u8 cpi)
1405 __u8 cpu = hard_smp_processor_id();
1409 outb(1 << cpi, QIC_INTERRUPT_CLEAR1);
1410 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1413 static void ack_special_QIC_CPI(__u8 cpi)
1417 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1420 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1423 /* also clear at the VIC, just in case (nop for non-extended proc) */
1427 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1428 static void ack_VIC_CPI(__u8 cpi)
1430 #ifdef VOYAGER_DEBUG
1431 unsigned long flags;
1433 __u8 cpu = smp_processor_id();
1435 local_irq_save(flags);
1436 isr = vic_read_isr();
1437 if ((isr & (1 << (cpi & 7))) == 0) {
1438 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1441 /* send specific EOI; the two system interrupts have
1442 * bit 4 set for a separate vector but behave as the
1443 * corresponding 3 bit intr */
1444 outb_p(0x60 | (cpi & 7), 0x20);
1446 #ifdef VOYAGER_DEBUG
1447 if ((vic_read_isr() & (1 << (cpi & 7))) != 0) {
1448 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1450 local_irq_restore(flags);
1454 /* cribbed with thanks from irq.c */
1455 #define __byte(x,y) (((unsigned char *)&(y))[x])
1456 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1457 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1459 static unsigned int startup_vic_irq(unsigned int irq)
1461 unmask_vic_irq(irq);
1466 /* The enable and disable routines. This is where we run into
1467 * conflicting architectural philosophy. Fundamentally, the voyager
1468 * architecture does not expect to have to disable interrupts globally
1469 * (the IRQ controllers belong to each CPU). The processor masquerade
1470 * which is used to start the system shouldn't be used in a running OS
1471 * since it will cause great confusion if two separate CPUs drive to
1472 * the same IRQ controller (I know, I've tried it).
1474 * The solution is a variant on the NCR lazy SPL design:
1476 * 1) To disable an interrupt, do nothing (other than set the
1477 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1479 * 2) If the interrupt dares to come in, raise the local mask against
1480 * it (this will result in all the CPU masks being raised
1483 * 3) To enable the interrupt, lower the mask on the local CPU and
1484 * broadcast an Interrupt enable CPI which causes all other CPUs to
1485 * adjust their masks accordingly. */
1487 static void unmask_vic_irq(unsigned int irq)
1489 /* linux doesn't to processor-irq affinity, so enable on
1490 * all CPUs we know about */
1491 int cpu = smp_processor_id(), real_cpu;
1492 __u16 mask = (1 << irq);
1493 __u32 processorList = 0;
1494 unsigned long flags;
1496 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
1497 irq, cpu, cpu_irq_affinity[cpu]));
1498 spin_lock_irqsave(&vic_irq_lock, flags);
1499 for_each_online_cpu(real_cpu) {
1500 if (!(voyager_extended_vic_processors & (1 << real_cpu)))
1502 if (!(cpu_irq_affinity[real_cpu] & mask)) {
1503 /* irq has no affinity for this CPU, ignore */
1506 if (real_cpu == cpu) {
1507 enable_local_vic_irq(irq);
1508 } else if (vic_irq_mask[real_cpu] & mask) {
1509 vic_irq_enable_mask[real_cpu] |= mask;
1510 processorList |= (1 << real_cpu);
1513 spin_unlock_irqrestore(&vic_irq_lock, flags);
1515 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1518 static void mask_vic_irq(unsigned int irq)
1520 /* lazy disable, do nothing */
1523 static void enable_local_vic_irq(unsigned int irq)
1525 __u8 cpu = smp_processor_id();
1526 __u16 mask = ~(1 << irq);
1527 __u16 old_mask = vic_irq_mask[cpu];
1529 vic_irq_mask[cpu] &= mask;
1530 if (vic_irq_mask[cpu] == old_mask)
1533 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1537 outb_p(cached_A1(cpu), 0xA1);
1540 outb_p(cached_21(cpu), 0x21);
1545 static void disable_local_vic_irq(unsigned int irq)
1547 __u8 cpu = smp_processor_id();
1548 __u16 mask = (1 << irq);
1549 __u16 old_mask = vic_irq_mask[cpu];
1554 vic_irq_mask[cpu] |= mask;
1555 if (old_mask == vic_irq_mask[cpu])
1558 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1562 outb_p(cached_A1(cpu), 0xA1);
1565 outb_p(cached_21(cpu), 0x21);
1570 /* The VIC is level triggered, so the ack can only be issued after the
1571 * interrupt completes. However, we do Voyager lazy interrupt
1572 * handling here: It is an extremely expensive operation to mask an
1573 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1574 * this interrupt actually comes in, then we mask and ack here to push
1575 * the interrupt off to another CPU */
1576 static void before_handle_vic_irq(unsigned int irq)
1578 irq_desc_t *desc = irq_desc + irq;
1579 __u8 cpu = smp_processor_id();
1581 _raw_spin_lock(&vic_irq_lock);
1583 vic_intr_count[cpu]++;
1585 if (!(cpu_irq_affinity[cpu] & (1 << irq))) {
1586 /* The irq is not in our affinity mask, push it off
1587 * onto another CPU */
1588 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d "
1589 "on cpu %d\n", irq, cpu));
1590 disable_local_vic_irq(irq);
1591 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1592 * actually calling the interrupt routine */
1593 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1594 } else if (desc->status & IRQ_DISABLED) {
1595 /* Damn, the interrupt actually arrived, do the lazy
1596 * disable thing. The interrupt routine in irq.c will
1597 * not handle a IRQ_DISABLED interrupt, so nothing more
1598 * need be done here */
1599 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1601 disable_local_vic_irq(irq);
1602 desc->status |= IRQ_REPLAY;
1604 desc->status &= ~IRQ_REPLAY;
1607 _raw_spin_unlock(&vic_irq_lock);
1610 /* Finish the VIC interrupt: basically mask */
1611 static void after_handle_vic_irq(unsigned int irq)
1613 irq_desc_t *desc = irq_desc + irq;
1615 _raw_spin_lock(&vic_irq_lock);
1617 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1618 #ifdef VOYAGER_DEBUG
1622 desc->status = status;
1623 if ((status & IRQ_DISABLED))
1624 disable_local_vic_irq(irq);
1625 #ifdef VOYAGER_DEBUG
1626 /* DEBUG: before we ack, check what's in progress */
1627 isr = vic_read_isr();
1628 if ((isr & (1 << irq) && !(status & IRQ_REPLAY)) == 0) {
1630 __u8 cpu = smp_processor_id();
1632 int mask; /* Um... initialize me??? --RR */
1634 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1636 for_each_possible_cpu(real_cpu, mask) {
1638 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1640 isr = vic_read_isr();
1641 if (isr & (1 << irq)) {
1643 ("VOYAGER SMP: CPU%d ack irq %d\n",
1647 outb(cpu, VIC_PROCESSOR_ID);
1650 #endif /* VOYAGER_DEBUG */
1651 /* as soon as we ack, the interrupt is eligible for
1652 * receipt by another CPU so everything must be in
1655 if (status & IRQ_REPLAY) {
1656 /* replay is set if we disable the interrupt
1657 * in the before_handle_vic_irq() routine, so
1658 * clear the in progress bit here to allow the
1659 * next CPU to handle this correctly */
1660 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1662 #ifdef VOYAGER_DEBUG
1663 isr = vic_read_isr();
1664 if ((isr & (1 << irq)) != 0)
1665 printk("VOYAGER SMP: after_handle_vic_irq() after "
1666 "ack irq=%d, isr=0x%x\n", irq, isr);
1667 #endif /* VOYAGER_DEBUG */
1669 _raw_spin_unlock(&vic_irq_lock);
1671 /* All code after this point is out of the main path - the IRQ
1672 * may be intercepted by another CPU if reasserted */
1675 /* Linux processor - interrupt affinity manipulations.
1677 * For each processor, we maintain a 32 bit irq affinity mask.
1678 * Initially it is set to all 1's so every processor accepts every
1679 * interrupt. In this call, we change the processor's affinity mask:
1681 * Change from enable to disable:
1683 * If the interrupt ever comes in to the processor, we will disable it
1684 * and ack it to push it off to another CPU, so just accept the mask here.
1686 * Change from disable to enable:
1688 * change the mask and then do an interrupt enable CPI to re-enable on
1689 * the selected processors */
1691 void set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1693 /* Only extended processors handle interrupts */
1694 unsigned long real_mask;
1695 unsigned long irq_mask = 1 << irq;
1698 real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1700 if (cpus_addr(mask)[0] == 0)
1701 /* can't have no CPUs to accept the interrupt -- extremely
1702 * bad things will happen */
1706 /* can't change the affinity of the timer IRQ. This
1707 * is due to the constraint in the voyager
1708 * architecture that the CPI also comes in on and IRQ
1709 * line and we have chosen IRQ0 for this. If you
1710 * raise the mask on this interrupt, the processor
1711 * will no-longer be able to accept VIC CPIs */
1715 /* You can only have 32 interrupts in a voyager system
1716 * (and 32 only if you have a secondary microchannel
1720 for_each_online_cpu(cpu) {
1721 unsigned long cpu_mask = 1 << cpu;
1723 if (cpu_mask & real_mask) {
1724 /* enable the interrupt for this cpu */
1725 cpu_irq_affinity[cpu] |= irq_mask;
1727 /* disable the interrupt for this cpu */
1728 cpu_irq_affinity[cpu] &= ~irq_mask;
1731 /* this is magic, we now have the correct affinity maps, so
1732 * enable the interrupt. This will send an enable CPI to
1733 * those CPUs who need to enable it in their local masks,
1734 * causing them to correct for the new affinity . If the
1735 * interrupt is currently globally disabled, it will simply be
1736 * disabled again as it comes in (voyager lazy disable). If
1737 * the affinity map is tightened to disable the interrupt on a
1738 * cpu, it will be pushed off when it comes in */
1739 unmask_vic_irq(irq);
1742 static void ack_vic_irq(unsigned int irq)
1745 outb(0x62, 0x20); /* Specific EOI to cascade */
1746 outb(0x60 | (irq & 7), 0xA0);
1748 outb(0x60 | (irq & 7), 0x20);
1752 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1753 * but are not vectored by it. This means that the 8259 mask must be
1754 * lowered to receive them */
1755 static __init void vic_enable_cpi(void)
1757 __u8 cpu = smp_processor_id();
1759 /* just take a copy of the current mask (nop for boot cpu) */
1760 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1762 enable_local_vic_irq(VIC_CPI_LEVEL0);
1763 enable_local_vic_irq(VIC_CPI_LEVEL1);
1764 /* for sys int and cmn int */
1765 enable_local_vic_irq(7);
1767 if (is_cpu_quad()) {
1768 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1769 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1770 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1771 cpu, QIC_CPI_ENABLE));
1774 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1775 cpu, vic_irq_mask[cpu]));
1778 void voyager_smp_dump()
1780 int old_cpu = smp_processor_id(), cpu;
1782 /* dump the interrupt masks of each processor */
1783 for_each_online_cpu(cpu) {
1784 __u16 imr, isr, irr;
1785 unsigned long flags;
1787 local_irq_save(flags);
1788 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1789 imr = (inb(0xa1) << 8) | inb(0x21);
1791 irr = inb(0xa0) << 8;
1795 isr = inb(0xa0) << 8;
1798 outb(old_cpu, VIC_PROCESSOR_ID);
1799 local_irq_restore(flags);
1800 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1801 cpu, vic_irq_mask[cpu], imr, irr, isr);
1803 /* These lines are put in to try to unstick an un ack'd irq */
1806 for (irq = 0; irq < 16; irq++) {
1807 if (isr & (1 << irq)) {
1808 printk("\tCPU%d: ack irq %d\n",
1810 local_irq_save(flags);
1811 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1814 outb(old_cpu, VIC_PROCESSOR_ID);
1815 local_irq_restore(flags);
1823 void smp_voyager_power_off(void *dummy)
1825 if (smp_processor_id() == boot_cpu_id)
1826 voyager_power_off();
1828 smp_stop_cpu_function(NULL);
1831 static void __init voyager_smp_prepare_cpus(unsigned int max_cpus)
1833 /* FIXME: ignore max_cpus for now */
1837 static void __cpuinit voyager_smp_prepare_boot_cpu(void)
1839 init_gdt(smp_processor_id());
1840 switch_to_new_gdt();
1842 cpu_set(smp_processor_id(), cpu_online_map);
1843 cpu_set(smp_processor_id(), cpu_callout_map);
1844 cpu_set(smp_processor_id(), cpu_possible_map);
1845 cpu_set(smp_processor_id(), cpu_present_map);
1848 static int __cpuinit voyager_cpu_up(unsigned int cpu)
1850 /* This only works at boot for x86. See "rewrite" above. */
1851 if (cpu_isset(cpu, smp_commenced_mask))
1854 /* In case one didn't come up */
1855 if (!cpu_isset(cpu, cpu_callin_map))
1857 /* Unleash the CPU! */
1858 cpu_set(cpu, smp_commenced_mask);
1859 while (!cpu_isset(cpu, cpu_online_map))
1864 static void __init voyager_smp_cpus_done(unsigned int max_cpus)
1869 void __init smp_setup_processor_id(void)
1871 current_thread_info()->cpu = hard_smp_processor_id();
1872 x86_write_percpu(cpu_number, hard_smp_processor_id());
1875 struct smp_ops smp_ops = {
1876 .smp_prepare_boot_cpu = voyager_smp_prepare_boot_cpu,
1877 .smp_prepare_cpus = voyager_smp_prepare_cpus,
1878 .cpu_up = voyager_cpu_up,
1879 .smp_cpus_done = voyager_smp_cpus_done,
1881 .smp_send_stop = voyager_smp_send_stop,
1882 .smp_send_reschedule = voyager_smp_send_reschedule,
1883 .smp_call_function_mask = voyager_smp_call_function_mask,