2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
10 #include <linux/interrupt.h>
11 #include <linux/seq_file.h>
12 #include <linux/debugfs.h>
13 #include <linux/pfn.h>
14 #include <linux/percpu.h>
15 #include <linux/gfp.h>
16 #include <linux/pci.h>
19 #include <asm/processor.h>
20 #include <asm/tlbflush.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <asm/uaccess.h>
24 #include <asm/pgalloc.h>
25 #include <asm/proto.h>
29 * The current flushing context - we pass it instead of 5 arguments:
38 unsigned force_split : 1;
44 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
45 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
46 * entries change the page attribute in parallel to some other cpu
47 * splitting a large page entry along with changing the attribute.
49 static DEFINE_SPINLOCK(cpa_lock);
51 #define CPA_FLUSHTLB 1
53 #define CPA_PAGES_ARRAY 4
56 static unsigned long direct_pages_count[PG_LEVEL_NUM];
58 void update_page_count(int level, unsigned long pages)
60 /* Protect against CPA */
62 direct_pages_count[level] += pages;
63 spin_unlock(&pgd_lock);
66 static void split_page_count(int level)
68 direct_pages_count[level]--;
69 direct_pages_count[level - 1] += PTRS_PER_PTE;
72 void arch_report_meminfo(struct seq_file *m)
74 seq_printf(m, "DirectMap4k: %8lu kB\n",
75 direct_pages_count[PG_LEVEL_4K] << 2);
76 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
77 seq_printf(m, "DirectMap2M: %8lu kB\n",
78 direct_pages_count[PG_LEVEL_2M] << 11);
80 seq_printf(m, "DirectMap4M: %8lu kB\n",
81 direct_pages_count[PG_LEVEL_2M] << 12);
85 seq_printf(m, "DirectMap1G: %8lu kB\n",
86 direct_pages_count[PG_LEVEL_1G] << 20);
90 static inline void split_page_count(int level) { }
95 static inline unsigned long highmap_start_pfn(void)
97 return __pa_symbol(_text) >> PAGE_SHIFT;
100 static inline unsigned long highmap_end_pfn(void)
102 return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
107 #ifdef CONFIG_DEBUG_PAGEALLOC
108 # define debug_pagealloc 1
110 # define debug_pagealloc 0
114 within(unsigned long addr, unsigned long start, unsigned long end)
116 return addr >= start && addr < end;
124 * clflush_cache_range - flush a cache range with clflush
125 * @vaddr: virtual start address
126 * @size: number of bytes to flush
128 * clflush is an unordered instruction which needs fencing with mfence
129 * to avoid ordering issues.
131 void clflush_cache_range(void *vaddr, unsigned int size)
133 void *vend = vaddr + size - 1;
137 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
140 * Flush any possible final partial cacheline:
146 EXPORT_SYMBOL_GPL(clflush_cache_range);
148 static void __cpa_flush_all(void *arg)
150 unsigned long cache = (unsigned long)arg;
153 * Flush all to work around Errata in early athlons regarding
154 * large page flushing.
158 if (cache && boot_cpu_data.x86 >= 4)
162 static void cpa_flush_all(unsigned long cache)
164 BUG_ON(irqs_disabled());
166 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
169 static void __cpa_flush_range(void *arg)
172 * We could optimize that further and do individual per page
173 * tlb invalidates for a low number of pages. Caveat: we must
174 * flush the high aliases on 64bit as well.
179 static void cpa_flush_range(unsigned long start, int numpages, int cache)
181 unsigned int i, level;
184 BUG_ON(irqs_disabled());
185 WARN_ON(PAGE_ALIGN(start) != start);
187 on_each_cpu(__cpa_flush_range, NULL, 1);
193 * We only need to flush on one CPU,
194 * clflush is a MESI-coherent instruction that
195 * will cause all other CPUs to flush the same
198 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
199 pte_t *pte = lookup_address(addr, &level);
202 * Only flush present addresses:
204 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
205 clflush_cache_range((void *) addr, PAGE_SIZE);
209 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
210 int in_flags, struct page **pages)
212 unsigned int i, level;
213 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
215 BUG_ON(irqs_disabled());
217 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
219 if (!cache || do_wbinvd)
223 * We only need to flush on one CPU,
224 * clflush is a MESI-coherent instruction that
225 * will cause all other CPUs to flush the same
228 for (i = 0; i < numpages; i++) {
232 if (in_flags & CPA_PAGES_ARRAY)
233 addr = (unsigned long)page_address(pages[i]);
237 pte = lookup_address(addr, &level);
240 * Only flush present addresses:
242 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
243 clflush_cache_range((void *)addr, PAGE_SIZE);
248 * Certain areas of memory on x86 require very specific protection flags,
249 * for example the BIOS area or kernel text. Callers don't always get this
250 * right (again, ioremap() on BIOS memory is not uncommon) so this function
251 * checks and fixes these known static required protection bits.
253 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
256 pgprot_t forbidden = __pgprot(0);
259 * The BIOS area between 640k and 1Mb needs to be executable for
260 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
262 #ifdef CONFIG_PCI_BIOS
263 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
264 pgprot_val(forbidden) |= _PAGE_NX;
268 * The kernel text needs to be executable for obvious reasons
269 * Does not cover __inittext since that is gone later on. On
270 * 64bit we do not enforce !NX on the low mapping
272 if (within(address, (unsigned long)_text, (unsigned long)_etext))
273 pgprot_val(forbidden) |= _PAGE_NX;
276 * The .rodata section needs to be read-only. Using the pfn
277 * catches all aliases.
279 if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
280 __pa_symbol(__end_rodata) >> PAGE_SHIFT))
281 pgprot_val(forbidden) |= _PAGE_RW;
283 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
285 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
286 * kernel text mappings for the large page aligned text, rodata sections
287 * will be always read-only. For the kernel identity mappings covering
288 * the holes caused by this alignment can be anything that user asks.
290 * This will preserve the large page mappings for kernel text/data
293 if (kernel_set_to_readonly &&
294 within(address, (unsigned long)_text,
295 (unsigned long)__end_rodata_hpage_align)) {
299 * Don't enforce the !RW mapping for the kernel text mapping,
300 * if the current mapping is already using small page mapping.
301 * No need to work hard to preserve large page mappings in this
304 * This also fixes the Linux Xen paravirt guest boot failure
305 * (because of unexpected read-only mappings for kernel identity
306 * mappings). In this paravirt guest case, the kernel text
307 * mapping and the kernel identity mapping share the same
308 * page-table pages. Thus we can't really use different
309 * protections for the kernel text and identity mappings. Also,
310 * these shared mappings are made of small page mappings.
311 * Thus this don't enforce !RW mapping for small page kernel
312 * text mapping logic will help Linux Xen parvirt guest boot
315 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
316 pgprot_val(forbidden) |= _PAGE_RW;
320 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
326 * Lookup the page table entry for a virtual address. Return a pointer
327 * to the entry and the level of the mapping.
329 * Note: We return pud and pmd either when the entry is marked large
330 * or when the present bit is not set. Otherwise we would return a
331 * pointer to a nonexisting mapping.
333 pte_t *lookup_address(unsigned long address, unsigned int *level)
335 pgd_t *pgd = pgd_offset_k(address);
339 *level = PG_LEVEL_NONE;
344 pud = pud_offset(pgd, address);
348 *level = PG_LEVEL_1G;
349 if (pud_large(*pud) || !pud_present(*pud))
352 pmd = pmd_offset(pud, address);
356 *level = PG_LEVEL_2M;
357 if (pmd_large(*pmd) || !pmd_present(*pmd))
360 *level = PG_LEVEL_4K;
362 return pte_offset_kernel(pmd, address);
364 EXPORT_SYMBOL_GPL(lookup_address);
367 * This is necessary because __pa() does not work on some
368 * kinds of memory, like vmalloc() or the alloc_remap()
369 * areas on 32-bit NUMA systems. The percpu areas can
370 * end up in this kind of memory, for instance.
372 * This could be optimized, but it is only intended to be
373 * used at inititalization time, and keeping it
374 * unoptimized should increase the testing coverage for
375 * the more obscure platforms.
377 phys_addr_t slow_virt_to_phys(void *__virt_addr)
379 unsigned long virt_addr = (unsigned long)__virt_addr;
380 phys_addr_t phys_addr;
381 unsigned long offset;
387 pte = lookup_address(virt_addr, &level);
389 psize = page_level_size(level);
390 pmask = page_level_mask(level);
391 offset = virt_addr & ~pmask;
392 phys_addr = pte_pfn(*pte) << PAGE_SHIFT;
393 return (phys_addr | offset);
395 EXPORT_SYMBOL_GPL(slow_virt_to_phys);
398 * Set the new pmd in all the pgds we know about:
400 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
403 set_pte_atomic(kpte, pte);
405 if (!SHARED_KERNEL_PMD) {
408 list_for_each_entry(page, &pgd_list, lru) {
413 pgd = (pgd_t *)page_address(page) + pgd_index(address);
414 pud = pud_offset(pgd, address);
415 pmd = pmd_offset(pud, address);
416 set_pte_atomic((pte_t *)pmd, pte);
423 try_preserve_large_page(pte_t *kpte, unsigned long address,
424 struct cpa_data *cpa)
426 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn;
427 pte_t new_pte, old_pte, *tmp;
428 pgprot_t old_prot, new_prot, req_prot;
432 if (cpa->force_split)
435 spin_lock(&pgd_lock);
437 * Check for races, another CPU might have split this page
440 tmp = lookup_address(address, &level);
449 psize = page_level_size(level);
450 pmask = page_level_mask(level);
458 * Calculate the number of pages, which fit into this large
459 * page starting at address:
461 nextpage_addr = (address + psize) & pmask;
462 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
463 if (numpages < cpa->numpages)
464 cpa->numpages = numpages;
467 * We are safe now. Check whether the new pgprot is the same:
470 old_prot = new_prot = req_prot = pte_pgprot(old_pte);
472 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
473 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
476 * Set the PSE and GLOBAL flags only if the PRESENT flag is
477 * set otherwise pmd_present/pmd_huge will return true even on
478 * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL
479 * for the ancient hardware that doesn't support it.
481 if (pgprot_val(new_prot) & _PAGE_PRESENT)
482 pgprot_val(new_prot) |= _PAGE_PSE | _PAGE_GLOBAL;
484 pgprot_val(new_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL);
486 new_prot = canon_pgprot(new_prot);
489 * old_pte points to the large page base address. So we need
490 * to add the offset of the virtual address:
492 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
495 new_prot = static_protections(req_prot, address, pfn);
498 * We need to check the full range, whether
499 * static_protection() requires a different pgprot for one of
500 * the pages in the range we try to preserve:
502 addr = address & pmask;
503 pfn = pte_pfn(old_pte);
504 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
505 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
507 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
512 * If there are no changes, return. maxpages has been updated
515 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
521 * We need to change the attributes. Check, whether we can
522 * change the large page in one go. We request a split, when
523 * the address is not aligned and the number of pages is
524 * smaller than the number of pages in the large page. Note
525 * that we limited the number of possible pages already to
526 * the number of pages in the large page.
528 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
530 * The address is aligned and the number of pages
531 * covers the full page.
533 new_pte = pfn_pte(pte_pfn(old_pte), new_prot);
534 __set_pmd_pte(kpte, address, new_pte);
535 cpa->flags |= CPA_FLUSHTLB;
540 spin_unlock(&pgd_lock);
545 int __split_large_page(pte_t *kpte, unsigned long address, pte_t *pbase)
547 unsigned long pfn, pfninc = 1;
548 unsigned int i, level;
551 struct page *base = virt_to_page(pbase);
553 spin_lock(&pgd_lock);
555 * Check for races, another CPU might have split this page
558 tmp = lookup_address(address, &level);
560 spin_unlock(&pgd_lock);
564 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
565 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
567 * If we ever want to utilize the PAT bit, we need to
568 * update this function to make sure it's converted from
569 * bit 12 to bit 7 when we cross from the 2MB level to
572 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
575 if (level == PG_LEVEL_1G) {
576 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
578 * Set the PSE flags only if the PRESENT flag is set
579 * otherwise pmd_present/pmd_huge will return true
580 * even on a non present pmd.
582 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
583 pgprot_val(ref_prot) |= _PAGE_PSE;
585 pgprot_val(ref_prot) &= ~_PAGE_PSE;
590 * Set the GLOBAL flags only if the PRESENT flag is set
591 * otherwise pmd/pte_present will return true even on a non
592 * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL
593 * for the ancient hardware that doesn't support it.
595 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
596 pgprot_val(ref_prot) |= _PAGE_GLOBAL;
598 pgprot_val(ref_prot) &= ~_PAGE_GLOBAL;
601 * Get the target pfn from the original entry:
603 pfn = pte_pfn(*kpte);
604 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
605 set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot)));
607 if (pfn_range_is_mapped(PFN_DOWN(__pa(address)),
608 PFN_DOWN(__pa(address)) + 1))
609 split_page_count(level);
612 * Install the new, split up pagetable.
614 * We use the standard kernel pagetable protections for the new
615 * pagetable protections, the actual ptes set above control the
616 * primary protection behavior:
618 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
621 * Intel Atom errata AAH41 workaround.
623 * The real fix should be in hw or in a microcode update, but
624 * we also probabilistically try to reduce the window of having
625 * a large TLB mixed with 4K TLBs while instruction fetches are
629 spin_unlock(&pgd_lock);
634 static int split_large_page(pte_t *kpte, unsigned long address)
639 if (!debug_pagealloc)
640 spin_unlock(&cpa_lock);
641 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
642 if (!debug_pagealloc)
643 spin_lock(&cpa_lock);
647 pbase = (pte_t *)page_address(base);
648 if (__split_large_page(kpte, address, pbase))
654 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
658 * Ignore all non primary paths.
664 * Ignore the NULL PTE for kernel identity mapping, as it is expected
666 * Also set numpages to '1' indicating that we processed cpa req for
667 * one virtual address page and its pfn. TBD: numpages can be set based
668 * on the initial value and the level returned by lookup_address().
670 if (within(vaddr, PAGE_OFFSET,
671 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
673 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
676 WARN(1, KERN_WARNING "CPA: called for zero pte. "
677 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
684 static int __change_page_attr(struct cpa_data *cpa, int primary)
686 unsigned long address;
689 pte_t *kpte, old_pte;
691 if (cpa->flags & CPA_PAGES_ARRAY) {
692 struct page *page = cpa->pages[cpa->curpage];
693 if (unlikely(PageHighMem(page)))
695 address = (unsigned long)page_address(page);
696 } else if (cpa->flags & CPA_ARRAY)
697 address = cpa->vaddr[cpa->curpage];
699 address = *cpa->vaddr;
701 kpte = lookup_address(address, &level);
703 return __cpa_process_fault(cpa, address, primary);
706 if (!pte_val(old_pte))
707 return __cpa_process_fault(cpa, address, primary);
709 if (level == PG_LEVEL_4K) {
711 pgprot_t new_prot = pte_pgprot(old_pte);
712 unsigned long pfn = pte_pfn(old_pte);
714 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
715 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
717 new_prot = static_protections(new_prot, address, pfn);
720 * Set the GLOBAL flags only if the PRESENT flag is
721 * set otherwise pte_present will return true even on
722 * a non present pte. The canon_pgprot will clear
723 * _PAGE_GLOBAL for the ancient hardware that doesn't
726 if (pgprot_val(new_prot) & _PAGE_PRESENT)
727 pgprot_val(new_prot) |= _PAGE_GLOBAL;
729 pgprot_val(new_prot) &= ~_PAGE_GLOBAL;
732 * We need to keep the pfn from the existing PTE,
733 * after all we're only going to change it's attributes
734 * not the memory it points to
736 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
739 * Do we really change anything ?
741 if (pte_val(old_pte) != pte_val(new_pte)) {
742 set_pte_atomic(kpte, new_pte);
743 cpa->flags |= CPA_FLUSHTLB;
750 * Check, whether we can keep the large page intact
751 * and just change the pte:
753 do_split = try_preserve_large_page(kpte, address, cpa);
755 * When the range fits into the existing large page,
756 * return. cp->numpages and cpa->tlbflush have been updated in
763 * We have to split the large page:
765 err = split_large_page(kpte, address);
768 * Do a global flush tlb after splitting the large page
769 * and before we do the actual change page attribute in the PTE.
771 * With out this, we violate the TLB application note, that says
772 * "The TLBs may contain both ordinary and large-page
773 * translations for a 4-KByte range of linear addresses. This
774 * may occur if software modifies the paging structures so that
775 * the page size used for the address range changes. If the two
776 * translations differ with respect to page frame or attributes
777 * (e.g., permissions), processor behavior is undefined and may
778 * be implementation-specific."
780 * We do this global tlb flush inside the cpa_lock, so that we
781 * don't allow any other cpu, with stale tlb entries change the
782 * page attribute in parallel, that also falls into the
783 * just split large page entry.
792 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
794 static int cpa_process_alias(struct cpa_data *cpa)
796 struct cpa_data alias_cpa;
797 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
801 if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1))
805 * No need to redo, when the primary call touched the direct
808 if (cpa->flags & CPA_PAGES_ARRAY) {
809 struct page *page = cpa->pages[cpa->curpage];
810 if (unlikely(PageHighMem(page)))
812 vaddr = (unsigned long)page_address(page);
813 } else if (cpa->flags & CPA_ARRAY)
814 vaddr = cpa->vaddr[cpa->curpage];
818 if (!(within(vaddr, PAGE_OFFSET,
819 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
822 alias_cpa.vaddr = &laddr;
823 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
825 ret = __change_page_attr_set_clr(&alias_cpa, 0);
832 * If the primary call didn't touch the high mapping already
833 * and the physical address is inside the kernel map, we need
834 * to touch the high mapped kernel as well:
836 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
837 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
838 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
839 __START_KERNEL_map - phys_base;
841 alias_cpa.vaddr = &temp_cpa_vaddr;
842 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
845 * The high mapping range is imprecise, so ignore the
848 __change_page_attr_set_clr(&alias_cpa, 0);
855 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
857 int ret, numpages = cpa->numpages;
861 * Store the remaining nr of pages for the large page
862 * preservation check.
864 cpa->numpages = numpages;
865 /* for array changes, we can't use large page */
866 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
869 if (!debug_pagealloc)
870 spin_lock(&cpa_lock);
871 ret = __change_page_attr(cpa, checkalias);
872 if (!debug_pagealloc)
873 spin_unlock(&cpa_lock);
878 ret = cpa_process_alias(cpa);
884 * Adjust the number of pages with the result of the
885 * CPA operation. Either a large page has been
886 * preserved or a single page update happened.
888 BUG_ON(cpa->numpages > numpages);
889 numpages -= cpa->numpages;
890 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
893 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
899 static inline int cache_attr(pgprot_t attr)
901 return pgprot_val(attr) &
902 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
905 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
906 pgprot_t mask_set, pgprot_t mask_clr,
907 int force_split, int in_flag,
911 int ret, cache, checkalias;
912 unsigned long baddr = 0;
915 * Check, if we are requested to change a not supported
918 mask_set = canon_pgprot(mask_set);
919 mask_clr = canon_pgprot(mask_clr);
920 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
923 /* Ensure we are PAGE_SIZE aligned */
924 if (in_flag & CPA_ARRAY) {
926 for (i = 0; i < numpages; i++) {
927 if (addr[i] & ~PAGE_MASK) {
928 addr[i] &= PAGE_MASK;
932 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
934 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
935 * No need to cehck in that case
937 if (*addr & ~PAGE_MASK) {
940 * People should not be passing in unaligned addresses:
945 * Save address for cache flush. *addr is modified in the call
946 * to __change_page_attr_set_clr() below.
951 /* Must avoid aliasing mappings in the highmem code */
958 cpa.numpages = numpages;
959 cpa.mask_set = mask_set;
960 cpa.mask_clr = mask_clr;
963 cpa.force_split = force_split;
965 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
966 cpa.flags |= in_flag;
968 /* No alias checking for _NX bit modifications */
969 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
971 ret = __change_page_attr_set_clr(&cpa, checkalias);
974 * Check whether we really changed something:
976 if (!(cpa.flags & CPA_FLUSHTLB))
980 * No need to flush, when we did not set any of the caching
983 cache = cache_attr(mask_set);
986 * On success we use clflush, when the CPU supports it to
987 * avoid the wbindv. If the CPU does not support it and in the
988 * error case we fall back to cpa_flush_all (which uses
991 if (!ret && cpu_has_clflush) {
992 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
993 cpa_flush_array(addr, numpages, cache,
996 cpa_flush_range(baddr, numpages, cache);
998 cpa_flush_all(cache);
1004 static inline int change_page_attr_set(unsigned long *addr, int numpages,
1005 pgprot_t mask, int array)
1007 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
1008 (array ? CPA_ARRAY : 0), NULL);
1011 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
1012 pgprot_t mask, int array)
1014 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
1015 (array ? CPA_ARRAY : 0), NULL);
1018 static inline int cpa_set_pages_array(struct page **pages, int numpages,
1021 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
1022 CPA_PAGES_ARRAY, pages);
1025 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
1028 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
1029 CPA_PAGES_ARRAY, pages);
1032 int _set_memory_uc(unsigned long addr, int numpages)
1035 * for now UC MINUS. see comments in ioremap_nocache()
1037 return change_page_attr_set(&addr, numpages,
1038 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1041 int set_memory_uc(unsigned long addr, int numpages)
1046 * for now UC MINUS. see comments in ioremap_nocache()
1048 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1049 _PAGE_CACHE_UC_MINUS, NULL);
1053 ret = _set_memory_uc(addr, numpages);
1060 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1064 EXPORT_SYMBOL(set_memory_uc);
1066 static int _set_memory_array(unsigned long *addr, int addrinarray,
1067 unsigned long new_type)
1073 * for now UC MINUS. see comments in ioremap_nocache()
1075 for (i = 0; i < addrinarray; i++) {
1076 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
1082 ret = change_page_attr_set(addr, addrinarray,
1083 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
1085 if (!ret && new_type == _PAGE_CACHE_WC)
1086 ret = change_page_attr_set_clr(addr, addrinarray,
1087 __pgprot(_PAGE_CACHE_WC),
1088 __pgprot(_PAGE_CACHE_MASK),
1089 0, CPA_ARRAY, NULL);
1096 for (j = 0; j < i; j++)
1097 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1102 int set_memory_array_uc(unsigned long *addr, int addrinarray)
1104 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);
1106 EXPORT_SYMBOL(set_memory_array_uc);
1108 int set_memory_array_wc(unsigned long *addr, int addrinarray)
1110 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);
1112 EXPORT_SYMBOL(set_memory_array_wc);
1114 int _set_memory_wc(unsigned long addr, int numpages)
1117 unsigned long addr_copy = addr;
1119 ret = change_page_attr_set(&addr, numpages,
1120 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1122 ret = change_page_attr_set_clr(&addr_copy, numpages,
1123 __pgprot(_PAGE_CACHE_WC),
1124 __pgprot(_PAGE_CACHE_MASK),
1130 int set_memory_wc(unsigned long addr, int numpages)
1135 return set_memory_uc(addr, numpages);
1137 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1138 _PAGE_CACHE_WC, NULL);
1142 ret = _set_memory_wc(addr, numpages);
1149 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1153 EXPORT_SYMBOL(set_memory_wc);
1155 int _set_memory_wb(unsigned long addr, int numpages)
1157 return change_page_attr_clear(&addr, numpages,
1158 __pgprot(_PAGE_CACHE_MASK), 0);
1161 int set_memory_wb(unsigned long addr, int numpages)
1165 ret = _set_memory_wb(addr, numpages);
1169 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1172 EXPORT_SYMBOL(set_memory_wb);
1174 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1179 ret = change_page_attr_clear(addr, addrinarray,
1180 __pgprot(_PAGE_CACHE_MASK), 1);
1184 for (i = 0; i < addrinarray; i++)
1185 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1189 EXPORT_SYMBOL(set_memory_array_wb);
1191 int set_memory_x(unsigned long addr, int numpages)
1193 if (!(__supported_pte_mask & _PAGE_NX))
1196 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1198 EXPORT_SYMBOL(set_memory_x);
1200 int set_memory_nx(unsigned long addr, int numpages)
1202 if (!(__supported_pte_mask & _PAGE_NX))
1205 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1207 EXPORT_SYMBOL(set_memory_nx);
1209 int set_memory_ro(unsigned long addr, int numpages)
1211 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1213 EXPORT_SYMBOL_GPL(set_memory_ro);
1215 int set_memory_rw(unsigned long addr, int numpages)
1217 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1219 EXPORT_SYMBOL_GPL(set_memory_rw);
1221 int set_memory_np(unsigned long addr, int numpages)
1223 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1226 int set_memory_4k(unsigned long addr, int numpages)
1228 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1229 __pgprot(0), 1, 0, NULL);
1232 int set_pages_uc(struct page *page, int numpages)
1234 unsigned long addr = (unsigned long)page_address(page);
1236 return set_memory_uc(addr, numpages);
1238 EXPORT_SYMBOL(set_pages_uc);
1240 static int _set_pages_array(struct page **pages, int addrinarray,
1241 unsigned long new_type)
1243 unsigned long start;
1249 for (i = 0; i < addrinarray; i++) {
1250 if (PageHighMem(pages[i]))
1252 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1253 end = start + PAGE_SIZE;
1254 if (reserve_memtype(start, end, new_type, NULL))
1258 ret = cpa_set_pages_array(pages, addrinarray,
1259 __pgprot(_PAGE_CACHE_UC_MINUS));
1260 if (!ret && new_type == _PAGE_CACHE_WC)
1261 ret = change_page_attr_set_clr(NULL, addrinarray,
1262 __pgprot(_PAGE_CACHE_WC),
1263 __pgprot(_PAGE_CACHE_MASK),
1264 0, CPA_PAGES_ARRAY, pages);
1267 return 0; /* Success */
1270 for (i = 0; i < free_idx; i++) {
1271 if (PageHighMem(pages[i]))
1273 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1274 end = start + PAGE_SIZE;
1275 free_memtype(start, end);
1280 int set_pages_array_uc(struct page **pages, int addrinarray)
1282 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);
1284 EXPORT_SYMBOL(set_pages_array_uc);
1286 int set_pages_array_wc(struct page **pages, int addrinarray)
1288 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);
1290 EXPORT_SYMBOL(set_pages_array_wc);
1292 int set_pages_wb(struct page *page, int numpages)
1294 unsigned long addr = (unsigned long)page_address(page);
1296 return set_memory_wb(addr, numpages);
1298 EXPORT_SYMBOL(set_pages_wb);
1300 int set_pages_array_wb(struct page **pages, int addrinarray)
1303 unsigned long start;
1307 retval = cpa_clear_pages_array(pages, addrinarray,
1308 __pgprot(_PAGE_CACHE_MASK));
1312 for (i = 0; i < addrinarray; i++) {
1313 if (PageHighMem(pages[i]))
1315 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1316 end = start + PAGE_SIZE;
1317 free_memtype(start, end);
1322 EXPORT_SYMBOL(set_pages_array_wb);
1324 int set_pages_x(struct page *page, int numpages)
1326 unsigned long addr = (unsigned long)page_address(page);
1328 return set_memory_x(addr, numpages);
1330 EXPORT_SYMBOL(set_pages_x);
1332 int set_pages_nx(struct page *page, int numpages)
1334 unsigned long addr = (unsigned long)page_address(page);
1336 return set_memory_nx(addr, numpages);
1338 EXPORT_SYMBOL(set_pages_nx);
1340 int set_pages_ro(struct page *page, int numpages)
1342 unsigned long addr = (unsigned long)page_address(page);
1344 return set_memory_ro(addr, numpages);
1347 int set_pages_rw(struct page *page, int numpages)
1349 unsigned long addr = (unsigned long)page_address(page);
1351 return set_memory_rw(addr, numpages);
1354 #ifdef CONFIG_DEBUG_PAGEALLOC
1356 static int __set_pages_p(struct page *page, int numpages)
1358 unsigned long tempaddr = (unsigned long) page_address(page);
1359 struct cpa_data cpa = { .vaddr = &tempaddr,
1360 .numpages = numpages,
1361 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1362 .mask_clr = __pgprot(0),
1366 * No alias checking needed for setting present flag. otherwise,
1367 * we may need to break large pages for 64-bit kernel text
1368 * mappings (this adds to complexity if we want to do this from
1369 * atomic context especially). Let's keep it simple!
1371 return __change_page_attr_set_clr(&cpa, 0);
1374 static int __set_pages_np(struct page *page, int numpages)
1376 unsigned long tempaddr = (unsigned long) page_address(page);
1377 struct cpa_data cpa = { .vaddr = &tempaddr,
1378 .numpages = numpages,
1379 .mask_set = __pgprot(0),
1380 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1384 * No alias checking needed for setting not present flag. otherwise,
1385 * we may need to break large pages for 64-bit kernel text
1386 * mappings (this adds to complexity if we want to do this from
1387 * atomic context especially). Let's keep it simple!
1389 return __change_page_attr_set_clr(&cpa, 0);
1392 void kernel_map_pages(struct page *page, int numpages, int enable)
1394 if (PageHighMem(page))
1397 debug_check_no_locks_freed(page_address(page),
1398 numpages * PAGE_SIZE);
1402 * The return value is ignored as the calls cannot fail.
1403 * Large pages for identity mappings are not used at boot time
1404 * and hence no memory allocations during large page split.
1407 __set_pages_p(page, numpages);
1409 __set_pages_np(page, numpages);
1412 * We should perform an IPI and flush all tlbs,
1413 * but that can deadlock->flush only current cpu:
1418 #ifdef CONFIG_HIBERNATION
1420 bool kernel_page_present(struct page *page)
1425 if (PageHighMem(page))
1428 pte = lookup_address((unsigned long)page_address(page), &level);
1429 return (pte_val(*pte) & _PAGE_PRESENT);
1432 #endif /* CONFIG_HIBERNATION */
1434 #endif /* CONFIG_DEBUG_PAGEALLOC */
1437 * The testcases use internal knowledge of the implementation that shouldn't
1438 * be exposed to the rest of the kernel. Include these directly here.
1440 #ifdef CONFIG_CPA_DEBUG
1441 #include "pageattr-test.c"