2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
10 #include <linux/interrupt.h>
11 #include <linux/seq_file.h>
12 #include <linux/debugfs.h>
13 #include <linux/pfn.h>
14 #include <linux/percpu.h>
15 #include <linux/gfp.h>
16 #include <linux/pci.h>
19 #include <asm/processor.h>
20 #include <asm/tlbflush.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <asm/uaccess.h>
24 #include <asm/pgalloc.h>
25 #include <asm/proto.h>
29 * The current flushing context - we pass it instead of 5 arguments:
38 unsigned force_split : 1;
44 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
45 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
46 * entries change the page attribute in parallel to some other cpu
47 * splitting a large page entry along with changing the attribute.
49 static DEFINE_SPINLOCK(cpa_lock);
51 #define CPA_FLUSHTLB 1
53 #define CPA_PAGES_ARRAY 4
56 static unsigned long direct_pages_count[PG_LEVEL_NUM];
58 void update_page_count(int level, unsigned long pages)
60 /* Protect against CPA */
62 direct_pages_count[level] += pages;
63 spin_unlock(&pgd_lock);
66 static void split_page_count(int level)
68 direct_pages_count[level]--;
69 direct_pages_count[level - 1] += PTRS_PER_PTE;
72 void arch_report_meminfo(struct seq_file *m)
74 seq_printf(m, "DirectMap4k: %8lu kB\n",
75 direct_pages_count[PG_LEVEL_4K] << 2);
76 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
77 seq_printf(m, "DirectMap2M: %8lu kB\n",
78 direct_pages_count[PG_LEVEL_2M] << 11);
80 seq_printf(m, "DirectMap4M: %8lu kB\n",
81 direct_pages_count[PG_LEVEL_2M] << 12);
85 seq_printf(m, "DirectMap1G: %8lu kB\n",
86 direct_pages_count[PG_LEVEL_1G] << 20);
90 static inline void split_page_count(int level) { }
95 static inline unsigned long highmap_start_pfn(void)
97 return __pa_symbol(_text) >> PAGE_SHIFT;
100 static inline unsigned long highmap_end_pfn(void)
102 return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
107 #ifdef CONFIG_DEBUG_PAGEALLOC
108 # define debug_pagealloc 1
110 # define debug_pagealloc 0
114 within(unsigned long addr, unsigned long start, unsigned long end)
116 return addr >= start && addr < end;
124 * clflush_cache_range - flush a cache range with clflush
125 * @vaddr: virtual start address
126 * @size: number of bytes to flush
128 * clflush is an unordered instruction which needs fencing with mfence
129 * to avoid ordering issues.
131 void clflush_cache_range(void *vaddr, unsigned int size)
133 void *vend = vaddr + size - 1;
137 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
140 * Flush any possible final partial cacheline:
146 EXPORT_SYMBOL_GPL(clflush_cache_range);
148 static void __cpa_flush_all(void *arg)
150 unsigned long cache = (unsigned long)arg;
153 * Flush all to work around Errata in early athlons regarding
154 * large page flushing.
158 if (cache && boot_cpu_data.x86 >= 4)
162 static void cpa_flush_all(unsigned long cache)
164 BUG_ON(irqs_disabled());
166 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
169 static void __cpa_flush_range(void *arg)
172 * We could optimize that further and do individual per page
173 * tlb invalidates for a low number of pages. Caveat: we must
174 * flush the high aliases on 64bit as well.
179 static void cpa_flush_range(unsigned long start, int numpages, int cache)
181 unsigned int i, level;
184 BUG_ON(irqs_disabled());
185 WARN_ON(PAGE_ALIGN(start) != start);
187 on_each_cpu(__cpa_flush_range, NULL, 1);
193 * We only need to flush on one CPU,
194 * clflush is a MESI-coherent instruction that
195 * will cause all other CPUs to flush the same
198 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
199 pte_t *pte = lookup_address(addr, &level);
202 * Only flush present addresses:
204 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
205 clflush_cache_range((void *) addr, PAGE_SIZE);
209 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
210 int in_flags, struct page **pages)
212 unsigned int i, level;
213 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
215 BUG_ON(irqs_disabled());
217 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
219 if (!cache || do_wbinvd)
223 * We only need to flush on one CPU,
224 * clflush is a MESI-coherent instruction that
225 * will cause all other CPUs to flush the same
228 for (i = 0; i < numpages; i++) {
232 if (in_flags & CPA_PAGES_ARRAY)
233 addr = (unsigned long)page_address(pages[i]);
237 pte = lookup_address(addr, &level);
240 * Only flush present addresses:
242 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
243 clflush_cache_range((void *)addr, PAGE_SIZE);
248 * Certain areas of memory on x86 require very specific protection flags,
249 * for example the BIOS area or kernel text. Callers don't always get this
250 * right (again, ioremap() on BIOS memory is not uncommon) so this function
251 * checks and fixes these known static required protection bits.
253 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
256 pgprot_t forbidden = __pgprot(0);
259 * The BIOS area between 640k and 1Mb needs to be executable for
260 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
262 #ifdef CONFIG_PCI_BIOS
263 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
264 pgprot_val(forbidden) |= _PAGE_NX;
268 * The kernel text needs to be executable for obvious reasons
269 * Does not cover __inittext since that is gone later on. On
270 * 64bit we do not enforce !NX on the low mapping
272 if (within(address, (unsigned long)_text, (unsigned long)_etext))
273 pgprot_val(forbidden) |= _PAGE_NX;
276 * The .rodata section needs to be read-only. Using the pfn
277 * catches all aliases.
279 if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
280 __pa_symbol(__end_rodata) >> PAGE_SHIFT))
281 pgprot_val(forbidden) |= _PAGE_RW;
283 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
285 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
286 * kernel text mappings for the large page aligned text, rodata sections
287 * will be always read-only. For the kernel identity mappings covering
288 * the holes caused by this alignment can be anything that user asks.
290 * This will preserve the large page mappings for kernel text/data
293 if (kernel_set_to_readonly &&
294 within(address, (unsigned long)_text,
295 (unsigned long)__end_rodata_hpage_align)) {
299 * Don't enforce the !RW mapping for the kernel text mapping,
300 * if the current mapping is already using small page mapping.
301 * No need to work hard to preserve large page mappings in this
304 * This also fixes the Linux Xen paravirt guest boot failure
305 * (because of unexpected read-only mappings for kernel identity
306 * mappings). In this paravirt guest case, the kernel text
307 * mapping and the kernel identity mapping share the same
308 * page-table pages. Thus we can't really use different
309 * protections for the kernel text and identity mappings. Also,
310 * these shared mappings are made of small page mappings.
311 * Thus this don't enforce !RW mapping for small page kernel
312 * text mapping logic will help Linux Xen parvirt guest boot
315 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
316 pgprot_val(forbidden) |= _PAGE_RW;
320 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
326 * Lookup the page table entry for a virtual address. Return a pointer
327 * to the entry and the level of the mapping.
329 * Note: We return pud and pmd either when the entry is marked large
330 * or when the present bit is not set. Otherwise we would return a
331 * pointer to a nonexisting mapping.
333 pte_t *lookup_address(unsigned long address, unsigned int *level)
335 pgd_t *pgd = pgd_offset_k(address);
339 *level = PG_LEVEL_NONE;
344 pud = pud_offset(pgd, address);
348 *level = PG_LEVEL_1G;
349 if (pud_large(*pud) || !pud_present(*pud))
352 pmd = pmd_offset(pud, address);
356 *level = PG_LEVEL_2M;
357 if (pmd_large(*pmd) || !pmd_present(*pmd))
360 *level = PG_LEVEL_4K;
362 return pte_offset_kernel(pmd, address);
364 EXPORT_SYMBOL_GPL(lookup_address);
367 * This is necessary because __pa() does not work on some
368 * kinds of memory, like vmalloc() or the alloc_remap()
369 * areas on 32-bit NUMA systems. The percpu areas can
370 * end up in this kind of memory, for instance.
372 * This could be optimized, but it is only intended to be
373 * used at inititalization time, and keeping it
374 * unoptimized should increase the testing coverage for
375 * the more obscure platforms.
377 phys_addr_t slow_virt_to_phys(void *__virt_addr)
379 unsigned long virt_addr = (unsigned long)__virt_addr;
380 phys_addr_t phys_addr;
381 unsigned long offset;
387 pte = lookup_address(virt_addr, &level);
389 psize = page_level_size(level);
390 pmask = page_level_mask(level);
391 offset = virt_addr & ~pmask;
392 phys_addr = pte_pfn(*pte) << PAGE_SHIFT;
393 return (phys_addr | offset);
395 EXPORT_SYMBOL_GPL(slow_virt_to_phys);
398 * Set the new pmd in all the pgds we know about:
400 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
403 set_pte_atomic(kpte, pte);
405 if (!SHARED_KERNEL_PMD) {
408 list_for_each_entry(page, &pgd_list, lru) {
413 pgd = (pgd_t *)page_address(page) + pgd_index(address);
414 pud = pud_offset(pgd, address);
415 pmd = pmd_offset(pud, address);
416 set_pte_atomic((pte_t *)pmd, pte);
423 try_preserve_large_page(pte_t *kpte, unsigned long address,
424 struct cpa_data *cpa)
426 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn;
427 pte_t new_pte, old_pte, *tmp;
428 pgprot_t old_prot, new_prot, req_prot;
432 if (cpa->force_split)
435 spin_lock(&pgd_lock);
437 * Check for races, another CPU might have split this page
440 tmp = lookup_address(address, &level);
449 psize = page_level_size(level);
450 pmask = page_level_mask(level);
458 * Calculate the number of pages, which fit into this large
459 * page starting at address:
461 nextpage_addr = (address + psize) & pmask;
462 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
463 if (numpages < cpa->numpages)
464 cpa->numpages = numpages;
467 * We are safe now. Check whether the new pgprot is the same:
470 old_prot = new_prot = req_prot = pte_pgprot(old_pte);
472 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
473 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
476 * old_pte points to the large page base address. So we need
477 * to add the offset of the virtual address:
479 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
482 new_prot = static_protections(req_prot, address, pfn);
485 * We need to check the full range, whether
486 * static_protection() requires a different pgprot for one of
487 * the pages in the range we try to preserve:
489 addr = address & pmask;
490 pfn = pte_pfn(old_pte);
491 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
492 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
494 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
499 * If there are no changes, return. maxpages has been updated
502 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
508 * We need to change the attributes. Check, whether we can
509 * change the large page in one go. We request a split, when
510 * the address is not aligned and the number of pages is
511 * smaller than the number of pages in the large page. Note
512 * that we limited the number of possible pages already to
513 * the number of pages in the large page.
515 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
517 * The address is aligned and the number of pages
518 * covers the full page.
520 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
521 __set_pmd_pte(kpte, address, new_pte);
522 cpa->flags |= CPA_FLUSHTLB;
527 spin_unlock(&pgd_lock);
532 static int split_large_page(pte_t *kpte, unsigned long address)
534 unsigned long pfn, pfninc = 1;
535 unsigned int i, level;
540 if (!debug_pagealloc)
541 spin_unlock(&cpa_lock);
542 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
543 if (!debug_pagealloc)
544 spin_lock(&cpa_lock);
548 spin_lock(&pgd_lock);
550 * Check for races, another CPU might have split this page
553 tmp = lookup_address(address, &level);
557 pbase = (pte_t *)page_address(base);
558 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
559 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
561 * If we ever want to utilize the PAT bit, we need to
562 * update this function to make sure it's converted from
563 * bit 12 to bit 7 when we cross from the 2MB level to
566 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
569 if (level == PG_LEVEL_1G) {
570 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
571 pgprot_val(ref_prot) |= _PAGE_PSE;
576 * Get the target pfn from the original entry:
578 pfn = pte_pfn(*kpte);
579 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
580 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
582 if (pfn_range_is_mapped(PFN_DOWN(__pa(address)),
583 PFN_DOWN(__pa(address)) + 1))
584 split_page_count(level);
587 * Install the new, split up pagetable.
589 * We use the standard kernel pagetable protections for the new
590 * pagetable protections, the actual ptes set above control the
591 * primary protection behavior:
593 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
596 * Intel Atom errata AAH41 workaround.
598 * The real fix should be in hw or in a microcode update, but
599 * we also probabilistically try to reduce the window of having
600 * a large TLB mixed with 4K TLBs while instruction fetches are
609 * If we dropped out via the lookup_address check under
610 * pgd_lock then stick the page back into the pool:
614 spin_unlock(&pgd_lock);
619 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
623 * Ignore all non primary paths.
629 * Ignore the NULL PTE for kernel identity mapping, as it is expected
631 * Also set numpages to '1' indicating that we processed cpa req for
632 * one virtual address page and its pfn. TBD: numpages can be set based
633 * on the initial value and the level returned by lookup_address().
635 if (within(vaddr, PAGE_OFFSET,
636 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
638 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
641 WARN(1, KERN_WARNING "CPA: called for zero pte. "
642 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
649 static int __change_page_attr(struct cpa_data *cpa, int primary)
651 unsigned long address;
654 pte_t *kpte, old_pte;
656 if (cpa->flags & CPA_PAGES_ARRAY) {
657 struct page *page = cpa->pages[cpa->curpage];
658 if (unlikely(PageHighMem(page)))
660 address = (unsigned long)page_address(page);
661 } else if (cpa->flags & CPA_ARRAY)
662 address = cpa->vaddr[cpa->curpage];
664 address = *cpa->vaddr;
666 kpte = lookup_address(address, &level);
668 return __cpa_process_fault(cpa, address, primary);
671 if (!pte_val(old_pte))
672 return __cpa_process_fault(cpa, address, primary);
674 if (level == PG_LEVEL_4K) {
676 pgprot_t new_prot = pte_pgprot(old_pte);
677 unsigned long pfn = pte_pfn(old_pte);
679 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
680 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
682 new_prot = static_protections(new_prot, address, pfn);
685 * We need to keep the pfn from the existing PTE,
686 * after all we're only going to change it's attributes
687 * not the memory it points to
689 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
692 * Do we really change anything ?
694 if (pte_val(old_pte) != pte_val(new_pte)) {
695 set_pte_atomic(kpte, new_pte);
696 cpa->flags |= CPA_FLUSHTLB;
703 * Check, whether we can keep the large page intact
704 * and just change the pte:
706 do_split = try_preserve_large_page(kpte, address, cpa);
708 * When the range fits into the existing large page,
709 * return. cp->numpages and cpa->tlbflush have been updated in
716 * We have to split the large page:
718 err = split_large_page(kpte, address);
721 * Do a global flush tlb after splitting the large page
722 * and before we do the actual change page attribute in the PTE.
724 * With out this, we violate the TLB application note, that says
725 * "The TLBs may contain both ordinary and large-page
726 * translations for a 4-KByte range of linear addresses. This
727 * may occur if software modifies the paging structures so that
728 * the page size used for the address range changes. If the two
729 * translations differ with respect to page frame or attributes
730 * (e.g., permissions), processor behavior is undefined and may
731 * be implementation-specific."
733 * We do this global tlb flush inside the cpa_lock, so that we
734 * don't allow any other cpu, with stale tlb entries change the
735 * page attribute in parallel, that also falls into the
736 * just split large page entry.
745 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
747 static int cpa_process_alias(struct cpa_data *cpa)
749 struct cpa_data alias_cpa;
750 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
754 if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1))
758 * No need to redo, when the primary call touched the direct
761 if (cpa->flags & CPA_PAGES_ARRAY) {
762 struct page *page = cpa->pages[cpa->curpage];
763 if (unlikely(PageHighMem(page)))
765 vaddr = (unsigned long)page_address(page);
766 } else if (cpa->flags & CPA_ARRAY)
767 vaddr = cpa->vaddr[cpa->curpage];
771 if (!(within(vaddr, PAGE_OFFSET,
772 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
775 alias_cpa.vaddr = &laddr;
776 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
778 ret = __change_page_attr_set_clr(&alias_cpa, 0);
785 * If the primary call didn't touch the high mapping already
786 * and the physical address is inside the kernel map, we need
787 * to touch the high mapped kernel as well:
789 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
790 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
791 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
792 __START_KERNEL_map - phys_base;
794 alias_cpa.vaddr = &temp_cpa_vaddr;
795 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
798 * The high mapping range is imprecise, so ignore the
801 __change_page_attr_set_clr(&alias_cpa, 0);
808 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
810 int ret, numpages = cpa->numpages;
814 * Store the remaining nr of pages for the large page
815 * preservation check.
817 cpa->numpages = numpages;
818 /* for array changes, we can't use large page */
819 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
822 if (!debug_pagealloc)
823 spin_lock(&cpa_lock);
824 ret = __change_page_attr(cpa, checkalias);
825 if (!debug_pagealloc)
826 spin_unlock(&cpa_lock);
831 ret = cpa_process_alias(cpa);
837 * Adjust the number of pages with the result of the
838 * CPA operation. Either a large page has been
839 * preserved or a single page update happened.
841 BUG_ON(cpa->numpages > numpages);
842 numpages -= cpa->numpages;
843 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
846 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
852 static inline int cache_attr(pgprot_t attr)
854 return pgprot_val(attr) &
855 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
858 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
859 pgprot_t mask_set, pgprot_t mask_clr,
860 int force_split, int in_flag,
864 int ret, cache, checkalias;
865 unsigned long baddr = 0;
868 * Check, if we are requested to change a not supported
871 mask_set = canon_pgprot(mask_set);
872 mask_clr = canon_pgprot(mask_clr);
873 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
876 /* Ensure we are PAGE_SIZE aligned */
877 if (in_flag & CPA_ARRAY) {
879 for (i = 0; i < numpages; i++) {
880 if (addr[i] & ~PAGE_MASK) {
881 addr[i] &= PAGE_MASK;
885 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
887 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
888 * No need to cehck in that case
890 if (*addr & ~PAGE_MASK) {
893 * People should not be passing in unaligned addresses:
898 * Save address for cache flush. *addr is modified in the call
899 * to __change_page_attr_set_clr() below.
904 /* Must avoid aliasing mappings in the highmem code */
911 cpa.numpages = numpages;
912 cpa.mask_set = mask_set;
913 cpa.mask_clr = mask_clr;
916 cpa.force_split = force_split;
918 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
919 cpa.flags |= in_flag;
921 /* No alias checking for _NX bit modifications */
922 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
924 ret = __change_page_attr_set_clr(&cpa, checkalias);
927 * Check whether we really changed something:
929 if (!(cpa.flags & CPA_FLUSHTLB))
933 * No need to flush, when we did not set any of the caching
936 cache = cache_attr(mask_set);
939 * On success we use clflush, when the CPU supports it to
940 * avoid the wbindv. If the CPU does not support it and in the
941 * error case we fall back to cpa_flush_all (which uses
944 if (!ret && cpu_has_clflush) {
945 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
946 cpa_flush_array(addr, numpages, cache,
949 cpa_flush_range(baddr, numpages, cache);
951 cpa_flush_all(cache);
957 static inline int change_page_attr_set(unsigned long *addr, int numpages,
958 pgprot_t mask, int array)
960 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
961 (array ? CPA_ARRAY : 0), NULL);
964 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
965 pgprot_t mask, int array)
967 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
968 (array ? CPA_ARRAY : 0), NULL);
971 static inline int cpa_set_pages_array(struct page **pages, int numpages,
974 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
975 CPA_PAGES_ARRAY, pages);
978 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
981 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
982 CPA_PAGES_ARRAY, pages);
985 int _set_memory_uc(unsigned long addr, int numpages)
988 * for now UC MINUS. see comments in ioremap_nocache()
990 return change_page_attr_set(&addr, numpages,
991 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
994 int set_memory_uc(unsigned long addr, int numpages)
999 * for now UC MINUS. see comments in ioremap_nocache()
1001 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1002 _PAGE_CACHE_UC_MINUS, NULL);
1006 ret = _set_memory_uc(addr, numpages);
1013 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1017 EXPORT_SYMBOL(set_memory_uc);
1019 static int _set_memory_array(unsigned long *addr, int addrinarray,
1020 unsigned long new_type)
1026 * for now UC MINUS. see comments in ioremap_nocache()
1028 for (i = 0; i < addrinarray; i++) {
1029 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
1035 ret = change_page_attr_set(addr, addrinarray,
1036 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
1038 if (!ret && new_type == _PAGE_CACHE_WC)
1039 ret = change_page_attr_set_clr(addr, addrinarray,
1040 __pgprot(_PAGE_CACHE_WC),
1041 __pgprot(_PAGE_CACHE_MASK),
1042 0, CPA_ARRAY, NULL);
1049 for (j = 0; j < i; j++)
1050 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1055 int set_memory_array_uc(unsigned long *addr, int addrinarray)
1057 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);
1059 EXPORT_SYMBOL(set_memory_array_uc);
1061 int set_memory_array_wc(unsigned long *addr, int addrinarray)
1063 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);
1065 EXPORT_SYMBOL(set_memory_array_wc);
1067 int _set_memory_wc(unsigned long addr, int numpages)
1070 unsigned long addr_copy = addr;
1072 ret = change_page_attr_set(&addr, numpages,
1073 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1075 ret = change_page_attr_set_clr(&addr_copy, numpages,
1076 __pgprot(_PAGE_CACHE_WC),
1077 __pgprot(_PAGE_CACHE_MASK),
1083 int set_memory_wc(unsigned long addr, int numpages)
1088 return set_memory_uc(addr, numpages);
1090 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1091 _PAGE_CACHE_WC, NULL);
1095 ret = _set_memory_wc(addr, numpages);
1102 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1106 EXPORT_SYMBOL(set_memory_wc);
1108 int _set_memory_wb(unsigned long addr, int numpages)
1110 return change_page_attr_clear(&addr, numpages,
1111 __pgprot(_PAGE_CACHE_MASK), 0);
1114 int set_memory_wb(unsigned long addr, int numpages)
1118 ret = _set_memory_wb(addr, numpages);
1122 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1125 EXPORT_SYMBOL(set_memory_wb);
1127 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1132 ret = change_page_attr_clear(addr, addrinarray,
1133 __pgprot(_PAGE_CACHE_MASK), 1);
1137 for (i = 0; i < addrinarray; i++)
1138 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1142 EXPORT_SYMBOL(set_memory_array_wb);
1144 int set_memory_x(unsigned long addr, int numpages)
1146 if (!(__supported_pte_mask & _PAGE_NX))
1149 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1151 EXPORT_SYMBOL(set_memory_x);
1153 int set_memory_nx(unsigned long addr, int numpages)
1155 if (!(__supported_pte_mask & _PAGE_NX))
1158 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1160 EXPORT_SYMBOL(set_memory_nx);
1162 int set_memory_ro(unsigned long addr, int numpages)
1164 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1166 EXPORT_SYMBOL_GPL(set_memory_ro);
1168 int set_memory_rw(unsigned long addr, int numpages)
1170 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1172 EXPORT_SYMBOL_GPL(set_memory_rw);
1174 int set_memory_np(unsigned long addr, int numpages)
1176 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1179 int set_memory_4k(unsigned long addr, int numpages)
1181 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1182 __pgprot(0), 1, 0, NULL);
1185 int set_pages_uc(struct page *page, int numpages)
1187 unsigned long addr = (unsigned long)page_address(page);
1189 return set_memory_uc(addr, numpages);
1191 EXPORT_SYMBOL(set_pages_uc);
1193 static int _set_pages_array(struct page **pages, int addrinarray,
1194 unsigned long new_type)
1196 unsigned long start;
1202 for (i = 0; i < addrinarray; i++) {
1203 if (PageHighMem(pages[i]))
1205 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1206 end = start + PAGE_SIZE;
1207 if (reserve_memtype(start, end, new_type, NULL))
1211 ret = cpa_set_pages_array(pages, addrinarray,
1212 __pgprot(_PAGE_CACHE_UC_MINUS));
1213 if (!ret && new_type == _PAGE_CACHE_WC)
1214 ret = change_page_attr_set_clr(NULL, addrinarray,
1215 __pgprot(_PAGE_CACHE_WC),
1216 __pgprot(_PAGE_CACHE_MASK),
1217 0, CPA_PAGES_ARRAY, pages);
1220 return 0; /* Success */
1223 for (i = 0; i < free_idx; i++) {
1224 if (PageHighMem(pages[i]))
1226 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1227 end = start + PAGE_SIZE;
1228 free_memtype(start, end);
1233 int set_pages_array_uc(struct page **pages, int addrinarray)
1235 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);
1237 EXPORT_SYMBOL(set_pages_array_uc);
1239 int set_pages_array_wc(struct page **pages, int addrinarray)
1241 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);
1243 EXPORT_SYMBOL(set_pages_array_wc);
1245 int set_pages_wb(struct page *page, int numpages)
1247 unsigned long addr = (unsigned long)page_address(page);
1249 return set_memory_wb(addr, numpages);
1251 EXPORT_SYMBOL(set_pages_wb);
1253 int set_pages_array_wb(struct page **pages, int addrinarray)
1256 unsigned long start;
1260 retval = cpa_clear_pages_array(pages, addrinarray,
1261 __pgprot(_PAGE_CACHE_MASK));
1265 for (i = 0; i < addrinarray; i++) {
1266 if (PageHighMem(pages[i]))
1268 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1269 end = start + PAGE_SIZE;
1270 free_memtype(start, end);
1275 EXPORT_SYMBOL(set_pages_array_wb);
1277 int set_pages_x(struct page *page, int numpages)
1279 unsigned long addr = (unsigned long)page_address(page);
1281 return set_memory_x(addr, numpages);
1283 EXPORT_SYMBOL(set_pages_x);
1285 int set_pages_nx(struct page *page, int numpages)
1287 unsigned long addr = (unsigned long)page_address(page);
1289 return set_memory_nx(addr, numpages);
1291 EXPORT_SYMBOL(set_pages_nx);
1293 int set_pages_ro(struct page *page, int numpages)
1295 unsigned long addr = (unsigned long)page_address(page);
1297 return set_memory_ro(addr, numpages);
1300 int set_pages_rw(struct page *page, int numpages)
1302 unsigned long addr = (unsigned long)page_address(page);
1304 return set_memory_rw(addr, numpages);
1307 #ifdef CONFIG_DEBUG_PAGEALLOC
1309 static int __set_pages_p(struct page *page, int numpages)
1311 unsigned long tempaddr = (unsigned long) page_address(page);
1312 struct cpa_data cpa = { .vaddr = &tempaddr,
1313 .numpages = numpages,
1314 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1315 .mask_clr = __pgprot(0),
1319 * No alias checking needed for setting present flag. otherwise,
1320 * we may need to break large pages for 64-bit kernel text
1321 * mappings (this adds to complexity if we want to do this from
1322 * atomic context especially). Let's keep it simple!
1324 return __change_page_attr_set_clr(&cpa, 0);
1327 static int __set_pages_np(struct page *page, int numpages)
1329 unsigned long tempaddr = (unsigned long) page_address(page);
1330 struct cpa_data cpa = { .vaddr = &tempaddr,
1331 .numpages = numpages,
1332 .mask_set = __pgprot(0),
1333 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1337 * No alias checking needed for setting not present flag. otherwise,
1338 * we may need to break large pages for 64-bit kernel text
1339 * mappings (this adds to complexity if we want to do this from
1340 * atomic context especially). Let's keep it simple!
1342 return __change_page_attr_set_clr(&cpa, 0);
1345 void kernel_map_pages(struct page *page, int numpages, int enable)
1347 if (PageHighMem(page))
1350 debug_check_no_locks_freed(page_address(page),
1351 numpages * PAGE_SIZE);
1355 * The return value is ignored as the calls cannot fail.
1356 * Large pages for identity mappings are not used at boot time
1357 * and hence no memory allocations during large page split.
1360 __set_pages_p(page, numpages);
1362 __set_pages_np(page, numpages);
1365 * We should perform an IPI and flush all tlbs,
1366 * but that can deadlock->flush only current cpu:
1371 #ifdef CONFIG_HIBERNATION
1373 bool kernel_page_present(struct page *page)
1378 if (PageHighMem(page))
1381 pte = lookup_address((unsigned long)page_address(page), &level);
1382 return (pte_val(*pte) & _PAGE_PRESENT);
1385 #endif /* CONFIG_HIBERNATION */
1387 #endif /* CONFIG_DEBUG_PAGEALLOC */
1390 * The testcases use internal knowledge of the implementation that shouldn't
1391 * be exposed to the rest of the kernel. Include these directly here.
1393 #ifdef CONFIG_CPA_DEBUG
1394 #include "pageattr-test.c"