2 * Low-Level PCI Access for i386 machines
4 * Copyright 1993, 1994 Drew Eckhardt
6 * (Unix and Linux consulting and custom programming)
10 * Drew's work was sponsored by:
11 * iX Multiuser Multitasking Magazine
15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
17 * For more information, please consult the following manuals (look at
18 * http://www.pcisig.com/ for how to get them):
20 * PCI BIOS Specification
21 * PCI Local Bus Specification
22 * PCI to PCI Bridge Specification
23 * PCI System Design Guide
27 #include <linux/types.h>
28 #include <linux/kernel.h>
29 #include <linux/export.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/ioport.h>
33 #include <linux/errno.h>
34 #include <linux/bootmem.h>
38 #include <asm/pci_x86.h>
39 #include <asm/io_apic.h>
43 * This list of dynamic mappings is for temporarily maintaining
44 * original BIOS BAR addresses for possible reinstatement.
46 struct pcibios_fwaddrmap {
47 struct list_head list;
49 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
52 static LIST_HEAD(pcibios_fwaddrmappings);
53 static DEFINE_SPINLOCK(pcibios_fwaddrmap_lock);
55 /* Must be called with 'pcibios_fwaddrmap_lock' lock held. */
56 static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev)
58 struct pcibios_fwaddrmap *map;
60 list_for_each_entry(map, &pcibios_fwaddrmappings, list)
68 pcibios_save_fw_addr(struct pci_dev *dev, int idx, resource_size_t fw_addr)
71 struct pcibios_fwaddrmap *map;
73 spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
74 map = pcibios_fwaddrmap_lookup(dev);
76 spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
77 map = kzalloc(sizeof(*map), GFP_KERNEL);
81 map->dev = pci_dev_get(dev);
82 map->fw_addr[idx] = fw_addr;
83 INIT_LIST_HEAD(&map->list);
85 spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
86 list_add_tail(&map->list, &pcibios_fwaddrmappings);
88 map->fw_addr[idx] = fw_addr;
89 spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
92 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
95 struct pcibios_fwaddrmap *map;
96 resource_size_t fw_addr = 0;
98 spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
99 map = pcibios_fwaddrmap_lookup(dev);
101 fw_addr = map->fw_addr[idx];
102 spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
107 static void pcibios_fw_addr_list_del(void)
110 struct pcibios_fwaddrmap *entry, *next;
112 spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
113 list_for_each_entry_safe(entry, next, &pcibios_fwaddrmappings, list) {
114 list_del(&entry->list);
115 pci_dev_put(entry->dev);
118 spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
122 skip_isa_ioresource_align(struct pci_dev *dev) {
124 if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
125 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
131 * We need to avoid collisions with `mirrored' VGA ports
132 * and other strange ISA hardware, so we always want the
133 * addresses to be allocated in the 0x000-0x0ff region
136 * Why? Because some silly external IO cards only decode
137 * the low 10 bits of the IO address. The 0x00-0xff region
138 * is reserved for motherboard devices that decode all 16
139 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
140 * but we want to try to avoid allocating at 0x2900-0x2bff
141 * which might have be mirrored at 0x0100-0x03ff..
144 pcibios_align_resource(void *data, const struct resource *res,
145 resource_size_t size, resource_size_t align)
147 struct pci_dev *dev = data;
148 resource_size_t start = res->start;
150 if (res->flags & IORESOURCE_IO) {
151 if (skip_isa_ioresource_align(dev))
154 start = (start + 0x3ff) & ~0x3ff;
158 EXPORT_SYMBOL(pcibios_align_resource);
161 * Handle resources of PCI devices. If the world were perfect, we could
162 * just allocate all the resource regions and do nothing more. It isn't.
163 * On the other hand, we cannot just re-allocate all devices, as it would
164 * require us to know lots of host bridge internals. So we attempt to
165 * keep as much of the original configuration as possible, but tweak it
166 * when it's found to be wrong.
168 * Known BIOS problems we have to work around:
169 * - I/O or memory regions not configured
170 * - regions configured, but not enabled in the command register
171 * - bogus I/O addresses above 64K used
172 * - expansion ROMs left enabled (this may sound harmless, but given
173 * the fact the PCI specs explicitly allow address decoders to be
174 * shared between expansion ROMs and other resource regions, it's
175 * at least dangerous)
176 * - bad resource sizes or overlaps with other regions
179 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
180 * This gives us fixed barriers on where we can allocate.
181 * (2) Allocate resources for all enabled devices. If there is
182 * a collision, just mark the resource as unallocated. Also
183 * disable expansion ROMs during this step.
184 * (3) Try to allocate resources for disabled devices. If the
185 * resources were assigned correctly, everything goes well,
186 * if they weren't, they won't disturb allocation of other
188 * (4) Assign new addresses to resources which were either
189 * not configured at all or misconfigured. If explicitly
190 * requested by the user, configure expansion ROM address
194 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
201 /* Depth-First Search on bus tree */
202 list_for_each_entry(bus, bus_list, node) {
203 if ((dev = bus->self)) {
204 for (idx = PCI_BRIDGE_RESOURCES;
205 idx < PCI_NUM_RESOURCES; idx++) {
206 r = &dev->resource[idx];
210 pci_claim_resource(dev, idx) < 0) {
212 * Something is wrong with the region.
213 * Invalidate the resource to prevent
214 * child resource allocations in this
217 r->start = r->end = 0;
222 pcibios_allocate_bus_resources(&bus->children);
226 struct pci_check_idx_range {
231 static void __init pcibios_allocate_resources(int pass)
233 struct pci_dev *dev = NULL;
234 int idx, disabled, i;
238 struct pci_check_idx_range idx_range[] = {
239 { PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
240 #ifdef CONFIG_PCI_IOV
241 { PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
245 for_each_pci_dev(dev) {
246 pci_read_config_word(dev, PCI_COMMAND, &command);
247 for (i = 0; i < ARRAY_SIZE(idx_range); i++)
248 for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
249 r = &dev->resource[idx];
250 if (r->parent) /* Already allocated */
252 if (!r->start) /* Address not assigned at all */
254 if (r->flags & IORESOURCE_IO)
255 disabled = !(command & PCI_COMMAND_IO);
257 disabled = !(command & PCI_COMMAND_MEMORY);
258 if (pass == disabled) {
260 "BAR %d: reserving %pr (d=%d, p=%d)\n",
261 idx, r, disabled, pass);
262 if (pci_claim_resource(dev, idx) < 0) {
263 /* We'll assign a new address later */
264 dev->fw_addr[idx] = r->start;
271 r = &dev->resource[PCI_ROM_RESOURCE];
272 if (r->flags & IORESOURCE_ROM_ENABLE) {
273 /* Turn the ROM off, leave the resource region,
274 * but keep it unregistered. */
276 dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
277 r->flags &= ~IORESOURCE_ROM_ENABLE;
278 pci_read_config_dword(dev,
279 dev->rom_base_reg, ®);
280 pci_write_config_dword(dev, dev->rom_base_reg,
281 reg & ~PCI_ROM_ADDRESS_ENABLE);
287 static int __init pcibios_assign_resources(void)
289 struct pci_dev *dev = NULL;
292 if (!(pci_probe & PCI_ASSIGN_ROMS)) {
294 * Try to use BIOS settings for ROMs, otherwise let
295 * pci_assign_unassigned_resources() allocate the new
298 for_each_pci_dev(dev) {
299 r = &dev->resource[PCI_ROM_RESOURCE];
300 if (!r->flags || !r->start)
302 if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
309 pci_assign_unassigned_resources();
314 void __init pcibios_resource_survey(void)
316 DBG("PCI: Allocating resources\n");
317 pcibios_allocate_bus_resources(&pci_root_buses);
318 pcibios_allocate_resources(0);
319 pcibios_allocate_resources(1);
321 e820_reserve_resources_late();
323 * Insert the IO APIC resources after PCI initialization has
324 * occurred to handle IO APICS that are mapped in on a BAR in
325 * PCI space, but before trying to assign unassigned pci res.
327 ioapic_insert_resources();
331 * called in fs_initcall (one below subsys_initcall),
332 * give a chance for motherboard reserve resources
334 fs_initcall(pcibios_assign_resources);
336 static const struct vm_operations_struct pci_mmap_ops = {
337 .access = generic_access_phys,
340 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
341 enum pci_mmap_state mmap_state, int write_combine)
345 /* I/O space cannot be accessed via normal processor loads and
346 * stores on this platform.
348 if (mmap_state == pci_mmap_io)
351 prot = pgprot_val(vma->vm_page_prot);
354 * Return error if pat is not enabled and write_combine is requested.
355 * Caller can followup with UC MINUS request and add a WC mtrr if there
356 * is a free mtrr slot.
358 if (!pat_enabled && write_combine)
361 if (pat_enabled && write_combine)
362 prot |= _PAGE_CACHE_WC;
363 else if (pat_enabled || boot_cpu_data.x86 > 3)
365 * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
366 * To avoid attribute conflicts, request UC MINUS here
369 prot |= _PAGE_CACHE_UC_MINUS;
371 prot |= _PAGE_IOMAP; /* creating a mapping for IO */
373 vma->vm_page_prot = __pgprot(prot);
375 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
376 vma->vm_end - vma->vm_start,
380 vma->vm_ops = &pci_mmap_ops;