2 * IOSF-SB MailBox Interface Driver
3 * Copyright (c) 2013, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * The IOSF-SB is a fabric bus available on Atom based SOC's that uses a
16 * mailbox interface (MBI) to communicate with mutiple devices. This
17 * driver implements access to this interface for those platforms that can
18 * enumerate the device using PCI.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/spinlock.h>
24 #include <linux/pci.h>
25 #include <linux/debugfs.h>
26 #include <linux/capability.h>
28 #include <asm/iosf_mbi.h>
30 #define PCI_DEVICE_ID_BAYTRAIL 0x0F00
31 #define PCI_DEVICE_ID_BRASWELL 0x2280
32 #define PCI_DEVICE_ID_QUARK_X1000 0x0958
34 static struct pci_dev *mbi_pdev;
35 static DEFINE_SPINLOCK(iosf_mbi_lock);
37 static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
39 return (op << 24) | (port << 16) | (offset << 8) | MBI_ENABLE;
42 static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr)
50 result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
56 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
60 result = pci_read_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
67 dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
71 static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr)
78 result = pci_write_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
83 result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
89 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
96 dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
100 int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
106 /* Access to the GFX unit is handled by GPU code */
107 if (port == BT_MBI_UNIT_GFX) {
112 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
113 mcrx = offset & MBI_MASK_HI;
115 spin_lock_irqsave(&iosf_mbi_lock, flags);
116 ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr);
117 spin_unlock_irqrestore(&iosf_mbi_lock, flags);
121 EXPORT_SYMBOL(iosf_mbi_read);
123 int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
129 /* Access to the GFX unit is handled by GPU code */
130 if (port == BT_MBI_UNIT_GFX) {
135 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
136 mcrx = offset & MBI_MASK_HI;
138 spin_lock_irqsave(&iosf_mbi_lock, flags);
139 ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr);
140 spin_unlock_irqrestore(&iosf_mbi_lock, flags);
144 EXPORT_SYMBOL(iosf_mbi_write);
146 int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
153 /* Access to the GFX unit is handled by GPU code */
154 if (port == BT_MBI_UNIT_GFX) {
159 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
160 mcrx = offset & MBI_MASK_HI;
162 spin_lock_irqsave(&iosf_mbi_lock, flags);
164 /* Read current mdr value */
165 ret = iosf_mbi_pci_read_mdr(mcrx, mcr & MBI_RD_MASK, &value);
167 spin_unlock_irqrestore(&iosf_mbi_lock, flags);
177 ret = iosf_mbi_pci_write_mdr(mcrx, mcr | MBI_WR_MASK, value);
179 spin_unlock_irqrestore(&iosf_mbi_lock, flags);
183 EXPORT_SYMBOL(iosf_mbi_modify);
185 bool iosf_mbi_available(void)
187 /* Mbi isn't hot-pluggable. No remove routine is provided */
190 EXPORT_SYMBOL(iosf_mbi_available);
192 #ifdef CONFIG_IOSF_MBI_DEBUG
197 static int mcr_get(void *data, u64 *val)
203 static int mcr_set(void *data, u64 val)
205 u8 command = ((u32)val & 0xFF000000) >> 24,
206 port = ((u32)val & 0x00FF0000) >> 16,
207 offset = ((u32)val & 0x0000FF00) >> 8;
212 if (!capable(CAP_SYS_RAWIO))
216 err = iosf_mbi_write(port,
221 err = iosf_mbi_read(port,
228 DEFINE_SIMPLE_ATTRIBUTE(iosf_mcr_fops, mcr_get, mcr_set , "%llx\n");
230 static struct dentry *iosf_dbg;
232 static void iosf_sideband_debug_init(void)
236 iosf_dbg = debugfs_create_dir("iosf_sb", NULL);
237 if (IS_ERR_OR_NULL(iosf_dbg))
241 d = debugfs_create_x32("mdr", 0660, iosf_dbg, &dbg_mdr);
246 d = debugfs_create_x32("mcrx", 0660, iosf_dbg, &dbg_mcrx);
250 /* mcr - initiates mailbox tranaction */
251 d = debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops);
258 debugfs_remove_recursive(d);
261 static void iosf_debugfs_init(void)
263 iosf_sideband_debug_init();
266 static void iosf_debugfs_remove(void)
268 debugfs_remove_recursive(iosf_dbg);
271 static inline void iosf_debugfs_init(void) { }
272 static inline void iosf_debugfs_remove(void) { }
273 #endif /* CONFIG_IOSF_MBI_DEBUG */
275 static int iosf_mbi_probe(struct pci_dev *pdev,
276 const struct pci_device_id *unused)
280 ret = pci_enable_device(pdev);
282 dev_err(&pdev->dev, "error: could not enable device\n");
286 mbi_pdev = pci_dev_get(pdev);
290 static const struct pci_device_id iosf_mbi_pci_ids[] = {
291 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
292 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRASWELL) },
293 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
296 MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);
298 static struct pci_driver iosf_mbi_pci_driver = {
299 .name = "iosf_mbi_pci",
300 .probe = iosf_mbi_probe,
301 .id_table = iosf_mbi_pci_ids,
304 static int __init iosf_mbi_init(void)
308 return pci_register_driver(&iosf_mbi_pci_driver);
311 static void __exit iosf_mbi_exit(void)
313 iosf_debugfs_remove();
315 pci_unregister_driver(&iosf_mbi_pci_driver);
316 pci_dev_put(mbi_pdev);
320 module_init(iosf_mbi_init);
321 module_exit(iosf_mbi_exit);
323 MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>");
324 MODULE_DESCRIPTION("IOSF Mailbox Interface accessor");
325 MODULE_LICENSE("GPL v2");