2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
34 #include <acpi/acpi_bus.h>
40 #include <asm/proto.h>
41 #include <asm/mach_apic.h>
45 #define __apicdebuginit __init
47 int sis_apic_bug; /* not actually supported, dummy for compile */
49 static int no_timer_check;
51 int disable_timer_pin_1 __initdata;
53 /* Where if anywhere is the i8259 connect in external int mode */
54 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
56 static DEFINE_SPINLOCK(ioapic_lock);
59 * # of IRQ routing registers
61 int nr_ioapic_registers[MAX_IO_APICS];
64 * Rough estimation of how many shared IRQs there are, can
67 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
68 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
71 * This is performance-critical, we want to do it O(1)
73 * the indexing order of this array favors 1:1 mappings
74 * between pins and IRQs.
77 static struct irq_pin_list {
78 short apic, pin, next;
79 } irq_2_pin[PIN_MAP_SIZE];
81 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
83 #define vector_to_irq(vector) \
84 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
86 #define vector_to_irq(vector) (vector)
89 #define __DO_ACTION(R, ACTION, FINAL) \
93 struct irq_pin_list *entry = irq_2_pin + irq; \
95 BUG_ON(irq >= NR_IRQS); \
101 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
103 io_apic_modify(entry->apic, reg); \
106 entry = irq_2_pin + entry->next; \
112 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
118 cpus_and(tmp, mask, cpu_online_map);
122 cpus_and(mask, tmp, CPU_MASK_ALL);
124 dest = cpu_mask_to_apicid(mask);
127 * Only the high 8 bits are valid.
129 dest = SET_APIC_LOGICAL_ID(dest);
131 spin_lock_irqsave(&ioapic_lock, flags);
132 __DO_ACTION(1, = dest, )
133 set_irq_info(irq, mask);
134 spin_unlock_irqrestore(&ioapic_lock, flags);
138 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
141 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
142 * shared ISA-space IRQs, so we have to support them. We are super
143 * fast in the common case, and fast for shared ISA-space IRQs.
145 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
147 static int first_free_entry = NR_IRQS;
148 struct irq_pin_list *entry = irq_2_pin + irq;
150 BUG_ON(irq >= NR_IRQS);
152 entry = irq_2_pin + entry->next;
154 if (entry->pin != -1) {
155 entry->next = first_free_entry;
156 entry = irq_2_pin + entry->next;
157 if (++first_free_entry >= PIN_MAP_SIZE)
158 panic("io_apic.c: ran out of irq_2_pin entries!");
165 #define DO_ACTION(name,R,ACTION, FINAL) \
167 static void name##_IO_APIC_irq (unsigned int irq) \
168 __DO_ACTION(R, ACTION, FINAL)
170 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
172 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
175 static void mask_IO_APIC_irq (unsigned int irq)
179 spin_lock_irqsave(&ioapic_lock, flags);
180 __mask_IO_APIC_irq(irq);
181 spin_unlock_irqrestore(&ioapic_lock, flags);
184 static void unmask_IO_APIC_irq (unsigned int irq)
188 spin_lock_irqsave(&ioapic_lock, flags);
189 __unmask_IO_APIC_irq(irq);
190 spin_unlock_irqrestore(&ioapic_lock, flags);
193 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
195 struct IO_APIC_route_entry entry;
198 /* Check delivery_mode to be sure we're not clearing an SMI pin */
199 spin_lock_irqsave(&ioapic_lock, flags);
200 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
201 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
202 spin_unlock_irqrestore(&ioapic_lock, flags);
203 if (entry.delivery_mode == dest_SMI)
206 * Disable it in the IO-APIC irq-routing table:
208 memset(&entry, 0, sizeof(entry));
210 spin_lock_irqsave(&ioapic_lock, flags);
211 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
212 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
213 spin_unlock_irqrestore(&ioapic_lock, flags);
216 static void clear_IO_APIC (void)
220 for (apic = 0; apic < nr_ioapics; apic++)
221 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
222 clear_IO_APIC_pin(apic, pin);
226 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
227 * specific CPU-side IRQs.
231 static int pirq_entries [MAX_PIRQS];
232 static int pirqs_enabled;
233 int skip_ioapic_setup;
236 /* dummy parsing: see setup.c */
238 static int __init disable_ioapic_setup(char *str)
240 skip_ioapic_setup = 1;
244 static int __init enable_ioapic_setup(char *str)
247 skip_ioapic_setup = 0;
251 __setup("noapic", disable_ioapic_setup);
252 __setup("apic", enable_ioapic_setup);
254 #include <asm/pci-direct.h>
255 #include <linux/pci_ids.h>
256 #include <linux/pci.h>
258 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
259 off. Check for an Nvidia or VIA PCI bridge and turn it off.
260 Use pci direct infrastructure because this runs before the PCI subsystem.
262 Can be overwritten with "apic"
264 And another hack to disable the IOMMU on VIA chipsets.
266 ... and others. Really should move this somewhere else.
269 void __init check_ioapic(void)
272 /* Poor man's PCI discovery */
273 for (num = 0; num < 32; num++) {
274 for (slot = 0; slot < 32; slot++) {
275 for (func = 0; func < 8; func++) {
279 class = read_pci_config(num,slot,func,
281 if (class == 0xffffffff)
284 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
287 vendor = read_pci_config(num, slot, func,
291 case PCI_VENDOR_ID_VIA:
292 #ifdef CONFIG_GART_IOMMU
293 if ((end_pfn > MAX_DMA32_PFN ||
295 !iommu_aperture_allowed) {
297 "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
298 iommu_aperture_disabled = 1;
302 case PCI_VENDOR_ID_NVIDIA:
304 /* All timer overrides on Nvidia
305 seem to be wrong. Skip them. */
306 acpi_skip_timer_override = 1;
308 "Nvidia board detected. Ignoring ACPI timer override.\n");
310 /* RED-PEN skip them on mptables too? */
312 case PCI_VENDOR_ID_ATI:
313 if (apic_runs_main_timer != 0)
316 /* Don't do this for laptops right
317 right now because their timer
318 doesn't necessarily tick in C2/3 */
319 if (acpi_fadt.revision >= 3 &&
320 (acpi_fadt.plvl2_lat + acpi_fadt.plvl3_lat) < 1100) {
322 "ATI board detected, but seems to be a laptop. Timer might be shakey, sorry\n");
327 "ATI board detected. Using APIC/PM timer.\n");
328 apic_runs_main_timer = 1;
333 /* No multi-function device? */
334 type = read_pci_config_byte(num,slot,func,
343 static int __init ioapic_pirq_setup(char *str)
346 int ints[MAX_PIRQS+1];
348 get_options(str, ARRAY_SIZE(ints), ints);
350 for (i = 0; i < MAX_PIRQS; i++)
351 pirq_entries[i] = -1;
354 apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
356 if (ints[0] < MAX_PIRQS)
359 for (i = 0; i < max; i++) {
360 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
362 * PIRQs are mapped upside down, usually.
364 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
369 __setup("pirq=", ioapic_pirq_setup);
372 * Find the IRQ entry number of a certain pin.
374 static int find_irq_entry(int apic, int pin, int type)
378 for (i = 0; i < mp_irq_entries; i++)
379 if (mp_irqs[i].mpc_irqtype == type &&
380 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
381 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
382 mp_irqs[i].mpc_dstirq == pin)
389 * Find the pin to which IRQ[irq] (ISA) is connected
391 static int __init find_isa_irq_pin(int irq, int type)
395 for (i = 0; i < mp_irq_entries; i++) {
396 int lbus = mp_irqs[i].mpc_srcbus;
398 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
399 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
400 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
401 (mp_irqs[i].mpc_irqtype == type) &&
402 (mp_irqs[i].mpc_srcbusirq == irq))
404 return mp_irqs[i].mpc_dstirq;
409 static int __init find_isa_irq_apic(int irq, int type)
413 for (i = 0; i < mp_irq_entries; i++) {
414 int lbus = mp_irqs[i].mpc_srcbus;
416 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
417 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
418 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
419 (mp_irqs[i].mpc_irqtype == type) &&
420 (mp_irqs[i].mpc_srcbusirq == irq))
423 if (i < mp_irq_entries) {
425 for(apic = 0; apic < nr_ioapics; apic++) {
426 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
435 * Find a specific PCI IRQ entry.
436 * Not an __init, possibly needed by modules
438 static int pin_2_irq(int idx, int apic, int pin);
440 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
442 int apic, i, best_guess = -1;
444 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
446 if (mp_bus_id_to_pci_bus[bus] == -1) {
447 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
450 for (i = 0; i < mp_irq_entries; i++) {
451 int lbus = mp_irqs[i].mpc_srcbus;
453 for (apic = 0; apic < nr_ioapics; apic++)
454 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
455 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
458 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
459 !mp_irqs[i].mpc_irqtype &&
461 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
462 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
464 if (!(apic || IO_APIC_IRQ(irq)))
467 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
470 * Use the first all-but-pin matching entry as a
471 * best-guess fuzzy result for broken mptables.
477 BUG_ON(best_guess >= NR_IRQS);
482 * EISA Edge/Level control register, ELCR
484 static int EISA_ELCR(unsigned int irq)
487 unsigned int port = 0x4d0 + (irq >> 3);
488 return (inb(port) >> (irq & 7)) & 1;
490 apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
494 /* EISA interrupts are always polarity zero and can be edge or level
495 * trigger depending on the ELCR value. If an interrupt is listed as
496 * EISA conforming in the MP table, that means its trigger type must
497 * be read in from the ELCR */
499 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
500 #define default_EISA_polarity(idx) (0)
502 /* ISA interrupts are always polarity zero edge triggered,
503 * when listed as conforming in the MP table. */
505 #define default_ISA_trigger(idx) (0)
506 #define default_ISA_polarity(idx) (0)
508 /* PCI interrupts are always polarity one level triggered,
509 * when listed as conforming in the MP table. */
511 #define default_PCI_trigger(idx) (1)
512 #define default_PCI_polarity(idx) (1)
514 /* MCA interrupts are always polarity zero level triggered,
515 * when listed as conforming in the MP table. */
517 #define default_MCA_trigger(idx) (1)
518 #define default_MCA_polarity(idx) (0)
520 static int __init MPBIOS_polarity(int idx)
522 int bus = mp_irqs[idx].mpc_srcbus;
526 * Determine IRQ line polarity (high active or low active):
528 switch (mp_irqs[idx].mpc_irqflag & 3)
530 case 0: /* conforms, ie. bus-type dependent polarity */
532 switch (mp_bus_id_to_type[bus])
534 case MP_BUS_ISA: /* ISA pin */
536 polarity = default_ISA_polarity(idx);
539 case MP_BUS_EISA: /* EISA pin */
541 polarity = default_EISA_polarity(idx);
544 case MP_BUS_PCI: /* PCI pin */
546 polarity = default_PCI_polarity(idx);
549 case MP_BUS_MCA: /* MCA pin */
551 polarity = default_MCA_polarity(idx);
556 printk(KERN_WARNING "broken BIOS!!\n");
563 case 1: /* high active */
568 case 2: /* reserved */
570 printk(KERN_WARNING "broken BIOS!!\n");
574 case 3: /* low active */
579 default: /* invalid */
581 printk(KERN_WARNING "broken BIOS!!\n");
589 static int MPBIOS_trigger(int idx)
591 int bus = mp_irqs[idx].mpc_srcbus;
595 * Determine IRQ trigger mode (edge or level sensitive):
597 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
599 case 0: /* conforms, ie. bus-type dependent */
601 switch (mp_bus_id_to_type[bus])
603 case MP_BUS_ISA: /* ISA pin */
605 trigger = default_ISA_trigger(idx);
608 case MP_BUS_EISA: /* EISA pin */
610 trigger = default_EISA_trigger(idx);
613 case MP_BUS_PCI: /* PCI pin */
615 trigger = default_PCI_trigger(idx);
618 case MP_BUS_MCA: /* MCA pin */
620 trigger = default_MCA_trigger(idx);
625 printk(KERN_WARNING "broken BIOS!!\n");
637 case 2: /* reserved */
639 printk(KERN_WARNING "broken BIOS!!\n");
648 default: /* invalid */
650 printk(KERN_WARNING "broken BIOS!!\n");
658 static inline int irq_polarity(int idx)
660 return MPBIOS_polarity(idx);
663 static inline int irq_trigger(int idx)
665 return MPBIOS_trigger(idx);
668 static int next_irq = 16;
671 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
672 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
673 * from ACPI, which can reach 800 in large boxen.
675 * Compact the sparse GSI space into a sequential IRQ series and reuse
676 * vectors if possible.
678 int gsi_irq_sharing(int gsi)
680 int i, tries, vector;
682 BUG_ON(gsi >= NR_IRQ_VECTORS);
684 if (platform_legacy_irq(gsi))
687 if (gsi_2_irq[gsi] != 0xFF)
688 return (int)gsi_2_irq[gsi];
692 vector = assign_irq_vector(gsi);
695 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
696 * use of vector and if found, return that IRQ. However, we never want
697 * to share legacy IRQs, which usually have a different trigger mode
700 for (i = 0; i < NR_IRQS; i++)
701 if (IO_APIC_VECTOR(i) == vector)
703 if (platform_legacy_irq(i)) {
705 IO_APIC_VECTOR(i) = 0;
708 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
712 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
718 BUG_ON(i >= NR_IRQS);
720 IO_APIC_VECTOR(i) = vector;
721 printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
726 static int pin_2_irq(int idx, int apic, int pin)
729 int bus = mp_irqs[idx].mpc_srcbus;
732 * Debugging check, we are in big trouble if this message pops up!
734 if (mp_irqs[idx].mpc_dstirq != pin)
735 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
737 switch (mp_bus_id_to_type[bus])
739 case MP_BUS_ISA: /* ISA pin */
743 irq = mp_irqs[idx].mpc_srcbusirq;
746 case MP_BUS_PCI: /* PCI pin */
749 * PCI IRQs are mapped in order
753 irq += nr_ioapic_registers[i++];
755 irq = gsi_irq_sharing(irq);
760 printk(KERN_ERR "unknown bus type %d.\n",bus);
765 BUG_ON(irq >= NR_IRQS);
768 * PCI IRQ command line redirection. Yes, limits are hardcoded.
770 if ((pin >= 16) && (pin <= 23)) {
771 if (pirq_entries[pin-16] != -1) {
772 if (!pirq_entries[pin-16]) {
773 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
775 irq = pirq_entries[pin-16];
776 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
781 BUG_ON(irq >= NR_IRQS);
785 static inline int IO_APIC_irq_trigger(int irq)
789 for (apic = 0; apic < nr_ioapics; apic++) {
790 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
791 idx = find_irq_entry(apic,pin,mp_INT);
792 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
793 return irq_trigger(idx);
797 * nonexistent IRQs are edge default
802 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
803 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
805 int assign_irq_vector(int irq)
807 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
809 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
810 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
811 return IO_APIC_VECTOR(irq);
814 if (current_vector == IA32_SYSCALL_VECTOR)
817 if (current_vector >= FIRST_SYSTEM_VECTOR) {
818 /* If we run out of vectors on large boxen, must share them. */
819 offset = (offset + 1) % 8;
820 current_vector = FIRST_DEVICE_VECTOR + offset;
823 vector_irq[current_vector] = irq;
824 if (irq != AUTO_ASSIGN)
825 IO_APIC_VECTOR(irq) = current_vector;
827 return current_vector;
830 extern void (*interrupt[NR_IRQS])(void);
831 static struct hw_interrupt_type ioapic_level_type;
832 static struct hw_interrupt_type ioapic_edge_type;
834 #define IOAPIC_AUTO -1
835 #define IOAPIC_EDGE 0
836 #define IOAPIC_LEVEL 1
838 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
840 if (use_pci_vector() && !platform_legacy_irq(irq)) {
841 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
842 trigger == IOAPIC_LEVEL)
843 irq_desc[vector].handler = &ioapic_level_type;
845 irq_desc[vector].handler = &ioapic_edge_type;
846 set_intr_gate(vector, interrupt[vector]);
848 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
849 trigger == IOAPIC_LEVEL)
850 irq_desc[irq].handler = &ioapic_level_type;
852 irq_desc[irq].handler = &ioapic_edge_type;
853 set_intr_gate(vector, interrupt[irq]);
857 static void __init setup_IO_APIC_irqs(void)
859 struct IO_APIC_route_entry entry;
860 int apic, pin, idx, irq, first_notcon = 1, vector;
863 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
865 for (apic = 0; apic < nr_ioapics; apic++) {
866 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
869 * add it to the IO-APIC irq-routing table:
871 memset(&entry,0,sizeof(entry));
873 entry.delivery_mode = INT_DELIVERY_MODE;
874 entry.dest_mode = INT_DEST_MODE;
875 entry.mask = 0; /* enable IRQ */
876 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
878 idx = find_irq_entry(apic,pin,mp_INT);
881 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
884 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
888 entry.trigger = irq_trigger(idx);
889 entry.polarity = irq_polarity(idx);
891 if (irq_trigger(idx)) {
894 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
897 irq = pin_2_irq(idx, apic, pin);
898 add_pin_to_irq(irq, apic, pin);
900 if (!apic && !IO_APIC_IRQ(irq))
903 if (IO_APIC_IRQ(irq)) {
904 vector = assign_irq_vector(irq);
905 entry.vector = vector;
907 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
908 if (!apic && (irq < 16))
909 disable_8259A_irq(irq);
911 spin_lock_irqsave(&ioapic_lock, flags);
912 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
913 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
914 set_native_irq_info(irq, TARGET_CPUS);
915 spin_unlock_irqrestore(&ioapic_lock, flags);
920 apic_printk(APIC_VERBOSE," not connected.\n");
924 * Set up the 8259A-master output pin as broadcast to all
927 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
929 struct IO_APIC_route_entry entry;
932 memset(&entry,0,sizeof(entry));
934 disable_8259A_irq(0);
937 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
940 * We use logical delivery to get the timer IRQ
943 entry.dest_mode = INT_DEST_MODE;
944 entry.mask = 0; /* unmask IRQ now */
945 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
946 entry.delivery_mode = INT_DELIVERY_MODE;
949 entry.vector = vector;
952 * The timer IRQ doesn't have to know that behind the
953 * scene we have a 8259A-master in AEOI mode ...
955 irq_desc[0].handler = &ioapic_edge_type;
958 * Add it to the IO-APIC irq-routing table:
960 spin_lock_irqsave(&ioapic_lock, flags);
961 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
962 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
963 spin_unlock_irqrestore(&ioapic_lock, flags);
968 void __init UNEXPECTED_IO_APIC(void)
972 void __apicdebuginit print_IO_APIC(void)
975 union IO_APIC_reg_00 reg_00;
976 union IO_APIC_reg_01 reg_01;
977 union IO_APIC_reg_02 reg_02;
980 if (apic_verbosity == APIC_QUIET)
983 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
984 for (i = 0; i < nr_ioapics; i++)
985 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
986 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
989 * We are a bit conservative about what we expect. We have to
990 * know about every hardware change ASAP.
992 printk(KERN_INFO "testing the IO APIC.......................\n");
994 for (apic = 0; apic < nr_ioapics; apic++) {
996 spin_lock_irqsave(&ioapic_lock, flags);
997 reg_00.raw = io_apic_read(apic, 0);
998 reg_01.raw = io_apic_read(apic, 1);
999 if (reg_01.bits.version >= 0x10)
1000 reg_02.raw = io_apic_read(apic, 2);
1001 spin_unlock_irqrestore(&ioapic_lock, flags);
1004 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1005 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1006 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1007 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1008 UNEXPECTED_IO_APIC();
1010 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1011 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1012 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1013 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1014 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1015 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1016 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1017 (reg_01.bits.entries != 0x2E) &&
1018 (reg_01.bits.entries != 0x3F) &&
1019 (reg_01.bits.entries != 0x03)
1021 UNEXPECTED_IO_APIC();
1023 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1024 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1025 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1026 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1027 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1028 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1029 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1030 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1032 UNEXPECTED_IO_APIC();
1033 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1034 UNEXPECTED_IO_APIC();
1036 if (reg_01.bits.version >= 0x10) {
1037 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1038 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1039 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1040 UNEXPECTED_IO_APIC();
1043 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1045 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1046 " Stat Dest Deli Vect: \n");
1048 for (i = 0; i <= reg_01.bits.entries; i++) {
1049 struct IO_APIC_route_entry entry;
1051 spin_lock_irqsave(&ioapic_lock, flags);
1052 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1053 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1054 spin_unlock_irqrestore(&ioapic_lock, flags);
1056 printk(KERN_DEBUG " %02x %03X %02X ",
1058 entry.dest.logical.logical_dest,
1059 entry.dest.physical.physical_dest
1062 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1067 entry.delivery_status,
1069 entry.delivery_mode,
1074 if (use_pci_vector())
1075 printk(KERN_INFO "Using vector-based indexing\n");
1076 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1077 for (i = 0; i < NR_IRQS; i++) {
1078 struct irq_pin_list *entry = irq_2_pin + i;
1081 if (use_pci_vector() && !platform_legacy_irq(i))
1082 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1084 printk(KERN_DEBUG "IRQ%d ", i);
1086 printk("-> %d:%d", entry->apic, entry->pin);
1089 entry = irq_2_pin + entry->next;
1094 printk(KERN_INFO ".................................... done.\n");
1101 static __apicdebuginit void print_APIC_bitfield (int base)
1106 if (apic_verbosity == APIC_QUIET)
1109 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1110 for (i = 0; i < 8; i++) {
1111 v = apic_read(base + i*0x10);
1112 for (j = 0; j < 32; j++) {
1122 void __apicdebuginit print_local_APIC(void * dummy)
1124 unsigned int v, ver, maxlvt;
1126 if (apic_verbosity == APIC_QUIET)
1129 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1130 smp_processor_id(), hard_smp_processor_id());
1131 v = apic_read(APIC_ID);
1132 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1133 v = apic_read(APIC_LVR);
1134 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1135 ver = GET_APIC_VERSION(v);
1136 maxlvt = get_maxlvt();
1138 v = apic_read(APIC_TASKPRI);
1139 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1141 v = apic_read(APIC_ARBPRI);
1142 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1143 v & APIC_ARBPRI_MASK);
1144 v = apic_read(APIC_PROCPRI);
1145 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1147 v = apic_read(APIC_EOI);
1148 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1149 v = apic_read(APIC_RRR);
1150 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1151 v = apic_read(APIC_LDR);
1152 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1153 v = apic_read(APIC_DFR);
1154 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1155 v = apic_read(APIC_SPIV);
1156 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1158 printk(KERN_DEBUG "... APIC ISR field:\n");
1159 print_APIC_bitfield(APIC_ISR);
1160 printk(KERN_DEBUG "... APIC TMR field:\n");
1161 print_APIC_bitfield(APIC_TMR);
1162 printk(KERN_DEBUG "... APIC IRR field:\n");
1163 print_APIC_bitfield(APIC_IRR);
1165 v = apic_read(APIC_ESR);
1166 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1168 v = apic_read(APIC_ICR);
1169 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1170 v = apic_read(APIC_ICR2);
1171 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1173 v = apic_read(APIC_LVTT);
1174 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1176 if (maxlvt > 3) { /* PC is LVT#4. */
1177 v = apic_read(APIC_LVTPC);
1178 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1180 v = apic_read(APIC_LVT0);
1181 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1182 v = apic_read(APIC_LVT1);
1183 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1185 if (maxlvt > 2) { /* ERR is LVT#3. */
1186 v = apic_read(APIC_LVTERR);
1187 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1190 v = apic_read(APIC_TMICT);
1191 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1192 v = apic_read(APIC_TMCCT);
1193 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1194 v = apic_read(APIC_TDCR);
1195 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1199 void print_all_local_APICs (void)
1201 on_each_cpu(print_local_APIC, NULL, 1, 1);
1204 void __apicdebuginit print_PIC(void)
1207 unsigned long flags;
1209 if (apic_verbosity == APIC_QUIET)
1212 printk(KERN_DEBUG "\nprinting PIC contents\n");
1214 spin_lock_irqsave(&i8259A_lock, flags);
1216 v = inb(0xa1) << 8 | inb(0x21);
1217 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1219 v = inb(0xa0) << 8 | inb(0x20);
1220 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1224 v = inb(0xa0) << 8 | inb(0x20);
1228 spin_unlock_irqrestore(&i8259A_lock, flags);
1230 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1232 v = inb(0x4d1) << 8 | inb(0x4d0);
1233 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1238 static void __init enable_IO_APIC(void)
1240 union IO_APIC_reg_01 reg_01;
1241 int i8259_apic, i8259_pin;
1243 unsigned long flags;
1245 for (i = 0; i < PIN_MAP_SIZE; i++) {
1246 irq_2_pin[i].pin = -1;
1247 irq_2_pin[i].next = 0;
1250 for (i = 0; i < MAX_PIRQS; i++)
1251 pirq_entries[i] = -1;
1254 * The number of IO-APIC IRQ registers (== #pins):
1256 for (apic = 0; apic < nr_ioapics; apic++) {
1257 spin_lock_irqsave(&ioapic_lock, flags);
1258 reg_01.raw = io_apic_read(apic, 1);
1259 spin_unlock_irqrestore(&ioapic_lock, flags);
1260 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1262 for(apic = 0; apic < nr_ioapics; apic++) {
1264 /* See if any of the pins is in ExtINT mode */
1265 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1266 struct IO_APIC_route_entry entry;
1267 spin_lock_irqsave(&ioapic_lock, flags);
1268 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1269 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1270 spin_unlock_irqrestore(&ioapic_lock, flags);
1273 /* If the interrupt line is enabled and in ExtInt mode
1274 * I have found the pin where the i8259 is connected.
1276 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1277 ioapic_i8259.apic = apic;
1278 ioapic_i8259.pin = pin;
1284 /* Look to see what if the MP table has reported the ExtINT */
1285 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1286 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1287 /* Trust the MP table if nothing is setup in the hardware */
1288 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1289 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1290 ioapic_i8259.pin = i8259_pin;
1291 ioapic_i8259.apic = i8259_apic;
1293 /* Complain if the MP table and the hardware disagree */
1294 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1295 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1297 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1301 * Do not trust the IO-APIC being empty at bootup
1307 * Not an __init, needed by the reboot code
1309 void disable_IO_APIC(void)
1312 * Clear the IO-APIC before rebooting:
1317 * If the i8259 is routed through an IOAPIC
1318 * Put that IOAPIC in virtual wire mode
1319 * so legacy interrupts can be delivered.
1321 if (ioapic_i8259.pin != -1) {
1322 struct IO_APIC_route_entry entry;
1323 unsigned long flags;
1325 memset(&entry, 0, sizeof(entry));
1326 entry.mask = 0; /* Enabled */
1327 entry.trigger = 0; /* Edge */
1329 entry.polarity = 0; /* High */
1330 entry.delivery_status = 0;
1331 entry.dest_mode = 0; /* Physical */
1332 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1334 entry.dest.physical.physical_dest =
1335 GET_APIC_ID(apic_read(APIC_ID));
1338 * Add it to the IO-APIC irq-routing table:
1340 spin_lock_irqsave(&ioapic_lock, flags);
1341 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1342 *(((int *)&entry)+1));
1343 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1344 *(((int *)&entry)+0));
1345 spin_unlock_irqrestore(&ioapic_lock, flags);
1348 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1352 * function to set the IO-APIC physical IDs based on the
1353 * values stored in the MPC table.
1355 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1358 static void __init setup_ioapic_ids_from_mpc (void)
1360 union IO_APIC_reg_00 reg_00;
1363 unsigned char old_id;
1364 unsigned long flags;
1367 * Set the IOAPIC ID to the value stored in the MPC table.
1369 for (apic = 0; apic < nr_ioapics; apic++) {
1371 /* Read the register 0 value */
1372 spin_lock_irqsave(&ioapic_lock, flags);
1373 reg_00.raw = io_apic_read(apic, 0);
1374 spin_unlock_irqrestore(&ioapic_lock, flags);
1376 old_id = mp_ioapics[apic].mpc_apicid;
1379 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1383 * We need to adjust the IRQ routing table
1384 * if the ID changed.
1386 if (old_id != mp_ioapics[apic].mpc_apicid)
1387 for (i = 0; i < mp_irq_entries; i++)
1388 if (mp_irqs[i].mpc_dstapic == old_id)
1389 mp_irqs[i].mpc_dstapic
1390 = mp_ioapics[apic].mpc_apicid;
1393 * Read the right value from the MPC table and
1394 * write it into the ID register.
1396 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1397 mp_ioapics[apic].mpc_apicid);
1399 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1400 spin_lock_irqsave(&ioapic_lock, flags);
1401 io_apic_write(apic, 0, reg_00.raw);
1402 spin_unlock_irqrestore(&ioapic_lock, flags);
1407 spin_lock_irqsave(&ioapic_lock, flags);
1408 reg_00.raw = io_apic_read(apic, 0);
1409 spin_unlock_irqrestore(&ioapic_lock, flags);
1410 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1411 printk("could not set ID!\n");
1413 apic_printk(APIC_VERBOSE," ok.\n");
1418 * There is a nasty bug in some older SMP boards, their mptable lies
1419 * about the timer IRQ. We do the following to work around the situation:
1421 * - timer IRQ defaults to IO-APIC IRQ
1422 * - if this function detects that timer IRQs are defunct, then we fall
1423 * back to ISA timer IRQs
1425 static int __init timer_irq_works(void)
1427 unsigned long t1 = jiffies;
1430 /* Let ten ticks pass... */
1431 mdelay((10 * 1000) / HZ);
1434 * Expect a few ticks at least, to be sure some possible
1435 * glue logic does not lock up after one or two first
1436 * ticks in a non-ExtINT mode. Also the local APIC
1437 * might have cached one ExtINT interrupt. Finally, at
1438 * least one tick may be lost due to delays.
1442 if (jiffies - t1 > 4)
1448 * In the SMP+IOAPIC case it might happen that there are an unspecified
1449 * number of pending IRQ events unhandled. These cases are very rare,
1450 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1451 * better to do it this way as thus we do not have to be aware of
1452 * 'pending' interrupts in the IRQ path, except at this point.
1455 * Edge triggered needs to resend any interrupt
1456 * that was delayed but this is now handled in the device
1461 * Starting up a edge-triggered IO-APIC interrupt is
1462 * nasty - we need to make sure that we get the edge.
1463 * If it is already asserted for some reason, we need
1464 * return 1 to indicate that is was pending.
1466 * This is not complete - we should be able to fake
1467 * an edge even if it isn't on the 8259A...
1470 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1472 int was_pending = 0;
1473 unsigned long flags;
1475 spin_lock_irqsave(&ioapic_lock, flags);
1477 disable_8259A_irq(irq);
1478 if (i8259A_irq_pending(irq))
1481 __unmask_IO_APIC_irq(irq);
1482 spin_unlock_irqrestore(&ioapic_lock, flags);
1488 * Once we have recorded IRQ_PENDING already, we can mask the
1489 * interrupt for real. This prevents IRQ storms from unhandled
1492 static void ack_edge_ioapic_irq(unsigned int irq)
1495 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1496 == (IRQ_PENDING | IRQ_DISABLED))
1497 mask_IO_APIC_irq(irq);
1502 * Level triggered interrupts can just be masked,
1503 * and shutting down and starting up the interrupt
1504 * is the same as enabling and disabling them -- except
1505 * with a startup need to return a "was pending" value.
1507 * Level triggered interrupts are special because we
1508 * do not touch any IO-APIC register while handling
1509 * them. We ack the APIC in the end-IRQ handler, not
1510 * in the start-IRQ-handler. Protection against reentrance
1511 * from the same interrupt is still provided, both by the
1512 * generic IRQ layer and by the fact that an unacked local
1513 * APIC does not accept IRQs.
1515 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1517 unmask_IO_APIC_irq(irq);
1519 return 0; /* don't check for pending */
1522 static void end_level_ioapic_irq (unsigned int irq)
1528 #ifdef CONFIG_PCI_MSI
1529 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1531 int irq = vector_to_irq(vector);
1533 return startup_edge_ioapic_irq(irq);
1536 static void ack_edge_ioapic_vector(unsigned int vector)
1538 int irq = vector_to_irq(vector);
1540 move_native_irq(vector);
1541 ack_edge_ioapic_irq(irq);
1544 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1546 int irq = vector_to_irq(vector);
1548 return startup_level_ioapic_irq (irq);
1551 static void end_level_ioapic_vector (unsigned int vector)
1553 int irq = vector_to_irq(vector);
1555 move_native_irq(vector);
1556 end_level_ioapic_irq(irq);
1559 static void mask_IO_APIC_vector (unsigned int vector)
1561 int irq = vector_to_irq(vector);
1563 mask_IO_APIC_irq(irq);
1566 static void unmask_IO_APIC_vector (unsigned int vector)
1568 int irq = vector_to_irq(vector);
1570 unmask_IO_APIC_irq(irq);
1574 static void set_ioapic_affinity_vector (unsigned int vector,
1577 int irq = vector_to_irq(vector);
1579 set_native_irq_info(vector, cpu_mask);
1580 set_ioapic_affinity_irq(irq, cpu_mask);
1582 #endif // CONFIG_SMP
1583 #endif // CONFIG_PCI_MSI
1586 * Level and edge triggered IO-APIC interrupts need different handling,
1587 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1588 * handled with the level-triggered descriptor, but that one has slightly
1589 * more overhead. Level-triggered interrupts cannot be handled with the
1590 * edge-triggered handler, without risking IRQ storms and other ugly
1594 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1595 .typename = "IO-APIC-edge",
1596 .startup = startup_edge_ioapic,
1597 .shutdown = shutdown_edge_ioapic,
1598 .enable = enable_edge_ioapic,
1599 .disable = disable_edge_ioapic,
1600 .ack = ack_edge_ioapic,
1601 .end = end_edge_ioapic,
1603 .set_affinity = set_ioapic_affinity,
1607 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1608 .typename = "IO-APIC-level",
1609 .startup = startup_level_ioapic,
1610 .shutdown = shutdown_level_ioapic,
1611 .enable = enable_level_ioapic,
1612 .disable = disable_level_ioapic,
1613 .ack = mask_and_ack_level_ioapic,
1614 .end = end_level_ioapic,
1616 .set_affinity = set_ioapic_affinity,
1620 static inline void init_IO_APIC_traps(void)
1625 * NOTE! The local APIC isn't very good at handling
1626 * multiple interrupts at the same interrupt level.
1627 * As the interrupt level is determined by taking the
1628 * vector number and shifting that right by 4, we
1629 * want to spread these out a bit so that they don't
1630 * all fall in the same interrupt level.
1632 * Also, we've got to be careful not to trash gate
1633 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1635 for (irq = 0; irq < NR_IRQS ; irq++) {
1637 if (use_pci_vector()) {
1638 if (!platform_legacy_irq(tmp))
1639 if ((tmp = vector_to_irq(tmp)) == -1)
1642 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1644 * Hmm.. We don't have an entry for this,
1645 * so default to an old-fashioned 8259
1646 * interrupt if we can..
1649 make_8259A_irq(irq);
1651 /* Strange. Oh, well.. */
1652 irq_desc[irq].handler = &no_irq_type;
1657 static void enable_lapic_irq (unsigned int irq)
1661 v = apic_read(APIC_LVT0);
1662 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1665 static void disable_lapic_irq (unsigned int irq)
1669 v = apic_read(APIC_LVT0);
1670 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1673 static void ack_lapic_irq (unsigned int irq)
1678 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1680 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1681 .typename = "local-APIC-edge",
1682 .startup = NULL, /* startup_irq() not used for IRQ0 */
1683 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1684 .enable = enable_lapic_irq,
1685 .disable = disable_lapic_irq,
1686 .ack = ack_lapic_irq,
1687 .end = end_lapic_irq,
1690 static void setup_nmi (void)
1693 * Dirty trick to enable the NMI watchdog ...
1694 * We put the 8259A master into AEOI mode and
1695 * unmask on all local APICs LVT0 as NMI.
1697 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1698 * is from Maciej W. Rozycki - so we do not have to EOI from
1699 * the NMI handler or the timer interrupt.
1701 printk(KERN_INFO "activating NMI Watchdog ...");
1703 enable_NMI_through_LVT0(NULL);
1709 * This looks a bit hackish but it's about the only one way of sending
1710 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1711 * not support the ExtINT mode, unfortunately. We need to send these
1712 * cycles as some i82489DX-based boards have glue logic that keeps the
1713 * 8259A interrupt line asserted until INTA. --macro
1715 static inline void unlock_ExtINT_logic(void)
1718 struct IO_APIC_route_entry entry0, entry1;
1719 unsigned char save_control, save_freq_select;
1720 unsigned long flags;
1722 pin = find_isa_irq_pin(8, mp_INT);
1723 apic = find_isa_irq_apic(8, mp_INT);
1727 spin_lock_irqsave(&ioapic_lock, flags);
1728 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1729 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1730 spin_unlock_irqrestore(&ioapic_lock, flags);
1731 clear_IO_APIC_pin(apic, pin);
1733 memset(&entry1, 0, sizeof(entry1));
1735 entry1.dest_mode = 0; /* physical delivery */
1736 entry1.mask = 0; /* unmask IRQ now */
1737 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1738 entry1.delivery_mode = dest_ExtINT;
1739 entry1.polarity = entry0.polarity;
1743 spin_lock_irqsave(&ioapic_lock, flags);
1744 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1745 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1746 spin_unlock_irqrestore(&ioapic_lock, flags);
1748 save_control = CMOS_READ(RTC_CONTROL);
1749 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1750 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1752 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1757 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1761 CMOS_WRITE(save_control, RTC_CONTROL);
1762 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1763 clear_IO_APIC_pin(apic, pin);
1765 spin_lock_irqsave(&ioapic_lock, flags);
1766 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1767 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1768 spin_unlock_irqrestore(&ioapic_lock, flags);
1772 * This code may look a bit paranoid, but it's supposed to cooperate with
1773 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1774 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1775 * fanatically on his truly buggy board.
1777 static inline void check_timer(void)
1779 int apic1, pin1, apic2, pin2;
1783 * get/set the timer IRQ vector:
1785 disable_8259A_irq(0);
1786 vector = assign_irq_vector(0);
1787 set_intr_gate(vector, interrupt[0]);
1790 * Subtle, code in do_timer_interrupt() expects an AEOI
1791 * mode for the 8259A whenever interrupts are routed
1792 * through I/O APICs. Also IRQ0 has to be enabled in
1793 * the 8259A which implies the virtual wire has to be
1794 * disabled in the local APIC.
1796 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1798 enable_8259A_irq(0);
1800 pin1 = find_isa_irq_pin(0, mp_INT);
1801 apic1 = find_isa_irq_apic(0, mp_INT);
1802 pin2 = ioapic_i8259.pin;
1803 apic2 = ioapic_i8259.apic;
1805 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1806 vector, apic1, pin1, apic2, pin2);
1810 * Ok, does IRQ0 through the IOAPIC work?
1812 unmask_IO_APIC_irq(0);
1813 if (!no_timer_check && timer_irq_works()) {
1814 nmi_watchdog_default();
1815 if (nmi_watchdog == NMI_IO_APIC) {
1816 disable_8259A_irq(0);
1818 enable_8259A_irq(0);
1820 if (disable_timer_pin_1 > 0)
1821 clear_IO_APIC_pin(0, pin1);
1824 clear_IO_APIC_pin(apic1, pin1);
1825 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1826 "connected to IO-APIC\n");
1829 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1830 "through the 8259A ... ");
1832 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1835 * legacy devices should be connected to IO APIC #0
1837 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1838 if (timer_irq_works()) {
1840 nmi_watchdog_default();
1841 if (nmi_watchdog == NMI_IO_APIC) {
1847 * Cleanup, just in case ...
1849 clear_IO_APIC_pin(apic2, pin2);
1851 printk(" failed.\n");
1854 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1858 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1860 disable_8259A_irq(0);
1861 irq_desc[0].handler = &lapic_irq_type;
1862 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1863 enable_8259A_irq(0);
1865 if (timer_irq_works()) {
1866 apic_printk(APIC_QUIET, " works.\n");
1869 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1870 apic_printk(APIC_VERBOSE," failed.\n");
1872 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1876 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1878 unlock_ExtINT_logic();
1880 if (timer_irq_works()) {
1881 apic_printk(APIC_VERBOSE," works.\n");
1884 apic_printk(APIC_VERBOSE," failed :(.\n");
1885 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1888 static int __init notimercheck(char *s)
1893 __setup("no_timer_check", notimercheck);
1897 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1898 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1899 * Linux doesn't really care, as it's not actually used
1900 * for any interrupt handling anyway.
1902 #define PIC_IRQS (1<<2)
1904 void __init setup_IO_APIC(void)
1909 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1911 io_apic_irqs = ~PIC_IRQS;
1913 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1916 * Set up the IO-APIC IRQ routing table.
1919 setup_ioapic_ids_from_mpc();
1921 setup_IO_APIC_irqs();
1922 init_IO_APIC_traps();
1928 struct sysfs_ioapic_data {
1929 struct sys_device dev;
1930 struct IO_APIC_route_entry entry[0];
1932 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1934 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1936 struct IO_APIC_route_entry *entry;
1937 struct sysfs_ioapic_data *data;
1938 unsigned long flags;
1941 data = container_of(dev, struct sysfs_ioapic_data, dev);
1942 entry = data->entry;
1943 spin_lock_irqsave(&ioapic_lock, flags);
1944 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1945 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1946 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1948 spin_unlock_irqrestore(&ioapic_lock, flags);
1953 static int ioapic_resume(struct sys_device *dev)
1955 struct IO_APIC_route_entry *entry;
1956 struct sysfs_ioapic_data *data;
1957 unsigned long flags;
1958 union IO_APIC_reg_00 reg_00;
1961 data = container_of(dev, struct sysfs_ioapic_data, dev);
1962 entry = data->entry;
1964 spin_lock_irqsave(&ioapic_lock, flags);
1965 reg_00.raw = io_apic_read(dev->id, 0);
1966 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1967 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1968 io_apic_write(dev->id, 0, reg_00.raw);
1970 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1971 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1972 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1974 spin_unlock_irqrestore(&ioapic_lock, flags);
1979 static struct sysdev_class ioapic_sysdev_class = {
1980 set_kset_name("ioapic"),
1981 .suspend = ioapic_suspend,
1982 .resume = ioapic_resume,
1985 static int __init ioapic_init_sysfs(void)
1987 struct sys_device * dev;
1988 int i, size, error = 0;
1990 error = sysdev_class_register(&ioapic_sysdev_class);
1994 for (i = 0; i < nr_ioapics; i++ ) {
1995 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1996 * sizeof(struct IO_APIC_route_entry);
1997 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1998 if (!mp_ioapic_data[i]) {
1999 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2002 memset(mp_ioapic_data[i], 0, size);
2003 dev = &mp_ioapic_data[i]->dev;
2005 dev->cls = &ioapic_sysdev_class;
2006 error = sysdev_register(dev);
2008 kfree(mp_ioapic_data[i]);
2009 mp_ioapic_data[i] = NULL;
2010 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2018 device_initcall(ioapic_init_sysfs);
2020 /* --------------------------------------------------------------------------
2021 ACPI-based IOAPIC Configuration
2022 -------------------------------------------------------------------------- */
2026 #define IO_APIC_MAX_ID 0xFE
2028 int __init io_apic_get_version (int ioapic)
2030 union IO_APIC_reg_01 reg_01;
2031 unsigned long flags;
2033 spin_lock_irqsave(&ioapic_lock, flags);
2034 reg_01.raw = io_apic_read(ioapic, 1);
2035 spin_unlock_irqrestore(&ioapic_lock, flags);
2037 return reg_01.bits.version;
2041 int __init io_apic_get_redir_entries (int ioapic)
2043 union IO_APIC_reg_01 reg_01;
2044 unsigned long flags;
2046 spin_lock_irqsave(&ioapic_lock, flags);
2047 reg_01.raw = io_apic_read(ioapic, 1);
2048 spin_unlock_irqrestore(&ioapic_lock, flags);
2050 return reg_01.bits.entries;
2054 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2056 struct IO_APIC_route_entry entry;
2057 unsigned long flags;
2059 if (!IO_APIC_IRQ(irq)) {
2060 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2066 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2067 * Note that we mask (disable) IRQs now -- these get enabled when the
2068 * corresponding device driver registers for this IRQ.
2071 memset(&entry,0,sizeof(entry));
2073 entry.delivery_mode = INT_DELIVERY_MODE;
2074 entry.dest_mode = INT_DEST_MODE;
2075 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2076 entry.trigger = triggering;
2077 entry.polarity = polarity;
2078 entry.mask = 1; /* Disabled (masked) */
2080 irq = gsi_irq_sharing(irq);
2082 * IRQs < 16 are already in the irq_2_pin[] map
2085 add_pin_to_irq(irq, ioapic, pin);
2087 entry.vector = assign_irq_vector(irq);
2089 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2090 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2091 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2092 triggering, polarity);
2094 ioapic_register_intr(irq, entry.vector, triggering);
2096 if (!ioapic && (irq < 16))
2097 disable_8259A_irq(irq);
2099 spin_lock_irqsave(&ioapic_lock, flags);
2100 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2101 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2102 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2103 spin_unlock_irqrestore(&ioapic_lock, flags);
2108 #endif /* CONFIG_ACPI */
2112 * This function currently is only a helper for the i386 smp boot process where
2113 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2114 * so mask in all cases should simply be TARGET_CPUS
2117 void __init setup_ioapic_dest(void)
2119 int pin, ioapic, irq, irq_entry;
2121 if (skip_ioapic_setup == 1)
2124 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2125 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2126 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2127 if (irq_entry == -1)
2129 irq = pin_2_irq(irq_entry, ioapic, pin);
2130 set_ioapic_affinity_irq(irq, TARGET_CPUS);