2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
36 #include <acpi/acpi_bus.h>
43 #include <asm/proto.h>
44 #include <asm/mach_apic.h>
48 #include <asm/msidef.h>
49 #include <asm/hypertransport.h>
54 unsigned move_cleanup_count;
56 u8 move_in_progress : 1;
59 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
60 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
61 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
62 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
63 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
64 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
65 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
66 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
67 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
68 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
69 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
70 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
71 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
72 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
73 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
74 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
75 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
76 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
79 static int assign_irq_vector(int irq, cpumask_t mask);
81 #define __apicdebuginit __init
83 int sis_apic_bug; /* not actually supported, dummy for compile */
85 static int no_timer_check;
87 static int disable_timer_pin_1 __initdata;
89 int timer_over_8254 __initdata = 1;
91 /* Where if anywhere is the i8259 connect in external int mode */
92 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
94 static DEFINE_SPINLOCK(ioapic_lock);
95 DEFINE_SPINLOCK(vector_lock);
98 * # of IRQ routing registers
100 int nr_ioapic_registers[MAX_IO_APICS];
103 * Rough estimation of how many shared IRQs there are, can
104 * be changed anytime.
106 #define MAX_PLUS_SHARED_IRQS NR_IRQS
107 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
110 * This is performance-critical, we want to do it O(1)
112 * the indexing order of this array favors 1:1 mappings
113 * between pins and IRQs.
116 static struct irq_pin_list {
117 short apic, pin, next;
118 } irq_2_pin[PIN_MAP_SIZE];
122 unsigned int unused[3];
126 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
128 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
129 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
132 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
134 struct io_apic __iomem *io_apic = io_apic_base(apic);
135 writel(reg, &io_apic->index);
136 return readl(&io_apic->data);
139 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
141 struct io_apic __iomem *io_apic = io_apic_base(apic);
142 writel(reg, &io_apic->index);
143 writel(value, &io_apic->data);
147 * Re-write a value: to be used for read-modify-write
148 * cycles where the read already set up the index register.
150 static inline void io_apic_modify(unsigned int apic, unsigned int value)
152 struct io_apic __iomem *io_apic = io_apic_base(apic);
153 writel(value, &io_apic->data);
157 * Synchronize the IO-APIC and the CPU by doing
158 * a dummy read from the IO-APIC
160 static inline void io_apic_sync(unsigned int apic)
162 struct io_apic __iomem *io_apic = io_apic_base(apic);
163 readl(&io_apic->data);
166 #define __DO_ACTION(R, ACTION, FINAL) \
170 struct irq_pin_list *entry = irq_2_pin + irq; \
172 BUG_ON(irq >= NR_IRQS); \
178 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
180 io_apic_modify(entry->apic, reg); \
184 entry = irq_2_pin + entry->next; \
189 struct { u32 w1, w2; };
190 struct IO_APIC_route_entry entry;
193 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
195 union entry_union eu;
197 spin_lock_irqsave(&ioapic_lock, flags);
198 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
199 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
200 spin_unlock_irqrestore(&ioapic_lock, flags);
205 * When we write a new IO APIC routing entry, we need to write the high
206 * word first! If the mask bit in the low word is clear, we will enable
207 * the interrupt, and we need to make sure the entry is fully populated
208 * before that happens.
211 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
213 union entry_union eu;
215 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
216 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
219 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
222 spin_lock_irqsave(&ioapic_lock, flags);
223 __ioapic_write_entry(apic, pin, e);
224 spin_unlock_irqrestore(&ioapic_lock, flags);
228 * When we mask an IO APIC routing entry, we need to write the low
229 * word first, in order to set the mask bit before we change the
232 static void ioapic_mask_entry(int apic, int pin)
235 union entry_union eu = { .entry.mask = 1 };
237 spin_lock_irqsave(&ioapic_lock, flags);
238 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
239 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
240 spin_unlock_irqrestore(&ioapic_lock, flags);
244 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
247 struct irq_pin_list *entry = irq_2_pin + irq;
249 BUG_ON(irq >= NR_IRQS);
256 io_apic_write(apic, 0x11 + pin*2, dest);
257 reg = io_apic_read(apic, 0x10 + pin*2);
260 io_apic_modify(apic, reg);
263 entry = irq_2_pin + entry->next;
267 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
269 struct irq_cfg *cfg = irq_cfg + irq;
274 cpus_and(tmp, mask, cpu_online_map);
278 if (assign_irq_vector(irq, mask))
281 cpus_and(tmp, cfg->domain, mask);
282 dest = cpu_mask_to_apicid(tmp);
285 * Only the high 8 bits are valid.
287 dest = SET_APIC_LOGICAL_ID(dest);
289 spin_lock_irqsave(&ioapic_lock, flags);
290 __target_IO_APIC_irq(irq, dest, cfg->vector);
291 irq_desc[irq].affinity = mask;
292 spin_unlock_irqrestore(&ioapic_lock, flags);
297 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
298 * shared ISA-space IRQs, so we have to support them. We are super
299 * fast in the common case, and fast for shared ISA-space IRQs.
301 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
303 static int first_free_entry = NR_IRQS;
304 struct irq_pin_list *entry = irq_2_pin + irq;
306 BUG_ON(irq >= NR_IRQS);
308 entry = irq_2_pin + entry->next;
310 if (entry->pin != -1) {
311 entry->next = first_free_entry;
312 entry = irq_2_pin + entry->next;
313 if (++first_free_entry >= PIN_MAP_SIZE)
314 panic("io_apic.c: ran out of irq_2_pin entries!");
321 #define DO_ACTION(name,R,ACTION, FINAL) \
323 static void name##_IO_APIC_irq (unsigned int irq) \
324 __DO_ACTION(R, ACTION, FINAL)
326 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
328 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
331 static void mask_IO_APIC_irq (unsigned int irq)
335 spin_lock_irqsave(&ioapic_lock, flags);
336 __mask_IO_APIC_irq(irq);
337 spin_unlock_irqrestore(&ioapic_lock, flags);
340 static void unmask_IO_APIC_irq (unsigned int irq)
344 spin_lock_irqsave(&ioapic_lock, flags);
345 __unmask_IO_APIC_irq(irq);
346 spin_unlock_irqrestore(&ioapic_lock, flags);
349 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
351 struct IO_APIC_route_entry entry;
353 /* Check delivery_mode to be sure we're not clearing an SMI pin */
354 entry = ioapic_read_entry(apic, pin);
355 if (entry.delivery_mode == dest_SMI)
358 * Disable it in the IO-APIC irq-routing table:
360 ioapic_mask_entry(apic, pin);
363 static void clear_IO_APIC (void)
367 for (apic = 0; apic < nr_ioapics; apic++)
368 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
369 clear_IO_APIC_pin(apic, pin);
372 int skip_ioapic_setup;
375 /* dummy parsing: see setup.c */
377 static int __init disable_ioapic_setup(char *str)
379 skip_ioapic_setup = 1;
382 early_param("noapic", disable_ioapic_setup);
384 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
385 static int __init disable_timer_pin_setup(char *arg)
387 disable_timer_pin_1 = 1;
390 __setup("disable_timer_pin_1", disable_timer_pin_setup);
392 static int __init setup_disable_8254_timer(char *s)
394 timer_over_8254 = -1;
397 static int __init setup_enable_8254_timer(char *s)
403 __setup("disable_8254_timer", setup_disable_8254_timer);
404 __setup("enable_8254_timer", setup_enable_8254_timer);
408 * Find the IRQ entry number of a certain pin.
410 static int find_irq_entry(int apic, int pin, int type)
414 for (i = 0; i < mp_irq_entries; i++)
415 if (mp_irqs[i].mpc_irqtype == type &&
416 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
417 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
418 mp_irqs[i].mpc_dstirq == pin)
425 * Find the pin to which IRQ[irq] (ISA) is connected
427 static int __init find_isa_irq_pin(int irq, int type)
431 for (i = 0; i < mp_irq_entries; i++) {
432 int lbus = mp_irqs[i].mpc_srcbus;
434 if (test_bit(lbus, mp_bus_not_pci) &&
435 (mp_irqs[i].mpc_irqtype == type) &&
436 (mp_irqs[i].mpc_srcbusirq == irq))
438 return mp_irqs[i].mpc_dstirq;
443 static int __init find_isa_irq_apic(int irq, int type)
447 for (i = 0; i < mp_irq_entries; i++) {
448 int lbus = mp_irqs[i].mpc_srcbus;
450 if (test_bit(lbus, mp_bus_not_pci) &&
451 (mp_irqs[i].mpc_irqtype == type) &&
452 (mp_irqs[i].mpc_srcbusirq == irq))
455 if (i < mp_irq_entries) {
457 for(apic = 0; apic < nr_ioapics; apic++) {
458 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
467 * Find a specific PCI IRQ entry.
468 * Not an __init, possibly needed by modules
470 static int pin_2_irq(int idx, int apic, int pin);
472 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
474 int apic, i, best_guess = -1;
476 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
478 if (mp_bus_id_to_pci_bus[bus] == -1) {
479 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
482 for (i = 0; i < mp_irq_entries; i++) {
483 int lbus = mp_irqs[i].mpc_srcbus;
485 for (apic = 0; apic < nr_ioapics; apic++)
486 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
487 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
490 if (!test_bit(lbus, mp_bus_not_pci) &&
491 !mp_irqs[i].mpc_irqtype &&
493 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
494 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
496 if (!(apic || IO_APIC_IRQ(irq)))
499 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
502 * Use the first all-but-pin matching entry as a
503 * best-guess fuzzy result for broken mptables.
509 BUG_ON(best_guess >= NR_IRQS);
513 /* ISA interrupts are always polarity zero edge triggered,
514 * when listed as conforming in the MP table. */
516 #define default_ISA_trigger(idx) (0)
517 #define default_ISA_polarity(idx) (0)
519 /* PCI interrupts are always polarity one level triggered,
520 * when listed as conforming in the MP table. */
522 #define default_PCI_trigger(idx) (1)
523 #define default_PCI_polarity(idx) (1)
525 static int __init MPBIOS_polarity(int idx)
527 int bus = mp_irqs[idx].mpc_srcbus;
531 * Determine IRQ line polarity (high active or low active):
533 switch (mp_irqs[idx].mpc_irqflag & 3)
535 case 0: /* conforms, ie. bus-type dependent polarity */
536 if (test_bit(bus, mp_bus_not_pci))
537 polarity = default_ISA_polarity(idx);
539 polarity = default_PCI_polarity(idx);
541 case 1: /* high active */
546 case 2: /* reserved */
548 printk(KERN_WARNING "broken BIOS!!\n");
552 case 3: /* low active */
557 default: /* invalid */
559 printk(KERN_WARNING "broken BIOS!!\n");
567 static int MPBIOS_trigger(int idx)
569 int bus = mp_irqs[idx].mpc_srcbus;
573 * Determine IRQ trigger mode (edge or level sensitive):
575 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
577 case 0: /* conforms, ie. bus-type dependent */
578 if (test_bit(bus, mp_bus_not_pci))
579 trigger = default_ISA_trigger(idx);
581 trigger = default_PCI_trigger(idx);
588 case 2: /* reserved */
590 printk(KERN_WARNING "broken BIOS!!\n");
599 default: /* invalid */
601 printk(KERN_WARNING "broken BIOS!!\n");
609 static inline int irq_polarity(int idx)
611 return MPBIOS_polarity(idx);
614 static inline int irq_trigger(int idx)
616 return MPBIOS_trigger(idx);
619 static int pin_2_irq(int idx, int apic, int pin)
622 int bus = mp_irqs[idx].mpc_srcbus;
625 * Debugging check, we are in big trouble if this message pops up!
627 if (mp_irqs[idx].mpc_dstirq != pin)
628 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
630 if (test_bit(bus, mp_bus_not_pci)) {
631 irq = mp_irqs[idx].mpc_srcbusirq;
634 * PCI IRQs are mapped in order
638 irq += nr_ioapic_registers[i++];
641 BUG_ON(irq >= NR_IRQS);
645 static int __assign_irq_vector(int irq, cpumask_t mask)
648 * NOTE! The local APIC isn't very good at handling
649 * multiple interrupts at the same interrupt level.
650 * As the interrupt level is determined by taking the
651 * vector number and shifting that right by 4, we
652 * want to spread these out a bit so that they don't
653 * all fall in the same interrupt level.
655 * Also, we've got to be careful not to trash gate
656 * 0x80, because int 0x80 is hm, kind of importantish. ;)
658 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
659 unsigned int old_vector;
663 BUG_ON((unsigned)irq >= NR_IRQS);
666 /* Only try and allocate irqs on cpus that are present */
667 cpus_and(mask, mask, cpu_online_map);
669 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
672 old_vector = cfg->vector;
675 cpus_and(tmp, cfg->domain, mask);
676 if (!cpus_empty(tmp))
680 for_each_cpu_mask(cpu, mask) {
681 cpumask_t domain, new_mask;
685 domain = vector_allocation_domain(cpu);
686 cpus_and(new_mask, domain, cpu_online_map);
688 vector = current_vector;
689 offset = current_offset;
692 if (vector >= FIRST_SYSTEM_VECTOR) {
693 /* If we run out of vectors on large boxen, must share them. */
694 offset = (offset + 1) % 8;
695 vector = FIRST_DEVICE_VECTOR + offset;
697 if (unlikely(current_vector == vector))
699 if (vector == IA32_SYSCALL_VECTOR)
701 for_each_cpu_mask(new_cpu, new_mask)
702 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
705 current_vector = vector;
706 current_offset = offset;
708 cfg->move_in_progress = 1;
709 cfg->old_domain = cfg->domain;
711 for_each_cpu_mask(new_cpu, new_mask)
712 per_cpu(vector_irq, new_cpu)[vector] = irq;
713 cfg->vector = vector;
714 cfg->domain = domain;
720 static int assign_irq_vector(int irq, cpumask_t mask)
725 spin_lock_irqsave(&vector_lock, flags);
726 err = __assign_irq_vector(irq, mask);
727 spin_unlock_irqrestore(&vector_lock, flags);
731 static void __clear_irq_vector(int irq)
737 BUG_ON((unsigned)irq >= NR_IRQS);
739 BUG_ON(!cfg->vector);
741 vector = cfg->vector;
742 cpus_and(mask, cfg->domain, cpu_online_map);
743 for_each_cpu_mask(cpu, mask)
744 per_cpu(vector_irq, cpu)[vector] = -1;
747 cfg->domain = CPU_MASK_NONE;
750 void __setup_vector_irq(int cpu)
752 /* Initialize vector_irq on a new cpu */
753 /* This function must be called with vector_lock held */
756 /* Mark the inuse vectors */
757 for (irq = 0; irq < NR_IRQS; ++irq) {
758 if (!cpu_isset(cpu, irq_cfg[irq].domain))
760 vector = irq_cfg[irq].vector;
761 per_cpu(vector_irq, cpu)[vector] = irq;
763 /* Mark the free vectors */
764 for (vector = 0; vector < NR_VECTORS; ++vector) {
765 irq = per_cpu(vector_irq, cpu)[vector];
768 if (!cpu_isset(cpu, irq_cfg[irq].domain))
769 per_cpu(vector_irq, cpu)[vector] = -1;
774 static struct irq_chip ioapic_chip;
776 static void ioapic_register_intr(int irq, unsigned long trigger)
779 set_irq_chip_and_handler_name(irq, &ioapic_chip,
780 handle_fasteoi_irq, "fasteoi");
782 set_irq_chip_and_handler_name(irq, &ioapic_chip,
783 handle_edge_irq, "edge");
786 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
787 int trigger, int polarity)
789 struct irq_cfg *cfg = irq_cfg + irq;
790 struct IO_APIC_route_entry entry;
793 if (!IO_APIC_IRQ(irq))
797 if (assign_irq_vector(irq, mask))
800 cpus_and(mask, cfg->domain, mask);
802 apic_printk(APIC_VERBOSE,KERN_DEBUG
803 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
804 "IRQ %d Mode:%i Active:%i)\n",
805 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
806 irq, trigger, polarity);
809 * add it to the IO-APIC irq-routing table:
811 memset(&entry,0,sizeof(entry));
813 entry.delivery_mode = INT_DELIVERY_MODE;
814 entry.dest_mode = INT_DEST_MODE;
815 entry.dest = cpu_mask_to_apicid(mask);
816 entry.mask = 0; /* enable IRQ */
817 entry.trigger = trigger;
818 entry.polarity = polarity;
819 entry.vector = cfg->vector;
821 /* Mask level triggered irqs.
822 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
827 ioapic_register_intr(irq, trigger);
829 disable_8259A_irq(irq);
831 ioapic_write_entry(apic, pin, entry);
834 static void __init setup_IO_APIC_irqs(void)
836 int apic, pin, idx, irq, first_notcon = 1;
838 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
840 for (apic = 0; apic < nr_ioapics; apic++) {
841 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
843 idx = find_irq_entry(apic,pin,mp_INT);
846 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
849 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
853 irq = pin_2_irq(idx, apic, pin);
854 add_pin_to_irq(irq, apic, pin);
856 setup_IO_APIC_irq(apic, pin, irq,
857 irq_trigger(idx), irq_polarity(idx));
862 apic_printk(APIC_VERBOSE," not connected.\n");
866 * Set up the 8259A-master output pin as broadcast to all
869 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
871 struct IO_APIC_route_entry entry;
874 memset(&entry,0,sizeof(entry));
876 disable_8259A_irq(0);
879 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
882 * We use logical delivery to get the timer IRQ
885 entry.dest_mode = INT_DEST_MODE;
886 entry.mask = 0; /* unmask IRQ now */
887 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
888 entry.delivery_mode = INT_DELIVERY_MODE;
891 entry.vector = vector;
894 * The timer IRQ doesn't have to know that behind the
895 * scene we have a 8259A-master in AEOI mode ...
897 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
900 * Add it to the IO-APIC irq-routing table:
902 spin_lock_irqsave(&ioapic_lock, flags);
903 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
904 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
905 spin_unlock_irqrestore(&ioapic_lock, flags);
910 void __apicdebuginit print_IO_APIC(void)
913 union IO_APIC_reg_00 reg_00;
914 union IO_APIC_reg_01 reg_01;
915 union IO_APIC_reg_02 reg_02;
918 if (apic_verbosity == APIC_QUIET)
921 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
922 for (i = 0; i < nr_ioapics; i++)
923 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
924 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
927 * We are a bit conservative about what we expect. We have to
928 * know about every hardware change ASAP.
930 printk(KERN_INFO "testing the IO APIC.......................\n");
932 for (apic = 0; apic < nr_ioapics; apic++) {
934 spin_lock_irqsave(&ioapic_lock, flags);
935 reg_00.raw = io_apic_read(apic, 0);
936 reg_01.raw = io_apic_read(apic, 1);
937 if (reg_01.bits.version >= 0x10)
938 reg_02.raw = io_apic_read(apic, 2);
939 spin_unlock_irqrestore(&ioapic_lock, flags);
942 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
943 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
944 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
946 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
947 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
949 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
950 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
952 if (reg_01.bits.version >= 0x10) {
953 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
954 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
957 printk(KERN_DEBUG ".... IRQ redirection table:\n");
959 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
960 " Stat Dmod Deli Vect: \n");
962 for (i = 0; i <= reg_01.bits.entries; i++) {
963 struct IO_APIC_route_entry entry;
965 entry = ioapic_read_entry(apic, i);
967 printk(KERN_DEBUG " %02x %03X ",
972 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
977 entry.delivery_status,
984 printk(KERN_DEBUG "IRQ to pin mappings:\n");
985 for (i = 0; i < NR_IRQS; i++) {
986 struct irq_pin_list *entry = irq_2_pin + i;
989 printk(KERN_DEBUG "IRQ%d ", i);
991 printk("-> %d:%d", entry->apic, entry->pin);
994 entry = irq_2_pin + entry->next;
999 printk(KERN_INFO ".................................... done.\n");
1006 static __apicdebuginit void print_APIC_bitfield (int base)
1011 if (apic_verbosity == APIC_QUIET)
1014 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1015 for (i = 0; i < 8; i++) {
1016 v = apic_read(base + i*0x10);
1017 for (j = 0; j < 32; j++) {
1027 void __apicdebuginit print_local_APIC(void * dummy)
1029 unsigned int v, ver, maxlvt;
1031 if (apic_verbosity == APIC_QUIET)
1034 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1035 smp_processor_id(), hard_smp_processor_id());
1036 v = apic_read(APIC_ID);
1037 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1038 v = apic_read(APIC_LVR);
1039 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1040 ver = GET_APIC_VERSION(v);
1041 maxlvt = get_maxlvt();
1043 v = apic_read(APIC_TASKPRI);
1044 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1046 v = apic_read(APIC_ARBPRI);
1047 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1048 v & APIC_ARBPRI_MASK);
1049 v = apic_read(APIC_PROCPRI);
1050 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1052 v = apic_read(APIC_EOI);
1053 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1054 v = apic_read(APIC_RRR);
1055 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1056 v = apic_read(APIC_LDR);
1057 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1058 v = apic_read(APIC_DFR);
1059 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1060 v = apic_read(APIC_SPIV);
1061 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1063 printk(KERN_DEBUG "... APIC ISR field:\n");
1064 print_APIC_bitfield(APIC_ISR);
1065 printk(KERN_DEBUG "... APIC TMR field:\n");
1066 print_APIC_bitfield(APIC_TMR);
1067 printk(KERN_DEBUG "... APIC IRR field:\n");
1068 print_APIC_bitfield(APIC_IRR);
1070 v = apic_read(APIC_ESR);
1071 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1073 v = apic_read(APIC_ICR);
1074 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1075 v = apic_read(APIC_ICR2);
1076 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1078 v = apic_read(APIC_LVTT);
1079 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1081 if (maxlvt > 3) { /* PC is LVT#4. */
1082 v = apic_read(APIC_LVTPC);
1083 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1085 v = apic_read(APIC_LVT0);
1086 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1087 v = apic_read(APIC_LVT1);
1088 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1090 if (maxlvt > 2) { /* ERR is LVT#3. */
1091 v = apic_read(APIC_LVTERR);
1092 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1095 v = apic_read(APIC_TMICT);
1096 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1097 v = apic_read(APIC_TMCCT);
1098 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1099 v = apic_read(APIC_TDCR);
1100 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1104 void print_all_local_APICs (void)
1106 on_each_cpu(print_local_APIC, NULL, 1, 1);
1109 void __apicdebuginit print_PIC(void)
1112 unsigned long flags;
1114 if (apic_verbosity == APIC_QUIET)
1117 printk(KERN_DEBUG "\nprinting PIC contents\n");
1119 spin_lock_irqsave(&i8259A_lock, flags);
1121 v = inb(0xa1) << 8 | inb(0x21);
1122 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1124 v = inb(0xa0) << 8 | inb(0x20);
1125 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1129 v = inb(0xa0) << 8 | inb(0x20);
1133 spin_unlock_irqrestore(&i8259A_lock, flags);
1135 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1137 v = inb(0x4d1) << 8 | inb(0x4d0);
1138 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1143 static void __init enable_IO_APIC(void)
1145 union IO_APIC_reg_01 reg_01;
1146 int i8259_apic, i8259_pin;
1148 unsigned long flags;
1150 for (i = 0; i < PIN_MAP_SIZE; i++) {
1151 irq_2_pin[i].pin = -1;
1152 irq_2_pin[i].next = 0;
1156 * The number of IO-APIC IRQ registers (== #pins):
1158 for (apic = 0; apic < nr_ioapics; apic++) {
1159 spin_lock_irqsave(&ioapic_lock, flags);
1160 reg_01.raw = io_apic_read(apic, 1);
1161 spin_unlock_irqrestore(&ioapic_lock, flags);
1162 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1164 for(apic = 0; apic < nr_ioapics; apic++) {
1166 /* See if any of the pins is in ExtINT mode */
1167 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1168 struct IO_APIC_route_entry entry;
1169 entry = ioapic_read_entry(apic, pin);
1171 /* If the interrupt line is enabled and in ExtInt mode
1172 * I have found the pin where the i8259 is connected.
1174 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1175 ioapic_i8259.apic = apic;
1176 ioapic_i8259.pin = pin;
1182 /* Look to see what if the MP table has reported the ExtINT */
1183 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1184 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1185 /* Trust the MP table if nothing is setup in the hardware */
1186 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1187 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1188 ioapic_i8259.pin = i8259_pin;
1189 ioapic_i8259.apic = i8259_apic;
1191 /* Complain if the MP table and the hardware disagree */
1192 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1193 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1195 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1199 * Do not trust the IO-APIC being empty at bootup
1205 * Not an __init, needed by the reboot code
1207 void disable_IO_APIC(void)
1210 * Clear the IO-APIC before rebooting:
1215 * If the i8259 is routed through an IOAPIC
1216 * Put that IOAPIC in virtual wire mode
1217 * so legacy interrupts can be delivered.
1219 if (ioapic_i8259.pin != -1) {
1220 struct IO_APIC_route_entry entry;
1222 memset(&entry, 0, sizeof(entry));
1223 entry.mask = 0; /* Enabled */
1224 entry.trigger = 0; /* Edge */
1226 entry.polarity = 0; /* High */
1227 entry.delivery_status = 0;
1228 entry.dest_mode = 0; /* Physical */
1229 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1231 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
1234 * Add it to the IO-APIC irq-routing table:
1236 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1239 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1243 * There is a nasty bug in some older SMP boards, their mptable lies
1244 * about the timer IRQ. We do the following to work around the situation:
1246 * - timer IRQ defaults to IO-APIC IRQ
1247 * - if this function detects that timer IRQs are defunct, then we fall
1248 * back to ISA timer IRQs
1250 static int __init timer_irq_works(void)
1252 unsigned long t1 = jiffies;
1255 /* Let ten ticks pass... */
1256 mdelay((10 * 1000) / HZ);
1259 * Expect a few ticks at least, to be sure some possible
1260 * glue logic does not lock up after one or two first
1261 * ticks in a non-ExtINT mode. Also the local APIC
1262 * might have cached one ExtINT interrupt. Finally, at
1263 * least one tick may be lost due to delays.
1267 if (jiffies - t1 > 4)
1273 * In the SMP+IOAPIC case it might happen that there are an unspecified
1274 * number of pending IRQ events unhandled. These cases are very rare,
1275 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1276 * better to do it this way as thus we do not have to be aware of
1277 * 'pending' interrupts in the IRQ path, except at this point.
1280 * Edge triggered needs to resend any interrupt
1281 * that was delayed but this is now handled in the device
1286 * Starting up a edge-triggered IO-APIC interrupt is
1287 * nasty - we need to make sure that we get the edge.
1288 * If it is already asserted for some reason, we need
1289 * return 1 to indicate that is was pending.
1291 * This is not complete - we should be able to fake
1292 * an edge even if it isn't on the 8259A...
1295 static unsigned int startup_ioapic_irq(unsigned int irq)
1297 int was_pending = 0;
1298 unsigned long flags;
1300 spin_lock_irqsave(&ioapic_lock, flags);
1302 disable_8259A_irq(irq);
1303 if (i8259A_irq_pending(irq))
1306 __unmask_IO_APIC_irq(irq);
1307 spin_unlock_irqrestore(&ioapic_lock, flags);
1312 static int ioapic_retrigger_irq(unsigned int irq)
1314 struct irq_cfg *cfg = &irq_cfg[irq];
1316 unsigned long flags;
1318 spin_lock_irqsave(&vector_lock, flags);
1320 cpu_set(first_cpu(cfg->domain), mask);
1322 send_IPI_mask(mask, cfg->vector);
1323 spin_unlock_irqrestore(&vector_lock, flags);
1329 * Level and edge triggered IO-APIC interrupts need different handling,
1330 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1331 * handled with the level-triggered descriptor, but that one has slightly
1332 * more overhead. Level-triggered interrupts cannot be handled with the
1333 * edge-triggered handler, without risking IRQ storms and other ugly
1338 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1340 unsigned vector, me;
1345 me = smp_processor_id();
1346 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1348 struct irq_desc *desc;
1349 struct irq_cfg *cfg;
1350 irq = __get_cpu_var(vector_irq)[vector];
1354 desc = irq_desc + irq;
1355 cfg = irq_cfg + irq;
1356 spin_lock(&desc->lock);
1357 if (!cfg->move_cleanup_count)
1360 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1363 __get_cpu_var(vector_irq)[vector] = -1;
1364 cfg->move_cleanup_count--;
1366 spin_unlock(&desc->lock);
1372 static void irq_complete_move(unsigned int irq)
1374 struct irq_cfg *cfg = irq_cfg + irq;
1375 unsigned vector, me;
1377 if (likely(!cfg->move_in_progress))
1380 vector = ~get_irq_regs()->orig_rax;
1381 me = smp_processor_id();
1382 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1383 cpumask_t cleanup_mask;
1385 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1386 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1387 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1388 cfg->move_in_progress = 0;
1392 static inline void irq_complete_move(unsigned int irq) {}
1395 static void ack_apic_edge(unsigned int irq)
1397 irq_complete_move(irq);
1398 move_native_irq(irq);
1402 static void ack_apic_level(unsigned int irq)
1404 int do_unmask_irq = 0;
1406 irq_complete_move(irq);
1407 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1408 /* If we are moving the irq we need to mask it */
1409 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1411 mask_IO_APIC_irq(irq);
1416 * We must acknowledge the irq before we move it or the acknowledge will
1417 * not propogate properly.
1421 /* Now we can move and renable the irq */
1422 move_masked_irq(irq);
1423 if (unlikely(do_unmask_irq))
1424 unmask_IO_APIC_irq(irq);
1427 static struct irq_chip ioapic_chip __read_mostly = {
1429 .startup = startup_ioapic_irq,
1430 .mask = mask_IO_APIC_irq,
1431 .unmask = unmask_IO_APIC_irq,
1432 .ack = ack_apic_edge,
1433 .eoi = ack_apic_level,
1435 .set_affinity = set_ioapic_affinity_irq,
1437 .retrigger = ioapic_retrigger_irq,
1440 static inline void init_IO_APIC_traps(void)
1445 * NOTE! The local APIC isn't very good at handling
1446 * multiple interrupts at the same interrupt level.
1447 * As the interrupt level is determined by taking the
1448 * vector number and shifting that right by 4, we
1449 * want to spread these out a bit so that they don't
1450 * all fall in the same interrupt level.
1452 * Also, we've got to be careful not to trash gate
1453 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1455 for (irq = 0; irq < NR_IRQS ; irq++) {
1457 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1459 * Hmm.. We don't have an entry for this,
1460 * so default to an old-fashioned 8259
1461 * interrupt if we can..
1464 make_8259A_irq(irq);
1466 /* Strange. Oh, well.. */
1467 irq_desc[irq].chip = &no_irq_chip;
1472 static void enable_lapic_irq (unsigned int irq)
1476 v = apic_read(APIC_LVT0);
1477 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1480 static void disable_lapic_irq (unsigned int irq)
1484 v = apic_read(APIC_LVT0);
1485 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1488 static void ack_lapic_irq (unsigned int irq)
1493 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1495 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1496 .typename = "local-APIC-edge",
1497 .startup = NULL, /* startup_irq() not used for IRQ0 */
1498 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1499 .enable = enable_lapic_irq,
1500 .disable = disable_lapic_irq,
1501 .ack = ack_lapic_irq,
1502 .end = end_lapic_irq,
1505 static void setup_nmi (void)
1508 * Dirty trick to enable the NMI watchdog ...
1509 * We put the 8259A master into AEOI mode and
1510 * unmask on all local APICs LVT0 as NMI.
1512 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1513 * is from Maciej W. Rozycki - so we do not have to EOI from
1514 * the NMI handler or the timer interrupt.
1516 printk(KERN_INFO "activating NMI Watchdog ...");
1518 enable_NMI_through_LVT0(NULL);
1524 * This looks a bit hackish but it's about the only one way of sending
1525 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1526 * not support the ExtINT mode, unfortunately. We need to send these
1527 * cycles as some i82489DX-based boards have glue logic that keeps the
1528 * 8259A interrupt line asserted until INTA. --macro
1530 static inline void unlock_ExtINT_logic(void)
1533 struct IO_APIC_route_entry entry0, entry1;
1534 unsigned char save_control, save_freq_select;
1535 unsigned long flags;
1537 pin = find_isa_irq_pin(8, mp_INT);
1538 apic = find_isa_irq_apic(8, mp_INT);
1542 spin_lock_irqsave(&ioapic_lock, flags);
1543 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1544 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1545 spin_unlock_irqrestore(&ioapic_lock, flags);
1546 clear_IO_APIC_pin(apic, pin);
1548 memset(&entry1, 0, sizeof(entry1));
1550 entry1.dest_mode = 0; /* physical delivery */
1551 entry1.mask = 0; /* unmask IRQ now */
1552 entry1.dest = hard_smp_processor_id();
1553 entry1.delivery_mode = dest_ExtINT;
1554 entry1.polarity = entry0.polarity;
1558 spin_lock_irqsave(&ioapic_lock, flags);
1559 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1560 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1561 spin_unlock_irqrestore(&ioapic_lock, flags);
1563 save_control = CMOS_READ(RTC_CONTROL);
1564 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1565 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1567 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1572 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1576 CMOS_WRITE(save_control, RTC_CONTROL);
1577 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1578 clear_IO_APIC_pin(apic, pin);
1580 spin_lock_irqsave(&ioapic_lock, flags);
1581 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1582 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1583 spin_unlock_irqrestore(&ioapic_lock, flags);
1587 * This code may look a bit paranoid, but it's supposed to cooperate with
1588 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1589 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1590 * fanatically on his truly buggy board.
1592 * FIXME: really need to revamp this for modern platforms only.
1594 static inline void check_timer(void)
1596 struct irq_cfg *cfg = irq_cfg + 0;
1597 int apic1, pin1, apic2, pin2;
1600 * get/set the timer IRQ vector:
1602 disable_8259A_irq(0);
1603 assign_irq_vector(0, TARGET_CPUS);
1606 * Subtle, code in do_timer_interrupt() expects an AEOI
1607 * mode for the 8259A whenever interrupts are routed
1608 * through I/O APICs. Also IRQ0 has to be enabled in
1609 * the 8259A which implies the virtual wire has to be
1610 * disabled in the local APIC.
1612 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1614 if (timer_over_8254 > 0)
1615 enable_8259A_irq(0);
1617 pin1 = find_isa_irq_pin(0, mp_INT);
1618 apic1 = find_isa_irq_apic(0, mp_INT);
1619 pin2 = ioapic_i8259.pin;
1620 apic2 = ioapic_i8259.apic;
1622 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1623 cfg->vector, apic1, pin1, apic2, pin2);
1627 * Ok, does IRQ0 through the IOAPIC work?
1629 unmask_IO_APIC_irq(0);
1630 if (!no_timer_check && timer_irq_works()) {
1631 nmi_watchdog_default();
1632 if (nmi_watchdog == NMI_IO_APIC) {
1633 disable_8259A_irq(0);
1635 enable_8259A_irq(0);
1637 if (disable_timer_pin_1 > 0)
1638 clear_IO_APIC_pin(0, pin1);
1641 clear_IO_APIC_pin(apic1, pin1);
1642 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1643 "connected to IO-APIC\n");
1646 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1647 "through the 8259A ... ");
1649 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1652 * legacy devices should be connected to IO APIC #0
1654 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1655 if (timer_irq_works()) {
1656 apic_printk(APIC_VERBOSE," works.\n");
1657 nmi_watchdog_default();
1658 if (nmi_watchdog == NMI_IO_APIC) {
1664 * Cleanup, just in case ...
1666 clear_IO_APIC_pin(apic2, pin2);
1668 apic_printk(APIC_VERBOSE," failed.\n");
1670 if (nmi_watchdog == NMI_IO_APIC) {
1671 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1675 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1677 disable_8259A_irq(0);
1678 irq_desc[0].chip = &lapic_irq_type;
1679 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1680 enable_8259A_irq(0);
1682 if (timer_irq_works()) {
1683 apic_printk(APIC_VERBOSE," works.\n");
1686 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1687 apic_printk(APIC_VERBOSE," failed.\n");
1689 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1693 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1695 unlock_ExtINT_logic();
1697 if (timer_irq_works()) {
1698 apic_printk(APIC_VERBOSE," works.\n");
1701 apic_printk(APIC_VERBOSE," failed :(.\n");
1702 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1705 static int __init notimercheck(char *s)
1710 __setup("no_timer_check", notimercheck);
1714 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1715 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1716 * Linux doesn't really care, as it's not actually used
1717 * for any interrupt handling anyway.
1719 #define PIC_IRQS (1<<2)
1721 void __init setup_IO_APIC(void)
1726 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1728 io_apic_irqs = ~PIC_IRQS;
1730 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1733 setup_IO_APIC_irqs();
1734 init_IO_APIC_traps();
1740 struct sysfs_ioapic_data {
1741 struct sys_device dev;
1742 struct IO_APIC_route_entry entry[0];
1744 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1746 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1748 struct IO_APIC_route_entry *entry;
1749 struct sysfs_ioapic_data *data;
1752 data = container_of(dev, struct sysfs_ioapic_data, dev);
1753 entry = data->entry;
1754 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1755 *entry = ioapic_read_entry(dev->id, i);
1760 static int ioapic_resume(struct sys_device *dev)
1762 struct IO_APIC_route_entry *entry;
1763 struct sysfs_ioapic_data *data;
1764 unsigned long flags;
1765 union IO_APIC_reg_00 reg_00;
1768 data = container_of(dev, struct sysfs_ioapic_data, dev);
1769 entry = data->entry;
1771 spin_lock_irqsave(&ioapic_lock, flags);
1772 reg_00.raw = io_apic_read(dev->id, 0);
1773 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1774 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1775 io_apic_write(dev->id, 0, reg_00.raw);
1777 spin_unlock_irqrestore(&ioapic_lock, flags);
1778 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1779 ioapic_write_entry(dev->id, i, entry[i]);
1784 static struct sysdev_class ioapic_sysdev_class = {
1785 set_kset_name("ioapic"),
1786 .suspend = ioapic_suspend,
1787 .resume = ioapic_resume,
1790 static int __init ioapic_init_sysfs(void)
1792 struct sys_device * dev;
1793 int i, size, error = 0;
1795 error = sysdev_class_register(&ioapic_sysdev_class);
1799 for (i = 0; i < nr_ioapics; i++ ) {
1800 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1801 * sizeof(struct IO_APIC_route_entry);
1802 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1803 if (!mp_ioapic_data[i]) {
1804 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1807 memset(mp_ioapic_data[i], 0, size);
1808 dev = &mp_ioapic_data[i]->dev;
1810 dev->cls = &ioapic_sysdev_class;
1811 error = sysdev_register(dev);
1813 kfree(mp_ioapic_data[i]);
1814 mp_ioapic_data[i] = NULL;
1815 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1823 device_initcall(ioapic_init_sysfs);
1826 * Dynamic irq allocate and deallocation
1828 int create_irq(void)
1830 /* Allocate an unused irq */
1833 unsigned long flags;
1836 spin_lock_irqsave(&vector_lock, flags);
1837 for (new = (NR_IRQS - 1); new >= 0; new--) {
1838 if (platform_legacy_irq(new))
1840 if (irq_cfg[new].vector != 0)
1842 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1846 spin_unlock_irqrestore(&vector_lock, flags);
1849 dynamic_irq_init(irq);
1854 void destroy_irq(unsigned int irq)
1856 unsigned long flags;
1858 dynamic_irq_cleanup(irq);
1860 spin_lock_irqsave(&vector_lock, flags);
1861 __clear_irq_vector(irq);
1862 spin_unlock_irqrestore(&vector_lock, flags);
1866 * MSI mesage composition
1868 #ifdef CONFIG_PCI_MSI
1869 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1871 struct irq_cfg *cfg = irq_cfg + irq;
1877 err = assign_irq_vector(irq, tmp);
1879 cpus_and(tmp, cfg->domain, tmp);
1880 dest = cpu_mask_to_apicid(tmp);
1882 msg->address_hi = MSI_ADDR_BASE_HI;
1885 ((INT_DEST_MODE == 0) ?
1886 MSI_ADDR_DEST_MODE_PHYSICAL:
1887 MSI_ADDR_DEST_MODE_LOGICAL) |
1888 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1889 MSI_ADDR_REDIRECTION_CPU:
1890 MSI_ADDR_REDIRECTION_LOWPRI) |
1891 MSI_ADDR_DEST_ID(dest);
1894 MSI_DATA_TRIGGER_EDGE |
1895 MSI_DATA_LEVEL_ASSERT |
1896 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1897 MSI_DATA_DELIVERY_FIXED:
1898 MSI_DATA_DELIVERY_LOWPRI) |
1899 MSI_DATA_VECTOR(cfg->vector);
1905 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1907 struct irq_cfg *cfg = irq_cfg + irq;
1912 cpus_and(tmp, mask, cpu_online_map);
1913 if (cpus_empty(tmp))
1916 if (assign_irq_vector(irq, mask))
1919 cpus_and(tmp, cfg->domain, mask);
1920 dest = cpu_mask_to_apicid(tmp);
1922 read_msi_msg(irq, &msg);
1924 msg.data &= ~MSI_DATA_VECTOR_MASK;
1925 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1926 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1927 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1929 write_msi_msg(irq, &msg);
1930 irq_desc[irq].affinity = mask;
1932 #endif /* CONFIG_SMP */
1935 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1936 * which implement the MSI or MSI-X Capability Structure.
1938 static struct irq_chip msi_chip = {
1940 .unmask = unmask_msi_irq,
1941 .mask = mask_msi_irq,
1942 .ack = ack_apic_edge,
1944 .set_affinity = set_msi_irq_affinity,
1946 .retrigger = ioapic_retrigger_irq,
1949 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
1957 set_irq_msi(irq, desc);
1958 ret = msi_compose_msg(dev, irq, &msg);
1964 write_msi_msg(irq, &msg);
1966 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1971 void arch_teardown_msi_irq(unsigned int irq)
1976 #endif /* CONFIG_PCI_MSI */
1979 * Hypertransport interrupt support
1981 #ifdef CONFIG_HT_IRQ
1985 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1987 struct ht_irq_msg msg;
1988 fetch_ht_irq_msg(irq, &msg);
1990 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1991 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1993 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1994 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
1996 write_ht_irq_msg(irq, &msg);
1999 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2001 struct irq_cfg *cfg = irq_cfg + irq;
2005 cpus_and(tmp, mask, cpu_online_map);
2006 if (cpus_empty(tmp))
2009 if (assign_irq_vector(irq, mask))
2012 cpus_and(tmp, cfg->domain, mask);
2013 dest = cpu_mask_to_apicid(tmp);
2015 target_ht_irq(irq, dest, cfg->vector);
2016 irq_desc[irq].affinity = mask;
2020 static struct irq_chip ht_irq_chip = {
2022 .mask = mask_ht_irq,
2023 .unmask = unmask_ht_irq,
2024 .ack = ack_apic_edge,
2026 .set_affinity = set_ht_irq_affinity,
2028 .retrigger = ioapic_retrigger_irq,
2031 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2033 struct irq_cfg *cfg = irq_cfg + irq;
2038 err = assign_irq_vector(irq, tmp);
2040 struct ht_irq_msg msg;
2043 cpus_and(tmp, cfg->domain, tmp);
2044 dest = cpu_mask_to_apicid(tmp);
2046 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2050 HT_IRQ_LOW_DEST_ID(dest) |
2051 HT_IRQ_LOW_VECTOR(cfg->vector) |
2052 ((INT_DEST_MODE == 0) ?
2053 HT_IRQ_LOW_DM_PHYSICAL :
2054 HT_IRQ_LOW_DM_LOGICAL) |
2055 HT_IRQ_LOW_RQEOI_EDGE |
2056 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2057 HT_IRQ_LOW_MT_FIXED :
2058 HT_IRQ_LOW_MT_ARBITRATED) |
2059 HT_IRQ_LOW_IRQ_MASKED;
2061 write_ht_irq_msg(irq, &msg);
2063 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2064 handle_edge_irq, "edge");
2068 #endif /* CONFIG_HT_IRQ */
2070 /* --------------------------------------------------------------------------
2071 ACPI-based IOAPIC Configuration
2072 -------------------------------------------------------------------------- */
2076 #define IO_APIC_MAX_ID 0xFE
2078 int __init io_apic_get_redir_entries (int ioapic)
2080 union IO_APIC_reg_01 reg_01;
2081 unsigned long flags;
2083 spin_lock_irqsave(&ioapic_lock, flags);
2084 reg_01.raw = io_apic_read(ioapic, 1);
2085 spin_unlock_irqrestore(&ioapic_lock, flags);
2087 return reg_01.bits.entries;
2091 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2093 if (!IO_APIC_IRQ(irq)) {
2094 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2100 * IRQs < 16 are already in the irq_2_pin[] map
2103 add_pin_to_irq(irq, ioapic, pin);
2105 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2110 #endif /* CONFIG_ACPI */
2114 * This function currently is only a helper for the i386 smp boot process where
2115 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2116 * so mask in all cases should simply be TARGET_CPUS
2119 void __init setup_ioapic_dest(void)
2121 int pin, ioapic, irq, irq_entry;
2123 if (skip_ioapic_setup == 1)
2126 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2127 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2128 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2129 if (irq_entry == -1)
2131 irq = pin_2_irq(irq_entry, ioapic, pin);
2133 /* setup_IO_APIC_irqs could fail to get vector for some device
2134 * when you have too many devices, because at that time only boot
2137 if (!irq_cfg[irq].vector)
2138 setup_IO_APIC_irq(ioapic, pin, irq,
2139 irq_trigger(irq_entry),
2140 irq_polarity(irq_entry));
2142 set_ioapic_affinity_irq(irq, TARGET_CPUS);