2 * arch/xtensa/kernel/setup.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 * Chris Zankel <chris@zankel.net>
12 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
14 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
17 #include <linux/errno.h>
18 #include <linux/init.h>
20 #include <linux/proc_fs.h>
21 #include <linux/screen_info.h>
22 #include <linux/bootmem.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/clk-provider.h>
26 #include <linux/cpu.h>
27 #include <linux/of_fdt.h>
28 #include <linux/of_platform.h>
30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31 # include <linux/console.h>
35 # include <linux/timex.h>
39 # include <linux/seq_file.h>
42 #include <asm/bootparam.h>
43 #include <asm/mmu_context.h>
44 #include <asm/pgtable.h>
45 #include <asm/processor.h>
46 #include <asm/timex.h>
47 #include <asm/platform.h>
49 #include <asm/setup.h>
50 #include <asm/param.h>
51 #include <asm/traps.h>
53 #include <asm/sysmem.h>
55 #include <platform/hardware.h>
57 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
58 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
61 #ifdef CONFIG_BLK_DEV_FD
62 extern struct fd_ops no_fd_ops;
63 struct fd_ops *fd_ops;
66 extern struct rtc_ops no_rtc_ops;
67 struct rtc_ops *rtc_ops;
69 #ifdef CONFIG_BLK_DEV_INITRD
70 extern unsigned long initrd_start;
71 extern unsigned long initrd_end;
72 int initrd_is_mapped = 0;
73 extern int initrd_below_start_ok;
77 extern u32 __dtb_start[];
78 void *dtb_start = __dtb_start;
81 unsigned char aux_device_present;
82 extern unsigned long loops_per_jiffy;
84 /* Command line specified as configuration option. */
86 static char __initdata command_line[COMMAND_LINE_SIZE];
88 #ifdef CONFIG_CMDLINE_BOOL
89 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
93 * Boot parameter parsing.
95 * The Xtensa port uses a list of variable-sized tags to pass data to
96 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
97 * to be recognised. The list is terminated with a zero-sized
101 typedef struct tagtable {
103 int (*parse)(const bp_tag_t*);
106 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
107 __attribute__((used, section(".taglist"))) = { tag, fn }
109 /* parse current tag */
111 static int __init parse_tag_mem(const bp_tag_t *tag)
113 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
115 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
118 return add_sysmem_bank(mi->start, mi->end);
121 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
123 #ifdef CONFIG_BLK_DEV_INITRD
125 static int __init parse_tag_initrd(const bp_tag_t* tag)
127 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
129 initrd_start = (unsigned long)__va(mi->start);
130 initrd_end = (unsigned long)__va(mi->end);
135 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
139 static int __init parse_tag_fdt(const bp_tag_t *tag)
141 dtb_start = __va(tag->data[0]);
145 __tagtable(BP_TAG_FDT, parse_tag_fdt);
147 #endif /* CONFIG_OF */
149 #endif /* CONFIG_BLK_DEV_INITRD */
151 static int __init parse_tag_cmdline(const bp_tag_t* tag)
153 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
157 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
159 static int __init parse_bootparam(const bp_tag_t* tag)
161 extern tagtable_t __tagtable_begin, __tagtable_end;
164 /* Boot parameters must start with a BP_TAG_FIRST tag. */
166 if (tag->id != BP_TAG_FIRST) {
167 printk(KERN_WARNING "Invalid boot parameters!\n");
171 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
173 /* Parse all tags. */
175 while (tag != NULL && tag->id != BP_TAG_LAST) {
176 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
177 if (tag->id == t->tag) {
182 if (t == &__tagtable_end)
183 printk(KERN_WARNING "Ignoring tag "
184 "0x%08x\n", tag->id);
185 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
192 bool __initdata dt_memory_scan = false;
194 #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
195 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
196 EXPORT_SYMBOL(xtensa_kio_paddr);
198 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
199 int depth, void *data)
201 const __be32 *ranges;
207 if (!of_flat_dt_is_compatible(node, "simple-bus"))
210 ranges = of_get_flat_dt_prop(node, "ranges", &len);
216 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
217 /* round down to nearest 256MB boundary */
218 xtensa_kio_paddr &= 0xf0000000;
223 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
224 int depth, void *data)
230 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
236 add_sysmem_bank(base, base + size);
239 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
241 return __alloc_bootmem(size, align, 0);
244 void __init early_init_devtree(void *params)
246 if (sysmem.nr_banks == 0)
247 dt_memory_scan = true;
249 early_init_dt_scan(params);
250 of_scan_flat_dt(xtensa_dt_io_area, NULL);
252 if (!command_line[0])
253 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
256 static int __init xtensa_device_probe(void)
259 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
263 device_initcall(xtensa_device_probe);
265 #endif /* CONFIG_OF */
268 * Initialize architecture. (Early stage)
271 void __init init_arch(bp_tag_t *bp_start)
273 /* Parse boot parameters */
276 parse_bootparam(bp_start);
279 early_init_devtree(dtb_start);
282 if (sysmem.nr_banks == 0) {
283 add_sysmem_bank(PLATFORM_DEFAULT_MEM_START,
284 PLATFORM_DEFAULT_MEM_START +
285 PLATFORM_DEFAULT_MEM_SIZE);
288 #ifdef CONFIG_CMDLINE_BOOL
289 if (!command_line[0])
290 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
293 /* Early hook for platforms */
295 platform_init(bp_start);
297 /* Initialize MMU. */
303 * Initialize system. Setup memory and reserve regions.
308 extern char _WindowVectors_text_start;
309 extern char _WindowVectors_text_end;
310 extern char _DebugInterruptVector_literal_start;
311 extern char _DebugInterruptVector_text_end;
312 extern char _KernelExceptionVector_literal_start;
313 extern char _KernelExceptionVector_text_end;
314 extern char _UserExceptionVector_literal_start;
315 extern char _UserExceptionVector_text_end;
316 extern char _DoubleExceptionVector_literal_start;
317 extern char _DoubleExceptionVector_text_end;
318 #if XCHAL_EXCM_LEVEL >= 2
319 extern char _Level2InterruptVector_text_start;
320 extern char _Level2InterruptVector_text_end;
322 #if XCHAL_EXCM_LEVEL >= 3
323 extern char _Level3InterruptVector_text_start;
324 extern char _Level3InterruptVector_text_end;
326 #if XCHAL_EXCM_LEVEL >= 4
327 extern char _Level4InterruptVector_text_start;
328 extern char _Level4InterruptVector_text_end;
330 #if XCHAL_EXCM_LEVEL >= 5
331 extern char _Level5InterruptVector_text_start;
332 extern char _Level5InterruptVector_text_end;
334 #if XCHAL_EXCM_LEVEL >= 6
335 extern char _Level6InterruptVector_text_start;
336 extern char _Level6InterruptVector_text_end;
341 #ifdef CONFIG_S32C1I_SELFTEST
342 #if XCHAL_HAVE_S32C1I
344 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
347 * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
349 * If *v == cmp, set *v = set. Return previous *v.
351 static inline int probed_compare_swap(int *v, int cmp, int set)
355 __asm__ __volatile__(
358 " wsr %2, scompare1\n"
359 "1: s32c1i %0, %3, 0\n"
360 : "=a" (set), "=&a" (tmp)
361 : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
367 /* Handle probed exception */
369 static void __init do_probed_exception(struct pt_regs *regs,
370 unsigned long exccause)
372 if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
373 regs->pc += 3; /* skip the s32c1i instruction */
376 do_unhandled(regs, exccause);
380 /* Simple test of S32C1I (soc bringup assist) */
382 static int __init check_s32c1i(void)
384 int n, cause1, cause2;
385 void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
388 handbus = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
389 do_probed_exception);
390 handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
391 do_probed_exception);
392 handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
393 do_probed_exception);
395 /* First try an S32C1I that does not store: */
398 n = probed_compare_swap(&rcw_word, 0, 2);
401 /* took exception? */
403 /* unclean exception? */
404 if (n != 2 || rcw_word != 1)
405 panic("S32C1I exception error");
406 } else if (rcw_word != 1 || n != 1) {
407 panic("S32C1I compare error");
410 /* Then an S32C1I that stores: */
412 rcw_word = 0x1234567;
413 n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
417 /* unclean exception? */
418 if (n != 0xabcde || rcw_word != 0x1234567)
419 panic("S32C1I exception error (b)");
420 } else if (rcw_word != 0xabcde || n != 0x1234567) {
421 panic("S32C1I store error");
424 /* Verify consistency of exceptions: */
425 if (cause1 || cause2) {
426 pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
427 /* If emulation of S32C1I upon bus error gets implemented,
428 we can get rid of this panic for single core (not SMP) */
429 panic("S32C1I exceptions not currently supported");
431 if (cause1 != cause2)
432 panic("inconsistent S32C1I exceptions");
434 trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
435 trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
436 trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
440 #else /* XCHAL_HAVE_S32C1I */
442 /* This condition should not occur with a commercially deployed processor.
443 Display reminder for early engr test or demo chips / FPGA bitstreams */
444 static int __init check_s32c1i(void)
446 pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
450 #endif /* XCHAL_HAVE_S32C1I */
451 early_initcall(check_s32c1i);
452 #endif /* CONFIG_S32C1I_SELFTEST */
455 void __init setup_arch(char **cmdline_p)
457 strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
458 *cmdline_p = command_line;
460 /* Reserve some memory regions */
462 #ifdef CONFIG_BLK_DEV_INITRD
463 if (initrd_start < initrd_end) {
464 initrd_is_mapped = mem_reserve(__pa(initrd_start),
465 __pa(initrd_end), 0) == 0;
466 initrd_below_start_ok = 1;
472 mem_reserve(__pa(&_stext),__pa(&_end), 1);
474 mem_reserve(__pa(&_WindowVectors_text_start),
475 __pa(&_WindowVectors_text_end), 0);
477 mem_reserve(__pa(&_DebugInterruptVector_literal_start),
478 __pa(&_DebugInterruptVector_text_end), 0);
480 mem_reserve(__pa(&_KernelExceptionVector_literal_start),
481 __pa(&_KernelExceptionVector_text_end), 0);
483 mem_reserve(__pa(&_UserExceptionVector_literal_start),
484 __pa(&_UserExceptionVector_text_end), 0);
486 mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
487 __pa(&_DoubleExceptionVector_text_end), 0);
489 #if XCHAL_EXCM_LEVEL >= 2
490 mem_reserve(__pa(&_Level2InterruptVector_text_start),
491 __pa(&_Level2InterruptVector_text_end), 0);
493 #if XCHAL_EXCM_LEVEL >= 3
494 mem_reserve(__pa(&_Level3InterruptVector_text_start),
495 __pa(&_Level3InterruptVector_text_end), 0);
497 #if XCHAL_EXCM_LEVEL >= 4
498 mem_reserve(__pa(&_Level4InterruptVector_text_start),
499 __pa(&_Level4InterruptVector_text_end), 0);
501 #if XCHAL_EXCM_LEVEL >= 5
502 mem_reserve(__pa(&_Level5InterruptVector_text_start),
503 __pa(&_Level5InterruptVector_text_end), 0);
505 #if XCHAL_EXCM_LEVEL >= 6
506 mem_reserve(__pa(&_Level6InterruptVector_text_start),
507 __pa(&_Level6InterruptVector_text_end), 0);
513 unflatten_and_copy_device_tree();
515 platform_setup(cmdline_p);
525 # if defined(CONFIG_VGA_CONSOLE)
526 conswitchp = &vga_con;
527 # elif defined(CONFIG_DUMMY_CONSOLE)
528 conswitchp = &dummy_con;
533 platform_pcibios_init();
537 static DEFINE_PER_CPU(struct cpu, cpu_data);
539 static int __init topology_init(void)
543 for_each_possible_cpu(i) {
544 struct cpu *cpu = &per_cpu(cpu_data, i);
545 cpu->hotpluggable = !!i;
546 register_cpu(cpu, i);
551 subsys_initcall(topology_init);
553 void machine_restart(char * cmd)
558 void machine_halt(void)
564 void machine_power_off(void)
566 platform_power_off();
569 #ifdef CONFIG_PROC_FS
572 * Display some core information through /proc/cpuinfo.
576 c_show(struct seq_file *f, void *slot)
578 char buf[NR_CPUS * 5];
580 cpulist_scnprintf(buf, sizeof(buf), cpu_online_mask);
581 /* high-level stuff */
582 seq_printf(f, "CPU count\t: %u\n"
584 "vendor_id\t: Tensilica\n"
585 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
586 "core ID\t\t: " XCHAL_CORE_ID "\n"
589 "cpu MHz\t\t: %lu.%02lu\n"
590 "bogomips\t: %lu.%02lu\n",
593 XCHAL_BUILD_UNIQUE_ID,
594 XCHAL_HAVE_BE ? "big" : "little",
596 (ccount_freq/10000) % 100,
597 loops_per_jiffy/(500000/HZ),
598 (loops_per_jiffy/(5000/HZ)) % 100);
600 seq_printf(f,"flags\t\t: "
610 #if XCHAL_HAVE_DENSITY
613 #if XCHAL_HAVE_BOOLEANS
622 #if XCHAL_HAVE_MINMAX
628 #if XCHAL_HAVE_CLAMPS
640 #if XCHAL_HAVE_MUL32_HIGH
646 #if XCHAL_HAVE_S32C1I
652 seq_printf(f,"physical aregs\t: %d\n"
663 seq_printf(f,"num ints\t: %d\n"
667 "debug level\t: %d\n",
668 XCHAL_NUM_INTERRUPTS,
669 XCHAL_NUM_EXTINTERRUPTS,
675 seq_printf(f,"icache line size: %d\n"
676 "icache ways\t: %d\n"
677 "icache size\t: %d\n"
679 #if XCHAL_ICACHE_LINE_LOCKABLE
683 "dcache line size: %d\n"
684 "dcache ways\t: %d\n"
685 "dcache size\t: %d\n"
687 #if XCHAL_DCACHE_IS_WRITEBACK
690 #if XCHAL_DCACHE_LINE_LOCKABLE
694 XCHAL_ICACHE_LINESIZE,
697 XCHAL_DCACHE_LINESIZE,
705 * We show only CPU #0 info.
708 c_start(struct seq_file *f, loff_t *pos)
710 return (*pos == 0) ? (void *)1 : NULL;
714 c_next(struct seq_file *f, void *v, loff_t *pos)
720 c_stop(struct seq_file *f, void *v)
724 const struct seq_operations cpuinfo_op =
732 #endif /* CONFIG_PROC_FS */