2 * arch/xtensa/kernel/setup.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 * Chris Zankel <chris@zankel.net>
12 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
14 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
17 #include <linux/errno.h>
18 #include <linux/init.h>
20 #include <linux/proc_fs.h>
21 #include <linux/screen_info.h>
22 #include <linux/bootmem.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/clk-provider.h>
26 #include <linux/cpu.h>
27 #include <linux/of_fdt.h>
28 #include <linux/of_platform.h>
30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31 # include <linux/console.h>
35 # include <linux/timex.h>
39 # include <linux/seq_file.h>
42 #include <asm/bootparam.h>
43 #include <asm/mmu_context.h>
44 #include <asm/pgtable.h>
45 #include <asm/processor.h>
46 #include <asm/timex.h>
47 #include <asm/platform.h>
49 #include <asm/setup.h>
50 #include <asm/param.h>
51 #include <asm/traps.h>
53 #include <asm/sysmem.h>
55 #include <platform/hardware.h>
57 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
58 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
61 #ifdef CONFIG_BLK_DEV_FD
62 extern struct fd_ops no_fd_ops;
63 struct fd_ops *fd_ops;
66 extern struct rtc_ops no_rtc_ops;
67 struct rtc_ops *rtc_ops;
69 #ifdef CONFIG_BLK_DEV_INITRD
70 extern unsigned long initrd_start;
71 extern unsigned long initrd_end;
72 int initrd_is_mapped = 0;
73 extern int initrd_below_start_ok;
77 void *dtb_start = __dtb_start;
80 unsigned char aux_device_present;
81 extern unsigned long loops_per_jiffy;
83 /* Command line specified as configuration option. */
85 static char __initdata command_line[COMMAND_LINE_SIZE];
87 #ifdef CONFIG_CMDLINE_BOOL
88 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
92 * Boot parameter parsing.
94 * The Xtensa port uses a list of variable-sized tags to pass data to
95 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
96 * to be recognised. The list is terminated with a zero-sized
100 typedef struct tagtable {
102 int (*parse)(const bp_tag_t*);
105 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
106 __attribute__((used, section(".taglist"))) = { tag, fn }
108 /* parse current tag */
110 static int __init parse_tag_mem(const bp_tag_t *tag)
112 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
114 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
117 return add_sysmem_bank(mi->start, mi->end);
120 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
122 #ifdef CONFIG_BLK_DEV_INITRD
124 static int __init parse_tag_initrd(const bp_tag_t* tag)
126 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
128 initrd_start = (unsigned long)__va(mi->start);
129 initrd_end = (unsigned long)__va(mi->end);
134 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
138 static int __init parse_tag_fdt(const bp_tag_t *tag)
140 dtb_start = __va(tag->data[0]);
144 __tagtable(BP_TAG_FDT, parse_tag_fdt);
146 #endif /* CONFIG_OF */
148 #endif /* CONFIG_BLK_DEV_INITRD */
150 static int __init parse_tag_cmdline(const bp_tag_t* tag)
152 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
156 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
158 static int __init parse_bootparam(const bp_tag_t* tag)
160 extern tagtable_t __tagtable_begin, __tagtable_end;
163 /* Boot parameters must start with a BP_TAG_FIRST tag. */
165 if (tag->id != BP_TAG_FIRST) {
166 printk(KERN_WARNING "Invalid boot parameters!\n");
170 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
172 /* Parse all tags. */
174 while (tag != NULL && tag->id != BP_TAG_LAST) {
175 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
176 if (tag->id == t->tag) {
181 if (t == &__tagtable_end)
182 printk(KERN_WARNING "Ignoring tag "
183 "0x%08x\n", tag->id);
184 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
191 bool __initdata dt_memory_scan = false;
193 #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
194 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
195 EXPORT_SYMBOL(xtensa_kio_paddr);
197 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
198 int depth, void *data)
200 const __be32 *ranges;
206 if (!of_flat_dt_is_compatible(node, "simple-bus"))
209 ranges = of_get_flat_dt_prop(node, "ranges", &len);
215 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
216 /* round down to nearest 256MB boundary */
217 xtensa_kio_paddr &= 0xf0000000;
222 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
223 int depth, void *data)
229 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
235 add_sysmem_bank(base, base + size);
238 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
240 return __alloc_bootmem(size, align, 0);
243 void __init early_init_devtree(void *params)
245 if (sysmem.nr_banks == 0)
246 dt_memory_scan = true;
248 early_init_dt_scan(params);
249 of_scan_flat_dt(xtensa_dt_io_area, NULL);
251 if (!command_line[0])
252 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
255 static int __init xtensa_device_probe(void)
258 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
262 device_initcall(xtensa_device_probe);
264 #endif /* CONFIG_OF */
267 * Initialize architecture. (Early stage)
270 void __init init_arch(bp_tag_t *bp_start)
272 /* Parse boot parameters */
275 parse_bootparam(bp_start);
278 early_init_devtree(dtb_start);
281 if (sysmem.nr_banks == 0) {
282 add_sysmem_bank(PLATFORM_DEFAULT_MEM_START,
283 PLATFORM_DEFAULT_MEM_START +
284 PLATFORM_DEFAULT_MEM_SIZE);
287 #ifdef CONFIG_CMDLINE_BOOL
288 if (!command_line[0])
289 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
292 /* Early hook for platforms */
294 platform_init(bp_start);
296 /* Initialize MMU. */
302 * Initialize system. Setup memory and reserve regions.
307 extern char _WindowVectors_text_start;
308 extern char _WindowVectors_text_end;
309 extern char _DebugInterruptVector_literal_start;
310 extern char _DebugInterruptVector_text_end;
311 extern char _KernelExceptionVector_literal_start;
312 extern char _KernelExceptionVector_text_end;
313 extern char _UserExceptionVector_literal_start;
314 extern char _UserExceptionVector_text_end;
315 extern char _DoubleExceptionVector_literal_start;
316 extern char _DoubleExceptionVector_text_end;
317 #if XCHAL_EXCM_LEVEL >= 2
318 extern char _Level2InterruptVector_text_start;
319 extern char _Level2InterruptVector_text_end;
321 #if XCHAL_EXCM_LEVEL >= 3
322 extern char _Level3InterruptVector_text_start;
323 extern char _Level3InterruptVector_text_end;
325 #if XCHAL_EXCM_LEVEL >= 4
326 extern char _Level4InterruptVector_text_start;
327 extern char _Level4InterruptVector_text_end;
329 #if XCHAL_EXCM_LEVEL >= 5
330 extern char _Level5InterruptVector_text_start;
331 extern char _Level5InterruptVector_text_end;
333 #if XCHAL_EXCM_LEVEL >= 6
334 extern char _Level6InterruptVector_text_start;
335 extern char _Level6InterruptVector_text_end;
340 #ifdef CONFIG_S32C1I_SELFTEST
341 #if XCHAL_HAVE_S32C1I
343 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
346 * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
348 * If *v == cmp, set *v = set. Return previous *v.
350 static inline int probed_compare_swap(int *v, int cmp, int set)
354 __asm__ __volatile__(
357 " wsr %2, scompare1\n"
358 "1: s32c1i %0, %3, 0\n"
359 : "=a" (set), "=&a" (tmp)
360 : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
366 /* Handle probed exception */
368 static void __init do_probed_exception(struct pt_regs *regs,
369 unsigned long exccause)
371 if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
372 regs->pc += 3; /* skip the s32c1i instruction */
375 do_unhandled(regs, exccause);
379 /* Simple test of S32C1I (soc bringup assist) */
381 static int __init check_s32c1i(void)
383 int n, cause1, cause2;
384 void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
387 handbus = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
388 do_probed_exception);
389 handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
390 do_probed_exception);
391 handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
392 do_probed_exception);
394 /* First try an S32C1I that does not store: */
397 n = probed_compare_swap(&rcw_word, 0, 2);
400 /* took exception? */
402 /* unclean exception? */
403 if (n != 2 || rcw_word != 1)
404 panic("S32C1I exception error");
405 } else if (rcw_word != 1 || n != 1) {
406 panic("S32C1I compare error");
409 /* Then an S32C1I that stores: */
411 rcw_word = 0x1234567;
412 n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
416 /* unclean exception? */
417 if (n != 0xabcde || rcw_word != 0x1234567)
418 panic("S32C1I exception error (b)");
419 } else if (rcw_word != 0xabcde || n != 0x1234567) {
420 panic("S32C1I store error");
423 /* Verify consistency of exceptions: */
424 if (cause1 || cause2) {
425 pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
426 /* If emulation of S32C1I upon bus error gets implemented,
427 we can get rid of this panic for single core (not SMP) */
428 panic("S32C1I exceptions not currently supported");
430 if (cause1 != cause2)
431 panic("inconsistent S32C1I exceptions");
433 trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
434 trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
435 trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
439 #else /* XCHAL_HAVE_S32C1I */
441 /* This condition should not occur with a commercially deployed processor.
442 Display reminder for early engr test or demo chips / FPGA bitstreams */
443 static int __init check_s32c1i(void)
445 pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
449 #endif /* XCHAL_HAVE_S32C1I */
450 early_initcall(check_s32c1i);
451 #endif /* CONFIG_S32C1I_SELFTEST */
454 void __init setup_arch(char **cmdline_p)
456 strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
457 *cmdline_p = command_line;
459 /* Reserve some memory regions */
461 #ifdef CONFIG_BLK_DEV_INITRD
462 if (initrd_start < initrd_end) {
463 initrd_is_mapped = mem_reserve(__pa(initrd_start),
464 __pa(initrd_end), 0) == 0;
465 initrd_below_start_ok = 1;
471 mem_reserve(__pa(&_stext),__pa(&_end), 1);
473 mem_reserve(__pa(&_WindowVectors_text_start),
474 __pa(&_WindowVectors_text_end), 0);
476 mem_reserve(__pa(&_DebugInterruptVector_literal_start),
477 __pa(&_DebugInterruptVector_text_end), 0);
479 mem_reserve(__pa(&_KernelExceptionVector_literal_start),
480 __pa(&_KernelExceptionVector_text_end), 0);
482 mem_reserve(__pa(&_UserExceptionVector_literal_start),
483 __pa(&_UserExceptionVector_text_end), 0);
485 mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
486 __pa(&_DoubleExceptionVector_text_end), 0);
488 #if XCHAL_EXCM_LEVEL >= 2
489 mem_reserve(__pa(&_Level2InterruptVector_text_start),
490 __pa(&_Level2InterruptVector_text_end), 0);
492 #if XCHAL_EXCM_LEVEL >= 3
493 mem_reserve(__pa(&_Level3InterruptVector_text_start),
494 __pa(&_Level3InterruptVector_text_end), 0);
496 #if XCHAL_EXCM_LEVEL >= 4
497 mem_reserve(__pa(&_Level4InterruptVector_text_start),
498 __pa(&_Level4InterruptVector_text_end), 0);
500 #if XCHAL_EXCM_LEVEL >= 5
501 mem_reserve(__pa(&_Level5InterruptVector_text_start),
502 __pa(&_Level5InterruptVector_text_end), 0);
504 #if XCHAL_EXCM_LEVEL >= 6
505 mem_reserve(__pa(&_Level6InterruptVector_text_start),
506 __pa(&_Level6InterruptVector_text_end), 0);
512 unflatten_and_copy_device_tree();
514 platform_setup(cmdline_p);
524 # if defined(CONFIG_VGA_CONSOLE)
525 conswitchp = &vga_con;
526 # elif defined(CONFIG_DUMMY_CONSOLE)
527 conswitchp = &dummy_con;
532 platform_pcibios_init();
536 static DEFINE_PER_CPU(struct cpu, cpu_data);
538 static int __init topology_init(void)
542 for_each_possible_cpu(i) {
543 struct cpu *cpu = &per_cpu(cpu_data, i);
544 cpu->hotpluggable = !!i;
545 register_cpu(cpu, i);
550 subsys_initcall(topology_init);
552 void machine_restart(char * cmd)
557 void machine_halt(void)
563 void machine_power_off(void)
565 platform_power_off();
568 #ifdef CONFIG_PROC_FS
571 * Display some core information through /proc/cpuinfo.
575 c_show(struct seq_file *f, void *slot)
577 /* high-level stuff */
578 seq_printf(f, "CPU count\t: %u\n"
579 "CPU list\t: %*pbl\n"
580 "vendor_id\t: Tensilica\n"
581 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
582 "core ID\t\t: " XCHAL_CORE_ID "\n"
585 "cpu MHz\t\t: %lu.%02lu\n"
586 "bogomips\t: %lu.%02lu\n",
588 cpumask_pr_args(cpu_online_mask),
589 XCHAL_BUILD_UNIQUE_ID,
590 XCHAL_HAVE_BE ? "big" : "little",
592 (ccount_freq/10000) % 100,
593 loops_per_jiffy/(500000/HZ),
594 (loops_per_jiffy/(5000/HZ)) % 100);
596 seq_printf(f,"flags\t\t: "
606 #if XCHAL_HAVE_DENSITY
609 #if XCHAL_HAVE_BOOLEANS
618 #if XCHAL_HAVE_MINMAX
624 #if XCHAL_HAVE_CLAMPS
636 #if XCHAL_HAVE_MUL32_HIGH
642 #if XCHAL_HAVE_S32C1I
648 seq_printf(f,"physical aregs\t: %d\n"
659 seq_printf(f,"num ints\t: %d\n"
663 "debug level\t: %d\n",
664 XCHAL_NUM_INTERRUPTS,
665 XCHAL_NUM_EXTINTERRUPTS,
671 seq_printf(f,"icache line size: %d\n"
672 "icache ways\t: %d\n"
673 "icache size\t: %d\n"
675 #if XCHAL_ICACHE_LINE_LOCKABLE
679 "dcache line size: %d\n"
680 "dcache ways\t: %d\n"
681 "dcache size\t: %d\n"
683 #if XCHAL_DCACHE_IS_WRITEBACK
686 #if XCHAL_DCACHE_LINE_LOCKABLE
690 XCHAL_ICACHE_LINESIZE,
693 XCHAL_DCACHE_LINESIZE,
701 * We show only CPU #0 info.
704 c_start(struct seq_file *f, loff_t *pos)
706 return (*pos == 0) ? (void *)1 : NULL;
710 c_next(struct seq_file *f, void *v, loff_t *pos)
716 c_stop(struct seq_file *f, void *v)
720 const struct seq_operations cpuinfo_op =
728 #endif /* CONFIG_PROC_FS */