4 * Extracted from init.c
6 #include <linux/bootmem.h>
7 #include <linux/percpu.h>
8 #include <linux/init.h>
9 #include <linux/string.h>
10 #include <linux/slab.h>
11 #include <linux/cache.h>
14 #include <asm/tlbflush.h>
15 #include <asm/mmu_context.h>
17 #include <asm/initialize_mmu.h>
20 #if defined(CONFIG_HIGHMEM)
21 static void * __init init_pmd(unsigned long vaddr)
23 pgd_t *pgd = pgd_offset_k(vaddr);
24 pmd_t *pmd = pmd_offset(pgd, vaddr);
28 pte_t *pte = alloc_bootmem_low_pages(PAGE_SIZE);
30 for (i = 0; i < 1024; i++)
31 pte_clear(NULL, 0, pte + i);
33 set_pmd(pmd, __pmd(((unsigned long)pte) & PAGE_MASK));
34 BUG_ON(pte != pte_offset_kernel(pmd, 0));
35 pr_debug("%s: vaddr: 0x%08lx, pmd: 0x%p, pte: 0x%p\n",
36 __func__, vaddr, pmd, pte);
39 return pte_offset_kernel(pmd, 0);
43 static void __init fixedrange_init(void)
45 BUILD_BUG_ON(FIXADDR_SIZE > PMD_SIZE);
46 init_pmd(__fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK);
50 void __init paging_init(void)
52 memset(swapper_pg_dir, 0, PAGE_SIZE);
55 pkmap_page_table = init_pmd(PKMAP_BASE);
61 * Flush the mmu and reset associated register to default values.
65 #if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
67 * Writing zeros to the instruction and data TLBCFG special
68 * registers ensure that valid values exist in the register.
70 * For existing PGSZID<w> fields, zero selects the first element
71 * of the page-size array. For nonexistent PGSZID<w> fields,
72 * zero is the best value to write. Also, when changing PGSZID<w>
73 * fields, the corresponding TLB must be flushed.
75 set_itlbcfg_register(0);
76 set_dtlbcfg_register(0);
78 #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)
80 * Update the IO area mapping in case xtensa_kio_paddr has changed
82 write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
83 XCHAL_KIO_CACHED_VADDR + 6);
84 write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
85 XCHAL_KIO_CACHED_VADDR + 6);
86 write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
87 XCHAL_KIO_BYPASS_VADDR + 6);
88 write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
89 XCHAL_KIO_BYPASS_VADDR + 6);
92 local_flush_tlb_all();
94 /* Set rasid register to a known value. */
96 set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
98 /* Set PTEVADDR special register to the start of the page
99 * table, which is in kernel mappable space (ie. not
100 * statically mapped). This register's value is undefined on
103 set_ptevaddr_register(PGTABLE_START);