clock_data-rk3066b.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <mach/cru.h>
  25 #include <mach/iomux.h>
  26 #include <mach/clock.h>
  27 #include <mach/pmu.h>
  28 #include <mach/dvfs.h>
  29 #include <mach/ddr.h>
  30 #include <mach/board.h>
  31
  32 #define MHZ                     (1000*1000)
  33 #define KHZ                     (1000)
  34 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  35 #define CLK_LOOPS_RATE_REF (1200) //Mhz
  36 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  37 void rk30_clk_dump_regs(void);
  38 #if 0
  39 //flags bit
  40 //has extern 27mhz
  41 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  42 //max i2s rate
  43 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  44 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  45 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  46 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  47 //uart 1m\3m
  48 #define CLK_FLG_UART_1_3M                       (1<<5)
  49 #endif
  50 #define ARCH_RK31
  51
  52 struct apll_clk_set {
  53         unsigned long rate;
  54         u32     pllcon0;
  55         u32     pllcon1;
  56         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  57         u32     rst_dly;//us
  58         u32     clksel0;
  59         u32     clksel1;
  60         unsigned long lpj;
  61 };
  62 struct pll_clk_set {
  63         unsigned long rate;
  64         u32     pllcon0;
  65         u32     pllcon1;
  66         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  67         u32     rst_dly;//us
  68 };
  69
  70 #define SET_PLL_DATA(_pll_id,_table) \
  71 {\
  72         .id=(_pll_id),\
  73         .table=(_table),\
  74 }
  75
  76
  77 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  78 { \
  79         .rate   = (_mhz) * KHZ, \
  80         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  81         .pllcon1 = PLL_CLKF_SET(nf),\
  82         .rst_dly=((nr*500)/24+1),\
  83 }
  84
  85
  86 #define _APLL_SET_LPJ(_mhz) \
  87         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  88
  89
  90 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _axi_core_div,\
  91                 _axi_div,_ahb_div, _apb_div,_ahb2apb) \
  92 { \
  93         .rate   = _mhz * MHZ, \
  94         .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
  95         .pllcon1 = PLL_CLKF_SET(nf),\
  96         .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
  97         .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_axi_core_div,\
  98         _APLL_SET_LPJ(_mhz),\
  99         .rst_dly=((nr*500)/24+1),\
 100 }
 101
 102 #define CRU_DIV_SET(mask,shift,max) \
 103         .div_mask=(mask),\
 104 .div_shift=(shift),\
 105 .div_max=(max)
 106
 107
 108 #define CRU_SRC_SET(mask,shift ) \
 109         .src_mask=(mask),\
 110 .src_shift=(shift)
 111
 112 #define CRU_PARENTS_SET(parents_array) \
 113         .parents=(parents_array),\
 114 .parents_num=ARRAY_SIZE((parents_array))
 115
 116 #define CRU_GATE_MODE_SET(_func,_IDX) \
 117         .mode=_func,\
 118 .gate_idx=(_IDX)
 119
 120 struct clk_src_sel {
 121         struct clk      *parent;
 122         u8      value;//crt bit
 123         u8      flag;
 124         //selgate
 125 };
 126
 127 #define GATE_CLK(NAME,PARENT,ID) \
 128         static struct clk clk_##NAME = { \
 129                 .name           = #NAME, \
 130                 .parent         = &PARENT, \
 131                 .mode           = gate_mode, \
 132                 .gate_idx       = CLK_GATE_##ID, \
 133         }
 134 #ifdef RK30_CLK_OFFBOARD_TEST
 135 u32 TEST_GRF_REG[0x240];
 136 u32 TEST_CRU_REG[0x240];
 137 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 138
 139 u32 cru_writel_is_pr(u32 offset)
 140 {
 141         return (offset == 0x4000);
 142 }
 143 void cru_writel(u32 v, u32 offset)
 144 {
 145
 146         u32 mask_v = v >> 16;
 147         TEST_CRU_REG[offset/4] &= (~mask_v);
 148
 149         v &= (mask_v);
 150
 151         TEST_CRU_REG[offset/4] |= v;
 152         TEST_CRU_REG[offset/4] &= 0x0000ffff;
 153
 154         if(cru_writel_is_pr(offset)) {
 155                 CLKDATA_DBG("cru w offset=%d,set=%x,reg=%x\n", offset, v, TEST_CRU_REG[offset/4]);
 156
 157         }
 158
 159 }
 160 void cru_writel_i2s(u32 v, u32 offset)
 161 {
 162         TEST_CRU_REG[offset/4] = v;
 163 }
 164 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 165
 166 #define regfile_readl(offset)   (0xffffffff)
 167 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 168 void rk30_clkdev_add(struct clk_lookup *cl);
 169 #else
 170 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 171 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 172 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 173 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 174
 175 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 176 #endif
 177
 178 //#define DEBUG
 179 #ifdef DEBUG
 180 #define CLKDATA_DBG(fmt, args...) printk(KERN_DEBUG "CLKDATA_DBG:\t"fmt, ##args)
 181 #define CLKDATA_LOG(fmt, args...) printk(KERN_INFO "CLKDATA_LOG:\t"fmt, ##args)
 182 #else
 183 #define CLKDATA_DBG(fmt, args...) do {} while(0)
 184 #define CLKDATA_LOG(fmt, args...) do {} while(0)
 185 #endif
 186 #define CLKDATA_ERR(fmt, args...) printk(KERN_ERR "CLKDATA_ERR:\t"fmt, ##args)
 187 #define CLKDATA_WARNNING(fmt, args...) printk("CLKDATA_WANNING:\t"fmt, ##args)
 188
 189
 190 #define get_cru_bits(con,mask,shift)\
 191         ((cru_readl((con)) >> (shift)) & (mask))
 192
 193 #define set_cru_bits_w_msk(val,mask,shift,con)\
 194         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 195
 196
 197 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 198                 &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 199
 200
 201 static u32 rk30_clock_flags = 0;
 202 static struct clk codec_pll_clk;
 203 static struct clk general_pll_clk;
 204 static struct clk arm_pll_clk;
 205 static unsigned long lpj_gpll;
 206 static unsigned int __initdata armclk = 504 * MHZ;
 207
 208
 209 /************************clk recalc div rate*********************************/
 210
 211 //for free div
 212 static unsigned long clksel_recalc_div(struct clk *clk)
 213 {
 214         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 215
 216         unsigned long rate = clk->parent->rate / div;
 217         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 218         return rate;
 219 }
 220
 221 //for div 1 2 4 2^n
 222 static unsigned long clksel_recalc_shift(struct clk *clk)
 223 {
 224         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
 225         unsigned long rate = clk->parent->rate >> shift;
 226         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 227         return rate;
 228 }
 229
 230
 231 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 232 {
 233         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
 234         unsigned long rate = clk->parent->rate >> shift;
 235         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 236         return rate;
 237 }
 238
 239 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 240 {
 241         unsigned long rate = clk->parent->rate;
 242         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 243         return rate;
 244 }
 245 /********************************set div rate***********************************/
 246
 247 //for free div
 248 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 249 {
 250         u32 div;
 251         for (div = 0; div < clk->div_max; div++) {
 252                 u32 new_rate = clk->parent->rate / (div + 1);
 253                 if (new_rate <= rate) {
 254                         set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
 255                         //clk->rate = new_rate;
 256                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n",
 257                                         clk->name, rate, div + 1);
 258                         return 0;
 259                 }
 260         }
 261         return -ENOENT;
 262 }
 263
 264 //for div 1 2 4 2^n
 265 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 266 {
 267         u32 shift;
 268         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 269                 u32 new_rate = clk->parent->rate >> shift;
 270                 if (new_rate <= rate) {
 271                         set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
 272                         clk->rate = new_rate;
 273                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 274                                         clk->name, rate, shift);
 275                         return 0;
 276                 }
 277         }
 278         return -ENOENT;
 279 }
 280
 281 //for div 2 4 2^n
 282 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 283 {
 284         u32 shift;
 285
 286         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 287                 u32 new_rate = clk->parent->rate >> shift;
 288                 if (new_rate <= rate) {
 289                         set_cru_bits_w_msk(shift - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 290                         clk->rate = new_rate;
 291                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n",
 292                                         clk->name, rate, shift);
 293                         return 0;
 294                 }
 295         }
 296         return -ENOENT;
 297 }
 298
 299
 300 //for div 1 2 4 2*n
 301 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 302 {
 303         u32 div;
 304         for (div = 2; div < clk->div_max; div += 2) {
 305                 u32 new_rate = clk->parent->rate / div;
 306                 if (new_rate <= rate) {
 307                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 308                         clk->rate = new_rate;
 309                         pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
 310                                         __func__, clk->name, rate, div);
 311                         return 0;
 312                 }
 313         }
 314         return -ENOENT;
 315 }
 316
 317 static u32 clk_get_evendiv(unsigned long rate_out, unsigned long rate , u32 div_max)
 318 {
 319        u32 div;
 320        unsigned long new_rate;
 321        for (div = 1; div < div_max; div += 2) {
 322                new_rate = rate / (div + 1);
 323                if (new_rate <= rate_out) {
 324                        return div + 1;
 325                }
 326        }
 327        return div_max ? div_max : 1;
 328 }
 329
 330 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate , u32 div_max)
 331 {
 332         u32 div;
 333         unsigned long new_rate;
 334         for (div = 0; div < div_max; div++) {
 335                 new_rate = rate / (div + 1);
 336                 if (new_rate <= rate_out) {
 337                         return div + 1;
 338                 }
 339         }
 340         return div_max ? div_max : 1;
 341 }
 342
 343 struct clk *get_evendiv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 344        u32 div[2] = {0, 0};
 345        unsigned long new_rate[2] = {0, 0};
 346        u32 i;
 347
 348        if(clk->rate == rate)
 349                return clk->parent;
 350        for(i = 0; i < 2; i++) {
 351                div[i] = clk_get_evendiv(rate, clk->parents[i]->rate, clk->div_max);
 352                new_rate[i] = clk->parents[i]->rate / div[i];
 353                if(new_rate[i] == rate) {
 354                        *div_out = div[i];
 355                        return clk->parents[i];
 356                }
 357        }
 358        if(new_rate[0] < new_rate[1])
 359                i = 1;
 360        else
 361                i = 0;
 362        *div_out = div[i];
 363        return clk->parents[i];
 364 }
 365
 366 struct clk *get_freediv_parents_div(struct clk *clk, unsigned long rate, u32 *div_out) {
 367         u32 div[2] = {0, 0};
 368         unsigned long new_rate[2] = {0, 0};
 369         u32 i;
 370
 371         if(clk->rate == rate)
 372                 return clk->parent;
 373         for(i = 0; i < 2; i++) {
 374                 div[i] = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
 375                 new_rate[i] = clk->parents[i]->rate / div[i];
 376                 if(new_rate[i] == rate) {
 377                         *div_out = div[i];
 378                         return clk->parents[i];
 379                 }
 380         }
 381         if(new_rate[0] < new_rate[1])
 382                 i = 1;
 383         else
 384                 i = 0;
 385         *div_out = div[i];
 386         return clk->parents[i];
 387 }
 388
 389 static int clkset_rate_evendiv_autosel_parents(struct clk *clk, unsigned long rate)
 390 {
 391        struct clk *p_clk;
 392        u32 div, old_div;
 393        int ret = 0;
 394        if(clk->rate == rate)
 395                return 0;
 396        p_clk = get_evendiv_parents_div(clk, rate, &div);
 397
 398        if(!p_clk)
 399                return -ENOENT;
 400
 401        CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 402        if (clk->parent != p_clk) {
 403                old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 404
 405                if(div > old_div) {
 406                        set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 407                }
 408                ret = clk_set_parent_nolock(clk, p_clk);
 409                if(ret) {
 410                        CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 411                        return -ENOENT;
 412                }
 413        }
 414        //set div
 415        set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 416        return 0;
 417 }
 418
 419 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 420 {
 421         struct clk *p_clk;
 422         u32 div, old_div;
 423         int ret = 0;
 424         if(clk->rate == rate)
 425                 return 0;
 426         p_clk = get_freediv_parents_div(clk, rate, &div);
 427
 428         if(!p_clk)
 429                 return -ENOENT;
 430
 431         CLKDATA_DBG("%s %lu,form %s\n", clk->name, rate, p_clk->name);
 432         if (clk->parent != p_clk) {
 433                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con), clk->div_shift, clk->div_mask) + 1;
 434
 435                 if(div > old_div) {
 436                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 437                 }
 438                 ret = clk_set_parent_nolock(clk, p_clk);
 439                 if(ret) {
 440                         CLKDATA_ERR("%s can't set %lu,reparent err\n", clk->name, rate);
 441                         return -ENOENT;
 442                 }
 443         }
 444         //set div
 445         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 446         return 0;
 447 }
 448
 449 //rate==div rate //hdmi
 450 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 451 {
 452         struct clk *p_clk;
 453         u32 div, old_div;
 454         int ret;
 455         p_clk = get_freediv_parents_div(clk, rate, &div);
 456
 457         if(!p_clk)
 458                 return -ENOENT;
 459
 460         if((p_clk->rate / div) != rate || (p_clk->rate % div))
 461                 return -ENOENT;
 462
 463         if (clk->parent != p_clk) {
 464                 old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
 465                                 clk->div_shift, clk->div_mask) + 1;
 466                 if(div > old_div) {
 467                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 468                 }
 469                 ret = clk_set_parent_nolock(clk, p_clk);
 470                 if (ret) {
 471                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
 472                         return ret;
 473                 }
 474         }
 475         //set div
 476         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 477         return 0;
 478 }
 479
 480 /***************************round********************************/
 481
 482 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 483 {
 484         return clk->parent->rate / clk_get_freediv(rate, clk->parent->rate, clk->div_max);
 485 }
 486
 487 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 488 {
 489         u32 div;
 490         struct clk *p_clk;
 491         if(clk->rate == rate)
 492                 return clk->rate;
 493         p_clk = get_freediv_parents_div(clk, rate, &div);
 494         if(!p_clk)
 495                 return 0;
 496         return p_clk->rate / div;
 497 }
 498
 499 /**************************************others seting************************************/
 500
 501 static struct clk *clksel_get_parent(struct clk *clk) {
 502         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 503 }
 504 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 505 {
 506         u32 i;
 507         if (unlikely(!clk->parents))
 508                 return -EINVAL;
 509         for (i = 0; (i < clk->parents_num); i++) {
 510                 if (clk->parents[i] != parent)
 511                         continue;
 512                 set_cru_bits_w_msk(i, clk->src_mask, clk->src_shift, clk->clksel_con);
 513                 return 0;
 514         }
 515         return -EINVAL;
 516 }
 517
 518 static int gate_mode(struct clk *clk, int on)
 519 {
 520         int idx = clk->gate_idx;
 521         if (idx >= CLK_GATE_MAX)
 522                 return -EINVAL;
 523         if(on) {
 524                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 525                 //CLKDATA_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 526                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 527         } else {
 528                 cru_writel(CLK_GATE_W_MSK(idx) | CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 529                 //      CLKDATA_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 530                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 531         }
 532         return 0;
 533 }
 534 /*****************************frac set******************************************/
 535
 536 static unsigned long clksel_recalc_frac(struct clk *clk)
 537 {
 538         unsigned long rate;
 539         u64 rate64;
 540         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 541         if (r == 0) // FPGA ?
 542                 return clk->parent->rate;
 543         numerator = r >> 16;
 544         denominator = r & 0xFFFF;
 545         rate64 = (u64)clk->parent->rate * numerator;
 546         do_div(rate64, denominator);
 547         rate = rate64;
 548         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 549         return rate;
 550 }
 551
 552 static u32 clk_gcd(u32 numerator, u32 denominator)
 553 {
 554         u32 a, b;
 555
 556         if (!numerator || !denominator)
 557                 return 0;
 558         if (numerator > denominator) {
 559                 a = numerator;
 560                 b = denominator;
 561         } else {
 562                 a = denominator;
 563                 b = numerator;
 564         }
 565         while (b != 0) {
 566                 int r = b;
 567                 b = a % b;
 568                 a = r;
 569         }
 570
 571         return a;
 572 }
 573
 574 static int frac_div_get_seting(unsigned long rate_out, unsigned long rate,
 575                 u32 *numerator, u32 *denominator)
 576 {
 577         u32 gcd_vl;
 578         gcd_vl = clk_gcd(rate, rate_out);
 579         CLKDATA_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n", rate_out, rate, gcd_vl);
 580
 581         if (!gcd_vl) {
 582                 CLKDATA_ERR("gcd=0, i2s frac div is not be supported\n");
 583                 return -ENOENT;
 584         }
 585
 586         *numerator = rate_out / gcd_vl;
 587         *denominator = rate / gcd_vl;
 588
 589         CLKDATA_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 590                         *numerator, *denominator, *denominator / *numerator);
 591
 592         if (*numerator > 0xffff || *denominator > 0xffff ||
 593                         (*denominator / (*numerator)) < 20) {
 594                 CLKDATA_ERR("can't get a available nume and deno\n");
 595                 return -ENOENT;
 596         }
 597
 598         return 0;
 599
 600 }
 601 /* *********************pll **************************/
 602
 603 #define rk30_clock_udelay(a) udelay(a);
 604
 605 /*********************pll lock status**********************************/
 606 //#define GRF_SOC_CON0       0x15c
 607 static void pll_wait_lock(int pll_idx)
 608 {
 609         u32 pll_state[4] = {1, 0, 2, 3};
 610         u32 bit = 0x20u << pll_state[pll_idx];
 611         int delay = 24000000;
 612         while (delay > 0) {
 613                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 614                         break;
 615                 delay--;
 616         }
 617         if (delay == 0) {
 618                 CLKDATA_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
 619                                 cru_readl(PLL_CONS(pll_idx, 0)),
 620                                 cru_readl(PLL_CONS(pll_idx, 1)),
 621                                 cru_readl(PLL_CONS(pll_idx, 2)),
 622                                 cru_readl(PLL_CONS(pll_idx, 3)));
 623
 624                 CLKDATA_ERR("wait pll bit 0x%x time out!\n", bit);
 625                 while(1);
 626         }
 627 }
 628
 629
 630
 631 /***************************pll function**********************************/
 632 static unsigned long pll_clk_recalc(u32 pll_id, unsigned long parent_rate)
 633 {
 634         unsigned long rate;
 635
 636         if (PLLS_IN_NORM(pll_id)) {
 637                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
 638                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
 639
 640
 641                 u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
 642
 643                 /*
 644                    CLKDATA_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 645                    ,PLL_CONS(pll_id,1),pll_con1, rate64);
 646                    */
 647
 648
 649                 //CLKDATA_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 650                 //CLKDATA_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 651                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 652
 653                 do_div(rate64, PLL_NR(pll_con0));
 654                 do_div(rate64, PLL_NO(pll_con0));
 655
 656                 rate = rate64;
 657                 /*
 658                    CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 659                    pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 660                    */
 661         } else {
 662                 rate = parent_rate;
 663                 CLKDATA_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n", pll_id, rate);
 664         }
 665         return rate;
 666 }
 667 static unsigned long plls_clk_recalc(struct clk *clk)
 668 {
 669         return pll_clk_recalc(clk->pll->id, clk->parent->rate);
 670 }
 671
 672 static int pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id)
 673 {
 674         //enter slowmode
 675         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 676         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 677         dsb();
 678         dsb();
 679         dsb();
 680         dsb();
 681         dsb();
 682         dsb();
 683         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
 684         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
 685
 686         rk30_clock_udelay(1);
 687         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 688
 689         pll_wait_lock(pll_id);
 690
 691         //return form slow
 692         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 693
 694         /*
 695            CLKDATA_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 696            cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 697            */
 698
 699         return 0;
 700 }
 701 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 702 {
 703         struct _pll_data *pll_data = c->pll;
 704         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 705
 706         while(clk_set->rate) {
 707                 if (clk_set->rate == rate) {
 708                         break;
 709                 }
 710                 clk_set++;
 711         }
 712         if(clk_set->rate == rate) {
 713                 pll_clk_set_rate(clk_set, pll_data->id);
 714                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 715         } else {
 716                 CLKDATA_ERR("gpll is no corresponding rate=%lu\n", rate);
 717                 return -1;
 718         }
 719         return 0;
 720 }
 721
 722 #define PLL_FREF_MIN (183*KHZ)
 723 #define PLL_FREF_MAX (1500*MHZ)
 724
 725 #define PLL_FVCO_MIN (300*MHZ)
 726 #define PLL_FVCO_MAX (1500*MHZ)
 727
 728 #define PLL_FOUT_MIN (18750*KHZ)
 729 #define PLL_FOUT_MAX (1500*MHZ)
 730
 731 #define PLL_NF_MAX (65536)
 732 #define PLL_NR_MAX (64)
 733 #define PLL_NO_MAX (64)
 734
 735 static int pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz, u32 *clk_nr, u32 *clk_nf, u32 *clk_no)
 736 {
 737         u32 nr, nf, no, nonr;
 738         u32 n;
 739         u32 YFfenzi;
 740         u32 YFfenmu;
 741         unsigned long fref, fvco, fout;
 742         u32 gcd_val = 0;
 743
 744         CLKDATA_DBG("pll_clk_get_set fin=%lu,fout=%lu\n", fin_hz, fout_hz);
 745         if(!fin_hz || !fout_hz || fout_hz == fin_hz)
 746                 return 0;
 747         gcd_val = clk_gcd(fin_hz, fout_hz);
 748         YFfenzi = fout_hz / gcd_val;
 749         YFfenmu = fin_hz / gcd_val;
 750
 751         for(n = 1;; n++) {
 752                 nf = YFfenzi * n;
 753                 nonr = YFfenmu * n;
 754                 if(nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 755                         break;
 756                 for(no = 1; no <= PLL_NO_MAX; no++) {
 757                         if(!(no == 1 || !(no % 2)))
 758                                 continue;
 759
 760                         if(nonr % no)
 761                                 continue;
 762                         nr = nonr / no;
 763
 764                         if(nr > PLL_NR_MAX) //PLL_NR_MAX
 765                                 continue;
 766
 767                         fref = fin_hz / nr;
 768                         if(fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 769                                 continue;
 770
 771                         fvco = (fin_hz / nr) * nf;
 772                         if(fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 773                                 continue;
 774                         fout = fvco / no;
 775                         if(fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 776                                 continue;
 777                         *clk_nr = nr;
 778                         *clk_no = no;
 779                         *clk_nf = nf;
 780                         return 1;
 781
 782                 }
 783
 784         }
 785         return 0;
 786 }
 787
 788 static int pll_clk_mode(struct clk *clk, int on)
 789 {
 790         u8 pll_id = clk->pll->id;
 791         u32 nr = PLL_NR(cru_readl(PLL_CONS(pll_id, 0)));
 792         u32 dly = (nr * 500) / 24 + 1;
 793         CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
 794         if (on) {
 795                 cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 796                 rk30_clock_udelay(dly);
 797                 pll_wait_lock(pll_id);
 798                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 799         } else {
 800                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 801                 cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
 802         }
 803         return 0;
 804 }
 805
 806 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 807 {
 808         struct _pll_data *pll_data = c->pll;
 809         struct pll_clk_set *clk_set = (struct pll_clk_set *)pll_data->table;
 810         struct pll_clk_set temp_clk_set;
 811         u32 clk_nr, clk_nf, clk_no;
 812
 813
 814         while(clk_set->rate) {
 815                 if (clk_set->rate == rate) {
 816                         break;
 817                 }
 818                 clk_set++;
 819         }
 820         if(clk_set->rate == rate) {
 821                 CLKDATA_DBG("cpll get a rate\n");
 822                 pll_clk_set_rate(clk_set, pll_data->id);
 823
 824         } else {
 825                 CLKDATA_DBG("cpll get auto calc a rate\n");
 826                 if(pll_clk_get_set(c->parent->rate, rate, &clk_nr, &clk_nf, &clk_no) == 0) {
 827                         pr_err("cpll auto set rate error\n");
 828                         return -ENOENT;
 829                 }
 830                 CLKDATA_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n", clk_nr, clk_nf, clk_no);
 831                 temp_clk_set.pllcon0 = PLL_CLKR_SET(clk_nr) | PLL_CLKOD_SET(clk_no);
 832                 temp_clk_set.pllcon1 = PLL_CLKF_SET(clk_nf);
 833                 temp_clk_set.rst_dly = (clk_nr * 500) / 24 + 1;
 834                 pll_clk_set_rate(&temp_clk_set, pll_data->id);
 835
 836         }
 837         return 0;
 838 }
 839
 840
 841 /* ******************fixed input clk ***********************************************/
 842 static struct clk xin24m = {
 843         .name           = "xin24m",
 844         .rate           = 24 * MHZ,
 845         .flags          = RATE_FIXED,
 846 };
 847 #if 0
 848 static struct clk xin27m = {
 849         .name           = "xin27m",
 850         .rate           = 27 * MHZ,
 851         //CLK_GATE_XIN27M
 852         .flags          = RATE_FIXED,
 853
 854 };
 855 #endif
 856 static struct clk clk_12m = {
 857         .name           = "clk_12m",
 858         .parent         = &xin24m,
 859         .rate           = 12 * MHZ,
 860         .flags          = RATE_FIXED,
 861 };
 862
 863 /************************************pll func***************************/
 864 static const struct apll_clk_set *arm_pll_clk_get_best_pll_set(unsigned long rate,
 865                 struct apll_clk_set *tables) {
 866         const struct apll_clk_set *ps, *pt;
 867
 868         /* find the arm_pll we want. */
 869         ps = pt = tables;
 870         while (pt->rate) {
 871                 if (pt->rate == rate) {
 872                         ps = pt;
 873                         break;
 874                 }
 875                 // we are sorted, and ps->rate > pt->rate.
 876                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 877                         ps = pt;
 878                 if (pt->rate < rate)
 879                         break;
 880                 pt++;
 881         }
 882         //CLKDATA_DBG("arm pll best rate=%lu\n",ps->rate);
 883         return ps;
 884 }
 885 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 886 {
 887         return arm_pll_clk_get_best_pll_set(rate, clk->pll->table)->rate;
 888 }
 889 #if 1
 890 struct arm_clks_div_set {
 891         u32 rate;
 892         u32     clksel0;
 893         u32     clksel1;
 894 };
 895
 896 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 897 { \
 898         .rate    =_mhz,\
 899         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
 900         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
 901         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
 902         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 903         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 904 }
 905 struct arm_clks_div_set arm_clk_div_tlb[] = {
 906         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
 907         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
 908         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
 909         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
 910         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
 911         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
 912         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
 913 };
 914 struct arm_clks_div_set *arm_clks_get_div(u32 rate) {
 915         int i = 0;
 916         for(i = 0; arm_clk_div_tlb[i].rate != 0; i++) {
 917                 if(arm_clk_div_tlb[i].rate >= rate)
 918                         return &arm_clk_div_tlb[i];
 919         }
 920         return NULL;
 921 }
 922
 923 #endif
 924
 925 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 926 {
 927         unsigned long flags;
 928         const struct apll_clk_set *ps;
 929         u32 pll_id = clk->pll->id;
 930         u32 temp_div;
 931         u32 old_aclk_div = 0, new_aclk_div;
 932
 933         ps = arm_pll_clk_get_best_pll_set(rate, (struct apll_clk_set *)clk->pll->table);
 934
 935         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
 936         new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
 937
 938         CLKDATA_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
 939                         ps->rate, ps->pllcon0, ps->pllcon1, ps->pllcon2, ps->clksel0, ps->clksel1);
 940
 941         if(general_pll_clk.rate > clk->rate) {
 942                 temp_div = clk_get_freediv(clk->rate, general_pll_clk.rate, 10);
 943         } else {
 944                 temp_div = 1;
 945         }
 946
 947         // ungating cpu gpll path
 948         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),
 949         //      CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 950
 951         local_irq_save(flags);
 952         //div arm clk for gpll
 953
 954         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
 955         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
 956
 957         loops_per_jiffy = lpj_gpll / temp_div;
 958         smp_wmb();
 959
 960         /*if core src don't select gpll ,apll neet to enter slow mode */
 961         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 962
 963
 964         cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
 965         dsb();
 966         dsb();
 967         dsb();
 968         dsb();
 969         dsb();
 970         dsb();
 971         cru_writel(ps->pllcon0, PLL_CONS(pll_id, 0));
 972         cru_writel(ps->pllcon1, PLL_CONS(pll_id, 1));
 973
 974         rk30_clock_udelay(1);
 975         cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
 976
 977         pll_wait_lock(pll_id);
 978
 979         //return form slow
 980         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 981         //reparent to apll
 982
 983         if(new_aclk_div>=old_aclk_div) {
 984                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
 985                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
 986         }
 987
 988         cru_writel(CORE_SEL_PLL_W_MSK | CORE_SEL_APLL, CRU_CLKSELS_CON(0));
 989         if(old_aclk_div>new_aclk_div) {
 990                 cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
 991                 cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
 992         }
 993
 994         cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
 995
 996         loops_per_jiffy = ps->lpj;
 997         smp_wmb();
 998
 999         //CLKDATA_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1000
1001         local_irq_restore(flags);
1002
1003         //gate gpll path
1004         // FIXME
1005         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH) | CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1006         //              , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1007
1008         CLKDATA_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n", cru_readl(PLL_CONS(pll_id, 0)),
1009                         cru_readl(PLL_CONS(pll_id, 1)), cru_readl(PLL_CONS(pll_id, 2)),
1010                         cru_readl(PLL_CONS(pll_id, 3)), cru_readl(CRU_CLKSELS_CON(0)),
1011                         cru_readl(CRU_CLKSELS_CON(1)));
1012         return 0;
1013 }
1014
1015
1016 /************************************pll clocks***************************/
1017
1018 static const struct apll_clk_set apll_clks[] = {
1019         //_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,
1020         //              _axi_core_div, _axi_div, _ahb_div, _apb_div, _ahb2apb)
1021         _APLL_SET_CLKS(1992, 1, 83, 1, 8,       81, 81, 21, 41, 21),
1022         _APLL_SET_CLKS(1896, 1, 79, 1, 8,       81, 81, 21, 41, 21),
1023         _APLL_SET_CLKS(1800, 1, 75, 1, 8,       81, 81, 21, 41, 21),
1024         _APLL_SET_CLKS(1704, 1, 71, 1, 8,       81, 81, 21, 41, 21),
1025         _APLL_SET_CLKS(1608, 1, 67, 1, 8,       41, 41, 21, 41, 21),
1026         _APLL_SET_CLKS(1560, 1, 65, 1, 8,       41, 41, 21, 41, 21),
1027         _APLL_SET_CLKS(1512, 1, 63, 1, 8,       41, 41, 21, 41, 21),
1028         _APLL_SET_CLKS(1464, 1, 61, 1, 8,       41, 41, 21, 41, 21),
1029         _APLL_SET_CLKS(1416, 1, 59, 1, 8,       41, 41, 21, 41, 21),
1030         _APLL_SET_CLKS(1368, 1, 57, 1, 8,       41, 41, 21, 41, 21),
1031         _APLL_SET_CLKS(1320, 1, 55, 1, 8,       41, 41, 21, 41, 21),
1032         _APLL_SET_CLKS(1296, 1, 54, 1, 8,       41, 41, 21, 41, 21),
1033         _APLL_SET_CLKS(1272, 1, 53, 1, 8,       41, 41, 21, 41, 21),
1034         _APLL_SET_CLKS(1200, 1, 50, 1, 8,       41, 41, 21, 41, 21),
1035         _APLL_SET_CLKS(1176, 1, 49, 1, 8,       41, 41, 21, 41, 21),
1036         _APLL_SET_CLKS(1128, 1, 47, 1, 8,       41, 41, 21, 41, 21),
1037         _APLL_SET_CLKS(1104, 1, 46, 1, 8,       41, 41, 21, 41, 21),
1038         _APLL_SET_CLKS(1008, 1, 84, 2, 8,       41, 31, 21, 41, 21),
1039         _APLL_SET_CLKS(912,  1, 76, 2, 8,       41, 31, 21, 41, 21),
1040         _APLL_SET_CLKS(888,  1, 74, 2, 8,       41, 31, 21, 41, 21),
1041         _APLL_SET_CLKS(816 , 1, 68, 2, 8,       41, 31, 21, 41, 21),
1042         _APLL_SET_CLKS(792 , 1, 66, 2, 8,       41, 31, 21, 41, 21),
1043         _APLL_SET_CLKS(696 , 1, 58, 2, 8,       41, 31, 21, 41, 21),
1044         _APLL_SET_CLKS(600 , 1, 50, 2, 4,       41, 31, 21, 41, 21),
1045         _APLL_SET_CLKS(504 , 1, 84, 4, 4,       41, 21, 21, 41, 21),
1046         _APLL_SET_CLKS(408 , 1, 68, 4, 4,       21, 21, 21, 41, 21),
1047         _APLL_SET_CLKS(312 , 1, 52, 4, 2,       21, 21, 21, 21, 11),
1048         _APLL_SET_CLKS(252 , 1, 84, 8, 2,       21, 21, 21, 21, 11),
1049         _APLL_SET_CLKS(216 , 1, 72, 8, 2,       21, 21, 21, 21, 11),
1050         _APLL_SET_CLKS(126 , 1, 84, 16, 2,      11, 21, 11, 11, 11),
1051         _APLL_SET_CLKS(48  , 1, 64, 32, 2,      11, 11, 11, 11, 11),
1052         _APLL_SET_CLKS(0   , 1, 21, 4, 2,       11, 11, 11, 11, 11),
1053
1054 };
1055 static struct _pll_data apll_data = SET_PLL_DATA(APLL_ID, (void *)apll_clks);
1056 static struct clk arm_pll_clk = {
1057         .name           = "arm_pll",
1058         .parent         = &xin24m,
1059         .mode           = pll_clk_mode,
1060         .recalc         = plls_clk_recalc,
1061         .set_rate       = arm_pll_clk_set_rate,
1062         .round_rate     = arm_pll_clk_round_rate,
1063         .pll            = &apll_data,
1064 };
1065
1066 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1067 {
1068         /* do nothing here */
1069         return 0;
1070 }
1071 static struct _pll_data dpll_data = SET_PLL_DATA(DPLL_ID, NULL);
1072 static struct clk ddr_pll_clk = {
1073         .name           = "ddr_pll",
1074         .parent         = &xin24m,
1075         .recalc         = plls_clk_recalc,
1076         .set_rate       = ddr_pll_clk_set_rate,
1077         .pll            = &dpll_data,
1078 };
1079
1080 static const struct pll_clk_set cpll_clks[] = {
1081         _PLL_SET_CLKS(360000, 1,  60,   4),
1082         _PLL_SET_CLKS(408000, 1,  68,   4),
1083         _PLL_SET_CLKS(456000, 1,  76,   4),
1084         _PLL_SET_CLKS(504000, 1,  84,   4),
1085         _PLL_SET_CLKS(552000, 1,  46,   2),
1086         _PLL_SET_CLKS(594000, 2,  198,  4),
1087         _PLL_SET_CLKS(600000, 1,  50,   2),
1088         _PLL_SET_CLKS(742500, 8,  495,  2),
1089         _PLL_SET_CLKS(768000, 1,  64,   2),
1090         _PLL_SET_CLKS(798000, 2,  133,  2),
1091         _PLL_SET_CLKS(1188000, 2, 99,   1),
1092         _PLL_SET_CLKS(     0, 4,  133,  1),
1093 };
1094 static struct _pll_data cpll_data = SET_PLL_DATA(CPLL_ID, (void *)cpll_clks);
1095 static struct clk codec_pll_clk = {
1096         .name           = "codec_pll",
1097         .parent         = &xin24m,
1098         .mode           = pll_clk_mode,
1099         .recalc         = plls_clk_recalc,
1100         .set_rate       = cpll_clk_set_rate,
1101         .pll            = &cpll_data,
1102 };
1103
1104 static const struct pll_clk_set gpll_clks[] = {
1105         _PLL_SET_CLKS(148500,   2,      99,     8),
1106         _PLL_SET_CLKS(297000,   2,      198,    8),
1107         _PLL_SET_CLKS(300000,   1,      50,     4),
1108         _PLL_SET_CLKS(384000,   1,      64,     4),
1109         _PLL_SET_CLKS(594000,   2,      198,    4),
1110         _PLL_SET_CLKS(1188000,  2,      99,     1),
1111         _PLL_SET_CLKS(1200000,  1,      50,     1),
1112         _PLL_SET_CLKS(0,        0,       0,     0),
1113 };
1114 static struct _pll_data gpll_data = SET_PLL_DATA(GPLL_ID, (void *)gpll_clks);
1115 static struct clk general_pll_clk = {
1116         .name           = "general_pll",
1117         .parent         = &xin24m,
1118         .recalc         = plls_clk_recalc,
1119         .set_rate       = gpll_clk_set_rate,
1120         .pll            = &gpll_data
1121 };
1122 /********************************clocks***********************************/
1123 /* core and cpu setting */
1124 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1125 {
1126         return 0;
1127 }
1128
1129 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1130 {
1131         return ddr_set_pll_rk3066b(rate / MHZ, 0) * MHZ;
1132 }
1133 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1134 {
1135         u32 shift = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift);
1136         unsigned long rate = clk->parent->recalc(clk->parent) >> shift;
1137         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
1138         return rate;
1139 }
1140 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &general_pll_clk};
1141 static struct clk clk_ddr = {
1142         .name           = "ddr",
1143         .parent         = &ddr_pll_clk,
1144         .recalc         = ddr_clk_recalc_rate,
1145         .set_rate       = ddr_clk_set_rate,
1146         .round_rate     = ddr_clk_round_rate,
1147         .clksel_con     = CRU_CLKSELS_CON(26),
1148         CRU_DIV_SET(0x3, 0, 4),
1149         CRU_SRC_SET(1, 8),
1150         CRU_PARENTS_SET(clk_ddr_parents),
1151 };
1152 static int arm_core_clk_set_rate(struct clk *c, unsigned long rate)
1153 {
1154         int ret;
1155
1156         ret = clk_set_rate_nolock(c->parent, rate);
1157         if (ret) {
1158                 CLKDATA_ERR("Failed to change clk pll %s to %lu\n", c->name, rate);
1159                 return ret;
1160         }
1161         //set arm pll div 1
1162         set_cru_bits_w_msk(0, c->div_mask, c->div_shift, c->clksel_con);
1163         return 0;
1164 }
1165 static unsigned long arm_core_clk_get_rate(struct clk *c)
1166 {
1167         u32 div = (get_cru_bits(c->clksel_con, c->div_mask, c->div_shift) + 1);
1168         //c->parent->rate=c->parent->recalc(c->parent);
1169         return c->parent->rate / div;
1170 }
1171 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1172 {
1173         u32 div = (get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1);
1174         return clk_round_rate_nolock(clk->parent, rate) / div;
1175 }
1176
1177 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1178 {
1179
1180         u32 temp_div;
1181         struct clk *old_prt;
1182
1183         if(clk->parent == new_prt)
1184                 return 0;
1185         if (unlikely(!clk->parents))
1186                 return -EINVAL;
1187         CLKDATA_DBG("%s,reparent %s\n", clk->name, new_prt->name);
1188         //arm
1189         old_prt = clk->parent;
1190
1191         if(clk->parents[0] == new_prt) {
1192                 new_prt->set_rate(new_prt, 300 * MHZ);
1193                 set_cru_bits_w_msk(0, clk->div_mask, clk->div_shift, clk->clksel_con);
1194         } else if(clk->parents[1] == new_prt) {
1195
1196                 if(new_prt->rate > old_prt->rate) {
1197                         temp_div = clk_get_freediv(old_prt->rate, new_prt->rate, clk->div_max);
1198                         set_cru_bits_w_msk(temp_div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1199                 }
1200                 set_cru_bits_w_msk(1, clk->src_mask, clk->src_shift, clk->clksel_con);
1201                 new_prt->set_rate(new_prt, 300 * MHZ);
1202         } else
1203                 return -1;
1204
1205
1206         return 0;
1207
1208 }
1209
1210 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1211 {
1212         u32 temp_div;
1213         u32 old_aclk_div = 0, new_aclk_div;
1214         struct arm_clks_div_set *temp_clk_div;
1215         unsigned long arm_gpll_rate, arm_gpll_lpj;
1216         temp_div = clk_get_freediv(rate, c->parent->rate, c->div_max);
1217         arm_gpll_rate = c->parent->rate / temp_div;
1218
1219         temp_clk_div = arm_clks_get_div(arm_gpll_rate / MHZ);
1220         if(!temp_clk_div)
1221                 temp_clk_div = &arm_clk_div_tlb[4];
1222
1223         old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1224         new_aclk_div = GET_CORE_ACLK_VAL(temp_clk_div->clksel1 & CORE_ACLK_MSK);
1225         if(c->rate >= rate) {
1226                 arm_gpll_lpj = lpj_gpll / temp_div;
1227                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1228         }
1229
1230         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1231         cru_writel((temp_clk_div->clksel0) | CORE_CLK_DIV(temp_div) | CORE_CLK_DIV_W_MSK,
1232                         CRU_CLKSELS_CON(0));
1233         if((c->rate < rate)) {
1234                 arm_gpll_lpj = lpj_gpll / temp_div;
1235                 set_cru_bits_w_msk(temp_div - 1, c->div_mask, c->div_shift, c->clksel_con);
1236         }
1237         return 0;
1238 }
1239 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1240 {
1241         return c->parent->rate;
1242 }
1243 static struct clk clk_core_gpll_path = {
1244         .name           = "cpu_gpll_path",
1245         .parent         = &general_pll_clk,
1246         .gate_idx       = CLK_GATE_CPU_GPLL_PATH,
1247         .recalc         = arm_core_gpll_clk_get_rate,
1248         .set_rate       = core_gpll_clk_set_rate,
1249         CRU_GATE_MODE_SET(gate_mode, CLK_GATE_CPU_GPLL_PATH),
1250 };
1251
1252
1253 static struct clk *clk_cpu_parents[2] = {&arm_pll_clk, &clk_core_gpll_path};
1254
1255 static struct clk clk_core = {
1256         .name           = "core",
1257         .parent         = &arm_pll_clk,
1258         .set_rate       = arm_core_clk_set_rate,
1259         .recalc         = arm_core_clk_get_rate,
1260         .round_rate     = core_clk_round_rate,
1261         .set_parent     = core_clksel_set_parent,
1262         .clksel_con     = CRU_CLKSELS_CON(0),
1263         CRU_DIV_SET(0x1f, 9, 32),
1264         CRU_SRC_SET(1, 8),
1265         CRU_PARENTS_SET(clk_cpu_parents),
1266 };
1267 #ifdef ARCH_RK31
1268 static struct clk *clk_cpu_div_parents[2] = {&arm_pll_clk, &general_pll_clk};
1269 static struct clk clk_cpu_div = {
1270         .name           = "cpu_div",
1271         .parent         = &arm_pll_clk,
1272         .set_rate       = clksel_set_rate_freediv,
1273         .recalc         = clksel_recalc_div,
1274         .clksel_con     = CRU_CLKSELS_CON(0),
1275         CRU_DIV_SET(0x1f, 0, 32),
1276         CRU_SRC_SET(1, 5),
1277         CRU_PARENTS_SET(clk_cpu_div_parents),
1278 };
1279
1280 #endif
1281 #ifdef ARCH_RK31
1282 GATE_CLK(l2c, clk_core, CLK_L2C);
1283 GATE_CLK(core_dbg, clk_core, CLK_CORE_DBG);
1284 #endif
1285 static unsigned long aclk_recalc(struct clk *clk)
1286 {
1287         unsigned long rate;
1288         u32 div = get_cru_bits(clk->clksel_con, clk->div_mask, clk->div_shift) + 1;
1289
1290         BUG_ON(div > 5);
1291         if (div >= 5)
1292                 div = 8;
1293         rate = clk->parent->rate / div;
1294         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1295
1296         return rate;
1297 };
1298 static struct clk core_periph = {
1299         .name           = "core_periph",
1300         .parent         = &clk_core,
1301         .gate_idx       = CLK_GATE_CORE_PERIPH,
1302         .recalc         = clksel_recalc_shift_2,
1303         .clksel_con     = CRU_CLKSELS_CON(0),
1304         CRU_DIV_SET(0x3, 6, 16),
1305 };
1306 #ifdef ARCH_RK31
1307 static struct clk aclk_core = {
1308         .name           = "aclk_core",
1309         .parent         = &clk_core,
1310         .gate_idx       = CLK_GATE_ACLK_CORE,
1311         .recalc         = aclk_recalc,
1312         .clksel_con     = CRU_CLKSELS_CON(1),
1313         CRU_DIV_SET(0x7, 3, 8),
1314 };
1315 #endif
1316
1317 static struct clk aclk_cpu = {
1318         .name           = "aclk_cpu",
1319         .parent         = &clk_cpu_div,
1320         .gate_idx       = CLK_GATE_ACLK_CPU,
1321         .recalc         = aclk_recalc,
1322         .set_rate       = clksel_set_rate_shift,
1323         .clksel_con     = CRU_CLKSELS_CON(1),
1324         CRU_DIV_SET(0x7, 0, 8),
1325 };
1326
1327 static struct clk hclk_cpu = {
1328         .name           = "hclk_cpu",
1329         .parent         = &aclk_cpu,
1330         .gate_idx       = CLK_GATE_HCLK_CPU,
1331         .recalc         = clksel_recalc_shift,
1332         .set_rate       = clksel_set_rate_shift,
1333         .clksel_con     = CRU_CLKSELS_CON(1),
1334         CRU_DIV_SET(0x3, 8, 4),
1335
1336 };
1337
1338 static struct clk pclk_cpu = {
1339         .name           = "pclk_cpu",
1340         .parent         = &aclk_cpu,
1341         .gate_idx       = CLK_GATE_PCLK_CPU,
1342         .recalc         = clksel_recalc_shift,
1343         .set_rate       = clksel_set_rate_shift,
1344         .clksel_con     = CRU_CLKSELS_CON(1),
1345         CRU_DIV_SET(0x3, 12, 8),
1346 };
1347
1348 static struct clk ahb2apb_cpu = {
1349         .name           = "ahb2apb",
1350         .parent         = &hclk_cpu,
1351         .recalc         = clksel_recalc_shift,
1352         .set_rate       = clksel_set_rate_shift,
1353         .clksel_con     = CRU_CLKSELS_CON(1),
1354         CRU_DIV_SET(0x3, 14, 4),
1355 };
1356
1357
1358 static struct clk atclk_cpu = {
1359         .name           = "atclk_cpu",
1360         .parent         = &pclk_cpu,
1361         .gate_idx       = CLK_GATE_ATCLK_CPU,
1362 };
1363
1364 /* GPU setting test */
1365 #if 0   //for gpu rate test
1366
1367 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
1368 {
1369         printk("gpu dbg clk %s set %lu\n",clk->name,rate);
1370         return clksel_set_rate_freediv(clk, rate);
1371 };
1372
1373 #define clk_gpu_set_rate_callback clk_gpu_set_rate
1374 #else
1375 #define clk_gpu_set_rate(clk,rate) clksel_set_rate_freediv((clk),(rate))
1376 #define clk_gpu_set_rate_callback clksel_set_rate_freediv
1377 #endif
1378
1379 #define   GPU_CORE_ACLK_CTR_TOGETHER
1380
1381 #ifdef GPU_CORE_ACLK_CTR_TOGETHER
1382 static struct clk aclk_gpu;
1383 static struct clk clk_gpu;
1384
1385 static int clk_gpu_ref_set_rate(struct clk *clk, unsigned long rate)
1386 {
1387         int ret = 0;
1388         ret=clk_gpu_set_rate(clk, rate);
1389         if(ret<0)
1390                 return ret;
1391         ret=clk_set_rate_nolock(&aclk_gpu, rate);
1392         return ret;
1393 };
1394 static long clk_gpu_ref_round_rate(struct clk *clk, unsigned long rate)
1395 {
1396         unsigned long rate_gpu;
1397         rate_gpu=clksel_freediv_round_rate(clk,rate);
1398 /*
1399         if(rate_gpu!=clksel_freediv_round_rate(&aclk_gpu,rate))
1400         {
1401                 CLKDATA_ERR("gpu rate is not equal ack gpu rate in %s\n",__FUNCTION__);
1402         }
1403 */
1404         return rate_gpu;
1405 }
1406 #endif
1407
1408 static struct clk *gpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1409
1410 static struct clk clk_gpu = {
1411         .name           = "gpu",
1412         .mode           = gate_mode,
1413         .recalc         = clksel_recalc_div,
1414 #ifdef GPU_CORE_ACLK_CTR_TOGETHER
1415         .round_rate     = clk_gpu_ref_round_rate,
1416         .set_rate               = clk_gpu_ref_set_rate,
1417 #else
1418         .round_rate     = clksel_freediv_round_rate,
1419         .set_rate               = clk_gpu_set_rate_callback,
1420 #endif
1421         .clksel_con     = CRU_CLKSELS_CON(33),
1422         .gate_idx       = CLK_GATE_CLK_GPU,
1423         CRU_DIV_SET(0x1f, 0, 32),
1424         CRU_SRC_SET(0x1, 7),
1425         CRU_PARENTS_SET(gpu_parents),
1426 };
1427 #ifdef ARCH_RK31
1428 static struct clk *gpu_aclk_parents[2] = {&codec_pll_clk, &general_pll_clk};
1429 static struct clk aclk_gpu = {
1430         .name           = "aclk_gpu",
1431         .recalc         = clksel_recalc_div,
1432         .round_rate     = clksel_freediv_round_rate,
1433         .set_rate               = clk_gpu_set_rate_callback,
1434         .clksel_con     = CRU_CLKSELS_CON(34),
1435         CRU_DIV_SET(0x1f, 0, 32),
1436         CRU_SRC_SET(0x1, 7),
1437         CRU_PARENTS_SET(gpu_parents),
1438 };
1439
1440 #ifdef GPU_CORE_ACLK_CTR_TOGETHER
1441 static int clk_aclk_gpu_null_set_rate(struct clk *clk, unsigned long rate)
1442 {
1443         return 0;
1444 };
1445
1446 static long clk_aclk_gpu_null_round_rate(struct clk *clk, unsigned long rate)
1447 {
1448         return clk->parent->round_rate(clk->parent,rate);
1449 }
1450 static unsigned long  clk_aclk_gpu_null_recalc_div(struct clk *clk)
1451 {
1452                 return clk->parent->rate;
1453 }
1454 //gpu and gpu together ctr,this clk is following aclk gpu.
1455 static struct clk aclk_gpu_null = {
1456         .name           = "aclk_gpu_null",
1457         .parent         = &aclk_gpu,
1458         .recalc         = clk_aclk_gpu_null_recalc_div,
1459         .round_rate     = clk_aclk_gpu_null_round_rate,
1460         .set_rate       = clk_aclk_gpu_null_set_rate,
1461 };
1462 #endif
1463 static struct clk aclk_gpu_slv = {
1464         .name           = "aclk_gpu_slv",
1465         .parent         = &aclk_gpu,
1466         .mode           = gate_mode,
1467         .gate_idx       = CLK_GATE_ACLK_GPU_SLV,
1468 };
1469
1470 static struct clk aclk_gpu_mst = {
1471         .name           = "aclk_gpu_mst",
1472         .parent         = &aclk_gpu,
1473         .mode           = gate_mode,
1474         .gate_idx       = CLK_GATE_ACLK_GPU_MST,
1475 };
1476 #endif
1477
1478 /* vcodec setting */
1479 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
1480 {
1481         unsigned long rate = clk->parent->rate / 4;
1482         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
1483         return rate;
1484 }
1485
1486 static struct clk *aclk_vepu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1487
1488 static struct clk aclk_vepu = {
1489         .name           = "aclk_vepu",
1490         .parent         = &codec_pll_clk,
1491         .mode           = gate_mode,
1492         .recalc         = clksel_recalc_div,
1493         //.set_rate     = clksel_set_rate_freediv,
1494         .set_rate       = clkset_rate_freediv_autosel_parents,
1495         .clksel_con     = CRU_CLKSELS_CON(32),
1496         .gate_idx       = CLK_GATE_ACLK_VEPU,
1497         CRU_DIV_SET(0x1f, 0, 32),
1498         CRU_SRC_SET(0x1, 7),
1499         CRU_PARENTS_SET(aclk_vepu_parents),
1500 };
1501
1502 static struct clk *aclk_vdpu_parents[2] = {&codec_pll_clk, &general_pll_clk};
1503
1504 static struct clk aclk_vdpu = {
1505         .name           = "aclk_vdpu",
1506         .mode           = gate_mode,
1507         .recalc         = clksel_recalc_div,
1508         //.set_rate     = clksel_set_rate_freediv,
1509         .set_rate       = clkset_rate_freediv_autosel_parents,
1510         .clksel_con     = CRU_CLKSELS_CON(32),
1511         .gate_idx       = CLK_GATE_ACLK_VDPU,
1512         CRU_DIV_SET(0x1f, 8, 32),
1513         CRU_SRC_SET(0x1, 15),
1514         CRU_PARENTS_SET(aclk_vdpu_parents),
1515 };
1516 static struct clk hclk_vepu = {
1517         .name           = "hclk_vepu",
1518         .parent         = &aclk_vepu,
1519         .mode           = gate_mode,
1520         .recalc         = clksel_recalc_vpu_hclk,
1521         .gate_idx       = CLK_GATE_HCLK_VEPU,
1522 };
1523
1524 static struct clk hclk_vdpu = {
1525         .name           = "hclk_vdpu",
1526         .parent         = &aclk_vdpu,
1527         .mode           = gate_mode,
1528         .recalc         = clksel_recalc_vpu_hclk,
1529         .gate_idx       = CLK_GATE_HCLK_VDPU,
1530 };
1531
1532 /* aclk lcdc setting */
1533 static struct clk *aclk_lcdc0_parents[] = {&codec_pll_clk, &general_pll_clk};
1534
1535 static struct clk aclk_lcdc0_pre = {
1536         .name           = "aclk_lcdc0_pre",
1537         .parent         = &codec_pll_clk,
1538         .mode           = gate_mode,
1539         .recalc         = clksel_recalc_div,
1540         .set_rate       = clkset_rate_freediv_autosel_parents,
1541         //.set_rate     = clksel_set_rate_freediv,
1542         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
1543         .clksel_con     = CRU_CLKSELS_CON(31),
1544         CRU_DIV_SET(0x1f, 0, 32),
1545         CRU_SRC_SET(0x1, 7),
1546         CRU_PARENTS_SET(aclk_lcdc0_parents),
1547 };
1548
1549 static struct clk *aclk_lcdc1_parents[] = {&codec_pll_clk, &general_pll_clk};
1550
1551 static struct clk aclk_lcdc1_pre = {
1552         .name           = "aclk_lcdc1_pre",
1553         .parent         = &codec_pll_clk,
1554         .mode           = gate_mode,
1555         .recalc         = clksel_recalc_div,
1556         .set_rate       = clkset_rate_freediv_autosel_parents,
1557         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
1558         .clksel_con     = CRU_CLKSELS_CON(31),
1559         CRU_DIV_SET(0x1f, 8, 32),
1560         CRU_SRC_SET(0x1, 15),
1561         CRU_PARENTS_SET(aclk_lcdc1_parents),
1562 };
1563
1564 /* aclk/hclk/pclk periph setting */
1565 static struct clk *aclk_periph_parents[2] = {&general_pll_clk, &codec_pll_clk};
1566
1567 static struct clk aclk_periph = {
1568         .name           = "aclk_periph",
1569         .parent         = &general_pll_clk,
1570         .mode           = gate_mode,
1571         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1572         .recalc         = clksel_recalc_div,
1573         .set_rate       = clksel_set_rate_freediv,
1574         .clksel_con     = CRU_CLKSELS_CON(10),
1575         CRU_DIV_SET(0x1f, 0, 32),
1576         CRU_SRC_SET(1, 15),
1577         CRU_PARENTS_SET(aclk_periph_parents),
1578 };
1579 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1580
1581 static struct clk pclk_periph = {
1582         .name           = "pclk_periph",
1583         .parent         = &aclk_periph,
1584         .mode           = gate_mode,
1585         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1586         .recalc         = clksel_recalc_shift,
1587         .set_rate       = clksel_set_rate_shift,
1588         .clksel_con     = CRU_CLKSELS_CON(10),
1589         CRU_DIV_SET(0x3, 12, 8),
1590 };
1591
1592 static struct clk hclk_periph = {
1593         .name           = "hclk_periph",
1594         .parent         = &aclk_periph,
1595         .mode           = gate_mode,
1596         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1597         .recalc         = clksel_recalc_shift,
1598         .set_rate       = clksel_set_rate_shift,
1599         .clksel_con     = CRU_CLKSELS_CON(10),
1600         CRU_DIV_SET(0x3, 8, 4),
1601 };
1602 /* dclk lcdc setting */
1603 // FIXME
1604 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
1605 {
1606         u32 div, old_div;
1607         int i;
1608         unsigned long new_rate;
1609         int ret = 0;
1610
1611         if(clk->rate == rate)
1612                 return 0;
1613         for(i = 0; i < 2; i++) {
1614                 div = clk_get_freediv(rate, clk->parents[i]->rate, clk->div_max);
1615                 new_rate = clk->parents[i]->rate / div;
1616                 if((rate == new_rate) && !(clk->parents[i]->rate % div)) {
1617                         break;
1618                 }
1619         }
1620         if(i >= 2) {
1621                 CLKDATA_ERR("%s can't set fixed rate%lu\n", clk->name, rate);
1622                 return -1;
1623         }
1624
1625         //CLKDATA_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
1626
1627         old_div = CRU_GET_REG_BITS_VAL(cru_readl(clk->clksel_con),
1628                         clk->div_shift, clk->div_mask) + 1;
1629         if(div > old_div)
1630                 set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1631
1632         if(clk->parents[i] != clk->parent) {
1633                 ret = clk_set_parent_nolock(clk, clk->parents[i]);
1634         }
1635
1636         if (ret) {
1637                 CLKDATA_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
1638                                 clk->name, rate, clk->parents[i]->name, clk->parent->name);
1639                 return ret;
1640         }
1641         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
1642         return 0;
1643 }
1644
1645 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
1646 {
1647         int ret = 0;
1648         struct clk *parent;
1649
1650         if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) {
1651                 parent = clk->parents[1];
1652                 //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name);
1653         } else {
1654                 parent = clk->parents[0];
1655         }
1656         //CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1657         //clk->name,rate,parent->name,clk->parent->name);
1658
1659         if(parent != clk->parents[1]) {
1660                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1661                 if (ret) {
1662                         CLKDATA_DBG("%s set rate=%lu err\n", clk->name, rate);
1663                         return ret;
1664                 }
1665         }
1666         if (clk->parent != parent) {
1667                 ret = clk_set_parent_nolock(clk, parent);
1668                 if (ret) {
1669                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1670                         return ret;
1671                 }
1672         }
1673         return ret;
1674 }
1675
1676 static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk};
1677 static struct clk dclk_lcdc0 = {
1678         .name           = "dclk_lcdc0",
1679         .mode           = gate_mode,
1680         .set_rate       = clkset_rate_evendiv_autosel_parents,
1681         .recalc         = clksel_recalc_div,
1682         .gate_idx       = CLK_GATE_DCLK_LCDC0_SRC,
1683         .clksel_con     = CRU_CLKSELS_CON(27),
1684         CRU_SRC_SET(0x1, 0),
1685         CRU_DIV_SET(0xff, 8, 256),
1686         CRU_PARENTS_SET(dclk_lcdc0_parents),
1687 };
1688
1689 static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk};
1690 static struct clk dclk_lcdc1 = {
1691         .name           = "dclk_lcdc1",
1692         .mode           = gate_mode,
1693         .set_rate       = clkset_rate_evendiv_autosel_parents,
1694         .recalc         = clksel_recalc_div,
1695         .gate_idx       = CLK_GATE_DCLK_LCDC1_SRC,
1696         .clksel_con     = CRU_CLKSELS_CON(28),
1697         CRU_SRC_SET(0x1, 0),
1698         CRU_DIV_SET(0xff, 8, 256),
1699         CRU_PARENTS_SET(dclk_lcdc1_parents),
1700 };
1701
1702 /* cif setting */
1703 // FIXME
1704 static struct clk *cifout_sel_pll_parents[2] = {&codec_pll_clk, &general_pll_clk};
1705 static struct clk cif_out_pll = {
1706         .name           = "cif_out_pll",
1707         .parent         = &general_pll_clk,
1708         .clksel_con     = CRU_CLKSELS_CON(29),
1709         CRU_SRC_SET(0x1, 0),
1710         CRU_PARENTS_SET(cifout_sel_pll_parents),
1711 };
1712
1713 static struct clk cif0_out_div = {
1714         .name           = "cif0_out_div",
1715         .parent         = &cif_out_pll,
1716         .mode           = gate_mode,
1717         .recalc         = clksel_recalc_div,
1718         .set_rate       = clksel_set_rate_freediv,
1719         .gate_idx       = CLK_GATE_CIF0_OUT,
1720         .clksel_con     = CRU_CLKSELS_CON(29),
1721         CRU_DIV_SET(0x1f, 1, 32),
1722 };
1723
1724 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
1725 {
1726         int ret = 0;
1727         struct clk *parent;
1728
1729         if (rate == 24 * MHZ) {
1730                 parent = clk->parents[1];
1731         } else {
1732                 parent = clk->parents[0];
1733                 ret = clk_set_rate_nolock(parent, rate);
1734                 if (ret)
1735                         return ret;
1736         }
1737         if (clk->parent != parent)
1738                 ret = clk_set_parent_nolock(clk, parent);
1739
1740         return ret;
1741 }
1742
1743 static struct clk *cif0_out_parents[2] = {&cif0_out_div, &xin24m};
1744 static struct clk cif0_out = {
1745         .name           = "cif0_out",
1746         .parent         = &cif0_out_div,
1747         .set_rate       = cif_out_set_rate,
1748         .clksel_con     = CRU_CLKSELS_CON(29),
1749         CRU_SRC_SET(0x1, 7),
1750         CRU_PARENTS_SET(cif0_out_parents),
1751 };
1752
1753 static struct clk pclkin_cif0 = {
1754         .name           = "pclkin_cif0",
1755         .mode           = gate_mode,
1756         .gate_idx       = CLK_GATE_PCLKIN_CIF0,
1757 };
1758
1759 static struct clk inv_cif0 = {
1760         .name           = "inv_cif0",
1761         .parent         = &pclkin_cif0,
1762 };
1763
1764 static struct clk *cif0_in_parents[2] = {&pclkin_cif0, &inv_cif0};
1765 static struct clk cif0_in = {
1766         .name           = "cif0_in",
1767         .parent         = &pclkin_cif0,
1768         .clksel_con     = CRU_CLKSELS_CON(30),
1769         CRU_SRC_SET(0x1, 8),
1770         CRU_PARENTS_SET(cif0_in_parents),
1771 };
1772
1773 /* i2s/spdif setting */
1774 static struct clk *clk_i2s_div_parents[] = {&general_pll_clk, &codec_pll_clk};
1775 static struct clk clk_i2s_pll = {
1776         .name           = "i2s_pll",
1777         .parent         = &general_pll_clk,
1778         .clksel_con     = CRU_CLKSELS_CON(2),
1779         CRU_SRC_SET(0x1, 15),
1780         CRU_PARENTS_SET(clk_i2s_div_parents),
1781 };
1782
1783 static struct clk clk_i2s0_div = {
1784         .name           = "i2s0_div",
1785         .parent         = &clk_i2s_pll,
1786         .mode           = gate_mode,
1787         .recalc         = clksel_recalc_div,
1788         .set_rate       = clksel_set_rate_freediv,
1789         .round_rate     = clksel_freediv_round_rate,
1790         .gate_idx       = CLK_GATE_I2S0_SRC,
1791         .clksel_con     = CRU_CLKSELS_CON(3),
1792         CRU_DIV_SET(0x7f, 0, 64),
1793 };
1794
1795 static struct clk clk_spdif_div = {
1796         .name           = "spdif_div",
1797         .parent         = &clk_i2s_pll,
1798         .recalc         = clksel_recalc_div,
1799         .set_rate       = clksel_set_rate_freediv,
1800         .round_rate     = clksel_freediv_round_rate,
1801         .mode           = gate_mode,
1802         .gate_idx       = CLK_GATE_SPDIF_SRC,
1803         .clksel_con     = CRU_CLKSELS_CON(5),
1804         CRU_DIV_SET(0x7f, 0, 64),
1805 };
1806 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1807 {
1808         u32 numerator, denominator;
1809         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1810         //clk->parent->parent
1811         if(frac_div_get_seting(rate, clk->parent->parent->rate,
1812                                 &numerator, &denominator) == 0) {
1813                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
1814                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1815                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
1816         } else {
1817                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
1818                 return -ENOENT;
1819         }
1820         return 0;
1821 }
1822
1823 static struct clk clk_i2s0_frac_div = {
1824         .name           = "i2s0_frac_div",
1825         .parent         = &clk_i2s0_div,
1826         .mode           = gate_mode,
1827         .gate_idx       = CLK_GATE_I2S0_FRAC,
1828         .recalc         = clksel_recalc_frac,
1829         .set_rate       = clk_i2s_fracdiv_set_rate,
1830         .clksel_con     = CRU_CLKSELS_CON(7),
1831 };
1832
1833 static struct clk clk_spdif_frac_div = {
1834         .name           = "spdif_frac_div",
1835         .parent         = &clk_spdif_div,
1836         .mode           = gate_mode,
1837         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1838         .recalc         = clksel_recalc_frac,
1839         .set_rate       = clk_i2s_fracdiv_set_rate,
1840         .clksel_con     = CRU_CLKSELS_CON(9),
1841 };
1842
1843 #define I2S_SRC_DIV     (0x0)
1844 #define I2S_SRC_FRAC    (0x1)
1845 #define I2S_SRC_12M     (0x2)
1846
1847 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1848 {
1849         int ret = -EINVAL;
1850         struct clk *parent;
1851
1852         if (rate == clk->parents[I2S_SRC_12M]->rate) {
1853                 parent = clk->parents[I2S_SRC_12M];
1854         } else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV], rate) == rate) {
1855                 parent = clk->parents[I2S_SRC_DIV];
1856         } else {
1857                 parent = clk->parents[I2S_SRC_FRAC];
1858         }
1859
1860         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
1861                         clk->name, rate, parent->name, clk->parent->name);
1862
1863         if(parent != clk->parents[I2S_SRC_12M]) {
1864                 ret = clk_set_rate_nolock(parent, rate); //div 1:1
1865                 if (ret) {
1866                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
1867                         return ret;
1868                 }
1869         }
1870
1871         if (clk->parent != parent) {
1872                 ret = clk_set_parent_nolock(clk, parent);
1873                 if (ret) {
1874                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
1875                         return ret;
1876                 }
1877         }
1878
1879         return ret;
1880 };
1881
1882 static struct clk *clk_i2s0_parents[3] = {&clk_i2s0_div, &clk_i2s0_frac_div, &clk_12m};
1883
1884 static struct clk clk_i2s0 = {
1885         .name           = "i2s0",
1886         .set_rate       = i2s_set_rate,
1887         .clksel_con     = CRU_CLKSELS_CON(3),
1888         CRU_SRC_SET(0x3, 8),
1889         CRU_PARENTS_SET(clk_i2s0_parents),
1890 };
1891
1892 static struct clk *clk_spdif_parents[3] = {&clk_spdif_div, &clk_spdif_frac_div, &clk_12m};
1893
1894 static struct clk clk_spdif = {
1895         .name           = "spdif",
1896         .parent         = &clk_spdif_frac_div,
1897         .set_rate       = i2s_set_rate,
1898         .clksel_con = CRU_CLKSELS_CON(5),
1899         CRU_SRC_SET(0x3, 8),
1900         CRU_PARENTS_SET(clk_spdif_parents),
1901 };
1902
1903 /* otgphy setting */
1904 GATE_CLK(otgphy0, xin24m, OTGPHY0);
1905 GATE_CLK(otgphy1, xin24m, OTGPHY1);
1906
1907 static struct clk clk_otgphy0_480m = {
1908         .name           = "otgphy0_480m",
1909         .parent         = &clk_otgphy0,
1910 };
1911 static struct clk clk_otgphy1_480m = {
1912         .name           = "otgphy1_480m",
1913         .parent         = &clk_otgphy1,
1914 };
1915
1916 /* hsicphy setting */
1917 #ifdef ARCH_RK31
1918 static struct clk *clk_hsicphy_parents[4] = {&clk_otgphy0_480m, &clk_otgphy1_480m, &general_pll_clk, &codec_pll_clk};
1919 static struct clk clk_hsicphy_480m = {
1920         .name           = "hsicphy_480m",
1921         .parent         = &clk_otgphy0_480m,
1922         .clksel_con      = CRU_CLKSELS_CON(30),
1923         CRU_SRC_SET(0x3, 0),
1924         CRU_PARENTS_SET(clk_hsicphy_parents),
1925 };
1926 static struct clk clk_hsicphy_12m = {
1927         .name           = "hsicphy_12m",
1928         .parent         = &clk_hsicphy_480m,
1929         .clksel_con     = CRU_CLKSELS_CON(11),
1930         CRU_DIV_SET(0x3f, 8, 64),
1931 };
1932 #endif
1933
1934 /* mac and rmii setting */
1935 // FIXME
1936 static struct clk rmii_clkin = {
1937         .name           = "rmii_clkin",
1938 };
1939 static struct clk *clk_mac_ref_div_parents[2] = {&general_pll_clk, &ddr_pll_clk};
1940 static struct clk clk_mac_pll_div = {
1941         .name           = "mac_pll_div",
1942         .parent         = &general_pll_clk,
1943         .mode           = gate_mode,
1944         .gate_idx       = CLK_GATE_MAC_SRC,
1945         .recalc         = clksel_recalc_div,
1946         .set_rate       = clksel_set_rate_freediv,
1947         .clksel_con     = CRU_CLKSELS_CON(21),
1948         CRU_DIV_SET(0x1f, 8, 32),
1949         CRU_SRC_SET(0x1, 0),
1950         CRU_PARENTS_SET(clk_mac_ref_div_parents),
1951 };
1952
1953 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
1954 {
1955         if(clk->parent == clk->parents[1]) {
1956                 CLKDATA_DBG("mac_ref clk is form mii clkin,can't set it\n" );
1957                 return -ENOENT;
1958         } else if(clk->parent == clk->parents[0]) {
1959                 return clk_set_rate_nolock(clk->parents[0], rate);
1960         }
1961         return -ENOENT;
1962 }
1963
1964 static struct clk *clk_mac_ref_parents[2] = {&clk_mac_pll_div, &rmii_clkin};
1965
1966 static struct clk clk_mac_ref = {
1967         .name           = "mac_ref",
1968         .parent         = &clk_mac_pll_div,
1969         .set_rate       = clksel_mac_ref_set_rate,
1970         .clksel_con     = CRU_CLKSELS_CON(21),
1971         CRU_SRC_SET(0x1, 4),
1972         CRU_PARENTS_SET(clk_mac_ref_parents),
1973 };
1974
1975 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
1976 {
1977         return clk_set_parent_nolock(clk->parent, parent);
1978 }
1979
1980 static struct clk clk_mii_tx = {
1981         .name           = "mii_tx",
1982         .parent         = &clk_mac_ref,
1983         //.set_parent   = clk_set_mii_tx_parent,
1984         .mode           = gate_mode,
1985         .gate_idx       = CLK_GATE_MAC_LBTEST,
1986 };
1987
1988 /* hsadc and saradc */
1989 static struct clk *clk_hsadc_pll_parents[2] = {&general_pll_clk, &codec_pll_clk};
1990 static struct clk clk_hsadc_pll_div = {
1991         .name           = "hsadc_pll_div",
1992         .parent         = &general_pll_clk,
1993         .mode           = gate_mode,
1994         .gate_idx       = CLK_GATE_HSADC_SRC,
1995         .recalc         = clksel_recalc_div,
1996         .round_rate     = clk_freediv_round_autosel_parents_rate,
1997         .set_rate       = clkset_rate_freediv_autosel_parents,
1998         //.round_rate   = clksel_freediv_round_rate,
1999         //.set_rate     = clksel_set_rate_freediv,
2000         .clksel_con = CRU_CLKSELS_CON(22),
2001         CRU_DIV_SET(0xff, 8, 256),
2002         CRU_SRC_SET(0x1, 0),
2003         CRU_PARENTS_SET(clk_hsadc_pll_parents),
2004 };
2005 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
2006 {
2007         u32 numerator, denominator;
2008         //        clk_hsadc_pll_div->gpll/cpll
2009         //clk->parent->parent
2010         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2011                                 &numerator, &denominator) == 0) {
2012                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2013
2014                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2015
2016                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2017         } else {
2018                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2019                 return -ENOENT;
2020         }
2021         return 0;
2022 }
2023 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
2024 {
2025         u32 numerator, denominator;
2026         u32 i, ret = 0;
2027         //        clk_hsadc_pll_div->gpll/cpll
2028         //clk->parent->parent
2029         for(i = 0; i < 2; i++) {
2030                 if(frac_div_get_seting(rate, clk->parent->parents[i]->rate,
2031                                         &numerator, &denominator) == 0)
2032                         break;
2033         }
2034         if(i >= 2)
2035                 return -ENOENT;
2036
2037         if(clk->parent->parent != clk->parent->parents[i])
2038                 ret = clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
2039         if(ret == 0) {
2040                 clk_set_rate_nolock(clk->parent, clk->parent->parents[i]->rate); //PLL:DIV 1:
2041
2042                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2043
2044                 CLKDATA_DBG("clk_frac_div %s, rate=%lu\n", clk->name, rate);
2045         } else {
2046                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2047                 return -ENOENT;
2048         }
2049         return 0;
2050 }
2051
2052 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2053 {
2054         u32 numerator, denominator;
2055
2056         CLKDATA_ERR("clk_hsadc_fracdiv_round_rate\n");
2057         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2058                                 &numerator, &denominator) == 0)
2059                 return rate;
2060
2061         return 0;
2062 }
2063 static struct clk clk_hsadc_frac_div = {
2064         .name           = "hsadc_frac_div",
2065         .parent         = &clk_hsadc_pll_div,
2066         .mode           = gate_mode,
2067         .recalc         = clksel_recalc_frac,
2068         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
2069         .round_rate     = clk_hsadc_fracdiv_round_rate,
2070         .gate_idx       = CLK_GATE_HSADC_FRAC_SRC,
2071         .clksel_con     = CRU_CLKSELS_CON(23),
2072 };
2073
2074 #define HSADC_SRC_DIV 0x0
2075 #define HSADC_SRC_FRAC 0x1
2076 #define HSADC_SRC_EXT 0x2
2077 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2078 {
2079         int ret = -EINVAL;
2080         struct clk *parent;
2081
2082         if(clk->parent == clk->parents[HSADC_SRC_EXT]) {
2083                 CLKDATA_DBG("hsadc clk is form ext\n");
2084                 return 0;
2085         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV], rate) == rate) {
2086                 parent = clk->parents[HSADC_SRC_DIV];
2087         } else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC], rate) == rate) {
2088                 parent = clk->parents[HSADC_SRC_FRAC];
2089         } else
2090                 parent = clk->parents[HSADC_SRC_DIV];
2091
2092         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2093                         clk->name, rate, parent->name, clk->parent->name);
2094
2095         ret = clk_set_rate_nolock(parent, rate);
2096         if (ret) {
2097                 CLKDATA_ERR("%s set rate%lu err\n", clk->name, rate);
2098                 return ret;
2099         }
2100         if (clk->parent != parent) {
2101                 ret = clk_set_parent_nolock(clk, parent);
2102                 if (ret) {
2103                         CLKDATA_ERR("%s can't get rate%lu,reparent err\n", clk->name, rate);
2104                         return ret;
2105                 }
2106         }
2107         return ret;
2108 }
2109
2110 static struct clk clk_hsadc_ext = {
2111         .name           = "hsadc_ext",
2112 };
2113
2114 static struct clk *clk_hsadc_out_parents[3] = {&clk_hsadc_pll_div, &clk_hsadc_frac_div, &clk_hsadc_ext};
2115 static struct clk clk_hsadc_out = {
2116         .name           = "hsadc_out",
2117         .parent         = &clk_hsadc_pll_div,
2118         .set_rate       = clk_hsadc_set_rate,
2119         .clksel_con     = CRU_CLKSELS_CON(22),
2120         CRU_SRC_SET(0x3, 4),
2121         CRU_PARENTS_SET(clk_hsadc_out_parents),
2122 };
2123 static struct clk clk_hsadc_out_inv = {
2124         .name           = "hsadc_out_inv",
2125         .parent         = &clk_hsadc_pll_div,
2126 };
2127
2128 static struct clk *clk_hsadc_parents[3] = {&clk_hsadc_out, &clk_hsadc_out_inv};
2129 static struct clk clk_hsadc = {
2130         .name           = "hsadc",
2131         .parent         = &clk_hsadc_out,
2132         .clksel_con     = CRU_CLKSELS_CON(22),
2133         CRU_SRC_SET(0x1, 7),
2134         CRU_PARENTS_SET(clk_hsadc_parents),
2135 };
2136
2137 static struct clk clk_saradc = {
2138         .name           = "saradc",
2139         .parent         = &xin24m,
2140         .mode           = gate_mode,
2141         .recalc         = clksel_recalc_div,
2142         .set_rate       = clksel_set_rate_freediv,
2143         .gate_idx       = CLK_GATE_SARADC_SRC,
2144         .clksel_con     = CRU_CLKSELS_CON(24),
2145         CRU_DIV_SET(0xff, 8, 256),
2146 };
2147
2148 /* smc setting */
2149 GATE_CLK(smc, hclk_periph, SMC_SRC);//smc
2150 static struct clk clkn_smc = {
2151         .name           = "smc_inv",
2152         .parent         = &clk_smc,
2153 };
2154
2155 /* spi setting */
2156 static struct clk clk_spi0 = {
2157         .name           = "spi0",
2158         .parent         = &pclk_periph,
2159         .mode           = gate_mode,
2160         .recalc         = clksel_recalc_div,
2161         .set_rate       = clksel_set_rate_freediv,
2162         .gate_idx       = CLK_GATE_SPI0_SRC,
2163         .clksel_con     = CRU_CLKSELS_CON(25),
2164         CRU_DIV_SET(0x7f, 0, 128),
2165 };
2166
2167 static struct clk clk_spi1 = {
2168         .name           = "spi1",
2169         .parent         = &pclk_periph,
2170         .mode           = gate_mode,
2171         .recalc         = clksel_recalc_div,
2172         .set_rate       = clksel_set_rate_freediv,
2173         .gate_idx       = CLK_GATE_SPI1_SRC,
2174         .clksel_con     = CRU_CLKSELS_CON(25),
2175         CRU_DIV_SET(0x7f, 8, 128),
2176 };
2177
2178 /* sdmmc/sdio/emmc setting */
2179 static struct clk clk_sdmmc = {
2180         .name           = "sdmmc",
2181         .parent         = &hclk_periph,
2182         .mode           = gate_mode,
2183         .recalc         = clksel_recalc_div,
2184         .set_rate       = clksel_set_rate_even,
2185         .gate_idx       = CLK_GATE_MMC0_SRC,
2186         .clksel_con     = CRU_CLKSELS_CON(11),
2187         CRU_DIV_SET(0x3f, 0, 64),
2188 };
2189
2190 static struct clk clk_sdio = {
2191         .name           = "sdio",
2192         .parent         = &hclk_periph,
2193         .mode           = gate_mode,
2194         .recalc         = clksel_recalc_div,
2195         .set_rate       = clksel_set_rate_even,
2196         .gate_idx       = CLK_GATE_SDIO_SRC,
2197         .clksel_con     = CRU_CLKSELS_CON(12),
2198         CRU_DIV_SET(0x3f, 0, 64),
2199
2200 };
2201
2202 static struct clk clk_emmc = {
2203         .name           = "emmc",
2204         .parent         = &hclk_periph,
2205         .mode           = gate_mode,
2206         .recalc         = clksel_recalc_div,
2207         .set_rate       = clksel_set_rate_freediv,
2208         .gate_idx       = CLK_GATE_EMMC_SRC,
2209         .clksel_con     = CRU_CLKSELS_CON(12),
2210         CRU_DIV_SET(0x3f, 8, 64),
2211 };
2212
2213 /* uart setting */
2214 static struct clk *clk_uart_src_parents[2] = {&general_pll_clk, &codec_pll_clk};
2215 static struct clk clk_uart_pll = {
2216         .name           = "uart_pll",
2217         .parent         = &general_pll_clk,
2218         .clksel_con     = CRU_CLKSELS_CON(12),
2219         CRU_SRC_SET(0x1, 15),
2220         CRU_PARENTS_SET(clk_uart_src_parents),
2221 };
2222 static struct clk clk_uart0_div = {
2223         .name           = "uart0_div",
2224         .parent         = &clk_uart_pll,
2225         .mode           = gate_mode,
2226         .gate_idx       = CLK_GATE_UART0_SRC,
2227         .recalc         = clksel_recalc_div,
2228         .set_rate       = clksel_set_rate_freediv,
2229         .round_rate     = clksel_freediv_round_rate,
2230         .clksel_con     = CRU_CLKSELS_CON(13),
2231         CRU_DIV_SET(0x7f, 0, 64),
2232 };
2233 static struct clk clk_uart1_div = {
2234         .name           = "uart1_div",
2235         .parent         = &clk_uart_pll,
2236         .mode           = gate_mode,
2237         .gate_idx       = CLK_GATE_UART1_SRC,
2238         .recalc         = clksel_recalc_div,
2239         .round_rate     = clksel_freediv_round_rate,
2240         .set_rate       = clksel_set_rate_freediv,
2241         .clksel_con     = CRU_CLKSELS_CON(14),
2242         CRU_DIV_SET(0x7f, 0, 64),
2243 };
2244
2245 static struct clk clk_uart2_div = {
2246         .name           = "uart2_div",
2247         .parent         = &clk_uart_pll,
2248         .mode           = gate_mode,
2249         .gate_idx       = CLK_GATE_UART2_SRC,
2250         .recalc         = clksel_recalc_div,
2251         .round_rate     = clksel_freediv_round_rate,
2252         .set_rate       = clksel_set_rate_freediv,
2253         .clksel_con     = CRU_CLKSELS_CON(15),
2254         CRU_DIV_SET(0x7f, 0, 64),
2255 };
2256
2257 static struct clk clk_uart3_div = {
2258         .name           = "uart3_div",
2259         .parent         = &clk_uart_pll,
2260         .mode           = gate_mode,
2261         .gate_idx       = CLK_GATE_UART3_SRC,
2262         .recalc         = clksel_recalc_div,
2263         .round_rate     = clksel_freediv_round_rate,
2264         .set_rate       = clksel_set_rate_freediv,
2265         .clksel_con     = CRU_CLKSELS_CON(16),
2266         CRU_DIV_SET(0x7f, 0, 64),
2267 };
2268 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
2269 {
2270         u32 numerator, denominator;
2271         //clk_uart0_div->clk_uart_pll->gpll/cpll
2272         //clk->parent->parent
2273         if(frac_div_get_seting(rate, clk->parent->parent->rate,
2274                                 &numerator, &denominator) == 0) {
2275                 clk_set_rate_nolock(clk->parent, clk->parent->parent->rate); //PLL:DIV 1:
2276
2277                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2278
2279                 CLKDATA_DBG("%s set rate=%lu,is ok\n", clk->name, rate);
2280         } else {
2281                 CLKDATA_ERR("clk_frac_div can't get rate=%lu,%s\n", rate, clk->name);
2282                 return -ENOENT;
2283         }
2284         return 0;
2285 }
2286
2287 static struct clk clk_uart0_frac_div = {
2288         .name           = "uart0_frac_div",
2289         .parent         = &clk_uart0_div,
2290         .mode           = gate_mode,
2291         .recalc         = clksel_recalc_frac,
2292         .set_rate       = clk_uart_fracdiv_set_rate,
2293         .gate_idx       = CLK_GATE_UART0_FRAC_SRC,
2294         .clksel_con     = CRU_CLKSELS_CON(17),
2295 };
2296 static struct clk clk_uart1_frac_div = {
2297         .name           = "uart1_frac_div",
2298         .parent         = &clk_uart1_div,
2299         .mode           = gate_mode,
2300         .recalc         = clksel_recalc_frac,
2301         .set_rate       = clk_uart_fracdiv_set_rate,
2302         .gate_idx       = CLK_GATE_UART1_FRAC_SRC,
2303         .clksel_con     = CRU_CLKSELS_CON(18),
2304 };
2305 static struct clk clk_uart2_frac_div = {
2306         .name           = "uart2_frac_div",
2307         .mode           = gate_mode,
2308         .parent         = &clk_uart2_div,
2309         .recalc         = clksel_recalc_frac,
2310         .set_rate       = clk_uart_fracdiv_set_rate,
2311         .gate_idx       = CLK_GATE_UART2_FRAC_SRC,
2312         .clksel_con     = CRU_CLKSELS_CON(19),
2313 };
2314 static struct clk clk_uart3_frac_div = {
2315         .name           = "uart3_frac_div",
2316         .parent         = &clk_uart3_div,
2317         .mode           = gate_mode,
2318         .recalc         = clksel_recalc_frac,
2319         .set_rate       = clk_uart_fracdiv_set_rate,
2320         .gate_idx       = CLK_GATE_UART3_FRAC_SRC,
2321         .clksel_con     = CRU_CLKSELS_CON(20),
2322 };
2323
2324 #define UART_SRC_DIV 0
2325 #define UART_SRC_FRAC 1
2326 #define UART_SRC_24M 2
2327
2328 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
2329 {
2330         int ret = 0;
2331         struct clk *parent;
2332
2333         if(rate == clk->parents[UART_SRC_24M]->rate) { //24m
2334                 parent = clk->parents[UART_SRC_24M];
2335         } else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate) == rate) {
2336                 parent = clk->parents[UART_SRC_DIV];
2337         } else {
2338                 parent = clk->parents[UART_SRC_FRAC];
2339         }
2340
2341         CLKDATA_DBG(" %s set rate=%lu parent %s(old %s)\n",
2342                         clk->name, rate, parent->name, clk->parent->name);
2343
2344         if(parent != clk->parents[UART_SRC_24M]) {
2345                 ret = clk_set_rate_nolock(parent, rate);
2346                 if (ret) {
2347                         CLKDATA_DBG("%s set rate%lu err\n", clk->name, rate);
2348                         return ret;
2349                 }
2350         }
2351
2352         if (clk->parent != parent) {
2353                 ret = clk_set_parent_nolock(clk, parent);
2354                 if (ret) {
2355                         CLKDATA_DBG("%s can't get rate%lu,reparent err\n", clk->name, rate);
2356                         return ret;
2357                 }
2358         }
2359
2360         return ret;
2361 }
2362
2363 static struct clk *clk_uart0_parents[3] = {&clk_uart0_div, &clk_uart0_frac_div, &xin24m};
2364 static struct clk clk_uart0 = {
2365         .name           = "uart0",
2366         .set_rate       = clk_uart_set_rate,
2367         .clksel_con     = CRU_CLKSELS_CON(13),
2368         CRU_SRC_SET(0x3, 8),
2369         CRU_PARENTS_SET(clk_uart0_parents),
2370 };
2371
2372 static struct clk *clk_uart1_parents[3] = {&clk_uart1_div, &clk_uart1_frac_div, &xin24m};
2373 static struct clk clk_uart1 = {
2374         .name           = "uart1",
2375         .set_rate       = clk_uart_set_rate,
2376         .clksel_con     = CRU_CLKSELS_CON(14),
2377         CRU_SRC_SET(0x3, 8),
2378         CRU_PARENTS_SET(clk_uart1_parents),
2379 };
2380
2381 static struct clk *clk_uart2_parents[3] = {&clk_uart2_div, &clk_uart2_frac_div, &xin24m};
2382 static struct clk clk_uart2 = {
2383         .name           = "uart2",
2384         .set_rate       = clk_uart_set_rate,
2385         .clksel_con     = CRU_CLKSELS_CON(15),
2386         CRU_SRC_SET(0x3, 8),
2387         CRU_PARENTS_SET(clk_uart2_parents),
2388 };
2389 static struct clk *clk_uart3_parents[3] = {&clk_uart3_div, &clk_uart3_frac_div, &xin24m};
2390 static struct clk clk_uart3 = {
2391         .name           = "uart3",
2392         .set_rate       = clk_uart_set_rate,
2393         .clksel_con     = CRU_CLKSELS_CON(16),
2394         CRU_SRC_SET(0x3, 8),
2395         CRU_PARENTS_SET(clk_uart3_parents),
2396 };
2397
2398 /* timer setting */
2399 GATE_CLK(timer0, xin24m, TIMER0);
2400 GATE_CLK(timer1, xin24m, TIMER1);
2401 GATE_CLK(timer2, xin24m, TIMER2);
2402
2403 /*********************power domain*******************************/
2404 #if 1
2405 #ifdef RK30_CLK_OFFBOARD_TEST
2406 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on) {};
2407 #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2408 #else
2409 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2410 #define _pmu_set_power_domain pmu_set_power_domain
2411 #endif
2412
2413 static int pd_video_mode(struct clk *clk, int on)
2414 {
2415         u32 gate[3];
2416         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2417         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2418         //gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2419         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2420         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2421         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2422         pmu_set_power_domain(PD_VIDEO, on);
2423         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2424         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2425         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2426         return 0;
2427 }
2428
2429 static struct clk pd_video = {
2430         .name   = "pd_video",
2431         .flags  = IS_PD,
2432         .mode   = pd_video_mode,
2433         .gate_idx       = PD_VIDEO,
2434 };
2435 static int pd_display_mode(struct clk *clk, int on)
2436 {
2437         u32 gate[10];
2438         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2439         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2440         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2441         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2442         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2443         //gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2444         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2445         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2446         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2447         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2448         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2449         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2450         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2451         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2452         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2453         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2454         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2455         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2456         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2457         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2458         pmu_set_power_domain(PD_VIO, on);
2459         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2460         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2461         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2462         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2463         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2464         //cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2465         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2466         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2467         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2468         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2469         return 0;
2470 }
2471
2472 static struct clk pd_display = {
2473         .name   = "pd_vio",
2474         .flags  = IS_PD,
2475         .mode   = pd_display_mode,
2476         .gate_idx       = PD_VIO,
2477 };
2478 static struct clk pd_lcdc0 = {
2479         .parent = &pd_display,
2480         .name   = "pd_lcdc0",
2481 };
2482 static struct clk pd_lcdc1 = {
2483         .parent = &pd_display,
2484         .name   = "pd_lcdc1",
2485 };
2486 static struct clk pd_cif0 = {
2487         .parent = &pd_display,
2488         .name   = "pd_cif0",
2489 };
2490 static struct clk pd_rga = {
2491         .parent = &pd_display,
2492         .name   = "pd_rga",
2493 };
2494 static struct clk pd_ipp = {
2495         .parent = &pd_display,
2496         .name   = "pd_ipp",
2497 };
2498 static struct clk pd_hdmi = {
2499         .parent = &pd_display,
2500         .name   = "pd_hdmi",
2501 };
2502
2503
2504 static int pd_gpu_mode(struct clk *clk, int on)
2505 {
2506         u32 gate[3];
2507         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
2508         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
2509         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
2510         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
2511         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_SLV), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
2512         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_MST), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
2513         pmu_set_power_domain(PD_GPU, on);
2514         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CLK_GPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_CLK_GPU));
2515         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_SLV) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_SLV));
2516         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU_MST) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU_MST));
2517         return 0;
2518 }
2519
2520 static struct clk pd_gpu = {
2521         .name   = "pd_gpu",
2522         .flags  = IS_PD,
2523         .mode   = pd_gpu_mode,
2524         .gate_idx       = PD_GPU,
2525 };
2526
2527 static int pm_off_mode(struct clk *clk, int on)
2528 {
2529         _pmu_set_power_domain(clk->gate_idx, on); //on 1
2530         return 0;
2531 }
2532 static struct clk pd_peri = {
2533         .name   = "pd_peri",
2534         .flags  = IS_PD,
2535         .mode   = pm_off_mode,
2536         .gate_idx       = PD_PERI,
2537 };
2538
2539
2540 #define PD_CLK(name) \
2541 {\
2542         .dev_id = NULL,\
2543         .con_id = #name,\
2544         .clk = &name,\
2545 }
2546
2547 #endif
2548 /************************rk30 fixed div clock****************************************/
2549
2550 /*************************aclk_cpu***********************/
2551
2552 GATE_CLK(dma1,          aclk_cpu,       ACLK_DMAC1);
2553 GATE_CLK(l2mem_con,     aclk_cpu,       ACLK_L2MEM_CON);
2554 GATE_CLK(intmem,        aclk_cpu,       ACLK_INTMEM);
2555 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2556
2557 /*************************hclk_cpu***********************/
2558
2559 GATE_CLK(rom,           hclk_cpu,       HCLK_ROM);
2560 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2561 GATE_CLK(hclk_spdif,    hclk_cpu,       HCLK_SPDIF);
2562 GATE_CLK(hclk_cpubus,   hclk_cpu,       HCLK_CPUBUS);
2563 GATE_CLK(hclk_ahb2apb,  hclk_cpu,       HCLK_AHB2APB);
2564 GATE_CLK(hclk_vio_bus,  hclk_cpu,       HCLK_VIO_BUS);
2565 GATE_CLK(hclk_lcdc0,    hclk_cpu,       HCLK_LCDC0);
2566 GATE_CLK(hclk_lcdc1,    hclk_cpu,       HCLK_LCDC1);
2567 GATE_CLK(hclk_cif0,     hclk_cpu,       HCLK_CIF0);
2568 GATE_CLK(hclk_ipp,      hclk_cpu,       HCLK_IPP);
2569 GATE_CLK(hclk_rga,      hclk_cpu,       HCLK_RGA);
2570 GATE_CLK(hclk_l2mem,    hclk_cpu,       HCLK_L2MEM);
2571 GATE_CLK(hclk_video_h2h, hclk_cpu,      HCLK_VIDEO_H2H);
2572 /*************************pclk_cpu***********************/
2573 GATE_CLK(pwm01,         pclk_cpu,       PCLK_PWM01);//pwm 0¡¢1
2574 GATE_CLK(pclk_timer0,   pclk_cpu,       PCLK_TIMER0);
2575 GATE_CLK(pclk_timer1,   pclk_cpu,       PCLK_TIMER1);
2576 GATE_CLK(pclk_timer2,   pclk_cpu,       PCLK_TIMER2);
2577 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2578 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2579 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2580 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2581 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2582 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2583 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2584 GATE_CLK(pclk_uart0,    pclk_cpu, PCLK_UART0);
2585 GATE_CLK(pclk_uart1,    pclk_cpu, PCLK_UART1);
2586 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2587 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2588 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2589 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2590 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2591
2592 /*************************aclk_periph***********************/
2593
2594 GATE_CLK(dma2, aclk_periph, ACLK_DMAC2);
2595 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2596 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2597 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2598 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2599
2600 /*************************hclk_periph***********************/
2601 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2602 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2603 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2604 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2605 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2606 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2607 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2608 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2609 GATE_CLK(hclk_hsic, hclk_periph, HCLK_HSIC);
2610 GATE_CLK(hclk_gps, hclk_periph, HCLK_GPS);
2611 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2612 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2613 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2614 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2615 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2616 /*************************pclk_periph***********************/
2617 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2618 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2619 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2620 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2621 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2622 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2623 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2624 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2625 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2626 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2627 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2628 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2629 /*************************aclk_lcdc0***********************/
2630
2631 GATE_CLK(aclk_vio0, aclk_lcdc0_pre, ACLK_VIO0);
2632
2633 GATE_CLK(aclk_lcdc0, clk_aclk_vio0, ACLK_LCDC0);
2634 GATE_CLK(aclk_cif0, clk_aclk_vio0, ACLK_CIF0);
2635 GATE_CLK(aclk_ipp,  clk_aclk_vio0, ACLK_IPP);
2636
2637 /*************************aclk_lcdc0***********************/
2638
2639 GATE_CLK(aclk_vio1, aclk_lcdc1_pre, ACLK_VIO1);
2640 GATE_CLK(aclk_lcdc1, clk_aclk_vio1, ACLK_LCDC1);
2641 GATE_CLK(aclk_rga,  clk_aclk_vio1, ACLK_RGA);
2642
2643
2644 #if 1
2645 #define CLK(dev, con, ck) \
2646 {\
2647         .dev_id = dev,\
2648         .con_id = con,\
2649         .clk = ck,\
2650 }
2651
2652
2653 #define CLK1(name) \
2654 {\
2655         .dev_id = NULL,\
2656         .con_id = #name,\
2657         .clk = &clk_##name,\
2658 }
2659
2660 #endif
2661
2662 static struct clk_lookup clks[] = {
2663         CLK(NULL, "xin24m", &xin24m),
2664         //CLK(NULL, "xin27m", &xin27m),
2665         CLK(NULL, "xin12m", &clk_12m),
2666         CLK(NULL, "arm_pll", &arm_pll_clk),
2667         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2668         CLK(NULL, "codec_pll", &codec_pll_clk),
2669         CLK(NULL, "general_pll", &general_pll_clk),
2670
2671         CLK(NULL, "ddr", &clk_ddr),
2672         CLK(NULL, "cpu", &clk_core),
2673         CLK(NULL, "logic", &clk_cpu_div),
2674         CLK(NULL, "arm_gpll", &clk_core_gpll_path),
2675         CLK1(l2c),
2676         CLK1(core_dbg),
2677         CLK("smp_twd", NULL, &core_periph),
2678         CLK(NULL, "aclk_core", &aclk_core),
2679         CLK(NULL, "aclk_cpu", &aclk_cpu),
2680         CLK(NULL, "pclk_cpu", &pclk_cpu),
2681         CLK(NULL, "atclk_cpu", &atclk_cpu),
2682         CLK(NULL, "hclk_cpu", &hclk_cpu),
2683         CLK(NULL, "ahb2apb_cpu", &ahb2apb_cpu),
2684
2685         CLK1(gpu),
2686         #ifdef GPU_CORE_ACLK_CTR_TOGETHER
2687         CLK(NULL, "aclk_gpu_real",&aclk_gpu),
2688         CLK(NULL, "aclk_gpu",     &aclk_gpu_null),
2689         #else
2690         CLK(NULL, "aclk_gpu",   &aclk_gpu),
2691         #endif
2692         CLK(NULL, "gpu_slv",    &aclk_gpu_slv),
2693         CLK(NULL, "gpu_mst",    &aclk_gpu_mst),
2694
2695         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2696         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2697         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2698         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2699
2700         CLK(NULL, "aclk_lcdc0_pre", &aclk_lcdc0_pre),
2701         CLK(NULL, "aclk_lcdc1_pre", &aclk_lcdc1_pre),
2702
2703         CLK(NULL, "aclk_periph", &aclk_periph),
2704         CLK(NULL, "pclk_periph", &pclk_periph),
2705         CLK(NULL, "hclk_periph", &hclk_periph),
2706
2707         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2708         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2709
2710         CLK(NULL, "cif_out_pll", &cif_out_pll),
2711         CLK(NULL, "cif0_out_div", &cif0_out_div),
2712
2713         CLK(NULL, "cif0_out", &cif0_out),
2714         CLK(NULL, "pclkin_cif0", &pclkin_cif0),
2715         CLK(NULL, "inv_cif0", &inv_cif0),
2716         CLK(NULL, "cif0_in", &cif0_in),
2717
2718         CLK1(i2s_pll),
2719         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2720         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2721         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2722
2723         // actually no i2s1
2724         CLK("rk29_i2s.1", "i2s_div", &clk_i2s0_div),
2725         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s0_frac_div),
2726         CLK("rk29_i2s.1", "i2s", &clk_i2s0),
2727
2728
2729         CLK1(spdif_div),
2730         CLK1(spdif_frac_div),
2731         CLK1(spdif),
2732
2733         CLK1(otgphy0),
2734         CLK1(otgphy1),
2735         CLK1(otgphy0_480m),
2736         CLK1(otgphy1_480m),
2737         CLK1(hsicphy_480m),
2738         CLK1(hsicphy_12m),
2739
2740         CLK(NULL, "rmii_clkin", &rmii_clkin),
2741         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2742         CLK1(mac_ref),
2743         CLK1(mii_tx),
2744
2745         CLK1(hsadc_pll_div),
2746         CLK1(hsadc_frac_div),
2747         CLK1(hsadc_ext),
2748         CLK1(hsadc_out),
2749         CLK1(hsadc_out_inv),
2750         CLK1(hsadc),
2751
2752         CLK1(saradc),
2753
2754         CLK1(smc),
2755         CLK(NULL, "smc_inv",    &clkn_smc),
2756
2757         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2758         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2759
2760         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2761         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2762         CLK1(emmc),
2763
2764         CLK1(uart_pll),
2765         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2766         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2767         CLK("rk_serial.0", "uart", &clk_uart0),
2768         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2769         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2770         CLK("rk_serial.1", "uart", &clk_uart1),
2771         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2772         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2773         CLK("rk_serial.2", "uart", &clk_uart2),
2774         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2775         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2776         CLK("rk_serial.3", "uart", &clk_uart3),
2777
2778         CLK1(timer0),
2779         CLK1(timer1),
2780         CLK1(timer2),
2781
2782         /*************************aclk_cpu***********************/
2783         CLK1(dma1),
2784         CLK1(l2mem_con),
2785         CLK1(intmem),
2786         CLK1(aclk_strc_sys),
2787
2788         /*************************hclk_cpu***********************/
2789         CLK1(rom),
2790         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s0_2ch),
2791         // actually no i2s1
2792         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2793         CLK1(hclk_spdif),
2794         CLK1(hclk_cpubus),
2795         CLK1(hclk_ahb2apb),
2796         CLK1(hclk_vio_bus),
2797         CLK1(hclk_lcdc0),
2798         CLK1(hclk_lcdc1),
2799         CLK1(hclk_cif0),
2800         CLK1(hclk_ipp),
2801         CLK1(hclk_rga),
2802         CLK1(hclk_video_h2h),
2803         CLK1(hclk_l2mem),
2804
2805         /*************************pclk_cpu***********************/
2806         CLK1(pwm01),
2807         CLK1(pclk_timer0),
2808         CLK1(pclk_timer1),
2809         CLK1(pclk_timer2),
2810         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2811         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2812         CLK1(gpio0),
2813         CLK1(gpio1),
2814         CLK1(gpio2),
2815         CLK1(efuse),
2816         CLK1(tzpc),
2817         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2818         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2819         CLK1(pclk_ddrupctl),
2820         CLK1(pclk_ddrpubl),
2821         CLK1(dbg),
2822         CLK1(grf),
2823         CLK1(pmu),
2824
2825         /*************************aclk_periph***********************/
2826         CLK1(dma2),
2827         CLK1(aclk_smc),
2828         CLK1(aclk_peri_niu),
2829         CLK1(aclk_cpu_peri),
2830         CLK1(aclk_peri_axi_matrix),
2831
2832         /*************************hclk_periph***********************/
2833         CLK1(hclk_peri_axi_matrix),
2834         CLK1(hclk_peri_ahb_arbi),
2835         CLK1(hclk_emem_peri),
2836         CLK1(hclk_mac),
2837         CLK1(nandc),
2838         CLK1(hclk_usb_peri),
2839         CLK1(hclk_otg0),
2840         CLK1(hclk_otg1),
2841         CLK1(hclk_hsic),
2842         CLK1(hclk_gps),
2843         CLK1(hclk_hsadc),
2844         CLK1(hclk_pidfilter),
2845         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2846         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2847         CLK1(hclk_emmc),
2848
2849         /*************************pclk_periph***********************/
2850         CLK1(pclk_peri_axi_matrix),
2851         CLK1(pwm23),
2852         CLK1(wdt),
2853         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2854         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2855         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2856         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2857         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2858         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2859         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2860         CLK1(gpio3),
2861         CLK1(pclk_saradc),
2862
2863         /*************************aclk_lcdc0***********************/
2864         CLK1(aclk_vio0),
2865         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2866         CLK1(aclk_cif0),
2867         CLK1(aclk_ipp),
2868
2869         /*************************aclk_lcdc1***********************/
2870         CLK1(aclk_vio1),
2871         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2872         CLK1(aclk_rga),
2873         /************************power domain**********************/
2874
2875         PD_CLK(pd_peri),
2876         PD_CLK(pd_display),
2877         PD_CLK(pd_video),
2878         PD_CLK(pd_lcdc0),
2879         PD_CLK(pd_lcdc1),
2880         PD_CLK(pd_cif0),
2881         //PD_CLK(pd_cif1),
2882         PD_CLK(pd_rga),
2883         PD_CLK(pd_ipp),
2884         PD_CLK(pd_video),
2885         PD_CLK(pd_gpu),
2886         //PD_CLK(pd_dbg),
2887 };
2888 static void __init rk30_init_enable_clocks(void)
2889 {
2890         #if 0
2891         //clk_enable_nolock(&xin24m);
2892         //clk_enable_nolock(&clk_12m);
2893         //clk_enable_nolock(&arm_pll_clk);
2894         //clk_enable_nolock(&ddr_pll_clk);
2895         //clk_enable_nolock(&codec_pll_clk);
2896         //clk_enable_nolock(&general_pll_clk);
2897         #endif
2898         clk_enable_nolock(&clk_ddr);
2899         //clk_enable_nolock(&clk_core);
2900         clk_enable_nolock(&clk_cpu_div);
2901         clk_enable_nolock(&clk_core_gpll_path);
2902         clk_enable_nolock(&clk_l2c);
2903         clk_enable_nolock(&clk_core_dbg);
2904         clk_enable_nolock(&core_periph);
2905         clk_enable_nolock(&aclk_core);
2906         //clk_enable_nolock(&aclk_cpu);
2907         //clk_enable_nolock(&pclk_cpu);
2908         clk_enable_nolock(&atclk_cpu);
2909         //clk_enable_nolock(&hclk_cpu);
2910         clk_enable_nolock(&ahb2apb_cpu);
2911         #if 0
2912          clk_enable_nolock(&clk_gpu);
2913          clk_enable_nolock(&aclk_gpu);
2914          clk_enable_nolock(&aclk_gpu_slv);
2915          clk_enable_nolock(&aclk_gpu_mst);
2916
2917          clk_enable_nolock(&aclk_vepu);
2918          clk_enable_nolock(&hclk_vepu);
2919          clk_enable_nolock(&aclk_vdpu);
2920          clk_enable_nolock(&hclk_vdpu);
2921
2922          clk_enable_nolock(&aclk_lcdc0_pre);
2923          clk_enable_nolock(&aclk_lcdc1_pre);
2924
2925          clk_enable_nolock(&aclk_periph);
2926         clk_enable_nolock(&pclk_periph);
2927         clk_enable_nolock(&hclk_periph);
2928         #endif
2929         #if 0
2930          clk_enable_nolock(&dclk_lcdc0);
2931          clk_enable_nolock(&dclk_lcdc1);
2932
2933          clk_enable_nolock(&cif_out_pll);
2934          clk_enable_nolock(&cif0_out_div);
2935
2936          clk_enable_nolock(&cif0_out);
2937          clk_enable_nolock(&pclkin_cif0);
2938          clk_enable_nolock(&inv_cif0);
2939          clk_enable_nolock(&cif0_in);
2940
2941          clk_enable_nolock(&clk_i2s_pll);
2942          clk_enable_nolock(&clk_i2s0_div);
2943          clk_enable_nolock(&clk_i2s0_frac_div);
2944          clk_enable_nolock(&clk_i2s0);
2945
2946           actually no i2s1
2947          clk_enable_nolock(&clk_i2s0_div);
2948          clk_enable_nolock(&clk_i2s0_frac_div);
2949          clk_enable_nolock(&clk_i2s0);
2950
2951         clk_enable_nolock(&clk_spdif_div);
2952         clk_enable_nolock(&clk_spdif_frac_div);
2953         clk_enable_nolock(&clk_spdif);
2954         #endif
2955         #if 0
2956         clk_enable_nolock(&clk_otgphy0);
2957         clk_enable_nolock(&clk_otgphy1);
2958         clk_enable_nolock(&clk_otgphy0_480m);
2959         clk_enable_nolock(&clk_otgphy1_480m);
2960         clk_enable_nolock(&clk_hsicphy_480m);
2961         clk_enable_nolock(&clk_hsicphy_12m);
2962         #endif
2963
2964         #if 0
2965         clk_enable_nolock(&rmii_clkin);
2966         clk_enable_nolock(&clk_mac_pll_div); // compatible with rk29
2967         clk_enable_nolock(&clk_mac_ref);
2968         clk_enable_nolock(&clk_mii_tx);
2969         #endif
2970
2971         #if 0
2972         clk_enable_nolock(&clk_hsadc_pll_div);
2973         clk_enable_nolock(&clk_hsadc_frac_div);
2974         clk_enable_nolock(&clk_hsadc_ext);
2975         clk_enable_nolock(&clk_hsadc_out);
2976         clk_enable_nolock(&clk_hsadc_out_inv);
2977         clk_enable_nolock(&clk_hsadc);
2978
2979         clk_enable_nolock(&clk_saradc);
2980         #endif
2981         /*
2982         clk_enable_nolock(&clk_smc);
2983         clk_enable_nolock(&clkn_smc);
2984         */
2985         /*
2986         clk_enable_nolock(&clk_spi0);
2987         clk_enable_nolock(&clk_spi1);
2988         */
2989         /*
2990         clk_enable_nolock(&clk_sdmmc);
2991         clk_enable_nolock(&clk_sdio);
2992         clk_enable_nolock(&clk_emmc);
2993         */
2994         #if 0
2995         clk_enable_nolock(&clk_uart_pll);
2996         clk_enable_nolock(&clk_uart0_div);
2997         clk_enable_nolock(&clk_uart0_frac_div);
2998         clk_enable_nolock(&clk_uart0);
2999         clk_enable_nolock(&clk_uart1_div);
3000         clk_enable_nolock(&clk_uart1_frac_div);
3001         clk_enable_nolock(&clk_uart1);
3002         clk_enable_nolock(&clk_uart2_div);
3003         clk_enable_nolock(&clk_uart2_frac_div);
3004         clk_enable_nolock(&clk_uart2);
3005         clk_enable_nolock(&clk_uart3_div);
3006         clk_enable_nolock(&clk_uart3_frac_div);
3007         clk_enable_nolock(&clk_uart3);
3008         #endif
3009         #if CONFIG_RK_DEBUG_UART == 0
3010                 clk_enable_nolock(&clk_uart0);
3011                 clk_enable_nolock(&clk_pclk_uart0);
3012         #elif CONFIG_RK_DEBUG_UART == 1
3013                 clk_enable_nolock(&clk_uart1);
3014                 clk_enable_nolock(&clk_pclk_uart1);
3015
3016         #elif CONFIG_RK_DEBUG_UART == 2
3017                 clk_enable_nolock(&clk_uart2);
3018                 clk_enable_nolock(&clk_pclk_uart2);
3019
3020         #elif CONFIG_RK_DEBUG_UART == 3
3021                 clk_enable_nolock(&clk_uart3);
3022                 clk_enable_nolock(&clk_pclk_uart3);
3023
3024         #endif
3025         #if 0
3026         clk_enable_nolock(&clk_timer0);
3027         clk_enable_nolock(&clk_timer1);
3028         clk_enable_nolock(&clk_timer2);
3029         #endif
3030
3031         /*************************aclk_cpu***********************/
3032         clk_enable_nolock(&clk_dma1);
3033         clk_enable_nolock(&clk_l2mem_con);
3034         clk_enable_nolock(&clk_intmem);
3035         clk_enable_nolock(&clk_aclk_strc_sys);
3036
3037         /*************************hclk_cpu***********************/
3038         clk_enable_nolock(&clk_rom);
3039         #if 0
3040         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3041         // actually no i2s1
3042         clk_enable_nolock(&clk_hclk_i2s0_2ch);
3043         clk_enable_nolock(&clk_hclk_spdif);
3044         #endif
3045         clk_enable_nolock(&clk_hclk_cpubus);
3046         clk_enable_nolock(&clk_hclk_ahb2apb);
3047         clk_enable_nolock(&clk_hclk_vio_bus);
3048         #if 0
3049         clk_enable_nolock(&clk_hclk_lcdc0);
3050         clk_enable_nolock(&clk_hclk_lcdc1);
3051         clk_enable_nolock(&clk_hclk_cif0);
3052         clk_enable_nolock(&clk_hclk_ipp);
3053         clk_enable_nolock(&clk_hclk_rga);
3054         #endif
3055         clk_enable_nolock(&clk_hclk_video_h2h);
3056         clk_enable_nolock(&clk_hclk_l2mem);
3057
3058         /*************************pclk_cpu***********************/
3059         #if 0
3060         clk_enable_nolock(&clk_pwm01);
3061         clk_enable_nolock(&clk_pclk_timer0);
3062         clk_enable_nolock(&clk_pclk_timer1);
3063         clk_enable_nolock(&clk_pclk_timer2);
3064         clk_enable_nolock(&clk_i2c0);
3065         clk_enable_nolock(&clk_i2c1);
3066         clk_enable_nolock(&clk_gpio0);
3067         clk_enable_nolock(&clk_gpio1);
3068         clk_enable_nolock(&clk_gpio2);
3069         clk_enable_nolock(&clk_efuse);
3070         #endif
3071         clk_enable_nolock(&clk_tzpc);
3072         //clk_enable_nolock(&clk_pclk_uart0);
3073         //clk_enable_nolock(&clk_pclk_uart1);
3074         clk_enable_nolock(&clk_pclk_ddrupctl);
3075         clk_enable_nolock(&clk_pclk_ddrpubl);
3076         clk_enable_nolock(&clk_dbg);
3077         clk_enable_nolock(&clk_grf);
3078         clk_enable_nolock(&clk_pmu);
3079
3080         /*************************aclk_periph***********************/
3081         clk_enable_nolock(&clk_dma2);
3082         clk_enable_nolock(&clk_aclk_smc);
3083         clk_enable_nolock(&clk_aclk_peri_niu);
3084         clk_enable_nolock(&clk_aclk_cpu_peri);
3085         clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3086
3087         /*************************hclk_periph***********************/
3088         clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3089         clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3090         clk_enable_nolock(&clk_hclk_emem_peri);
3091         //clk_enable_nolock(&clk_hclk_mac);
3092         clk_enable_nolock(&clk_nandc);
3093         clk_enable_nolock(&clk_hclk_usb_peri);
3094         #if 0
3095         clk_enable_nolock(&clk_hclk_otg0);
3096         clk_enable_nolock(&clk_hclk_otg1);
3097         clk_enable_nolock(&clk_hclk_hsic);
3098         clk_enable_nolock(&clk_hclk_gps);
3099         clk_enable_nolock(&clk_hclk_hsadc);
3100         clk_enable_nolock(&clk_hclk_pidfilter);
3101         clk_enable_nolock(&clk_hclk_sdmmc);
3102         clk_enable_nolock(&clk_hclk_sdio);
3103         clk_enable_nolock(&clk_hclk_emmc);
3104         #endif
3105
3106         /*************************pclk_periph***********************/
3107         clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3108         #if 0
3109         clk_enable_nolock(&clk_pwm23);
3110         clk_enable_nolock(&clk_wdt);
3111         clk_enable_nolock(&clk_pclk_spi0);
3112         clk_enable_nolock(&clk_pclk_spi1);
3113         clk_enable_nolock(&clk_pclk_uart2);
3114         clk_enable_nolock(&clk_pclk_uart3);
3115         #endif
3116         #if 0
3117         clk_enable_nolock(&clk_i2c2);
3118         clk_enable_nolock(&clk_i2c3);
3119         clk_enable_nolock(&clk_i2c4);
3120         clk_enable_nolock(&clk_gpio3);
3121         clk_enable_nolock(&clk_pclk_saradc);
3122         #endif
3123         /*************************aclk_lcdc0***********************/
3124 #if 1
3125         //clk_enable_nolock(&clk_aclk_vio0);
3126         //clk_enable_nolock(&clk_aclk_lcdc0);
3127         //clk_enable_nolock(&clk_aclk_cif0);
3128         //clk_enable_nolock(&clk_aclk_ipp);
3129 #endif
3130         /*************************aclk_lcdc1***********************/
3131 #if 1
3132         //clk_enable_nolock(&clk_aclk_vio1);
3133         //clk_enable_nolock(&clk_aclk_lcdc1);
3134         //clk_enable_nolock(&clk_aclk_rga);
3135 #endif
3136         /************************power domain**********************/
3137
3138 }
3139 static void periph_clk_set_init(void)
3140 {
3141         unsigned long aclk_p, hclk_p, pclk_p;
3142         unsigned long ppll_rate = general_pll_clk.rate;
3143         //aclk 148.5
3144
3145         /* general pll */
3146         switch (ppll_rate) {
3147                 case 148500* KHZ:
3148                         aclk_p = 148500 * KHZ;
3149                         hclk_p = aclk_p >> 1;
3150                         pclk_p = aclk_p >> 2;
3151                         break;
3152                 case 1188*MHZ:
3153                         aclk_p = aclk_p >> 3; // 0
3154                         hclk_p = aclk_p >> 1;
3155                         pclk_p = aclk_p >> 2;
3156
3157                 case 297 * MHZ:
3158                         aclk_p = ppll_rate >> 1;
3159                         hclk_p = aclk_p >> 0;
3160                         pclk_p = aclk_p >> 1;
3161                         break;
3162
3163                 case 300 * MHZ:
3164                         aclk_p = ppll_rate >> 1;
3165                         hclk_p = aclk_p >> 0;
3166                         pclk_p = aclk_p >> 1;
3167                         break;
3168                 case 384 * MHZ:
3169                         aclk_p = ppll_rate >> 1;
3170                         hclk_p = aclk_p >> 1;
3171                         pclk_p = aclk_p >> 2;
3172                         break;
3173                 case 594 * MHZ:
3174                         aclk_p = ppll_rate >> 2;
3175                         hclk_p = aclk_p >> 0;
3176                         pclk_p = aclk_p >> 1;
3177                         break;
3178                 default:
3179                         aclk_p = 150 * MHZ;
3180                         hclk_p = 150 * MHZ;
3181                         pclk_p = 75 * MHZ;
3182                         break;
3183         }
3184         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3185         clk_set_rate_nolock(&aclk_periph, aclk_p);
3186         clk_set_rate_nolock(&hclk_periph, hclk_p);
3187         clk_set_rate_nolock(&pclk_periph, pclk_p);
3188 }
3189
3190 static void cpu_axi_init(void)
3191 {
3192         unsigned long cpu_div_rate, aclk_cpu_rate, hclk_cpu_rate, pclk_cpu_rate, ahb2apb_cpu_rate;
3193         unsigned long gpll_rate = general_pll_clk.rate;
3194
3195         switch (gpll_rate) {
3196                 case 297 * MHZ:
3197                         cpu_div_rate = gpll_rate;
3198                         aclk_cpu_rate = cpu_div_rate >> 0;
3199                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3200                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3201                         break;
3202                 case 384 * MHZ:
3203                         cpu_div_rate = gpll_rate >> 1;
3204                         aclk_cpu_rate = cpu_div_rate >> 0;
3205                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3206                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3207                         break;
3208
3209                 case 594 * MHZ:
3210                         cpu_div_rate = gpll_rate >> 1;
3211                         aclk_cpu_rate = cpu_div_rate >> 0;
3212                         hclk_cpu_rate = aclk_cpu_rate >> 1;
3213                         pclk_cpu_rate = aclk_cpu_rate >> 2;
3214                         break;
3215                 default:
3216                         aclk_cpu_rate = 150 * MHZ;
3217                         hclk_cpu_rate = 150 * MHZ;
3218                         pclk_cpu_rate = 75 * MHZ;
3219                         break;
3220         }
3221         ahb2apb_cpu_rate = pclk_cpu_rate;
3222
3223         clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);
3224         clk_set_rate_nolock(&clk_cpu_div, cpu_div_rate);
3225         clk_set_rate_nolock(&aclk_cpu, aclk_cpu_rate);
3226         clk_set_rate_nolock(&hclk_cpu, hclk_cpu_rate);
3227         clk_set_rate_nolock(&pclk_cpu, pclk_cpu_rate);
3228         clk_set_rate_nolock(&ahb2apb_cpu, ahb2apb_cpu_rate);
3229 }
3230
3231 void rk30_clock_common_i2s_init(void)
3232 {
3233         unsigned long i2s_rate;
3234         //20 times
3235         if(rk30_clock_flags & CLK_FLG_MAX_I2S_49152KHZ) {
3236                 i2s_rate = 49152000;
3237         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_24576KHZ) {
3238                 i2s_rate = 24576000;
3239         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_22579_2KHZ) {
3240                 i2s_rate = 22579000;
3241         } else if(rk30_clock_flags & CLK_FLG_MAX_I2S_12288KHZ) {
3242                 i2s_rate = 12288000;
3243         } else {
3244                 i2s_rate = 49152000;
3245         }
3246
3247         if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
3248                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3249         } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
3250                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3251         } else {
3252                 if(general_pll_clk.rate > codec_pll_clk.rate)
3253                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3254                 else
3255                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3256         }
3257 }
3258
3259 void rk_clock_common_uart_init(struct clk *cpll_clk,struct clk *gpll_clk)
3260 {
3261         struct clk *p_clk;
3262         unsigned long rate;
3263         if(!(gpll_clk->rate%(48*MHZ)))
3264         {
3265                 p_clk=gpll_clk;
3266                 rate=48*MHZ;
3267         }
3268         else if(!(cpll_clk->rate%(48*MHZ)))
3269         {
3270                 p_clk=cpll_clk;
3271                 rate=48*MHZ;
3272         }
3273         else if(!(gpll_clk->rate%(49500*KHZ)))
3274         {
3275                 p_clk=gpll_clk;
3276                 rate=(49500*KHZ);
3277         }
3278         else if(!(cpll_clk->rate%(49500*KHZ)))
3279         {
3280                 p_clk=cpll_clk;
3281                 rate=(49500*KHZ);
3282         }
3283         else
3284         {
3285                 if(cpll_clk->rate>gpll_clk->rate)
3286                 {
3287                         p_clk=cpll_clk;
3288                 }
3289                 else
3290                 {
3291                         p_clk=gpll_clk;
3292                 }
3293                 rate=50*MHZ;
3294         }
3295         clk_set_parent_nolock(&clk_uart_pll, p_clk);
3296         clk_set_rate_nolock(&clk_uart0_div,rate);
3297         clk_set_rate_nolock(&clk_uart1_div,rate);
3298         clk_set_rate_nolock(&clk_uart2_div,rate);
3299         clk_set_rate_nolock(&clk_uart3_div,rate);
3300         clk_set_rate_nolock(&clk_uart1,rate);
3301 }
3302 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
3303 {
3304
3305         //general
3306         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3307         lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
3308
3309         //code pll
3310         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3311
3312         cpu_axi_init();
3313         clk_set_rate_nolock(&clk_core, 312 * MHZ);
3314         //periph clk
3315         periph_clk_set_init();
3316
3317         //i2s
3318         rk30_clock_common_i2s_init();
3319
3320         // spi
3321         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3322         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3323
3324         // uart
3325
3326         rk_clock_common_uart_init(&codec_pll_clk,&general_pll_clk);
3327
3328         //mac
3329         if(!(gpll_rate % (50 * MHZ)))
3330                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3331         else if(!(ddr_pll_clk.rate % (50 * MHZ)))
3332                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3333         else
3334                 CLKDATA_ERR("mac can't get 50mhz\n");
3335
3336         //hsadc
3337         //auto pll sel
3338         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3339
3340         //lcdc0 lcd auto sel pll
3341         clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
3342         clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
3343
3344         //cif
3345         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3346
3347         //axi lcdc auto sel
3348         clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
3349         clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
3350         clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
3351         clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
3352
3353         //axi vepu auto sel
3354         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3355         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3356
3357         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3358         clk_set_rate_nolock(&aclk_vdpu, 300 * MHZ);
3359
3360         if(rk30_clock_flags&CLK_GPU_GPLL)
3361         {
3362                 clk_set_parent_nolock(&clk_gpu, &general_pll_clk);
3363                 clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
3364
3365         }
3366         else
3367         {
3368                 clk_set_parent_nolock(&clk_gpu, &codec_pll_clk);
3369                 clk_set_parent_nolock(&aclk_gpu, &codec_pll_clk);
3370         }
3371         clk_set_rate_nolock(&clk_gpu, 200 * MHZ);
3372         clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
3373
3374         clk_set_rate_nolock(&clk_uart0, 49500000);
3375         clk_set_rate_nolock(&clk_sdmmc, 24750000);
3376         clk_set_rate_nolock(&clk_sdio, 24750000);
3377 }
3378
3379 static struct clk def_ops_clk = {
3380         .get_parent = clksel_get_parent,
3381         .set_parent = clksel_set_parent,
3382 };
3383
3384 #ifdef CONFIG_PROC_FS
3385 struct clk_dump_ops dump_ops;
3386 #endif
3387 void rk_dump_clock_info(void);
3388
3389 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
3390 {
3391         struct clk_lookup *lk;
3392
3393         clk_register_dump_ops(&dump_ops);
3394         clk_register_default_ops_clk(&def_ops_clk);
3395         rk30_clock_flags = flags;
3396         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3397 #ifdef RK30_CLK_OFFBOARD_TEST
3398                 rk30_clkdev_add(lk);
3399 #else
3400                 clkdev_add(lk);
3401 #endif
3402                 clk_register(lk->clk);
3403         }
3404         clk_recalculate_root_clocks_nolock();
3405
3406         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3407
3408         /*
3409          * Only enable those clocks we will need, let the drivers
3410          * enable other clocks as necessary
3411          */
3412         rk30_init_enable_clocks();
3413 #if 0
3414         // print loader config
3415         rk_dump_clock_info();
3416         while(1);
3417 #endif
3418         /*
3419          * Disable any unused clocks left on by the bootloader
3420          */
3421         //clk_disable_unused();
3422         rk30_clock_common_init(gpll, cpll);
3423         preset_lpj = loops_per_jiffy;
3424
3425         //gpio6_b7
3426         //regfile_writel(0xc0004000,0x10c);
3427         //cru_writel(0x07000000,CRU_MISC_CON);
3428
3429 }
3430
3431 void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
3432 {
3433         _rk30_clock_data_init(gpll, cpll, flags);
3434         rk_dvfs_init();
3435 }
3436
3437 /*
3438  * You can override arm_clk rate with armclk= cmdline option.
3439  */
3440 static int __init armclk_setup(char *str)
3441 {
3442         get_option(&str, &armclk);
3443
3444         if (!armclk)
3445                 return 0;
3446         if (armclk < 10000)
3447                 armclk *= MHZ;
3448         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3449         return 0;
3450 }
3451 #ifndef RK30_CLK_OFFBOARD_TEST
3452 early_param("armclk", armclk_setup);
3453 #endif
3454
3455
3456 static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
3457 {
3458         struct clk *ck;
3459         int i;
3460         unsigned long rate = clk->rate;
3461         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3462         for (i = 0; i < deep; i++)
3463                 printk("    ");
3464
3465         printk("%-11s ", clk->name);
3466 #ifndef RK30_CLK_OFFBOARD_TEST
3467         if (clk->flags & IS_PD) {
3468                 printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3469         }
3470 #endif
3471         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3472                 int idx = clk->gate_idx;
3473                 u32 v;
3474                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3475                 printk("%s ", v ? "off" : "on ");
3476         }
3477
3478         if (clk->pll) {
3479                 u32 pll_mode;
3480                 u32 pll_id = clk->pll->id;
3481                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3482                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3483                         printk("slow   ");
3484                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3485                         printk("normal ");
3486                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3487                         printk("deep   ");
3488
3489                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3490                         printk("bypass ");
3491         } else if(clk == &clk_ddr) {
3492                 rate = clk->recalc(clk);
3493         }
3494
3495         if (rate >= MHZ) {
3496                 if (rate % MHZ)
3497                         printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3498                 else
3499                         printk("%ld MHz", rate / MHZ);
3500         } else if (rate >= KHZ) {
3501                 if (rate % KHZ)
3502                         printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3503                 else
3504                         printk("%ld KHz", rate / KHZ);
3505         } else {
3506                 printk("%ld Hz", rate);
3507         }
3508
3509         printk(" usecount = %d", clk->usecount);
3510
3511         if (clk->parent)
3512                 printk(" parent = %s", clk->parent->name);
3513
3514         printk("\n");
3515
3516         list_for_each_entry(ck, root_clocks, node) {
3517                 if (ck->parent == clk)
3518                         rk_dump_clock(ck, deep + 1, root_clocks);
3519         }
3520 }
3521
3522 #if 1
3523 struct list_head *get_rk_clocks_head(void);
3524
3525 void rk_dump_clock_info(void)
3526 {
3527         struct clk* clk;
3528         list_for_each_entry(clk, get_rk_clocks_head(), node) {
3529                 if (!clk->parent)
3530                 rk_dump_clock(clk, 0,get_rk_clocks_head());
3531         }
3532 }
3533 #endif
3534
3535 #ifdef CONFIG_PROC_FS
3536
3537 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks)
3538 {
3539         struct clk *ck;
3540         int i;
3541         unsigned long rate = clk->rate;
3542         //CLKDATA_DBG("dump_clock %s\n",clk->name);
3543         for (i = 0; i < deep; i++)
3544                 seq_printf(s, "    ");
3545
3546         seq_printf(s, "%-11s ", clk->name);
3547 #ifndef RK30_CLK_OFFBOARD_TEST
3548         if (clk->flags & IS_PD) {
3549                 seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3550         }
3551 #endif
3552         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3553                 int idx = clk->gate_idx;
3554                 u32 v;
3555                 v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
3556                 seq_printf(s, "%s ", v ? "off" : "on ");
3557         }
3558
3559         if (clk->pll) {
3560                 u32 pll_mode;
3561                 u32 pll_id = clk->pll->id;
3562                 pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3563                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3564                         seq_printf(s, "slow   ");
3565                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3566                         seq_printf(s, "normal ");
3567                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3568                         seq_printf(s, "deep   ");
3569
3570                 if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
3571                         seq_printf(s, "bypass ");
3572         } else if(clk == &clk_ddr) {
3573                 rate = clk->recalc(clk);
3574         }
3575
3576         if (rate >= MHZ) {
3577                 if (rate % MHZ)
3578                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3579                 else
3580                         seq_printf(s, "%ld MHz", rate / MHZ);
3581         } else if (rate >= KHZ) {
3582                 if (rate % KHZ)
3583                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3584                 else
3585                         seq_printf(s, "%ld KHz", rate / KHZ);
3586         } else {
3587                 seq_printf(s, "%ld Hz", rate);
3588         }
3589
3590         seq_printf(s, " usecount = %d", clk->usecount);
3591
3592         if (clk->parent)
3593                 seq_printf(s, " parent = %s", clk->parent->name);
3594
3595         seq_printf(s, "\n");
3596
3597         list_for_each_entry(ck, root_clocks, node) {
3598                 if (ck->parent == clk)
3599                         dump_clock(s, ck, deep + 1, root_clocks);
3600         }
3601 }
3602
3603 static void dump_regs(struct seq_file *s)
3604 {
3605         int i = 0;
3606         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3607         seq_printf(s, "\nPLLRegisters:\n");
3608         for(i = 0; i < END_PLL_ID; i++) {
3609                 seq_printf(s, "pll%d        :cons:%x,%x,%x,%x\n", i,
3610                                 cru_readl(PLL_CONS(i, 0)),
3611                                 cru_readl(PLL_CONS(i, 1)),
3612                                 cru_readl(PLL_CONS(i, 2)),
3613                                 cru_readl(PLL_CONS(i, 3))
3614                           );
3615         }
3616         seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3617
3618         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3619                 seq_printf(s, "CLKSEL%d            :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3620         }
3621         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3622                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3623         }
3624         seq_printf(s, "GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3625         seq_printf(s, "GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3626
3627         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3628                 seq_printf(s, "CLKGATE%d          :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3629         }
3630         seq_printf(s, "CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3631         seq_printf(s, "GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3632
3633 }
3634
3635 void rk30_clk_dump_regs(void)
3636 {
3637         int i = 0;
3638         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3639         printk("\nPLLRegisters:\n");
3640         for(i = 0; i < END_PLL_ID; i++) {
3641                 printk("pll%d        :cons:%x,%x,%x,%x\n", i,
3642                                 cru_readl(PLL_CONS(i, 0)),
3643                                 cru_readl(PLL_CONS(i, 1)),
3644                                 cru_readl(PLL_CONS(i, 2)),
3645                                 cru_readl(PLL_CONS(i, 3))
3646                       );
3647         }
3648         printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3649
3650         for(i = 0; i < CRU_CLKSELS_CON_CNT; i++) {
3651                 printk("CLKSEL%d           :%x\n", i, cru_readl(CRU_CLKSELS_CON(i)));
3652         }
3653         for(i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
3654                 printk("CLKGATE%d         :%x\n", i, cru_readl(CRU_CLKGATES_CON(i)));
3655         }
3656         printk("GLB_SRST_FST:%x\n", cru_readl(CRU_GLB_SRST_FST));
3657         printk("GLB_SRST_SND:%x\n", cru_readl(CRU_GLB_SRST_SND));
3658
3659         for(i = 0; i < CRU_SOFTRSTS_CON_CNT; i++) {
3660                 printk("SOFTRST%d         :%x\n", i, cru_readl(CRU_SOFTRSTS_CON(i)));
3661         }
3662         printk("CRU MISC    :%x\n", cru_readl(CRU_MISC_CON));
3663         printk("GLB_CNT_TH  :%x\n", cru_readl(CRU_GLB_CNT_TH));
3664
3665 }
3666
3667
3668 #ifdef CONFIG_PROC_FS
3669 static void dump_clock(struct seq_file *s, struct clk *clk, int deep, const struct list_head *root_clocks);
3670 struct clk_dump_ops dump_ops = {
3671         .dump_clk = dump_clock,
3672         .dump_regs = dump_regs,
3673 };
3674 #endif
3675
3676
3677 #endif /* CONFIG_PROC_FS */
3678
3679
3680
3681
3682 #ifdef RK30_CLK_OFFBOARD_TEST
3683 struct clk *test_get_parent(struct clk *clk) {
3684         return clk->parent;
3685 }
3686
3687 void i2s_test(void)
3688 {
3689         struct clk *i2s_clk = &clk_i2s0;
3690
3691         clk_enable_nolock(i2s_clk);
3692
3693         clk_set_rate_nolock(i2s_clk, 12288000);
3694         printk("int %s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3695         clk_set_rate_nolock(i2s_clk, 297 * MHZ / 2);
3696         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3697         clk_set_rate_nolock(i2s_clk, 12 * MHZ);
3698         printk("int%s parent is %s\n", i2s_clk->name, test_get_parent(i2s_clk)->name);
3699
3700 }
3701
3702 void uart_test(void)
3703 {
3704         struct clk *uart_clk = &clk_uart0;
3705
3706         clk_enable_nolock(uart_clk);
3707
3708         clk_set_rate_nolock(uart_clk, 12288000);
3709         printk("int %s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3710         clk_set_rate_nolock(uart_clk, 297 * MHZ / 2);
3711         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3712         clk_set_rate_nolock(uart_clk, 12 * MHZ);
3713         printk("int%s parent is %s\n", uart_clk->name, test_get_parent(uart_clk)->name);
3714
3715 }
3716 void hsadc_test(void)
3717 {
3718         struct clk *hsadc_clk = &clk_hsadc;
3719
3720         printk("******************hsadc_test**********************\n");
3721         clk_enable_nolock(hsadc_clk);
3722
3723         clk_set_rate_nolock(hsadc_clk, 12288000);
3724         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3725
3726
3727         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3728         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3729
3730         clk_set_rate_nolock(hsadc_clk, 300 * MHZ / 2);
3731
3732         clk_set_rate_nolock(hsadc_clk, 296 * MHZ / 2);
3733
3734         printk("******************hsadc out clock**********************\n");
3735
3736         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3737         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3738         clk_set_rate_nolock(hsadc_clk, 297 * MHZ / 2);
3739         printk("****end %s parent is %s\n", hsadc_clk->name, test_get_parent(hsadc_clk)->name);
3740
3741
3742
3743 }
3744
3745 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3746 {
3747         //arm
3748         printk("*********arm_pll_clk***********\n");
3749         clk_set_rate_nolock(&arm_pll_clk, 816 * MHZ);
3750
3751         printk("*********set clk_core parent***********\n");
3752         clk_set_parent_nolock(&clk_core, &arm_pll_clk);
3753         clk_set_rate_nolock(&clk_core, 504 * MHZ);
3754
3755         //general
3756         printk("*********general_pll_clk***********\n");
3757         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3758
3759         //code pll
3760         printk("*********codec_pll_clk***********\n");
3761         clk_set_rate_nolock(&codec_pll_clk, 600 * MHZ);
3762
3763
3764         printk("*********periph_clk_set_init***********\n");
3765         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3766         periph_clk_set_init();
3767
3768 #if 0 //
3769         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3770 #else
3771         printk("*********clk i2s***********\n");
3772         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3773         printk("common %s parent is %s\n", clk_i2s_pll.name, test_get_parent(&clk_i2s_pll)->name);
3774         i2s_test();
3775 #endif
3776         // spi
3777         clk_enable_nolock(&clk_spi0);
3778         clk_set_rate_nolock(&clk_spi0, 30 * MHZ);
3779         printk("common %s parent is %s\n", clk_spi0.name, test_get_parent(&clk_spi0)->name);
3780         //saradc
3781         clk_enable_nolock(&clk_saradc);
3782         clk_set_rate_nolock(&clk_saradc, 6 * MHZ);
3783         printk("common %s parent is %s\n", clk_saradc.name, test_get_parent(&clk_saradc)->name);
3784         //sdio
3785         clk_enable_nolock(&clk_sdio);
3786         clk_set_rate_nolock(&clk_sdio, 50 * MHZ);
3787         printk("common %s parent is %s\n", clk_sdio.name, test_get_parent(&clk_sdio)->name);
3788         // uart
3789         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3790         uart_test();
3791         //mac
3792         printk("*********mac***********\n");
3793
3794         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3795         printk("common %s parent is %s\n", clk_mac_pll_div.name, test_get_parent(&clk_mac_pll_div)->name);
3796
3797         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3798         clk_set_rate_nolock(&clk_mac_ref, 50 * MHZ);
3799         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3800
3801         printk("*********mac mii set***********\n");
3802         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3803         clk_set_rate_nolock(&clk_mac_ref, 20 * MHZ);
3804         printk("common %s parent is %s\n", clk_mac_ref.name, test_get_parent(&clk_mac_ref)->name);
3805         //hsadc
3806         printk("*********hsadc 1***********\n");
3807         //auto pll
3808         hsadc_test();
3809         //lcdc
3810         clk_enable_nolock(&dclk_lcdc0);
3811
3812         clk_set_rate_nolock(&dclk_lcdc0, 60 * MHZ);
3813         clk_set_rate_nolock(&dclk_lcdc0, 27 * MHZ);
3814
3815         //cif
3816         clk_enable_nolock(&cif0_out);
3817
3818         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3819         printk("common %s parent is %s\n", cif_out_pll.name, test_get_parent(&cif_out_pll)->name);
3820
3821         clk_set_rate_nolock(&cif0_out, 60 * MHZ);
3822         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3823
3824         clk_set_rate_nolock(&cif0_out, 24 * MHZ);
3825         printk("common %s parent is %s\n", cif0_out.name, test_get_parent(&cif0_out)->name);
3826         //cif_in
3827         clk_enable_nolock(&cif0_in);
3828         clk_set_rate_nolock(&cif0_in, 24 * MHZ);
3829         //axi lcdc
3830         clk_enable_nolock(&aclk_lcdc0);
3831         clk_set_rate_nolock(&aclk_lcdc0, 150 * MHZ);
3832         printk("common %s parent is %s\n", aclk_lcdc0.name, test_get_parent(&aclk_lcdc0)->name);
3833         //axi vepu
3834         clk_enable_nolock(&aclk_vepu);
3835         clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3836         printk("common %s parent is %s\n", aclk_vepu.name, test_get_parent(&aclk_vepu)->name);
3837
3838         clk_set_rate_nolock(&hclk_vepu, 300 * MHZ);
3839         printk("common %s parent is %s\n", hclk_vepu.name, test_get_parent(&hclk_vepu)->name);
3840
3841         printk("test end\n");
3842
3843         /* arm pll
3844            clk_set_rate_nolock(&arm_pll_clk, armclk);
3845            clk_set_rate_nolock(&clk_core,       armclk);//pll:core =1:1
3846            */
3847         //
3848         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3849         //
3850         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3851         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3852
3853 }
3854
3855
3856
3857
3858
3859 static LIST_HEAD(rk30_clocks);
3860 static DEFINE_MUTEX(rk30_clocks_mutex);
3861
3862 static inline int __rk30clk_get(struct clk *clk)
3863 {
3864         return 1;
3865 }
3866 void rk30_clkdev_add(struct clk_lookup *cl)
3867 {
3868         mutex_lock(&rk30_clocks_mutex);
3869         list_add_tail(&cl->node, &rk30_clocks);
3870         mutex_unlock(&rk30_clocks_mutex);
3871 }
3872 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id) {
3873         struct clk_lookup *p, *cl = NULL;
3874         int match, best = 0;
3875
3876         list_for_each_entry(p, &rk30_clocks, node) {
3877                 match = 0;
3878                 if (p->dev_id) {
3879                         if (!dev_id || strcmp(p->dev_id, dev_id))
3880                                 continue;
3881                         match += 2;
3882                 }
3883                 if (p->con_id) {
3884                         if (!con_id || strcmp(p->con_id, con_id))
3885                                 continue;
3886                         match += 1;
3887                 }
3888
3889                 if (match > best) {
3890                         cl = p;
3891                         if (match != 3)
3892                                 best = match;
3893                         else
3894                                 break;
3895                 }
3896         }
3897         return cl;
3898 }
3899
3900 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id) {
3901         struct clk_lookup *cl;
3902
3903         mutex_lock(&rk30_clocks_mutex);
3904         cl = rk30_clk_find(dev_id, con_id);
3905         if (cl && !__rk30clk_get(cl->clk))
3906                 cl = NULL;
3907         mutex_unlock(&rk30_clocks_mutex);
3908
3909         return cl ? cl->clk : ERR_PTR(-ENOENT);
3910 }
3911 //EXPORT_SYMBOL(rk30_clk_get_sys);
3912
3913 struct clk *rk30_clk_get(struct device *dev, const char *con_id) {
3914         const char *dev_id = dev ? dev_name(dev) : NULL;
3915         return rk30_clk_get_sys(dev_id, con_id);
3916 }
3917 //EXPORT_SYMBOL(rk30_clk_get);
3918
3919
3920 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
3921
3922 void rk30_clocks_test(void)
3923 {
3924         struct clk *test_gpll;
3925         test_gpll = rk30_clk_get(NULL, "general_pll");
3926         if(test_gpll) {
3927                 rk30_clk_set_rate(test_gpll, 297 * 2 * MHZ);
3928                 printk("gpll rate=%lu\n", test_gpll->rate);
3929         }
3930         //while(1);
3931 }
3932
3933 void __init rk30_clock_init_test(void)
3934 {
3935
3936         rk30_clock_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
3937         //while(1);
3938 }
3939
3940
3941 #endif
3942
3943