clock_data.c

   1 /* linux/arch/arm/mach-rk30/clock_data.c
   2  *
   3  * Copyright (C) 2012 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/clkdev.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/hardirq.h>
  24 #include <mach/cru.h>
  25 #include <mach/iomux.h>
  26 #include <mach/clock.h>
  27 #include <mach/pmu.h>
  28 #include <mach/dvfs.h>
  29 #include <mach/ddr.h>
  30
  31 #define MHZ                     (1000*1000)
  32 #define KHZ                     (1000)
  33 #define CLK_LOOPS_JIFFY_REF 11996091ULL
  34 #define CLK_LOOPS_RATE_REF (1200) //Mhz
  35 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
  36
  37 //flags bit
  38 //has extern 27mhz
  39 #define CLK_FLG_EXT_27MHZ                       (1<<0)
  40 //max i2s rate
  41 #define CLK_FLG_MAX_I2S_12288KHZ        (1<<1)
  42 #define CLK_FLG_MAX_I2S_22579_2KHZ      (1<<2)
  43 #define CLK_FLG_MAX_I2S_24576KHZ        (1<<3)
  44 #define CLK_FLG_MAX_I2S_49152KHZ        (1<<4)
  45 //uart 1m\3m
  46 #define CLK_FLG_UART_1_3M                       (1<<5)
  47 #define CLK_CPU_HPCLK_11                                (1<<6)
  48
  49
  50
  51 struct apll_clk_set {
  52         unsigned long rate;
  53         u32     pllcon0;
  54         u32     pllcon1;
  55         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  56         u32 rst_dly;//us
  57         u32     clksel0;
  58         u32     clksel1;
  59         unsigned long lpj;
  60 };
  61 struct pll_clk_set {
  62         unsigned long rate;
  63         u32     pllcon0;
  64         u32     pllcon1;
  65         u32     pllcon2; //nb=bwadj+1;0:11;nb=nf/2
  66         u32 rst_dly;//us
  67 };
  68
  69 #define SET_PLL_DATA(_pll_id,_table) \
  70 {\
  71         .id=(_pll_id),\
  72         .table=(_table),\
  73 }
  74
  75
  76 #define _PLL_SET_CLKS(_mhz, nr, nf, no) \
  77 { \
  78         .rate   = (_mhz) * KHZ, \
  79         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
  80         .pllcon1 = PLL_CLKF_SET(nf),\
  81         .pllcon2 = PLL_CLK_BWADJ_SET(nf/2-1),\
  82         .rst_dly=((nr*500)/24+1),\
  83         }
  84
  85
  86 #define _APLL_SET_LPJ(_mhz) \
  87         .lpj= (CLK_LOOPS_JIFFY_REF * _mhz)/CLK_LOOPS_RATE_REF
  88
  89
  90 #define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
  91         { \
  92         .rate   = _mhz * MHZ, \
  93         .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no),\
  94         .pllcon1 = PLL_CLKF_SET(nf),\
  95         .pllcon2 = PLL_CLK_BWADJ_SET(nf>>1),\
  96         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
  97         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
  98         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
  99         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 100         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 101         _APLL_SET_LPJ(_mhz),\
 102         .rst_dly=((nr*500)/24+1),\
 103         }
 104
 105 #define CRU_DIV_SET(mask,shift,max) \
 106         .div_mask=(mask),\
 107         .div_shift=(shift),\
 108         .div_max=(max)
 109
 110
 111 #define CRU_SRC_SET(mask,shift ) \
 112         .src_mask=(mask),\
 113         .src_shift=(shift)
 114
 115 #define CRU_PARENTS_SET(parents_array) \
 116         .parents=(parents_array),\
 117         .parents_num=ARRAY_SIZE((parents_array))
 118
 119 #define CRU_GATE_MODE_SET(_func,_IDX) \
 120         .mode=_func,\
 121         .gate_idx=(_IDX)
 122
 123 struct clk_src_sel {
 124         struct clk      *parent;
 125         u8      value;//crt bit
 126         u8      flag;
 127 //selgate
 128 };
 129
 130 #define GATE_CLK(NAME,PARENT,ID) \
 131 static struct clk clk_##NAME = { \
 132         .name           = #NAME, \
 133         .parent         = &PARENT, \
 134         .mode           = gate_mode, \
 135         .gate_idx       = CLK_GATE_##ID, \
 136 }
 137 #ifdef RK30_CLK_OFFBOARD_TEST
 138 u32 TEST_GRF_REG[0x240];
 139 u32 TEST_CRU_REG[0x240];
 140 #define cru_readl(offset)       (TEST_CRU_REG[offset/4])
 141
 142 u32 cru_writel_is_pr(u32 offset)
 143 {
 144         return (offset==0x4000);
 145 }
 146 void cru_writel(u32 v, u32 offset)
 147 {
 148
 149         u32 mask_v=v>>16;
 150         TEST_CRU_REG[offset/4]&=(~mask_v);
 151
 152         v&=(mask_v);
 153
 154         TEST_CRU_REG[offset/4]|=v;
 155         TEST_CRU_REG[offset/4]&=0x0000ffff;
 156
 157         if(cru_writel_is_pr(offset))
 158         {
 159                 CRU_PRINTK_DBG("cru w offset=%d,set=%x,reg=%x\n",offset,v,TEST_CRU_REG[offset/4]);
 160
 161         }
 162
 163 }
 164 void cru_writel_i2s(u32 v, u32 offset)
 165 {
 166         TEST_CRU_REG[offset/4]=v;
 167 }
 168 #define cru_writel_frac(v,offset) cru_writel_i2s((v),(offset))
 169
 170 #define regfile_readl(offset)   (0xffffffff)
 171 //#define pmu_readl(offset)        readl(RK30_GRF_BASE + offset)
 172 void rk30_clkdev_add(struct clk_lookup *cl);
 173 #else
 174 #define regfile_readl(offset)   readl_relaxed(RK30_GRF_BASE + offset)
 175 #define regfile_writel(v, offset) do { writel_relaxed(v, RK30_GRF_BASE + offset); dsb(); } while (0)
 176 #define cru_readl(offset)       readl_relaxed(RK30_CRU_BASE + offset)
 177 #define cru_writel(v, offset)   do { writel_relaxed(v, RK30_CRU_BASE + offset); dsb(); } while (0)
 178
 179 #define cru_writel_frac(v,offset) cru_writel((v),(offset))
 180 #endif
 181
 182 #ifdef DEBUG
 183 #define CRU_PRINTK_DBG(fmt, args...) pr_debug(fmt, ## args)
 184 #define CRU_PRINTK_LOG(fmt, args...) pr_debug(fmt, ## args)
 185 #else
 186 #define CRU_PRINTK_DBG(fmt, args...) do {} while(0)
 187 #define CRU_PRINTK_LOG(fmt, args...) do {} while(0)
 188 #endif
 189 #define CRU_PRINTK_ERR(fmt, args...) pr_err(fmt, ## args)
 190
 191
 192 #define get_cru_bits(con,mask,shift)\
 193         ((cru_readl((con)) >> (shift)) & (mask))
 194
 195 #define set_cru_bits_w_msk(val,mask,shift,con)\
 196         cru_writel(((mask)<<(shift+16))|((val)<<(shift)),(con))
 197
 198
 199 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
 200         &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
 201
 202
 203 static u32 rk30_clock_flags=0;
 204 static struct clk codec_pll_clk;
 205 static struct clk general_pll_clk;
 206 static struct clk arm_pll_clk;
 207 static unsigned long lpj_gpll;
 208 static unsigned int __initdata armclk = 504*MHZ;
 209
 210
 211 /************************clk recalc div rate*********************************/
 212
 213 //for free div
 214 static unsigned long clksel_recalc_div(struct clk *clk)
 215 {
 216         u32 div = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift) + 1;
 217
 218         unsigned long rate = clk->parent->rate / div;
 219         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, div);
 220         return rate;
 221 }
 222
 223 //for div 1 2 4 2^n
 224 static unsigned long clksel_recalc_shift(struct clk *clk)
 225 {
 226         u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift);
 227         unsigned long rate = clk->parent->rate >> shift;
 228         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 229         return rate;
 230 }
 231
 232
 233 static unsigned long clksel_recalc_shift_2(struct clk *clk)
 234 {
 235         u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1;
 236         unsigned long rate = clk->parent->rate >> shift;
 237         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
 238         return rate;
 239 }
 240
 241 static unsigned long clksel_recalc_parent_rate(struct clk *clk)
 242 {
 243         unsigned long rate = clk->parent->rate;
 244         pr_debug("%s new clock rate is %lu\n", clk->name, rate);
 245         return rate;
 246 }
 247 /********************************set div rate***********************************/
 248
 249 //for free div
 250 static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
 251 {
 252         u32 div;
 253         for (div = 0; div < clk->div_max; div++) {
 254                 u32 new_rate = clk->parent->rate / (div + 1);
 255                 if (new_rate <= rate) {
 256                         set_cru_bits_w_msk(div,clk->div_mask,clk->div_shift,clk->clksel_con);
 257                         //clk->rate = new_rate;
 258                         pr_debug("clksel_set_rate_freediv for clock %s to rate %ld (div %d)\n", clk->name, rate, div + 1);
 259                         return 0;
 260                 }
 261         }
 262         return -ENOENT;
 263 }
 264
 265 //for div 1 2 4 2^n
 266 static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
 267 {
 268         u32 shift;
 269         for (shift = 0; (1 << shift) < clk->div_max; shift++) {
 270                 u32 new_rate = clk->parent->rate >> shift;
 271                 if (new_rate <= rate) {
 272                         set_cru_bits_w_msk(shift,clk->div_mask,clk->div_shift,clk->clksel_con);
 273                         clk->rate = new_rate;
 274                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 275                         return 0;
 276                 }
 277         }
 278         return -ENOENT;
 279 }
 280
 281 //for div 2 4 2^n
 282 static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 283 {
 284         u32 shift;
 285
 286         for (shift = 1; (1 << shift) < clk->div_max; shift++) {
 287                 u32 new_rate = clk->parent->rate >> shift;
 288                 if (new_rate <= rate) {
 289                         set_cru_bits_w_msk(shift-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 290                         clk->rate = new_rate;
 291                         pr_debug("clksel_set_rate_shift for clock %s to rate %ld (shift %d)\n", clk->name, rate, shift);
 292                         return 0;
 293                 }
 294         }
 295         return -ENOENT;
 296 }
 297
 298 //for div 1 2 4 2*n
 299 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 300 {
 301         u32 div;
 302         for (div = 2; div < clk->div_max; div += 2) {
 303                 u32 new_rate = clk->parent->rate / div;
 304                 if (new_rate <= rate) {
 305                         set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 306                         clk->rate = new_rate;
 307                         pr_debug("%s for clock %s to rate %ld (even div = %d)\n",
 308                                         __func__, clk->name, rate, div);
 309                         return 0;
 310                 }
 311         }
 312         return -ENOENT;
 313 }
 314
 315 static u32 clk_get_freediv(unsigned long rate_out, unsigned long rate ,u32 div_max)
 316 {
 317         u32 div;
 318         unsigned long new_rate;
 319         for (div = 0; div <div_max; div++) {
 320                 new_rate = rate / (div + 1);
 321                 if (new_rate <= rate_out) {
 322                         return div+1;
 323                 }
 324         }
 325         return div_max?div_max:1;
 326 }
 327 struct clk *get_freediv_parents_div(struct clk *clk,unsigned long rate,u32 *div_out)
 328 {
 329         u32 div[2]={0,0};
 330         unsigned long new_rate[2]={0,0};
 331         u32 i;
 332
 333         if(clk->rate==rate)
 334                 return clk->parent;
 335         for(i=0;i<2;i++)
 336         {
 337                 div[i]=clk_get_freediv(rate,clk->parents[i]->rate,clk->div_max);
 338                 new_rate[i] = clk->parents[i]->rate/div[i];
 339                 if(new_rate[i]==rate)
 340                 {
 341                         *div_out=div[i];
 342                         return clk->parents[i];
 343                 }
 344         }
 345         if(new_rate[0]<new_rate[1])
 346                 i=1;
 347         else
 348                 i=0;
 349         *div_out=div[i];
 350         return clk->parents[i];
 351 }
 352
 353 static int clkset_rate_freediv_autosel_parents(struct clk *clk, unsigned long rate)
 354 {
 355         struct clk *p_clk;
 356         u32 div,old_div;
 357         int ret=0;
 358         if(clk->rate==rate)
 359                 return 0;
 360         p_clk=get_freediv_parents_div(clk,rate,&div);
 361
 362         if(!p_clk)
 363                 return -ENOENT;
 364
 365         CRU_PRINTK_DBG("%s %lu,form %s\n",clk->name,rate,p_clk->name);
 366         if (clk->parent != p_clk)
 367         {
 368                 old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),clk->div_shift,clk->div_mask)+1;
 369
 370                 if(div>old_div)
 371                 {
 372                         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 373                 }
 374                 ret=clk_set_parent_nolock(clk,p_clk);
 375                 if(ret)
 376                 {
 377                         CRU_PRINTK_ERR("%s can't set %lu,reparent err\n",clk->name,rate);
 378                         return -ENOENT;
 379                 }
 380         }
 381         //set div
 382         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 383         return 0;
 384 }
 385
 386 //rate==div rate //hdmi
 387 static int clk_freediv_autosel_parents_set_fixed_rate(struct clk *clk, unsigned long rate)
 388 {
 389         struct clk *p_clk;
 390         u32 div,old_div;
 391         int ret;
 392         p_clk=get_freediv_parents_div(clk,rate,&div);
 393
 394         if(!p_clk)
 395         return -ENOENT;
 396
 397         if((p_clk->rate/div)!=rate||(p_clk->rate%div))
 398         return -ENOENT;
 399
 400         if (clk->parent != p_clk)
 401         {
 402                 old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),
 403                                                                         clk->div_shift,clk->div_mask)+1;
 404                 if(div>old_div)
 405                 {
 406                         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 407                 }
 408                 ret=clk_set_parent_nolock(clk,p_clk);
 409                 if (ret)
 410                 {
 411                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
 412                         return ret;
 413                 }
 414         }
 415         //set div
 416         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
 417         return 0;
 418 }
 419
 420 /***************************round********************************/
 421
 422 static long clksel_freediv_round_rate(struct clk *clk, unsigned long rate)
 423 {
 424         return clk->parent->rate/clk_get_freediv(rate,clk->parent->rate,clk->div_max);
 425 }
 426
 427 static long clk_freediv_round_autosel_parents_rate(struct clk *clk, unsigned long rate)
 428 {
 429         u32 div;
 430         struct clk *p_clk;
 431         if(clk->rate == rate)
 432                 return clk->rate;
 433         p_clk=get_freediv_parents_div(clk,rate,&div);
 434         if(!p_clk)
 435                 return 0;
 436         return p_clk->rate/div;
 437 }
 438
 439 /**************************************others seting************************************/
 440
 441 static struct clk* clksel_get_parent(struct clk *clk)
 442 {
 443         return clk->parents[(cru_readl(clk->clksel_con) >> clk->src_shift) & clk->src_mask];
 444 }
 445 static int clksel_set_parent(struct clk *clk, struct clk *parent)
 446 {
 447         u32 i;
 448         if (unlikely(!clk->parents))
 449                 return -EINVAL;
 450         for (i = 0; (i <clk->parents_num); i++) {
 451                 if (clk->parents[i]!= parent)
 452                         continue;
 453                 set_cru_bits_w_msk(i,clk->src_mask,clk->src_shift,clk->clksel_con);
 454                 return 0;
 455         }
 456         return -EINVAL;
 457 }
 458
 459 static int gate_mode(struct clk *clk, int on)
 460 {
 461         int idx = clk->gate_idx;
 462         if (idx >= CLK_GATE_MAX)
 463                 return -EINVAL;
 464         if(on)
 465         {
 466                 cru_writel(CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 467                 //CRU_PRINTK_DBG("un gate id=%d %s(%x),con %x\n",idx,clk->name,
 468                 //      CLK_GATE_W_MSK(idx)|CLK_UN_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 469         }
 470         else
 471         {
 472                 cru_writel(CLK_GATE_W_MSK(idx)|CLK_GATE(idx), CLK_GATE_CLKID_CONS(idx));
 473         //      CRU_PRINTK_DBG("gate id=%d %s(%x),con%x\n",idx,clk->name,
 474                 //      CLK_GATE_W_MSK(idx)|CLK_GATE(idx),CLK_GATE_CLKID_CONS(idx));
 475         }
 476         return 0;
 477 }
 478 /*****************************frac set******************************************/
 479
 480 static unsigned long clksel_recalc_frac(struct clk *clk)
 481 {
 482         unsigned long rate;
 483         u64 rate64;
 484         u32 r = cru_readl(clk->clksel_con), numerator, denominator;
 485         if (r == 0) // FPGA ?
 486                 return clk->parent->rate;
 487         numerator = r >> 16;
 488         denominator = r & 0xFFFF;
 489         rate64 = (u64)clk->parent->rate * numerator;
 490         do_div(rate64, denominator);
 491         rate = rate64;
 492         pr_debug("%s new clock rate is %lu (frac %u/%u)\n", clk->name, rate, numerator, denominator);
 493         return rate;
 494 }
 495
 496 static u32 clk_gcd(u32 numerator, u32 denominator)
 497 {
 498         u32 a, b;
 499
 500         if (!numerator || !denominator)
 501                 return 0;
 502         if (numerator > denominator) {
 503                 a = numerator;
 504                 b = denominator;
 505         } else {
 506                 a = denominator;
 507                 b = numerator;
 508         }
 509         while (b != 0) {
 510                 int r = b;
 511                 b = a % b;
 512                 a = r;
 513         }
 514
 515         return a;
 516 }
 517
 518 static int frac_div_get_seting(unsigned long rate_out,unsigned long rate,
 519         u32 *numerator,u32 *denominator)
 520 {
 521         u32 gcd_vl;
 522         gcd_vl = clk_gcd(rate, rate_out);
 523         CRU_PRINTK_DBG("frac_get_seting rate=%lu,parent=%lu,gcd=%d\n",rate_out,rate, gcd_vl);
 524
 525         if (!gcd_vl) {
 526                 CRU_PRINTK_ERR("gcd=0, i2s frac div is not be supported\n");
 527                 return -ENOENT;
 528         }
 529
 530         *numerator = rate_out / gcd_vl;
 531         *denominator = rate/ gcd_vl;
 532
 533         CRU_PRINTK_DBG("frac_get_seting numerator=%d,denominator=%d,times=%d\n",
 534                         *numerator, *denominator, *denominator / *numerator);
 535
 536         if (*numerator > 0xffff || *denominator > 0xffff||
 537                 (*denominator/(*numerator))<20) {
 538                 CRU_PRINTK_ERR("can't get a available nume and deno\n");
 539                 return -ENOENT;
 540         }
 541
 542         return 0;
 543
 544 }
 545 /* *********************pll **************************/
 546
 547 #define rk30_clock_udelay(a) udelay(a);
 548
 549 /*********************pll lock status**********************************/
 550 //#define GRF_SOC_CON0       0x15c
 551 static void pll_wait_lock(int pll_idx)
 552 {
 553         u32 pll_state[4]={1,0,2,3};
 554         u32 bit = 0x10u << pll_state[pll_idx];
 555         int delay = 24000000;
 556         while (delay > 0) {
 557                 if (regfile_readl(GRF_SOC_STATUS0) & bit)
 558                         break;
 559                 delay--;
 560         }
 561         if (delay == 0) {
 562                 CRU_PRINTK_ERR("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\npll_con2=%08x\npll_con3=%08x\n", pll_idx,
 563                                 cru_readl(PLL_CONS(pll_idx, 0)),
 564                                 cru_readl(PLL_CONS(pll_idx, 1)),
 565                                 cru_readl(PLL_CONS(pll_idx, 2)),
 566                                 cru_readl(PLL_CONS(pll_idx, 3)));
 567
 568                 CRU_PRINTK_ERR("wait pll bit 0x%x time out!\n", bit);
 569                 while(1);
 570         }
 571 }
 572
 573
 574
 575 /***************************pll function**********************************/
 576 static unsigned long pll_clk_recalc(u32 pll_id,unsigned long parent_rate)
 577 {
 578         unsigned long rate;
 579
 580         if (PLLS_IN_NORM(pll_id)) {
 581                 u32 pll_con0 = cru_readl(PLL_CONS(pll_id,0));
 582                 u32 pll_con1 = cru_readl(PLL_CONS(pll_id,1));
 583
 584
 585                 u64 rate64 = (u64)parent_rate*PLL_NF(pll_con1);
 586
 587                 /*
 588                 CRU_PRINTK_DBG("selcon con0(%x) %x,con1(%x)%x, rate64 %llu\n",PLL_CONS(pll_id,0),pll_con0
 589                         ,PLL_CONS(pll_id,1),pll_con1, rate64);
 590                 */
 591
 592
 593                 //CRU_PRINTK_DBG("pll id=%d con0=%x,con1=%x,parent=%lu\n",pll_id,pll_con0,pll_con1,parent_rate);
 594         //CRU_PRINTK_DBG("first pll id=%d rate is %lu (NF %d NR %d NO %d)\n",
 595                 //pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0), 1 << PLL_NO(pll_con0));
 596
 597                 do_div(rate64, PLL_NR(pll_con0));
 598                 do_div(rate64, PLL_NO(pll_con0));
 599
 600                 rate = rate64;
 601                 /*
 602                 CRU_PRINTK_DBG("pll_clk_recalc id=%d rate=%lu (NF %d NR %d NO %d) rate64=%llu\n",
 603                         pll_id, rate, PLL_NF(pll_con1), PLL_NR(pll_con0),PLL_NO(pll_con0), rate64);
 604                 */
 605         } else {
 606                 rate = parent_rate;
 607                 CRU_PRINTK_DBG("pll_clk_recalc id=%d rate=%lu by pass mode\n",pll_id,rate);
 608         }
 609         return rate;
 610 }
 611 static unsigned long plls_clk_recalc(struct clk *clk)
 612 {
 613         return pll_clk_recalc(clk->pll->id,clk->parent->rate);
 614 }
 615
 616 static int pll_clk_set_rate(struct pll_clk_set *clk_set,u8 pll_id)
 617 {
 618         //enter slowmode
 619         cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 620         //enter rest
 621         cru_writel(PLL_REST_W_MSK|PLL_REST, PLL_CONS(pll_id,3));
 622         cru_writel(clk_set->pllcon0, PLL_CONS(pll_id,0));
 623         cru_writel(clk_set->pllcon1, PLL_CONS(pll_id,1));
 624         cru_writel(clk_set->pllcon2, PLL_CONS(pll_id,2));
 625         rk30_clock_udelay(5);
 626
 627         //return form rest
 628         cru_writel(PLL_REST_W_MSK|PLL_REST_RESM, PLL_CONS(pll_id,3));
 629
 630         //wating lock state
 631         rk30_clock_udelay(clk_set->rst_dly);
 632         pll_wait_lock(pll_id);
 633
 634         //return form slow
 635         cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 636
 637         /*
 638         CRU_PRINTK_ERR("pll reg id=%d,con0=%x,con1=%x,mode=%x\n",pll_id,
 639                 cru_readl(PLL_CONS(pll_id,0)),(PLL_CONS(pll_id,1)),cru_readl(CRU_MODE_CON));
 640         */
 641
 642
 643         return 0;
 644 }
 645 static int gpll_clk_set_rate(struct clk *c, unsigned long rate)
 646 {
 647         struct _pll_data *pll_data=c->pll;
 648         struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
 649
 650         while(clk_set->rate)
 651         {
 652                 if (clk_set->rate == rate) {
 653                         break;
 654                 }
 655                 clk_set++;
 656         }
 657         if(clk_set->rate== rate)
 658         {
 659                 pll_clk_set_rate(clk_set,pll_data->id);
 660                 lpj_gpll = CLK_LOOPS_RECALC(rate);
 661         }
 662         else
 663         {
 664                 CRU_PRINTK_ERR("gpll is no corresponding rate=%lu\n", rate);
 665                 return -1;
 666         }
 667         return 0;
 668 }
 669
 670 #define PLL_FREF_MIN (183*KHZ)
 671 #define PLL_FREF_MAX (1500*MHZ)
 672
 673 #define PLL_FVCO_MIN (300*MHZ)
 674 #define PLL_FVCO_MAX (1500*MHZ)
 675
 676 #define PLL_FOUT_MIN (18750*KHZ)
 677 #define PLL_FOUT_MAX (1500*MHZ)
 678
 679 #define PLL_NF_MAX (4096)
 680 #define PLL_NR_MAX (64)
 681 #define PLL_NO_MAX (16)
 682
 683 static int pll_clk_get_set(unsigned long fin_hz,unsigned long fout_hz,u32 *clk_nr,u32 *clk_nf,u32 *clk_no)
 684 {
 685         u32 nr,nf,no,nonr;
 686         u32 n;
 687         u32 YFfenzi;
 688         u32 YFfenmu;
 689         unsigned long fref,fvco,fout;
 690         u32 gcd_val=0;
 691
 692         CRU_PRINTK_DBG("pll_clk_get_set fin=%lu,fout=%lu\n",fin_hz,fout_hz);
 693         if(!fin_hz||!fout_hz||fout_hz==fin_hz)
 694                 return 0;
 695         gcd_val=clk_gcd(fin_hz,fout_hz);
 696         YFfenzi=fout_hz/gcd_val;
 697         YFfenmu=fin_hz/gcd_val;
 698
 699         for(n=1;;n++)
 700         {
 701                 nf=YFfenzi*n;
 702                 nonr=YFfenmu*n;
 703                 if(nf>PLL_NF_MAX||nonr>(PLL_NO_MAX*PLL_NR_MAX))
 704                  break;
 705                 for(no=1;no<=PLL_NO_MAX;no++)
 706                 {
 707                         if(!(no==1||!(no%2)))
 708                                 continue;
 709
 710                         if(nonr%no)
 711                                 continue;
 712                         nr=nonr/no;
 713
 714                         if(nr>PLL_NR_MAX)//PLL_NR_MAX
 715                                 continue;
 716
 717                         fref=fin_hz/nr;
 718                         if(fref<PLL_FREF_MIN||fref>PLL_FREF_MAX)
 719                                 continue;
 720
 721                         fvco=(fin_hz/nr)*nf;
 722                         if(fvco<PLL_FVCO_MIN||fvco>PLL_FVCO_MAX)
 723                                 continue;
 724                         fout=fvco/no;
 725                         if(fout<PLL_FOUT_MIN||fout>PLL_FOUT_MAX)
 726                                 continue;
 727                         *clk_nr=nr;
 728                         *clk_no=no;
 729                         *clk_nf=nf;
 730                         return 1;
 731
 732                 }
 733
 734         }
 735         return 0;
 736 }
 737
 738 static int pll_clk_mode(struct clk *clk, int on)
 739 {
 740         u8 pll_id=clk->pll->id;
 741         u32 nr=PLL_NR(cru_readl(PLL_CONS(pll_id,0)));
 742         u32 dly= (nr*500)/24+1;
 743         CRU_PRINTK_DBG("pll_mode %s(%d)",clk->name,on);
 744         if (on) {
 745                 cru_writel(PLL_PWR_ON|PLL_PWR_DN_W_MSK,PLL_CONS(pll_id,3));
 746                 rk30_clock_udelay(dly);
 747                 pll_wait_lock(pll_id);
 748                 cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
 749         } else {
 750                 cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
 751                 cru_writel(PLL_PWR_DN|PLL_PWR_DN_W_MSK, PLL_CONS(pll_id,3));
 752         }
 753         return 0;
 754 }
 755
 756 static int cpll_clk_set_rate(struct clk *c, unsigned long rate)
 757 {
 758         struct _pll_data *pll_data=c->pll;
 759         struct pll_clk_set *clk_set=(struct pll_clk_set*)pll_data->table;
 760         struct pll_clk_set temp_clk_set;
 761         u32 clk_nr,clk_nf,clk_no;
 762
 763
 764         while(clk_set->rate)
 765         {
 766                 if (clk_set->rate == rate) {
 767                         break;
 768                 }
 769                 clk_set++;
 770         }
 771         if(clk_set->rate==rate)
 772         {
 773                 CRU_PRINTK_DBG("cpll get a rate\n");
 774                 pll_clk_set_rate(clk_set,pll_data->id);
 775
 776         }
 777         else
 778         {
 779                 CRU_PRINTK_DBG("cpll get auto calc a rate\n");
 780                 if(pll_clk_get_set(c->parent->rate,rate,&clk_nr,&clk_nf,&clk_no)==0)
 781                 {
 782                         pr_err("cpll auto set rate error\n");
 783                         return -ENOENT;
 784                 }
 785                 CRU_PRINTK_DBG("cpll auto ger rate set nr=%d,nf=%d,no=%d\n",clk_nr,clk_nf,clk_no);
 786                 temp_clk_set.pllcon0=PLL_CLKR_SET(clk_nr)|PLL_CLKOD_SET(clk_no);
 787                 temp_clk_set.pllcon1=PLL_CLKF_SET(clk_nf);
 788                 temp_clk_set.pllcon2=PLL_CLK_BWADJ_SET(clk_nf/2-1);
 789                 temp_clk_set.rst_dly=(clk_nr*500)/24+1;
 790                 pll_clk_set_rate(&temp_clk_set,pll_data->id);
 791
 792         }
 793         return 0;
 794 }
 795
 796
 797 /* ******************fixed input clk ***********************************************/
 798 static struct clk xin24m = {
 799         .name           = "xin24m",
 800         .rate           = 24 * MHZ,
 801         .flags          = RATE_FIXED,
 802 };
 803 static struct clk xin27m = {
 804         .name           = "xin27m",
 805         .rate           = 27 * MHZ,
 806         //CLK_GATE_XIN27M
 807         .flags          = RATE_FIXED,
 808
 809 };
 810 static struct clk clk_12m = {
 811         .name           = "clk_12m",
 812         .parent         =&xin24m,
 813         .rate           = 12 * MHZ,
 814         .flags          = RATE_FIXED,
 815 };
 816
 817 /************************************pll func***************************/
 818 static const struct apll_clk_set* arm_pll_clk_get_best_pll_set(unsigned long rate,
 819         struct apll_clk_set *tables)
 820 {
 821         const struct apll_clk_set *ps, *pt;
 822
 823         /* find the arm_pll we want. */
 824         ps = pt = tables;
 825         while (pt->rate) {
 826                 if (pt->rate == rate) {
 827                         ps = pt;
 828                         break;
 829                 }
 830                 // we are sorted, and ps->rate > pt->rate.
 831                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 832                         ps = pt;
 833                 if (pt->rate < rate)
 834                         break;
 835                 pt++;
 836         }
 837         //CRU_PRINTK_DBG("arm pll best rate=%lu\n",ps->rate);
 838         return ps;
 839 }
 840 static long arm_pll_clk_round_rate(struct clk *clk, unsigned long rate)
 841 {
 842         return arm_pll_clk_get_best_pll_set(rate,clk->pll->table)->rate;
 843 }
 844 #if 1
 845 struct arm_clks_div_set {
 846         u32 rate;
 847         u32     clksel0;
 848         u32     clksel1;
 849 };
 850
 851 #define _arm_clks_div_set(_mhz,_periph_div,_axi_div,_ahb_div, _apb_div,_ahb2apb) \
 852         { \
 853         .rate    =_mhz,\
 854         .clksel0 = CORE_PERIPH_W_MSK|CORE_PERIPH_##_periph_div,\
 855         .clksel1 = CORE_ACLK_W_MSK|CORE_ACLK_##_axi_div\
 856         |ACLK_HCLK_W_MSK|ACLK_HCLK_##_ahb_div\
 857         |ACLK_PCLK_W_MSK|ACLK_PCLK_##_apb_div\
 858         |AHB2APB_W_MSK  |AHB2APB_##_ahb2apb,\
 859 }
 860 struct arm_clks_div_set arm_clk_div_tlb[]={
 861         _arm_clks_div_set(50 ,  2, 11, 11, 11, 11),//25,50,50,50,50
 862         _arm_clks_div_set(100 , 4, 11, 21, 21, 11),//25,100,50,50,50
 863         _arm_clks_div_set(150 , 4, 11, 21, 21, 11),//37,150,75,75,75
 864         _arm_clks_div_set(200 , 8, 21, 21, 21, 11),//25,100,50,50,50
 865         _arm_clks_div_set(300 , 8, 21, 21, 21, 11),//37,150,75,75,75
 866         _arm_clks_div_set(400 , 8, 21, 21, 41, 21),//50,200,100,50,50
 867         _arm_clks_div_set(0 ,   2, 11, 11, 11, 11),//25,50,50,50,50
 868 };
 869 struct arm_clks_div_set * arm_clks_get_div(u32 rate)
 870 {
 871         int i=0;
 872         for(i=0;arm_clk_div_tlb[i].rate!=0;i++)
 873         {
 874                 if(arm_clk_div_tlb[i].rate>=rate)
 875                         return &arm_clk_div_tlb[i];
 876         }
 877         return NULL;
 878 }
 879
 880 #endif
 881
 882 static u32 force_cpu_hpclk_11(u32 clksel1)
 883 {
 884         u8 p_bits=(clksel1&ACLK_PCLK_MSK)>>ACLK_PCLK_OFF;
 885         if(p_bits<3)
 886         {
 887                 return ((clksel1&(~(ACLK_HCLK_MSK|AHB2APB_MSK)))|AHB2APB_11|(p_bits<<ACLK_HCLK_OFF));
 888         }
 889         else
 890         {
 891                 return clksel1;
 892         }
 893
 894 }
 895 static int arm_pll_clk_set_rate(struct clk *clk, unsigned long rate)
 896 {
 897         unsigned long flags;
 898         const struct apll_clk_set *ps;
 899         u32 pll_id=clk->pll->id;
 900         u32 temp_div;
 901         u32 old_aclk_div=0,new_aclk_div,gpll_arm_aclk_div;
 902         struct arm_clks_div_set *temp_clk_div;
 903         unsigned long arm_gpll_rate, arm_gpll_lpj;
 904         u32 ps_clksel1;
 905
 906         ps = arm_pll_clk_get_best_pll_set(rate,(struct apll_clk_set *)clk->pll->table);
 907
 908         old_aclk_div=GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
 909         new_aclk_div=GET_CORE_ACLK_VAL(ps->clksel1&CORE_ACLK_MSK);
 910
 911         CRU_PRINTK_LOG("apll will set rate(%lu) tlb con(%x,%x,%x),sel(%x,%x)\n",
 912                 ps->rate,ps->pllcon0,ps->pllcon1,ps->pllcon2,ps->clksel0,ps->clksel1);
 913
 914         //rk30_l2_cache_latency(ps->rate/MHZ);
 915
 916         if(general_pll_clk.rate>clk->rate)
 917         {
 918                 temp_div=clk_get_freediv(clk->rate,general_pll_clk.rate,10);
 919         }
 920         else
 921         {
 922                 temp_div=1;
 923         }
 924         //sel gpll
 925         //cru_writel(CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
 926
 927         arm_gpll_rate=general_pll_clk.rate/temp_div;
 928         arm_gpll_lpj = lpj_gpll / temp_div;
 929         temp_clk_div=arm_clks_get_div(arm_gpll_rate/MHZ);
 930         if(!temp_clk_div)
 931                 temp_clk_div=&arm_clk_div_tlb[4];
 932         if(rk30_clock_flags&CLK_CPU_HPCLK_11)
 933         {
 934                 temp_clk_div->clksel1=force_cpu_hpclk_11(temp_clk_div->clksel1);
 935         }
 936
 937         gpll_arm_aclk_div=GET_CORE_ACLK_VAL(temp_clk_div->clksel1&CORE_ACLK_MSK);
 938
 939         CRU_PRINTK_LOG("gpll_arm_rate=%lu,sel rate%u,sel0%x,sel1%x\n",arm_gpll_rate,temp_clk_div->rate,
 940                                         temp_clk_div->clksel0,temp_clk_div->clksel1);
 941
 942         local_irq_save(flags);
 943         //new div max first
 944         if(gpll_arm_aclk_div>=old_aclk_div)
 945         {
 946                 if((old_aclk_div==3||gpll_arm_aclk_div==3)&&(gpll_arm_aclk_div!=old_aclk_div))
 947                 {
 948                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 949                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 950                         cru_writel((temp_clk_div->clksel0|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK),
 951                                                                                                 CRU_CLKSELS_CON(0));
 952                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 953                 }
 954                 else
 955                 {
 956                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 957                         cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
 958                                                                                 CRU_CLKSELS_CON(0));
 959                 }
 960         }
 961         // open gpu gpll path
 962         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH)|CLK_UN_GATE(CLK_GATE_CPU_GPLL_PATH),CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
 963         cru_writel(CORE_SEL_GPLL|CORE_SEL_PLL_W_MSK, CRU_CLKSELS_CON(0));
 964         loops_per_jiffy = arm_gpll_lpj;
 965         smp_wmb();
 966         //new div max late
 967         if(gpll_arm_aclk_div<old_aclk_div)
 968         {
 969                 if((old_aclk_div==3||gpll_arm_aclk_div==3)&&(gpll_arm_aclk_div!=old_aclk_div))
 970                 {
 971                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 972                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 973                         cru_writel((temp_clk_div->clksel0|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK),
 974                                                                                                 CRU_CLKSELS_CON(0));
 975                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
 976                 }
 977                 else
 978                 {
 979                         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
 980                         cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
 981                                                                                 CRU_CLKSELS_CON(0));
 982                 }
 983         }
 984
 985         /*if core src don't select gpll ,apll neet to enter slow mode */
 986         //cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
 987
 988         //enter rest
 989         cru_writel(PLL_REST_W_MSK|PLL_REST, PLL_CONS(pll_id,3));
 990         cru_writel(ps->pllcon0, PLL_CONS(pll_id,0));
 991         cru_writel(ps->pllcon1, PLL_CONS(pll_id,1));
 992         cru_writel(ps->pllcon2, PLL_CONS(pll_id,2));
 993
 994         rk30_clock_udelay(5);
 995
 996         //return form rest
 997         cru_writel(PLL_REST_W_MSK|PLL_REST_RESM, PLL_CONS(pll_id,3));
 998
 999         //wating lock state
1000         ///rk30_clock_udelay(ps->rst_dly);//lcdc flash
1001
1002         pll_wait_lock(pll_id);
1003
1004         if(rk30_clock_flags&CLK_CPU_HPCLK_11)
1005         {
1006                 ps_clksel1=force_cpu_hpclk_11(ps->clksel1);
1007         }
1008         else
1009         {
1010                 ps_clksel1=ps->clksel1;
1011         }
1012         //return form slow
1013         //cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1014         //a/h/p clk sel
1015    if(new_aclk_div>=gpll_arm_aclk_div)
1016    {
1017                 if((gpll_arm_aclk_div==3||new_aclk_div==3)&&(new_aclk_div!=gpll_arm_aclk_div))
1018                 {
1019                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1020                         cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
1021                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
1022                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1023                 }
1024                 else
1025                 {
1026                         cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
1027                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
1028                 }
1029         }
1030
1031         //reparent to apll
1032         cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_APLL, CRU_CLKSELS_CON(0));
1033         loops_per_jiffy = ps->lpj;
1034         smp_wmb();
1035
1036    if(new_aclk_div<gpll_arm_aclk_div)
1037    {
1038                 if((gpll_arm_aclk_div==3||new_aclk_div==3)&&(new_aclk_div!=gpll_arm_aclk_div))
1039                 {
1040                         cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
1041                         cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
1042                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
1043                         cru_writel(PLL_MODE_NORM(APLL_ID), CRU_MODE_CON);
1044                 }
1045                 else
1046                 {
1047                         cru_writel((ps_clksel1), CRU_CLKSELS_CON(1));
1048                         cru_writel((ps->clksel0)|CORE_CLK_DIV(1)|CORE_CLK_DIV_W_MSK, CRU_CLKSELS_CON(0));
1049                 }
1050         }
1051         //CRU_PRINTK_DBG("apll set loops_per_jiffy =%lu,rate(%lu)\n",loops_per_jiffy,ps->rate);
1052
1053         local_irq_restore(flags);
1054
1055         //gate gpll path
1056         cru_writel(CLK_GATE_W_MSK(CLK_GATE_CPU_GPLL_PATH)|CLK_GATE(CLK_GATE_CPU_GPLL_PATH)
1057         , CLK_GATE_CLKID_CONS(CLK_GATE_CPU_GPLL_PATH));
1058
1059         CRU_PRINTK_LOG("apll set over con(%x,%x,%x,%x),sel(%x,%x)\n",cru_readl(PLL_CONS(pll_id,0)),
1060                 cru_readl(PLL_CONS(pll_id,1)),cru_readl(PLL_CONS(pll_id,2)),
1061                 cru_readl(PLL_CONS(pll_id,3)),cru_readl(CRU_CLKSELS_CON(0)),
1062                 cru_readl(CRU_CLKSELS_CON(1)));
1063         return 0;
1064 }
1065
1066
1067 /************************************pll clocks***************************/
1068
1069 static const struct apll_clk_set apll_clks[] = {
1070         //rate, nr ,nf ,no,core_div,peri,axi,hclk,pclk,_ahb2apb
1071         //_APLL_SET_CLKS(1800, 1, 75, 1, 8, 41,  41,  81,21),
1072         //_APLL_SET_CLKS(1752, 1, 73, 1, 8, 41,  41,  81,21),
1073         //_APLL_SET_CLKS(1704, 1, 71, 1, 8, 41,  41,  81,21),
1074         //_APLL_SET_CLKS(1656, 1, 69, 1, 8, 41,  41,  81,21),
1075         _APLL_SET_CLKS(1608, 1, 67, 1, 8, 41, 21, 41, 21),
1076         _APLL_SET_CLKS(1560, 1, 65, 1, 8, 41, 21, 41, 21),
1077         _APLL_SET_CLKS(1512, 1, 63, 1, 8, 41, 21, 41, 21),
1078         _APLL_SET_CLKS(1464, 1, 61, 1, 8, 41, 21, 41, 21),
1079         _APLL_SET_CLKS(1416, 1, 59, 1, 8, 41, 21, 41, 21),
1080         _APLL_SET_CLKS(1368, 1, 57, 1, 8, 41, 21, 41, 21),
1081         _APLL_SET_CLKS(1320, 1, 55, 1, 8, 41, 21, 41, 21),
1082         _APLL_SET_CLKS(1296, 1, 54, 1, 8, 41, 21, 41, 21),
1083         _APLL_SET_CLKS(1272, 1, 53, 1, 8, 41, 21, 41, 21),
1084         _APLL_SET_CLKS(1200, 1, 50, 1, 8, 41, 21, 41, 21),
1085         _APLL_SET_CLKS(1176, 1, 49, 1, 8, 41, 21, 41, 21),
1086         _APLL_SET_CLKS(1128, 1, 47, 1, 8, 41, 21, 41, 21),
1087         _APLL_SET_CLKS(1104, 1, 46, 1, 8, 41, 21, 41, 21),
1088         _APLL_SET_CLKS(1008, 1, 42, 1, 8, 31, 21, 41, 21),
1089         _APLL_SET_CLKS(888,  1, 37, 1, 8, 31, 21, 41, 21),
1090         _APLL_SET_CLKS(816 , 1, 34, 1, 8, 31, 21, 41, 21),
1091         _APLL_SET_CLKS(792 , 1, 33, 1, 8, 31, 21, 41, 21),
1092         _APLL_SET_CLKS(696 , 1, 29, 1, 8, 31, 21, 41, 21),
1093         _APLL_SET_CLKS(600 , 1, 25, 1, 4, 31, 21, 41, 21),
1094         _APLL_SET_CLKS(504 , 1, 21, 1, 4, 21, 21, 41, 21),
1095         _APLL_SET_CLKS(408 , 1, 17, 1, 4, 21, 21, 41, 21),
1096         _APLL_SET_CLKS(312 , 1, 13, 1, 2, 21, 21, 21, 11),
1097         _APLL_SET_CLKS(252 , 1, 21, 2, 2, 21, 21, 21, 11),
1098         _APLL_SET_CLKS(216 , 1, 18, 2, 2, 21, 21, 21, 11),
1099         _APLL_SET_CLKS(126 , 1, 21, 4, 2, 21, 11, 11, 11),
1100         _APLL_SET_CLKS(48  , 1, 16, 8, 2, 11, 11, 11, 11),
1101         _APLL_SET_CLKS(0   , 1, 21, 4, 2, 21, 21, 41, 21),
1102
1103 };
1104 static struct _pll_data apll_data=SET_PLL_DATA(APLL_ID,(void *)apll_clks);
1105 static struct clk arm_pll_clk ={
1106         .name           = "arm_pll",
1107         .parent         = &xin24m,
1108         .mode = pll_clk_mode,
1109         .recalc         = plls_clk_recalc,
1110         .set_rate       = arm_pll_clk_set_rate,
1111         .round_rate     = arm_pll_clk_round_rate,
1112         .pll=&apll_data,
1113  };
1114
1115 static int ddr_pll_clk_set_rate(struct clk *clk, unsigned long rate)
1116 {
1117         /* do nothing here */
1118         return 0;
1119 }
1120 static struct _pll_data dpll_data=SET_PLL_DATA(DPLL_ID,NULL);
1121 static struct clk ddr_pll_clk = {
1122         .name           = "ddr_pll",
1123         .parent         = &xin24m,
1124         .recalc         = plls_clk_recalc,
1125         .set_rate       = ddr_pll_clk_set_rate,
1126         .pll=&dpll_data,
1127 };
1128
1129 static const struct pll_clk_set cpll_clks[] = {
1130         _PLL_SET_CLKS(360000, 1,  15, 1),
1131         _PLL_SET_CLKS(408000, 1,  17, 1),
1132         _PLL_SET_CLKS(456000, 1,  19, 1),
1133         _PLL_SET_CLKS(504000, 1,  21, 1),
1134         _PLL_SET_CLKS(552000, 1,  23, 1),
1135         _PLL_SET_CLKS(600000, 1,  25, 1),
1136         _PLL_SET_CLKS(742500, 8,  495, 2),
1137         _PLL_SET_CLKS(768000, 1,  32, 1),
1138         _PLL_SET_CLKS(798000, 4,  133, 1),
1139         _PLL_SET_CLKS(1188000,2,  99,   1),
1140         _PLL_SET_CLKS(     0, 4,  133, 1),
1141 };
1142 static struct _pll_data cpll_data=SET_PLL_DATA(CPLL_ID,(void *)cpll_clks);
1143 static struct clk codec_pll_clk = {
1144         .name           = "codec_pll",
1145         .parent         = &xin24m,
1146         .mode           = pll_clk_mode,
1147         .recalc         = plls_clk_recalc,
1148         .set_rate       = cpll_clk_set_rate,
1149         .pll= &cpll_data,
1150 };
1151
1152 static const struct pll_clk_set gpll_clks[] = {
1153         _PLL_SET_CLKS(148500,   4,      99,     4),
1154         _PLL_SET_CLKS(297000,   2,      99,     4),
1155         _PLL_SET_CLKS(300000,   1,      25,     2),
1156         _PLL_SET_CLKS(1188000,  2,      99,     1),
1157         _PLL_SET_CLKS(0,        0,       0,     0),
1158 };
1159 static struct _pll_data gpll_data=SET_PLL_DATA(GPLL_ID,(void *)gpll_clks);
1160 static struct clk general_pll_clk = {
1161         .name           = "general_pll",
1162         .parent         = &xin24m,
1163         .recalc         = plls_clk_recalc,
1164         .set_rate       = gpll_clk_set_rate,
1165         .pll= &gpll_data
1166 };
1167 /********************************clocks***********************************/
1168 static int ddr_clk_set_rate(struct clk *c, unsigned long rate)
1169 {
1170         return 0;
1171 }
1172
1173 static long ddr_clk_round_rate(struct clk *clk, unsigned long rate)
1174 {
1175         return ddr_set_pll(rate/MHZ,0)*MHZ;
1176 }
1177 static unsigned long ddr_clk_recalc_rate(struct clk *clk)
1178 {
1179         u32 shift = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift);
1180         unsigned long rate = clk->parent->recalc(clk->parent)>> shift;
1181         pr_debug("%s new clock rate is %lu (shift %u)\n", clk->name, rate, shift);
1182         return rate;
1183 }
1184 static struct clk *clk_ddr_parents[2] = {&ddr_pll_clk, &general_pll_clk};
1185 static struct clk clk_ddr = {
1186         .name           = "ddr",
1187         .parent         = &ddr_pll_clk,
1188         .recalc         = ddr_clk_recalc_rate,
1189         .set_rate       = ddr_clk_set_rate,
1190         .round_rate     = ddr_clk_round_rate,
1191         .clksel_con     = CRU_CLKSELS_CON(26),
1192         //CRU_DIV_SET(0x3,0,4),
1193         //CRU_SRC_SET(1,8),
1194         //CRU_PARENTS_SET(clk_ddr_parents),
1195 };
1196 static int arm_core_clk_set_rate(struct clk *c, unsigned long rate)
1197 {
1198         int ret;
1199         //set arm pll div 1
1200         //set_cru_bits_w_msk(0,c->div_mask,c->div_shift,c->clksel_con);
1201
1202         ret = clk_set_rate_nolock(c->parent, rate);
1203         if (ret) {
1204                 CRU_PRINTK_ERR("Failed to change clk pll %s to %lu\n",c->name,rate);
1205                 return ret;
1206         }
1207         return 0;
1208 }
1209 static unsigned long arm_core_clk_get_rate(struct clk *c)
1210 {
1211         u32 div=(get_cru_bits(c->clksel_con,c->div_mask,c->div_shift)+1);
1212         //c->parent->rate=c->parent->recalc(c->parent);
1213         return c->parent->rate/div;
1214 }
1215 static long core_clk_round_rate(struct clk *clk, unsigned long rate)
1216 {
1217         u32 div=(get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1);
1218         return clk_round_rate_nolock(clk->parent,rate)/div;
1219 }
1220
1221 static int core_clksel_set_parent(struct clk *clk, struct clk *new_prt)
1222 {
1223
1224         u32 temp_div;
1225         struct clk *old_prt;
1226
1227         if(clk->parent==new_prt)
1228                 return 0;
1229         if (unlikely(!clk->parents))
1230                 return -EINVAL;
1231         CRU_PRINTK_DBG("%s,reparent %s\n",clk->name,new_prt->name);
1232         //arm
1233         old_prt=clk->parent;
1234
1235         if(clk->parents[0]==new_prt)
1236         {
1237                 new_prt->set_rate(new_prt,300*MHZ);
1238                 set_cru_bits_w_msk(0,clk->div_mask,clk->div_shift,clk->clksel_con);
1239         }
1240         else if(clk->parents[1]==new_prt)
1241         {
1242
1243                 if(new_prt->rate>old_prt->rate)
1244                 {
1245                         temp_div=clk_get_freediv(old_prt->rate,new_prt->rate,clk->div_max);
1246                         set_cru_bits_w_msk(temp_div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
1247                 }
1248                 set_cru_bits_w_msk(1,clk->src_mask,clk->src_shift,clk->clksel_con);
1249                 new_prt->set_rate(new_prt,300*MHZ);
1250         }
1251         else
1252                 return -1;
1253
1254
1255         return 0;
1256
1257 }
1258
1259 static int core_gpll_clk_set_rate(struct clk *c, unsigned long rate)
1260 {
1261         unsigned long flags;
1262         u32 pll_id=APLL_ID;
1263         u32 temp_div;
1264         u32 old_aclk_div=0,new_aclk_div;
1265         struct arm_clks_div_set *temp_clk_div;
1266         unsigned long arm_gpll_rate, arm_gpll_lpj;
1267         temp_div=clk_get_freediv(rate,c->parent->rate,c->div_max);
1268         arm_gpll_rate=c->parent->rate/temp_div;
1269
1270         temp_clk_div=arm_clks_get_div(arm_gpll_rate/MHZ);
1271         if(!temp_clk_div)
1272                 temp_clk_div=&arm_clk_div_tlb[4];
1273
1274         old_aclk_div=GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1))&CORE_ACLK_MSK);
1275         new_aclk_div=GET_CORE_ACLK_VAL(temp_clk_div->clksel1&CORE_ACLK_MSK);
1276         if(c->rate>=rate)
1277         {
1278                 arm_gpll_lpj = lpj_gpll / temp_div;
1279                 set_cru_bits_w_msk(temp_div-1,c->div_mask,c->div_shift,c->clksel_con);
1280         }
1281
1282         cru_writel((temp_clk_div->clksel1), CRU_CLKSELS_CON(1));
1283         cru_writel((temp_clk_div->clksel0)|CORE_CLK_DIV(temp_div)|CORE_CLK_DIV_W_MSK,
1284                                                                 CRU_CLKSELS_CON(0));
1285         if((c->rate<rate))
1286         {
1287                 arm_gpll_lpj = lpj_gpll / temp_div;
1288                 set_cru_bits_w_msk(temp_div-1,c->div_mask,c->div_shift,c->clksel_con);
1289         }
1290         return 0;
1291 }
1292 static unsigned long arm_core_gpll_clk_get_rate(struct clk *c)
1293 {
1294         return c->parent->rate;
1295 }
1296
1297 static struct clk clk_cpu_gpll_path = {
1298         .name   =  "cpu_gpll_path",
1299         .parent =  &general_pll_clk,
1300         .recalc =  arm_core_gpll_clk_get_rate,
1301         .set_rate = core_gpll_clk_set_rate,
1302         CRU_DIV_SET(0x1f,0,32),
1303         CRU_GATE_MODE_SET(gate_mode,CLK_GATE_CPU_GPLL_PATH),
1304 };
1305
1306
1307 static struct clk *clk_cpu_parents[2] = {&arm_pll_clk,&clk_cpu_gpll_path};
1308
1309 static struct clk clk_cpu = {
1310         .name   =  "cpu",
1311         .parent =  &arm_pll_clk,
1312         .set_rate =     arm_core_clk_set_rate,
1313         .recalc =  arm_core_clk_get_rate,
1314         .round_rate     = core_clk_round_rate,
1315         .set_parent = core_clksel_set_parent,
1316         .clksel_con     = CRU_CLKSELS_CON(0),
1317         CRU_DIV_SET(0x1f,0,32),
1318         CRU_SRC_SET(1,8),
1319         CRU_PARENTS_SET(clk_cpu_parents),
1320 };
1321 static unsigned long aclk_cpu_recalc(struct clk *clk)
1322 {
1323         unsigned long rate;
1324         u32 div = get_cru_bits(clk->clksel_con,clk->div_mask,clk->div_shift)+1;
1325
1326         BUG_ON(div > 5);
1327         if (div >= 5)
1328                 div = 8;
1329         rate = clk->parent->rate / div;
1330         pr_debug("%s new clock rate is %ld (div %d)\n", clk->name, rate, div);
1331
1332         return rate;
1333 };
1334 static struct clk core_periph = {
1335         .name           = "core_periph",
1336         .parent         = &clk_cpu,
1337         .recalc         = clksel_recalc_shift_2,
1338         .clksel_con     = CRU_CLKSELS_CON(0),
1339         CRU_DIV_SET(0x3,6,16),
1340 };
1341
1342 static struct clk aclk_cpu = {
1343         .name           = "aclk_cpu",
1344         .parent         = &clk_cpu,
1345         .recalc         = aclk_cpu_recalc,
1346         .clksel_con     = CRU_CLKSELS_CON(1),
1347         CRU_DIV_SET(0x7,0,8),
1348 };
1349
1350 static struct clk hclk_cpu = {
1351         .name           = "hclk_cpu",
1352         .parent         = &aclk_cpu,
1353         .recalc         = clksel_recalc_shift,
1354         //.set_rate     = clksel_set_rate_shift,
1355         .clksel_con     = CRU_CLKSELS_CON(1),
1356         CRU_DIV_SET(0x3,8,4),
1357
1358 };
1359
1360 static struct clk pclk_cpu = {
1361         .name           = "pclk_cpu",
1362         .parent         = &aclk_cpu,
1363         .recalc         = clksel_recalc_shift,
1364         //.set_rate     = clksel_set_rate_shift,
1365         .clksel_con     = CRU_CLKSELS_CON(1),
1366         CRU_DIV_SET(0x3,12,8),
1367 };
1368 static struct clk ahb2apb_cpu = {
1369         .name           = "ahb2apb",
1370         .parent         = &hclk_cpu,
1371         .recalc         = clksel_recalc_shift,
1372         .clksel_con     = CRU_CLKSELS_CON(1),
1373         CRU_DIV_SET(0x3,14,4),
1374 };
1375
1376
1377 static struct clk atclk_cpu = {
1378         .name           = "atclk_cpu",
1379         .parent         = &pclk_cpu,
1380 };
1381
1382 static struct clk *clk_i2s_div_parents[]={&general_pll_clk,&codec_pll_clk};
1383 static struct clk clk_i2s_pll = {
1384         .name           = "i2s_pll",
1385         .parent         = &general_pll_clk,
1386         .clksel_con     = CRU_CLKSELS_CON(2),
1387         CRU_SRC_SET(0x1,16),
1388         CRU_PARENTS_SET(clk_i2s_div_parents),
1389 };
1390
1391 static struct clk clk_i2s0_div = {
1392         .name           = "i2s0_div",
1393         .parent = &clk_i2s_pll,
1394         .mode           = gate_mode,
1395         .recalc         = clksel_recalc_div,
1396         .set_rate       = clksel_set_rate_freediv,
1397         .round_rate     =clksel_freediv_round_rate,
1398         .gate_idx       = CLK_GATE_I2S0,
1399         .clksel_con     = CRU_CLKSELS_CON(2),
1400         CRU_DIV_SET(0x7f,0,64),
1401 };
1402
1403 static struct clk clk_i2s1_div = {
1404         .name           = "i2s1_div",
1405         .parent = &clk_i2s_pll,
1406         .recalc         = clksel_recalc_div,
1407         .set_rate       = clksel_set_rate_freediv,
1408         .round_rate     =clksel_freediv_round_rate,
1409         .mode           = gate_mode,
1410         .gate_idx       = CLK_GATE_I2S1,
1411         .clksel_con     = CRU_CLKSELS_CON(3),
1412         CRU_DIV_SET(0x7f,0,64),
1413 };
1414
1415
1416 static struct clk clk_i2s2_div = {
1417         .name           = "i2s2_div",
1418         .parent = &clk_i2s_pll,
1419         .recalc         = clksel_recalc_div,
1420         .set_rate       = clksel_set_rate_freediv,
1421         .round_rate     =clksel_freediv_round_rate,
1422         .mode           = gate_mode,
1423         .gate_idx       = CLK_GATE_I2S2,
1424         .clksel_con     = CRU_CLKSELS_CON(4),
1425         CRU_DIV_SET(0x7f,0,64),
1426 };
1427 static struct clk clk_spdif_div = {
1428         .name           = "spdif_div",
1429         .parent = &clk_i2s_pll,
1430         .recalc         = clksel_recalc_div,
1431         .set_rate       = clksel_set_rate_freediv,
1432         .round_rate     =clksel_freediv_round_rate,
1433         .mode           = gate_mode,
1434         .gate_idx       = CLK_GATE_SPDIF,
1435         .clksel_con     = CRU_CLKSELS_CON(5),
1436         CRU_DIV_SET(0x7f,0,64),
1437 };
1438 static int clk_i2s_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1439 {
1440         u32 numerator, denominator;
1441         //clk_i2s_div->clk_i2s_pll->gpll/cpll
1442         //clk->parent->parent
1443         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1444                         &numerator,&denominator)==0)
1445         {
1446                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1447                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1448                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1449         }
1450         else
1451         {
1452                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1453                 return -ENOENT;
1454         }
1455         return 0;
1456 }
1457
1458
1459 static struct clk clk_i2s0_frac_div = {
1460         .name           = "i2s0_frac_div",
1461         .parent         = &clk_i2s0_div,
1462         .mode           = gate_mode,
1463         .gate_idx       = CLK_GATE_I2S0_FRAC,
1464         .recalc         = clksel_recalc_frac,
1465         .set_rate       = clk_i2s_fracdiv_set_rate,
1466         .clksel_con     = CRU_CLKSELS_CON(6),
1467 };
1468
1469 static struct clk clk_i2s1_frac_div = {
1470         .name           = "i2s1_frac_div",
1471         .parent         = &clk_i2s1_div,
1472         .mode           = gate_mode,
1473         .gate_idx       = CLK_GATE_I2S1_FRAC,
1474         .recalc         = clksel_recalc_frac,
1475         .set_rate       = clk_i2s_fracdiv_set_rate,
1476         .clksel_con     = CRU_CLKSELS_CON(7),
1477 };
1478
1479 static struct clk clk_i2s2_frac_div = {
1480         .name           = "i2s2_frac_div",
1481         .mode           = gate_mode,
1482         .gate_idx       = CLK_GATE_I2S2_FRAC,
1483         .parent         = &clk_i2s2_div,
1484         .recalc         = clksel_recalc_frac,
1485         .set_rate       = clk_i2s_fracdiv_set_rate,
1486         .clksel_con     = CRU_CLKSELS_CON(8),
1487 };
1488 static struct clk clk_spdif_frac_div = {
1489         .name           = "spdif_frac_div",
1490         .parent         = &clk_spdif_div,
1491         .mode           = gate_mode,
1492         .gate_idx       = CLK_GATE_SPDIF_FRAC,
1493         .recalc         = clksel_recalc_frac,
1494         .set_rate       = clk_i2s_fracdiv_set_rate,
1495         .clksel_con     = CRU_CLKSELS_CON(9),
1496 };
1497
1498 #define I2S_SRC_DIV  (0x0)
1499 #define I2S_SRC_FRAC  (0x1)
1500 #define I2S_SRC_12M  (0x2)
1501
1502 static int i2s_set_rate(struct clk *clk, unsigned long rate)
1503 {
1504         int ret = -EINVAL;
1505         struct clk *parent;
1506
1507         if (rate == clk->parents[I2S_SRC_12M]->rate){
1508                 parent = clk->parents[I2S_SRC_12M];
1509         }else if((long)clk_round_rate_nolock(clk->parents[I2S_SRC_DIV],rate)==rate)
1510         {
1511                 parent = clk->parents[I2S_SRC_DIV];
1512         }
1513         else
1514         {
1515                 parent =clk->parents[I2S_SRC_FRAC];
1516         }
1517
1518         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
1519                 clk->name,rate,parent->name,clk->parent->name);
1520
1521         if(parent!=clk->parents[I2S_SRC_12M])
1522         {
1523                 ret = clk_set_rate_nolock(parent,rate);//div 1:1
1524                 if (ret)
1525                 {
1526                         CRU_PRINTK_DBG("%s set rate%lu err\n",clk->name,rate);
1527                         return ret;
1528                 }
1529         }
1530
1531         if (clk->parent != parent)
1532         {
1533                 ret = clk_set_parent_nolock(clk, parent);
1534                 if (ret)
1535                 {
1536                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
1537                         return ret;
1538                 }
1539         }
1540
1541         return ret;
1542 };
1543
1544 static struct clk *clk_i2s0_parents[3]={&clk_i2s0_div,&clk_i2s0_frac_div,&clk_12m};
1545
1546 static struct clk clk_i2s0 = {
1547         .name           = "i2s0",
1548         .set_rate       = i2s_set_rate,
1549         .clksel_con     = CRU_CLKSELS_CON(2),
1550         CRU_SRC_SET(0x3,8),
1551         CRU_PARENTS_SET(clk_i2s0_parents),
1552 };
1553
1554 static struct clk *clk_i2s1_parents[3]={&clk_i2s1_div,&clk_i2s1_frac_div,&clk_12m};
1555
1556 static struct clk clk_i2s1 = {
1557         .name           = "i2s1",
1558         .set_rate       = i2s_set_rate,
1559         .clksel_con     = CRU_CLKSELS_CON(3),
1560         CRU_SRC_SET(0x3,8),
1561         CRU_PARENTS_SET(clk_i2s1_parents),
1562 };
1563
1564 static struct clk *clk_i2s2_parents[3]={&clk_i2s2_div,&clk_i2s2_frac_div,&clk_12m};
1565
1566 static struct clk clk_i2s2 = {
1567         .name           = "i2s2",
1568         .set_rate       = i2s_set_rate,
1569         .clksel_con     = CRU_CLKSELS_CON(4),
1570         CRU_SRC_SET(0x3,8),
1571         CRU_PARENTS_SET(clk_i2s2_parents),
1572 };
1573
1574 static struct clk *clk_spdif_parents[3]={&clk_spdif_div,&clk_spdif_frac_div,&clk_12m};
1575
1576 static struct clk clk_spdif = {
1577         .name           = "spdif",
1578         .parent         = &clk_spdif_frac_div,
1579         .set_rate       = i2s_set_rate,
1580         .clksel_con = CRU_CLKSELS_CON(5),
1581         CRU_SRC_SET(0x3,8),
1582         CRU_PARENTS_SET(clk_spdif_parents),
1583 };
1584
1585 static struct clk *aclk_periph_parents[2]={&general_pll_clk,&codec_pll_clk};
1586
1587 static struct clk aclk_periph = {
1588         .name           = "aclk_periph",
1589         .parent         = &general_pll_clk,
1590         .mode           = gate_mode,
1591         .gate_idx       = CLK_GATE_ACLK_PERIPH,
1592         .recalc         = clksel_recalc_div,
1593         .set_rate       = clksel_set_rate_freediv,
1594         .clksel_con     = CRU_CLKSELS_CON(10),
1595         CRU_DIV_SET(0x1f,0,32),
1596         CRU_SRC_SET(1,15),
1597         CRU_PARENTS_SET(aclk_periph_parents),
1598 };
1599 GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
1600
1601 static struct clk pclk_periph = {
1602         .name           = "pclk_periph",
1603         .parent         = &aclk_periph,
1604         .mode           = gate_mode,
1605         .gate_idx       = CLK_GATE_PCLK_PERIPH,
1606         .recalc         = clksel_recalc_shift,
1607         .set_rate       = clksel_set_rate_shift,
1608         .clksel_con     = CRU_CLKSELS_CON(10),
1609         CRU_DIV_SET(0x3,12,8),
1610 };
1611
1612 static struct clk hclk_periph = {
1613         .name           = "hclk_periph",
1614         .parent         = &aclk_periph,
1615         .mode           = gate_mode,
1616         .gate_idx       = CLK_GATE_HCLK_PERIPH,
1617         .recalc         = clksel_recalc_shift,
1618         .set_rate       = clksel_set_rate_shift,
1619         .clksel_con = CRU_CLKSELS_CON(10),
1620         CRU_DIV_SET(0x3,8,4),
1621 };
1622
1623 static struct clk clk_spi0 = {
1624         .name           = "spi0",
1625         .parent         = &pclk_periph,
1626         .mode           = gate_mode,
1627         .recalc         = clksel_recalc_div,
1628         .set_rate       = clksel_set_rate_freediv,
1629         .gate_idx       = CLK_GATE_SPI0,
1630         .clksel_con     = CRU_CLKSELS_CON(25),
1631         CRU_DIV_SET(0x7f,0,128),
1632 };
1633
1634 static struct clk clk_spi1 = {
1635         .name           = "spi1",
1636         .parent         = &pclk_periph,
1637         .mode           = gate_mode,
1638         .recalc         = clksel_recalc_div,
1639         .set_rate       = clksel_set_rate_freediv,
1640         .gate_idx       = CLK_GATE_SPI1,
1641         .clksel_con     = CRU_CLKSELS_CON(25),
1642         CRU_DIV_SET(0x7f,8,128),
1643 };
1644
1645 static struct clk clk_saradc = {
1646         .name           = "saradc",
1647         .parent         = &xin24m,
1648         .mode           = gate_mode,
1649         .recalc         = clksel_recalc_div,
1650         .set_rate       = clksel_set_rate_freediv,
1651         .gate_idx       =  CLK_GATE_SARADC,
1652         .clksel_con     =CRU_CLKSELS_CON(24),
1653         CRU_DIV_SET(0xff,8,256),
1654 };
1655 static struct clk clk_tsadc = {
1656         .name           = "tsadc",
1657         .parent         = &xin24m,
1658         .mode           = gate_mode,
1659         .recalc         = clksel_recalc_div,
1660         .set_rate       = clksel_set_rate_freediv,
1661         .gate_idx       = CLK_GATE_TSADC,
1662         .clksel_con =CRU_CLKSELS_CON(34),
1663         CRU_DIV_SET(0xffff,0,65536),
1664 };
1665 GATE_CLK(otgphy0, xin24m, OTGPHY0);
1666 GATE_CLK(otgphy1, xin24m, OTGPHY1);
1667
1668
1669 GATE_CLK(smc, pclk_periph, SMC);//smc
1670
1671 static struct clk clk_sdmmc = {
1672         .name           = "sdmmc",
1673         .parent         = &hclk_periph,
1674         .mode           = gate_mode,
1675         .recalc         = clksel_recalc_div,
1676         .set_rate       = clksel_set_rate_even,
1677         .gate_idx       = CLK_GATE_MMC0,
1678         .clksel_con =CRU_CLKSELS_CON(11),
1679         CRU_DIV_SET(0x3f,0,64),
1680 };
1681
1682 static struct clk clk_sdio = {
1683         .name           = "sdio",
1684         .parent         = &hclk_periph,
1685         .mode           = gate_mode,
1686         .recalc         = clksel_recalc_div,
1687         .set_rate       = clksel_set_rate_even,
1688         .gate_idx       = CLK_GATE_SDIO,
1689         .clksel_con =CRU_CLKSELS_CON(12),
1690         CRU_DIV_SET(0x3f,0,64),
1691
1692 };
1693
1694 static struct clk clk_emmc = {
1695         .name           = "emmc",
1696         .parent         = &hclk_periph,
1697         .mode           = gate_mode,
1698         .recalc         = clksel_recalc_div,
1699         .set_rate       = clksel_set_rate_freediv,
1700         .gate_idx       = CLK_GATE_EMMC,
1701         .clksel_con =CRU_CLKSELS_CON(12),
1702         CRU_DIV_SET(0x3f,8,64),
1703 };
1704
1705 static struct clk *clk_uart_src_parents[2]={&general_pll_clk,&codec_pll_clk};
1706 static struct clk clk_uart_pll = {
1707         .name           = "uart_pll",
1708         .parent         = &general_pll_clk,
1709         .clksel_con =CRU_CLKSELS_CON(12),
1710         CRU_SRC_SET(0x1,15),
1711         CRU_PARENTS_SET(clk_uart_src_parents),
1712 };
1713 static struct clk clk_uart0_div = {
1714         .name           = "uart0_div",
1715         .parent         = &clk_uart_pll,
1716         .mode           = gate_mode,
1717         .gate_idx       = CLK_GATE_UART0,
1718         .recalc         = clksel_recalc_div,
1719         .set_rate       = clksel_set_rate_freediv,
1720         .round_rate     =clksel_freediv_round_rate,
1721         .clksel_con     = CRU_CLKSELS_CON(13),
1722         CRU_DIV_SET(0x7f,0,64),
1723 };
1724 static struct clk clk_uart1_div = {
1725         .name           = "uart1_div",
1726         .parent         = &clk_uart_pll,
1727         .mode           = gate_mode,
1728         .gate_idx       = CLK_GATE_UART1,
1729         .recalc         = clksel_recalc_div,
1730         .round_rate     =clksel_freediv_round_rate,
1731         .set_rate       = clksel_set_rate_freediv,
1732         .clksel_con     = CRU_CLKSELS_CON(14),
1733         CRU_DIV_SET(0x7f,0,64),
1734 };
1735
1736 static struct clk clk_uart2_div = {
1737         .name           = "uart2_div",
1738         .parent         = &clk_uart_pll,
1739         .mode           = gate_mode,
1740         .gate_idx       = CLK_GATE_UART2,
1741         .recalc         = clksel_recalc_div,
1742         .round_rate     =clksel_freediv_round_rate,
1743         .set_rate       = clksel_set_rate_freediv,
1744         .clksel_con     = CRU_CLKSELS_CON(15),
1745         CRU_DIV_SET(0x7f,0,64),
1746 };
1747
1748 static struct clk clk_uart3_div = {
1749         .name           = "uart3_div",
1750         .parent         = &clk_uart_pll,
1751         .mode           = gate_mode,
1752         .gate_idx       = CLK_GATE_UART3,
1753         .recalc         = clksel_recalc_div,
1754         .round_rate     =clksel_freediv_round_rate,
1755         .set_rate       = clksel_set_rate_freediv,
1756         .clksel_con     = CRU_CLKSELS_CON(16),
1757         CRU_DIV_SET(0x7f,0,64),
1758 };
1759 static int clk_uart_fracdiv_set_rate(struct clk *clk, unsigned long rate)
1760 {
1761         u32 numerator, denominator;
1762         //clk_uart0_div->clk_uart_pll->gpll/cpll
1763         //clk->parent->parent
1764         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1765                         &numerator,&denominator)==0)
1766         {
1767                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1768
1769                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1770
1771                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1772         }
1773         else
1774         {
1775                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
1776                 return -ENOENT;
1777         }
1778         return 0;
1779 }
1780
1781 static struct clk clk_uart0_frac_div = {
1782         .name           = "uart0_frac_div",
1783         .parent         = &clk_uart0_div,
1784         .mode           = gate_mode,
1785         .recalc         = clksel_recalc_frac,
1786         .set_rate       = clk_uart_fracdiv_set_rate,
1787         .gate_idx       = CLK_GATE_FRAC_UART0,
1788         .clksel_con     = CRU_CLKSELS_CON(17),
1789 };
1790 static struct clk clk_uart1_frac_div = {
1791         .name           = "uart1_frac_div",
1792         .parent         = &clk_uart1_div,
1793         .mode           = gate_mode,
1794         .recalc         = clksel_recalc_frac,
1795         .set_rate       = clk_uart_fracdiv_set_rate,
1796         .gate_idx       = CLK_GATE_FRAC_UART1,
1797         .clksel_con     = CRU_CLKSELS_CON(18),
1798 };
1799 static struct clk clk_uart2_frac_div = {
1800         .name           = "uart2_frac_div",
1801         .mode           = gate_mode,
1802         .parent         = &clk_uart2_div,
1803         .recalc         = clksel_recalc_frac,
1804         .set_rate       = clk_uart_fracdiv_set_rate,
1805         .gate_idx       = CLK_GATE_FRAC_UART2,
1806         .clksel_con     = CRU_CLKSELS_CON(19),
1807 };
1808 static struct clk clk_uart3_frac_div = {
1809         .name           = "uart3_frac_div",
1810         .parent         = &clk_uart3_div,
1811         .mode           = gate_mode,
1812         .recalc         = clksel_recalc_frac,
1813         .set_rate       = clk_uart_fracdiv_set_rate,
1814         .gate_idx       = CLK_GATE_FRAC_UART3,
1815         .clksel_con     = CRU_CLKSELS_CON(20),
1816 };
1817
1818
1819 #define UART_SRC_DIV 0
1820 #define UART_SRC_FRAC 1
1821 #define UART_SRC_24M 2
1822
1823 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
1824 {
1825         int ret = 0;
1826         struct clk *parent;
1827
1828         if(rate==clk->parents[UART_SRC_24M]->rate)//24m
1829         {
1830                 parent = clk->parents[UART_SRC_24M];
1831         }
1832         else if((long)clk_round_rate_nolock(clk->parents[UART_SRC_DIV], rate)==rate)
1833         {
1834                 parent = clk->parents[UART_SRC_DIV];
1835         }
1836         else
1837         {
1838                 parent = clk->parents[UART_SRC_FRAC];
1839         }
1840
1841         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
1842                 clk->name,rate,parent->name,clk->parent->name);
1843
1844
1845         if(parent!=clk->parents[UART_SRC_24M])
1846         {
1847                 ret = clk_set_rate_nolock(parent,rate);
1848                 if (ret)
1849                 {
1850                         CRU_PRINTK_DBG("%s set rate%lu err\n",clk->name,rate);
1851                         return ret;
1852                 }
1853         }
1854
1855         if (clk->parent != parent)
1856         {
1857                 ret = clk_set_parent_nolock(clk, parent);
1858                 if (ret)
1859                 {
1860                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
1861                         return ret;
1862                 }
1863         }
1864
1865
1866         return ret;
1867 }
1868
1869
1870 static struct clk *clk_uart0_parents[3]={&clk_uart0_div,&clk_uart0_frac_div,&xin24m};
1871 static struct clk clk_uart0 = {
1872         .name           = "uart0",
1873         .set_rate       = clk_uart_set_rate,
1874         .clksel_con     = CRU_CLKSELS_CON(13),
1875         CRU_SRC_SET(0x3,8),
1876         CRU_PARENTS_SET(clk_uart0_parents),
1877 };
1878
1879 static struct clk *clk_uart1_parents[3]={&clk_uart1_div,&clk_uart1_frac_div,&xin24m};
1880 static struct clk clk_uart1 = {
1881         .name           = "uart1",
1882         .set_rate       = clk_uart_set_rate,
1883         .clksel_con     = CRU_CLKSELS_CON(14),
1884         CRU_SRC_SET(0x3,8),
1885         CRU_PARENTS_SET(clk_uart1_parents),
1886 };
1887
1888 static struct clk *clk_uart2_parents[3]={&clk_uart2_div,&clk_uart2_frac_div,&xin24m};
1889 static struct clk clk_uart2 = {
1890         .name           = "uart2",
1891         .set_rate       = clk_uart_set_rate,
1892         .clksel_con     = CRU_CLKSELS_CON(15),
1893         CRU_SRC_SET(0x3,8),
1894         CRU_PARENTS_SET(clk_uart2_parents),
1895 };
1896 static struct clk *clk_uart3_parents[3]={&clk_uart3_div,&clk_uart3_frac_div,&xin24m};
1897 static struct clk clk_uart3 = {
1898         .name           = "uart3",
1899         .set_rate       = clk_uart_set_rate,
1900         .clksel_con     = CRU_CLKSELS_CON(16),
1901         CRU_SRC_SET(0x3,8),
1902         CRU_PARENTS_SET(clk_uart3_parents),
1903 };
1904
1905 GATE_CLK(timer0, xin24m, TIMER0);
1906 GATE_CLK(timer1, xin24m, TIMER1);
1907 GATE_CLK(timer2, xin24m, TIMER2);
1908
1909 static struct clk rmii_clkin = {
1910         .name           = "rmii_clkin",
1911 };
1912 static struct clk *clk_mac_ref_div_parents[2]={&general_pll_clk,&ddr_pll_clk};
1913 static struct clk clk_mac_pll_div = {
1914         .name           = "mac_pll_div",
1915         .parent         = &ddr_pll_clk,
1916         .mode           = gate_mode,
1917         .gate_idx       = CLK_GATE_MAC,
1918         .recalc         = clksel_recalc_div,
1919         .set_rate       =clksel_set_rate_freediv,
1920         //.set_rate     = clksel_set_rate_freediv,
1921         .clksel_con     =CRU_CLKSELS_CON(21),
1922         CRU_DIV_SET(0x1f,8,32),
1923         CRU_SRC_SET(0x1,0),
1924         CRU_PARENTS_SET(clk_mac_ref_div_parents),
1925 };
1926
1927 static int clksel_mac_ref_set_rate(struct clk *clk, unsigned long rate)
1928 {
1929
1930         if(clk->parent==clk->parents[1])
1931         {
1932                 CRU_PRINTK_DBG("mac_ref clk is form mii clkin,can't set it\n" );
1933                 return -ENOENT;
1934         }
1935         else if(clk->parent==clk->parents[0])
1936         {
1937         return clk_set_rate_nolock(clk->parents[0],rate);
1938         }
1939         return -ENOENT;
1940 }
1941
1942 static struct clk *clk_mac_ref_parents[2]={&clk_mac_pll_div,&rmii_clkin};
1943
1944 static struct clk clk_mac_ref = {
1945         .name           = "mac_ref",
1946         .parent         = &clk_mac_pll_div,
1947         .set_rate       = clksel_mac_ref_set_rate,
1948         .clksel_con =CRU_CLKSELS_CON(21),
1949         CRU_SRC_SET(0x1,4),
1950         CRU_PARENTS_SET(clk_mac_ref_parents),
1951 };
1952
1953 static int clk_set_mii_tx_parent(struct clk *clk, struct clk *parent)
1954 {
1955         return clk_set_parent_nolock(clk->parent,parent);
1956 }
1957
1958 static struct clk clk_mii_tx = {
1959         .name           = "mii_tx",
1960         .parent         = &clk_mac_ref,
1961         //.set_parent   = clk_set_mii_tx_parent,
1962         .mode           = gate_mode,
1963         .gate_idx       = CLK_GATE_MAC_LBTEST,//???
1964 };
1965
1966 static struct clk *clk_hsadc_pll_parents[2]={&general_pll_clk,&codec_pll_clk};
1967 static struct clk clk_hsadc_pll_div = {
1968         .name           = "hsadc_pll_div",
1969         .parent         = &general_pll_clk,
1970         .mode           = gate_mode,
1971         .gate_idx       = CLK_GATE_SARADC,
1972         .recalc         = clksel_recalc_div,
1973         .round_rate     =clk_freediv_round_autosel_parents_rate,
1974         .set_rate       = clkset_rate_freediv_autosel_parents,
1975         //.round_rate =clksel_freediv_round_rate,
1976         //.set_rate     = clksel_set_rate_freediv,
1977         .clksel_con =CRU_CLKSELS_CON(22),
1978         CRU_DIV_SET(0xff,8,256),
1979         CRU_SRC_SET(0x1,0),
1980         CRU_PARENTS_SET(clk_hsadc_pll_parents),
1981 };
1982
1983 static int clk_hsadc_fracdiv_set_rate_fixed_parent(struct clk *clk, unsigned long rate)
1984 {
1985         u32 numerator, denominator;
1986         //        clk_hsadc_pll_div->gpll/cpll
1987         //clk->parent->parent
1988         if(frac_div_get_seting(rate,clk->parent->parent->rate,
1989                         &numerator,&denominator)==0)
1990         {
1991                 clk_set_rate_nolock(clk->parent,clk->parent->parent->rate);//PLL:DIV 1:
1992
1993                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
1994
1995                 CRU_PRINTK_DBG("%s set rate=%lu,is ok\n",clk->name,rate);
1996         }
1997         else
1998         {
1999                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
2000                 return -ENOENT;
2001         }
2002         return 0;
2003 }
2004 static int clk_hsadc_fracdiv_set_rate_auto_parents(struct clk *clk, unsigned long rate)
2005 {
2006         u32 numerator, denominator;
2007         u32 i,ret=0;
2008         //        clk_hsadc_pll_div->gpll/cpll
2009         //clk->parent->parent
2010         for(i=0;i<2;i++)
2011         {
2012                 if(frac_div_get_seting(rate,clk->parent->parents[i]->rate,
2013                         &numerator,&denominator)==0)
2014                         break;
2015         }
2016         if(i>=2)
2017                 return -ENOENT;
2018
2019         if(clk->parent->parent!=clk->parent->parents[i])
2020                 ret=clk_set_parent_nolock(clk->parent, clk->parent->parents[i]);
2021         if(ret==0)
2022         {
2023                 clk_set_rate_nolock(clk->parent,clk->parent->parents[i]->rate);//PLL:DIV 1:
2024
2025                 cru_writel_frac(numerator << 16 | denominator, clk->clksel_con);
2026
2027                 CRU_PRINTK_DBG("clk_frac_div %s, rate=%lu\n",clk->name,rate);
2028         }
2029         else
2030         {
2031                 CRU_PRINTK_ERR("clk_frac_div can't get rate=%lu,%s\n",rate,clk->name);
2032                 return -ENOENT;
2033         }
2034         return 0;
2035 }
2036
2037 static long clk_hsadc_fracdiv_round_rate(struct clk *clk, unsigned long rate)
2038 {
2039         u32 numerator, denominator;
2040
2041         CRU_PRINTK_ERR("clk_hsadc_fracdiv_round_rate\n");
2042         if(frac_div_get_seting(rate,clk->parent->parent->rate,
2043                         &numerator,&denominator)==0)
2044                 return rate;
2045
2046         return 0;
2047 }
2048 static struct clk clk_hsadc_frac_div = {
2049         .name           = "hsadc_frac_div",
2050         .parent         = &clk_hsadc_pll_div,
2051         .mode           = gate_mode,
2052         .recalc         = clksel_recalc_frac,
2053         .set_rate       = clk_hsadc_fracdiv_set_rate_auto_parents,
2054         .round_rate     =clk_hsadc_fracdiv_round_rate,
2055         .gate_idx       = CLK_GATE_HSADC_FRAC,
2056         .clksel_con     = CRU_CLKSELS_CON(23),
2057 };
2058
2059 #define HSADC_SRC_DIV 0x0
2060 #define HSADC_SRC_FRAC 0x1
2061 #define HSADC_SRC_EXT 0x2
2062 static int clk_hsadc_set_rate(struct clk *clk, unsigned long rate)
2063 {
2064         int ret = -EINVAL;
2065         struct clk *parent;
2066
2067         if(clk->parent == clk->parents[HSADC_SRC_EXT]){
2068                 CRU_PRINTK_DBG("hsadc clk is form ext\n");
2069                 return 0;
2070         }
2071         else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_DIV],rate)==rate)
2072         {
2073                 parent =clk->parents[HSADC_SRC_DIV];
2074         }
2075         else if((long)clk_round_rate_nolock(clk->parents[HSADC_SRC_FRAC],rate)==rate)
2076         {
2077                 parent = clk->parents[HSADC_SRC_FRAC];
2078         }
2079         else
2080                 parent =clk->parents[HSADC_SRC_DIV];
2081
2082         CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
2083                 clk->name,rate,parent->name,clk->parent->name);
2084
2085         ret = clk_set_rate_nolock(parent,rate);
2086         if (ret)
2087         {
2088                 CRU_PRINTK_ERR("%s set rate%lu err\n",clk->name,rate);
2089                 return ret;
2090         }
2091         if (clk->parent != parent)
2092         {
2093                 ret = clk_set_parent_nolock(clk, parent);
2094                 if (ret)
2095                 {
2096                         CRU_PRINTK_ERR("%s can't get rate%lu,reparent err\n",clk->name,rate);
2097                         return ret;
2098                 }
2099         }
2100         return ret;
2101 }
2102
2103 static struct clk clk_hsadc_ext = {
2104         .name           = "hsadc_ext",
2105 };
2106
2107 static struct clk *clk_hsadc_parents[3]={&clk_hsadc_pll_div,&clk_hsadc_frac_div,&clk_hsadc_ext};
2108 static struct clk clk_hsadc = {
2109         .name           = "hsadc",
2110         .parent         = &clk_hsadc_pll_div,
2111         .set_rate       = clk_hsadc_set_rate,
2112         .clksel_con     = CRU_CLKSELS_CON(22),
2113         CRU_SRC_SET(0x3,4),
2114         CRU_PARENTS_SET(clk_hsadc_parents),
2115 };
2116
2117 static struct clk *dclk_lcdc_div_parents[]={&codec_pll_clk,&general_pll_clk};
2118 static struct clk dclk_lcdc0_div = {
2119         .name           = "dclk_lcdc0_div",
2120         .parent         = &general_pll_clk,
2121         .recalc         = clksel_recalc_div,
2122         .set_rate       = clkset_rate_freediv_autosel_parents,
2123         .clksel_con     = CRU_CLKSELS_CON(27),
2124         CRU_DIV_SET(0xff,8,256),
2125         CRU_SRC_SET(0x1,0),
2126         CRU_PARENTS_SET(dclk_lcdc_div_parents),
2127 };
2128
2129 static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate)
2130 {
2131         u32 div,old_div;
2132         int i;
2133         unsigned long new_rate;
2134         int ret=0;
2135
2136         if(clk->rate==rate)
2137                 return 0;
2138         for(i=0;i<2;i++)
2139         {
2140                 div=clk_get_freediv(rate,clk->parents[i]->rate,clk->div_max);
2141                 new_rate= clk->parents[i]->rate/div;
2142                 if((rate==new_rate)&&!(clk->parents[i]->rate%div))
2143                 {
2144                         break;
2145                 }
2146         }
2147         if(i>=2)
2148         {
2149                 CRU_PRINTK_ERR("%s can't set fixed rate%lu\n",clk->name,rate);
2150                 return -1;
2151         }
2152
2153         //CRU_PRINTK_DBG("%s set rate %lu(from %s)\n",clk->name,rate,clk->parents[i]->name);
2154
2155         old_div=CRU_GET_REG_BIYS_VAL(cru_readl(clk->clksel_con),
2156                                                                                 clk->div_shift,clk->div_mask)+1;
2157         if(div>old_div)
2158                 set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
2159
2160         if(clk->parents[i]!=clk->parent)
2161         {
2162                 ret=clk_set_parent_nolock(clk,clk->parents[i]);
2163         }
2164
2165         if (ret)
2166         {
2167                 CRU_PRINTK_ERR("lcdc1 %s can't get rate%lu,reparent%s(now %s) err\n",
2168                         clk->name,rate,clk->parents[i]->name,clk->parent->name);
2169                 return ret;
2170         }
2171         set_cru_bits_w_msk(div-1,clk->div_mask,clk->div_shift,clk->clksel_con);
2172         return 0;
2173 }
2174 //hdmi
2175 static struct clk dclk_lcdc1_div = {
2176         .name           = "dclk_lcdc1_div",
2177         .parent         = &general_pll_clk,
2178         .recalc         = clksel_recalc_div,
2179         .set_rate       = clksel_set_rate_hdmi,//clk_freediv_autosel_parents_set_fixed_rate
2180         .clksel_con     = CRU_CLKSELS_CON(28),
2181         CRU_DIV_SET(0xff,8,256),
2182         CRU_SRC_SET(0x1,0),
2183         CRU_PARENTS_SET(dclk_lcdc_div_parents),
2184 };
2185
2186 static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
2187 {
2188         int ret = 0;
2189         struct clk *parent;
2190
2191         if (rate == 27 * MHZ&&(rk30_clock_flags&CLK_FLG_EXT_27MHZ)) {
2192                 parent =clk->parents[1];
2193                 //CRU_PRINTK_DBG(" %s from=%s\n",clk->name,parent->name);
2194         } else {
2195                 parent=clk->parents[0];
2196         }
2197         //CRU_PRINTK_DBG(" %s set rate=%lu parent %s(old %s)\n",
2198                         //clk->name,rate,parent->name,clk->parent->name);
2199
2200         if(parent!=clk->parents[1])
2201         {
2202                 ret = clk_set_rate_nolock(parent,rate);//div 1:1
2203                 if (ret)
2204                 {
2205                         CRU_PRINTK_DBG("%s set rate=%lu err\n",clk->name,rate);
2206                         return ret;
2207                 }
2208         }
2209         if (clk->parent != parent)
2210         {
2211                 ret = clk_set_parent_nolock(clk, parent);
2212                 if (ret)
2213                 {
2214                         CRU_PRINTK_DBG("%s can't get rate%lu,reparent err\n",clk->name,rate);
2215                         return ret;
2216                 }
2217         }
2218         return ret;
2219 }
2220
2221 static struct clk *dclk_lcdc0_parents[2]={&dclk_lcdc0_div,&xin27m};
2222 static struct clk dclk_lcdc0 = {
2223         .name           = "dclk_lcdc0",
2224         .mode           = gate_mode,
2225         .set_rate       = dclk_lcdc_set_rate,
2226         .gate_idx       = CLK_GATE_DCLK_LCDC0,
2227         .clksel_con     = CRU_CLKSELS_CON(27),
2228         CRU_SRC_SET(0x1,4),
2229         CRU_PARENTS_SET(dclk_lcdc0_parents),
2230 };
2231
2232 static struct clk *dclk_lcdc1_parents[2]={&dclk_lcdc1_div,&xin27m};
2233 static struct clk dclk_lcdc1 = {
2234         .name           = "dclk_lcdc1",
2235         .mode           = gate_mode,
2236         .set_rate       = dclk_lcdc_set_rate,
2237         .gate_idx       = CLK_GATE_DCLK_LCDC1,
2238         .clksel_con     = CRU_CLKSELS_CON(28),
2239         CRU_SRC_SET(0x1,4),
2240         CRU_PARENTS_SET(dclk_lcdc1_parents),
2241 };
2242
2243 static struct clk *cifout_sel_pll_parents[2]={&codec_pll_clk,&general_pll_clk};
2244 static struct clk cif_out_pll = {
2245         .name           = "cif_out_pll",
2246         .parent         = &general_pll_clk,
2247         .clksel_con     = CRU_CLKSELS_CON(29),
2248         CRU_SRC_SET(0x1,0),
2249         CRU_PARENTS_SET(cifout_sel_pll_parents),
2250 };
2251
2252 static struct clk cif0_out_div = {
2253         .name           = "cif0_out_div",
2254         .parent         = &cif_out_pll,
2255         .mode           = gate_mode,
2256         .recalc         = clksel_recalc_div,
2257         .set_rate       = clksel_set_rate_freediv,
2258         .gate_idx       =CLK_GATE_CIF0_OUT,
2259         .clksel_con     = CRU_CLKSELS_CON(29),
2260         CRU_DIV_SET(0x1f,1,32),
2261 };
2262
2263 static struct clk cif1_out_div = {
2264         .name           = "cif1_out_div",
2265         .parent         = &cif_out_pll,
2266         .mode           = gate_mode,
2267         .recalc         = clksel_recalc_div,
2268         .set_rate       = clksel_set_rate_freediv,
2269         .gate_idx       =       CLK_GATE_CIF1_OUT,
2270         .clksel_con     = CRU_CLKSELS_CON(29),
2271         CRU_DIV_SET(0x1f,8,32),
2272 };
2273
2274
2275 static int cif_out_set_rate(struct clk *clk, unsigned long rate)
2276 {
2277         int ret = 0;
2278         struct clk *parent;
2279
2280         if (rate == 24 * MHZ) {
2281                 parent =clk->parents[1];
2282         } else {
2283                 parent=clk->parents[0];
2284                 ret = clk_set_rate_nolock(parent, rate);
2285                 if (ret)
2286                         return ret;
2287         }
2288         if (clk->parent != parent)
2289                 ret = clk_set_parent_nolock(clk, parent);
2290
2291         return ret;
2292 }
2293
2294 static struct clk *cif0_out_parents[2]={&cif0_out_div,&xin24m};
2295 static struct clk cif0_out = {
2296         .name           = "cif0_out",
2297         .parent         = &cif0_out_div,
2298         .set_rate       = cif_out_set_rate,
2299         .clksel_con     = CRU_CLKSELS_CON(29),
2300         CRU_SRC_SET(0x1,7),
2301         CRU_PARENTS_SET(cif0_out_parents),
2302 };
2303 static struct clk *cif1_out_parents[2]={&cif1_out_div,&xin24m};
2304
2305 static struct clk cif1_out = {
2306         .name           = "cif1_out",
2307         .parent         = &cif1_out_div,
2308         .set_rate       = cif_out_set_rate,
2309         .clksel_con     = CRU_CLKSELS_CON(29),
2310         CRU_SRC_SET(0x1,15),
2311         CRU_PARENTS_SET(cif1_out_parents),
2312 };
2313
2314 static struct clk pclkin_cif0 = {
2315         .name           = "pclkin_cif0",
2316         .mode           = gate_mode,
2317         .gate_idx       =CLK_GATE_PCLKIN_CIF0,
2318 };
2319
2320 static struct clk inv_cif0 = {
2321         .name           = "inv_cif0",
2322         .parent         = &pclkin_cif0,
2323 };
2324
2325 static struct clk *cif0_in_parents[2]={&pclkin_cif0,&inv_cif0};
2326 static struct clk cif0_in = {
2327         .name           = "cif0_in",
2328         .parent         = &pclkin_cif0,
2329         .clksel_con     = CRU_CLKSELS_CON(30),
2330         CRU_SRC_SET(0x1,8),
2331         CRU_PARENTS_SET(cif0_in_parents),
2332 };
2333
2334 static struct clk pclkin_cif1 = {
2335         .name           = "pclkin_cif1",
2336         .mode           = gate_mode,
2337         .gate_idx       =CLK_GATE_PCLKIN_CIF1,
2338 };
2339
2340 static struct clk inv_cif1 = {
2341         .name           = "inv_cif1",
2342         .parent         = &pclkin_cif1,
2343 };
2344 static struct clk *cif1_in_parents[2]={&pclkin_cif1,&inv_cif1};
2345
2346 static struct clk cif1_in = {
2347         .name           = "cif1_in",
2348         .parent         = &pclkin_cif1,
2349         .clksel_con     = CRU_CLKSELS_CON(30),
2350         CRU_SRC_SET(0x1,12),
2351         CRU_PARENTS_SET(cif1_in_parents),
2352 };
2353
2354 static struct clk *aclk_lcdc0_ipp_parents[]={&codec_pll_clk,&general_pll_clk};
2355
2356 static struct clk aclk_lcdc0_ipp_parent = {
2357         .name           = "aclk_lcdc0_ipp_parent",
2358         .parent         = &codec_pll_clk,
2359         .mode           = gate_mode,
2360         .recalc         = clksel_recalc_div,
2361         .set_rate       = clkset_rate_freediv_autosel_parents,
2362         //.set_rate     = clksel_set_rate_freediv,
2363         .gate_idx       = CLK_GATE_ACLK_LCDC0_SRC,
2364         .clksel_con     = CRU_CLKSELS_CON(31),
2365         CRU_DIV_SET(0x1f,0,32),
2366         CRU_SRC_SET(0x1,7),
2367         CRU_PARENTS_SET(aclk_lcdc0_ipp_parents),
2368 };
2369
2370 static struct clk *aclk_lcdc1_rga_parents[]={&codec_pll_clk,&general_pll_clk};
2371
2372 static struct clk aclk_lcdc1_rga_parent = {
2373         .name           = "aclk_lcdc1_rga_parent",
2374         .parent         = &codec_pll_clk,
2375         .mode           = gate_mode,
2376         .recalc         = clksel_recalc_div,
2377         .set_rate       = clkset_rate_freediv_autosel_parents,
2378         .gate_idx       = CLK_GATE_ACLK_LCDC1_SRC,
2379         .clksel_con     = CRU_CLKSELS_CON(31),
2380         CRU_DIV_SET(0x1f,8,32),
2381         CRU_SRC_SET(0x1,15),
2382         CRU_PARENTS_SET(aclk_lcdc1_rga_parents),
2383 };
2384
2385
2386 //for free div
2387 static unsigned long clksel_recalc_vpu_hclk(struct clk *clk)
2388 {
2389         unsigned long rate = clk->parent->rate / 4;
2390         pr_debug("%s new clock rate is %lu (div %u)\n", clk->name, rate, 4);
2391         return rate;
2392 }
2393
2394 static struct clk *aclk_vepu_parents[2]={&codec_pll_clk,&general_pll_clk};
2395
2396 static struct clk aclk_vepu = {
2397         .name           = "aclk_vepu",
2398         .parent         = &codec_pll_clk,
2399         .mode           = gate_mode,
2400         .recalc         = clksel_recalc_div,
2401         //.set_rate     = clksel_set_rate_freediv,
2402         .set_rate       =clkset_rate_freediv_autosel_parents,
2403         .clksel_con     = CRU_CLKSELS_CON(32),
2404         .gate_idx       = CLK_GATE_ACLK_VEPU,
2405         CRU_DIV_SET(0x1f,0,32),
2406         CRU_SRC_SET(0x1,7),
2407         CRU_PARENTS_SET(aclk_vepu_parents),
2408 };
2409
2410 static struct clk hclk_vepu = {
2411         .name           = "hclk_vepu",
2412         .parent         = &aclk_vepu,
2413         .mode           = gate_mode,
2414         .recalc         = clksel_recalc_vpu_hclk,
2415         .clksel_con     = CRU_CLKSELS_CON(32),
2416         .gate_idx       = CLK_GATE_HCLK_VEPU,
2417 };
2418
2419 static struct clk *aclk_vdpu_parents[2]={&codec_pll_clk,&general_pll_clk};
2420
2421 static struct clk aclk_vdpu = {
2422         .name           = "aclk_vdpu",
2423         .mode           = gate_mode,
2424         .recalc         = clksel_recalc_div,
2425         //.set_rate     = clksel_set_rate_freediv,
2426         .set_rate       =clkset_rate_freediv_autosel_parents,
2427         .clksel_con     = CRU_CLKSELS_CON(32),
2428         .gate_idx       = CLK_GATE_ACLK_VDPU,
2429         CRU_DIV_SET(0x1f,8,32),
2430         CRU_SRC_SET(0x1,15),
2431         CRU_PARENTS_SET(aclk_vdpu_parents),
2432 };
2433 static struct clk hclk_vdpu = {
2434         .name           = "hclk_vdpu",
2435         .parent         = &aclk_vdpu,
2436         .mode           = gate_mode,
2437         .recalc         = clksel_recalc_vpu_hclk,
2438         .clksel_con     = CRU_CLKSELS_CON(32),
2439         .gate_idx       = CLK_GATE_HCLK_VDPU,
2440 };
2441
2442
2443 static int clk_gpu_set_rate(struct clk *clk, unsigned long rate)
2444 {
2445         unsigned long max_rate = rate / 100 * 105;      /* +5% */
2446         return clkset_rate_freediv_autosel_parents(clk,max_rate);
2447 };
2448
2449 static struct clk *gpu_parents[2]={&codec_pll_clk,&general_pll_clk};
2450
2451 static struct clk clk_gpu = {
2452         .name           = "gpu",
2453         .mode           = gate_mode,
2454         .recalc         = clksel_recalc_div,
2455         .round_rate     = clk_freediv_round_autosel_parents_rate,
2456         .set_rate       = clkset_rate_freediv_autosel_parents,
2457         .clksel_con = CRU_CLKSELS_CON(33),
2458         .gate_idx       =  CLK_GATE_GPU_SRC,
2459         CRU_DIV_SET(0x1f,0,32),
2460         CRU_SRC_SET(0x1,8),
2461         CRU_PARENTS_SET(gpu_parents),
2462 };
2463
2464 /*********************power domain*******************************/
2465 #ifdef RK30_CLK_OFFBOARD_TEST
2466 void pmu_set_power_domain_test(enum pmu_power_domain pd, bool on){};
2467         #define _pmu_set_power_domain pmu_set_power_domain_test//rk30_pmu_set_power_domain
2468 #else
2469 void pmu_set_power_domain(enum pmu_power_domain pd, bool on);
2470         #define _pmu_set_power_domain pmu_set_power_domain
2471 #endif
2472 static int pm_off_mode(struct clk *clk, int on)
2473 {
2474          _pmu_set_power_domain(clk->gate_idx,on);//on 1
2475          return 0;
2476 }
2477 static struct clk pd_peri = {
2478         .name   = "pd_peri",
2479         .flags  = IS_PD,
2480         .mode   = pm_off_mode,
2481         .gate_idx       = PD_PERI,
2482 };
2483
2484 static int pd_display_mode(struct clk *clk, int on)
2485 {
2486         u32 gate[10];
2487
2488         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2489         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2490         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2491         gate[3] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2492         gate[4] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2493         gate[5] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2494         gate[6] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2495         gate[7] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2496         gate[8] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2497         gate[9] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2498         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2499         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2500         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2501         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2502         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2503         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2504         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2505         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2506         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2507         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2508         pmu_set_power_domain(PD_VIO, on);
2509         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0_SRC));
2510         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1_SRC) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1_SRC));
2511         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC0) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC0));
2512         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_LCDC1) | gate[3], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_LCDC1));
2513         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF0) | gate[4], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF0));
2514         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_CIF1) | gate[5], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_CIF1));
2515         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO0) | gate[6], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO0));
2516         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VIO1) | gate[7], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VIO1));
2517         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_IPP) | gate[8], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_IPP));
2518         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_RGA) | gate[9], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_RGA));
2519
2520         return 0;
2521 }
2522
2523 static struct clk pd_display = {
2524         .name   = "pd_display",
2525         .flags  = IS_PD,
2526         .mode   = pd_display_mode,
2527         .gate_idx       = PD_VIO,
2528 };
2529
2530 static struct clk pd_lcdc0 = {
2531         .parent = &pd_display,
2532         .name   = "pd_lcdc0",
2533 };
2534 static struct clk pd_lcdc1 = {
2535         .parent = &pd_display,
2536         .name   = "pd_lcdc1",
2537 };
2538 static struct clk pd_cif0 = {
2539         .parent = &pd_display,
2540         .name   = "pd_cif0",
2541 };
2542 static struct clk pd_cif1 = {
2543         .parent = &pd_display,
2544         .name   = "pd_cif1",
2545 };
2546 static struct clk pd_rga = {
2547         .parent = &pd_display,
2548         .name   = "pd_rga",
2549 };
2550 static struct clk pd_ipp = {
2551         .parent = &pd_display,
2552         .name   = "pd_ipp",
2553 };
2554
2555 static int pd_video_mode(struct clk *clk, int on)
2556 {
2557         u32 gate[3];
2558
2559         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2560         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2561         gate[2] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2562         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2563         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2564         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2565         pmu_set_power_domain(PD_VIDEO, on);
2566         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VEPU) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VEPU));
2567         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VDPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VDPU));
2568         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_VCODEC) | gate[2], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_VCODEC));
2569
2570         return 0;
2571 }
2572
2573 static struct clk pd_video = {
2574         .name   = "pd_video",
2575         .flags  = IS_PD,
2576         .mode   = pd_video_mode,
2577         .gate_idx       = PD_VIDEO,
2578 };
2579
2580 static int pd_gpu_mode(struct clk *clk, int on)
2581 {
2582         u32 gate[2];
2583
2584         gate[0] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
2585         gate[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2586         cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC), CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
2587         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU), CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2588         pmu_set_power_domain(PD_GPU, on);
2589         cru_writel(CLK_GATE_W_MSK(CLK_GATE_GPU_SRC) | gate[0], CLK_GATE_CLKID_CONS(CLK_GATE_GPU_SRC));
2590         cru_writel(CLK_GATE_W_MSK(CLK_GATE_ACLK_GPU) | gate[1], CLK_GATE_CLKID_CONS(CLK_GATE_ACLK_GPU));
2591
2592         return 0;
2593 }
2594
2595 static struct clk pd_gpu = {
2596         .name   = "pd_gpu",
2597         .flags  = IS_PD,
2598         .mode   = pd_gpu_mode,
2599         .gate_idx       = PD_GPU,
2600 };
2601 static struct clk pd_dbg = {
2602         .name   = "pd_dbg",
2603         .flags  = IS_PD,
2604         .mode   = pm_off_mode,
2605         .gate_idx       = PD_DBG,
2606 };
2607
2608 #define PD_CLK(name) \
2609 {\
2610         .dev_id = NULL,\
2611         .con_id = #name,\
2612         .clk = &name,\
2613 }
2614
2615
2616 /************************rk30 fixed div clock****************************************/
2617
2618 /*************************aclk_cpu***********************/
2619
2620 GATE_CLK(dma1, aclk_cpu,        ACLK_DMAC1);
2621 GATE_CLK(l2mem_con, aclk_cpu,   ACLK_L2MEM_CON);
2622 GATE_CLK(intmem, aclk_cpu,      ACLK_INTMEM);
2623 GATE_CLK(aclk_strc_sys, aclk_cpu,       ACLK_STRC_SYS);
2624
2625 /*************************hclk_cpu***********************/
2626
2627 GATE_CLK(rom, hclk_cpu, HCLK_ROM);
2628 GATE_CLK(hclk_i2s0_2ch, hclk_cpu,       HCLK_I2S0_2CH);
2629 GATE_CLK(hclk_i2s1_2ch, hclk_cpu,       HCLK_I2S1_2CH);
2630 GATE_CLK(hclk_spdif, hclk_cpu, HCLK_SPDIF);
2631 GATE_CLK(hclk_i2s_8ch, hclk_cpu, HCLK_I2S_8CH);
2632 GATE_CLK(hclk_cpubus, hclk_cpu, HCLK_CPUBUS);
2633 GATE_CLK(hclk_ahb2apb,  hclk_cpu, HCLK_AHB2APB);
2634 GATE_CLK(hclk_vio_bus,  hclk_cpu, HCLK_VIO_BUS);
2635 GATE_CLK(hclk_lcdc0,    hclk_cpu, HCLK_LCDC0);
2636 GATE_CLK(hclk_lcdc1,    hclk_cpu, HCLK_LCDC1);
2637 GATE_CLK(hclk_cif0,     hclk_cpu, HCLK_CIF0);
2638 GATE_CLK(hclk_cif1,     hclk_cpu, HCLK_CIF1);
2639 GATE_CLK(hclk_ipp,              hclk_cpu, HCLK_IPP);
2640 GATE_CLK(hclk_rga,              hclk_cpu, HCLK_RGA);
2641 GATE_CLK(hclk_hdmi,     hclk_cpu, HCLK_HDMI);
2642 //GATE_CLK(hclk_vidoe_h2h,      hclk_cpu, ); ???
2643 /*************************pclk_cpu***********************/
2644 GATE_CLK(pwm01, pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
2645 //GATE_CLK(pclk_pwm1,   pclk_cpu, PCLK_PWM01);//pwm 0¡¢1
2646 GATE_CLK(pclk_timer0,   pclk_cpu, PCLK_TIMER0);
2647 GATE_CLK(pclk_timer1,   pclk_cpu, PCLK_TIMER1);
2648 GATE_CLK(pclk_timer2,   pclk_cpu, PCLK_TIMER2);
2649 GATE_CLK(i2c0,  pclk_cpu, PCLK_I2C0);
2650 GATE_CLK(i2c1,  pclk_cpu, PCLK_I2C1);
2651 GATE_CLK(gpio0, pclk_cpu, PCLK_GPIO0);
2652 GATE_CLK(gpio1, pclk_cpu, PCLK_GPIO1);
2653 GATE_CLK(gpio2, pclk_cpu, PCLK_GPIO2);
2654 GATE_CLK(gpio6, pclk_cpu, PCLK_GPIO6);
2655 GATE_CLK(efuse, pclk_cpu, PCLK_EFUSE);
2656 GATE_CLK(tzpc,  pclk_cpu, PCLK_TZPC);
2657 GATE_CLK(pclk_uart0,    pclk_cpu, PCLK_UART0);
2658 GATE_CLK(pclk_uart1,    pclk_cpu, PCLK_UART1);
2659 GATE_CLK(pclk_ddrupctl, pclk_cpu, PCLK_DDRUPCTL);
2660 GATE_CLK(pclk_ddrpubl,  pclk_cpu, PCLK_PUBL);
2661 GATE_CLK(dbg,   pclk_cpu, PCLK_DBG);
2662 GATE_CLK(grf,   pclk_cpu, PCLK_GRF);
2663 GATE_CLK(pmu,   pclk_cpu, PCLK_PMU);
2664
2665 /*************************aclk_periph***********************/
2666
2667 GATE_CLK(dma2, aclk_periph,ACLK_DMAC2);
2668 GATE_CLK(aclk_smc, aclk_periph, ACLK_SMC);
2669 GATE_CLK(aclk_peri_niu, aclk_periph, ACLK_PEI_NIU);
2670 GATE_CLK(aclk_cpu_peri, aclk_periph, ACLK_CPU_PERI);
2671 GATE_CLK(aclk_peri_axi_matrix, aclk_periph, ACLK_PERI_AXI_MATRIX);
2672
2673 /*************************hclk_periph***********************/
2674 GATE_CLK(hclk_peri_axi_matrix, hclk_periph, HCLK_PERI_AXI_MATRIX);
2675 GATE_CLK(hclk_peri_ahb_arbi, hclk_periph, HCLK_PERI_AHB_ARBI);
2676 GATE_CLK(hclk_emem_peri, hclk_periph, HCLK_EMEM_PERI);
2677 GATE_CLK(hclk_mac, hclk_periph, HCLK_EMAC);
2678 GATE_CLK(nandc, hclk_periph, HCLK_NANDC);
2679 GATE_CLK(hclk_usb_peri, hclk_periph, HCLK_USB_PERI);
2680 GATE_CLK(hclk_otg0, clk_hclk_usb_peri, HCLK_OTG0);
2681 GATE_CLK(hclk_otg1, clk_hclk_usb_peri, HCLK_OTG1);
2682 GATE_CLK(hclk_hsadc, hclk_periph, HCLK_HSADC);
2683 GATE_CLK(hclk_pidfilter, hclk_periph, HCLK_PIDF);
2684 GATE_CLK(hclk_sdmmc, hclk_periph, HCLK_SDMMC0);
2685 GATE_CLK(hclk_sdio, hclk_periph, HCLK_SDIO);
2686 GATE_CLK(hclk_emmc, hclk_periph, HCLK_EMMC);
2687 /*************************pclk_periph***********************/
2688 GATE_CLK(pclk_peri_axi_matrix, pclk_periph, PCLK_PERI_AXI_MATRIX);
2689 GATE_CLK(pwm23, pclk_periph, PCLK_PWM23);
2690 //GATE_CLK(pclk_pwm3, pclk_periph, PCLK_PWM3);
2691 GATE_CLK(wdt, pclk_periph, PCLK_WDT);
2692 GATE_CLK(pclk_spi0, pclk_periph, PCLK_SPI0);
2693 GATE_CLK(pclk_spi1, pclk_periph, PCLK_SPI1);
2694 GATE_CLK(pclk_uart2, pclk_periph, PCLK_UART2);
2695 GATE_CLK(pclk_uart3, pclk_periph, PCLK_UART3);
2696 GATE_CLK(i2c2, pclk_periph, PCLK_I2C2);
2697 GATE_CLK(i2c3, pclk_periph, PCLK_I2C3);
2698 GATE_CLK(i2c4, pclk_periph, PCLK_I2C4);
2699 GATE_CLK(gpio3, pclk_periph, PCLK_GPIO3);
2700 GATE_CLK(gpio4, pclk_periph, PCLK_GPIO4);
2701 GATE_CLK(pclk_saradc, pclk_periph, PCLK_SARADC);
2702 GATE_CLK(pclk_tsadc, pclk_periph, PCLK_TSADC);
2703 /*************************aclk_lcdc0***********************/
2704 GATE_CLK(aclk_lcdc0, aclk_lcdc0_ipp_parent, ACLK_LCDC0);
2705 GATE_CLK(aclk_vio0, aclk_lcdc0_ipp_parent, ACLK_VIO0);
2706 GATE_CLK(aclk_cif0, aclk_lcdc0_ipp_parent, ACLK_CIF0);
2707 GATE_CLK(aclk_ipp,  aclk_lcdc0_ipp_parent, ACLK_IPP);
2708
2709 /*************************aclk_lcdc0***********************/
2710
2711 GATE_CLK(aclk_lcdc1, aclk_lcdc1_rga_parent, ACLK_LCDC1);
2712 GATE_CLK(aclk_vio1, aclk_lcdc1_rga_parent, ACLK_VIO1);
2713 GATE_CLK(aclk_cif1, aclk_lcdc1_rga_parent, ACLK_CIF0);
2714 GATE_CLK(aclk_rga,  aclk_lcdc1_rga_parent, ACLK_RGA);
2715
2716
2717 #if 1
2718 #define CLK(dev, con, ck) \
2719  {\
2720         .dev_id = dev,\
2721         .con_id = con,\
2722         .clk = ck,\
2723  }
2724
2725
2726 #define CLK1(name) \
2727         {\
2728         .dev_id = NULL,\
2729         .con_id = #name,\
2730         .clk = &clk_##name,\
2731         }
2732
2733 #endif
2734
2735
2736
2737
2738 static struct clk_lookup clks[] = {
2739         CLK(NULL, "xin24m", &xin24m),
2740         CLK(NULL, "xin27m", &xin27m),
2741         CLK(NULL, "xin12m", &clk_12m),
2742         CLK(NULL, "arm_pll", &arm_pll_clk),
2743         CLK(NULL, "ddr_pll", &ddr_pll_clk),
2744         CLK(NULL, "codec_pll", &codec_pll_clk),
2745         CLK(NULL, "general_pll", &general_pll_clk),
2746
2747         CLK(NULL, "ddr", &clk_ddr),
2748         //CLK(NULL, "core_gpll_path", &clk_cpu_gpll_path),
2749         CLK(NULL, "cpu", &clk_cpu),
2750         CLK(NULL, "arm_gpll", &clk_cpu_gpll_path),
2751         CLK("smp_twd", NULL, &core_periph),
2752         CLK(NULL, "aclk_cpu", &aclk_cpu),
2753         CLK(NULL, "hclk_cpu", &hclk_cpu),
2754         CLK(NULL, "pclk_cpu", &pclk_cpu),
2755         CLK(NULL, "atclk_cpu", &atclk_cpu),
2756
2757
2758         CLK1(i2s_pll),
2759         CLK("rk29_i2s.0", "i2s_div", &clk_i2s0_div),
2760         CLK("rk29_i2s.0", "i2s_frac_div", &clk_i2s0_frac_div),
2761         CLK("rk29_i2s.0", "i2s", &clk_i2s0),
2762         CLK("rk29_i2s.0", "hclk_i2s", &clk_hclk_i2s_8ch),
2763
2764         CLK("rk29_i2s.1", "i2s_div", &clk_i2s1_div),
2765         CLK("rk29_i2s.1", "i2s_frac_div", &clk_i2s1_frac_div),
2766         CLK("rk29_i2s.1", "i2s", &clk_i2s1),
2767         CLK("rk29_i2s.1", "hclk_i2s", &clk_hclk_i2s0_2ch),
2768
2769         CLK("rk29_i2s.2", "i2s_div", &clk_i2s2_div),
2770         CLK("rk29_i2s.2", "i2s_frac_div", &clk_i2s2_frac_div),
2771         CLK("rk29_i2s.2", "i2s", &clk_i2s2),
2772         CLK("rk29_i2s.2", "hclk_i2s", &clk_hclk_i2s1_2ch),
2773
2774         CLK1(spdif_div),
2775         CLK1(spdif_frac_div),
2776         CLK1(spdif),
2777         CLK1(hclk_spdif),
2778
2779         CLK(NULL, "aclk_periph", &aclk_periph),
2780         CLK(NULL, "pclk_periph", &pclk_periph),
2781         CLK(NULL, "hclk_periph", &hclk_periph),
2782
2783         CLK("rk29xx_spim.0", "spi", &clk_spi0),
2784         CLK("rk29xx_spim.0", "pclk_spi", &clk_pclk_spi0),
2785
2786         CLK("rk29xx_spim.1", "spi", &clk_spi1),
2787         CLK("rk29xx_spim.1", "pclk_spi", &clk_pclk_spi1),
2788
2789         CLK1(saradc),
2790         CLK1(pclk_saradc),
2791         CLK1(tsadc),
2792         CLK1(pclk_tsadc),
2793         CLK1(otgphy0),
2794         CLK1(otgphy1),
2795         CLK1(hclk_usb_peri),
2796         CLK1(hclk_otg0),
2797         CLK1(hclk_otg1),
2798
2799
2800
2801
2802
2803         CLK1(smc),
2804         CLK1(aclk_smc),
2805
2806         CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc),
2807         CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc),
2808         CLK("rk29_sdmmc.1", "mmc", &clk_sdio),
2809         CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio),
2810
2811         CLK1(emmc),
2812         CLK1(hclk_emmc),
2813
2814
2815         CLK1(uart_pll),
2816         CLK("rk_serial.0", "uart_div", &clk_uart0_div),
2817         CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div),
2818         CLK("rk_serial.0", "uart", &clk_uart0),
2819         CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0),
2820         CLK("rk_serial.1", "uart_div", &clk_uart1_div),
2821         CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div),
2822         CLK("rk_serial.1", "uart", &clk_uart1),
2823         CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1),
2824         CLK("rk_serial.2", "uart_div", &clk_uart2_div),
2825         CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div),
2826         CLK("rk_serial.2", "uart", &clk_uart2),
2827         CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2),
2828         CLK("rk_serial.3", "uart_div", &clk_uart3_div),
2829         CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div),
2830         CLK("rk_serial.3", "uart", &clk_uart3),
2831         CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3),
2832
2833         CLK1(timer0),
2834         CLK1(pclk_timer0),
2835
2836         CLK1(timer1),
2837         CLK1(pclk_timer1),
2838
2839         CLK1(timer2),
2840         CLK1(pclk_timer2),
2841
2842         CLK(NULL, "rmii_clkin", &rmii_clkin),
2843         CLK(NULL, "mac_ref_div", &clk_mac_pll_div), // compatible with rk29
2844         CLK1(mac_ref),
2845         CLK1(mii_tx),
2846         CLK1(hsadc_pll_div),
2847         CLK1(hsadc_frac_div),
2848         CLK1(hsadc_ext),
2849         CLK1(hsadc),
2850         CLK1(hclk_hsadc),
2851
2852         CLK(NULL, "aclk_lcdc0_ipp_parent", &aclk_lcdc0_ipp_parent),
2853         CLK(NULL, "aclk_lcdc1_rga_parent", &aclk_lcdc1_rga_parent),
2854
2855         CLK(NULL, "dclk_lcdc0_div", &dclk_lcdc0_div),
2856         CLK(NULL, "dclk_lcdc1_div", &dclk_lcdc1_div),
2857
2858         CLK(NULL, "dclk_lcdc0", &dclk_lcdc0),
2859         CLK(NULL, "aclk_lcdc0", &clk_aclk_lcdc0),
2860         CLK1(hclk_lcdc0),
2861
2862         CLK(NULL, "dclk_lcdc1", &dclk_lcdc1),
2863         CLK(NULL, "aclk_lcdc1", &clk_aclk_lcdc1),
2864         CLK1(hclk_lcdc1),
2865
2866         CLK(NULL, "cif_out_pll", &cif_out_pll),
2867         CLK(NULL, "cif0_out_div", &cif0_out_div),
2868         CLK(NULL, "cif1_out_div", &cif1_out_div),
2869
2870         CLK(NULL, "cif0_out", &cif0_out),
2871         CLK1(hclk_cif0),
2872
2873         CLK(NULL, "cif1_out", &cif1_out),
2874         CLK1(hclk_cif1),
2875
2876         CLK1(hclk_ipp),
2877         CLK1(hclk_rga),
2878         CLK1(hclk_hdmi),
2879
2880         CLK(NULL, "pclkin_cif0",        &pclkin_cif0),
2881         CLK(NULL, "inv_cif0",                   &inv_cif0),
2882         CLK(NULL, "cif0_in",                    &cif0_in),
2883         CLK(NULL, "pclkin_cif1", &pclkin_cif1),
2884         CLK(NULL, "inv_cif1",   &inv_cif1),
2885         CLK(NULL, "cif1_in",    &cif1_in),
2886         //CLK(NULL, "aclk_lcdc0",       &aclk_lcdc0),
2887         //CLK(NULL, "aclk_lcdc1",       &aclk_lcdc1),
2888         CLK(NULL, "aclk_vepu",  &aclk_vepu),
2889         CLK(NULL, "hclk_vepu",  &hclk_vepu),
2890         CLK(NULL, "aclk_vdpu",  &aclk_vdpu),
2891         CLK(NULL, "hclk_vdpu",  &hclk_vdpu),
2892         CLK1(gpu),
2893         CLK1(dma1),
2894         CLK1(l2mem_con),
2895         CLK1(intmem),
2896
2897         CLK1(aclk_strc_sys),
2898
2899         /*************************hclk_cpu***********************/
2900
2901         CLK1(rom),
2902         //CLK1(hclk_i2s0_2ch),
2903         //CLK1(hclk_i2s1_2ch),
2904         //CLK1(hclk_spdif),
2905         //CLK1(hclk_i2s_8ch),
2906         CLK1(hclk_cpubus),
2907         CLK1(hclk_ahb2apb),
2908         CLK1(hclk_vio_bus),
2909         //CLK1(hclk_lcdc0),
2910         //CLK1(hclk_lcdc1),
2911         //CLK1(hclk_cif0),
2912         //CLK1(hclk_cif1),
2913         //CLK1(hclk_ipp),
2914         //CLK1(hclk_rga),
2915         //CLK1(hclk_hdmi),
2916         //CLK1(hclk_vidoe_h2h,  hclk_cpu, ); ???
2917         /*************************pclk_cpu***********************/
2918         CLK1(pwm01),//pwm 0¡¢1
2919
2920         //CLK1(pclk_timer0),
2921         //CLK1(pclk_timer1),
2922         //CLK1(pclk_timer2),
2923
2924         CLK("rk30_i2c.0", "i2c", &clk_i2c0),
2925         CLK("rk30_i2c.1", "i2c", &clk_i2c1),
2926
2927         CLK1(gpio0),
2928         CLK1(gpio1),
2929         CLK1(gpio2),
2930         CLK1(gpio6),
2931         CLK1(efuse),
2932         CLK1(tzpc),
2933         //CLK1(pclk_uart0),
2934         //CLK1(pclk_uart1),
2935         CLK1(pclk_ddrupctl),
2936         CLK1(pclk_ddrpubl),
2937         CLK1(dbg),
2938         CLK1(grf),
2939         CLK1(pmu),
2940
2941         /*************************aclk_periph***********************/
2942
2943         CLK1(dma2),
2944         //CLK1(aclk_smc),
2945         CLK1(aclk_peri_niu),
2946         CLK1(aclk_cpu_peri),
2947         CLK1(aclk_peri_axi_matrix),
2948
2949         /*************************hclk_periph***********************/
2950         CLK1(hclk_peri_axi_matrix),
2951         CLK1(hclk_peri_ahb_arbi),
2952         CLK1(hclk_emem_peri),
2953         CLK1(hclk_mac),
2954         CLK1(nandc),
2955         //CLK1(hclk_usb_peri),
2956         //CLK1(hclk_usbotg0),
2957         //CLK1(hclk_usbotg1),
2958         //CLK1(hclk_hsadc),
2959         CLK1(hclk_pidfilter),
2960
2961         //CLK1(hclk_emmc),
2962         /*************************pclk_periph***********************/
2963         CLK1(pclk_peri_axi_matrix),
2964         CLK1(pwm23),
2965
2966         CLK1(wdt),
2967         //CLK1(pclk_spi0),
2968         //CLK1(pclk_spi1),
2969         //CLK1(pclk_uart2),
2970         //CLK1(pclk_uart3),
2971
2972         CLK("rk30_i2c.2", "i2c", &clk_i2c2),
2973         CLK("rk30_i2c.3", "i2c", &clk_i2c3),
2974         CLK("rk30_i2c.4", "i2c", &clk_i2c4),
2975
2976         CLK1(gpio3),
2977         CLK1(gpio4),
2978
2979         /*************************aclk_lcdc0***********************/
2980         //CLK1(aclk_vio0),
2981         CLK1(aclk_cif0),
2982         CLK1(aclk_ipp),
2983
2984         /*************************aclk_lcdc0***********************/
2985         //CLK1(aclk_vio1),
2986         CLK1(aclk_cif1),
2987         CLK1(aclk_rga),
2988         /************************power domain**********************/
2989         PD_CLK(pd_peri),
2990         PD_CLK(pd_display),
2991         PD_CLK(pd_video),
2992         PD_CLK(pd_lcdc0),
2993         PD_CLK(pd_lcdc1),
2994         PD_CLK(pd_cif0),
2995         PD_CLK(pd_cif1),
2996         PD_CLK(pd_rga),
2997         PD_CLK(pd_ipp),
2998         PD_CLK(pd_video),
2999         PD_CLK(pd_gpu),
3000         PD_CLK(pd_dbg),
3001 };
3002 static void __init rk30_init_enable_clocks(void)
3003 {
3004                 //clk_enable_nolock(&xin24m);
3005                 //clk_enable_nolock(&xin27m);
3006                 //clk_enable_nolock(&clk_12m);
3007                 //clk_enable_nolock(&arm_pll_clk);
3008                 //clk_enable_nolock(&ddr_pll_clk);
3009                 //clk_enable_nolock(&codec_pll_clk);
3010                 //clk_enable_nolock(&general_pll_clk);
3011                 //clk_enable_nolock(&clk_ddr);
3012
3013                 clk_enable_nolock(&clk_cpu);
3014                 clk_enable_nolock(&core_periph);
3015                 clk_enable_nolock(&aclk_cpu);
3016                 clk_enable_nolock(&hclk_cpu);
3017                 clk_enable_nolock(&pclk_cpu);
3018                 clk_enable_nolock(&atclk_cpu);
3019
3020                 #if 0
3021                 clk_enable_nolock(&clk_i2s_pll);
3022                 clk_enable_nolock(&clk_i2s0_div);
3023                 clk_enable_nolock(&clk_i2s0_frac_div);
3024                 clk_enable_nolock(&clk_i2s0);
3025                 clk_enable_nolock(&clk_hclk_i2s_8ch);
3026
3027                 clk_enable_nolock(&clk_i2s1_div);
3028                 clk_enable_nolock(&clk_i2s1_frac_div);
3029                 clk_enable_nolock(&clk_i2s1);
3030                 clk_enable_nolock(&clk_hclk_i2s0_2ch);
3031
3032                 clk_enable_nolock(&clk_i2s2_div);
3033                 clk_enable_nolock(&clk_i2s2_frac_div);
3034                 clk_enable_nolock(&clk_i2s2);
3035                 clk_enable_nolock(&clk_hclk_i2s1_2ch);
3036
3037                 clk_enable_nolock(&clk_spdif_div);
3038                 clk_enable_nolock(&clk_spdif_frac_div);
3039                 clk_enable_nolock(&clk_spdif);
3040                 clk_enable_nolock(&clk_hclk_spdif);
3041                 #endif
3042                 clk_enable_nolock(&aclk_periph);
3043                 clk_enable_nolock(&pclk_periph);
3044                 clk_enable_nolock(&hclk_periph);
3045
3046                 #if 0
3047                 clk_enable_nolock(&clk_spi0);
3048                 clk_enable_nolock(&clk_pclk_spi0);
3049
3050                 clk_enable_nolock(&clk_spi1);
3051                 clk_enable_nolock(&clk_pclk_spi1);
3052                 clk_enable_nolock(&clk_saradc);
3053                 clk_enable_nolock(&clk_pclk_saradc);
3054                 clk_enable_nolock(&clk_tsadc);
3055                 clk_enable_nolock(&clk_pclk_tsadc);
3056                 #endif
3057                 #if 0
3058                 clk_enable_nolock(&clk_otgphy0);
3059                 clk_enable_nolock(&clk_otgphy1);
3060                 clk_enable_nolock(&clk_hclk_usb_peri);
3061                 clk_enable_nolock(&clk_hclk_otg0);
3062                 clk_enable_nolock(&clk_hclk_otg1);
3063                 #endif
3064                 #if 0
3065                 clk_enable_nolock(&clk_smc);
3066                 clk_enable_nolock(&clk_aclk_smc);
3067
3068                 clk_enable_nolock(&clk_sdmmc);
3069                 clk_enable_nolock(&clk_hclk_sdmmc);
3070                 clk_enable_nolock(&clk_sdio);
3071                 clk_enable_nolock(&clk_hclk_sdio);
3072
3073                 clk_enable_nolock(&clk_emmc);
3074                 clk_enable_nolock(&clk_hclk_emmc);
3075
3076                 #endif
3077
3078         #if CONFIG_RK_DEBUG_UART == 0
3079                 clk_enable_nolock(&clk_uart0);
3080                 clk_enable_nolock(&clk_pclk_uart0);
3081         #elif CONFIG_RK_DEBUG_UART == 1
3082                 clk_enable_nolock(&clk_uart1);
3083                 clk_enable_nolock(&clk_pclk_uart1);
3084
3085         #elif CONFIG_RK_DEBUG_UART == 2
3086                 clk_enable_nolock(&clk_uart2);
3087                 clk_enable_nolock(&clk_pclk_uart2);
3088
3089         #elif CONFIG_RK_DEBUG_UART == 3
3090                 clk_enable_nolock(&clk_uart3);
3091                 clk_enable_nolock(&clk_pclk_uart3);
3092
3093         #endif
3094
3095                 #if 0
3096                 clk_enable_nolock(&clk_timer0);
3097                 clk_enable_nolock(&clk_pclk_timer0);
3098
3099                 clk_enable_nolock(&clk_timer1);
3100                 clk_enable_nolock(&clk_pclk_timer1);
3101
3102                 clk_enable_nolock(&clk_timer2);
3103                 clk_enable_nolock(&clk_pclk_timer2);
3104                 #endif
3105                 #if 0
3106                 clk_enable_nolock(&rmii_clkin);
3107                 clk_enable_nolock(&clk_mac_pll_div);
3108                 clk_enable_nolock(&clk_mac_ref);
3109                 clk_enable_nolock(&clk_mii_tx);
3110                 #endif
3111
3112                 #if 0
3113                 clk_enable_nolock(&clk_hsadc_pll_div);
3114                 clk_enable_nolock(&clk_hsadc_frac_div);
3115                 clk_enable_nolock(&clk_hsadc_ext);
3116                 clk_enable_nolock(&clk_hsadc);
3117                 clk_enable_nolock(&clk_hclk_hsadc);
3118                 #endif
3119
3120                 #if 0
3121                 clk_enable_nolock(&aclk_lcdc0_ipp_parent);
3122                 clk_enable_nolock(&aclk_lcdc1_rga_parent);
3123
3124                 clk_enable_nolock(&dclk_lcdc0_div);
3125                 clk_enable_nolock(&dclk_lcdc1_div);
3126
3127                 clk_enable_nolock(&dclk_lcdc0);
3128                 clk_enable_nolock(&clk_aclk_lcdc0);
3129                 clk_enable_nolock(&clk_hclk_lcdc0);
3130
3131                 clk_enable_nolock(&dclk_lcdc1);
3132                 clk_enable_nolock(&clk_aclk_lcdc1);
3133                 clk_enable_nolock(&clk_hclk_lcdc1);
3134
3135                 clk_enable_nolock(&cif_out_pll);
3136                 clk_enable_nolock(&cif0_out_div);
3137                 clk_enable_nolock(&cif1_out_div);
3138
3139                 clk_enable_nolock(&cif0_out);
3140                 clk_enable_nolock(&clk_hclk_cif0);
3141
3142                 clk_enable_nolock(&cif1_out);
3143                 clk_enable_nolock(&clk_hclk_cif1);
3144
3145                 clk_enable_nolock(&clk_hclk_ipp);
3146                 clk_enable_nolock(&clk_hclk_rga);
3147                 clk_enable_nolock(&clk_hclk_hdmi);
3148
3149                 clk_enable_nolock(&pclkin_cif0);
3150                 clk_enable_nolock(&inv_cif0);
3151                 clk_enable_nolock(&cif0_in);
3152                 clk_enable_nolock(&pclkin_cif1);
3153                 clk_enable_nolock(&inv_cif1);
3154                 clk_enable_nolock(&cif1_in);
3155                 //CLK(NULL, "aclk_lcdc0",       &aclk_lcdc0),
3156                 //CLK(NULL, "aclk_lcdc1",       &aclk_lcdc1),
3157                 clk_enable_nolock(&aclk_vepu);
3158                 clk_enable_nolock(&hclk_vepu);
3159                 clk_enable_nolock(&aclk_vdpu);
3160                 clk_enable_nolock(&hclk_vdpu);
3161                 clk_enable_nolock(&clk_gpu);
3162                 #endif
3163
3164                 clk_enable_nolock(&clk_dma1);
3165                 clk_enable_nolock(&clk_l2mem_con);
3166                 clk_enable_nolock(&clk_intmem);
3167
3168                 clk_enable_nolock(&clk_aclk_strc_sys);
3169
3170                 /*************************hclk_cpu***********************/
3171
3172                 clk_enable_nolock(&clk_rom);
3173
3174                 clk_enable_nolock(&clk_hclk_cpubus);
3175                 clk_enable_nolock(&clk_hclk_ahb2apb);
3176                 clk_enable_nolock(&clk_hclk_vio_bus);
3177
3178                 /*************************pclk_cpu***********************/
3179
3180                 //clk_enable_nolock(&clk_pwm01);//pwm 0¡¢1
3181                 #if 0
3182
3183
3184                 clk_enable_nolock(&clk_i2c0);
3185                 clk_enable_nolock(&clk_i2c1);
3186
3187                 clk_enable_nolock(&clk_gpio0);
3188                 clk_enable_nolock(&clk_gpio1);
3189                 clk_enable_nolock(&clk_gpio2);
3190                 clk_enable_nolock(&clk_gpio6);
3191                 clk_enable_nolock(&clk_efuse);
3192                 #endif
3193                 clk_enable_nolock(&clk_tzpc);
3194
3195                 //CLK1(pclk_uart0),
3196                 //CLK1(pclk_uart1),
3197                 clk_enable_nolock(&clk_pclk_ddrupctl);
3198                 clk_enable_nolock(&clk_pclk_ddrpubl);
3199                 clk_enable_nolock(&clk_dbg);
3200                 clk_enable_nolock(&clk_grf);
3201                 clk_enable_nolock(&clk_pmu);
3202
3203                 /*************************aclk_periph***********************/
3204
3205                 clk_enable_nolock(&clk_dma2);
3206                 //CLK1(aclk_smc),
3207                 clk_enable_nolock(&clk_aclk_peri_niu);
3208                 clk_enable_nolock(&clk_aclk_cpu_peri);
3209                 clk_enable_nolock(&clk_aclk_peri_axi_matrix);
3210
3211                 /*************************hclk_periph***********************/
3212                 clk_enable_nolock(&clk_hclk_peri_axi_matrix);
3213                 clk_enable_nolock(&clk_hclk_peri_ahb_arbi);
3214                 clk_enable_nolock(&clk_hclk_emem_peri);
3215                 clk_enable_nolock(&clk_hclk_mac);
3216                 clk_enable_nolock(&clk_nandc);
3217                 //CLK1(hclk_usb_peri),
3218                 //CLK1(hclk_usbotg0),
3219                 //CLK1(hclk_usbotg1),
3220                 //CLK1(hclk_hsadc),
3221                 clk_enable_nolock(&clk_hclk_pidfilter);
3222
3223                 /*************************pclk_periph***********************/
3224                 clk_enable_nolock(&clk_pclk_peri_axi_matrix);
3225                 //clk_enable_nolock(&clk_pwm23);
3226
3227                 //clk_enable_nolock(&clk_wdt);
3228
3229                 #if 0
3230
3231                 clk_enable_nolock(&clk_i2c2);
3232                 clk_enable_nolock(&clk_i2c3);
3233                 clk_enable_nolock(&clk_i2c4);
3234
3235                 clk_enable_nolock(&clk_gpio3);
3236                 clk_enable_nolock(&clk_gpio4);
3237                 #endif
3238                 /*************************aclk_lcdc0***********************/
3239                 //clk_enable_nolock(&clk_aclk_vio0);
3240                 //clk_enable_nolock(&clk_aclk_cif0);
3241                 //clk_enable_nolock(&clk_aclk_ipp);
3242
3243                 /*************************aclk_lcdc0***********************/
3244                 //clk_enable_nolock(&clk_aclk_vio1);
3245                 //clk_enable_nolock(&clk_aclk_cif1);
3246                 //clk_enable_nolock(&clk_aclk_rga);
3247                 /************************power domain**********************/
3248 }
3249 static void periph_clk_set_init(void)
3250 {
3251         unsigned long aclk_p, hclk_p, pclk_p;
3252         unsigned long ppll_rate=general_pll_clk.rate;
3253         //aclk 148.5
3254
3255         /* general pll */
3256         switch (ppll_rate) {
3257         case 148500* KHZ:
3258                 aclk_p = 148500*KHZ;
3259                 hclk_p = aclk_p>>1;
3260                 pclk_p = aclk_p>>2;
3261                 break;
3262         case 1188*MHZ:
3263                 aclk_p = aclk_p>>3;// 0
3264                 hclk_p = aclk_p>>1;
3265                 pclk_p = aclk_p>>2;
3266
3267         case 297 * MHZ:
3268                 aclk_p = ppll_rate>>1;
3269                 hclk_p = aclk_p>>0;
3270                 pclk_p = aclk_p>>1;
3271                 break;
3272
3273         case 300 * MHZ:
3274                 aclk_p = ppll_rate>>1;
3275                 hclk_p = aclk_p>>0;
3276                 pclk_p = aclk_p>>1;
3277                 break;
3278         default:
3279                 aclk_p = 150 * MHZ;
3280                 hclk_p = 150 * MHZ;
3281                 pclk_p = 75 * MHZ;
3282                 break;
3283         }
3284         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3285         clk_set_rate_nolock(&aclk_periph, aclk_p);
3286         clk_set_rate_nolock(&hclk_periph, hclk_p);
3287         clk_set_rate_nolock(&pclk_periph, pclk_p);
3288 }
3289
3290
3291 void rk30_clock_common_i2s_init(void)
3292 {
3293         struct clk *max_clk,*min_clk;
3294         unsigned long i2s_rate;
3295         //20 times
3296         if(rk30_clock_flags&CLK_FLG_MAX_I2S_49152KHZ)
3297         {
3298                 i2s_rate=49152000;
3299         }else if(rk30_clock_flags&CLK_FLG_MAX_I2S_24576KHZ)
3300         {
3301                 i2s_rate=24576000;
3302         }
3303         else if(rk30_clock_flags&CLK_FLG_MAX_I2S_22579_2KHZ)
3304         {
3305                 i2s_rate=22579000;
3306         }
3307         else if(rk30_clock_flags&CLK_FLG_MAX_I2S_12288KHZ)
3308         {
3309                 i2s_rate=12288000;
3310         }
3311         else
3312         {
3313                 i2s_rate=49152000;
3314         }
3315
3316         if(((i2s_rate*20)<=general_pll_clk.rate)||!(general_pll_clk.rate%i2s_rate))
3317         {
3318                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3319         }
3320         else if(((i2s_rate*20)<=codec_pll_clk.rate)||!(codec_pll_clk.rate%i2s_rate))
3321         {
3322                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3323         }
3324         else
3325         {
3326                 if(general_pll_clk.rate>codec_pll_clk.rate)
3327                         clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3328                 else
3329                         clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3330         }
3331
3332
3333
3334
3335
3336
3337 }
3338 static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long cpll_rate)
3339 {
3340
3341         clk_set_rate_nolock(&clk_cpu, 816*MHZ);//816
3342         //general
3343 #ifdef CONFIG_RK29_VMAC
3344         /* because loader gpll_rate = 300M, but config(nr, nf, no) is not fit for VMAC,
3345          * board with VMAC need gpll 300, so it will do nothing when gpll init,
3346          * DO below to make sure gpll's config use (nr = 1, nf = 25, no = 2)
3347          */
3348         clk_set_rate_nolock(&general_pll_clk, 297 * MHZ);
3349 #endif
3350         clk_set_rate_nolock(&general_pll_clk, gpll_rate);
3351         lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
3352
3353         //code pll
3354         clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
3355
3356         //periph clk
3357         periph_clk_set_init();
3358
3359         //i2s
3360         rk30_clock_common_i2s_init();
3361
3362         // spi
3363         clk_set_rate_nolock(&clk_spi0, clk_spi0.parent->rate);
3364         clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
3365
3366         // uart
3367         if(rk30_clock_flags&CLK_FLG_UART_1_3M)
3368                 clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
3369         else
3370                 clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3371         //mac
3372         if(!(gpll_rate%(50*MHZ)))
3373                 clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3374         else if(!(ddr_pll_clk.rate%(50*MHZ)))
3375                 clk_set_parent_nolock(&clk_mac_pll_div, &ddr_pll_clk);
3376         else
3377                 CRU_PRINTK_ERR("mac can't get 50mhz\n");
3378
3379         //hsadc
3380         //auto pll sel
3381         //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
3382
3383         //lcdc1  hdmi
3384         clk_set_parent_nolock(&dclk_lcdc1_div, &general_pll_clk);
3385
3386         //lcdc0 lcd auto sel pll
3387         //clk_set_parent_nolock(&dclk_lcdc0_div, &general_pll_clk);
3388
3389         //cif
3390         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3391
3392         //axi lcdc auto sel
3393         //clk_set_parent_nolock(&aclk_lcdc0, &general_pll_clk);
3394         //clk_set_parent_nolock(&aclk_lcdc1, &general_pll_clk);
3395         clk_set_rate_nolock(&aclk_lcdc0_ipp_parent, 300*MHZ);
3396         clk_set_rate_nolock(&aclk_lcdc1_rga_parent, 300*MHZ);
3397
3398         //axi vepu auto sel
3399         //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
3400         //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
3401
3402         clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
3403         clk_set_rate_nolock(&aclk_vdpu, 300*MHZ);
3404         //gpu auto sel
3405         //clk_set_parent_nolock(&clk_gpu, &general_pll_clk);
3406
3407         clk_set_rate_nolock(&clk_uart0, 49500000);
3408         clk_set_rate_nolock(&clk_sdmmc, 24750000);
3409         clk_set_rate_nolock(&clk_sdio, 24750000);
3410 }
3411
3412 static struct clk def_ops_clk={
3413         .get_parent=clksel_get_parent,
3414         .set_parent=clksel_set_parent,
3415 };
3416
3417 #ifdef CONFIG_PROC_FS
3418 struct clk_dump_ops dump_ops;
3419 #endif
3420
3421 static void clk_dump_regs(void);
3422
3423 void __init _rk30_clock_data_init(unsigned long gpll,unsigned long cpll,int flags)
3424 {
3425         struct clk_lookup *lk;
3426
3427         clk_register_dump_ops(&dump_ops);
3428         clk_register_default_ops_clk(&def_ops_clk);
3429         rk30_clock_flags=flags;
3430         for (lk = clks; lk < clks + ARRAY_SIZE(clks); lk++) {
3431                 #ifdef RK30_CLK_OFFBOARD_TEST
3432                         rk30_clkdev_add(lk);
3433                 #else
3434                         clkdev_add(lk);
3435                 #endif
3436                 clk_register(lk->clk);
3437         }
3438         clk_recalculate_root_clocks_nolock();
3439
3440         loops_per_jiffy = CLK_LOOPS_RECALC(arm_pll_clk.rate);
3441
3442         /*
3443          * Only enable those clocks we will need, let the drivers
3444          * enable other clocks as necessary
3445          */
3446         rk30_init_enable_clocks();
3447
3448         /*
3449          * Disable any unused clocks left on by the bootloader
3450          */
3451         //clk_disable_unused();
3452         rk30_clock_common_init(gpll,cpll);
3453         preset_lpj = loops_per_jiffy;
3454
3455         //gpio6_b7
3456         //regfile_writel(0xc0004000,0x10c);
3457         //cru_writel(0x07000000,CRU_MISC_CON);
3458
3459 }
3460 int rk_dvfs_init(void);
3461
3462 void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags)
3463 {
3464         _rk30_clock_data_init(gpll,cpll,flags);
3465         rk_dvfs_init();
3466 }
3467
3468 /*
3469  * You can override arm_clk rate with armclk= cmdline option.
3470  */
3471 static int __init armclk_setup(char *str)
3472 {
3473         get_option(&str, &armclk);
3474
3475         if (!armclk)
3476                 return 0;
3477         if (armclk < 10000)
3478                 armclk *= MHZ;
3479         //clk_set_rate_nolock(&arm_pll_clk, armclk);
3480         return 0;
3481 }
3482 #ifndef RK30_CLK_OFFBOARD_TEST
3483 early_param("armclk", armclk_setup);
3484 #endif
3485
3486
3487
3488 #ifdef CONFIG_PROC_FS
3489
3490 static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks)
3491 {
3492         struct clk* ck;
3493         int i;
3494         unsigned long rate = clk->rate;
3495         //CRU_PRINTK_DBG("dump_clock %s\n",clk->name);
3496         for (i = 0; i < deep; i++)
3497                 seq_printf(s, "    ");
3498
3499         seq_printf(s, "%-11s ", clk->name);
3500 #ifndef RK30_CLK_OFFBOARD_TEST
3501         if (clk->flags & IS_PD) {
3502                         seq_printf(s, "%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
3503         }
3504 #endif
3505         if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
3506                 int idx = clk->gate_idx;
3507                 u32 v;
3508                 v = cru_readl(CLK_GATE_CLKID_CONS(idx))&((0x1)<<(idx%16));
3509                 seq_printf(s, "%s ", v ? "off" : "on ");
3510         }
3511
3512         if (clk->pll)
3513         {
3514                 u32 pll_mode;
3515                 u32 pll_id=clk->pll->id;
3516                 pll_mode=cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
3517                 if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
3518                         seq_printf(s, "slow   ");
3519                 else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
3520                         seq_printf(s, "normal ");
3521                 else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
3522                         seq_printf(s, "deep   ");
3523
3524                 if(cru_readl(PLL_CONS(pll_id,3)) & PLL_BYPASS)
3525                         seq_printf(s, "bypass ");
3526         }
3527         else if(clk == &clk_ddr) {
3528                 rate = clk->recalc(clk);
3529         }
3530
3531         if (rate >= MHZ) {
3532                 if (rate % MHZ)
3533                         seq_printf(s, "%ld.%06ld MHz", rate / MHZ, rate % MHZ);
3534                 else
3535                         seq_printf(s, "%ld MHz", rate / MHZ);
3536         } else if (rate >= KHZ) {
3537                 if (rate % KHZ)
3538                         seq_printf(s, "%ld.%03ld KHz", rate / KHZ, rate % KHZ);
3539                 else
3540                         seq_printf(s, "%ld KHz", rate / KHZ);
3541         } else {
3542                 seq_printf(s, "%ld Hz", rate);
3543         }
3544
3545         seq_printf(s, " usecount = %d", clk->usecount);
3546
3547         if (clk->parent)
3548                 seq_printf(s, " parent = %s", clk->parent->name);
3549
3550         seq_printf(s, "\n");
3551
3552         list_for_each_entry(ck, root_clocks, node) {
3553                 if (ck->parent == clk)
3554                         dump_clock(s, ck, deep + 1,root_clocks);
3555         }
3556 }
3557
3558 static void dump_regs(struct seq_file *s)
3559 {
3560         int i=0;
3561         seq_printf(s, "\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3562         seq_printf(s, "\nPLLRegisters:\n");
3563         for(i=0;i<END_PLL_ID;i++)
3564         {
3565                 seq_printf(s,"pll%d        :cons:%x,%x,%x,%x\n",i,
3566                         cru_readl(PLL_CONS(i,0)),
3567                         cru_readl(PLL_CONS(i,1)),
3568                         cru_readl(PLL_CONS(i,2)),
3569                         cru_readl(PLL_CONS(i,3))
3570                         );
3571         }
3572                 seq_printf(s, "MODE        :%x\n", cru_readl(CRU_MODE_CON));
3573
3574         for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
3575         {
3576                 seq_printf(s,"CLKSEL%d     :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
3577         }
3578         for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
3579         {
3580                 seq_printf(s,"CLKGATE%d           :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
3581         }
3582         seq_printf(s,"GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
3583         seq_printf(s,"GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
3584
3585         for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
3586         {
3587                 seq_printf(s,"CLKGATE%d           :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
3588         }
3589         seq_printf(s,"CRU MISC    :%x\n",cru_readl(CRU_MISC_CON));
3590         seq_printf(s,"GLB_CNT_TH  :%x\n",cru_readl(CRU_GLB_CNT_TH));
3591
3592 }
3593
3594 void rk30_clk_dump_regs(void)
3595 {
3596         int i=0;
3597         printk("\nPLL(id=0 apll,id=1,dpll,id=2,cpll,id=3 cpll)\n");
3598         printk("\nPLLRegisters:\n");
3599         for(i=0;i<END_PLL_ID;i++)
3600         {
3601                 printk("pll%d        :cons:%x,%x,%x,%x\n",i,
3602                         cru_readl(PLL_CONS(i,0)),
3603                         cru_readl(PLL_CONS(i,1)),
3604                         cru_readl(PLL_CONS(i,2)),
3605                         cru_readl(PLL_CONS(i,3))
3606                         );
3607         }
3608                 printk("MODE        :%x\n", cru_readl(CRU_MODE_CON));
3609
3610         for(i=0;i<CRU_CLKSELS_CON_CNT;i++)
3611         {
3612                 printk("CLKSEL%d           :%x\n",i,cru_readl(CRU_CLKSELS_CON(i)));
3613         }
3614         for(i=0;i<CRU_CLKGATES_CON_CNT;i++)
3615         {
3616                 printk("CLKGATE%d         :%x\n",i,cru_readl(CRU_CLKGATES_CON(i)));
3617         }
3618         printk("GLB_SRST_FST:%x\n",cru_readl(CRU_GLB_SRST_FST));
3619         printk("GLB_SRST_SND:%x\n",cru_readl(CRU_GLB_SRST_SND));
3620
3621         for(i=0;i<CRU_SOFTRSTS_CON_CNT;i++)
3622         {
3623                 printk("SOFTRST%d         :%x\n",i,cru_readl(CRU_SOFTRSTS_CON(i)));
3624         }
3625         printk("CRU MISC    :%x\n",cru_readl(CRU_MISC_CON));
3626         printk("GLB_CNT_TH  :%x\n",cru_readl(CRU_GLB_CNT_TH));
3627
3628 }
3629
3630
3631 #ifdef CONFIG_PROC_FS
3632 static void dump_clock(struct seq_file *s, struct clk *clk, int deep,const struct list_head *root_clocks);
3633 struct clk_dump_ops dump_ops={
3634         .dump_clk=dump_clock,
3635         .dump_regs=dump_regs,
3636 };
3637 #endif
3638
3639
3640 #endif /* CONFIG_PROC_FS */
3641
3642
3643
3644
3645 #ifdef RK30_CLK_OFFBOARD_TEST
3646 struct clk *test_get_parent(struct clk *clk)
3647 {
3648         return clk->parent;
3649 }
3650
3651 void i2s_test(void)
3652 {
3653         struct clk *i2s_clk=&clk_i2s0;
3654
3655         clk_enable_nolock(i2s_clk);
3656
3657         clk_set_rate_nolock(i2s_clk, 12288000);
3658         printk("int %s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
3659         clk_set_rate_nolock(i2s_clk, 297*MHZ/2);
3660         printk("int%s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
3661         clk_set_rate_nolock(i2s_clk, 12*MHZ);
3662         printk("int%s parent is %s\n",i2s_clk->name,test_get_parent(i2s_clk)->name);
3663
3664 }
3665
3666 void uart_test(void)
3667 {
3668         struct clk *uart_clk=&clk_uart0;
3669
3670         clk_enable_nolock(uart_clk);
3671
3672         clk_set_rate_nolock(uart_clk, 12288000);
3673         printk("int %s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3674         clk_set_rate_nolock(uart_clk, 297*MHZ/2);
3675         printk("int%s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3676         clk_set_rate_nolock(uart_clk, 12*MHZ);
3677         printk("int%s parent is %s\n",uart_clk->name,test_get_parent(uart_clk)->name);
3678
3679 }
3680 void hsadc_test(void)
3681 {
3682         struct clk *hsadc_clk=&clk_hsadc;
3683
3684         printk("******************hsadc_test**********************\n");
3685         clk_enable_nolock(hsadc_clk);
3686
3687         clk_set_rate_nolock(hsadc_clk, 12288000);
3688         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3689
3690
3691         clk_set_rate_nolock(hsadc_clk, 297*MHZ/2);
3692         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3693
3694         clk_set_rate_nolock(hsadc_clk, 300*MHZ/2);
3695
3696         clk_set_rate_nolock(hsadc_clk, 296*MHZ/2);
3697
3698         printk("******************hsadc out clock**********************\n");
3699
3700         clk_set_parent_nolock(hsadc_clk, &clk_hsadc_ext);
3701         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3702         clk_set_rate_nolock(hsadc_clk, 297*MHZ/2);
3703         printk("****end %s parent is %s\n",hsadc_clk->name,test_get_parent(hsadc_clk)->name);
3704
3705
3706
3707 }
3708
3709 static void __init rk30_clock_test_init(unsigned long ppll_rate)
3710 {
3711         //arm
3712         printk("*********arm_pll_clk***********\n");
3713         clk_set_rate_nolock(&arm_pll_clk, 816*MHZ);
3714
3715         printk("*********set clk_cpu parent***********\n");
3716         clk_set_parent_nolock(&clk_cpu, &arm_pll_clk);
3717         clk_set_rate_nolock(&clk_cpu, 504*MHZ);
3718
3719         //general
3720         printk("*********general_pll_clk***********\n");
3721         clk_set_rate_nolock(&general_pll_clk, ppll_rate);
3722
3723         //code pll
3724         printk("*********codec_pll_clk***********\n");
3725         clk_set_rate_nolock(&codec_pll_clk, 600*MHZ);
3726
3727
3728         printk("*********periph_clk_set_init***********\n");
3729         clk_set_parent_nolock(&aclk_periph, &general_pll_clk);
3730         periph_clk_set_init();
3731
3732         #if 0 //
3733                 clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
3734         #else
3735                 printk("*********clk i2s***********\n");
3736                 clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
3737                 printk("common %s parent is %s\n",clk_i2s_pll.name,test_get_parent(&clk_i2s_pll)->name);
3738                 i2s_test();
3739         #endif
3740 // spi
3741         clk_enable_nolock(&clk_spi0);
3742         clk_set_rate_nolock(&clk_spi0, 30*MHZ);
3743         printk("common %s parent is %s\n",clk_spi0.name,test_get_parent(&clk_spi0)->name);
3744 //saradc
3745         clk_enable_nolock(&clk_saradc);
3746         clk_set_rate_nolock(&clk_saradc, 6*MHZ);
3747         printk("common %s parent is %s\n",clk_saradc.name,test_get_parent(&clk_saradc)->name);
3748 //sdio
3749         clk_enable_nolock(&clk_sdio);
3750         clk_set_rate_nolock(&clk_sdio, 50*MHZ);
3751         printk("common %s parent is %s\n",clk_sdio.name,test_get_parent(&clk_sdio)->name);
3752 // uart
3753         clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
3754         uart_test();
3755 //mac
3756         printk("*********mac***********\n");
3757
3758         clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);
3759         printk("common %s parent is %s\n",clk_mac_pll_div.name,test_get_parent(&clk_mac_pll_div)->name);
3760
3761         //clk_set_parent_nolock(&clk_mac_ref, &clk_mac_pll_div);
3762         clk_set_rate_nolock(&clk_mac_ref, 50*MHZ);
3763         printk("common %s parent is %s\n",clk_mac_ref.name,test_get_parent(&clk_mac_ref)->name);
3764
3765         printk("*********mac mii set***********\n");
3766         clk_set_parent_nolock(&clk_mac_ref, &rmii_clkin);
3767         clk_set_rate_nolock(&clk_mac_ref, 20*MHZ);
3768         printk("common %s parent is %s\n",clk_mac_ref.name,test_get_parent(&clk_mac_ref)->name);
3769 //hsadc
3770         printk("*********hsadc 1***********\n");
3771         //auto pll
3772         hsadc_test();
3773 //lcdc
3774         clk_enable_nolock(&dclk_lcdc0);
3775
3776         clk_set_rate_nolock(&dclk_lcdc0, 60*MHZ);
3777         clk_set_rate_nolock(&dclk_lcdc0, 27*MHZ);
3778
3779 //cif
3780         clk_enable_nolock(&cif0_out);
3781
3782         clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
3783         printk("common %s parent is %s\n",cif_out_pll.name,test_get_parent(&cif_out_pll)->name);
3784
3785         clk_set_rate_nolock(&cif0_out, 60*MHZ);
3786         printk("common %s parent is %s\n",cif0_out.name,test_get_parent(&cif0_out)->name);
3787
3788         clk_set_rate_nolock(&cif0_out, 24*MHZ);
3789         printk("common %s parent is %s\n",cif0_out.name,test_get_parent(&cif0_out)->name);
3790 //cif_in
3791         clk_enable_nolock(&cif0_in);
3792         clk_set_rate_nolock(&cif0_in, 24*MHZ);
3793 //axi lcdc
3794         clk_enable_nolock(&aclk_lcdc0);
3795         clk_set_rate_nolock(&aclk_lcdc0, 150*MHZ);
3796         printk("common %s parent is %s\n",aclk_lcdc0.name,test_get_parent(&aclk_lcdc0)->name);
3797 //axi vepu
3798         clk_enable_nolock(&aclk_vepu);
3799         clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
3800         printk("common %s parent is %s\n",aclk_vepu.name,test_get_parent(&aclk_vepu)->name);
3801
3802         clk_set_rate_nolock(&hclk_vepu, 300*MHZ);
3803         printk("common %s parent is %s\n",hclk_vepu.name,test_get_parent(&hclk_vepu)->name);
3804
3805         printk("test end\n");
3806
3807         /* arm pll
3808         clk_set_rate_nolock(&arm_pll_clk, armclk);
3809         clk_set_rate_nolock(&clk_cpu,   armclk);//pll:core =1:1
3810         */
3811         //
3812         //clk_set_rate_nolock(&codec_pll_clk, ppll_rate*2);
3813         //
3814         //clk_set_rate_nolock(&aclk_vepu, 300 * MHZ);
3815         //clk_set_rate_nolock(&clk_gpu, 300 * MHZ);
3816
3817 }
3818
3819
3820
3821
3822
3823 static LIST_HEAD(rk30_clocks);
3824 static DEFINE_MUTEX(rk30_clocks_mutex);
3825
3826 static inline int __rk30clk_get(struct clk *clk)
3827 {
3828         return 1;
3829 }
3830 void rk30_clkdev_add(struct clk_lookup *cl)
3831 {
3832         mutex_lock(&rk30_clocks_mutex);
3833         list_add_tail(&cl->node, &rk30_clocks);
3834         mutex_unlock(&rk30_clocks_mutex);
3835 }
3836 static struct clk_lookup *rk30_clk_find(const char *dev_id, const char *con_id)
3837 {
3838         struct clk_lookup *p, *cl = NULL;
3839         int match, best = 0;
3840
3841         list_for_each_entry(p, &rk30_clocks, node) {
3842                 match = 0;
3843                 if (p->dev_id) {
3844                         if (!dev_id || strcmp(p->dev_id, dev_id))
3845                                 continue;
3846                         match += 2;
3847                 }
3848                 if (p->con_id) {
3849                         if (!con_id || strcmp(p->con_id, con_id))
3850                                 continue;
3851                         match += 1;
3852                 }
3853
3854                 if (match > best) {
3855                         cl = p;
3856                         if (match != 3)
3857                                 best = match;
3858                         else
3859                                 break;
3860                 }
3861         }
3862         return cl;
3863 }
3864
3865 struct clk *rk30_clk_get_sys(const char *dev_id, const char *con_id)
3866 {
3867         struct clk_lookup *cl;
3868
3869         mutex_lock(&rk30_clocks_mutex);
3870         cl = rk30_clk_find(dev_id, con_id);
3871         if (cl && !__rk30clk_get(cl->clk))
3872                 cl = NULL;
3873         mutex_unlock(&rk30_clocks_mutex);
3874
3875         return cl ? cl->clk : ERR_PTR(-ENOENT);
3876 }
3877 //EXPORT_SYMBOL(rk30_clk_get_sys);
3878
3879 struct clk *rk30_clk_get(struct device *dev, const char *con_id)
3880 {
3881         const char *dev_id = dev ? dev_name(dev) : NULL;
3882         return rk30_clk_get_sys(dev_id, con_id);
3883 }
3884 //EXPORT_SYMBOL(rk30_clk_get);
3885
3886
3887 int rk30_clk_set_rate(struct clk *clk, unsigned long rate);
3888
3889 void rk30_clocks_test(void)
3890 {
3891     struct clk *test_gpll;
3892         test_gpll=rk30_clk_get(NULL,"general_pll");
3893         if(test_gpll)
3894         {
3895                 rk30_clk_set_rate(test_gpll,297*2*MHZ);
3896                 printk("gpll rate=%lu\n",test_gpll->rate);
3897         }
3898         //while(1);
3899 }
3900
3901 void __init rk30_clock_init_test(void){
3902
3903         rk30_clock_init(periph_pll_297mhz,codec_pll_360mhz,max_i2s_12288khz);
3904         //while(1);
3905 }
3906
3907
3908 #endif
3909
3910