common.c

   1 #include <linux/clk.h>
   2 #include <linux/cpufreq.h>
   3 #include <linux/kernel.h>
   4 #include <linux/interrupt.h>
   5 #include <linux/irq.h>
   6 #include <linux/io.h>
   7
   8 #include <asm/pgtable-hwdef.h>
   9 #include <asm/hardware/gic.h>
  10 #include <asm/mach/arch.h>
  11 #include <asm/hardware/cache-l2x0.h>
  12
  13 #include <plat/sram.h>
  14 #include <mach/board.h>
  15 #include <mach/gpio.h>
  16 #include <mach/iomux.h>
  17 #include <mach/fiq.h>
  18 #include <mach/pmu.h>
  19 #include <mach/loader.h>
  20 #include <mach/ddr.h>
  21 #include <mach/dvfs.h>
  22 #include <mach/cpu_axi.h>
  23 #include <mach/debug_uart.h>
  24
  25 static void __init rk30_cpu_axi_init(void)
  26 {
  27         CPU_AXI_SET_QOS_PRIORITY(0, 0, DMAC);
  28         CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU0);
  29         CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1R);
  30         CPU_AXI_SET_QOS_PRIORITY(0, 0, CPU1W);
  31 #ifdef CONFIG_RK29_VMAC
  32         CPU_AXI_SET_QOS_PRIORITY(2, 2, PERI);
  33 #else
  34         CPU_AXI_SET_QOS_PRIORITY(0, 0, PERI);
  35 #endif
  36         CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC0);
  37         CPU_AXI_SET_QOS_PRIORITY(3, 3, LCDC1);
  38
  39         writel_relaxed(0x3f, RK30_CPU_AXI_BUS_BASE + 0x0014);   // memory scheduler read latency
  40         dsb();
  41 }
  42
  43 #define L2_LY_SP_OFF (0)
  44 #define L2_LY_SP_MSK (0x7)
  45
  46 #define L2_LY_RD_OFF (4)
  47 #define L2_LY_RD_MSK (0x7)
  48
  49 #define L2_LY_WR_OFF (8)
  50 #define L2_LY_WR_MSK (0x7)
  51 #define L2_LY_SET(ly,off) (((ly)-1)<<(off))
  52
  53 #define L2_LATENCY(setup_cycles, read_cycles, write_cycles) \
  54         L2_LY_SET(setup_cycles, L2_LY_SP_OFF) | \
  55         L2_LY_SET(read_cycles, L2_LY_RD_OFF) | \
  56         L2_LY_SET(write_cycles, L2_LY_WR_OFF)
  57
  58 static void __init rk30_l2_cache_init(void)
  59 {
  60 #ifdef CONFIG_CACHE_L2X0
  61         u32 aux_ctrl, aux_ctrl_mask, data_latency_ctrl;
  62 #if defined(CONFIG_ARCH_RK3188)
  63         data_latency_ctrl = L2_LATENCY(2, 3, 1);
  64 #else
  65         unsigned int max_cpu_freq = 1608000; // kHz
  66         struct cpufreq_frequency_table *table = NULL;
  67         struct clk *clk_cpu;
  68         int i;
  69
  70         clk_cpu = clk_get(NULL, "cpu");
  71         if (!IS_ERR(clk_cpu)) {
  72                 table = dvfs_get_freq_volt_table(clk_cpu);
  73                 if (!table)
  74                         pr_err("failed to get cpu freq volt table\n");
  75         } else
  76                 pr_err("failed to get clk cpu\n");
  77         for (i = 0; table && table[i].frequency != CPUFREQ_TABLE_END; i++) {
  78                 if (max_cpu_freq < table[i].frequency)
  79                         max_cpu_freq = table[i].frequency;
  80         }
  81
  82         if (max_cpu_freq <= 1608000)
  83                 data_latency_ctrl = L2_LATENCY(4, 6, 1);
  84         else if (max_cpu_freq <= 1800000)
  85                 data_latency_ctrl = L2_LATENCY(5, 7, 1);
  86         else if (max_cpu_freq <= 1992000)
  87                 data_latency_ctrl = L2_LATENCY(5, 8, 1);
  88         else
  89                 data_latency_ctrl = L2_LATENCY(6, 8, 1);
  90 #endif
  91
  92         writel_relaxed(L2_LATENCY(1, 1, 1), RK30_L2C_BASE + L2X0_TAG_LATENCY_CTRL);
  93         writel_relaxed(data_latency_ctrl, RK30_L2C_BASE + L2X0_DATA_LATENCY_CTRL);
  94
  95         /* L2X0 Prefetch Control */
  96         writel_relaxed(0x70000003, RK30_L2C_BASE + L2X0_PREFETCH_CTRL);
  97
  98         /* L2X0 Power Control */
  99         writel_relaxed(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, RK30_L2C_BASE + L2X0_POWER_CTRL);
 100
 101         aux_ctrl = (
 102                         (0x1 << 25) |   // round-robin
 103                         (0x1 << 0) |            // Full Line of Zero Enable
 104                         (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
 105                         (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
 106                         (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
 107                         (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
 108
 109         aux_ctrl_mask = ~(
 110                         (0x1 << 25) |   // round-robin
 111                         (0x1 << 0) |            // Full Line of Zero Enable
 112                         (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
 113                         (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
 114                         (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
 115                         (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT) );
 116
 117         l2x0_init(RK30_L2C_BASE, aux_ctrl, aux_ctrl_mask);
 118 #endif
 119 }
 120
 121 static int boot_mode;
 122
 123 static const char *boot_flag_name(u32 flag)
 124 {
 125         flag -= SYS_KERNRL_REBOOT_FLAG;
 126         switch (flag) {
 127         case BOOT_NORMAL: return "NORMAL";
 128         case BOOT_LOADER: return "LOADER";
 129         case BOOT_MASKROM: return "MASKROM";
 130         case BOOT_RECOVER: return "RECOVER";
 131         case BOOT_NORECOVER: return "NORECOVER";
 132         case BOOT_SECONDOS: return "SECONDOS";
 133         case BOOT_WIPEDATA: return "WIPEDATA";
 134         case BOOT_WIPEALL: return "WIPEALL";
 135         case BOOT_CHECKIMG: return "CHECKIMG";
 136         case BOOT_FASTBOOT: return "FASTBOOT";
 137         default: return "";
 138         }
 139 }
 140
 141 static const char *boot_mode_name(u32 mode)
 142 {
 143         switch (mode) {
 144         case BOOT_MODE_NORMAL: return "NORMAL";
 145         case BOOT_MODE_FACTORY2: return "FACTORY2";
 146         case BOOT_MODE_RECOVERY: return "RECOVERY";
 147         case BOOT_MODE_CHARGE: return "CHARGE";
 148         case BOOT_MODE_POWER_TEST: return "POWER_TEST";
 149         case BOOT_MODE_OFFMODE_CHARGING: return "OFFMODE_CHARGING";
 150         case BOOT_MODE_REBOOT: return "REBOOT";
 151         case BOOT_MODE_PANIC: return "PANIC";
 152         case BOOT_MODE_WATCHDOG: return "WATCHDOG";
 153         default: return "";
 154         }
 155 }
 156
 157 static void __init rk30_boot_mode_init(void)
 158 {
 159         u32 boot_flag = readl_relaxed(RK30_PMU_BASE + PMU_SYS_REG0);
 160         boot_mode = readl_relaxed(RK30_PMU_BASE + PMU_SYS_REG1);
 161
 162         if (boot_flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER)) {
 163                 boot_mode = BOOT_MODE_RECOVERY;
 164         }
 165         if (boot_mode || ((boot_flag & 0xff) && ((boot_flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
 166                 printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(boot_mode), boot_mode, boot_flag_name(boot_flag), boot_flag);
 167 #ifdef CONFIG_RK29_WATCHDOG
 168         writel_relaxed(BOOT_MODE_WATCHDOG, RK30_PMU_BASE + PMU_SYS_REG1);
 169 #endif
 170 }
 171
 172 int board_boot_mode(void)
 173 {
 174         return boot_mode;
 175 }
 176 EXPORT_SYMBOL(board_boot_mode);
 177
 178 void __init rk30_init_irq(void)
 179 {
 180         gic_init(0, IRQ_LOCALTIMER, RK30_GICD_BASE, RK30_GICC_BASE);
 181 #ifdef CONFIG_FIQ
 182         rk_fiq_init();
 183 #endif
 184         rk30_gpio_init();
 185 }
 186
 187 static void usb_uart_init(void)
 188 {
 189 #if defined(CONFIG_ARCH_RK3188) && (CONFIG_RK_DEBUG_UART == 2)
 190 #ifdef CONFIG_RK_USB_UART
 191         if (!(readl_relaxed(RK30_GRF_BASE + GRF_SOC_STATUS0) & (1 << 13))) { //detect id
 192                 writel_relaxed((0x0300 << 16), RK30_GRF_BASE + GRF_UOC0_CON0);
 193         } else {
 194                 if (!(readl_relaxed(RK30_GRF_BASE + GRF_SOC_STATUS0) & (1 << 10))) { //detect vbus
 195                         writel_relaxed(((0x01 << 2) | ((0x01 << 2) << 16)), RK30_GRF_BASE + GRF_UOC0_CON2); //software control usb phy enable
 196                         writel_relaxed((0x2A | (0x3F << 16)), RK30_GRF_BASE + GRF_UOC0_CON3); //usb phy enter suspend
 197                         writel_relaxed((0x0300 | (0x0300 << 16)), RK30_GRF_BASE + GRF_UOC0_CON0);
 198                 } else {
 199                         writel_relaxed((0x0300 << 16), RK30_GRF_BASE + GRF_UOC0_CON0);
 200                 }
 201         }
 202 #else
 203         writel_relaxed((0x0300 << 16), RK30_GRF_BASE + GRF_UOC0_CON0);
 204 #endif
 205 #endif
 206 }
 207
 208 void __init rk30_map_io(void)
 209 {
 210         rk30_map_common_io();
 211         usb_uart_init();
 212         rk29_setup_early_printk();
 213         rk30_cpu_axi_init();
 214         rk29_sram_init();
 215         board_clock_init();
 216         rk30_l2_cache_init();
 217         ddr_init(DDR_TYPE, DDR_FREQ);
 218         clk_disable_unused();
 219         rk30_iomux_init();
 220         rk30_boot_mode_init();
 221 }
 222
 223 static __init u32 rk30_get_ddr_size(void)
 224 {
 225         u32 size;
 226         u32 v[3], a[3];
 227         u32 pgtbl = PAGE_OFFSET + TEXT_OFFSET - 0x4000;
 228         u32 flag = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ;
 229
 230         a[0] = pgtbl + (((u32)RK30_CPU_AXI_BUS_BASE >> 20) << 2);
 231         a[1] = pgtbl + (((u32)RK30_DDR_PUBL_BASE >> 20) << 2);
 232         a[2] = pgtbl + (((u32)RK30_GRF_BASE >> 20) << 2);
 233         v[0] = readl_relaxed(a[0]);
 234         v[1] = readl_relaxed(a[1]);
 235         v[2] = readl_relaxed(a[2]);
 236         writel_relaxed(flag | ((RK30_CPU_AXI_BUS_PHYS >> 20) << 20), a[0]);
 237         writel_relaxed(flag | ((RK30_DDR_PUBL_PHYS >> 20) << 20), a[1]);
 238         writel_relaxed(flag | ((RK30_GRF_PHYS >> 20) << 20), a[2]);
 239
 240         size = ddr_get_cap();
 241
 242         writel_relaxed(v[0], a[0]);
 243         writel_relaxed(v[1], a[1]);
 244         writel_relaxed(v[2], a[2]);
 245
 246         return size;
 247 }
 248
 249 void __init rk30_fixup(struct machine_desc *desc, struct tag *tags,
 250                         char **cmdline, struct meminfo *mi)
 251 {
 252         mi->nr_banks = 1;
 253         mi->bank[0].start = PLAT_PHYS_OFFSET;
 254         mi->bank[0].size = rk30_get_ddr_size();
 255 }
 256