2 * arch/arm/mach-rk30/ddr.c
4 * Function Driver for DDR controller
6 * Copyright (C) 2011 Fuzhou Rockchip Electronics Co.,Ltd
14 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/clk.h>
19 #include <asm/cacheflush.h>
20 #include <asm/tlbflush.h>
22 #include <mach/sram.h>
25 #include <plat/efuse.h>
27 typedef uint32_t uint32;
29 #define ENABLE_DDR_CLCOK_GPLL_PATH //for RK3188
31 #define DDR3_DDR2_DLL_DISABLE_FREQ (125)
32 #define DDR3_DDR2_ODT_DISABLE_FREQ (333)
33 #define SR_IDLE (0x1) //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
34 #define PD_IDLE (0X40) //unit:DDR clk cycle, and 0 for disable auto power-down
36 #define PMU_BASE_ADDR RK30_PMU_BASE
37 #define SDRAMC_BASE_ADDR RK30_DDR_PCTL_BASE
38 #define DDR_PUBL_BASE RK30_DDR_PUBL_BASE
39 #define CRU_BASE_ADDR RK30_CRU_BASE
40 #define REG_FILE_BASE_ADDR RK30_GRF_BASE
41 #define SysSrv_DdrConf (RK30_CPU_AXI_BUS_BASE+0x08)
42 #define SysSrv_DdrTiming (RK30_CPU_AXI_BUS_BASE+0x0c)
43 #define SysSrv_DdrMode (RK30_CPU_AXI_BUS_BASE+0x10)
44 #define SysSrv_ReadLatency (RK30_CPU_AXI_BUS_BASE+0x14)
46 #define ddr_print(x...) printk( "DDR DEBUG: " x )
48 /***********************************
50 ***********************************/
51 //MR0 (Device Information)
52 #define LPDDR2_DAI (0x1) // 0:DAI complete, 1:DAI still in progress
53 #define LPDDR2_DI (0x1<<1) // 0:S2 or S4 SDRAM, 1:NVM
54 #define LPDDR2_DNVI (0x1<<2) // 0:DNV not supported, 1:DNV supported
55 #define LPDDR2_RZQI (0x3<<3) // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
56 // 10:ZQ-pin may short to GND. 11:ZQ-pin self test completed, no error condition detected.
58 //MR1 (Device Feature)
59 #define LPDDR2_BL4 (0x2)
60 #define LPDDR2_BL8 (0x3)
61 #define LPDDR2_BL16 (0x4)
62 #define LPDDR2_nWR(n) (((n)-2)<<5)
64 //MR2 (Device Feature 2)
65 #define LPDDR2_RL3_WL1 (0x1)
66 #define LPDDR2_RL4_WL2 (0x2)
67 #define LPDDR2_RL5_WL2 (0x3)
68 #define LPDDR2_RL6_WL3 (0x4)
69 #define LPDDR2_RL7_WL4 (0x5)
70 #define LPDDR2_RL8_WL4 (0x6)
72 //MR3 (IO Configuration 1)
73 #define LPDDR2_DS_34 (0x1)
74 #define LPDDR2_DS_40 (0x2)
75 #define LPDDR2_DS_48 (0x3)
76 #define LPDDR2_DS_60 (0x4)
77 #define LPDDR2_DS_80 (0x6)
78 #define LPDDR2_DS_120 (0x7) //optional
80 //MR4 (Device Temperature)
81 #define LPDDR2_tREF_MASK (0x7)
82 #define LPDDR2_4_tREF (0x1)
83 #define LPDDR2_2_tREF (0x2)
84 #define LPDDR2_1_tREF (0x3)
85 #define LPDDR2_025_tREF (0x5)
86 #define LPDDR2_025_tREF_DERATE (0x6)
88 #define LPDDR2_TUF (0x1<<7)
90 //MR8 (Basic configuration 4)
91 #define LPDDR2_S4 (0x0)
92 #define LPDDR2_S2 (0x1)
93 #define LPDDR2_N (0x2)
94 #define LPDDR2_Density(mr8) (8<<(((mr8)>>2)&0xf)) // Unit:MB
95 #define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
98 #define LPDDR2_ZQINIT (0xFF)
99 #define LPDDR2_ZQCL (0xAB)
100 #define LPDDR2_ZQCS (0x56)
101 #define LPDDR2_ZQRESET (0xC3)
103 //MR16 (PASR Bank Mask)
105 #define LPDDR2_PASR_Full (0x0)
106 #define LPDDR2_PASR_1_2 (0x1)
107 #define LPDDR2_PASR_1_4 (0x2)
108 #define LPDDR2_PASR_1_8 (0x3)
110 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
112 //MR32 (DQ Calibration Pattern A)
114 //MR40 (DQ Calibration Pattern B)
116 /***********************************
118 ***********************************/
121 #define DDR3_BC4_8 (1)
123 #define DDR3_CL(n) (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
124 #define DDR3_WR(n) (((n)&0x7)<<9)
125 #define DDR3_DLL_RESET (1<<8)
126 #define DDR3_DLL_DeRESET (0<<8)
129 #define DDR3_DLL_ENABLE (0)
130 #define DDR3_DLL_DISABLE (1)
131 #define DDR3_MR1_AL(n) (((n)&0x3)<<3)
133 #define DDR3_DS_40 (0)
134 #define DDR3_DS_34 (1<<1)
135 #define DDR3_Rtt_Nom_DIS (0)
136 #define DDR3_Rtt_Nom_60 (1<<2)
137 #define DDR3_Rtt_Nom_120 (1<<6)
138 #define DDR3_Rtt_Nom_40 ((1<<2)|(1<<6))
141 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
142 #define DDR3_Rtt_WR_DIS (0)
143 #define DDR3_Rtt_WR_60 (1<<9)
144 #define DDR3_Rtt_WR_120 (2<<9)
146 /***********************************
148 ***********************************/
149 //MR; //Mode Register
152 #define DDR2_CL(n) (((n)&0x7)<<4)
153 #define DDR2_WR(n) ((((n)-1)&0x7)<<9)
154 #define DDR2_DLL_RESET (1<<8)
155 #define DDR2_DLL_DeRESET (0<<8)
157 //EMR; //Extended Mode Register
158 #define DDR2_DLL_ENABLE (0)
159 #define DDR2_DLL_DISABLE (1)
161 #define DDR2_STR_FULL (0)
162 #define DDR2_STR_REDUCE (1<<1)
163 #define DDR2_AL(n) (((n)&0x7)<<3)
164 #define DDR2_Rtt_Nom_DIS (0)
165 #define DDR2_Rtt_Nom_150 (0x40)
166 #define DDR2_Rtt_Nom_75 (0x4)
167 #define DDR2_Rtt_Nom_50 (0x44)
169 /***********************************
171 ***********************************/
175 #define mDDR_CL(n) (((n)&0x7)<<4)
177 #define mDDR_DS_Full (0)
178 #define mDDR_DS_1_2 (1<<5)
179 #define mDDR_DS_1_4 (2<<5)
180 #define mDDR_DS_1_8 (3<<5)
181 #define mDDR_DS_3_4 (4<<5)
185 #define idle_req_cpu_cfg (1<<1)
186 #define idle_req_peri_cfg (1<<2)
187 #define idle_req_gpu_cfg (1<<3)
188 #define idle_req_video_cfg (1<<4)
189 #define idle_req_vio_cfg (1<<5)
190 #define idle_req_core_cfg (1<<14)
191 #define idle_req_dma_cfg (1<<16)
194 #define idle_cpu (1<<26)
195 #define idle_peri (1<<25)
196 #define idle_gpu (1<<24)
197 #define idle_video (1<<23)
198 #define idle_vio (1<<22)
199 #define idle_core (1<<15)
200 #define idle_dma (1<<14)
202 #define pd_a9_0_pwr_st (1<<0)
203 #define pd_a9_1_pwr_st (1<<1)
204 #define pd_peri_pwr_st (1<<6)
205 #define pd_vio_pwr_st (1<<7)
206 #define pd_video_pwr_st (1<<8)
207 #define pd_gpu_pwr_st (1<<9)
211 typedef volatile struct tagPMU_FILE
213 uint32 PMU_WAKEUP_CFG[2];
214 uint32 PMU_PWRDN_CON;
222 uint32 PMU_DDRIO_PWRON_CNT;
223 uint32 PMU_WAKEUP_RST_CLR_CNT;
224 uint32 PMU_SCU_PWRDWN_CNT;
225 uint32 PMU_SCU_PWRUP_CNT;
226 uint32 PMU_MISC_CON1;
227 uint32 PMU_GPIO6_CON;
228 uint32 PMU_PMU_SYS_REG[4];
229 } PMU_FILE, *pPMU_FILE;
231 #define pPMU_Reg ((pPMU_FILE)PMU_BASE_ADDR)
233 #define PLL_RESET (((0x1<<5)<<16) | (0x1<<5))
234 #define PLL_DE_RESET (((0x1<<5)<<16) | (0x0<<5))
235 #define NR(n) ((0x3F<<(8+16)) | (((n)-1)<<8))
236 #define NO(n) ((0xF<<16) | ((n)-1))
237 #define NF(n) ((0x1FFF<<16) | ((n)-1))
238 #define NB(n) ((0xFFF<<16) | ((n)-1))
241 #define PLL_RESET_RK3066B (((0x1<<1)<<16) | (0x1<<1))
242 #define PLL_DE_RESET_RK3066B (((0x1<<1)<<16) | (0x0<<1))
243 #define NR_RK3066B(n) ((0x3F<<(8+16)) | (((n)-1)<<8))
244 #define NO_RK3066B(n) ((0x3F<<16) | ((n)-1))
245 #define NF_RK3066B(n) ((0xFFFF<<16) | ((n)-1))
248 typedef volatile struct tagCRU_STRUCT
250 uint32 CRU_PLL_CON[4][4];
252 uint32 CRU_CLKSEL_CON[35];
253 uint32 CRU_CLKGATE_CON[10];
255 uint32 CRU_GLB_SRST_FST_VALUE;
256 uint32 CRU_GLB_SRST_SND_VALUE;
258 uint32 CRU_SOFTRST_CON[9];
261 uint32 CRU_GLB_CNT_TH;
262 } CRU_REG, *pCRU_REG;
264 #define pCRU_Reg ((pCRU_REG)CRU_BASE_ADDR)
266 #define bank2_to_rank_en ((1<<2) | ((1<<2)<<16))
267 #define bank2_to_rank_dis ((0<<2) | ((1<<2)<<16))
268 #define rank_to_row15_en ((1<<1) | ((1<<1)<<16))
269 #define rank_to_row15_dis ((0<<1) | ((1<<1)<<16))
271 typedef struct tagGPIO_LH
277 typedef struct tagGPIO_IOMUX
286 typedef volatile struct tagREG_FILE
288 GPIO_LH_T GRF_GPIO_DIR[7];
289 GPIO_LH_T GRF_GPIO_DO[7];
290 GPIO_LH_T GRF_GPIO_EN[7];
291 GPIO_IOMUX_T GRF_GPIO_IOMUX[7];
292 GPIO_LH_T GRF_GPIO_PULL[7];
293 uint32 GRF_SOC_CON[3];
294 uint32 GRF_SOC_STATUS0;
295 uint32 GRF_DMAC1_CON[3];
296 uint32 GRF_DMAC2_CON[4];
297 uint32 GRF_UOC0_CON[3];
298 uint32 GRF_UOC1_CON[4];
299 uint32 GRF_DDRC_CON0;
300 uint32 GRF_DDRC_STAT;
301 uint32 reserved[(0x1c8-0x1a0)/4];
302 uint32 GRF_OS_REG[4];
303 } REG_FILE, *pREG_FILE;
305 #define pGRF_Reg ((pREG_FILE)REG_FILE_BASE_ADDR)
308 typedef volatile struct tagREG_FILE_RK3066B
310 GPIO_LH_T GRF_GPIO_DIR[4];
311 GPIO_LH_T GRF_GPIO_DO[4];
312 GPIO_LH_T GRF_GPIO_EN[4];
313 GPIO_IOMUX_T GRF_GPIO_IOMUX[4];
314 uint32 GRF_SOC_CON[3];
315 uint32 GRF_SOC_STATUS0;
316 uint32 GRF_DMAC0_CON[3];
317 uint32 GRF_DMAC1_CON[4];
318 uint32 reserved0[(0xec-0xcc)/4];
319 uint32 GRF_DDRC_CON0;
320 uint32 GRF_DDRC_STAT;
321 uint32 GRF_IO_CON[5];
323 uint32 GRF_UOC0_CON[4];
324 uint32 GRF_UOC1_CON[4];
325 uint32 GRF_UOC2_CON[2];
327 uint32 GRF_UOC3_CON[2];
328 uint32 GRF_HSIC_STAT;
329 uint32 GRF_OS_REG[8];
330 } REG_FILE_RK3066B, *pREG_FILE_RK3066B;
332 #define pGRF_Reg_RK3066B ((pREG_FILE_RK3066B)REG_FILE_BASE_ADDR)
335 #define INIT_STATE (0)
336 #define CFG_STATE (1)
338 #define SLEEP_STATE (3)
339 #define WAKEUP_STATE (4)
344 #define Config_req (2)
346 #define Access_req (4)
347 #define Low_power (5)
348 #define Low_power_entry_req (6)
349 #define Low_power_exit_req (7)
352 #define mddr_lpddr2_clk_stop_idle(n) ((n)<<24)
353 #define pd_idle(n) ((n)<<8)
354 #define mddr_en (2<<22)
355 #define lpddr2_en (3<<22)
356 #define ddr2_en (0<<5)
357 #define ddr3_en (1<<5)
358 #define lpddr2_s2 (0<<6)
359 #define lpddr2_s4 (1<<6)
360 #define mddr_lpddr2_bl_2 (0<<20)
361 #define mddr_lpddr2_bl_4 (1<<20)
362 #define mddr_lpddr2_bl_8 (2<<20)
363 #define mddr_lpddr2_bl_16 (3<<20)
364 #define ddr2_ddr3_bl_4 (0)
365 #define ddr2_ddr3_bl_8 (1)
366 #define tfaw_cfg(n) (((n)-4)<<18)
367 #define pd_exit_slow (0<<17)
368 #define pd_exit_fast (1<<17)
369 #define pd_type(n) ((n)<<16)
370 #define two_t_en(n) ((n)<<3)
371 #define bl8int_en(n) ((n)<<2)
372 #define cke_or_en(n) ((n)<<1)
375 #define power_up_start (1<<0)
378 #define power_up_done (1<<0)
381 #define dfi_init_complete (1<<0)
384 #define cmd_tstat (1<<0)
387 #define cmd_tstat_en (1<<1)
390 #define Deselect_cmd (0)
400 #define lpddr2_op(n) ((n)<<12)
401 #define lpddr2_ma(n) ((n)<<4)
403 #define bank_addr(n) ((n)<<17)
404 #define cmd_addr(n) ((n)<<4)
406 #define start_cmd (1u<<31)
408 typedef union STAT_Tag
413 unsigned ctl_stat : 3;
414 unsigned reserved3 : 1;
415 unsigned lp_trig : 3;
416 unsigned reserved7_31 : 25;
420 typedef union SCFG_Tag
425 unsigned hw_low_power_en : 1;
426 unsigned reserved1_5 : 5;
427 unsigned nfifo_nif1_dis : 1;
428 unsigned reserved7 : 1;
429 unsigned bbflags_timing : 4;
430 unsigned reserved12_31 : 20;
434 /* DDR Controller register struct */
435 typedef volatile struct DDR_REG_Tag
437 //Operational State, Control, and Status Registers
438 SCFG_T SCFG; //State Configuration Register
439 volatile uint32 SCTL; //State Control Register
440 STAT_T STAT; //State Status Register
441 volatile uint32 INTRSTAT; //Interrupt Status Register
442 uint32 reserved0[(0x40-0x10)/4];
443 //Initailization Control and Status Registers
444 volatile uint32 MCMD; //Memory Command Register
445 volatile uint32 POWCTL; //Power Up Control Registers
446 volatile uint32 POWSTAT; //Power Up Status Register
447 volatile uint32 CMDTSTAT; //Command Timing Status Register
448 volatile uint32 CMDTSTATEN; //Command Timing Status Enable Register
449 uint32 reserved1[(0x60-0x54)/4];
450 volatile uint32 MRRCFG0; //MRR Configuration 0 Register
451 volatile uint32 MRRSTAT0; //MRR Status 0 Register
452 volatile uint32 MRRSTAT1; //MRR Status 1 Register
453 uint32 reserved2[(0x7c-0x6c)/4];
454 //Memory Control and Status Registers
455 volatile uint32 MCFG1; //Memory Configuration 1 Register
456 volatile uint32 MCFG; //Memory Configuration Register
457 volatile uint32 PPCFG; //Partially Populated Memories Configuration Register
458 volatile uint32 MSTAT; //Memory Status Register
459 volatile uint32 LPDDR2ZQCFG; //LPDDR2 ZQ Configuration Register
461 //DTU Control and Status Registers
462 volatile uint32 DTUPDES; //DTU Status Register
463 volatile uint32 DTUNA; //DTU Number of Random Addresses Created Register
464 volatile uint32 DTUNE; //DTU Number of Errors Register
465 volatile uint32 DTUPRD0; //DTU Parallel Read 0
466 volatile uint32 DTUPRD1; //DTU Parallel Read 1
467 volatile uint32 DTUPRD2; //DTU Parallel Read 2
468 volatile uint32 DTUPRD3; //DTU Parallel Read 3
469 volatile uint32 DTUAWDT; //DTU Address Width
470 uint32 reserved4[(0xc0-0xb4)/4];
471 //Memory Timing Registers
472 volatile uint32 TOGCNT1U; //Toggle Counter 1U Register
473 volatile uint32 TINIT; //t_init Timing Register
474 volatile uint32 TRSTH; //Reset High Time Register
475 volatile uint32 TOGCNT100N; //Toggle Counter 100N Register
476 volatile uint32 TREFI; //t_refi Timing Register
477 volatile uint32 TMRD; //t_mrd Timing Register
478 volatile uint32 TRFC; //t_rfc Timing Register
479 volatile uint32 TRP; //t_rp Timing Register
480 volatile uint32 TRTW; //t_rtw Timing Register
481 volatile uint32 TAL; //AL Latency Register
482 volatile uint32 TCL; //CL Timing Register
483 volatile uint32 TCWL; //CWL Register
484 volatile uint32 TRAS; //t_ras Timing Register
485 volatile uint32 TRC; //t_rc Timing Register
486 volatile uint32 TRCD; //t_rcd Timing Register
487 volatile uint32 TRRD; //t_rrd Timing Register
488 volatile uint32 TRTP; //t_rtp Timing Register
489 volatile uint32 TWR; //t_wr Timing Register
490 volatile uint32 TWTR; //t_wtr Timing Register
491 volatile uint32 TEXSR; //t_exsr Timing Register
492 volatile uint32 TXP; //t_xp Timing Register
493 volatile uint32 TXPDLL; //t_xpdll Timing Register
494 volatile uint32 TZQCS; //t_zqcs Timing Register
495 volatile uint32 TZQCSI; //t_zqcsi Timing Register
496 volatile uint32 TDQS; //t_dqs Timing Register
497 volatile uint32 TCKSRE; //t_cksre Timing Register
498 volatile uint32 TCKSRX; //t_cksrx Timing Register
499 volatile uint32 TCKE; //t_cke Timing Register
500 volatile uint32 TMOD; //t_mod Timing Register
501 volatile uint32 TRSTL; //Reset Low Timing Register
502 volatile uint32 TZQCL; //t_zqcl Timing Register
503 volatile uint32 TMRR; //t_mrr Timing Register
504 volatile uint32 TCKESR; //t_ckesr Timing Register
505 volatile uint32 TDPD; //t_dpd Timing Register
506 uint32 reserved5[(0x180-0x148)/4];
507 //ECC Configuration, Control, and Status Registers
508 volatile uint32 ECCCFG; //ECC Configuration Register
509 volatile uint32 ECCTST; //ECC Test Register
510 volatile uint32 ECCCLR; //ECC Clear Register
511 volatile uint32 ECCLOG; //ECC Log Register
512 uint32 reserved6[(0x200-0x190)/4];
513 //DTU Control and Status Registers
514 volatile uint32 DTUWACTL; //DTU Write Address Control Register
515 volatile uint32 DTURACTL; //DTU Read Address Control Register
516 volatile uint32 DTUCFG; //DTU Configuration Control Register
517 volatile uint32 DTUECTL; //DTU Execute Control Register
518 volatile uint32 DTUWD0; //DTU Write Data 0
519 volatile uint32 DTUWD1; //DTU Write Data 1
520 volatile uint32 DTUWD2; //DTU Write Data 2
521 volatile uint32 DTUWD3; //DTU Write Data 3
522 volatile uint32 DTUWDM; //DTU Write Data Mask
523 volatile uint32 DTURD0; //DTU Read Data 0
524 volatile uint32 DTURD1; //DTU Read Data 1
525 volatile uint32 DTURD2; //DTU Read Data 2
526 volatile uint32 DTURD3; //DTU Read Data 3
527 volatile uint32 DTULFSRWD; //DTU LFSR Seed for Write Data Generation
528 volatile uint32 DTULFSRRD; //DTU LFSR Seed for Read Data Generation
529 volatile uint32 DTUEAF; //DTU Error Address FIFO
530 //DFI Control Registers
531 volatile uint32 DFITCTRLDELAY; //DFI tctrl_delay Register
532 volatile uint32 DFIODTCFG; //DFI ODT Configuration Register
533 volatile uint32 DFIODTCFG1; //DFI ODT Configuration 1 Register
534 volatile uint32 DFIODTRANKMAP; //DFI ODT Rank Mapping Register
535 //DFI Write Data Registers
536 volatile uint32 DFITPHYWRDATA; //DFI tphy_wrdata Register
537 volatile uint32 DFITPHYWRLAT; //DFI tphy_wrlat Register
538 uint32 reserved7[(0x260-0x258)/4];
539 volatile uint32 DFITRDDATAEN; //DFI trddata_en Register
540 volatile uint32 DFITPHYRDLAT; //DFI tphy_rddata Register
541 uint32 reserved8[(0x270-0x268)/4];
542 //DFI Update Registers
543 volatile uint32 DFITPHYUPDTYPE0; //DFI tphyupd_type0 Register
544 volatile uint32 DFITPHYUPDTYPE1; //DFI tphyupd_type1 Register
545 volatile uint32 DFITPHYUPDTYPE2; //DFI tphyupd_type2 Register
546 volatile uint32 DFITPHYUPDTYPE3; //DFI tphyupd_type3 Register
547 volatile uint32 DFITCTRLUPDMIN; //DFI tctrlupd_min Register
548 volatile uint32 DFITCTRLUPDMAX; //DFI tctrlupd_max Register
549 volatile uint32 DFITCTRLUPDDLY; //DFI tctrlupd_dly Register
551 volatile uint32 DFIUPDCFG; //DFI Update Configuration Register
552 volatile uint32 DFITREFMSKI; //DFI Masked Refresh Interval Register
553 volatile uint32 DFITCTRLUPDI; //DFI tctrlupd_interval Register
554 uint32 reserved10[(0x2ac-0x29c)/4];
555 volatile uint32 DFITRCFG0; //DFI Training Configuration 0 Register
556 volatile uint32 DFITRSTAT0; //DFI Training Status 0 Register
557 volatile uint32 DFITRWRLVLEN; //DFI Training dfi_wrlvl_en Register
558 volatile uint32 DFITRRDLVLEN; //DFI Training dfi_rdlvl_en Register
559 volatile uint32 DFITRRDLVLGATEEN; //DFI Training dfi_rdlvl_gate_en Register
560 //DFI Status Registers
561 volatile uint32 DFISTSTAT0; //DFI Status Status 0 Register
562 volatile uint32 DFISTCFG0; //DFI Status Configuration 0 Register
563 volatile uint32 DFISTCFG1; //DFI Status configuration 1 Register
565 volatile uint32 DFITDRAMCLKEN; //DFI tdram_clk_enalbe Register
566 volatile uint32 DFITDRAMCLKDIS; //DFI tdram_clk_disalbe Register
567 volatile uint32 DFISTCFG2; //DFI Status configuration 2 Register
568 volatile uint32 DFISTPARCLR; //DFI Status Parity Clear Register
569 volatile uint32 DFISTPARLOG; //DFI Status Parity Log Register
570 uint32 reserved12[(0x2f0-0x2e4)/4];
571 //DFI Low Power Registers
572 volatile uint32 DFILPCFG0; //DFI Low Power Configuration 0 Register
573 uint32 reserved13[(0x300-0x2f4)/4];
574 //DFI Training 2 Registers
575 volatile uint32 DFITRWRLVLRESP0; //DFI Training dif_wrlvl_resp Status 0 Register
576 volatile uint32 DFITRWRLVLRESP1; //DFI Training dif_wrlvl_resp Status 1 Register
577 volatile uint32 DFITRWRLVLRESP2; //DFI Training dif_wrlvl_resp Status 2 Register
578 volatile uint32 DFITRRDLVLRESP0; //DFI Training dif_rdlvl_resp Status 0 Register
579 volatile uint32 DFITRRDLVLRESP1; //DFI Training dif_rdlvl_resp Status 1 Register
580 volatile uint32 DFITRRDLVLRESP2; //DFI Training dif_rdlvl_resp Status 2 Register
581 volatile uint32 DFITRWRLVLDELAY0; //DFI Training dif_wrlvl_delay Configuration 0 Register
582 volatile uint32 DFITRWRLVLDELAY1; //DFI Training dif_wrlvl_delay Configuration 1 Register
583 volatile uint32 DFITRWRLVLDELAY2; //DFI Training dif_wrlvl_delay Configuration 2 Register
584 volatile uint32 DFITRRDLVLDELAY0; //DFI Training dif_rdlvl_delay Configuration 0 Register
585 volatile uint32 DFITRRDLVLDELAY1; //DFI Training dif_rdlvl_delay Configuration 1 Register
586 volatile uint32 DFITRRDLVLDELAY2; //DFI Training dif_rdlvl_delay Configuration 2 Register
587 volatile uint32 DFITRRDLVLGATEDELAY0; //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
588 volatile uint32 DFITRRDLVLGATEDELAY1; //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
589 volatile uint32 DFITRRDLVLGATEDELAY2; //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
590 volatile uint32 DFITRCMD; //DFI Training Command Register
591 uint32 reserved14[(0x3f8-0x340)/4];
592 //IP Status Registers
593 volatile uint32 IPVR; //IP Version Register
594 volatile uint32 IPTR; //IP Type Register
595 }DDR_REG_T, *pDDR_REG_T;
597 #define pDDR_Reg ((pDDR_REG_T)SDRAMC_BASE_ADDR)
601 #define DLLSRST (1<<1)
602 #define DLLLOCK (1<<2)
604 #define ITMSRST (1<<4)
605 #define DRAMRST (1<<5)
606 #define DRAMINIT (1<<6)
608 #define EYETRN (1<<8)
610 #define DLLBYP (1<<17)
611 #define CTLDINIT (1<<18)
612 #define CLRSR (1<<28)
613 #define LOCKBYP (1<<29)
614 #define ZCALBYP (1<<30)
615 #define INITBYP (1u<<31)
618 #define DFTLMT(n) ((n)<<3)
619 #define DFTCMP(n) ((n)<<2)
620 #define DQSCFG(n) ((n)<<1)
621 #define ITMDMD(n) ((n)<<0)
622 #define RANKEN(n) ((n)<<18)
626 #define DLDONE (1<<1)
627 #define ZCDONE (1<<2)
628 #define DIDONE (1<<3)
629 #define DTDONE (1<<4)
631 #define DTIERR (1<<6)
632 #define DFTERR (1<<7)
636 #define tITMSRST(n) ((n)<<18)
637 #define tDLLLOCK(n) ((n)<<6)
638 #define tDLLSRST(n) ((n)<<0)
641 #define tDINIT1(n) ((n)<<19)
642 #define tDINIT0(n) ((n)<<0)
645 #define tDINIT3(n) ((n)<<17)
646 #define tDINIT2(n) ((n)<<0)
649 #define DQSGE(n) ((n)<<8)
650 #define DQSGX(n) ((n)<<5)
652 typedef union DCR_Tag
658 unsigned DDR8BNK : 1;
661 unsigned DDRTYPE : 2;
662 unsigned reserved10_26 : 17;
672 typedef volatile struct DATX8_REG_Tag
674 volatile uint32 DXGCR; //DATX8 General Configuration Register
675 volatile uint32 DXGSR[2]; //DATX8 General Status Register
676 volatile uint32 DXDLLCR; //DATX8 DLL Control Register
677 volatile uint32 DXDQTR; //DATX8 DQ Timing Register
678 volatile uint32 DXDQSTR; //DATX8 DQS Timing Register
679 uint32 reserved[0x80-0x76];
682 /* DDR PHY register struct */
683 typedef volatile struct DDRPHY_REG_Tag
685 volatile uint32 RIDR; //Revision Identification Register
686 volatile uint32 PIR; //PHY Initialization Register
687 volatile uint32 PGCR; //PHY General Configuration Register
688 volatile uint32 PGSR; //PHY General Status Register
689 volatile uint32 DLLGCR; //DLL General Control Register
690 volatile uint32 ACDLLCR; //AC DLL Control Register
691 volatile uint32 PTR[3]; //PHY Timing Registers 0-2
692 volatile uint32 ACIOCR; //AC I/O Configuration Register
693 volatile uint32 DXCCR; //DATX8 Common Configuration Register
694 volatile uint32 DSGCR; //DDR System General Configuration Register
695 DCR_T DCR; //DRAM Configuration Register
696 volatile uint32 DTPR[3]; //DRAM Timing Parameters Register 0-2
697 volatile uint32 MR[4]; //Mode Register 0-3
698 volatile uint32 ODTCR; //ODT Configuration Register
699 volatile uint32 DTAR; //Data Training Address Register
700 volatile uint32 DTDR[2]; //Data Training Data Register 0-1
702 uint32 reserved1[0x30-0x18];
703 uint32 DCU[0x38-0x30];
704 uint32 reserved2[0x40-0x38];
705 uint32 BIST[0x51-0x40];
706 uint32 reserved3[0x60-0x51];
708 volatile uint32 ZQ0CR[2]; //ZQ 0 Impedance Control Register 0-1
709 volatile uint32 ZQ0SR[2]; //ZQ 0 Impedance Status Register 0-1
710 volatile uint32 ZQ1CR[2]; //ZQ 1 Impedance Control Register 0-1
711 volatile uint32 ZQ1SR[2]; //ZQ 1 Impedance Status Register 0-1
712 volatile uint32 ZQ2CR[2]; //ZQ 2 Impedance Control Register 0-1
713 volatile uint32 ZQ2SR[2]; //ZQ 2 Impedance Status Register 0-1
714 volatile uint32 ZQ3CR[2]; //ZQ 3 Impedance Control Register 0-1
715 volatile uint32 ZQ3SR[2]; //ZQ 3 Impedance Status Register 0-1
717 DATX8_REG_T DATX8[9]; //DATX8 Register
718 }DDRPHY_REG_T, *pDDRPHY_REG_T;
720 #define pPHY_Reg ((pDDRPHY_REG_T)DDR_PUBL_BASE)
722 typedef enum DRAM_TYPE_Tag
733 typedef struct PCTRL_TIMING_Tag
736 //Memory Timing Registers
737 uint32 togcnt1u; //Toggle Counter 1U Register
738 uint32 tinit; //t_init Timing Register
739 uint32 trsth; //Reset High Time Register
740 uint32 togcnt100n; //Toggle Counter 100N Register
741 uint32 trefi; //t_refi Timing Register
742 uint32 tmrd; //t_mrd Timing Register
743 uint32 trfc; //t_rfc Timing Register
744 uint32 trp; //t_rp Timing Register
745 uint32 trtw; //t_rtw Timing Register
746 uint32 tal; //AL Latency Register
747 uint32 tcl; //CL Timing Register
748 uint32 tcwl; //CWL Register
749 uint32 tras; //t_ras Timing Register
750 uint32 trc; //t_rc Timing Register
751 uint32 trcd; //t_rcd Timing Register
752 uint32 trrd; //t_rrd Timing Register
753 uint32 trtp; //t_rtp Timing Register
754 uint32 twr; //t_wr Timing Register
755 uint32 twtr; //t_wtr Timing Register
756 uint32 texsr; //t_exsr Timing Register
757 uint32 txp; //t_xp Timing Register
758 uint32 txpdll; //t_xpdll Timing Register
759 uint32 tzqcs; //t_zqcs Timing Register
760 uint32 tzqcsi; //t_zqcsi Timing Register
761 uint32 tdqs; //t_dqs Timing Register
762 uint32 tcksre; //t_cksre Timing Register
763 uint32 tcksrx; //t_cksrx Timing Register
764 uint32 tcke; //t_cke Timing Register
765 uint32 tmod; //t_mod Timing Register
766 uint32 trstl; //Reset Low Timing Register
767 uint32 tzqcl; //t_zqcl Timing Register
768 uint32 tmrr; //t_mrr Timing Register
769 uint32 tckesr; //t_ckesr Timing Register
770 uint32 tdpd; //t_dpd Timing Register
773 typedef union DTPR_0_Tag
790 typedef union DTPR_1_Tag
800 unsigned reserved12_15 : 4;
803 unsigned tDQSCKmax : 3;
804 unsigned reserved30_31 : 2;
808 typedef union DTPR_2_Tag
817 unsigned reserved29_31 : 3;
821 typedef struct PHY_TIMING_Tag
826 uint32 mr[4]; //LPDDR2 no MR0, mr[2] is mDDR MR1
829 typedef union NOC_TIMING_Tag
834 unsigned ActToAct : 6;
835 unsigned RdToMiss : 6;
836 unsigned WrToMiss : 6;
837 unsigned BurstLen : 3;
840 unsigned BwRatio : 1;
844 typedef struct PCTL_REG_Tag
850 PCTL_TIMING_T pctl_timing;
851 //DFI Control Registers
852 uint32 DFITCTRLDELAY;
855 uint32 DFIODTRANKMAP;
856 //DFI Write Data Registers
857 uint32 DFITPHYWRDATA;
859 //DFI Read Data Registers
862 //DFI Update Registers
863 uint32 DFITPHYUPDTYPE0;
864 uint32 DFITPHYUPDTYPE1;
865 uint32 DFITPHYUPDTYPE2;
866 uint32 DFITPHYUPDTYPE3;
867 uint32 DFITCTRLUPDMIN;
868 uint32 DFITCTRLUPDMAX;
869 uint32 DFITCTRLUPDDLY;
873 //DFI Status Registers
876 uint32 DFITDRAMCLKEN;
877 uint32 DFITDRAMCLKDIS;
879 //DFI Low Power Register
883 typedef struct PUBL_REG_Tag
894 PHY_TIMING_T phy_timing;
921 typedef struct BACKUP_REG_Tag
926 NOC_TIMING_T noc_timing;
931 __sramdata BACKUP_REG_T ddr_reg;
933 uint8_t ddr_cfg_2_rbc[] =
935 /****************************/
936 // [7:6] bank(n:n bit bank)
938 // [3:2] bank(n:n bit bank)
940 /****************************/
941 //bank, row, bank, col
942 ((3<<6)|(2<<4)|(0<<2)|2), // 0 bank ahead
943 ((0<<6)|(2<<4)|(3<<2)|1), // 1
944 ((0<<6)|(1<<4)|(3<<2)|1), // 2
945 ((0<<6)|(0<<4)|(3<<2)|1), // 3
946 ((0<<6)|(2<<4)|(3<<2)|2), // 4
947 ((0<<6)|(1<<4)|(3<<2)|2), // 5
948 ((0<<6)|(0<<4)|(3<<2)|2), // 6
949 ((0<<6)|(1<<4)|(3<<2)|0), // 7
950 ((0<<6)|(0<<4)|(3<<2)|0), // 8
951 ((1<<6)|(2<<4)|(2<<2)|2), // 9
952 ((1<<6)|(1<<4)|(2<<2)|2), // 10
953 ((1<<6)|(2<<4)|(2<<2)|1), // 11
954 ((1<<6)|(1<<4)|(2<<2)|1), // 12
955 ((1<<6)|(2<<4)|(2<<2)|0), // 13
956 ((1<<6)|(1<<4)|(2<<2)|0), // 14
957 ((3<<6)|(2<<4)|(0<<2)|1), // 15 bank ahead
960 __attribute__((aligned(4096))) uint32_t ddr_data_training_buf[32];
962 uint8_t __sramdata ddr3_cl_cwl[22][4]={
963 /* 0~330 330~400 400~533 speed
964 * tCK >3 2.5~3 1.875~2.5 1.5~1.875
965 * cl<<4, cwl cl<<4, cwl cl<<4, cwl */
966 {((5<<4)|5), ((5<<4)|5), 0 , 0}, //DDR3_800D
967 {((5<<4)|5), ((6<<4)|5), 0 , 0}, //DDR3_800E
969 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), 0}, //DDR3_1066E
970 {((5<<4)|5), ((6<<4)|5), ((7<<4)|6), 0}, //DDR3_1066F
971 {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), 0}, //DDR3_1066G
973 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7)}, //DDR3_1333F
974 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((8<<4)|7)}, //DDR3_1333G
975 {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((9<<4)|7)}, //DDR3_1333H
976 {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7)}, //DDR3_1333J
978 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7)}, //DDR3_1600G
979 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7)}, //DDR3_1600H
980 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_1600J
981 {((5<<4)|5), ((6<<4)|5), ((7<<4)|6), ((10<<4)|7)}, //DDR3_1600K
983 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7)}, //DDR3_1866J
984 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((8<<4)|7)}, //DDR3_1866K
985 {((6<<4)|5), ((6<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_1866L
986 {((6<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7)}, //DDR3_1866M
988 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7)}, //DDR3_2133K
989 {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7)}, //DDR3_2133L
990 {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_2133M
991 {((6<<4)|5), ((6<<4)|5), ((7<<4)|6), ((9<<4)|7)}, //DDR3_2133N
993 {((6<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7)} //DDR3_DEFAULT
996 uint16_t __sramdata ddr3_tRC_tFAW[22]={
998 ((50<<8)|50), //DDR3_800D
999 ((53<<8)|50), //DDR3_800E
1001 ((49<<8)|50), //DDR3_1066E
1002 ((51<<8)|50), //DDR3_1066F
1003 ((53<<8)|50), //DDR3_1066G
1005 ((47<<8)|45), //DDR3_1333F
1006 ((48<<8)|45), //DDR3_1333G
1007 ((50<<8)|45), //DDR3_1333H
1008 ((51<<8)|45), //DDR3_1333J
1010 ((45<<8)|40), //DDR3_1600G
1011 ((47<<8)|40), //DDR3_1600H
1012 ((48<<8)|40), //DDR3_1600J
1013 ((49<<8)|40), //DDR3_1600K
1015 ((45<<8)|35), //DDR3_1866J
1016 ((46<<8)|35), //DDR3_1866K
1017 ((47<<8)|35), //DDR3_1866L
1018 ((48<<8)|35), //DDR3_1866M
1020 ((44<<8)|35), //DDR3_2133K
1021 ((45<<8)|35), //DDR3_2133L
1022 ((46<<8)|35), //DDR3_2133M
1023 ((47<<8)|35), //DDR3_2133N
1025 ((53<<8)|50) //DDR3_DEFAULT
1028 __sramdata uint32_t mem_type; // 0:LPDDR, 1:DDR, 2:DDR2, 3:DDR3, 4:LPDDR2
1029 static __sramdata uint32_t ddr_speed_bin; // used for ddr3 only
1030 static __sramdata uint32_t ddr_capability_per_die; // one chip cs capability
1031 static __sramdata uint32_t ddr_freq;
1032 static __sramdata uint32_t ddr_sr_idle;
1034 /****************************************************************************
1035 Internal sram us delay function
1036 Cpu highest frequency is 1.6 GHz
1038 1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
1039 *****************************************************************************/
1040 static __sramdata volatile uint32_t loops_per_us;
1042 #define LPJ_100MHZ 999456UL
1044 /*static*/ void __sramlocalfunc ddr_delayus(uint32_t us)
1048 unsigned int i = (loops_per_us*us);
1051 asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
1055 __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
1059 for(i=0; i<words; i++)
1065 uint32 ddr_get_row(void)
1070 i = *(volatile uint32*)SysSrv_DdrConf;
1071 row = 13+((ddr_cfg_2_rbc[i]>>4)&0x3);
1072 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
1073 if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (1<<1))
1078 if(pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
1086 uint32 ddr_get_bank(void)
1091 i = *(volatile uint32*)SysSrv_DdrConf;
1092 bank = ((ddr_cfg_2_rbc[i]>>6)&0x3) + ((ddr_cfg_2_rbc[i]>>2)&0x3);
1093 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
1094 if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (1<<2))
1099 if(pGRF_Reg->GRF_SOC_CON[2] & (1<<2))
1107 uint32 ddr_get_col(void)
1112 i = *(volatile uint32*)SysSrv_DdrConf;
1113 col = 9+(ddr_cfg_2_rbc[i]&0x3);
1114 if(pDDR_Reg->PPCFG & 1)
1121 uint32 ddr_get_bw(void)
1125 if(pDDR_Reg->PPCFG & 1)
1136 uint32 ddr_get_cs(void)
1140 switch((pPHY_Reg->PGCR>>18) & 0xF)
1157 uint32_t ddr_get_datatraing_addr(void)
1167 // caculate aglined physical address
1168 addr = __pa((unsigned long)ddr_data_training_buf);
1171 addr += (64-(addr&0x3F));
1174 // find out col£¬row£¬bank
1175 row = ddr_get_row();
1176 bank = ddr_get_bank();
1177 col = ddr_get_col();
1179 // according different address mapping, caculate DTAR register value
1180 i = (*(volatile uint32*)SysSrv_DdrConf);
1181 value |= (addr>>bw) & ((0x1<<col)-1); // col
1184 value |= ((addr>>(bw+col+((ddr_cfg_2_rbc[i]>>2)&0x3))) & 0x7FFF) << 12; // row
1185 value |= (((addr>>(bw+col+bank+15))&0x1)<<15)<<12;
1186 row = 15; //use for bank
1190 value |= ((addr>>(bw+col+((ddr_cfg_2_rbc[i]>>2)&0x3))) & ((0x1<<row)-1)) << 12; // row
1192 if(((ddr_cfg_2_rbc[i]>>6)&0x3)==1)
1194 value |= (((addr>>(bw+col)) & 0x3) << 28)
1195 | (((addr>>(bw+col+2+row)) & (bank-2)) << 30); // bank
1197 else if(((ddr_cfg_2_rbc[i]>>6)&0x3)==3)
1199 value |= (((addr>>(bw+col+row)) & ((0x1<<bank)-1)) << 28); // bank
1203 value |= (((addr>>(bw+col)) & 0x7) << 28); // bank
1209 __sramlocalfunc void ddr_reset_dll(void)
1211 pPHY_Reg->ACDLLCR &= ~0x40000000;
1212 pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
1213 pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
1214 if(!(pDDR_Reg->PPCFG & 1))
1216 pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
1217 pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
1220 pPHY_Reg->ACDLLCR |= 0x40000000;
1221 pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
1222 pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
1223 if(!(pDDR_Reg->PPCFG & 1))
1225 pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
1226 pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
1231 __sramfunc void ddr_move_to_Lowpower_state(void)
1233 volatile uint32 value;
1237 value = pDDR_Reg->STAT.b.ctl_stat;
1238 if(value == Low_power)
1245 pDDR_Reg->SCTL = CFG_STATE;
1247 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1249 pDDR_Reg->SCTL = GO_STATE;
1251 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1253 pDDR_Reg->SCTL = SLEEP_STATE;
1255 while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
1257 default: //Transitional state
1263 __sramfunc void ddr_move_to_Access_state(void)
1265 volatile uint32 value;
1267 //set auto self-refresh idle
1268 pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)|ddr_sr_idle | (1<<31);
1273 value = pDDR_Reg->STAT.b.ctl_stat;
1274 if((value == Access)
1275 || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
1282 pDDR_Reg->SCTL = WAKEUP_STATE;
1284 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1285 while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
1288 pDDR_Reg->SCTL = CFG_STATE;
1290 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1292 pDDR_Reg->SCTL = GO_STATE;
1294 while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
1295 || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
1297 default: //Transitional state
1301 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
1302 pGRF_Reg_RK3066B->GRF_SOC_CON[2] = (1<<16 | 0);//de_hw_wakeup :enable auto sr if sr_idle != 0
1304 pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 0);//de_hw_wakeup :enable auto sr if sr_idle != 0
1309 __sramfunc void ddr_move_to_Config_state(void)
1311 volatile uint32 value;
1312 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
1313 pGRF_Reg_RK3066B->GRF_SOC_CON[2] = (1<<16 | 1); //hw_wakeup :disable auto sr
1315 pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 1); //hw_wakeup :disable auto sr
1321 value = pDDR_Reg->STAT.b.ctl_stat;
1329 pDDR_Reg->SCTL = WAKEUP_STATE;
1331 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
1332 while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
1335 pDDR_Reg->SCTL = CFG_STATE;
1337 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
1339 default: //Transitional state
1345 //arg°üÀ¨bank_addrºÍcmd_addr
1346 void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
1348 pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
1350 while(pDDR_Reg->MCMD & start_cmd);
1353 //¶ÔtypeÀàÐ͵ÄDDRµÄ¼¸¸öcs½øÐÐDTT
1356 uint32_t __sramlocalfunc ddr_data_training(void)
1360 // disable auto refresh
1361 value = pDDR_Reg->TREFI;
1362 pDDR_Reg->TREFI = 0;
1364 if(mem_type != LPDDR2)
1367 pPHY_Reg->PGCR |= (1<<1);
1369 // clear DTDONE status
1370 pPHY_Reg->PIR |= CLRSR;
1371 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
1373 pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
1375 // wait echo byte DTDONE
1376 while((pPHY_Reg->DATX8[0].DXGSR[0] & cs) != cs);
1377 while((pPHY_Reg->DATX8[1].DXGSR[0] & cs) != cs);
1378 if(!(pDDR_Reg->PPCFG & 1))
1380 while((pPHY_Reg->DATX8[2].DXGSR[0] & cs) != cs);
1381 while((pPHY_Reg->DATX8[3].DXGSR[0] & cs) != cs);
1383 // send some auto refresh to complement the lost while DTT£¬//²âµ½1¸öCSµÄDTT×ʱ¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
1386 ddr_send_command(cs, REF_cmd, 0);
1387 ddr_send_command(cs, REF_cmd, 0);
1388 ddr_send_command(cs, REF_cmd, 0);
1389 ddr_send_command(cs, REF_cmd, 0);
1393 ddr_send_command(cs, REF_cmd, 0);
1394 ddr_send_command(cs, REF_cmd, 0);
1396 if(mem_type != LPDDR2)
1399 pPHY_Reg->PGCR &= ~(1<<1);
1401 // resume auto refresh
1402 pDDR_Reg->TREFI = value;
1404 if(pPHY_Reg->PGSR & DTERR)
1414 void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
1418 pPHY_Reg->DLLGCR &= ~(1<<23);
1419 pPHY_Reg->ACDLLCR |= 0x80000000;
1420 pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
1421 pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
1422 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
1423 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
1424 pPHY_Reg->PIR |= DLLBYP;
1428 pPHY_Reg->DLLGCR |= (1<<23);
1429 pPHY_Reg->ACDLLCR |= 0x80000000;
1430 pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
1431 pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
1432 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
1433 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
1434 pPHY_Reg->PIR |= DLLBYP;
1438 pPHY_Reg->DLLGCR &= ~(1<<23);
1439 pPHY_Reg->ACDLLCR &= ~0x80000000;
1440 pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
1441 pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
1442 if(!(pDDR_Reg->PPCFG & 1))
1444 pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
1445 pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
1447 pPHY_Reg->PIR &= ~DLLBYP;
1451 static __sramdata uint32_t clkr;
1452 static __sramdata uint32_t clkf;
1453 static __sramdata uint32_t clkod;
1455 static __sramdata uint32_t dpllvaluel=0,gpllvaluel=0;
1456 static __sramdata uint32_t ddr_select_gpll_div=0; // 0-Disable, 1-1:1, 2-2:1, 4-4:1
1458 static __sramdata bool ddr_soc_is_rk3188_plus=false;
1460 typedef enum PLL_ID_Tag
1469 uint32_t __sramlocalfunc ddr_get_pll_freq(PLL_ID pll_id) //APLL-1;CPLL-2;DPLL-3;GPLL-4
1473 // freq = (Fin/NR)*NF/OD
1474 if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1) // DPLL Normal mode
1475 ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0xffff)+1) // NF = 2*(CLKF+1)
1476 /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1) // NR = CLKR+1
1477 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0x3F)+1)); // OD = 2^CLKOD
1484 /*****************************************
1485 NR NO NF Fout freq Step finally use
1486 1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
1487 1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
1488 1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
1489 1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
1490 1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
1491 ******************************************/
1492 uint32_t __sramlocalfunc ddr_set_pll_3066(uint32_t nMHz, uint32_t set)
1496 uint32_t pll_id=1; //DPLL
1497 //NOÒ»¶¨ÒªÅ¼Êý,NR¾¡Á¿Ð¡£¬jitter¾Í»áС
1511 else if(nMHz <= 200)
1515 else if(nMHz <= 300)
1519 else if(nMHz <= 600)
1528 clkf=(nMHz*clkr*clkod)/24;
1529 ret = (24*clkf)/(clkr*clkod);
1533 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
1535 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET;
1536 pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR(clkr) | NO(clkod);
1537 pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF(clkf);
1538 pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
1540 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET;
1545 if (pGRF_Reg->GRF_SOC_STATUS0 & (0x1<<4))
1549 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1550 | (0x0<<8) //clk_ddr_src = DDR PLL
1551 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1553 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
1561 /*****************************************
1563 NR NO NF Fout freq Step finally use
1564 1 14 46 - 91 78MHz - 157MHz 1.7MHz 78MHz<= 150MHz
1565 1 8 46 - 91 137MHz - 275MHz 3MHz 150MHz<= 200MHz
1566 1 6 46 - 91 183MHz - 366MHz 4MHz 200MHz<= 300MHz
1567 1 4 46 - 91 275MHz - 550MHz 6MHz 300MHz<= 550MHz
1568 1 2 46 - 91 550MHz - 1100MHz 12MHz 550MHz<= 1100MHz
1569 1 1 46 - 91 1100MHz - 2200MHz 24MHz 1100MHz<= 2200MHz
1570 ******************************************/
1571 uint32_t __sramlocalfunc ddr_set_pll_rk3066b(uint32_t nMHz, uint32_t set)
1575 uint32_t pll_id=1; //DPLL
1585 dpllvaluel = ddr_get_pll_freq(DPLL);
1586 gpllvaluel = ddr_get_pll_freq(GPLL);
1588 if(ddr_select_gpll_div > 0)
1590 if(ddr_select_gpll_div == 4)
1592 else if(ddr_select_gpll_div == 2)
1603 else if(nMHz <= 200)
1607 else if(nMHz <= 300)
1611 else if(nMHz <= 550)
1615 else if(nMHz <= 1100)
1624 clkf=(nMHz*clkr*clkod)/24;
1625 ret = (24*clkf)/(clkr*clkod);
1631 if(ddr_select_gpll_div > 0)
1633 if(ddr_select_gpll_div == 4)
1635 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1636 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1637 | (0x1<<8) //clk_ddr_src = G PLL
1638 | 2; //clk_ddr_src:clk_ddrphy = 4:1
1641 if(ddr_select_gpll_div == 2)
1643 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1644 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1645 | (0x1<<8) //clk_ddr_src = G PLL
1646 | 1; //clk_ddr_src:clk_ddrphy = 2:1
1651 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1652 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1653 | (0x1<<8) //clk_ddr_src = G PLL
1654 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1658 else if((nMHz==dpllvaluel) && (set == 1))
1660 // ddr_pll_clk: clk_ddr=1:1
1661 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1662 | (0x0<<8) //clk_ddr_src = DDR PLL
1663 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1668 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
1671 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET_RK3066B;
1673 pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR_RK3066B(clkr) | NO_RK3066B(clkod);
1674 pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF_RK3066B(clkf);
1675 // pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
1677 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET_RK3066B;
1682 if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (0x1<<5))
1688 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1689 | (0x0<<8) //clk_ddr_src = DDR PLL
1690 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1692 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
1701 /*****************************************
1702 NR NO NF Fout freq Step finally use
1703 1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
1704 1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
1705 1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
1706 1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
1707 1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
1708 ******************************************/
1709 uint32_t __sramlocalfunc ddr_set_pll_rk3188_plus(uint32_t nMHz, uint32_t set)
1713 uint32_t pll_id=1; //DPLL
1723 dpllvaluel = ddr_get_pll_freq(DPLL);
1724 gpllvaluel = ddr_get_pll_freq(GPLL);
1726 if(ddr_select_gpll_div > 0)
1728 if(ddr_select_gpll_div == 4)
1730 else if(ddr_select_gpll_div == 2)
1741 else if(nMHz <= 200)
1745 else if(nMHz <= 300)
1749 else if(nMHz <= 600)
1758 clkf=(nMHz*clkr*clkod)/24;
1759 ret = (24*clkf)/(clkr*clkod);
1765 if(ddr_select_gpll_div > 0)
1767 if(ddr_select_gpll_div == 4)
1769 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1770 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1771 | (0x1<<8) //clk_ddr_src = G PLL
1772 | 2; //clk_ddr_src:clk_ddrphy = 4:1
1775 if(ddr_select_gpll_div == 2)
1777 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1778 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1779 | (0x1<<8) //clk_ddr_src = G PLL
1780 | 1; //clk_ddr_src:clk_ddrphy = 2:1
1785 pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000;
1786 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1787 | (0x1<<8) //clk_ddr_src = G PLL
1788 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1792 else if((nMHz==dpllvaluel) && (set == 1))
1794 // ddr_pll_clk: clk_ddr=1:1
1795 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1796 | (0x0<<8) //clk_ddr_src = DDR PLL
1797 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1802 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
1805 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_RESET;
1807 pCRU_Reg->CRU_PLL_CON[pll_id][0] = NR(clkr) | NO(clkod);
1808 pCRU_Reg->CRU_PLL_CON[pll_id][1] = NF(clkf);
1809 pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
1811 pCRU_Reg->CRU_PLL_CON[pll_id][3] = PLL_DE_RESET;
1816 if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (0x1<<5))
1822 pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3 | (0x1<<8))<<16)
1823 | (0x0<<8) //clk_ddr_src = DDR PLL
1824 | 0; //clk_ddr_src:clk_ddrphy = 1:1
1826 pCRU_Reg->CRU_MODE_CON = (0x3<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
1835 uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
1837 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
1838 if(ddr_soc_is_rk3188_plus == true)
1839 return ddr_set_pll_rk3188_plus(nMHz,set);
1841 return ddr_set_pll_rk3066b(nMHz,set);
1843 return ddr_set_pll_3066(nMHz,set);
1847 uint32_t ddr_get_parameter(uint32_t nMHz)
1855 PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
1856 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
1857 NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
1859 p_pctl_timing->togcnt1u = nMHz;
1860 p_pctl_timing->togcnt100n = nMHz/10;
1861 p_pctl_timing->tinit = 200;
1862 p_pctl_timing->trsth = 500;
1864 if(mem_type == DDR3)
1866 if(ddr_speed_bin > DDR3_DEFAULT){
1871 #define DDR3_tREFI_7_8_us (78)
1872 #define DDR3_tMRD (4)
1873 #define DDR3_tRFC_512Mb (90)
1874 #define DDR3_tRFC_1Gb (110)
1875 #define DDR3_tRFC_2Gb (160)
1876 #define DDR3_tRFC_4Gb (300)
1877 #define DDR3_tRFC_8Gb (350)
1878 #define DDR3_tRTW (2) //register min valid value
1879 #define DDR3_tRAS (37)
1880 #define DDR3_tRRD (10)
1881 #define DDR3_tRTP (7)
1882 #define DDR3_tWR (15)
1883 #define DDR3_tWTR (7)
1884 #define DDR3_tXP (7)
1885 #define DDR3_tXPDLL (24)
1886 #define DDR3_tZQCS (80)
1887 #define DDR3_tZQCSI (10000)
1888 #define DDR3_tDQS (1)
1889 #define DDR3_tCKSRE (10)
1890 #define DDR3_tCKE_400MHz (7)
1891 #define DDR3_tCKE_533MHz (6)
1892 #define DDR3_tMOD (15)
1893 #define DDR3_tRSTL (100)
1894 #define DDR3_tZQCL (320)
1895 #define DDR3_tDLLK (512)
1915 cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4)&0xf;
1916 cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
1919 if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
1921 p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
1925 p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
1927 p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
1928 p_publ_timing->mr[3] = 0;
1929 /**************************************************
1931 **************************************************/
1933 * tREFI, average periodic refresh interval, 7.8us
1935 p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
1939 p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
1940 p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
1942 * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
1944 if(ddr_capability_per_die <= 0x4000000) // 512Mb 90ns
1946 tmp = DDR3_tRFC_512Mb;
1948 else if(ddr_capability_per_die <= 0x8000000) // 1Gb 110ns
1950 tmp = DDR3_tRFC_1Gb;
1952 else if(ddr_capability_per_die <= 0x10000000) // 2Gb 160ns
1954 tmp = DDR3_tRFC_2Gb;
1956 else if(ddr_capability_per_die <= 0x20000000) // 4Gb 300ns
1958 tmp = DDR3_tRFC_4Gb;
1962 tmp = DDR3_tRFC_8Gb;
1964 p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
1965 p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000)&0xFF;
1967 * tXSR, =tDLLK=512 tCK
1969 p_pctl_timing->texsr = DDR3_tDLLK;
1970 p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
1974 p_pctl_timing->trp = cl;
1975 p_publ_timing->dtpr0.b.tRP = cl;
1977 * WrToMiss=WL*tCK + tWR + tRP + tRCD
1979 p_noc_timing->b.WrToMiss = ((cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
1983 p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
1984 p_noc_timing->b.ActToAct = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
1985 p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0xF;
1987 p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
1988 p_publ_timing->dtpr1.b.tRTW = 0;
1989 p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
1990 p_pctl_timing->tal = al;
1991 p_pctl_timing->tcl = cl;
1992 p_pctl_timing->tcwl = cwl;
1994 * tRAS, 37.5ns(400MHz) 37.5ns(533MHz)
1996 p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
1997 p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x1F;
2001 p_pctl_timing->trcd = cl;
2002 p_publ_timing->dtpr0.b.tRCD = cl;
2004 * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
2005 * max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
2006 * max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
2009 tmp = ((DDR3_tRRD*nMHz+999)/1000);
2014 p_pctl_timing->trrd = (tmp&0xF);
2015 p_publ_timing->dtpr0.b.tRRD = tmp&0xF;
2017 * tRTP, max(4 tCK,7.5ns)
2019 tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
2024 p_pctl_timing->trtp = tmp&0xF;
2025 p_publ_timing->dtpr0.b.tRTP = tmp;
2027 * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2029 p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
2033 tmp = ((DDR3_tWR*nMHz+999)/1000);
2034 p_pctl_timing->twr = tmp&0x1F;
2039 bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
2040 p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
2043 * tWTR, max(4 tCK,7.5ns)
2045 tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
2050 p_pctl_timing->twtr = tmp&0xF;
2051 p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
2052 p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
2054 * tXP, max(3 tCK, 7.5ns)(<933MHz)
2056 tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
2061 p_pctl_timing->txp = tmp&0x7;
2062 p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
2064 * tXPDLL, max(10 tCK,24ns)
2066 tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
2071 p_pctl_timing->txpdll = tmp & 0x3F;
2073 * tZQCS, max(64 tCK, 80ns)
2075 tmp = ((DDR3_tZQCS*nMHz+999)/1000);
2080 p_pctl_timing->tzqcs = tmp&0x7F;
2084 p_pctl_timing->tzqcsi = DDR3_tZQCSI;
2088 p_pctl_timing->tdqs = DDR3_tDQS;
2090 * tCKSRE, max(5 tCK, 10ns)
2092 tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
2097 p_pctl_timing->tcksre = tmp & 0x1F;
2099 * tCKSRX, max(5 tCK, 10ns)
2101 p_pctl_timing->tcksrx = tmp & 0x1F;
2103 * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
2107 tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
2111 tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
2117 p_pctl_timing->tcke = tmp & 0x7;
2118 p_publ_timing->dtpr2.b.tCKE = tmp;
2120 * tCKESR, =tCKE + 1tCK
2122 p_pctl_timing->tckesr = (tmp+1)&0xF;
2124 * tMOD, max(12 tCK,15ns)
2126 tmp = ((DDR3_tMOD*nMHz+999)/1000);
2131 p_pctl_timing->tmod = tmp&0x1F;
2132 p_publ_timing->dtpr1.b.tMOD = tmp;
2136 p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
2138 * tZQCL, max(256 tCK, 320ns)
2140 tmp = ((DDR3_tZQCL*nMHz+999)/1000);
2145 p_pctl_timing->tzqcl = tmp&0x3FF;
2149 p_pctl_timing->tmrr = 0;
2153 p_pctl_timing->tdpd = 0;
2155 /**************************************************
2157 **************************************************/
2159 * tCCD, BL/2 for DDR2 and 4 for DDR3
2161 p_publ_timing->dtpr0.b.tCCD = 0;
2165 p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2167 * tRTODT, 0:ODT may be turned on immediately after read post-amble
2168 * 1:ODT may not be turned on until one clock after the read post-amble
2170 p_publ_timing->dtpr1.b.tRTODT = 1;
2172 * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page) 50ns(533MHz 2KB page)
2174 p_publ_timing->dtpr1.b.tFAW = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000)&0x7F;
2178 p_publ_timing->dtpr1.b.tAOND = 0;
2182 p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
2183 /**************************************************
2185 **************************************************/
2186 p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
2188 else if(mem_type == LPDDR2)
2190 #define LPDDR2_tREFI_3_9_us (38)
2191 #define LPDDR2_tREFI_7_8_us (78)
2192 #define LPDDR2_tMRD (5) //tCK
2193 #define LPDDR2_tRFC_8Gb (210) //ns
2194 #define LPDDR2_tRFC_4Gb (130) //ns
2195 #define LPDDR2_tRP_4_BANK (24) //ns
2196 #define LPDDR2_tRPab_SUB_tRPpb_4_BANK (0)
2197 #define LPDDR2_tRP_8_BANK (27) //ns
2198 #define LPDDR2_tRPab_SUB_tRPpb_8_BANK (3)
2199 #define LPDDR2_tRTW (1) //tCK register min valid value
2200 #define LPDDR2_tRAS (42) //ns
2201 #define LPDDR2_tRCD (24) //ns
2202 #define LPDDR2_tRRD (10) //ns
2203 #define LPDDR2_tRTP (7) //ns
2204 #define LPDDR2_tWR (15) //ns
2205 #define LPDDR2_tWTR_GREAT_200MHz (7) //ns
2206 #define LPDDR2_tWTR_LITTLE_200MHz (10) //ns
2207 #define LPDDR2_tXP (7) //ns
2208 #define LPDDR2_tXPDLL (0)
2209 #define LPDDR2_tZQCS (90) //ns
2210 #define LPDDR2_tZQCSI (10000)
2211 #define LPDDR2_tDQS (1)
2212 #define LPDDR2_tCKSRE (1) //tCK
2213 #define LPDDR2_tCKSRX (2) //tCK
2214 #define LPDDR2_tCKE (3) //tCK
2215 #define LPDDR2_tMOD (0)
2216 #define LPDDR2_tRSTL (0)
2217 #define LPDDR2_tZQCL (360) //ns
2218 #define LPDDR2_tMRR (2) //tCK
2219 #define LPDDR2_tCKESR (15) //ns
2220 #define LPDDR2_tDPD_US (500)
2221 #define LPDDR2_tFAW_GREAT_200MHz (50) //ns
2222 #define LPDDR2_tFAW_LITTLE_200MHz (60) //ns
2223 #define LPDDR2_tDLLK (2) //tCK
2224 #define LPDDR2_tDQSCK_MAX (3) //tCK
2225 #define LPDDR2_tDQSCK_MIN (0) //tCK
2226 #define LPDDR2_tDQSS (1) //tCK
2230 /* 1066 933 800 667 533 400 333
2238 p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
2244 p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
2250 p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
2256 p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
2262 p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
2268 p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
2270 p_publ_timing->mr[3] = LPDDR2_DS_34;
2271 p_publ_timing->mr[0] = 0;
2272 /**************************************************
2274 **************************************************/
2276 * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
2278 if(ddr_capability_per_die >= 0x10000000) // 2Gb
2280 p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
2284 p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
2288 * tMRD, (=tMRW), 5 tCK
2290 p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
2291 p_publ_timing->dtpr0.b.tMRD = 3;
2293 * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
2295 if(ddr_capability_per_die >= 0x40000000) // 8Gb
2297 p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
2301 p_pctl_timing->texsr = (((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000)&0x3FF;
2302 p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000)&0xFF;
2303 p_publ_timing->dtpr2.b.tXS = (((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000)&0x3FF;
2307 p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
2308 p_pctl_timing->texsr = (((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000)&0x3FF;
2309 p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000)&0xFF;
2310 p_publ_timing->dtpr2.b.tXS = (((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000)&0x3FF;
2314 * tRP, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow)
2316 if(pPHY_Reg->DCR.b.DDR8BNK)
2318 p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (((LPDDR2_tRP_8_BANK*nMHz+999)/1000)&0xF);
2319 p_publ_timing->dtpr0.b.tRP = ((LPDDR2_tRP_8_BANK*nMHz+999)/1000);
2321 * WrToMiss=WL*tCK + tDQSS + tWR + tRP + tRCD
2323 p_noc_timing->b.WrToMiss = ((cwl+LPDDR2_tDQSS+(((LPDDR2_tWR+LPDDR2_tRP_8_BANK+LPDDR2_tRCD)*nMHz+999)/1000))&0x3F);
2325 * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
2327 p_noc_timing->b.RdToMiss = (((((LPDDR2_tRTP+LPDDR2_tRP_8_BANK+LPDDR2_tRCD)*nMHz+(nMHz>>1)+999)/1000)-(bl>>1))&0x3F);
2331 p_pctl_timing->trc = ((((LPDDR2_tRP_8_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0x3F);
2332 p_noc_timing->b.ActToAct = ((((LPDDR2_tRP_8_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0x3F);
2333 p_publ_timing->dtpr0.b.tRC = (((LPDDR2_tRP_8_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0xF;
2337 p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (((LPDDR2_tRP_4_BANK*nMHz+999)/1000)&0xF);
2338 p_publ_timing->dtpr0.b.tRP = ((LPDDR2_tRP_4_BANK*nMHz+999)/1000);
2339 p_noc_timing->b.WrToMiss = ((cwl+LPDDR2_tDQSS+(((LPDDR2_tWR+LPDDR2_tRP_4_BANK+LPDDR2_tRCD)*nMHz+999)/1000))&0x3F);
2340 p_noc_timing->b.RdToMiss = (((((LPDDR2_tRTP+LPDDR2_tRP_4_BANK+LPDDR2_tRCD)*nMHz+(nMHz>>1)+999)/1000)-(bl>>1))&0x3F);
2341 p_pctl_timing->trc = ((((LPDDR2_tRP_4_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0x3F);
2342 p_noc_timing->b.ActToAct = ((((LPDDR2_tRP_4_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0x3F);
2343 p_publ_timing->dtpr0.b.tRC = (((LPDDR2_tRP_4_BANK+LPDDR2_tRAS)*nMHz+999)/1000)&0xF;
2346 p_pctl_timing->trtw = (cl+LPDDR2_tDQSCK_MAX+(bl/2)+1-cwl);//LPDDR2_tRTW;
2347 p_publ_timing->dtpr1.b.tRTW = 0;
2349 * RdToWr=RL+tDQSCK-WL
2351 p_noc_timing->b.RdToWr = ((cl+LPDDR2_tDQSCK_MAX+1-cwl)&0x1F);
2352 p_pctl_timing->tal = al;
2353 p_pctl_timing->tcl = cl;
2354 p_pctl_timing->tcwl = cwl;
2358 p_pctl_timing->tras = (((LPDDR2_tRAS*nMHz+999)/1000)&0x3F);
2359 p_publ_timing->dtpr0.b.tRAS = ((LPDDR2_tRAS*nMHz+999)/1000)&0x1F;
2361 * tRCD, 15ns(Fast) 18ns(Typ) 24ns(Slow)
2363 p_pctl_timing->trcd = (((LPDDR2_tRCD*nMHz+999)/1000)&0xF);
2364 p_publ_timing->dtpr0.b.tRCD = ((LPDDR2_tRCD*nMHz+999)/1000)&0xF;
2368 p_pctl_timing->trrd = (((LPDDR2_tRRD*nMHz+999)/1000)&0xF);
2369 p_publ_timing->dtpr0.b.tRRD = ((LPDDR2_tRRD*nMHz+999)/1000)&0xF;
2373 tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
2374 p_pctl_timing->trtp = tmp&0xF;
2375 p_publ_timing->dtpr0.b.tRTP = (tmp<2) ? 2 : tmp;
2379 p_pctl_timing->twr = ((LPDDR2_tWR*nMHz+999)/1000)&0x1F;
2380 bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
2381 p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(((LPDDR2_tWR*nMHz+999)/1000));
2383 * tWTR, 7.5ns(533-266MHz) 10ns(200-166MHz)
2387 p_pctl_timing->twtr = ((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000)&0xF;
2388 p_publ_timing->dtpr0.b.tWTR = ((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000)&0x7;
2390 * WrToRd=WL+tDQSS+tWTR
2392 p_noc_timing->b.WrToRd = ((LPDDR2_tDQSS+((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000)+cwl)&0x1F);
2396 p_pctl_timing->twtr = ((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000)&0xF;
2397 p_publ_timing->dtpr0.b.tWTR = ((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000)&0x7;
2398 p_noc_timing->b.WrToRd = ((LPDDR2_tDQSS+((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000)+cwl)&0x1F);
2403 p_pctl_timing->txp = ((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000)&0x7;
2404 p_publ_timing->dtpr2.b.tXP = ((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000)&0x1F;
2408 p_pctl_timing->txpdll = LPDDR2_tXPDLL;
2412 p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
2416 if(pDDR_Reg->MCFG &= lpddr2_s4)
2418 p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
2422 p_pctl_timing->tzqcsi = 0;
2427 p_pctl_timing->tdqs = LPDDR2_tDQS;
2431 p_pctl_timing->tcksre = LPDDR2_tCKSRE;
2435 p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
2439 p_pctl_timing->tcke = LPDDR2_tCKE;
2440 p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
2444 p_pctl_timing->tmod = LPDDR2_tMOD;
2445 p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
2449 p_pctl_timing->trstl = LPDDR2_tRSTL;
2453 p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
2457 p_pctl_timing->tmrr = LPDDR2_tMRR;
2461 p_pctl_timing->tckesr = ((LPDDR2_tCKESR*nMHz+999)/1000)&0xF;
2465 p_pctl_timing->tdpd = LPDDR2_tDPD_US;
2467 /**************************************************
2469 **************************************************/
2471 * tCCD, BL/2 for DDR2 and 4 for DDR3
2473 p_publ_timing->dtpr0.b.tCCD = 0;
2477 p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
2481 p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
2483 * tRTODT, 0:ODT may be turned on immediately after read post-amble
2484 * 1:ODT may not be turned on until one clock after the read post-amble
2486 p_publ_timing->dtpr1.b.tRTODT = 1;
2488 * tFAW,50ns(200-533MHz) 60ns(166MHz)
2492 p_publ_timing->dtpr1.b.tFAW = ((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000)&0x7F;
2496 p_publ_timing->dtpr1.b.tFAW = ((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000)&0x7F;
2501 p_publ_timing->dtpr1.b.tAOND = 0;
2505 p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
2506 /**************************************************
2508 **************************************************/
2509 p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
2511 else if(mem_type == DDR2)
2513 #define DDR2_tREFI_7_8_us (78)
2514 #define DDR2_tMRD (2)
2515 #define DDR2_tRFC_256Mb (75)
2516 #define DDR2_tRFC_512Mb (105)
2517 #define DDR2_tRFC_1Gb (128)
2518 #define DDR2_tRFC_2Gb (195)
2519 #define DDR2_tRFC_4Gb (328)
2520 #define DDR2_tRAS (45)
2521 #define DDR2_tRTW (2) //register min valid value
2522 #define DDR2_tRRD (10)
2523 #define DDR2_tRTP (7)
2524 #define DDR2_tWR (15)
2525 #define DDR2_tWTR_LITTLE_200MHz (10)
2526 #define DDR2_tWTR_GREAT_200MHz (7)
2527 #define DDR2_tDQS (1)
2528 #define DDR2_tCKSRE (1)
2529 #define DDR2_tCKSRX (1)
2530 #define DDR2_tCKE (3)
2531 #define DDR2_tCKESR DDR2_tCKE
2532 #define DDR2_tMOD (12)
2533 #define DDR2_tFAW_333MHz (50)
2534 #define DDR2_tFAW_400MHz (45)
2535 #define DDR2_tDLLK (200)
2543 else if((nMHz > 266) && (nMHz <= 333))
2547 else if((nMHz > 333) && (nMHz <= 400))
2556 if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2558 p_publ_timing->mr[1] = DDR2_STR_REDUCE | DDR2_Rtt_Nom_DIS;
2562 p_publ_timing->mr[1] = DDR2_STR_REDUCE | DDR2_Rtt_Nom_75;
2564 p_publ_timing->mr[2] = 0;
2565 p_publ_timing->mr[3] = 0;
2566 /**************************************************
2568 **************************************************/
2570 * tREFI, average periodic refresh interval, 7.8us
2572 p_pctl_timing->trefi = DDR2_tREFI_7_8_us;
2576 p_pctl_timing->tmrd = DDR2_tMRD & 0x7;
2577 p_publ_timing->dtpr0.b.tMRD = DDR2_tMRD;
2579 * tRFC, 75ns(256Mb) 105ns(512Mb) 127.5ns(1Gb) 195ns(2Gb) 327.5ns(4Gb)
2581 if(ddr_capability_per_die <= 0x2000000) // 256Mb
2583 tmp = DDR2_tRFC_256Mb;
2585 else if(ddr_capability_per_die <= 0x4000000) // 512Mb
2587 tmp = DDR2_tRFC_512Mb;
2589 else if(ddr_capability_per_die <= 0x8000000) // 1Gb
2591 tmp = DDR2_tRFC_1Gb;
2593 else if(ddr_capability_per_die <= 0x10000000) // 2Gb
2595 tmp = DDR2_tRFC_2Gb;
2599 tmp = DDR2_tRFC_4Gb;
2601 p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2602 p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000)&0xFF;
2604 * tXSR, max(tRFC+10,200 tCK)
2606 tmp = (((tmp+10)*nMHz+999)/1000);
2611 p_pctl_timing->texsr = tmp&0x3FF;
2612 p_publ_timing->dtpr2.b.tXS = tmp&0x3FF;
2616 if(pPHY_Reg->DCR.b.DDR8BNK)
2618 p_pctl_timing->trp = (1<<16) | cl;
2622 p_pctl_timing->trp = cl;
2624 p_publ_timing->dtpr0.b.tRP = cl;
2626 * WrToMiss=WL*tCK + tWR + tRP + tRCD
2628 p_noc_timing->b.WrToMiss = ((cwl+((DDR2_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
2632 tmp=((DDR2_tRAS*nMHz+999)/1000);
2633 p_pctl_timing->tras = (tmp&0x3F);
2634 p_publ_timing->dtpr0.b.tRAS = tmp&0x1F;
2638 p_pctl_timing->trc = ((tmp+cl)&0x3F);
2639 p_noc_timing->b.ActToAct = ((tmp+cl)&0x3F);
2640 p_publ_timing->dtpr0.b.tRC = (tmp+cl)&0xF;
2642 p_pctl_timing->trtw = (cl+2-cwl);//DDR2_tRTW;
2643 p_publ_timing->dtpr1.b.tRTW = 0;
2644 p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
2645 p_pctl_timing->tal = al;
2646 p_pctl_timing->tcl = cl;
2647 p_pctl_timing->tcwl = cwl;
2651 p_pctl_timing->trcd = cl;
2652 p_publ_timing->dtpr0.b.tRCD = cl;
2654 * tRRD = 10ns(2KB page)
2657 p_pctl_timing->trrd = (((DDR2_tRRD*nMHz+999)/1000)&0xF);
2658 p_publ_timing->dtpr0.b.tRRD = ((DDR2_tRRD*nMHz+999)/1000)&0xF;
2662 tmp = ((DDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
2663 p_pctl_timing->trtp = tmp&0xF;
2664 p_publ_timing->dtpr0.b.tRTP = tmp;
2666 * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2668 p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
2672 tmp = ((DDR2_tWR*nMHz+999)/1000);
2673 p_pctl_timing->twr = tmp&0x1F;
2674 bl_tmp = (bl == 8) ? DDR2_BL8 : DDR2_BL4;
2675 p_publ_timing->mr[0] = bl_tmp | DDR2_CL(cl) | DDR2_WR(tmp);
2677 * tWTR, 10ns(200MHz) 7.5ns(>200MHz)
2681 tmp = ((DDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
2685 tmp = ((DDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
2687 p_pctl_timing->twtr = tmp&0xF;
2688 p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
2689 p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
2691 * tXP, 6-AL(200MHz) 6-AL(266MHz) 7-AL(333MHz) 8-AL(400MHz) 10-AL(533MHz)
2709 p_pctl_timing->txp = tmp&0x7;
2710 p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
2714 p_pctl_timing->txpdll = tmp & 0x3F;
2718 p_pctl_timing->tzqcs = 0;
2722 p_pctl_timing->tzqcsi = 0;
2726 p_pctl_timing->tdqs = DDR2_tDQS;
2730 p_pctl_timing->tcksre = DDR2_tCKSRE & 0x1F;
2732 * tCKSRX, no such timing
2734 p_pctl_timing->tcksrx = DDR2_tCKSRX & 0x1F;
2738 p_pctl_timing->tcke = DDR2_tCKE & 0x7;
2739 p_publ_timing->dtpr2.b.tCKE = DDR2_tCKE;
2743 p_pctl_timing->tckesr = DDR2_tCKESR&0xF;
2747 p_pctl_timing->tmod = ((DDR2_tMOD*nMHz+999)/1000)&0x1F;
2748 p_publ_timing->dtpr1.b.tMOD = ((DDR2_tMOD*nMHz+999)/1000);
2752 p_pctl_timing->trstl = 0;
2756 p_pctl_timing->tzqcl = 0;
2760 p_pctl_timing->tmrr = 0;
2764 p_pctl_timing->tdpd = 0;
2766 /**************************************************
2768 **************************************************/
2770 * tCCD, BL/2 for DDR2 and 4 for DDR3
2772 p_publ_timing->dtpr0.b.tCCD = 0;
2776 p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2778 * tRTODT, 0:ODT may be turned on immediately after read post-amble
2779 * 1:ODT may not be turned on until one clock after the read post-amble
2781 p_publ_timing->dtpr1.b.tRTODT = 1;
2783 * tFAW,50ns(<=333MHz 2KB page) 45ns(400MHz 2KB page) 45ns(533MHz 2KB page)
2787 tmp = DDR2_tFAW_333MHz;
2791 tmp = DDR2_tFAW_400MHz;
2793 p_publ_timing->dtpr1.b.tFAW = ((tmp*nMHz+999)/1000)&0x7F;
2797 p_publ_timing->dtpr1.b.tAOND = 0;
2799 * tDLLK,=tXSRD=200 tCK
2801 p_publ_timing->dtpr2.b.tDLLK = DDR2_tDLLK;
2802 /**************************************************
2804 **************************************************/
2805 p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
2807 else //if(mem_type == LPDDR)
2809 #define mDDR_tREFI_7_8_us (78)
2810 #define mDDR_tMRD (2)
2811 #define mDDR_tRFC_256Mb (80)
2812 #define mDDR_tRFC_512Mb (110)
2813 #define mDDR_tRFC_1Gb (140)
2814 #define mDDR_tXSR (200)
2815 #define mDDR_tRAS_100MHz (50)
2816 #define mDDR_tRAS_133MHz (45)
2817 #define mDDR_tRAS_185MHz (42)
2818 #define mDDR_tRAS_200MHz (40)
2819 #define mDDR_tRTW (3) //register min valid value
2820 #define mDDR_tRRD_133MHz (15)
2821 #define mDDR_tRRD_166MHz (12)
2822 #define mDDR_tRRD_185MHz (11)
2823 #define mDDR_tRRD_200MHz (10)
2824 #define mDDR_tRTP (0)
2825 #define mDDR_tWR (15)
2826 #define mDDR_tWTR_133MHz (1)
2827 #define mDDR_tWTR_200MHz (2)
2828 #define mDDR_tXP (25)
2829 #define mDDR_tDQS (1)
2830 #define mDDR_tCKSRE (1)
2831 #define mDDR_tCKSRX (1)
2832 #define mDDR_tCKE (2)
2837 * mobile DDR timing USE 3-3-3, CL always = 3
2841 bl_tmp = (bl == 8) ? mDDR_BL8 : ((bl == 4) ? mDDR_BL4 : mDDR_BL2);
2842 p_publ_timing->mr[0] = bl_tmp | mDDR_CL(cl);
2843 p_publ_timing->mr[2] = mDDR_DS_3_4; //mr[2] is mDDR MR1
2844 p_publ_timing->mr[1] = 0;
2845 p_publ_timing->mr[3] = 0;
2846 /**************************************************
2848 **************************************************/
2850 * tREFI, average periodic refresh interval, 7.8us
2852 p_pctl_timing->trefi = mDDR_tREFI_7_8_us;
2856 p_pctl_timing->tmrd = mDDR_tMRD & 0x7;
2857 p_publ_timing->dtpr0.b.tMRD = mDDR_tMRD;
2859 * tRFC, 80ns(128Mb,256Mb) 110ns(512Mb) 140ns(1Gb,2Gb)
2861 if(ddr_capability_per_die <= 0x2000000) // 256Mb
2863 tmp = mDDR_tRFC_256Mb;
2865 else if(ddr_capability_per_die <= 0x4000000) // 512Mb
2867 tmp = mDDR_tRFC_512Mb;
2871 tmp = mDDR_tRFC_1Gb;
2873 p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2874 p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000)&0xFF;
2878 p_pctl_timing->tckesr = tmp&0xF;
2882 p_pctl_timing->texsr = ((mDDR_tXSR*nMHz+999)/1000)&0x3FF;
2883 p_publ_timing->dtpr2.b.tXS = ((mDDR_tXSR*nMHz+999)/1000)&0x3FF;
2887 p_pctl_timing->trp = cl;
2888 p_publ_timing->dtpr0.b.tRP = cl;
2890 * WrToMiss=WL*tCK + tWR + tRP + tRCD
2892 p_noc_timing->b.WrToMiss = ((cwl+((mDDR_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
2894 * tRAS, 50ns(100MHz) 45ns(133MHz) 42ns(166MHz) 42ns(185MHz) 40ns(200MHz)
2898 tmp = mDDR_tRAS_100MHz;
2902 tmp = mDDR_tRAS_133MHz;
2906 tmp =mDDR_tRAS_185MHz;
2910 tmp = mDDR_tRAS_200MHz;
2912 tmp = ((tmp*nMHz+999)/1000);
2913 p_pctl_timing->tras = (tmp&0x3F);
2914 p_publ_timing->dtpr0.b.tRAS = tmp&0x1F;
2918 p_pctl_timing->trc = ((tmp+cl)&0x3F);
2919 p_noc_timing->b.ActToAct = ((tmp+cl)&0x3F);
2920 p_publ_timing->dtpr0.b.tRC = (tmp+cl)&0xF;
2921 p_pctl_timing->trtw = (cl+2-cwl);//mDDR_tRTW;
2922 p_publ_timing->dtpr1.b.tRTW = 0;
2923 p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
2924 p_pctl_timing->tal = al;
2925 p_pctl_timing->tcl = cl;
2926 p_pctl_timing->tcwl = cwl;
2930 p_pctl_timing->trcd = cl;
2931 p_publ_timing->dtpr0.b.tRCD = cl;
2933 * tRRD,15ns(100MHz) 15ns(133MHz) 12ns(166MHz) 10.8ns(185MHz) 10ns(200MHz)
2938 tmp = mDDR_tRRD_133MHz;
2942 tmp = mDDR_tRRD_166MHz;
2946 tmp = mDDR_tRRD_185MHz;
2950 tmp = mDDR_tRRD_200MHz;
2952 p_pctl_timing->trrd = (((tmp*nMHz+999)/1000)&0xF);
2953 p_publ_timing->dtpr0.b.tRRD = ((tmp*nMHz+999)/1000)&0xF;
2957 tmp = ((mDDR_tRTP*nMHz+999)/1000);
2958 p_pctl_timing->trtp = tmp&0xF;
2959 p_publ_timing->dtpr0.b.tRTP = tmp;
2961 * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2963 p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
2967 p_pctl_timing->twr = ((mDDR_tWR*nMHz+999)/1000)&0x1F;
2969 * tWTR, 1 tCK(100MHz,133MHz) 2 tCK(166MHz,185MHz,200MHz)
2973 tmp = mDDR_tWTR_133MHz;
2977 tmp = mDDR_tWTR_200MHz;
2979 p_pctl_timing->twtr = tmp&0xF;
2980 p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
2981 p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
2986 p_pctl_timing->txp = ((mDDR_tXP*nMHz+999)/1000)&0x7;
2987 p_publ_timing->dtpr2.b.tXP = ((mDDR_tXP*nMHz+999)/1000)&0x1F;
2991 p_pctl_timing->txpdll = 0;
2995 p_pctl_timing->tzqcs = 0;
2999 p_pctl_timing->tzqcsi = 0;
3003 p_pctl_timing->tdqs = mDDR_tDQS;
3007 p_pctl_timing->tcksre = mDDR_tCKSRE & 0x1F;
3009 * tCKSRX, no such timing
3011 p_pctl_timing->tcksrx = mDDR_tCKSRX & 0x1F;
3015 p_pctl_timing->tcke = mDDR_tCKE & 0x7;
3016 p_publ_timing->dtpr2.b.tCKE = mDDR_tCKE;
3020 p_pctl_timing->tmod = 0;
3021 p_publ_timing->dtpr1.b.tMOD = 0;
3025 p_pctl_timing->trstl = 0;
3029 p_pctl_timing->tzqcl = 0;
3033 p_pctl_timing->tmrr = 0;
3037 p_pctl_timing->tdpd = 0;
3039 /**************************************************
3041 **************************************************/
3043 * tCCD, BL/2 for DDR2 and 4 for DDR3
3045 p_publ_timing->dtpr0.b.tCCD = 0;
3049 p_publ_timing->dtpr1.b.tDQSCKmax = 0;
3051 * tRTODT, 0:ODT may be turned on immediately after read post-amble
3052 * 1:ODT may not be turned on until one clock after the read post-amble
3054 p_publ_timing->dtpr1.b.tRTODT = 1;
3058 p_publ_timing->dtpr1.b.tFAW = 0;
3062 p_publ_timing->dtpr1.b.tAOND = 0;
3066 p_publ_timing->dtpr2.b.tDLLK = 0;
3067 /**************************************************
3069 **************************************************/
3070 p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
3076 uint32_t __sramlocalfunc ddr_update_timing(void)
3078 uint32_t i,bl_tmp=0;
3079 PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
3080 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
3081 NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
3083 ddr_copy((uint32_t *)&(pDDR_Reg->TOGCNT1U), (uint32_t*)&(p_pctl_timing->togcnt1u), 34);
3084 ddr_copy((uint32_t *)&(pPHY_Reg->DTPR[0]), (uint32_t*)&(p_publ_timing->dtpr0), 3);
3085 *(volatile uint32_t *)SysSrv_DdrTiming = p_noc_timing->d32;
3087 if(mem_type == DDR3)
3089 bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
3090 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
3091 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-2;
3092 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL-1;
3094 else if(mem_type == LPDDR2)
3096 if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
3098 bl_tmp = mddr_lpddr2_bl_8;
3100 else if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
3102 bl_tmp = mddr_lpddr2_bl_4;
3104 else //if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL16)
3106 bl_tmp = mddr_lpddr2_bl_16;
3110 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
3114 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | mddr_lpddr2_bl_8 | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
3116 i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
3117 pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8); //tDQSCKmax-tDQSCK
3118 pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-1;
3119 pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL;
3121 else if(mem_type == DDR2)
3123 bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR2_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
3124 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
3126 else// if(mem_type == LPDDR)
3128 switch(p_publ_timing->mr[0] & 0x7)
3131 bl_tmp = mddr_lpddr2_bl_2;
3134 bl_tmp = mddr_lpddr2_bl_4;
3137 bl_tmp = mddr_lpddr2_bl_8;
3140 pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
3145 uint32_t __sramlocalfunc ddr_update_mr(void)
3147 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
3148 uint32_t cs,dll_off;
3150 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3151 dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
3152 ddr_copy((uint32_t *)&(pPHY_Reg->MR[0]), (uint32_t*)&(p_publ_timing->mr[0]), 4);
3153 if((mem_type == DDR3) || (mem_type == DDR2))
3155 if(ddr_freq>DDR3_DDR2_DLL_DISABLE_FREQ)
3157 if(dll_off) // off -> on
3159 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1]))); //DLL enable
3160 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((p_publ_timing->mr[0]))| DDR3_DLL_RESET)); //DLL reset
3161 ddr_delayus(2); //at least 200 DDR cycle
3162 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3166 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));
3167 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3172 pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3173 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE)); //DLL disable
3174 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3176 ddr_send_command(cs, MRS_cmd, bank_addr(0x2) | cmd_addr((p_publ_timing->mr[2])));
3178 else if(mem_type == LPDDR2)
3180 ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((p_publ_timing->mr[1])));
3181 ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((p_publ_timing->mr[2])));
3182 ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((p_publ_timing->mr[3])));
3186 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3187 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
3192 void __sramlocalfunc ddr_update_odt(void)
3196 //adjust DRV and ODT
3197 if((mem_type == DDR3) || (mem_type == DDR2))
3199 if(ddr_freq <= DDR3_DDR2_ODT_DISABLE_FREQ)
3201 pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
3202 pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3203 if(!(pDDR_Reg->PPCFG & 1))
3205 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3206 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3211 pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9); //dynamic RTT enable
3212 pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
3213 if(!(pDDR_Reg->PPCFG & 1))
3215 pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
3216 pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
3222 pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
3223 pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3224 if(!(pDDR_Reg->PPCFG & 1))
3226 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3227 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3230 tmp = (0x1<<28) | (0x2<<15) | (0x2<<10) | (0xb<<5) | 0xb; //DS=34ohm,ODT=171ohm
3231 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3234 pPHY_Reg->ZQ1CR[0] = tmp;
3237 pPHY_Reg->ZQ0CR[0] = tmp;
3241 __sramfunc void ddr_adjust_config(uint32_t dram_type)
3244 unsigned long save_sp;
3247 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3249 //get data training address before idle port
3250 value = ddr_get_datatraing_addr();
3252 /** 1. Make sure there is no host access */
3257 DDR_SAVE_SP(save_sp);
3264 n= pDDR_Reg->SCFG.d32;
3266 n= pCRU_Reg->CRU_PLL_CON[0][0];
3267 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3268 n= *(volatile uint32_t *)SysSrv_DdrConf;
3269 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
3270 n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
3272 n= pGRF_Reg->GRF_SOC_STATUS0;
3276 //enter config state
3277 ddr_move_to_Config_state();
3279 //set data training address
3280 pPHY_Reg->DTAR = value;
3282 //set auto power down idle
3283 pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
3286 pPHY_Reg->PGCR &= ~(0x3<<12);
3288 //enable the hardware low-power interface
3289 pDDR_Reg->SCFG.b.hw_low_power_en = 1;
3291 if(pDDR_Reg->PPCFG & 1)
3293 pPHY_Reg->DATX8[2].DXGCR &= ~(1); //disable byte
3294 pPHY_Reg->DATX8[3].DXGCR &= ~(1);
3295 pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000; //disable DLL
3296 pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
3301 //enter access state
3302 ddr_move_to_Access_state();
3304 DDR_RESTORE_SP(save_sp);
3308 void __sramlocalfunc idle_port(void)
3311 uint32 clk_gate[10];
3313 //save clock gate status
3315 clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
3317 //enable all clock gate for request idle
3319 pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
3321 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
3323 #ifdef CONFIG_ARCH_RK3188
3324 pPMU_Reg->PMU_MISC_CON1 |= idle_req_dma_cfg;
3326 while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) == 0 );
3328 pPMU_Reg->PMU_MISC_CON1 |= idle_req_cpu_cfg;
3330 while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) == 0 );
3334 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
3336 pPMU_Reg->PMU_MISC_CON1 |= idle_req_peri_cfg;
3338 while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) == 0 );
3341 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
3343 pPMU_Reg->PMU_MISC_CON1 |= idle_req_vio_cfg;
3345 while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) == 0 );
3348 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
3350 pPMU_Reg->PMU_MISC_CON1 |= idle_req_video_cfg;
3352 while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) == 0 );
3355 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
3357 pPMU_Reg->PMU_MISC_CON1 |= idle_req_gpu_cfg;
3359 while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) == 0 );
3362 //resume clock gate status
3364 pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
3367 void __sramlocalfunc deidle_port(void)
3370 uint32 clk_gate[10];
3372 //save clock gate status
3374 clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
3376 //enable all clock gate for request idle
3378 pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
3380 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
3383 #ifdef CONFIG_ARCH_RK3188
3384 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_dma_cfg;
3386 while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) != 0 );
3388 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_cpu_cfg;
3390 while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) != 0 );
3393 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
3395 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_peri_cfg;
3397 while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) != 0 );
3400 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
3402 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_vio_cfg;
3404 while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) != 0 );
3407 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
3409 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_video_cfg;
3411 while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) != 0 );
3414 if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
3416 pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_gpu_cfg;
3418 while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) != 0 );
3421 //resume clock gate status
3423 pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
3427 void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
3429 PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
3432 ddr_move_to_Config_state();
3433 pDDR_Reg->TZQCSI = 0;
3434 if((nMHz<=DDR3_DDR2_DLL_DISABLE_FREQ) && ((mem_type == DDR3) || (mem_type == DDR2))) // DLL disable
3436 cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3437 pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3438 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));
3440 ddr_move_to_Lowpower_state();
3442 ddr_set_dll_bypass(0); //dll bypass
3443 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2); //disable DDR PHY clock
3447 void __sramlocalfunc ddr_selfrefresh_exit(void)
3451 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2); //enable DDR PHY clock
3453 ddr_set_dll_bypass(ddr_freq);
3455 //ddr_delayus(10); //wait DLL lock
3457 ddr_move_to_Config_state();
3458 ddr_update_timing();
3461 n = ddr_data_training();
3462 ddr_move_to_Access_state();
3465 sram_printascii("DTT failed!\n");
3469 #if defined(CONFIG_ARCH_RK3066B)
3470 static __sramdata uint32_t data8_dqstr[25][4];
3471 static __sramdata uint32_t min_ddr_freq,dqstr_flag=false;
3473 int ddr_get_datatraing_value_3168(bool end_flag,uint32_t dqstr_value,uint32_t min_freq)
3475 if(end_flag == true)
3477 dqstr_flag = true; //complete learn data training value flag
3478 min_ddr_freq = min_freq;
3482 data8_dqstr[dqstr_value][0]=pPHY_Reg->DATX8[0].DXDQSTR;
3483 data8_dqstr[dqstr_value][1]=pPHY_Reg->DATX8[0].DXDQSTR;
3484 data8_dqstr[dqstr_value][2]=pPHY_Reg->DATX8[0].DXDQSTR;
3485 data8_dqstr[dqstr_value][3]=pPHY_Reg->DATX8[0].DXDQSTR;
3487 ddr_print("training %luMhz[%d]:0x%x-0x%x-0x%x-0x%x\n",
3488 clk_get_rate(clk_get(NULL, "ddr_pll"))/1000000,dqstr_value,data8_dqstr[dqstr_value][0],data8_dqstr[dqstr_value][1],
3489 data8_dqstr[dqstr_value][2],data8_dqstr[dqstr_value][3]);
3492 EXPORT_SYMBOL(ddr_get_datatraing_value_3168);
3494 void __sramlocalfunc ddr_set_pll_enter_3168(uint32_t freq_slew)
3496 uint32_t value_1u,value_100n;
3497 ddr_move_to_Config_state();
3501 value_100n = ddr_reg.pctl.pctl_timing.togcnt100n;
3502 value_1u = ddr_reg.pctl.pctl_timing.togcnt1u;
3503 ddr_reg.pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
3504 ddr_reg.pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
3505 ddr_update_timing();
3507 ddr_reg.pctl.pctl_timing.togcnt100n = value_100n;
3508 ddr_reg.pctl.pctl_timing.togcnt1u = value_1u;
3512 pDDR_Reg->TOGCNT100N = ddr_reg.pctl.pctl_timing.togcnt100n;
3513 pDDR_Reg->TOGCNT1U = ddr_reg.pctl.pctl_timing.togcnt1u;
3516 pDDR_Reg->TZQCSI = 0;
3517 ddr_move_to_Lowpower_state();
3519 ddr_set_dll_bypass(0); //dll bypass
3520 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2); //disable DDR PHY clock
3524 void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32_t dqstr_value)
3526 pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2); //enable DDR PHY clock
3528 ddr_set_dll_bypass(ddr_freq);
3531 if(dqstr_flag==true)
3533 pPHY_Reg->DATX8[0].DXDQSTR=data8_dqstr[dqstr_value][0];
3534 pPHY_Reg->DATX8[1].DXDQSTR=data8_dqstr[dqstr_value][1];
3535 pPHY_Reg->DATX8[2].DXDQSTR=data8_dqstr[dqstr_value][2];
3536 pPHY_Reg->DATX8[3].DXDQSTR=data8_dqstr[dqstr_value][3];
3540 ddr_move_to_Config_state();
3543 pDDR_Reg->TOGCNT100N = ddr_reg.pctl.pctl_timing.togcnt100n;
3544 pDDR_Reg->TOGCNT1U = ddr_reg.pctl.pctl_timing.togcnt1u;
3545 pDDR_Reg->TZQCSI = ddr_reg.pctl.pctl_timing.tzqcsi;
3549 ddr_update_timing();
3552 ddr_data_training();
3553 ddr_move_to_Access_state();
3557 static __sramdata bool ddr_rk3188_dpll_is_good=true;
3558 #if defined(CONFIG_ARCH_RK3188)
3559 bool ddr_get_dpll_status(void) //CPLL or DPLL bad rerurn false;good return true;
3561 if (rk_pll_flag() & 0x3)
3568 uint32_t __sramfunc ddr_change_freq_sram(uint32_t nMHz)
3573 unsigned long flags;
3574 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3575 unsigned long save_sp;
3578 #if defined(CONFIG_ARCH_RK3066B)
3579 uint32_t freq_slew=0,dqstr_value=0;
3580 if(dqstr_flag==true)
3582 dqstr_value=(nMHz-min_ddr_freq+1)/50;
3583 freq_slew = (nMHz>ddr_freq)? 1 : 0;
3587 freq = ddr_get_pll_freq(APLL); //APLL
3589 loops_per_us = LPJ_100MHZ*freq / 1000000;
3591 ret=ddr_set_pll(nMHz,0);
3593 ddr_get_parameter(ret);
3595 /** 1. Make sure there is no host access */
3596 local_irq_save(flags);
3597 local_fiq_disable();
3602 DDR_SAVE_SP(save_sp);
3604 #if defined(CONFIG_ARCH_RK30)
3605 #define SRAM_SIZE RK30_IMEM_SIZE
3606 #elif defined(CONFIG_ARCH_RK3188)
3607 #define SRAM_SIZE RK3188_IMEM_SIZE
3609 for(i=0;i<SRAM_SIZE/4096;i++)
3615 n= pDDR_Reg->SCFG.d32;
3617 n= pCRU_Reg->CRU_PLL_CON[0][0];
3618 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3619 n= *(volatile uint32_t *)SysSrv_DdrConf;
3620 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
3621 n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
3623 n= pGRF_Reg->GRF_SOC_STATUS0;
3627 /** 2. ddr enter self-refresh mode or precharge power-down mode */
3629 #if defined(CONFIG_ARCH_RK3066B)
3630 ddr_set_pll_enter_3168(freq_slew);
3632 ddr_selfrefresh_enter(ret);
3635 /** 3. change frequence */
3639 /** 5. Issues a Mode Exit command */
3640 #if defined(CONFIG_ARCH_RK3066B)
3641 ddr_set_pll_exit_3168(freq_slew,dqstr_value);
3643 ddr_selfrefresh_exit();
3647 DDR_RESTORE_SP(save_sp);
3649 local_irq_restore(flags);
3653 uint32_t ddr_change_freq_gpll_dpll(uint32_t nMHz)
3655 uint32_t gpll_freq,gpll_div;
3657 gpllvaluel = ddr_get_pll_freq(GPLL);
3659 if((200 < gpllvaluel) ||( gpllvaluel <1600)) //GPLL:200MHz~1600MHz
3661 if( gpllvaluel > 800) //800-1600MHz /4:200MHz-400MHz
3663 gpll_freq = gpllvaluel/4;
3666 else if( gpllvaluel > 400) //400-800MHz /2:200MHz-400MHz
3668 gpll_freq = gpllvaluel/2;
3671 else //200-400MHz /1:200MHz-400MHz
3673 gpll_freq = gpllvaluel;
3677 ddr_select_gpll_div=gpll_div; //select GPLL
3678 ddr_change_freq_sram(gpll_freq);
3679 ddr_select_gpll_div=0;
3681 ddr_set_pll(nMHz,0); //count DPLL
3682 ddr_set_pll(nMHz,2); //lock DPLL only,but not select DPLL
3686 ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3689 return ddr_change_freq_sram(nMHz);
3693 /*****************************************
3694 if rk3188 DPLL is bad,use GPLL
3696 1000MHz-2000MHz 4:250MHz-500MHz
3697 800MHz-1000MHz 4:200MHz-250MHz 2:400MHz-500MHz
3698 500MHz-800MHz 2:250MHz-400MHz
3699 200MHz-500MHz 1:200MHz-500MHz
3700 ******************************************/
3701 uint32_t ddr_change_freq(uint32_t nMHz)
3704 if(ddr_rk3188_dpll_is_good == false) //if rk3188 DPLL is bad,use GPLL
3706 gpllvaluel = ddr_get_pll_freq(GPLL);
3708 if( (gpllvaluel < 200) ||(gpllvaluel > 2000))
3710 ddr_print("DPLL is bad and GPLL freq = %dMHz,Not suitable for ddr_clock\n",gpllvaluel);
3714 if(gpllvaluel > 1000) //GPLL:1000MHz-2000MHz
3716 ddr_select_gpll_div=4; //DDR_CLCOK:250MHz-500MHz
3718 else if(gpllvaluel > 800) //GPLL:800MHz-1000MHz
3721 ddr_select_gpll_div=2; //DDR_CLCOK:400MHz-500MHz
3723 ddr_select_gpll_div=4; //DDR_CLCOK:200MHz-250MHz
3725 else if(gpllvaluel > 500) //GPLL:500MHz-800MHz
3727 ddr_select_gpll_div=2; //DDR_CLCOK:250MHz-400MHz
3729 else //GPLL:200MHz-500MHz
3731 ddr_select_gpll_div=1; //DDR_CLCOK:200MHz-500MHz
3733 return ddr_change_freq_sram(gpllvaluel/ddr_select_gpll_div);
3737 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH) && defined(CONFIG_ARCH_RK3188)
3738 return ddr_change_freq_gpll_dpll(nMHz);
3740 return ddr_change_freq_sram(nMHz);
3744 EXPORT_SYMBOL(ddr_change_freq);
3746 void ddr_set_auto_self_refresh(bool en)
3748 //set auto self-refresh idle
3749 ddr_sr_idle = en ? SR_IDLE : 0;
3751 EXPORT_SYMBOL(ddr_set_auto_self_refresh);
3760 #define PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
3761 #define PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
3763 #define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
3764 #define CRU_SET_BITS(val,bits_shift, msk) (((val)&(msk)) << (bits_shift))
3766 #define CRU_W_MSK_SETBITS(val,bits_shift,msk) (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
3768 #define PERI_ACLK_DIV_MASK 0x1f
3769 #define PERI_ACLK_DIV_OFF 0
3771 #define PERI_HCLK_DIV_MASK 0x3
3772 #define PERI_HCLK_DIV_OFF 8
3774 #define PERI_PCLK_DIV_MASK 0x3
3775 #define PERI_PCLK_DIV_OFF 12
3776 static __sramdata u32 cru_sel32_sram;
3777 void __sramfunc ddr_suspend(void)
3781 volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3784 if(pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<8))
3788 /** 1. Make sure there is no host access */
3793 #if defined(CONFIG_ARCH_RK30)
3794 #define SRAM_SIZE RK30_IMEM_SIZE
3795 #elif defined(CONFIG_ARCH_RK3188)
3796 #define SRAM_SIZE RK3188_IMEM_SIZE
3798 for(i=0;i<SRAM_SIZE/4096;i++)
3804 n= pDDR_Reg->SCFG.d32;
3806 n= pCRU_Reg->CRU_PLL_CON[0][0];
3807 n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3808 n= *(volatile uint32_t *)SysSrv_DdrConf;
3809 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
3810 n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
3812 n= pGRF_Reg->GRF_SOC_STATUS0;
3816 ddr_selfrefresh_enter(0);
3818 pCRU_Reg->CRU_MODE_CON = PLL_MODE_SLOW(pll_idx); //PLL slow-mode
3821 pCRU_Reg->CRU_PLL_CON[pll_idx][3] = ((0x1<<1)<<16) | (0x1<<1); //PLL power-down
3824 if(pll_idx==GPLL_IDX)
3826 cru_sel32_sram= pCRU_Reg->CRU_CLKSEL_CON[10];
3828 pCRU_Reg->CRU_CLKSEL_CON[10]=CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
3829 | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
3830 |CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK);
3832 pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29))); //CKOE
3834 EXPORT_SYMBOL(ddr_suspend);
3836 void __sramfunc ddr_resume(void)
3840 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
3846 if(pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<8))
3857 pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29)); //CKOE
3860 if(pll_idx==GPLL_IDX)
3861 pCRU_Reg->CRU_CLKSEL_CON[10]=0xffff0000|cru_sel32_sram;
3865 pCRU_Reg->CRU_PLL_CON[pll_idx][3] = ((0x1<<1)<<16) | (0x0<<1); //PLL no power-down
3870 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
3871 if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (1<<5))
3874 if (pGRF_Reg->GRF_SOC_STATUS0 & (1<<4))
3880 pCRU_Reg->CRU_MODE_CON = PLL_MODE_NORM(pll_idx); //PLL normal
3883 ddr_selfrefresh_exit();
3885 EXPORT_SYMBOL(ddr_resume);
3887 //»ñÈ¡ÈÝÁ¿£¬·µ»Ø×Ö½ÚÊý
3888 uint32 ddr_get_cap(void)
3890 return (1 << (ddr_get_row()+ddr_get_col()+ddr_get_bank()+ddr_get_bw()))*ddr_get_cs();
3892 EXPORT_SYMBOL(ddr_get_cap);
3894 void ddr_reg_save(void)
3897 ddr_reg.pctl.SCFG = pDDR_Reg->SCFG.d32;
3898 ddr_reg.pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
3899 ddr_reg.pctl.MCFG1 = pDDR_Reg->MCFG1;
3900 ddr_reg.pctl.MCFG = pDDR_Reg->MCFG;
3901 ddr_reg.pctl.pctl_timing.ddrFreq = ddr_freq;
3902 ddr_reg.pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
3903 ddr_reg.pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
3904 ddr_reg.pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
3905 ddr_reg.pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
3906 ddr_reg.pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
3907 ddr_reg.pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
3908 ddr_reg.pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
3909 ddr_reg.pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
3910 ddr_reg.pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
3911 ddr_reg.pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
3912 ddr_reg.pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
3913 ddr_reg.pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
3914 ddr_reg.pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
3915 ddr_reg.pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
3916 ddr_reg.pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
3918 ddr_reg.pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
3919 ddr_reg.pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
3920 ddr_reg.pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
3921 ddr_reg.pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
3922 ddr_reg.pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
3923 ddr_reg.pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
3924 ddr_reg.pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
3925 ddr_reg.pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
3926 ddr_reg.pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
3929 ddr_reg.publ.PIR = pPHY_Reg->PIR;
3930 ddr_reg.publ.PGCR = pPHY_Reg->PGCR;
3931 ddr_reg.publ.DLLGCR = pPHY_Reg->DLLGCR;
3932 ddr_reg.publ.ACDLLCR = pPHY_Reg->ACDLLCR;
3933 ddr_reg.publ.PTR[0] = pPHY_Reg->PTR[0];
3934 ddr_reg.publ.PTR[1] = pPHY_Reg->PTR[1];
3935 ddr_reg.publ.PTR[2] = pPHY_Reg->PTR[2];
3936 ddr_reg.publ.ACIOCR = pPHY_Reg->ACIOCR;
3937 ddr_reg.publ.DXCCR = pPHY_Reg->DXCCR;
3938 ddr_reg.publ.DSGCR = pPHY_Reg->DSGCR;
3939 ddr_reg.publ.DCR = pPHY_Reg->DCR.d32;
3940 ddr_reg.publ.ODTCR = pPHY_Reg->ODTCR;
3941 ddr_reg.publ.DTAR = pPHY_Reg->DTAR;
3942 ddr_reg.publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
3943 ddr_reg.publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
3945 ddr_reg.publ.DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
3946 ddr_reg.publ.DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
3947 ddr_reg.publ.DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
3948 ddr_reg.publ.DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
3950 ddr_reg.publ.DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
3951 ddr_reg.publ.DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
3952 ddr_reg.publ.DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
3953 ddr_reg.publ.DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
3955 ddr_reg.publ.DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
3956 ddr_reg.publ.DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
3957 ddr_reg.publ.DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
3958 ddr_reg.publ.DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
3960 ddr_reg.publ.DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
3961 ddr_reg.publ.DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
3962 ddr_reg.publ.DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
3963 ddr_reg.publ.DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
3966 ddr_reg.DdrConf = *(volatile uint32_t *)SysSrv_DdrConf;
3967 ddr_reg.DdrMode = *(volatile uint32_t *)SysSrv_DdrMode;
3968 ddr_reg.ReadLatency = *(volatile uint32_t *)SysSrv_ReadLatency;
3970 EXPORT_SYMBOL(ddr_reg_save);
3972 __attribute__((aligned(4))) __sramdata uint32 ddr_reg_resume[] =
3974 #include "ddr_reg_resume.inc"
3977 int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
3979 volatile uint32_t value = 0;
3983 ddr_print("version 1.00 20130510 \n");
3985 mem_type = pPHY_Reg->DCR.b.DDRMD;
3986 ddr_speed_bin = dram_speed_bin;
3991 ddr_freq = clk_get_rate(clk_get(NULL, "ddr_pll"))/1000000;
3995 #if defined(CONFIG_ARCH_RK3188)
3996 ddr_soc_is_rk3188_plus = soc_is_rk3188plus();
3997 ddr_rk3188_dpll_is_good = ddr_get_dpll_status();
4002 die = 2; //there is two die DDR3 at least
4003 ddr_print("DDR3 Device\n");
4006 ddr_print("LPDDR2 Device\n");
4009 ddr_print("DDR2 Device\n");
4012 ddr_print("DDR Device\n");
4015 ddr_print("LPDDR Device\n");
4018 //get capability per chip, not total size, used for calculate tRFC
4019 ddr_capability_per_die = ddr_get_cap()/(ddr_get_cs()*die);
4020 ddr_print("Bus Width=%d Col=%d Bank=%d Row=%d CS=%d Total Capability=%dMB\n",
4023 (0x1<<(ddr_get_bank())), \
4026 (ddr_get_cap()>>20));
4027 ddr_adjust_config(mem_type);
4029 if(ddr_rk3188_dpll_is_good == true)
4032 value=ddr_change_freq(freq);
4034 value=ddr_change_freq(clk_get_rate(clk_get(NULL, "ddr"))/1000000);
4036 clk_set_rate(clk_get(NULL, "ddr"), 0);
4037 ddr_print("init success!!! freq=%luMHz\n", clk_get_rate(clk_get(NULL, "ddr"))/1000000);
4039 for(value=0;value<4;value++)
4041 gsr = pPHY_Reg->DATX8[value].DXGSR[0];
4042 dqstr = pPHY_Reg->DATX8[value].DXDQSTR;
4043 ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=0x%x, DGSL=%d extra clock, DGPS=%d\n", \
4044 (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), ((gsr>>13)&0xFFF), (dqstr&0x7), ((((dqstr>>12)&0x3)+1)*90));
4046 ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
4047 (pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
4048 (pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
4049 pPHY_Reg->ZQ0SR[1]&0x3,\
4050 (pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
4051 (pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
4052 (pPHY_Reg->ZQ0SR[1]>>6)&0x3);
4053 ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", pPHY_Reg->ZQ0SR[0]&0x1F, (pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
4054 ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (pPHY_Reg->ZQ0SR[0]>>15)&0x1F);
4058 EXPORT_SYMBOL(ddr_init);