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12 LLVM Atomic Instructions and Concurrency Guide
16 <li><a href="#introduction">Introduction</a></li>
17 <li><a href="#outsideatomic">Optimization outside atomic</a></li>
18 <li><a href="#atomicinst">Atomic instructions</a></li>
19 <li><a href="#ordering">Atomic orderings</a></li>
20 <li><a href="#iropt">Atomics and IR optimization</a></li>
21 <li><a href="#codegen">Atomics and Codegen</a></li>
24 <div class="doc_author">
25 <p>Written by Eli Friedman</p>
28 <!-- *********************************************************************** -->
30 <a name="introduction">Introduction</a>
32 <!-- *********************************************************************** -->
36 <p>Historically, LLVM has not had very strong support for concurrency; some
37 minimal intrinsics were provided, and <code>volatile</code> was used in some
38 cases to achieve rough semantics in the presence of concurrency. However, this
39 is changing; there are now new instructions which are well-defined in the
40 presence of threads and asynchronous signals, and the model for existing
41 instructions has been clarified in the IR.</p>
43 <p>The atomic instructions are designed specifically to provide readable IR and
44 optimized code generation for the following:</p>
46 <li>The new C++0x <code><atomic></code> header.
47 (<a href="http://www.open-std.org/jtc1/sc22/wg21/">C++0x draft available here</a>.)
48 (<a href="http://www.open-std.org/jtc1/sc22/wg14/">C1x draft available here</a>)</li>
49 <li>Proper semantics for Java-style memory, for both <code>volatile</code> and
50 regular shared variables.
51 (<a href="http://java.sun.com/docs/books/jls/third_edition/html/memory.html">Java Specification</a>)</li>
52 <li>gcc-compatible <code>__sync_*</code> builtins.
53 (<a href="http://gcc.gnu.org/onlinedocs/gcc/Atomic-Builtins.html">Description</a>)</li>
54 <li>Other scenarios with atomic semantics, including <code>static</code>
55 variables with non-trivial constructors in C++.</li>
58 <p>Atomic and volatile in the IR are orthogonal; "volatile" is the C/C++
59 volatile, which ensures that every volatile load and store happens and is
60 performed in the stated order. A couple examples: if a
61 SequentiallyConsistent store is immediately followed by another
62 SequentiallyConsistent store to the same address, the first store can
63 be erased. This transformation is not allowed for a pair of volatile
64 stores. On the other hand, a non-volatile non-atomic load can be moved
65 across a volatile load freely, but not an Acquire load.</p>
67 <p>This document is intended to provide a guide to anyone either writing a
68 frontend for LLVM or working on optimization passes for LLVM with a guide
69 for how to deal with instructions with special semantics in the presence of
70 concurrency. This is not intended to be a precise guide to the semantics;
71 the details can get extremely complicated and unreadable, and are not
72 usually necessary.</p>
76 <!-- *********************************************************************** -->
78 <a name="outsideatomic">Optimization outside atomic</a>
80 <!-- *********************************************************************** -->
84 <p>The basic <code>'load'</code> and <code>'store'</code> allow a variety of
85 optimizations, but can lead to undefined results in a concurrent environment;
86 see <a href="#o_nonatomic">NonAtomic</a>. This section specifically goes
87 into the one optimizer restriction which applies in concurrent environments,
88 which gets a bit more of an extended description because any optimization
89 dealing with stores needs to be aware of it.</p>
91 <p>From the optimizer's point of view, the rule is that if there
92 are not any instructions with atomic ordering involved, concurrency does
93 not matter, with one exception: if a variable might be visible to another
94 thread or signal handler, a store cannot be inserted along a path where it
95 might not execute otherwise. Take the following example:</p>
98 /* C code, for readability; run through clang -O2 -S -emit-llvm to get
102 for (int i = 0; i < 100; i++) {
109 <p>The following is equivalent in non-concurrent situations:</p>
115 for (int i = 0; i < 100; i++) {
123 <p>However, LLVM is not allowed to transform the former to the latter: it could
124 introduce undefined behavior if another thread can access x at the same time.
125 (This example is particularly of interest because before the concurrency model
126 was implemented, LLVM would perform this transformation.)</p>
128 <p>Note that speculative loads are allowed; a load which
129 is part of a race returns <code>undef</code>, but does not have undefined
135 <!-- *********************************************************************** -->
137 <a name="atomicinst">Atomic instructions</a>
139 <!-- *********************************************************************** -->
143 <p>For cases where simple loads and stores are not sufficient, LLVM provides
144 various atomic instructions. The exact guarantees provided depend on the
145 ordering; see <a href="#ordering">Atomic orderings</a></p>
147 <p><code>load atomic</code> and <code>store atomic</code> provide the same
148 basic functionality as non-atomic loads and stores, but provide additional
149 guarantees in situations where threads and signals are involved.</p>
151 <p><code>cmpxchg</code> and <code>atomicrmw</code> are essentially like an
152 atomic load followed by an atomic store (where the store is conditional for
153 <code>cmpxchg</code>), but no other memory operation can happen on any thread
154 between the load and store. Note that LLVM's cmpxchg does not provide quite
155 as many options as the C++0x version.</p>
157 <p>A <code>fence</code> provides Acquire and/or Release ordering which is not
158 part of another operation; it is normally used along with Monotonic memory
159 operations. A Monotonic load followed by an Acquire fence is roughly
160 equivalent to an Acquire load.</p>
162 <p>Frontends generating atomic instructions generally need to be aware of the
163 target to some degree; atomic instructions are guaranteed to be lock-free,
164 and therefore an instruction which is wider than the target natively supports
165 can be impossible to generate.</p>
169 <!-- *********************************************************************** -->
171 <a name="ordering">Atomic orderings</a>
173 <!-- *********************************************************************** -->
177 <p>In order to achieve a balance between performance and necessary guarantees,
178 there are six levels of atomicity. They are listed in order of strength;
179 each level includes all the guarantees of the previous level except for
182 <!-- ======================================================================= -->
184 <a name="o_notatomic">NotAtomic</a>
189 <p>NotAtomic is the obvious, a load or store which is not atomic. (This isn't
190 really a level of atomicity, but is listed here for comparison.) This is
191 essentially a regular load or store. If code accesses a memory location
192 from multiple threads at the same time, the resulting loads return
196 <dt>Relevant standard</dt>
197 <dd>This is intended to match shared variables in C/C++, and to be used
198 in any other context where memory access is necessary, and
199 a race is impossible.
200 <dt>Notes for frontends</dt>
201 <dd>The rule is essentially that all memory accessed with basic loads and
202 stores by multiple threads should be protected by a lock or other
203 synchronization; otherwise, you are likely to run into undefined
204 behavior. If your frontend is for a "safe" language like Java,
205 use Unordered to load and store any shared variable. Note that NotAtomic
206 volatile loads and stores are not properly atomic; do not try to use
207 them as a substitute. (Per the C/C++ standards, volatile does provide
208 some limited guarantees around asynchronous signals, but atomics are
209 generally a better solution.)
210 <dt>Notes for optimizers</dt>
211 <dd>Introducing loads to shared variables along a codepath where they would
212 not otherwise exist is allowed; introducing stores to shared variables
213 is not. See <a href="#outsideatomic">Optimization outside
215 <dt>Notes for code generation</dt>
216 <dd>The one interesting restriction here is that it is not allowed to write
217 to bytes outside of the bytes relevant to a store. This is mostly
218 relevant to unaligned stores: it is not allowed in general to convert
219 an unaligned store into two aligned stores of the same width as the
220 unaligned store. Backends are also expected to generate an i8 store
221 as an i8 store, and not an instruction which writes to surrounding
222 bytes. (If you are writing a backend for an architecture which cannot
223 satisfy these restrictions and cares about concurrency, please send an
224 email to llvmdev.)</dd>
230 <!-- ======================================================================= -->
232 <a name="o_unordered">Unordered</a>
237 <p>Unordered is the lowest level of atomicity. It essentially guarantees that
238 races produce somewhat sane results instead of having undefined behavior.
239 It also guarantees the operation to be lock-free, so it do not depend on
240 the data being part of a special atomic structure or depend on a separate
241 per-process global lock. Note that code generation will fail for
242 unsupported atomic operations; if you need such an operation, use explicit
246 <dt>Relevant standard</dt>
247 <dd>This is intended to match the Java memory model for shared
249 <dt>Notes for frontends</dt>
250 <dd>This cannot be used for synchronization, but is useful for Java and
251 other "safe" languages which need to guarantee that the generated
252 code never exhibits undefined behavior. Note that this guarantee
253 is cheap on common platforms for loads of a native width, but can
254 be expensive or unavailable for wider loads, like a 64-bit store
255 on ARM. (A frontend for Java or other "safe" languages would normally
256 split a 64-bit store on ARM into two 32-bit unordered stores.)
257 <dt>Notes for optimizers</dt>
258 <dd>In terms of the optimizer, this prohibits any transformation that
259 transforms a single load into multiple loads, transforms a store
260 into multiple stores, narrows a store, or stores a value which
261 would not be stored otherwise. Some examples of unsafe optimizations
262 are narrowing an assignment into a bitfield, rematerializing
263 a load, and turning loads and stores into a memcpy call. Reordering
264 unordered operations is safe, though, and optimizers should take
265 advantage of that because unordered operations are common in
266 languages that need them.</dd>
267 <dt>Notes for code generation</dt>
268 <dd>These operations are required to be atomic in the sense that if you
269 use unordered loads and unordered stores, a load cannot see a value
270 which was never stored. A normal load or store instruction is usually
271 sufficient, but note that an unordered load or store cannot
272 be split into multiple instructions (or an instruction which
273 does multiple memory operations, like <code>LDRD</code> on ARM).</dd>
278 <!-- ======================================================================= -->
280 <a name="o_monotonic">Monotonic</a>
285 <p>Monotonic is the weakest level of atomicity that can be used in
286 synchronization primitives, although it does not provide any general
287 synchronization. It essentially guarantees that if you take all the
288 operations affecting a specific address, a consistent ordering exists.
291 <dt>Relevant standard</dt>
292 <dd>This corresponds to the C++0x/C1x <code>memory_order_relaxed</code>;
293 see those standards for the exact definition.
294 <dt>Notes for frontends</dt>
295 <dd>If you are writing a frontend which uses this directly, use with caution.
296 The guarantees in terms of synchronization are very weak, so make
297 sure these are only used in a pattern which you know is correct.
298 Generally, these would either be used for atomic operations which
299 do not protect other memory (like an atomic counter), or along with
300 a <code>fence</code>.</dd>
301 <dt>Notes for optimizers</dt>
302 <dd>In terms of the optimizer, this can be treated as a read+write on the
303 relevant memory location (and alias analysis will take advantage of
304 that). In addition, it is legal to reorder non-atomic and Unordered
305 loads around Monotonic loads. CSE/DSE and a few other optimizations
306 are allowed, but Monotonic operations are unlikely to be used in ways
307 which would make those optimizations useful.</dd>
308 <dt>Notes for code generation</dt>
309 <dd>Code generation is essentially the same as that for unordered for loads
310 and stores. No fences is required. <code>cmpxchg</code> and
311 <code>atomicrmw</code> are required to appear as a single operation.</dd>
316 <!-- ======================================================================= -->
318 <a name="o_acquire">Acquire</a>
323 <p>Acquire provides a barrier of the sort necessary to acquire a lock to access
324 other memory with normal loads and stores.
327 <dt>Relevant standard</dt>
328 <dd>This corresponds to the C++0x/C1x <code>memory_order_acquire</code>. It
329 should also be used for C++0x/C1x <code>memory_order_consume</code>.
330 <dt>Notes for frontends</dt>
331 <dd>If you are writing a frontend which uses this directly, use with caution.
332 Acquire only provides a semantic guarantee when paired with a Release
334 <dt>Notes for optimizers</dt>
335 <dd>Optimizers not aware of atomics can treat this like a nothrow call.
336 It is also possible to move stores from before an Acquire load
337 or read-modify-write operation to after it, and move non-Acquire
338 loads from before an Acquire operation to after it.</dd>
339 <dt>Notes for code generation</dt>
340 <dd>Architectures with weak memory ordering (essentially everything relevant
341 today except x86 and SPARC) require some sort of fence to maintain
342 the Acquire semantics. The precise fences required varies widely by
343 architecture, but for a simple implementation, most architectures provide
344 a barrier which is strong enough for everything (<code>dmb</code> on ARM,
345 <code>sync</code> on PowerPC, etc.). Putting such a fence after the
346 equivalent Monotonic operation is sufficient to maintain Acquire
347 semantics for a memory operation.</dd>
352 <!-- ======================================================================= -->
354 <a name="o_acquire">Release</a>
359 <p>Release is similar to Acquire, but with a barrier of the sort necessary to
363 <dt>Relevant standard</dt>
364 <dd>This corresponds to the C++0x/C1x <code>memory_order_release</code>.</dd>
365 <dt>Notes for frontends</dt>
366 <dd>If you are writing a frontend which uses this directly, use with caution.
367 Release only provides a semantic guarantee when paired with a Acquire
369 <dt>Notes for optimizers</dt>
370 <dd>Optimizers not aware of atomics can treat this like a nothrow call.
371 It is also possible to move loads from after a Release store
372 or read-modify-write operation to before it, and move non-Release
373 stores from after an Release operation to before it.</dd>
374 <dt>Notes for code generation</dt>
375 <dd>See the section on Acquire; a fence before the relevant operation is
376 usually sufficient for Release. Note that a store-store fence is not
377 sufficient to implement Release semantics; store-store fences are
378 generally not exposed to IR because they are extremely difficult to
384 <!-- ======================================================================= -->
386 <a name="o_acqrel">AcquireRelease</a>
391 <p>AcquireRelease (<code>acq_rel</code> in IR) provides both an Acquire and a
392 Release barrier (for fences and operations which both read and write memory).
395 <dt>Relevant standard</dt>
396 <dd>This corresponds to the C++0x/C1x <code>memory_order_acq_rel</code>.
397 <dt>Notes for frontends</dt>
398 <dd>If you are writing a frontend which uses this directly, use with caution.
399 Acquire only provides a semantic guarantee when paired with a Release
400 operation, and vice versa.</dd>
401 <dt>Notes for optimizers</dt>
402 <dd>In general, optimizers should treat this like a nothrow call; the
403 the possible optimizations are usually not interesting.</dd>
404 <dt>Notes for code generation</dt>
405 <dd>This operation has Acquire and Release semantics; see the sections on
406 Acquire and Release.</dd>
411 <!-- ======================================================================= -->
413 <a name="o_seqcst">SequentiallyConsistent</a>
418 <p>SequentiallyConsistent (<code>seq_cst</code> in IR) provides
419 Acquire semantics for loads and Release semantics for
420 stores. Additionally, it guarantees that a total ordering exists
421 between all SequentiallyConsistent operations.
424 <dt>Relevant standard</dt>
425 <dd>This corresponds to the C++0x/C1x <code>memory_order_seq_cst</code>,
426 Java volatile, and the gcc-compatible <code>__sync_*</code> builtins
427 which do not specify otherwise.
428 <dt>Notes for frontends</dt>
429 <dd>If a frontend is exposing atomic operations, these are much easier to
430 reason about for the programmer than other kinds of operations, and using
431 them is generally a practical performance tradeoff.</dd>
432 <dt>Notes for optimizers</dt>
433 <dd>Optimizers not aware of atomics can treat this like a nothrow call.
434 For SequentiallyConsistent loads and stores, the same reorderings are
435 allowed as for Acquire loads and Release stores, except that
436 SequentiallyConsistent operations may not be reordered.</dd>
437 <dt>Notes for code generation</dt>
438 <dd>SequentiallyConsistent loads minimally require the same barriers
439 as Acquire operations and SequeuentiallyConsistent stores require
440 Release barriers. Additionally, the code generator must enforce
441 ordering between SequeuentiallyConsistent stores followed by
442 SequeuentiallyConsistent loads. This is usually done by emitting
443 either a full fence before the loads or a full fence after the
444 stores; which is preferred varies by architecture.</dd>
451 <!-- *********************************************************************** -->
453 <a name="iropt">Atomics and IR optimization</a>
455 <!-- *********************************************************************** -->
459 <p>Predicates for optimizer writers to query:
461 <li>isSimple(): A load or store which is not volatile or atomic. This is
462 what, for example, memcpyopt would check for operations it might
464 <li>isUnordered(): A load or store which is not volatile and at most
465 Unordered. This would be checked, for example, by LICM before hoisting
467 <li>mayReadFromMemory()/mayWriteToMemory(): Existing predicate, but note
468 that they return true for any operation which is volatile or at least
470 <li>Alias analysis: Note that AA will return ModRef for anything Acquire or
471 Release, and for the address accessed by any Monotonic operation.</li>
474 <p>To support optimizing around atomic operations, make sure you are using
475 the right predicates; everything should work if that is done. If your
476 pass should optimize some atomic operations (Unordered operations in
477 particular), make sure it doesn't replace an atomic load or store with
478 a non-atomic operation.</p>
480 <p>Some examples of how optimizations interact with various kinds of atomic
483 <li>memcpyopt: An atomic operation cannot be optimized into part of a
484 memcpy/memset, including unordered loads/stores. It can pull operations
485 across some atomic operations.
486 <li>LICM: Unordered loads/stores can be moved out of a loop. It just treats
487 monotonic operations like a read+write to a memory location, and anything
488 stricter than that like a nothrow call.
489 <li>DSE: Unordered stores can be DSE'ed like normal stores. Monotonic stores
490 can be DSE'ed in some cases, but it's tricky to reason about, and not
491 especially important.
492 <li>Folding a load: Any atomic load from a constant global can be
493 constant-folded, because it cannot be observed. Similar reasoning allows
494 scalarrepl with atomic loads and stores.
499 <!-- *********************************************************************** -->
501 <a name="codegen">Atomics and Codegen</a>
503 <!-- *********************************************************************** -->
507 <p>Atomic operations are represented in the SelectionDAG with
508 <code>ATOMIC_*</code> opcodes. On architectures which use barrier
509 instructions for all atomic ordering (like ARM), appropriate fences are
510 split out as the DAG is built.</p>
512 <p>The MachineMemOperand for all atomic operations is currently marked as
513 volatile; this is not correct in the IR sense of volatile, but CodeGen
514 handles anything marked volatile very conservatively. This should get
515 fixed at some point.</p>
517 <p>Common architectures have some way of representing at least a pointer-sized
518 lock-free <code>cmpxchg</code>; such an operation can be used to implement
519 all the other atomic operations which can be represented in IR up to that
520 size. Backends are expected to implement all those operations, but not
521 operations which cannot be implemented in a lock-free manner. It is
522 expected that backends will give an error when given an operation which
523 cannot be implemented. (The LLVM code generator is not very helpful here
524 at the moment, but hopefully that will change.)</p>
526 <p>The implementation of atomics on LL/SC architectures (like ARM) is currently
527 a bit of a mess; there is a lot of copy-pasted code across targets, and
528 the representation is relatively unsuited to optimization (it would be nice
529 to be able to optimize loops involving cmpxchg etc.).</p>
531 <p>On x86, all atomic loads generate a <code>MOV</code>.
532 SequentiallyConsistent stores generate an <code>XCHG</code>, other stores
533 generate a <code>MOV</code>. SequentiallyConsistent fences generate an
534 <code>MFENCE</code>, other fences do not cause any code to be generated.
535 cmpxchg uses the <code>LOCK CMPXCHG</code> instruction.
536 <code>atomicrmw xchg</code> uses <code>XCHG</code>,
537 <code>atomicrmw add</code> and <code>atomicrmw sub</code> use
538 <code>XADD</code>, and all other <code>atomicrmw</code> operations generate
539 a loop with <code>LOCK CMPXCHG</code>. Depending on the users of the
540 result, some <code>atomicrmw</code> operations can be translated into
541 operations like <code>LOCK AND</code>, but that does not work in
544 <p>On ARM, MIPS, and many other RISC architectures, Acquire, Release, and
545 SequentiallyConsistent semantics require barrier instructions
546 for every such operation. Loads and stores generate normal instructions.
547 <code>cmpxchg</code> and <code>atomicrmw</code> can be represented using
548 a loop with LL/SC-style instructions which take some sort of exclusive
549 lock on a cache line (<code>LDREX</code> and <code>STREX</code> on
550 ARM, etc.). At the moment, the IR does not provide any way to represent a
551 weak <code>cmpxchg</code> which would not require a loop.</p>
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