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5 <title>The LLVM Target-Independent Code Generator</title>
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10 <div class="doc_title">
11 The LLVM Target-Independent Code Generator
15 <li><a href="#introduction">Introduction</a>
17 <li><a href="#required">Required components in the code generator</a></li>
18 <li><a href="#high-level-design">The high-level design of the code generator</a></li>
19 <li><a href="#tablegen">Using TableGen for target description</a></li>
22 <li><a href="#targetdesc">Target description classes</a>
24 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
25 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
26 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
27 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
28 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
29 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
30 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
33 <li><a href="#codegendesc">Machine code description classes</a>
35 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
38 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
40 <li><a href="#instselect">Instruction Selection</a>
42 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
43 <li><a href="#selectiondag_process">SelectionDAG Code Generation
45 <li><a href="#selectiondag_build">Initial SelectionDAG
47 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
48 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
50 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
51 <li><a href="#selectiondag_future">Future directions for the
56 <li><a href="#targetimpls">Target description implementations</a>
58 <li><a href="#x86">The X86 backend</a></li>
64 <div class="doc_author">
65 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a></p>
68 <div class="doc_warning">
69 <p>Warning: This is a work in progress.</p>
72 <!-- *********************************************************************** -->
73 <div class="doc_section">
74 <a name="introduction">Introduction</a>
76 <!-- *********************************************************************** -->
78 <div class="doc_text">
80 <p>The LLVM target-independent code generator is a framework that provides a
81 suite of reusable components for translating the LLVM internal representation to
82 the machine code for a specified target -- either in assembly form (suitable for
83 a static compiler) or in binary machine code format (usable for a JIT compiler).
84 The LLVM target-independent code generator consists of five main components:</p>
87 <li><a href="#targetdesc">Abstract target description</a> interfaces which
88 capture important properties about various aspects of the machine, independently
89 of how they will be used. These interfaces are defined in
90 <tt>include/llvm/Target/</tt>.</li>
92 <li>Classes used to represent the <a href="#codegendesc">machine code</a> being
93 generated for a target. These classes are intended to be abstract enough to
94 represent the machine code for <i>any</i> target machine. These classes are
95 defined in <tt>include/llvm/CodeGen/</tt>.</li>
97 <li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
98 various phases of native code generation (register allocation, scheduling, stack
99 frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
101 <li><a href="#targetimpls">Implementations of the abstract target description
102 interfaces</a> for particular targets. These machine descriptions make use of
103 the components provided by LLVM, and can optionally provide custom
104 target-specific passes, to build complete code generators for a specific target.
105 Target descriptions live in <tt>lib/Target/</tt>.</li>
107 <li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
108 completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
109 interface for target-specific issues. The code for the target-independent
110 JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
115 Depending on which part of the code generator you are interested in working on,
116 different pieces of this will be useful to you. In any case, you should be
117 familiar with the <a href="#targetdesc">target description</a> and <a
118 href="#codegendesc">machine code representation</a> classes. If you want to add
119 a backend for a new target, you will need to <a href="#targetimpls">implement the
120 target description</a> classes for your new target and understand the <a
121 href="LangRef.html">LLVM code representation</a>. If you are interested in
122 implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
123 should only depend on the target-description and machine code representation
124 classes, ensuring that it is portable.
129 <!-- ======================================================================= -->
130 <div class="doc_subsection">
131 <a name="required">Required components in the code generator</a>
134 <div class="doc_text">
136 <p>The two pieces of the LLVM code generator are the high-level interface to the
137 code generator and the set of reusable components that can be used to build
138 target-specific backends. The two most important interfaces (<a
139 href="#targetmachine"><tt>TargetMachine</tt></a> and <a
140 href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
141 required to be defined for a backend to fit into the LLVM system, but the others
142 must be defined if the reusable code generator components are going to be
145 <p>This design has two important implications. The first is that LLVM can
146 support completely non-traditional code generation targets. For example, the C
147 backend does not require register allocation, instruction selection, or any of
148 the other standard components provided by the system. As such, it only
149 implements these two interfaces, and does its own thing. Another example of a
150 code generator like this is a (purely hypothetical) backend that converts LLVM
151 to the GCC RTL form and uses GCC to emit machine code for a target.</p>
153 <p>This design also implies that it is possible to design and
154 implement radically different code generators in the LLVM system that do not
155 make use of any of the built-in components. Doing so is not recommended at all,
156 but could be required for radically different targets that do not fit into the
157 LLVM machine description model: programmable FPGAs for example.</p>
159 <p><b>Important Note:</b> For historical reasons, the LLVM SparcV9 code
160 generator uses almost entirely different code paths than described in this
161 document. For this reason, there are some deprecated interfaces (such as
162 <tt>TargetRegInfo</tt> and <tt>TargetSchedInfo</tt>), which are only used by the
163 V9 backend and should not be used by any other targets. Also, all code in the
164 <tt>lib/Target/SparcV9</tt> directory and subdirectories should be considered
165 deprecated, and should not be used as the basis for future code generator work.
166 The SparcV9 backend is slowly being merged into the rest of the
167 target-independent code generators, but this is a low-priority process with no
168 predictable completion date.</p>
172 <!-- ======================================================================= -->
173 <div class="doc_subsection">
174 <a name="high-level-design">The high-level design of the code generator</a>
177 <div class="doc_text">
179 <p>The LLVM target-independent code generator is designed to support efficient and
180 quality code generation for standard register-based microprocessors. Code
181 generation in this model is divided into the following stages:</p>
184 <li><b><a href="#instselect">Instruction Selection</a></b> - Determining an
185 efficient implementation of the input LLVM code in the target instruction set.
186 This stage produces the initial code for the program in the target instruction
187 set, then makes use of virtual registers in SSA form and physical registers that
188 represent any required register assignments due to target constraints or calling
191 <li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
192 optional stage consists of a series of machine-code optimizations that
193 operate on the SSA-form produced by the instruction selector. Optimizations
194 like modulo-scheduling, normal scheduling, or peephole optimization work here.
197 <li><b><a name="#regalloc">Register Allocation</a></b> - The
198 target code is transformed from an infinite virtual register file in SSA form
199 to the concrete register file used by the target. This phase introduces spill
200 code and eliminates all virtual register references from the program.</li>
202 <li><b><a name="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
203 machine code has been generated for the function and the amount of stack space
204 required is known (used for LLVM alloca's and spill slots), the prolog and
205 epilog code for the function can be inserted and "abstract stack location
206 references" can be eliminated. This stage is responsible for implementing
207 optimizations like frame-pointer elimination and stack packing.</li>
209 <li><b><a name="latemco">Late Machine Code Optimizations</a></b> - Optimizations
210 that operate on "final" machine code can go here, such as spill code scheduling
211 and peephole optimizations.</li>
213 <li><b><a name="codemission">Code Emission</a></b> - The final stage actually
214 puts out the code for the current function, either in the target assembler
215 format or in machine code.</li>
220 The code generator is based on the assumption that the instruction selector will
221 use an optimal pattern matching selector to create high-quality sequences of
222 native instructions. Alternative code generator designs based on pattern
224 aggressive iterative peephole optimization are much slower. This design
225 permits efficient compilation (important for JIT environments) and
226 aggressive optimization (used when generating code offline) by allowing
227 components of varying levels of sophistication to be used for any step of
231 In addition to these stages, target implementations can insert arbitrary
232 target-specific passes into the flow. For example, the X86 target uses a
233 special pass to handle the 80x87 floating point stack architecture. Other
234 targets with unusual requirements can be supported with custom passes as needed.
240 <!-- ======================================================================= -->
241 <div class="doc_subsection">
242 <a name="tablegen">Using TableGen for target description</a>
245 <div class="doc_text">
247 <p>The target description classes require a detailed description of the target
248 architecture. These target descriptions often have a large amount of common
249 information (e.g., an <tt>add</tt> instruction is almost identical to a
250 <tt>sub</tt> instruction).
251 In order to allow the maximum amount of commonality to be factored out, the LLVM
252 code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
253 describe big chunks of the target machine, which allows the use of
254 domain-specific and target-specific abstractions to reduce the amount of
260 <!-- *********************************************************************** -->
261 <div class="doc_section">
262 <a name="targetdesc">Target description classes</a>
264 <!-- *********************************************************************** -->
266 <div class="doc_text">
268 <p>The LLVM target description classes (which are located in the
269 <tt>include/llvm/Target</tt> directory) provide an abstract description of the
270 target machine; independent of any particular client. These classes are
271 designed to capture the <i>abstract</i> properties of the target (such as the
272 instructions and registers it has), and do not incorporate any particular pieces
273 of code generation algorithms. These interfaces do not take interference graphs
274 as inputs or other algorithm-specific data structures.</p>
276 <p>All of the target description classes (except the <tt><a
277 href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
278 the concrete target implementation, and have virtual methods implemented. To
279 get to these implementations, the <tt><a
280 href="#targetmachine">TargetMachine</a></tt> class provides accessors that
281 should be implemented by the target.</p>
285 <!-- ======================================================================= -->
286 <div class="doc_subsection">
287 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
290 <div class="doc_text">
292 <p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
293 access the target-specific implementations of the various target description
294 classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
295 <tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
296 designed to be specialized by
297 a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
298 implements the various virtual methods. The only required target description
299 class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
300 code generator components are to be used, the other interfaces should be
301 implemented as well.</p>
306 <!-- ======================================================================= -->
307 <div class="doc_subsection">
308 <a name="targetdata">The <tt>TargetData</tt> class</a>
311 <div class="doc_text">
313 <p>The <tt>TargetData</tt> class is the only required target description class,
314 and it is the only class that is not extensible. You cannot derived a new
315 class from it. <tt>TargetData</tt> specifies information about how the target
316 lays out memory for structures, the alignment requirements for various data
317 types, the size of pointers in the target, and whether the target is
318 little-endian or big-endian.</p>
322 <!-- ======================================================================= -->
323 <div class="doc_subsection">
324 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
327 <div class="doc_text">
329 <p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
330 selectors primarily to describe how LLVM code should be lowered to SelectionDAG
331 operations. Among other things, this class indicates:
332 <ul><li>an initial register class to use for various ValueTypes,</li>
333 <li>which operations are natively supported by the target machine,</li>
334 <li>the return type of setcc operations, and</li>
335 <li>the type to use for shift amounts, etc</li>.
344 <!-- ======================================================================= -->
345 <div class="doc_subsection">
346 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
349 <div class="doc_text">
351 <p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
352 <tt>TargetRegisterInfo</tt>) is used to describe the register file of the
353 target and any interactions between the registers.</p>
355 <p>Registers in the code generator are represented in the code generator by
356 unsigned numbers. Physical registers (those that actually exist in the target
357 description) are unique small numbers, and virtual registers are generally
360 <p>Each register in the processor description has an associated
361 <tt>TargetRegisterDesc</tt> entry, which provides a textual name for the register
362 (used for assembly output and debugging dumps) and a set of aliases (used to
363 indicate that one register overlaps with another).
366 <p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
367 exposes a set of processor specific register classes (instances of the
368 <tt>TargetRegisterClass</tt> class). Each register class contains sets of
369 registers that have the same properties (for example, they are all 32-bit
370 integer registers). Each SSA virtual register created by the instruction
371 selector has an associated register class. When the register allocator runs, it
372 replaces virtual registers with a physical register in the set.</p>
375 The target-specific implementations of these classes is auto-generated from a <a
376 href="TableGenFundamentals.html">TableGen</a> description of the register file.
381 <!-- ======================================================================= -->
382 <div class="doc_subsection">
383 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
386 <div class="doc_text">
387 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
388 instructions supported by the target. It is essentially an array of
389 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
390 instruction the target supports. Descriptors define things like the mnemonic
391 for the opcode, the number of operands, the list of implicit register uses
392 and defs, whether the instruction has certain target-independent properties
393 (accesses memory, is commutable, etc), and holds any target-specific flags.</p>
396 <!-- ======================================================================= -->
397 <div class="doc_subsection">
398 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
401 <div class="doc_text">
402 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
403 stack frame layout of the target. It holds the direction of stack growth,
404 the known stack alignment on entry to each function, and the offset to the
405 locals area. The offset to the local area is the offset from the stack
406 pointer on function entry to the first location where function data (local
407 variables, spill locations) can be stored.</p>
409 <!-- ======================================================================= -->
410 <div class="doc_subsection">
411 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
414 <!-- *********************************************************************** -->
415 <div class="doc_section">
416 <a name="codegendesc">Machine code description classes</a>
418 <!-- *********************************************************************** -->
420 <div class="doc_text">
423 At the high-level, LLVM code is translated to a machine specific representation
424 formed out of MachineFunction, MachineBasicBlock, and <a
425 href="#machineinstr"><tt>MachineInstr</tt></a> instances
426 (defined in include/llvm/CodeGen). This representation is completely target
427 agnostic, representing instructions in their most abstract form: an opcode and a
428 series of operands. This representation is designed to support both SSA
429 representation for machine code, as well as a register allocated, non-SSA form.
434 <!-- ======================================================================= -->
435 <div class="doc_subsection">
436 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
439 <div class="doc_text">
441 <p>Target machine instructions are represented as instances of the
442 <tt>MachineInstr</tt> class. This class is an extremely abstract way of
443 representing machine instructions. In particular, it only keeps track of
444 an opcode number and a set of operands.</p>
446 <p>The opcode number is a simple unsigned number that only has meaning to a
447 specific backend. All of the instructions for a target should be defined in
448 the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
449 are auto-generated from this description. The <tt>MachineInstr</tt> class does
450 not have any information about how to interpret the instruction (i.e., what the
451 semantics of the instruction are): for that you must refer to the
452 <tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
454 <p>The operands of a machine instruction can be of several different types:
455 they can be a register reference, constant integer, basic block reference, etc.
456 In addition, a machine operand should be marked as a def or a use of the value
457 (though only registers are allowed to be defs).</p>
459 <p>By convention, the LLVM code generator orders instruction operands so that
460 all register definitions come before the register uses, even on architectures
461 that are normally printed in other orders. For example, the SPARC add
462 instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
463 and stores the result into the "%i3" register. In the LLVM code generator,
464 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
467 <p>Keeping destination (definition) operands at the beginning of the operand
468 list has several advantages. In particular, the debugging printer will print
469 the instruction like this:</p>
475 <p>If the first operand is a def, and it is also easier to <a
476 href="#buildmi">create instructions</a> whose only def is the first
481 <!-- _______________________________________________________________________ -->
482 <div class="doc_subsubsection">
483 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
486 <div class="doc_text">
488 <p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
489 located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
490 <tt>BuildMI</tt> functions make it easy to build arbitrary machine
491 instructions. Usage of the <tt>BuildMI</tt> functions look like this:
495 // Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
496 // instruction. The '1' specifies how many operands will be added.
497 MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
499 // Create the same instr, but insert it at the end of a basic block.
500 MachineBasicBlock &MBB = ...
501 BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
503 // Create the same instr, but insert it before a specified iterator point.
504 MachineBasicBlock::iterator MBBI = ...
505 BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
507 // Create a 'cmp Reg, 0' instruction, no destination reg.
508 MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
509 // Create an 'sahf' instruction which takes no operands and stores nothing.
510 MI = BuildMI(X86::SAHF, 0);
512 // Create a self looping branch instruction.
513 BuildMI(MBB, X86::JNE, 1).addMBB(&MBB);
517 The key thing to remember with the <tt>BuildMI</tt> functions is that you have
518 to specify the number of operands that the machine instruction will take. This
519 allows for efficient memory allocation. You also need to specify if operands
520 default to be uses of values, not definitions. If you need to add a definition
521 operand (other than the optional destination register), you must explicitly
527 <!-- _______________________________________________________________________ -->
528 <div class="doc_subsubsection">
529 <a name="fixedregs">Fixed (preassigned) registers</a>
532 <div class="doc_text">
534 <p>One important issue that the code generator needs to be aware of is the
535 presence of fixed registers. In particular, there are often places in the
536 instruction stream where the register allocator <em>must</em> arrange for a
537 particular value to be in a particular register. This can occur due to
538 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
539 with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
540 conventions. In any case, the instruction selector should emit code that
541 copies a virtual register into or out of a physical register when needed.</p>
543 <p>For example, consider this simple LLVM example:</p>
546 int %test(int %X, int %Y) {
552 <p>The X86 instruction selector produces this machine code for the div
554 "<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
558 %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
559 %reg1027 = sar %reg1024, 31
560 %EDX = mov %reg1027 ;; Sign extend X into EDX
561 idiv %reg1025 ;; Divide by Y (in reg1025)
562 %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
565 %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
569 <p>By the end of code generation, the register allocator has coalesced
570 the registers and deleted the resultant identity moves, producing the
574 ;; X is in EAX, Y is in ECX
581 <p>This approach is extremely general (if it can handle the X86 architecture,
582 it can handle anything!) and allows all of the target specific
583 knowledge about the instruction stream to be isolated in the instruction
584 selector. Note that physical registers should have a short lifetime for good
585 code generation, and all physical registers are assumed dead on entry and
586 exit of basic blocks (before register allocation). Thus if you need a value
587 to be live across basic block boundaries, it <em>must</em> live in a virtual
592 <!-- _______________________________________________________________________ -->
593 <div class="doc_subsubsection">
594 <a name="ssa">Machine code SSA form</a>
597 <div class="doc_text">
599 <p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
600 are maintained in SSA-form until register allocation happens. For the most
601 part, this is trivially simple since LLVM is already in SSA form: LLVM PHI nodes
602 become machine code PHI nodes, and virtual registers are only allowed to have a
603 single definition.</p>
605 <p>After register allocation, machine code is no longer in SSA-form, as there
606 are no virtual registers left in the code.</p>
610 <!-- *********************************************************************** -->
611 <div class="doc_section">
612 <a name="codegenalgs">Target-independent code generation algorithms</a>
614 <!-- *********************************************************************** -->
616 <div class="doc_text">
618 <p>This section documents the phases described in the <a
619 href="high-level-design">high-level design of the code generator</a>. It
620 explains how they work and some of the rationale behind their design.</p>
624 <!-- ======================================================================= -->
625 <div class="doc_subsection">
626 <a name="instselect">Instruction Selection</a>
629 <div class="doc_text">
631 Instruction Selection is the process of translating LLVM code presented to the
632 code generator into target-specific machine instructions. There are several
633 well-known ways to do this in the literature. In LLVM there are two main forms:
634 the old-style 'simple' instruction selector (which effectively peephole selects
635 each LLVM instruction into a series of machine instructions), and the new
636 SelectionDAG based instruction selector.
639 <p>The 'simple' instruction selectors are tedious to write, require a lot of
640 boiler plate code, and are difficult to get correct. Additionally, any
641 optimizations written for a simple instruction selector cannot be used by other
642 targets. For this reason, LLVM is moving to a new SelectionDAG based
643 instruction selector, which is described in this section. If you are starting a
644 new port, we recommend that you write the instruction selector using the
645 SelectionDAG infrastructure.</p>
647 <p>In time, most of the target-specific code for instruction selection will be
648 auto-generated from the target description (<tt>*.td</tt>) files. For now,
649 however, the <a href="#selectiondag_select">Select Phase</a> must still be
653 <!-- _______________________________________________________________________ -->
654 <div class="doc_subsubsection">
655 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
658 <div class="doc_text">
661 The SelectionDAG provides an abstraction for code representation in a way that
662 is amenable to instruction selection using automatic techniques
663 (e.g. dynamic-programming based optimal pattern matching selectors), It is also
664 well suited to other phases of code generation; in particular, instruction scheduling. Additionally, the SelectionDAG provides a host representation where a
665 large variety of very-low-level (but target-independent)
666 <a href="#selectiondag_optimize">optimizations</a> may be
667 performed: ones which require extensive information about the instructions
668 efficiently supported by the target.
672 The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
673 <tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
674 operation code (Opcode) that indicates what operation the node performs.
675 The various operation node types are described at the top of the
676 <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file. Depending on the
677 operation, nodes may contain additional information (e.g. the condition code
678 for a SETCC node) contained in a derived class.</p>
680 <p>Although most operations define a single value, each node in the graph may
681 define multiple values. For example, a combined div/rem operation will define
682 both the dividend and the remainder. Many other situations require multiple
683 values as well. Each node also has some number of operands, which are edges
684 to the node defining the used value. Because nodes may define multiple values,
685 edges are represented by instances of the <tt>SDOperand</tt> class, which is
686 a <SDNode, unsigned> pair, indicating the node and result
687 value being used, respectively. Each value produced by an SDNode has an
688 associated MVT::ValueType, indicating what type the value is.
692 SelectionDAGs contain two different kinds of values: those that represent data
693 flow and those that represent control flow dependencies. Data values are simple
694 edges with an integer or floating point value type. Control edges are
695 represented as "chain" edges which are of type MVT::Other. These edges provide
696 an ordering between nodes that have side effects (such as
697 loads/stores/calls/return/etc). All nodes that have side effects should take a
698 token chain as input and produce a new one as output. By convention, token
699 chain inputs are always operand #0, and chain results are always the last
700 value produced by an operation.</p>
703 A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
704 always a marker node with an Opcode of ISD::EntryToken. The Root node is the
705 final side-effecting node in the token chain. For example, in a single basic
706 block function, this would be the return node.
710 One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal"
711 DAG. A legal DAG for a target is one that only uses supported operations and
712 supported types. On PowerPC, for example, a DAG with any values of i1, i8, i16,
713 or i64 type would be illegal. The <a href="#selectiondag_legalize">legalize</a>
714 phase is responsible for turning an illegal DAG into a legal DAG.
718 <!-- _______________________________________________________________________ -->
719 <div class="doc_subsubsection">
720 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
723 <div class="doc_text">
726 SelectionDAG-based instruction selection consists of the following steps:
730 <li><a href="#selectiondag_build">Build initial DAG</a> - This stage performs
731 a simple translation from the input LLVM code to an illegal SelectionDAG.
733 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
734 performs simple optimizations on the SelectionDAG to simplify it and
735 recognize meta instructions (like rotates and div/rem pairs) for
736 targets that support these meta operations. This makes the resultant code
737 more efficient and the 'select instructions from DAG' phase (below) simpler.
739 <li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
740 converts the illegal SelectionDAG to a legal SelectionDAG, by eliminating
741 unsupported operations and data types.</li>
742 <li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
743 second run of the SelectionDAG optimized the newly legalized DAG, to
744 eliminate inefficiencies introduced by legalization.</li>
745 <li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
746 the target instruction selector matches the DAG operations to target
747 instructions, emitting them and building the MachineFunction being
751 <p>After all of these steps are complete, the SelectionDAG is destroyed and the
752 rest of the code generation passes are run.</p>
756 <!-- _______________________________________________________________________ -->
757 <div class="doc_subsubsection">
758 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
761 <div class="doc_text">
764 The initial SelectionDAG is naively peephole expanded from the LLVM input by
765 the <tt>SelectionDAGLowering</tt> class in the SelectionDAGISel.cpp file. The
766 intent of this pass is to expose as much low-level, target-specific details
767 to the SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM
768 add turns into an SDNode add while a geteelementptr is expanded into the obvious
769 arithmetic). This pass requires target-specific hooks to lower calls and
770 returns, varargs, etc. For these features, the TargetLowering interface is
776 <!-- _______________________________________________________________________ -->
777 <div class="doc_subsubsection">
778 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
781 <div class="doc_text">
783 <p>The Legalize phase is in charge of converting a DAG to only use the types and
784 operations that are natively supported by the target. This involves two major
788 <li><p>Convert values of unsupported types to values of supported types.</p>
789 <p>There are two main ways of doing this: promoting a small type to a larger
790 type (e.g. f32 -> f64, or i16 -> i32), and breaking up large
792 to smaller ones (e.g. implementing i64 with i32 operations where
793 possible). Type conversions can insert sign and zero extensions as
794 needed to make sure that the final code has the same behavior as the
798 <li><p>Eliminate operations that are not supported by the target in a supported
800 <p>Targets often have wierd constraints, such as not supporting every
801 operation on every supported datatype (e.g. X86 does not support byte
802 conditional moves). Legalize takes care of either open-coding another
803 sequence of operations to emulate the operation (this is known as
804 expansion), promoting to a larger type that supports the operation
805 (promotion), or using a target-specific hook to implement the
811 Instead of using a Legalize pass, we could require that every target-specific
812 <a href="#selectiondag_optimize">selector</a> supports and expands every
813 operator and type even if they are not supported and may require many
814 instructions to implement (in fact, this is the approach taken by the
815 "simple" selectors). However, using a Legalize pass allows all of the
816 cannonicalization patterns to be shared across targets which makes it very
817 easy to optimize the cannonicalized code because it is still in the form of
823 <!-- _______________________________________________________________________ -->
824 <div class="doc_subsubsection">
825 <a name="selectiondag_optimize">SelectionDAG Optimization Phase</a>
828 <div class="doc_text">
831 The SelectionDAG optimization phase is run twice for code generation: once
832 immediately after the DAG is built and once after legalization. The first run
833 of the pass allows the initial code to be cleaned up (e.g. performing
834 optimizations that depend on knowing that the operators have restricted type
835 inputs). The second run of the pass cleans up the messy code generated by the
836 Legalize pass, allowing Legalize to be very simple since it can ignore many
841 One important class of optimizations that this pass will do in the future is
842 optimizing inserted sign and zero extension instructions. Here are some good
843 papers on the subject:</p>
846 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
847 integer arithmetic</a>"<br>
848 Kevin Redwine and Norman Ramsey<br>
849 International Conference on Compiler Construction (CC) 2004
854 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
855 sign extension elimination</a>"<br>
856 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
857 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
863 <!-- _______________________________________________________________________ -->
864 <div class="doc_subsubsection">
865 <a name="selectiondag_select">SelectionDAG Select Phase</a>
868 <div class="doc_text">
870 <p>The Select phase is the bulk of the target-specific code for instruction
871 selection. This phase takes a legal SelectionDAG as input, and does simple
872 pattern matching on the DAG to generate code. In time, the Select phase will
873 be automatically generated from the target's InstrInfo.td file, which is why we
874 want to make the Select phase as simple and mechanical as possible.</p>
878 <!-- _______________________________________________________________________ -->
879 <div class="doc_subsubsection">
880 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
883 <div class="doc_text">
886 <li>Optional whole-function selection.</li>
887 <li>Select is a graph translation phase.</li>
888 <li>Place the machine instructions resulting from Select according to register
889 pressure or a schedule.</li>
890 <li>DAG Scheduling.</li>
891 <li>Auto-generate the Select phase from the target description (*.td) files.
897 <!-- ======================================================================= -->
898 <div class="doc_subsection">
899 <a name="ssamco">SSA-based Machine Code Optimizations</a>
901 <div class="doc_text"><p>To Be Written</p></div>
902 <!-- ======================================================================= -->
903 <div class="doc_subsection">
904 <a name="regalloc">Register Allocation</a>
906 <div class="doc_text"><p>To Be Written</p></div>
907 <!-- ======================================================================= -->
908 <div class="doc_subsection">
909 <a name="proepicode">Prolog/Epilog Code Insertion</a>
911 <div class="doc_text"><p>To Be Written</p></div>
912 <!-- ======================================================================= -->
913 <div class="doc_subsection">
914 <a name="latemco">Late Machine Code Optimizations</a>
916 <div class="doc_text"><p>To Be Written</p></div>
917 <!-- ======================================================================= -->
918 <div class="doc_subsection">
919 <a name="codemission">Code Emission</a>
922 <!-- *********************************************************************** -->
923 <div class="doc_section">
924 <a name="targetimpls">Target description implementations</a>
926 <!-- *********************************************************************** -->
928 <div class="doc_text">
930 <p>This section of the document explains features or design decisions that
931 are specific to the code generator for a particular target.</p>
936 <!-- ======================================================================= -->
937 <div class="doc_subsection">
938 <a name="x86">The X86 backend</a>
941 <div class="doc_text">
944 The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
945 code generator currently targets a generic P6-like processor. As such, it
946 produces a few P6-and-above instructions (like conditional moves), but it does
947 not make use of newer features like MMX or SSE. In the future, the X86 backend
948 will have sub-target support added for specific processor families and
953 <!-- _______________________________________________________________________ -->
954 <div class="doc_subsubsection">
955 <a name="x86_tt">X86 Target Triples Supported</a>
958 <div class="doc_text">
960 The following are the known target triples that are supported by the X86
961 backend. This is not an exhaustive list, but it would be useful to add those
966 <li><b>i686-pc-linux-gnu</b> - Linux</li>
967 <li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
968 <li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
969 <li><b>i686-pc-mingw32</b> - MingW on Win32</li>
970 <li><b>i686-apple-darwin*</b> - Apple Darwin</li>
975 <!-- _______________________________________________________________________ -->
976 <div class="doc_subsubsection">
977 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
980 <div class="doc_text">
982 <p>The x86 has a very flexible way of accessing memory. It is capable of
983 forming memory addresses of the following expression directly in integer
984 instructions (which use ModR/M addressing):</p>
987 Base+[1,2,4,8]*IndexReg+Disp32
990 <p>In order to represent this, LLVM tracks no less than 4 operands for each
991 memory operand of this form. This means that the "load" form of 'mov' has the
992 following <tt>MachineOperand</tt>s in this order:</p>
996 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
997 OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1000 <p>Stores, and all other instructions, treat the four memory operands in the
1001 same way, in the same order.</p>
1005 <!-- _______________________________________________________________________ -->
1006 <div class="doc_subsubsection">
1007 <a name="x86_names">Instruction naming</a>
1010 <div class="doc_text">
1013 An instruction name consists of the base name, a default operand size, and a
1014 a character per operand with an optional special size. For example:</p>
1017 <tt>ADD8rr</tt> -> add, 8-bit register, 8-bit register<br>
1018 <tt>IMUL16rmi</tt> -> imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1019 <tt>IMUL16rmi8</tt> -> imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1020 <tt>MOVSX32rm16</tt> -> movsx, 32-bit register, 16-bit memory
1025 <!-- *********************************************************************** -->
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