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11 <div class="doc_title">
12 The LLVM Target-Independent Code Generator
16 <li><a href="#introduction">Introduction</a>
18 <li><a href="#required">Required components in the code generator</a></li>
19 <li><a href="#high-level-design">The high-level design of the code
21 <li><a href="#tablegen">Using TableGen for target description</a></li>
24 <li><a href="#targetdesc">Target description classes</a>
26 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
27 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
28 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
29 <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
30 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
31 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
32 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
33 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
36 <li><a href="#codegendesc">Machine code description classes</a>
38 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
39 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
41 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
44 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
46 <li><a href="#instselect">Instruction Selection</a>
48 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
49 <li><a href="#selectiondag_process">SelectionDAG Code Generation
51 <li><a href="#selectiondag_build">Initial SelectionDAG
53 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
54 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
55 Phase: the DAG Combiner</a></li>
56 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
57 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
59 <li><a href="#selectiondag_future">Future directions for the
62 <li><a href="#liveintervals">Live Intervals</a>
64 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
65 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
67 <li><a href="#regalloc">Register Allocation</a>
69 <li><a href="#regAlloc_represent">How registers are represented in
71 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
73 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
74 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
75 <li><a href="#regAlloc_fold">Instruction folding</a></li>
76 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
78 <li><a href="#codeemit">Code Emission</a>
80 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
81 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
85 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
87 <li><a href="#tailcallopt">Tail call optimization</a></li>
88 <li><a href="#x86">The X86 backend</a></li>
89 <li><a href="#ppc">The PowerPC backend</a>
91 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
92 <li><a href="#ppc_frame">Frame Layout</a></li>
93 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
94 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
100 <div class="doc_author">
101 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
102 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>,
103 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
105 <a href="mailto:jlaskey@mac.com">Jim Laskey</a></p>
108 <div class="doc_warning">
109 <p>Warning: This is a work in progress.</p>
112 <!-- *********************************************************************** -->
113 <div class="doc_section">
114 <a name="introduction">Introduction</a>
116 <!-- *********************************************************************** -->
118 <div class="doc_text">
120 <p>The LLVM target-independent code generator is a framework that provides a
121 suite of reusable components for translating the LLVM internal representation to
122 the machine code for a specified target—either in assembly form (suitable
123 for a static compiler) or in binary machine code format (usable for a JIT
124 compiler). The LLVM target-independent code generator consists of five main
128 <li><a href="#targetdesc">Abstract target description</a> interfaces which
129 capture important properties about various aspects of the machine, independently
130 of how they will be used. These interfaces are defined in
131 <tt>include/llvm/Target/</tt>.</li>
133 <li>Classes used to represent the <a href="#codegendesc">machine code</a> being
134 generated for a target. These classes are intended to be abstract enough to
135 represent the machine code for <i>any</i> target machine. These classes are
136 defined in <tt>include/llvm/CodeGen/</tt>.</li>
138 <li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
139 various phases of native code generation (register allocation, scheduling, stack
140 frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
142 <li><a href="#targetimpls">Implementations of the abstract target description
143 interfaces</a> for particular targets. These machine descriptions make use of
144 the components provided by LLVM, and can optionally provide custom
145 target-specific passes, to build complete code generators for a specific target.
146 Target descriptions live in <tt>lib/Target/</tt>.</li>
148 <li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
149 completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
150 interface for target-specific issues. The code for the target-independent
151 JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
156 Depending on which part of the code generator you are interested in working on,
157 different pieces of this will be useful to you. In any case, you should be
158 familiar with the <a href="#targetdesc">target description</a> and <a
159 href="#codegendesc">machine code representation</a> classes. If you want to add
160 a backend for a new target, you will need to <a href="#targetimpls">implement the
161 target description</a> classes for your new target and understand the <a
162 href="LangRef.html">LLVM code representation</a>. If you are interested in
163 implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
164 should only depend on the target-description and machine code representation
165 classes, ensuring that it is portable.
170 <!-- ======================================================================= -->
171 <div class="doc_subsection">
172 <a name="required">Required components in the code generator</a>
175 <div class="doc_text">
177 <p>The two pieces of the LLVM code generator are the high-level interface to the
178 code generator and the set of reusable components that can be used to build
179 target-specific backends. The two most important interfaces (<a
180 href="#targetmachine"><tt>TargetMachine</tt></a> and <a
181 href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
182 required to be defined for a backend to fit into the LLVM system, but the others
183 must be defined if the reusable code generator components are going to be
186 <p>This design has two important implications. The first is that LLVM can
187 support completely non-traditional code generation targets. For example, the C
188 backend does not require register allocation, instruction selection, or any of
189 the other standard components provided by the system. As such, it only
190 implements these two interfaces, and does its own thing. Another example of a
191 code generator like this is a (purely hypothetical) backend that converts LLVM
192 to the GCC RTL form and uses GCC to emit machine code for a target.</p>
194 <p>This design also implies that it is possible to design and
195 implement radically different code generators in the LLVM system that do not
196 make use of any of the built-in components. Doing so is not recommended at all,
197 but could be required for radically different targets that do not fit into the
198 LLVM machine description model: FPGAs for example.</p>
202 <!-- ======================================================================= -->
203 <div class="doc_subsection">
204 <a name="high-level-design">The high-level design of the code generator</a>
207 <div class="doc_text">
209 <p>The LLVM target-independent code generator is designed to support efficient and
210 quality code generation for standard register-based microprocessors. Code
211 generation in this model is divided into the following stages:</p>
214 <li><b><a href="#instselect">Instruction Selection</a></b> - This phase
215 determines an efficient way to express the input LLVM code in the target
217 This stage produces the initial code for the program in the target instruction
218 set, then makes use of virtual registers in SSA form and physical registers that
219 represent any required register assignments due to target constraints or calling
220 conventions. This step turns the LLVM code into a DAG of target
223 <li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
224 phase takes the DAG of target instructions produced by the instruction selection
225 phase, determines an ordering of the instructions, then emits the instructions
226 as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
227 that we describe this in the <a href="#instselect">instruction selection
228 section</a> because it operates on a <a
229 href="#selectiondag_intro">SelectionDAG</a>.
232 <li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
233 optional stage consists of a series of machine-code optimizations that
234 operate on the SSA-form produced by the instruction selector. Optimizations
235 like modulo-scheduling or peephole optimization work here.
238 <li><b><a href="#regalloc">Register Allocation</a></b> - The
239 target code is transformed from an infinite virtual register file in SSA form
240 to the concrete register file used by the target. This phase introduces spill
241 code and eliminates all virtual register references from the program.</li>
243 <li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
244 machine code has been generated for the function and the amount of stack space
245 required is known (used for LLVM alloca's and spill slots), the prolog and
246 epilog code for the function can be inserted and "abstract stack location
247 references" can be eliminated. This stage is responsible for implementing
248 optimizations like frame-pointer elimination and stack packing.</li>
250 <li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
251 that operate on "final" machine code can go here, such as spill code scheduling
252 and peephole optimizations.</li>
254 <li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
255 puts out the code for the current function, either in the target assembler
256 format or in machine code.</li>
260 <p>The code generator is based on the assumption that the instruction selector
261 will use an optimal pattern matching selector to create high-quality sequences of
262 native instructions. Alternative code generator designs based on pattern
263 expansion and aggressive iterative peephole optimization are much slower. This
264 design permits efficient compilation (important for JIT environments) and
265 aggressive optimization (used when generating code offline) by allowing
266 components of varying levels of sophistication to be used for any step of
269 <p>In addition to these stages, target implementations can insert arbitrary
270 target-specific passes into the flow. For example, the X86 target uses a
271 special pass to handle the 80x87 floating point stack architecture. Other
272 targets with unusual requirements can be supported with custom passes as
278 <!-- ======================================================================= -->
279 <div class="doc_subsection">
280 <a name="tablegen">Using TableGen for target description</a>
283 <div class="doc_text">
285 <p>The target description classes require a detailed description of the target
286 architecture. These target descriptions often have a large amount of common
287 information (e.g., an <tt>add</tt> instruction is almost identical to a
288 <tt>sub</tt> instruction).
289 In order to allow the maximum amount of commonality to be factored out, the LLVM
290 code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
291 describe big chunks of the target machine, which allows the use of
292 domain-specific and target-specific abstractions to reduce the amount of
295 <p>As LLVM continues to be developed and refined, we plan to move more and more
296 of the target description to the <tt>.td</tt> form. Doing so gives us a
297 number of advantages. The most important is that it makes it easier to port
298 LLVM because it reduces the amount of C++ code that has to be written, and the
299 surface area of the code generator that needs to be understood before someone
300 can get something working. Second, it makes it easier to change things. In
301 particular, if tables and other things are all emitted by <tt>tblgen</tt>, we
302 only need a change in one place (<tt>tblgen</tt>) to update all of the targets
303 to a new interface.</p>
307 <!-- *********************************************************************** -->
308 <div class="doc_section">
309 <a name="targetdesc">Target description classes</a>
311 <!-- *********************************************************************** -->
313 <div class="doc_text">
315 <p>The LLVM target description classes (located in the
316 <tt>include/llvm/Target</tt> directory) provide an abstract description of the
317 target machine independent of any particular client. These classes are
318 designed to capture the <i>abstract</i> properties of the target (such as the
319 instructions and registers it has), and do not incorporate any particular pieces
320 of code generation algorithms.</p>
322 <p>All of the target description classes (except the <tt><a
323 href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
324 the concrete target implementation, and have virtual methods implemented. To
325 get to these implementations, the <tt><a
326 href="#targetmachine">TargetMachine</a></tt> class provides accessors that
327 should be implemented by the target.</p>
331 <!-- ======================================================================= -->
332 <div class="doc_subsection">
333 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
336 <div class="doc_text">
338 <p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
339 access the target-specific implementations of the various target description
340 classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
341 <tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
342 designed to be specialized by
343 a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
344 implements the various virtual methods. The only required target description
345 class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
346 code generator components are to be used, the other interfaces should be
347 implemented as well.</p>
352 <!-- ======================================================================= -->
353 <div class="doc_subsection">
354 <a name="targetdata">The <tt>TargetData</tt> class</a>
357 <div class="doc_text">
359 <p>The <tt>TargetData</tt> class is the only required target description class,
360 and it is the only class that is not extensible (you cannot derived a new
361 class from it). <tt>TargetData</tt> specifies information about how the target
362 lays out memory for structures, the alignment requirements for various data
363 types, the size of pointers in the target, and whether the target is
364 little-endian or big-endian.</p>
368 <!-- ======================================================================= -->
369 <div class="doc_subsection">
370 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
373 <div class="doc_text">
375 <p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
376 selectors primarily to describe how LLVM code should be lowered to SelectionDAG
377 operations. Among other things, this class indicates:</p>
380 <li>an initial register class to use for various <tt>ValueType</tt>s</li>
381 <li>which operations are natively supported by the target machine</li>
382 <li>the return type of <tt>setcc</tt> operations</li>
383 <li>the type to use for shift amounts</li>
384 <li>various high-level characteristics, like whether it is profitable to turn
385 division by a constant into a multiplication sequence</li>
390 <!-- ======================================================================= -->
391 <div class="doc_subsection">
392 <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
395 <div class="doc_text">
397 <p>The <tt>TargetRegisterInfo</tt> class is used to describe the register
398 file of the target and any interactions between the registers.</p>
400 <p>Registers in the code generator are represented in the code generator by
401 unsigned integers. Physical registers (those that actually exist in the target
402 description) are unique small numbers, and virtual registers are generally
403 large. Note that register #0 is reserved as a flag value.</p>
405 <p>Each register in the processor description has an associated
406 <tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
407 register (used for assembly output and debugging dumps) and a set of aliases
408 (used to indicate whether one register overlaps with another).
411 <p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
412 class exposes a set of processor specific register classes (instances of the
413 <tt>TargetRegisterClass</tt> class). Each register class contains sets of
414 registers that have the same properties (for example, they are all 32-bit
415 integer registers). Each SSA virtual register created by the instruction
416 selector has an associated register class. When the register allocator runs, it
417 replaces virtual registers with a physical register in the set.</p>
420 The target-specific implementations of these classes is auto-generated from a <a
421 href="TableGenFundamentals.html">TableGen</a> description of the register file.
426 <!-- ======================================================================= -->
427 <div class="doc_subsection">
428 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
431 <div class="doc_text">
432 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
433 instructions supported by the target. It is essentially an array of
434 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
435 instruction the target supports. Descriptors define things like the mnemonic
436 for the opcode, the number of operands, the list of implicit register uses
437 and defs, whether the instruction has certain target-independent properties
438 (accesses memory, is commutable, etc), and holds any target-specific
442 <!-- ======================================================================= -->
443 <div class="doc_subsection">
444 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
447 <div class="doc_text">
448 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
449 stack frame layout of the target. It holds the direction of stack growth,
450 the known stack alignment on entry to each function, and the offset to the
451 local area. The offset to the local area is the offset from the stack
452 pointer on function entry to the first location where function data (local
453 variables, spill locations) can be stored.</p>
456 <!-- ======================================================================= -->
457 <div class="doc_subsection">
458 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
461 <div class="doc_text">
462 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
463 specific chip set being targeted. A sub-target informs code generation of
464 which instructions are supported, instruction latencies and instruction
465 execution itinerary; i.e., which processing units are used, in what order, and
470 <!-- ======================================================================= -->
471 <div class="doc_subsection">
472 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
475 <div class="doc_text">
476 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
477 Just-In-Time code generator to perform target-specific activities, such as
478 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
479 should provide one of these objects through the <tt>getJITInfo</tt>
483 <!-- *********************************************************************** -->
484 <div class="doc_section">
485 <a name="codegendesc">Machine code description classes</a>
487 <!-- *********************************************************************** -->
489 <div class="doc_text">
491 <p>At the high-level, LLVM code is translated to a machine specific
492 representation formed out of
493 <a href="#machinefunction"><tt>MachineFunction</tt></a>,
494 <a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>, and <a
495 href="#machineinstr"><tt>MachineInstr</tt></a> instances
496 (defined in <tt>include/llvm/CodeGen</tt>). This representation is completely
497 target agnostic, representing instructions in their most abstract form: an
498 opcode and a series of operands. This representation is designed to support
499 both an SSA representation for machine code, as well as a register allocated,
504 <!-- ======================================================================= -->
505 <div class="doc_subsection">
506 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
509 <div class="doc_text">
511 <p>Target machine instructions are represented as instances of the
512 <tt>MachineInstr</tt> class. This class is an extremely abstract way of
513 representing machine instructions. In particular, it only keeps track of
514 an opcode number and a set of operands.</p>
516 <p>The opcode number is a simple unsigned integer that only has meaning to a
517 specific backend. All of the instructions for a target should be defined in
518 the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
519 are auto-generated from this description. The <tt>MachineInstr</tt> class does
520 not have any information about how to interpret the instruction (i.e., what the
521 semantics of the instruction are); for that you must refer to the
522 <tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
524 <p>The operands of a machine instruction can be of several different types:
525 a register reference, a constant integer, a basic block reference, etc. In
526 addition, a machine operand should be marked as a def or a use of the value
527 (though only registers are allowed to be defs).</p>
529 <p>By convention, the LLVM code generator orders instruction operands so that
530 all register definitions come before the register uses, even on architectures
531 that are normally printed in other orders. For example, the SPARC add
532 instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
533 and stores the result into the "%i3" register. In the LLVM code generator,
534 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
537 <p>Keeping destination (definition) operands at the beginning of the operand
538 list has several advantages. In particular, the debugging printer will print
539 the instruction like this:</p>
541 <div class="doc_code">
547 <p>Also if the first operand is a def, it is easier to <a
548 href="#buildmi">create instructions</a> whose only def is the first
553 <!-- _______________________________________________________________________ -->
554 <div class="doc_subsubsection">
555 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
558 <div class="doc_text">
560 <p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
561 located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
562 <tt>BuildMI</tt> functions make it easy to build arbitrary machine
563 instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
565 <div class="doc_code">
567 // Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
568 // instruction. The '1' specifies how many operands will be added.
569 MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
571 // Create the same instr, but insert it at the end of a basic block.
572 MachineBasicBlock &MBB = ...
573 BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
575 // Create the same instr, but insert it before a specified iterator point.
576 MachineBasicBlock::iterator MBBI = ...
577 BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
579 // Create a 'cmp Reg, 0' instruction, no destination reg.
580 MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
581 // Create an 'sahf' instruction which takes no operands and stores nothing.
582 MI = BuildMI(X86::SAHF, 0);
584 // Create a self looping branch instruction.
585 BuildMI(MBB, X86::JNE, 1).addMBB(&MBB);
589 <p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
590 have to specify the number of operands that the machine instruction will take.
591 This allows for efficient memory allocation. You also need to specify if
592 operands default to be uses of values, not definitions. If you need to add a
593 definition operand (other than the optional destination register), you must
594 explicitly mark it as such:</p>
596 <div class="doc_code">
598 MI.addReg(Reg, MachineOperand::Def);
604 <!-- _______________________________________________________________________ -->
605 <div class="doc_subsubsection">
606 <a name="fixedregs">Fixed (preassigned) registers</a>
609 <div class="doc_text">
611 <p>One important issue that the code generator needs to be aware of is the
612 presence of fixed registers. In particular, there are often places in the
613 instruction stream where the register allocator <em>must</em> arrange for a
614 particular value to be in a particular register. This can occur due to
615 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
616 with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
617 conventions. In any case, the instruction selector should emit code that
618 copies a virtual register into or out of a physical register when needed.</p>
620 <p>For example, consider this simple LLVM example:</p>
622 <div class="doc_code">
624 int %test(int %X, int %Y) {
631 <p>The X86 instruction selector produces this machine code for the <tt>div</tt>
632 and <tt>ret</tt> (use
633 "<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
635 <div class="doc_code">
638 %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
639 %reg1027 = sar %reg1024, 31
640 %EDX = mov %reg1027 ;; Sign extend X into EDX
641 idiv %reg1025 ;; Divide by Y (in reg1025)
642 %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
645 %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
650 <p>By the end of code generation, the register allocator has coalesced
651 the registers and deleted the resultant identity moves producing the
654 <div class="doc_code">
656 ;; X is in EAX, Y is in ECX
664 <p>This approach is extremely general (if it can handle the X86 architecture,
665 it can handle anything!) and allows all of the target specific
666 knowledge about the instruction stream to be isolated in the instruction
667 selector. Note that physical registers should have a short lifetime for good
668 code generation, and all physical registers are assumed dead on entry to and
669 exit from basic blocks (before register allocation). Thus, if you need a value
670 to be live across basic block boundaries, it <em>must</em> live in a virtual
675 <!-- _______________________________________________________________________ -->
676 <div class="doc_subsubsection">
677 <a name="ssa">Machine code in SSA form</a>
680 <div class="doc_text">
682 <p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
683 are maintained in SSA-form until register allocation happens. For the most
684 part, this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
685 become machine code PHI nodes, and virtual registers are only allowed to have a
686 single definition.</p>
688 <p>After register allocation, machine code is no longer in SSA-form because there
689 are no virtual registers left in the code.</p>
693 <!-- ======================================================================= -->
694 <div class="doc_subsection">
695 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
698 <div class="doc_text">
700 <p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
701 (<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
702 corresponds to the LLVM code input to the instruction selector, but there can be
703 a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
704 basic blocks). The <tt>MachineBasicBlock</tt> class has a
705 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
710 <!-- ======================================================================= -->
711 <div class="doc_subsection">
712 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
715 <div class="doc_text">
717 <p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
718 (<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
719 corresponds one-to-one with the LLVM function input to the instruction selector.
720 In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
721 a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
722 <tt>MachineFunctionInfo</tt>, and a <tt>MachineRegisterInfo</tt>. See
723 <tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
727 <!-- *********************************************************************** -->
728 <div class="doc_section">
729 <a name="codegenalgs">Target-independent code generation algorithms</a>
731 <!-- *********************************************************************** -->
733 <div class="doc_text">
735 <p>This section documents the phases described in the <a
736 href="#high-level-design">high-level design of the code generator</a>. It
737 explains how they work and some of the rationale behind their design.</p>
741 <!-- ======================================================================= -->
742 <div class="doc_subsection">
743 <a name="instselect">Instruction Selection</a>
746 <div class="doc_text">
748 Instruction Selection is the process of translating LLVM code presented to the
749 code generator into target-specific machine instructions. There are several
750 well-known ways to do this in the literature. LLVM uses a SelectionDAG based
751 instruction selector.
754 <p>Portions of the DAG instruction selector are generated from the target
755 description (<tt>*.td</tt>) files. Our goal is for the entire instruction
756 selector to be generated from these <tt>.td</tt> files, though currently
757 there are still things that require custom C++ code.</p>
760 <!-- _______________________________________________________________________ -->
761 <div class="doc_subsubsection">
762 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
765 <div class="doc_text">
767 <p>The SelectionDAG provides an abstraction for code representation in a way
768 that is amenable to instruction selection using automatic techniques
769 (e.g. dynamic-programming based optimal pattern matching selectors). It is also
770 well-suited to other phases of code generation; in particular,
771 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
772 post-selection). Additionally, the SelectionDAG provides a host representation
773 where a large variety of very-low-level (but target-independent)
774 <a href="#selectiondag_optimize">optimizations</a> may be
775 performed; ones which require extensive information about the instructions
776 efficiently supported by the target.</p>
778 <p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
779 <tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
780 operation code (Opcode) that indicates what operation the node performs and
781 the operands to the operation.
782 The various operation node types are described at the top of the
783 <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
785 <p>Although most operations define a single value, each node in the graph may
786 define multiple values. For example, a combined div/rem operation will define
787 both the dividend and the remainder. Many other situations require multiple
788 values as well. Each node also has some number of operands, which are edges
789 to the node defining the used value. Because nodes may define multiple values,
790 edges are represented by instances of the <tt>SDOperand</tt> class, which is
791 a <tt><SDNode, unsigned></tt> pair, indicating the node and result
792 value being used, respectively. Each value produced by an <tt>SDNode</tt> has
793 an associated <tt>MVT::ValueType</tt> indicating what type the value is.</p>
795 <p>SelectionDAGs contain two different kinds of values: those that represent
796 data flow and those that represent control flow dependencies. Data values are
797 simple edges with an integer or floating point value type. Control edges are
798 represented as "chain" edges which are of type <tt>MVT::Other</tt>. These edges
799 provide an ordering between nodes that have side effects (such as
800 loads, stores, calls, returns, etc). All nodes that have side effects should
801 take a token chain as input and produce a new one as output. By convention,
802 token chain inputs are always operand #0, and chain results are always the last
803 value produced by an operation.</p>
805 <p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
806 always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root node
807 is the final side-effecting node in the token chain. For example, in a single
808 basic block function it would be the return node.</p>
810 <p>One important concept for SelectionDAGs is the notion of a "legal" vs.
811 "illegal" DAG. A legal DAG for a target is one that only uses supported
812 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
813 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
814 SREM or UREM operation. The
815 <a href="#selectiondag_legalize">legalize</a> phase is responsible for turning
816 an illegal DAG into a legal DAG.</p>
820 <!-- _______________________________________________________________________ -->
821 <div class="doc_subsubsection">
822 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
825 <div class="doc_text">
827 <p>SelectionDAG-based instruction selection consists of the following steps:</p>
830 <li><a href="#selectiondag_build">Build initial DAG</a> - This stage
831 performs a simple translation from the input LLVM code to an illegal
833 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
834 performs simple optimizations on the SelectionDAG to simplify it, and
835 recognize meta instructions (like rotates and <tt>div</tt>/<tt>rem</tt>
836 pairs) for targets that support these meta operations. This makes the
837 resultant code more efficient and the <a href="#selectiondag_select">select
838 instructions from DAG</a> phase (below) simpler.</li>
839 <li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
840 converts the illegal SelectionDAG to a legal SelectionDAG by eliminating
841 unsupported operations and data types.</li>
842 <li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
843 second run of the SelectionDAG optimizes the newly legalized DAG to
844 eliminate inefficiencies introduced by legalization.</li>
845 <li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
846 the target instruction selector matches the DAG operations to target
847 instructions. This process translates the target-independent input DAG into
848 another DAG of target instructions.</li>
849 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
850 - The last phase assigns a linear order to the instructions in the
851 target-instruction DAG and emits them into the MachineFunction being
852 compiled. This step uses traditional prepass scheduling techniques.</li>
855 <p>After all of these steps are complete, the SelectionDAG is destroyed and the
856 rest of the code generation passes are run.</p>
858 <p>One great way to visualize what is going on here is to take advantage of a
859 few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
860 option pops up a window with the SelectionDAG input to the Select phase for all
861 of the code compiled (if you only get errors printed to the console while using
862 this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
863 your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
864 views the SelectionDAG output from the Select phase and input to the Scheduler
865 phase. The <tt>-view-sunit-dags</tt> option views the ScheduleDAG, which is
866 based on the final SelectionDAG, with nodes that must be scheduled as a unit
867 bundled together into a single node, and with immediate operands and other
868 nodes that aren't relevent for scheduling omitted.
873 <!-- _______________________________________________________________________ -->
874 <div class="doc_subsubsection">
875 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
878 <div class="doc_text">
880 <p>The initial SelectionDAG is naïvely peephole expanded from the LLVM
881 input by the <tt>SelectionDAGLowering</tt> class in the
882 <tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of this
883 pass is to expose as much low-level, target-specific details to the SelectionDAG
884 as possible. This pass is mostly hard-coded (e.g. an LLVM <tt>add</tt> turns
885 into an <tt>SDNode add</tt> while a <tt>geteelementptr</tt> is expanded into the
886 obvious arithmetic). This pass requires target-specific hooks to lower calls,
887 returns, varargs, etc. For these features, the
888 <tt><a href="#targetlowering">TargetLowering</a></tt> interface is used.</p>
892 <!-- _______________________________________________________________________ -->
893 <div class="doc_subsubsection">
894 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
897 <div class="doc_text">
899 <p>The Legalize phase is in charge of converting a DAG to only use the types and
900 operations that are natively supported by the target. This involves two major
904 <li><p>Convert values of unsupported types to values of supported types.</p>
905 <p>There are two main ways of doing this: converting small types to
906 larger types ("promoting"), and breaking up large integer types
907 into smaller ones ("expanding"). For example, a target might require
908 that all f32 values are promoted to f64 and that all i1/i8/i16 values
909 are promoted to i32. The same target might require that all i64 values
910 be expanded into i32 values. These changes can insert sign and zero
911 extensions as needed to make sure that the final code has the same
912 behavior as the input.</p>
913 <p>A target implementation tells the legalizer which types are supported
914 (and which register class to use for them) by calling the
915 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
918 <li><p>Eliminate operations that are not supported by the target.</p>
919 <p>Targets often have weird constraints, such as not supporting every
920 operation on every supported datatype (e.g. X86 does not support byte
921 conditional moves and PowerPC does not support sign-extending loads from
922 a 16-bit memory location). Legalize takes care of this by open-coding
923 another sequence of operations to emulate the operation ("expansion"), by
924 promoting one type to a larger type that supports the operation
925 ("promotion"), or by using a target-specific hook to implement the
926 legalization ("custom").</p>
927 <p>A target implementation tells the legalizer which operations are not
928 supported (and which of the above three actions to take) by calling the
929 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
934 <p>Prior to the existance of the Legalize pass, we required that every target
935 <a href="#selectiondag_optimize">selector</a> supported and handled every
936 operator and type even if they are not natively supported. The introduction of
937 the Legalize phase allows all of the cannonicalization patterns to be shared
938 across targets, and makes it very easy to optimize the cannonicalized code
939 because it is still in the form of a DAG.</p>
943 <!-- _______________________________________________________________________ -->
944 <div class="doc_subsubsection">
945 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
949 <div class="doc_text">
951 <p>The SelectionDAG optimization phase is run twice for code generation: once
952 immediately after the DAG is built and once after legalization. The first run
953 of the pass allows the initial code to be cleaned up (e.g. performing
954 optimizations that depend on knowing that the operators have restricted type
955 inputs). The second run of the pass cleans up the messy code generated by the
956 Legalize pass, which allows Legalize to be very simple (it can focus on making
957 code legal instead of focusing on generating <em>good</em> and legal code).</p>
959 <p>One important class of optimizations performed is optimizing inserted sign
960 and zero extension instructions. We currently use ad-hoc techniques, but could
961 move to more rigorous techniques in the future. Here are some good papers on
965 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
966 integer arithmetic</a>"<br>
967 Kevin Redwine and Norman Ramsey<br>
968 International Conference on Compiler Construction (CC) 2004
973 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
974 sign extension elimination</a>"<br>
975 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
976 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
982 <!-- _______________________________________________________________________ -->
983 <div class="doc_subsubsection">
984 <a name="selectiondag_select">SelectionDAG Select Phase</a>
987 <div class="doc_text">
989 <p>The Select phase is the bulk of the target-specific code for instruction
990 selection. This phase takes a legal SelectionDAG as input, pattern matches the
991 instructions supported by the target to this DAG, and produces a new DAG of
992 target code. For example, consider the following LLVM fragment:</p>
994 <div class="doc_code">
996 %t1 = add float %W, %X
997 %t2 = mul float %t1, %Y
998 %t3 = add float %t2, %Z
1002 <p>This LLVM code corresponds to a SelectionDAG that looks basically like
1005 <div class="doc_code">
1007 (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
1011 <p>If a target supports floating point multiply-and-add (FMA) operations, one
1012 of the adds can be merged with the multiply. On the PowerPC, for example, the
1013 output of the instruction selector might look like this DAG:</p>
1015 <div class="doc_code">
1017 (FMADDS (FADDS W, X), Y, Z)
1021 <p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1022 first two operands and adds the third (as single-precision floating-point
1023 numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1024 add instruction. To perform this pattern match, the PowerPC backend includes
1025 the following instruction definitions:</p>
1027 <div class="doc_code">
1029 def FMADDS : AForm_1<59, 29,
1030 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1031 "fmadds $FRT, $FRA, $FRC, $FRB",
1032 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1033 F4RC:$FRB))</b>]>;
1034 def FADDS : AForm_2<59, 21,
1035 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1036 "fadds $FRT, $FRA, $FRB",
1037 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]>;
1041 <p>The portion of the instruction definition in bold indicates the pattern used
1042 to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1043 are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
1044 "<tt>F4RC</tt>" is the register class of the input and result values.<p>
1046 <p>The TableGen DAG instruction selector generator reads the instruction
1047 patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
1048 matching code for your target. It has the following strengths:</p>
1051 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1052 you if your patterns make sense or not.</li>
1053 <li>It can handle arbitrary constraints on operands for the pattern match. In
1054 particular, it is straight-forward to say things like "match any immediate
1055 that is a 13-bit sign-extended value". For examples, see the
1056 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1058 <li>It knows several important identities for the patterns defined. For
1059 example, it knows that addition is commutative, so it allows the
1060 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1061 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1062 to specially handle this case.</li>
1063 <li>It has a full-featured type-inferencing system. In particular, you should
1064 rarely have to explicitly tell the system what type parts of your patterns
1065 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1066 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'. It
1067 was able to infer and propagate this knowledge from the fact that
1068 <tt>F4RC</tt> has type 'f32'.</li>
1069 <li>Targets can define their own (and rely on built-in) "pattern fragments".
1070 Pattern fragments are chunks of reusable patterns that get inlined into your
1071 patterns during compiler-compiler time. For example, the integer
1072 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment that
1073 expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not have a
1074 native '<tt>not</tt>' operation. Targets can define their own short-hand
1075 fragments as they see fit. See the definition of '<tt>not</tt>' and
1076 '<tt>ineg</tt>' for examples.</li>
1077 <li>In addition to instructions, targets can specify arbitrary patterns that
1078 map to one or more instructions using the 'Pat' class. For example,
1079 the PowerPC has no way to load an arbitrary integer immediate into a
1080 register in one instruction. To tell tblgen how to do this, it defines:
1083 <div class="doc_code">
1085 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1086 def : Pat<(i32 imm:$imm),
1087 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1091 If none of the single-instruction patterns for loading an immediate into a
1092 register match, this will be used. This rule says "match an arbitrary i32
1093 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and an
1094 <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to the
1095 left 16 bits') instruction". To make this work, the
1096 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate the
1097 input immediate (in this case, take the high or low 16-bits of the
1099 <li>While the system does automate a lot, it still allows you to write custom
1100 C++ code to match special cases if there is something that is hard to
1104 <p>While it has many strengths, the system currently has some limitations,
1105 primarily because it is a work in progress and is not yet finished:</p>
1108 <li>Overall, there is no way to define or match SelectionDAG nodes that define
1109 multiple values (e.g. <tt>ADD_PARTS</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1110 etc). This is the biggest reason that you currently still <em>have to</em>
1111 write custom C++ code for your instruction selector.</li>
1112 <li>There is no great way to support matching complex addressing modes yet. In
1113 the future, we will extend pattern fragments to allow them to define
1114 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1115 addressing mode</a>, which are currently matched with custom C++ code).
1116 In addition, we'll extend fragments so that a
1117 fragment can match multiple different patterns.</li>
1118 <li>We don't automatically infer flags like isStore/isLoad yet.</li>
1119 <li>We don't automatically generate the set of supported registers and
1120 operations for the <a href="#selectiondag_legalize">Legalizer</a> yet.</li>
1121 <li>We don't have a way of tying in custom legalized nodes yet.</li>
1124 <p>Despite these limitations, the instruction selector generator is still quite
1125 useful for most of the binary and logical operations in typical instruction
1126 sets. If you run into any problems or can't figure out how to do something,
1127 please let Chris know!</p>
1131 <!-- _______________________________________________________________________ -->
1132 <div class="doc_subsubsection">
1133 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
1136 <div class="doc_text">
1138 <p>The scheduling phase takes the DAG of target instructions from the selection
1139 phase and assigns an order. The scheduler can pick an order depending on
1140 various constraints of the machines (i.e. order for minimal register pressure or
1141 try to cover instruction latencies). Once an order is established, the DAG is
1142 converted to a list of <tt><a href="#machineinstr">MachineInstr</a></tt>s and
1143 the SelectionDAG is destroyed.</p>
1145 <p>Note that this phase is logically separate from the instruction selection
1146 phase, but is tied to it closely in the code because it operates on
1151 <!-- _______________________________________________________________________ -->
1152 <div class="doc_subsubsection">
1153 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1156 <div class="doc_text">
1159 <li>Optional function-at-a-time selection.</li>
1160 <li>Auto-generate entire selector from <tt>.td</tt> file.</li>
1165 <!-- ======================================================================= -->
1166 <div class="doc_subsection">
1167 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1169 <div class="doc_text"><p>To Be Written</p></div>
1171 <!-- ======================================================================= -->
1172 <div class="doc_subsection">
1173 <a name="liveintervals">Live Intervals</a>
1176 <div class="doc_text">
1178 <p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
1179 They are used by some <a href="#regalloc">register allocator</a> passes to
1180 determine if two or more virtual registers which require the same physical
1181 register are live at the same point in the program (i.e., they conflict). When
1182 this situation occurs, one virtual register must be <i>spilled</i>.</p>
1186 <!-- _______________________________________________________________________ -->
1187 <div class="doc_subsubsection">
1188 <a name="livevariable_analysis">Live Variable Analysis</a>
1191 <div class="doc_text">
1193 <p>The first step in determining the live intervals of variables is to
1194 calculate the set of registers that are immediately dead after the
1195 instruction (i.e., the instruction calculates the value, but it is
1196 never used) and the set of registers that are used by the instruction,
1197 but are never used after the instruction (i.e., they are killed). Live
1198 variable information is computed for each <i>virtual</i> register and
1199 <i>register allocatable</i> physical register in the function. This
1200 is done in a very efficient manner because it uses SSA to sparsely
1201 compute lifetime information for virtual registers (which are in SSA
1202 form) and only has to track physical registers within a block. Before
1203 register allocation, LLVM can assume that physical registers are only
1204 live within a single basic block. This allows it to do a single,
1205 local analysis to resolve physical register lifetimes within each
1206 basic block. If a physical register is not register allocatable (e.g.,
1207 a stack pointer or condition codes), it is not tracked.</p>
1209 <p>Physical registers may be live in to or out of a function. Live in values
1210 are typically arguments in registers. Live out values are typically return
1211 values in registers. Live in values are marked as such, and are given a dummy
1212 "defining" instruction during live intervals analysis. If the last basic block
1213 of a function is a <tt>return</tt>, then it's marked as using all live out
1214 values in the function.</p>
1216 <p><tt>PHI</tt> nodes need to be handled specially, because the calculation
1217 of the live variable information from a depth first traversal of the CFG of
1218 the function won't guarantee that a virtual register used by the <tt>PHI</tt>
1219 node is defined before it's used. When a <tt>PHI</tt> node is encounted, only
1220 the definition is handled, because the uses will be handled in other basic
1223 <p>For each <tt>PHI</tt> node of the current basic block, we simulate an
1224 assignment at the end of the current basic block and traverse the successor
1225 basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1226 the <tt>PHI</tt> node's operands is coming from the current basic block,
1227 then the variable is marked as <i>alive</i> within the current basic block
1228 and all of its predecessor basic blocks, until the basic block with the
1229 defining instruction is encountered.</p>
1233 <!-- _______________________________________________________________________ -->
1234 <div class="doc_subsubsection">
1235 <a name="liveintervals_analysis">Live Intervals Analysis</a>
1238 <div class="doc_text">
1240 <p>We now have the information available to perform the live intervals analysis
1241 and build the live intervals themselves. We start off by numbering the basic
1242 blocks and machine instructions. We then handle the "live-in" values. These
1243 are in physical registers, so the physical register is assumed to be killed by
1244 the end of the basic block. Live intervals for virtual registers are computed
1245 for some ordering of the machine instructions <tt>[1, N]</tt>. A live interval
1246 is an interval <tt>[i, j)</tt>, where <tt>1 <= i <= j < N</tt>, for which a
1247 variable is live.</p>
1249 <p><i><b>More to come...</b></i></p>
1253 <!-- ======================================================================= -->
1254 <div class="doc_subsection">
1255 <a name="regalloc">Register Allocation</a>
1258 <div class="doc_text">
1260 <p>The <i>Register Allocation problem</i> consists in mapping a program
1261 <i>P<sub>v</sub></i>, that can use an unbounded number of virtual
1262 registers, to a program <i>P<sub>p</sub></i> that contains a finite
1263 (possibly small) number of physical registers. Each target architecture has
1264 a different number of physical registers. If the number of physical
1265 registers is not enough to accommodate all the virtual registers, some of
1266 them will have to be mapped into memory. These virtuals are called
1267 <i>spilled virtuals</i>.</p>
1271 <!-- _______________________________________________________________________ -->
1273 <div class="doc_subsubsection">
1274 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1277 <div class="doc_text">
1279 <p>In LLVM, physical registers are denoted by integer numbers that
1280 normally range from 1 to 1023. To see how this numbering is defined
1281 for a particular architecture, you can read the
1282 <tt>GenRegisterNames.inc</tt> file for that architecture. For
1283 instance, by inspecting
1284 <tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the 32-bit
1285 register <tt>EAX</tt> is denoted by 15, and the MMX register
1286 <tt>MM0</tt> is mapped to 48.</p>
1288 <p>Some architectures contain registers that share the same physical
1289 location. A notable example is the X86 platform. For instance, in the
1290 X86 architecture, the registers <tt>EAX</tt>, <tt>AX</tt> and
1291 <tt>AL</tt> share the first eight bits. These physical registers are
1292 marked as <i>aliased</i> in LLVM. Given a particular architecture, you
1293 can check which registers are aliased by inspecting its
1294 <tt>RegisterInfo.td</tt> file. Moreover, the method
1295 <tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1296 all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1298 <p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1299 Elements in the same register class are functionally equivalent, and can
1300 be interchangeably used. Each virtual register can only be mapped to
1301 physical registers of a particular class. For instance, in the X86
1302 architecture, some virtuals can only be allocated to 8 bit registers.
1303 A register class is described by <tt>TargetRegisterClass</tt> objects.
1304 To discover if a virtual register is compatible with a given physical,
1305 this code can be used:
1308 <div class="doc_code">
1310 bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1313 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &&
1314 "Target register must be physical");
1315 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1316 return trc->contains(p_reg);
1321 <p>Sometimes, mostly for debugging purposes, it is useful to change
1322 the number of physical registers available in the target
1323 architecture. This must be done statically, inside the
1324 <tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt> for
1325 <tt>RegisterClass</tt>, the last parameter of which is a list of
1326 registers. Just commenting some out is one simple way to avoid them
1327 being used. A more polite way is to explicitly exclude some registers
1328 from the <i>allocation order</i>. See the definition of the
1329 <tt>GR</tt> register class in
1330 <tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
1331 (e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
1333 <p>Virtual registers are also denoted by integer numbers. Contrary to
1334 physical registers, different virtual registers never share the same
1335 number. The smallest virtual register is normally assigned the number
1336 1024. This may change, so, in order to know which is the first virtual
1337 register, you should access
1338 <tt>TargetRegisterInfo::FirstVirtualRegister</tt>. Any register whose
1339 number is greater than or equal to
1340 <tt>TargetRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
1341 register. Whereas physical registers are statically defined in a
1342 <tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1343 application developer, that is not the case with virtual registers.
1344 In order to create new virtual registers, use the method
1345 <tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method will return a
1346 virtual register with the highest code.
1349 <p>Before register allocation, the operands of an instruction are
1350 mostly virtual registers, although physical registers may also be
1351 used. In order to check if a given machine operand is a register, use
1352 the boolean function <tt>MachineOperand::isRegister()</tt>. To obtain
1353 the integer code of a register, use
1354 <tt>MachineOperand::getReg()</tt>. An instruction may define or use a
1355 register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1356 defines the registers 1024, and uses registers 1025 and 1026. Given a
1357 register operand, the method <tt>MachineOperand::isUse()</tt> informs
1358 if that register is being used by the instruction. The method
1359 <tt>MachineOperand::isDef()</tt> informs if that registers is being
1362 <p>We will call physical registers present in the LLVM bitcode before
1363 register allocation <i>pre-colored registers</i>. Pre-colored
1364 registers are used in many different situations, for instance, to pass
1365 parameters of functions calls, and to store results of particular
1366 instructions. There are two types of pre-colored registers: the ones
1367 <i>implicitly</i> defined, and those <i>explicitly</i>
1368 defined. Explicitly defined registers are normal operands, and can be
1369 accessed with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In
1370 order to check which registers are implicitly defined by an
1371 instruction, use the
1372 <tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>, where
1373 <tt>opcode</tt> is the opcode of the target instruction. One important
1374 difference between explicit and implicit physical registers is that
1375 the latter are defined statically for each instruction, whereas the
1376 former may vary depending on the program being compiled. For example,
1377 an instruction that represents a function call will always implicitly
1378 define or use the same set of physical registers. To read the
1379 registers implicitly used by an instruction, use
1380 <tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1381 registers impose constraints on any register allocation algorithm. The
1382 register allocator must make sure that none of them is been
1383 overwritten by the values of virtual registers while still alive.</p>
1387 <!-- _______________________________________________________________________ -->
1389 <div class="doc_subsubsection">
1390 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1393 <div class="doc_text">
1395 <p>There are two ways to map virtual registers to physical registers (or to
1396 memory slots). The first way, that we will call <i>direct mapping</i>,
1397 is based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
1398 and <tt>MachineOperand</tt>. The second way, that we will call
1399 <i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
1400 order to insert loads and stores sending and getting values to and from
1403 <p>The direct mapping provides more flexibility to the developer of
1404 the register allocator; however, it is more error prone, and demands
1405 more implementation work. Basically, the programmer will have to
1406 specify where load and store instructions should be inserted in the
1407 target function being compiled in order to get and store values in
1408 memory. To assign a physical register to a virtual register present in
1409 a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
1410 a store instruction, use
1411 <tt>TargetRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
1412 instruction, use <tt>TargetRegisterInfo::loadRegFromStackSlot</tt>.</p>
1414 <p>The indirect mapping shields the application developer from the
1415 complexities of inserting load and store instructions. In order to map
1416 a virtual register to a physical one, use
1417 <tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In order to map a
1418 certain virtual register to memory, use
1419 <tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will
1420 return the stack slot where <tt>vreg</tt>'s value will be located. If
1421 it is necessary to map another virtual register to the same stack
1422 slot, use <tt>VirtRegMap::assignVirt2StackSlot(vreg,
1423 stack_location)</tt>. One important point to consider when using the
1424 indirect mapping, is that even if a virtual register is mapped to
1425 memory, it still needs to be mapped to a physical register. This
1426 physical register is the location where the virtual register is
1427 supposed to be found before being stored or after being reloaded.</p>
1429 <p>If the indirect strategy is used, after all the virtual registers
1430 have been mapped to physical registers or stack slots, it is necessary
1431 to use a spiller object to place load and store instructions in the
1432 code. Every virtual that has been mapped to a stack slot will be
1433 stored to memory after been defined and will be loaded before being
1434 used. The implementation of the spiller tries to recycle load/store
1435 instructions, avoiding unnecessary instructions. For an example of how
1436 to invoke the spiller, see
1437 <tt>RegAllocLinearScan::runOnMachineFunction</tt> in
1438 <tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1442 <!-- _______________________________________________________________________ -->
1443 <div class="doc_subsubsection">
1444 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1447 <div class="doc_text">
1449 <p>With very rare exceptions (e.g., function calls), the LLVM machine
1450 code instructions are three address instructions. That is, each
1451 instruction is expected to define at most one register, and to use at
1452 most two registers. However, some architectures use two address
1453 instructions. In this case, the defined register is also one of the
1454 used register. For instance, an instruction such as <tt>ADD %EAX,
1455 %EBX</tt>, in X86 is actually equivalent to <tt>%EAX = %EAX +
1458 <p>In order to produce correct code, LLVM must convert three address
1459 instructions that represent two address instructions into true two
1460 address instructions. LLVM provides the pass
1461 <tt>TwoAddressInstructionPass</tt> for this specific purpose. It must
1462 be run before register allocation takes place. After its execution,
1463 the resulting code may no longer be in SSA form. This happens, for
1464 instance, in situations where an instruction such as <tt>%a = ADD %b
1465 %c</tt> is converted to two instructions such as:</p>
1467 <div class="doc_code">
1474 <p>Notice that, internally, the second instruction is represented as
1475 <tt>ADD %a[def/use] %b</tt>. I.e., the register operand <tt>%a</tt> is
1476 both used and defined by the instruction.</p>
1480 <!-- _______________________________________________________________________ -->
1481 <div class="doc_subsubsection">
1482 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1485 <div class="doc_text">
1487 <p>An important transformation that happens during register allocation is called
1488 the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many
1489 analyses that are performed on the control flow graph of
1490 programs. However, traditional instruction sets do not implement
1491 PHI instructions. Thus, in order to generate executable code, compilers
1492 must replace PHI instructions with other instructions that preserve their
1495 <p>There are many ways in which PHI instructions can safely be removed
1496 from the target code. The most traditional PHI deconstruction
1497 algorithm replaces PHI instructions with copy instructions. That is
1498 the strategy adopted by LLVM. The SSA deconstruction algorithm is
1499 implemented in n<tt>lib/CodeGen/>PHIElimination.cpp</tt>. In order to
1500 invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
1501 marked as required in the code of the register allocator.</p>
1505 <!-- _______________________________________________________________________ -->
1506 <div class="doc_subsubsection">
1507 <a name="regAlloc_fold">Instruction folding</a>
1510 <div class="doc_text">
1512 <p><i>Instruction folding</i> is an optimization performed during
1513 register allocation that removes unnecessary copy instructions. For
1514 instance, a sequence of instructions such as:</p>
1516 <div class="doc_code">
1518 %EBX = LOAD %mem_address
1523 <p>can be safely substituted by the single instruction:
1525 <div class="doc_code">
1527 %EAX = LOAD %mem_address
1531 <p>Instructions can be folded with the
1532 <tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1533 taken when folding instructions; a folded instruction can be quite
1534 different from the original instruction. See
1535 <tt>LiveIntervals::addIntervalsForSpills</tt> in
1536 <tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its use.</p>
1540 <!-- _______________________________________________________________________ -->
1542 <div class="doc_subsubsection">
1543 <a name="regAlloc_builtIn">Built in register allocators</a>
1546 <div class="doc_text">
1548 <p>The LLVM infrastructure provides the application developer with
1549 three different register allocators:</p>
1552 <li><i>Simple</i> - This is a very simple implementation that does
1553 not keep values in registers across instructions. This register
1554 allocator immediately spills every value right after it is
1555 computed, and reloads all used operands from memory to temporary
1556 registers before each instruction.</li>
1557 <li><i>Local</i> - This register allocator is an improvement on the
1558 <i>Simple</i> implementation. It allocates registers on a basic
1559 block level, attempting to keep values in registers and reusing
1560 registers as appropriate.</li>
1561 <li><i>Linear Scan</i> - <i>The default allocator</i>. This is the
1562 well-know linear scan register allocator. Whereas the
1563 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1564 implementation technique, the <i>Linear Scan</i> implementation
1565 uses a spiller in order to place load and stores.</li>
1568 <p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1569 command line option <tt>-regalloc=...</tt>:</p>
1571 <div class="doc_code">
1573 $ llc -f -regalloc=simple file.bc -o sp.s;
1574 $ llc -f -regalloc=local file.bc -o lc.s;
1575 $ llc -f -regalloc=linearscan file.bc -o ln.s;
1581 <!-- ======================================================================= -->
1582 <div class="doc_subsection">
1583 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1585 <div class="doc_text"><p>To Be Written</p></div>
1586 <!-- ======================================================================= -->
1587 <div class="doc_subsection">
1588 <a name="latemco">Late Machine Code Optimizations</a>
1590 <div class="doc_text"><p>To Be Written</p></div>
1591 <!-- ======================================================================= -->
1592 <div class="doc_subsection">
1593 <a name="codeemit">Code Emission</a>
1595 <div class="doc_text"><p>To Be Written</p></div>
1596 <!-- _______________________________________________________________________ -->
1597 <div class="doc_subsubsection">
1598 <a name="codeemit_asm">Generating Assembly Code</a>
1600 <div class="doc_text"><p>To Be Written</p></div>
1601 <!-- _______________________________________________________________________ -->
1602 <div class="doc_subsubsection">
1603 <a name="codeemit_bin">Generating Binary Machine Code</a>
1606 <div class="doc_text">
1607 <p>For the JIT or <tt>.o</tt> file writer</p>
1611 <!-- *********************************************************************** -->
1612 <div class="doc_section">
1613 <a name="targetimpls">Target-specific Implementation Notes</a>
1615 <!-- *********************************************************************** -->
1617 <div class="doc_text">
1619 <p>This section of the document explains features or design decisions that
1620 are specific to the code generator for a particular target.</p>
1624 <!-- ======================================================================= -->
1625 <div class="doc_subsection">
1626 <a name="tailcallopt">Tail call optimization</a>
1629 <div class="doc_text">
1630 <p>Tail call optimization, callee reusing the stack of the caller, is currently supported on x86/x86-64 and PowerPC. It is performed if:
1632 <li>Caller and callee have the calling convention <tt>fastcc</tt>.</li>
1633 <li>The call is a tail call - in tail position (ret immediately follows call and ret uses value of call or is void).</li>
1634 <li>Option <tt>-tailcallopt</tt> is enabled.</li>
1635 <li>Platform specific constraints are met.</li>
1639 <p>x86/x86-64 constraints:
1641 <li>No variable argument lists are used.</li>
1642 <li>On x86-64 when generating GOT/PIC code only module-local calls (visibility = hidden or protected) are supported.</li>
1645 <p>PowerPC constraints:
1647 <li>No variable argument lists are used.</li>
1648 <li>No byval parameters are used.</li>
1649 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
1653 <p>Call as <tt>llc -tailcallopt test.ll</tt>.
1654 <div class="doc_code">
1656 declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
1658 define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
1659 %l1 = add i32 %in1, %in2
1660 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
1665 <p>Implications of <tt>-tailcallopt</tt>:</p>
1666 <p>To support tail call optimization in situations where the callee has more arguments than the caller a 'callee pops arguments' convention is used. This currently causes each <tt>fastcc</tt> call that is not tail call optimized (because one or more of above constraints are not met) to be followed by a readjustment of the stack. So performance might be worse in such cases.</p>
1667 <p>On x86 and x86-64 one register is reserved for indirect tail calls (e.g via a function pointer). So there is one less register for integer argument passing. For x86 this means 2 registers (if <tt>inreg</tt> parameter attribute is used) and for x86-64 this means 5 register are used.</p>
1669 <!-- ======================================================================= -->
1670 <div class="doc_subsection">
1671 <a name="x86">The X86 backend</a>
1674 <div class="doc_text">
1676 <p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
1677 code generator is capable of targeting a variety of x86-32 and x86-64
1678 processors, and includes support for ISA extensions such as MMX and SSE.
1683 <!-- _______________________________________________________________________ -->
1684 <div class="doc_subsubsection">
1685 <a name="x86_tt">X86 Target Triples Supported</a>
1688 <div class="doc_text">
1690 <p>The following are the known target triples that are supported by the X86
1691 backend. This is not an exhaustive list, and it would be useful to add those
1692 that people test.</p>
1695 <li><b>i686-pc-linux-gnu</b> - Linux</li>
1696 <li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1697 <li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1698 <li><b>i686-pc-mingw32</b> - MingW on Win32</li>
1699 <li><b>i386-pc-mingw32msvc</b> - MingW crosscompiler on Linux</li>
1700 <li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
1705 <!-- _______________________________________________________________________ -->
1706 <div class="doc_subsubsection">
1707 <a name="x86_cc">X86 Calling Conventions supported</a>
1711 <div class="doc_text">
1713 <p>The folowing target-specific calling conventions are known to backend:</p>
1716 <li><b>x86_StdCall</b> - stdcall calling convention seen on Microsoft Windows
1717 platform (CC ID = 64).</li>
1718 <li><b>x86_FastCall</b> - fastcall calling convention seen on Microsoft Windows
1719 platform (CC ID = 65).</li>
1724 <!-- _______________________________________________________________________ -->
1725 <div class="doc_subsubsection">
1726 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1729 <div class="doc_text">
1731 <p>The x86 has a very flexible way of accessing memory. It is capable of
1732 forming memory addresses of the following expression directly in integer
1733 instructions (which use ModR/M addressing):</p>
1735 <div class="doc_code">
1737 Base + [1,2,4,8] * IndexReg + Disp32
1741 <p>In order to represent this, LLVM tracks no less than 4 operands for each
1742 memory operand of this form. This means that the "load" form of '<tt>mov</tt>'
1743 has the following <tt>MachineOperand</tt>s in this order:</p>
1747 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1748 OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1751 <p>Stores, and all other instructions, treat the four memory operands in the
1752 same way and in the same order.</p>
1756 <!-- _______________________________________________________________________ -->
1757 <div class="doc_subsubsection">
1758 <a name="x86_names">Instruction naming</a>
1761 <div class="doc_text">
1763 <p>An instruction name consists of the base name, a default operand size, and a
1764 a character per operand with an optional special size. For example:</p>
1767 <tt>ADD8rr</tt> -> add, 8-bit register, 8-bit register<br>
1768 <tt>IMUL16rmi</tt> -> imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1769 <tt>IMUL16rmi8</tt> -> imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1770 <tt>MOVSX32rm16</tt> -> movsx, 32-bit register, 16-bit memory
1775 <!-- ======================================================================= -->
1776 <div class="doc_subsection">
1777 <a name="ppc">The PowerPC backend</a>
1780 <div class="doc_text">
1781 <p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
1782 code generation is retargetable to several variations or <i>subtargets</i> of
1783 the PowerPC ISA; including ppc32, ppc64 and altivec.
1787 <!-- _______________________________________________________________________ -->
1788 <div class="doc_subsubsection">
1789 <a name="ppc_abi">LLVM PowerPC ABI</a>
1792 <div class="doc_text">
1793 <p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
1794 relative (PIC) or static addressing for accessing global values, so no TOC (r2)
1795 is used. Second, r31 is used as a frame pointer to allow dynamic growth of a
1796 stack frame. LLVM takes advantage of having no TOC to provide space to save
1797 the frame pointer in the PowerPC linkage area of the caller frame. Other
1798 details of PowerPC ABI can be found at <a href=
1799 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
1800 >PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The
1801 64 bit ABI is similar except space for GPRs are 8 bytes wide (not 4) and r13 is
1802 reserved for system use.</p>
1805 <!-- _______________________________________________________________________ -->
1806 <div class="doc_subsubsection">
1807 <a name="ppc_frame">Frame Layout</a>
1810 <div class="doc_text">
1811 <p>The size of a PowerPC frame is usually fixed for the duration of a
1812 function’s invocation. Since the frame is fixed size, all references into
1813 the frame can be accessed via fixed offsets from the stack pointer. The
1814 exception to this is when dynamic alloca or variable sized arrays are present,
1815 then a base pointer (r31) is used as a proxy for the stack pointer and stack
1816 pointer is free to grow or shrink. A base pointer is also used if llvm-gcc is
1817 not passed the -fomit-frame-pointer flag. The stack pointer is always aligned to
1818 16 bytes, so that space allocated for altivec vectors will be properly
1820 <p>An invocation frame is layed out as follows (low memory at top);</p>
1823 <div class="doc_text">
1824 <table class="layout">
1826 <td>Linkage<br><br></td>
1829 <td>Parameter area<br><br></td>
1832 <td>Dynamic area<br><br></td>
1835 <td>Locals area<br><br></td>
1838 <td>Saved registers area<br><br></td>
1840 <tr style="border-style: none hidden none hidden;">
1844 <td>Previous Frame<br><br></td>
1849 <div class="doc_text">
1850 <p>The <i>linkage</i> area is used by a callee to save special registers prior
1851 to allocating its own frame. Only three entries are relevant to LLVM. The
1852 first entry is the previous stack pointer (sp), aka link. This allows probing
1853 tools like gdb or exception handlers to quickly scan the frames in the stack. A
1854 function epilog can also use the link to pop the frame from the stack. The
1855 third entry in the linkage area is used to save the return address from the lr
1856 register. Finally, as mentioned above, the last entry is used to save the
1857 previous frame pointer (r31.) The entries in the linkage area are the size of a
1858 GPR, thus the linkage area is 24 bytes long in 32 bit mode and 48 bytes in 64
1862 <div class="doc_text">
1863 <p>32 bit linkage area</p>
1864 <table class="layout">
1867 <td>Saved SP (r1)</td>
1887 <td>Saved FP (r31)</td>
1892 <div class="doc_text">
1893 <p>64 bit linkage area</p>
1894 <table class="layout">
1897 <td>Saved SP (r1)</td>
1917 <td>Saved FP (r31)</td>
1922 <div class="doc_text">
1923 <p>The <i>parameter area</i> is used to store arguments being passed to a callee
1924 function. Following the PowerPC ABI, the first few arguments are actually
1925 passed in registers, with the space in the parameter area unused. However, if
1926 there are not enough registers or the callee is a thunk or vararg function,
1927 these register arguments can be spilled into the parameter area. Thus, the
1928 parameter area must be large enough to store all the parameters for the largest
1929 call sequence made by the caller. The size must also be mimimally large enough
1930 to spill registers r3-r10. This allows callees blind to the call signature,
1931 such as thunks and vararg functions, enough space to cache the argument
1932 registers. Therefore, the parameter area is minimally 32 bytes (64 bytes in 64
1933 bit mode.) Also note that since the parameter area is a fixed offset from the
1934 top of the frame, that a callee can access its spilt arguments using fixed
1935 offsets from the stack pointer (or base pointer.)</p>
1938 <div class="doc_text">
1939 <p>Combining the information about the linkage, parameter areas and alignment. A
1940 stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
1944 <div class="doc_text">
1945 <p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
1946 alloca then space is added to the stack, the linkage and parameter areas are
1947 shifted to top of stack, and the new space is available immediately below the
1948 linkage and parameter areas. The cost of shifting the linkage and parameter
1949 areas is minor since only the link value needs to be copied. The link value can
1950 be easily fetched by adding the original frame size to the base pointer. Note
1951 that allocations in the dynamic space need to observe 16 byte aligment.</p>
1954 <div class="doc_text">
1955 <p>The <i>locals area</i> is where the llvm compiler reserves space for local
1959 <div class="doc_text">
1960 <p>The <i>saved registers area</i> is where the llvm compiler spills callee saved
1961 registers on entry to the callee.</p>
1964 <!-- _______________________________________________________________________ -->
1965 <div class="doc_subsubsection">
1966 <a name="ppc_prolog">Prolog/Epilog</a>
1969 <div class="doc_text">
1970 <p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
1971 the following exceptions. Callee saved registers are spilled after the frame is
1972 created. This allows the llvm epilog/prolog support to be common with other
1973 targets. The base pointer callee saved register r31 is saved in the TOC slot of
1974 linkage area. This simplifies allocation of space for the base pointer and
1975 makes it convenient to locate programatically and during debugging.</p>
1978 <!-- _______________________________________________________________________ -->
1979 <div class="doc_subsubsection">
1980 <a name="ppc_dynamic">Dynamic Allocation</a>
1983 <div class="doc_text">
1987 <div class="doc_text">
1988 <p><i>TODO - More to come.</i></p>
1992 <!-- *********************************************************************** -->
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