5 llc - LLVM static compiler
9 B<llc> [I<options>] [I<filename>]
13 The B<llc> command compiles LLVM bytecode into assembly language for a
14 specified architecture. The assembly language output can then be passed through
15 a native assembler and linker to generate a native executable.
17 The choice of architecture for the output assembly code is automatically
18 determined from the input bytecode file, unless the B<-march> option is used to
23 If I<filename> is - or omitted, B<llc> reads LLVM bytecode from standard input.
24 Otherwise, it will read LLVM bytecode from I<filename>.
26 If the B<-o> option is omitted, then B<llc> will send its output to standard
27 output if the input is from standard input. If the B<-o> option specifies -,
28 then the output will also be sent to standard output.
30 If no B<-o> option is specified and an input file other than - is specified,
31 then B<llc> creates the output filename by taking the input filename,
32 removing any existing F<.bc> extension, and adding a F<.s> suffix.
34 Other B<llc> options are as follows:
36 =head2 End-user Options
42 Print a summary of command line options.
46 Overwrite output files. By default, B<llc> will refuse to overwrite
47 an output file which already exists.
49 =item B<-mtriple>=I<target triple>
51 Override the target triple specified in the input bytecode file with the
54 =item B<-march>=I<arch>
56 Specify the architecture for which to generate assembly, overriding the target
57 encoded in the bytecode file. See the output of B<llc --help> for a list of
58 valid architectures. By default this is inferred from the target triple or
59 autodetected to the current architecture.
61 =item B<-mcpu>=I<cpuname>
63 Specify a specific chip in the current architecture to generate code for.
64 By default this is inferred from the target triple and autodetected to
65 the current architecture. For a list of available CPUs, use:
66 B<llvm-as E<lt> /dev/null | llc -march=xyz -mcpu=help>
68 =item B<-mattr>=I<a1,+a2,-a3,...>
70 Override or control specific attributes of the target, such as whether SIMD
71 operations are enabled or not. The default set of attributes is set by the
72 current CPU. For a list of available attributes, use:
73 B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help>
75 =item B<--disable-fp-elim>
77 Disable frame pointer elimination optimization.
79 =item B<--disable-excess-fp-precision>
81 Disable optimizations that may produce excess precision for floating point.
82 Note that this option can dramatically slow down code on some systems
85 =item B<--enable-unsafe-fp-math>
87 Enable optimizations that make unsafe assumptions about IEEE math (e.g. that
88 addition is associative) or may not work for all input ranges. These
89 optimizations allow the code generator to make use of some instructions which
90 would otherwise not be usable (such as fsin on X86).
92 =item B<--enable-correct-eh-support>
94 Instruct the B<lowerinvoke> pass to insert code for correct exception handling
95 support. This is expensive and is by default omitted for efficiency.
99 Print statistics recorded by code-generation passes.
101 =item B<--time-passes>
103 Record the amount of time needed for each pass and print a report to standard
106 =item B<--load>=F<dso_path>
108 Dynamically load F<dso_path> (a path to a dynamically shared object) that
109 implements an LLVM target. This will permit the target name to be used with the
110 B<-march> option so that code can be generated for that target.
114 =head2 Tuning/Configuration Options
118 =item B<--print-machineinstrs>
120 Print generated machine code between compilation phases (useful for debugging).
122 =item B<--regalloc>=I<allocator>
124 Specify the register allocator to use. The default I<allocator> is I<local>.
125 Valid register allocators are:
131 Very simple "always spill" register allocator
135 Local register allocator
139 Linear scan global register allocator
141 =item I<iterativescan>
143 Iterative scan global register allocator
147 =item B<--spiller>=I<spiller>
149 Specify the spiller to use for register allocators that support it. Currently
150 this option is used only by the linear scan register allocator. The default
151 I<spiller> is I<local>. Valid spillers are:
167 =head2 Intel IA-32-specific Options
171 =item B<--x86-asm-syntax=att|intel>
173 Specify whether to emit assembly code in AT&T syntax (the default) or intel
180 If B<llc> succeeds, it will exit with 0. Otherwise, if an error occurs,
181 it will exit with a non-zero value.
189 Maintained by the LLVM Team (L<http://llvm.org>).