5 llc - LLVM static compiler
9 B<llc> [I<options>] [I<filename>]
13 The B<llc> command compiles LLVM bytecode into assembly language for a
14 specified architecture. The assembly language output can then be passed through
15 a native assembler and linker to generate native code.
17 The choice of architecture for the output assembly code is determined as
18 follows, by attempting to satisfy each of the following rules in turn (first
25 If the user has specified an architecture with the -m option, use that
30 Examine the input LLVM bytecode file: if it is little endian and has a
31 pointer size of 32 bits, select the Intel IA-32 architecture. If it is big
32 endian and has a pointer size of 64 bits, select the SparcV9 architecture.
36 If B<llc> was compiled on an architecture for which it can generate code, select
37 the architecture upon which B<llc> was compiled.
41 Exit with an error message telling the user to specify the output
42 architecture explicitly.
48 If I<filename> is - or omitted, B<llc> reads LLVM bytecode from standard input.
49 Otherwise, it will read LLVM bytecode from I<filename>.
51 If the B<-o> option is omitted, then B<llc> will send its output to standard
52 output if the input is from standard input. If the B<-o> option specifies -,
53 then the output will also be sent to standard output.
55 If no B<-o> option is specified and an input file other than - is specified,
56 then B<llc> creates the output filename by taking the input filename,
57 removing any existing F<.bc> extension, and adding a F<.s> suffix.
59 Other B<llc> options are as follows:
65 Overwrite output files. By default, B<llc> will refuse to overwrite
66 an output file which already exists.
68 =item B<-march>=I<arch>
70 Specify the architecture for which to generate assembly. Valid
77 Intel IA-32 (Pentium and above)
85 Emit C code, not assembly
89 =item B<-enable-correct-eh-support>
91 Instruct the B<-lowerinvoke> pass to insert code for correct exception handling
92 support. This is expensive and is by default omitted for efficiency.
96 Print a summary of command line options.
100 Print statistics recorded by code-generation passes.
102 =item B<-time-passes>
104 Record the amount of time needed for each pass and print a report to standard
109 =head2 Intel IA-32-specific Options
113 =item B<--disable-fp-elim>
115 Disable frame pointer elimination optimization.
117 =item B<--disable-pattern-isel>
119 Use the 'simple' X86 instruction selector (the default).
121 =item B<--print-machineinstrs>
123 Print generated machine code.
125 =item B<--regalloc>=I<allocator>
127 Specify the register allocator to use. The default I<allocator> is I<local>.
128 Valid register allocators are:
134 Very simple "always spill" register allocator
138 Local register allocator
142 Linear scan global register allocator
144 =item I<iterativerscan>
146 Iterative scan global register allocator
150 =item B<--spiller>=I<spiller>
152 Specify the spiller to use for register allocators that support it. Currently
153 this option is used only by the linear scan register allocator. The default
154 I<spiller> is I<local>. Valid spillers are:
170 =head2 SPARCV9-specific Options
174 =item B<--disable-peephole>
176 Disable peephole optimization pass.
178 =item B<--disable-sched>
180 Disable local scheduling pass.
182 =item B<--disable-strip>
184 The Sparc backend embeds the LLVM bytecode into the assembly output. This
185 option requests that symbol names be retained; by default, they are stripped out.
187 =item B<--enable-maps>
189 Emit LLVM-to-machine code mapping information into the assembly output.
195 If B<llc> succeeds, it will exit with 0. Otherwise, if an error occurs,
196 it will exit with a non-zero value.
204 Maintained by the LLVM Team (L<http://llvm.cs.uiuc.edu>).