1 tblgen - Target Description To C++ Code Generator
2 =================================================
7 :program:`tblgen` [*options*] [*filename*]
12 :program:`tblgen` translates from target description (``.td``) files into C++
13 code that can be included in the definition of an LLVM target library. Most
14 users of LLVM will not need to use this program. It is only for assisting with
15 writing an LLVM target backend.
17 The input and output of :program:`tblgen` is beyond the scope of this short
18 introduction. Please see :doc:`../TableGenFundamentals`.
20 The *filename* argument specifies the name of a Target Description (``.td``)
21 file to read as input.
28 Print a summary of command line options.
30 .. option:: -o filename
32 Specify the output file name. If ``filename`` is ``-``, then
33 :program:`tblgen` sends its output to standard output.
35 .. option:: -I directory
37 Specify where to find other target description files for inclusion. The
38 ``directory`` value should be a full or partial path to a directory that
39 contains target description files.
41 .. option:: -asmparsernum N
43 Make -gen-asm-parser emit assembly writer number ``N``.
45 .. option:: -asmwriternum N
47 Make -gen-asm-writer emit assembly writer number ``N``.
49 .. option:: -class className
51 Print the enumeration list for this class.
53 .. option:: -print-records
55 Print all records to standard output (default).
57 .. option:: -print-enums
59 Print enumeration values for a class
61 .. option:: -print-sets
63 Print expanded sets for testing DAG exprs.
65 .. option:: -gen-emitter
67 Generate machine code emitter.
69 .. option:: -gen-register-info
71 Generate registers and register classes info.
73 .. option:: -gen-instr-info
75 Generate instruction descriptions.
77 .. option:: -gen-asm-writer
79 Generate the assembly writer.
81 .. option:: -gen-disassembler
83 Generate disassembler.
85 .. option:: -gen-pseudo-lowering
87 Generate pseudo instruction lowering.
89 .. option:: -gen-dag-isel
91 Generate a DAG (Directed Acycle Graph) instruction selector.
93 .. option:: -gen-asm-matcher
95 Generate assembly instruction matcher.
97 .. option:: -gen-dfa-packetizer
99 Generate DFA Packetizer for VLIW targets.
101 .. option:: -gen-fast-isel
103 Generate a "fast" instruction selector.
105 .. option:: -gen-subtarget
107 Generate subtarget enumerations.
109 .. option:: -gen-intrinsic
111 Generate intrinsic information.
113 .. option:: -gen-tgt-intrinsic
115 Generate target intrinsic information.
117 .. option:: -gen-enhanced-disassembly-info
119 Generate enhanced disassembly info.
123 Show the version number of this program.
128 If :program:`tblgen` succeeds, it will exit with 0. Otherwise, if an error
129 occurs, it will exit with a non-zero value.