1 tblgen - Target Description To C++ Code Generator
2 =================================================
7 :program:`tblgen` [*options*] [*filename*]
12 :program:`tblgen` translates from target description (``.td``) files into C++
13 code that can be included in the definition of an LLVM target library. Most
14 users of LLVM will not need to use this program. It is only for assisting with
15 writing an LLVM target backend.
17 The input and output of :program:`tblgen` is beyond the scope of this short
18 introduction. Please see :doc:`../TableGenFundamentals`.
20 The *filename* argument specifies the name of a Target Description (``.td``)
21 file to read as input.
30 Print a summary of command line options.
32 .. option:: -o filename
34 Specify the output file name. If ``filename`` is ``-``, then
35 :program:`tblgen` sends its output to standard output.
37 .. option:: -I directory
39 Specify where to find other target description files for inclusion. The
40 ``directory`` value should be a full or partial path to a directory that
41 contains target description files.
43 .. option:: -asmparsernum N
45 Make -gen-asm-parser emit assembly writer number ``N``.
47 .. option:: -asmwriternum N
49 Make -gen-asm-writer emit assembly writer number ``N``.
51 .. option:: -class className
53 Print the enumeration list for this class.
55 .. option:: -print-records
57 Print all records to standard output (default).
59 .. option:: -print-enums
61 Print enumeration values for a class.
63 .. option:: -print-sets
65 Print expanded sets for testing DAG exprs.
67 .. option:: -gen-emitter
69 Generate machine code emitter.
71 .. option:: -gen-register-info
73 Generate registers and register classes info.
75 .. option:: -gen-instr-info
77 Generate instruction descriptions.
79 .. option:: -gen-asm-writer
81 Generate the assembly writer.
83 .. option:: -gen-disassembler
85 Generate disassembler.
87 .. option:: -gen-pseudo-lowering
89 Generate pseudo instruction lowering.
91 .. option:: -gen-dag-isel
93 Generate a DAG (Directed Acycle Graph) instruction selector.
95 .. option:: -gen-asm-matcher
97 Generate assembly instruction matcher.
99 .. option:: -gen-dfa-packetizer
101 Generate DFA Packetizer for VLIW targets.
103 .. option:: -gen-fast-isel
105 Generate a "fast" instruction selector.
107 .. option:: -gen-subtarget
109 Generate subtarget enumerations.
111 .. option:: -gen-intrinsic
113 Generate intrinsic information.
115 .. option:: -gen-tgt-intrinsic
117 Generate target intrinsic information.
119 .. option:: -gen-enhanced-disassembly-info
121 Generate enhanced disassembly info.
125 Show the version number of this program.
130 If :program:`tblgen` succeeds, it will exit with 0. Otherwise, if an error
131 occurs, it will exit with a non-zero value.