9 These are in-progress notes for the upcoming LLVM 3.3 release. You may
10 prefer the `LLVM 3.2 Release Notes <http://llvm.org/releases/3.2/docs
11 /ReleaseNotes.html>`_.
17 This document contains the release notes for the LLVM Compiler Infrastructure,
18 release 3.3. Here we describe the status of LLVM, including major improvements
19 from the previous release, improvements in various subprojects of LLVM, and
20 some of the current users of the code. All LLVM releases may be downloaded
21 from the `LLVM releases web site <http://llvm.org/releases/>`_.
23 For more information about LLVM, including information about the latest
24 release, please check out the `main LLVM web site <http://llvm.org/>`_. If you
25 have questions or comments, the `LLVM Developer's Mailing List
26 <http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev>`_ is a good place to send
29 Note that if you are reading this file from a Subversion checkout or the main
30 LLVM web page, this document applies to the *next* release, not the current
31 one. To see the release notes for a specific release, please see the `releases
32 page <http://llvm.org/releases/>`_.
34 Non-comprehensive list of changes in this release
35 =================================================
38 For small 1-3 sentence descriptions, just add an entry at the end of
39 this list. If your description won't fit comfortably in one bullet
40 point (e.g. maybe you would like to give an example of the
41 functionality, or simply have a lot to talk about), see the `NOTE` below
42 for adding a new subsection.
44 * The CellSPU port has been removed. It can still be found in older versions.
46 * The IR-level extended linker APIs (for example, to link bitcode files out of
47 archives) have been removed. Any existing clients of these features should
48 move to using a linker with integrated LTO support.
50 * LLVM and Clang's documentation has been migrated to the `Sphinx
51 <http://sphinx-doc.org/>`_ documentation generation system which uses
52 easy-to-write reStructuredText. See `llvm/docs/README.txt` for more
55 * TargetTransformInfo (TTI) is a new interface that can be used by IR-level
56 passes to obtain target-specific information, such as the costs of
57 instructions. Only "Lowering" passes such as LSR and the vectorizer are
58 allowed to use the TTI infrastructure.
60 * We've improved the X86 and ARM cost model.
62 * The Attributes classes have been completely rewritten and expanded. They now
63 support not only enumerated attributes and alignments, but "string"
64 attributes, which are useful for passing information to code generation. See
65 :doc:`HowToUseAttributes` for more details.
67 * TableGen's syntax for instruction selection patterns has been simplified.
68 Instead of specifying types indirectly with register classes, you should now
69 specify types directly in the input patterns. See ``SparcInstrInfo.td`` for
70 examples of the new syntax. The old syntax using register classes still
71 works, but it will be removed in a future LLVM release.
73 * MCJIT now supports exception handling. Support for it in the old jit will be
74 removed in the 3.4 release.
79 If you would like to document a larger change, then you can add a
80 subsection about it right here. You can copy the following boilerplate
81 and un-indent it (the indentation causes it to be inside this comment).
86 Makes programs 10x faster by doing Special New Thing.
91 We've added support for AArch64, ARM's 64-bit architecture. Development is still
92 in fairly early stages, but we expect successful compilation when:
94 - compiling standard compliant C99 and C++03 with Clang;
95 - using Linux as a target platform;
96 - where code + static data doesn't exceed 4GB in size (heap allocated data has
99 Some additional functionality is also implemented, notably DWARF debugging,
100 GNU-style thread local storage and inline assembly.
105 - Removed support for legacy hexagonv2 and hexagonv3 processor
106 architectures which are no longer in use. Currently supported
107 architectures are hexagonv4 and hexagonv5.
112 We've continued the work on the loop vectorizer. The loop vectorizer now
113 has the following features:
115 - Loops with unknown trip counts.
116 - Runtime checks of pointers.
117 - Reductions, Inductions.
118 - Min/Max reductions of integers.
120 - Pointer induction variables.
122 - Vectorization of mixed types.
123 - Vectorization of function calls.
124 - Partial unrolling during vectorization.
126 The loop vectorizer is now enabled by default for -O3.
131 LLVM now has a new SLP vectorizer. The new SLP vectorizer is not enabled by
132 default but can be enabled using the clang flag -fslp-vectorize. The BB-vectorizer
133 can also be enabled using the command line flag -fslp-vectorize-aggressive.
138 The R600 backend was added in this release, it supports AMD GPUs
139 (HD2XXX - HD7XXX). This backend is used in AMD's Open Source
140 graphics / compute drivers which are developed as part of the `Mesa3D
141 <http://www.mesa3d.org>`_ project.
144 External Open Source Projects Using LLVM 3.3
145 ============================================
147 An exciting aspect of LLVM is that it is used as an enabling technology for
148 a lot of other language and tools projects. This section lists some of the
149 projects that have already been updated to work with LLVM 3.3.
152 Portable Computing Language (pocl)
153 ----------------------------------
155 In addition to producing an easily portable open source OpenCL
156 implementation, another major goal of `pocl <http://pocl.sourceforge.net/>`_
157 is improving performance portability of OpenCL programs with
158 compiler optimizations, reducing the need for target-dependent manual
159 optimizations. An important part of pocl is a set of LLVM passes used to
160 statically parallelize multiple work-items with the kernel compiler, even in
161 the presence of work-group barriers. This enables static parallelization of
162 the fine-grained static concurrency in the work groups in multiple ways.
164 TTA-based Co-design Environment (TCE)
165 -------------------------------------
167 `TCE <http://tce.cs.tut.fi/>`_ is a toolset for designing new
168 processors based on the Transport triggered architecture (TTA).
169 The toolset provides a complete co-design flow from C/C++
170 programs down to synthesizable VHDL/Verilog and parallel program binaries.
171 Processor customization points include the register files, function units,
172 supported operations, and the interconnection network.
174 TCE uses Clang and LLVM for C/C++/OpenCL C language support, target independent
175 optimizations and also for parts of code generation. It generates new
176 LLVM-based code generators "on the fly" for the designed TTA processors and
177 loads them in to the compiler backend as runtime libraries to avoid
178 per-target recompilation of larger parts of the compiler chain.
181 Additional Information
182 ======================
184 A wide variety of additional information is available on the `LLVM web page
185 <http://llvm.org/>`_, in particular in the `documentation
186 <http://llvm.org/docs/>`_ section. The web page also contains versions of the
187 API documentation which is up-to-date with the Subversion version of the source
188 code. You can access versions of these documents specific to this release by
189 going into the ``llvm/docs/`` directory in the LLVM tree.
191 If you have any questions or comments about LLVM, please feel free to contact
192 us via the `mailing lists <http://llvm.org/docs/#maillist>`_.