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5 <title>Writing an LLVM backend</title>
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11 <div class="doc_title">
12 Writing an LLVM backend
16 <li><a href="#intro">Introduction</a>
17 <li><a href="#backends">Writing a backend</a>
19 <li><a href="#machine">Machine backends</a>
21 <li><a href="#machineTOC">Outline</a></li>
22 <li><a href="#machineDetails">Implementation details</a></li>
24 <li><a href="#lang">Language backends</a></li>
26 <li><a href="#related">Related reading material</a>
29 <div class="doc_author">
30 <p>Written by <a href="http://misha.brukman.net">Misha Brukman</a></p>
33 <!-- *********************************************************************** -->
34 <div class="doc_section">
35 <a name="intro">Introduction</a>
37 <!-- *********************************************************************** -->
39 <div class="doc_text">
41 <p>This document describes techniques for writing backends for LLVM which
42 convert the LLVM representation to machine assembly code or other languages.</p>
46 <!-- *********************************************************************** -->
47 <div class="doc_section">
48 <a name="backends">Writing a backend</a>
50 <!-- *********************************************************************** -->
52 <!-- ======================================================================= -->
53 <div class="doc_subsection">
54 <a name="machine">Machine backends</a>
57 <!-- _______________________________________________________________________ -->
58 <div class="doc_subsubsection">
59 <a name="machineTOC">Outline</a>
62 <div class="doc_text">
64 <p>In general, you want to follow the format of SPARC, X86 or PowerPC (in
65 <tt>lib/Target</tt>). SPARC is the simplest backend, and is RISC, so if
66 you're working on a RISC target, it is a good one to start with.</p>
68 <p>To create a static compiler (one that emits text assembly), you need to
69 implement the following:</p>
72 <li>Describe the register set.
74 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
75 the register set and register classes</li>
76 <li>Implement a subclass of <tt><a
77 href="CodeGenerator.html#mregisterinfo">MRegisterInfo</a></tt></li>
79 <li>Describe the instruction set.
81 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
82 the instruction set</li>
83 <li>Implement a subclass of <tt><a
84 href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a></tt></li>
86 <li>Describe the target machine.
88 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
89 the target that describes the pointer size and references the instruction
91 <li>Implement a subclass of <tt><a
92 href="CodeGenerator.html#targetmachine">TargetMachine</a></tt>, which
93 configures <tt><a href="CodeGenerator.html#targetdata">TargetData</a></tt>
95 <li>Register your new target using the <tt>RegisterTarget</tt>
97 <div class="doc_code"><pre>
98 RegisterTarget<<em>MyTargetMachine</em>> M("short_name", " Target name");
100 <br>Here, <em>MyTargetMachine</em> is the name of your implemented
102 href="CodeGenerator.html#targetmachine">TargetMachine</a></tt>,
103 <em>short_name</em> is the option that will be active following
104 <tt>-march=</tt> to select a target in llc and lli, and the last string
105 is the description of your target to appear in <tt>-help</tt>
108 <li>Implement the assembly printer for the architecture.
110 <li>Define all of the assembly strings for your target, adding them to the
111 instructions in your *InstrInfo.td file.</li>
112 <li>Implement the <tt>llvm::AsmPrinter</tt> interface.</li>
115 <li>Implement an instruction selector for the architecture.
117 <li>The recommended method is the <a href="CodeGenerator.html#instselect">
118 pattern-matching DAG-to-DAG instruction selector</a> (for example, see
119 the PowerPC backend in PPCISelDAGtoDAG.cpp). Parts of instruction
120 selector creation can be performed by adding patterns to the instructions
121 in your <tt>.td</tt> file.</li>
124 <li>Optionally, add subtarget support.
126 <li>If your target has multiple subtargets (e.g. variants with different
127 capabilities), implement the <tt>llvm::TargetSubtarget</tt> interface
128 for your architecture. This allows you to add <tt>-mcpu=</tt> and
129 <tt>-mattr=</tt> options.</li>
131 <li>Optionally, add JIT support.
133 <li>Create a subclass of <tt><a
134 href="CodeGenerator.html#targetjitinfo">TargetJITInfo</a></tt></li>
135 <li>Create a machine code emitter that will be used to emit binary code
136 directly into memory, given <tt>MachineInstr</tt>s</li>
141 <!-- _______________________________________________________________________ -->
142 <div class="doc_subsubsection">
143 <a name="machineDetails">Implementation details</a>
146 <div class="doc_text">
150 <li><p><b>TableGen register info description</b> - describe a class which
151 will store the register's number in the binary encoding of the instruction
152 (e.g., for JIT purposes).</p>
154 <p>You also need to define register classes to contain these registers, such as
155 the integer register class and floating-point register class, so that you can
156 allocate virtual registers to instructions from these sets, and let the
157 target-independent register allocator automatically choose the actual
158 architected registers.</p>
160 <div class="doc_code">
162 // class Register is defined in Target.td
163 <b>class</b> <em>Target</em>Reg<string name> : Register<name> {
164 <b>let</b> Namespace = "<em>Target</em>";
167 <b>class</b> IntReg<<b>bits</b><5> num, string name> : <em>Target</em>Reg<name> {
168 <b>field</b> <b>bits</b><5> Num = num;
171 <b>def</b> R0 : IntReg<0, "%R0">;
174 // class RegisterClass is defined in Target.td
175 <b>def</b> IReg : RegisterClass<i64, 64, [R0, ... ]>;
180 <li><p><b>TableGen instruction info description</b> - break up instructions into
181 classes, usually that's already done by the manufacturer (see instruction
182 manual). Define a class for each instruction category. Define each opcode as a
183 subclass of the category, with appropriate parameters such as the fixed binary
184 encoding of opcodes and extended opcodes, and map the register bits to the bits
185 of the instruction which they are encoded in (for the JIT). Also specify how
186 the instruction should be printed so it can use the automatic assembly printer,
189 <div class="doc_code">
191 // class Instruction is defined in Target.td
192 <b>class</b> Form<<b>bits</b><6> opcode, <b>dag</b> OL, <b>string</b> asmstr> : Instruction {
193 <b>field</b> <b>bits</b><42> Inst;
195 <b>let</b> Namespace = "<em>Target</em>";
196 <b>let</b> Inst{0-6} = opcode;
197 <b>let</b> OperandList = OL;
198 <b>let</b> AsmString = asmstr;
201 <b>def</b> ADD : Form<42, (ops IReg:$rD, IReg:$rA, IReg:$rB), "add $rD, $rA, $rB">;
210 <!-- ======================================================================= -->
211 <div class="doc_subsection">
212 <a name="lang">Language backends</a>
215 <div class="doc_text">
217 <p>For now, just take a look at <tt>lib/Target/CBackend</tt> for an example of
218 how the C backend is written.</p>
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223 <div class="doc_section">
224 <a name="related">Related reading material</a>
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228 <div class="doc_text">
231 <li><a href="CodeGenerator.html">Code generator</a> -
232 describes some of the classes in code generation at a high level, but
233 it is not (yet) complete</li>
234 <li><a href="TableGenFundamentals.html">TableGen fundamentals</a> -
235 describes how to use TableGen to describe your target information
237 <li><a href="HowToSubmitABug.html#codegen">Debugging code generation with
238 bugpoint</a> - shows bugpoint usage scenarios to simplify backend
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253 <a href="http://misha.brukman.net">Misha Brukman</a><br>
254 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a>
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