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12 <div class="doc_title">
13 Writing an LLVM Compiler Backend
17 <li><a href="#intro">Introduction</a>
19 <li><a href="#Audience">Audience</a></li>
20 <li><a href="#Prerequisite">Prerequisite Reading</a></li>
21 <li><a href="#Basic">Basic Steps</a></li>
22 <li><a href="#Preliminaries">Preliminaries</a></li>
24 <li><a href="#TargetMachine">Target Machine</a></li>
25 <li><a href="#TargetRegistration">Target Registration</a></li>
26 <li><a href="#RegisterSet">Register Set and Register Classes</a>
28 <li><a href="#RegisterDef">Defining a Register</a></li>
29 <li><a href="#RegisterClassDef">Defining a Register Class</a></li>
30 <li><a href="#implementRegister">Implement a subclass of TargetRegisterInfo</a></li>
32 <li><a href="#InstructionSet">Instruction Set</a>
34 <li><a href="#operandMapping">Instruction Operand Mapping</a></li>
35 <li><a href="#implementInstr">Implement a subclass of TargetInstrInfo</a></li>
36 <li><a href="#branchFolding">Branch Folding and If Conversion</a></li>
38 <li><a href="#InstructionSelector">Instruction Selector</a>
40 <li><a href="#LegalizePhase">The SelectionDAG Legalize Phase</a>
42 <li><a href="#promote">Promote</a></li>
43 <li><a href="#expand">Expand</a></li>
44 <li><a href="#custom">Custom</a></li>
45 <li><a href="#legal">Legal</a></li>
47 <li><a href="#callingConventions">Calling Conventions</a></li>
49 <li><a href="#assemblyPrinter">Assembly Printer</a></li>
50 <li><a href="#subtargetSupport">Subtarget Support</a></li>
51 <li><a href="#jitSupport">JIT Support</a>
53 <li><a href="#mce">Machine Code Emitter</a></li>
54 <li><a href="#targetJITInfo">Target JIT Info</a></li>
58 <div class="doc_author">
59 <p>Written by <a href="http://www.woo.com">Mason Woo</a> and
60 <a href="http://misha.brukman.net">Misha Brukman</a></p>
63 <!-- *********************************************************************** -->
64 <div class="doc_section">
65 <a name="intro">Introduction</a>
67 <!-- *********************************************************************** -->
69 <div class="doc_text">
72 This document describes techniques for writing compiler backends that convert
73 the LLVM Intermediate Representation (IR) to code for a specified machine or
74 other languages. Code intended for a specific machine can take the form of
75 either assembly code or binary code (usable for a JIT compiler).
79 The backend of LLVM features a target-independent code generator that may create
80 output for several types of target CPUs — including X86, PowerPC, Alpha,
81 and SPARC. The backend may also be used to generate code targeted at SPUs of the
82 Cell processor or GPUs to support the execution of compute kernels.
86 The document focuses on existing examples found in subdirectories
87 of <tt>llvm/lib/Target</tt> in a downloaded LLVM release. In particular, this
88 document focuses on the example of creating a static compiler (one that emits
89 text assembly) for a SPARC target, because SPARC has fairly standard
90 characteristics, such as a RISC instruction set and straightforward calling
96 <div class="doc_subsection">
97 <a name="Audience">Audience</a>
100 <div class="doc_text">
103 The audience for this document is anyone who needs to write an LLVM backend to
104 generate code for a specific hardware or software target.
109 <div class="doc_subsection">
110 <a name="Prerequisite">Prerequisite Reading</a>
113 <div class="doc_text">
116 These essential documents must be read before reading this document:
120 <li><i><a href="http://www.llvm.org/docs/LangRef.html">LLVM Language Reference
121 Manual</a></i> — a reference manual for the LLVM assembly language.</li>
123 <li><i><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
124 Target-Independent Code Generator</a></i> — a guide to the components
125 (classes and code generation algorithms) for translating the LLVM internal
126 representation into machine code for a specified target. Pay particular
127 attention to the descriptions of code generation stages: Instruction
128 Selection, Scheduling and Formation, SSA-based Optimization, Register
129 Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations,
130 and Code Emission.</li>
132 <li><i><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen
133 Fundamentals</a></i> —a document that describes the TableGen
134 (<tt>tblgen</tt>) application that manages domain-specific information to
135 support LLVM code generation. TableGen processes input from a target
136 description file (<tt>.td</tt> suffix) and generates C++ code that can be
137 used for code generation.</li>
139 <li><i><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM
140 Pass</a></i> — The assembly printer is a <tt>FunctionPass</tt>, as are
141 several SelectionDAG processing steps.</li>
145 To follow the SPARC examples in this document, have a copy of
146 <i><a href="http://www.sparc.org/standards/V8.pdf">The SPARC Architecture
147 Manual, Version 8</a></i> for reference. For details about the ARM instruction
148 set, refer to the <i><a href="http://infocenter.arm.com/">ARM Architecture
149 Reference Manual</a></i>. For more about the GNU Assembler format
151 <i><a href="http://sourceware.org/binutils/docs/as/index.html">Using As</a></i>,
152 especially for the assembly printer. <i>Using As</i> contains a list of target
153 machine dependent features.
158 <div class="doc_subsection">
159 <a name="Basic">Basic Steps</a>
162 <div class="doc_text">
165 To write a compiler backend for LLVM that converts the LLVM IR to code for a
166 specified target (machine or other language), follow these steps:
170 <li>Create a subclass of the TargetMachine class that describes characteristics
171 of your target machine. Copy existing examples of specific TargetMachine
172 class and header files; for example, start with
173 <tt>SparcTargetMachine.cpp</tt> and <tt>SparcTargetMachine.h</tt>, but
174 change the file names for your target. Similarly, change code that
175 references "Sparc" to reference your target. </li>
177 <li>Describe the register set of the target. Use TableGen to generate code for
178 register definition, register aliases, and register classes from a
179 target-specific <tt>RegisterInfo.td</tt> input file. You should also write
180 additional code for a subclass of the TargetRegisterInfo class that
181 represents the class register file data used for register allocation and
182 also describes the interactions between registers.</li>
184 <li>Describe the instruction set of the target. Use TableGen to generate code
185 for target-specific instructions from target-specific versions of
186 <tt>TargetInstrFormats.td</tt> and <tt>TargetInstrInfo.td</tt>. You should
187 write additional code for a subclass of the TargetInstrInfo class to
188 represent machine instructions supported by the target machine. </li>
190 <li>Describe the selection and conversion of the LLVM IR from a Directed Acyclic
191 Graph (DAG) representation of instructions to native target-specific
192 instructions. Use TableGen to generate code that matches patterns and
193 selects instructions based on additional information in a target-specific
194 version of <tt>TargetInstrInfo.td</tt>. Write code
195 for <tt>XXXISelDAGToDAG.cpp</tt>, where XXX identifies the specific target,
196 to perform pattern matching and DAG-to-DAG instruction selection. Also write
197 code in <tt>XXXISelLowering.cpp</tt> to replace or remove operations and
198 data types that are not supported natively in a SelectionDAG. </li>
200 <li>Write code for an assembly printer that converts LLVM IR to a GAS format for
201 your target machine. You should add assembly strings to the instructions
202 defined in your target-specific version of <tt>TargetInstrInfo.td</tt>. You
203 should also write code for a subclass of AsmPrinter that performs the
204 LLVM-to-assembly conversion and a trivial subclass of TargetAsmInfo.</li>
206 <li>Optionally, add support for subtargets (i.e., variants with different
207 capabilities). You should also write code for a subclass of the
208 TargetSubtarget class, which allows you to use the <tt>-mcpu=</tt>
209 and <tt>-mattr=</tt> command-line options.</li>
211 <li>Optionally, add JIT support and create a machine code emitter (subclass of
212 TargetJITInfo) that is used to emit binary code directly into memory. </li>
216 In the <tt>.cpp</tt> and <tt>.h</tt>. files, initially stub up these methods and
217 then implement them later. Initially, you may not know which private members
218 that the class will need and which components will need to be subclassed.
223 <div class="doc_subsection">
224 <a name="Preliminaries">Preliminaries</a>
227 <div class="doc_text">
230 To actually create your compiler backend, you need to create and modify a few
231 files. The absolute minimum is discussed here. But to actually use the LLVM
232 target-independent code generator, you must perform the steps described in
233 the <a href="http://www.llvm.org/docs/CodeGenerator.html">LLVM
234 Target-Independent Code Generator</a> document.
238 First, you should create a subdirectory under <tt>lib/Target</tt> to hold all
239 the files related to your target. If your target is called "Dummy," create the
240 directory <tt>lib/Target/Dummy</tt>.
245 directory, create a <tt>Makefile</tt>. It is easiest to copy a
246 <tt>Makefile</tt> of another target and modify it. It should at least contain
247 the <tt>LEVEL</tt>, <tt>LIBRARYNAME</tt> and <tt>TARGET</tt> variables, and then
248 include <tt>$(LEVEL)/Makefile.common</tt>. The library can be
249 named <tt>LLVMDummy</tt> (for example, see the MIPS target). Alternatively, you
250 can split the library into <tt>LLVMDummyCodeGen</tt>
251 and <tt>LLVMDummyAsmPrinter</tt>, the latter of which should be implemented in a
252 subdirectory below <tt>lib/Target/Dummy</tt> (for example, see the PowerPC
257 Note that these two naming schemes are hardcoded into <tt>llvm-config</tt>.
258 Using any other naming scheme will confuse <tt>llvm-config</tt> and produce a
259 lot of (seemingly unrelated) linker errors when linking <tt>llc</tt>.
263 To make your target actually do something, you need to implement a subclass of
264 <tt>TargetMachine</tt>. This implementation should typically be in the file
265 <tt>lib/Target/DummyTargetMachine.cpp</tt>, but any file in
266 the <tt>lib/Target</tt> directory will be built and should work. To use LLVM's
267 target independent code generator, you should do what all current machine
268 backends do: create a subclass of <tt>LLVMTargetMachine</tt>. (To create a
269 target from scratch, create a subclass of <tt>TargetMachine</tt>.)
273 To get LLVM to actually build and link your target, you need to add it to
274 the <tt>TARGETS_TO_BUILD</tt> variable. To do this, you modify the configure
275 script to know about your target when parsing the <tt>--enable-targets</tt>
276 option. Search the configure script for <tt>TARGETS_TO_BUILD</tt>, add your
277 target to the lists there (some creativity required), and then
278 reconfigure. Alternatively, you can change <tt>autotools/configure.ac</tt> and
279 regenerate configure by running <tt>./autoconf/AutoRegen.sh</tt>.
284 <!-- *********************************************************************** -->
285 <div class="doc_section">
286 <a name="TargetMachine">Target Machine</a>
288 <!-- *********************************************************************** -->
290 <div class="doc_text">
293 <tt>LLVMTargetMachine</tt> is designed as a base class for targets implemented
294 with the LLVM target-independent code generator. The <tt>LLVMTargetMachine</tt>
295 class should be specialized by a concrete target class that implements the
296 various virtual methods. <tt>LLVMTargetMachine</tt> is defined as a subclass of
297 <tt>TargetMachine</tt> in <tt>include/llvm/Target/TargetMachine.h</tt>. The
298 <tt>TargetMachine</tt> class implementation (<tt>TargetMachine.cpp</tt>) also
299 processes numerous command-line options.
303 To create a concrete target-specific subclass of <tt>LLVMTargetMachine</tt>,
304 start by copying an existing <tt>TargetMachine</tt> class and header. You
305 should name the files that you create to reflect your specific target. For
306 instance, for the SPARC target, name the files <tt>SparcTargetMachine.h</tt> and
307 <tt>SparcTargetMachine.cpp</tt>.
311 For a target machine <tt>XXX</tt>, the implementation of
312 <tt>XXXTargetMachine</tt> must have access methods to obtain objects that
313 represent target components. These methods are named <tt>get*Info</tt>, and are
314 intended to obtain the instruction set (<tt>getInstrInfo</tt>), register set
315 (<tt>getRegisterInfo</tt>), stack frame layout (<tt>getFrameInfo</tt>), and
316 similar information. <tt>XXXTargetMachine</tt> must also implement the
317 <tt>getTargetData</tt> method to access an object with target-specific data
318 characteristics, such as data type size and alignment requirements.
322 For instance, for the SPARC target, the header file
323 <tt>SparcTargetMachine.h</tt> declares prototypes for several <tt>get*Info</tt>
324 and <tt>getTargetData</tt> methods that simply return a class member.
327 <div class="doc_code">
333 class SparcTargetMachine : public LLVMTargetMachine {
334 const TargetData DataLayout; // Calculates type size & alignment
335 SparcSubtarget Subtarget;
336 SparcInstrInfo InstrInfo;
337 TargetFrameInfo FrameInfo;
340 virtual const TargetAsmInfo *createTargetAsmInfo() const;
343 SparcTargetMachine(const Module &M, const std::string &FS);
345 virtual const SparcInstrInfo *getInstrInfo() const {return &InstrInfo; }
346 virtual const TargetFrameInfo *getFrameInfo() const {return &FrameInfo; }
347 virtual const TargetSubtarget *getSubtargetImpl() const{return &Subtarget; }
348 virtual const TargetRegisterInfo *getRegisterInfo() const {
349 return &InstrInfo.getRegisterInfo();
351 virtual const TargetData *getTargetData() const { return &DataLayout; }
352 static unsigned getModuleMatchQuality(const Module &M);
354 // Pass Pipeline Configuration
355 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
356 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
359 } // end namespace llvm
366 <div class="doc_text">
369 <li><tt>getInstrInfo()</tt></li>
370 <li><tt>getRegisterInfo()</tt></li>
371 <li><tt>getFrameInfo()</tt></li>
372 <li><tt>getTargetData()</tt></li>
373 <li><tt>getSubtargetImpl()</tt></li>
376 <p>For some targets, you also need to support the following methods:</p>
379 <li><tt>getTargetLowering()</tt></li>
380 <li><tt>getJITInfo()</tt></li>
384 In addition, the <tt>XXXTargetMachine</tt> constructor should specify a
385 <tt>TargetDescription</tt> string that determines the data layout for the target
386 machine, including characteristics such as pointer size, alignment, and
387 endianness. For example, the constructor for SparcTargetMachine contains the
391 <div class="doc_code">
393 SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS)
394 : DataLayout("E-p:32:32-f128:128:128"),
395 Subtarget(M, FS), InstrInfo(Subtarget),
396 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
403 <div class="doc_text">
405 <p>Hyphens separate portions of the <tt>TargetDescription</tt> string.</p>
408 <li>An upper-case "<tt>E</tt>" in the string indicates a big-endian target data
409 model. a lower-case "<tt>e</tt>" indicates little-endian.</li>
411 <li>"<tt>p:</tt>" is followed by pointer information: size, ABI alignment, and
412 preferred alignment. If only two figures follow "<tt>p:</tt>", then the
413 first value is pointer size, and the second value is both ABI and preferred
416 <li>Then a letter for numeric type alignment: "<tt>i</tt>", "<tt>f</tt>",
417 "<tt>v</tt>", or "<tt>a</tt>" (corresponding to integer, floating point,
418 vector, or aggregate). "<tt>i</tt>", "<tt>v</tt>", or "<tt>a</tt>" are
419 followed by ABI alignment and preferred alignment. "<tt>f</tt>" is followed
420 by three values: the first indicates the size of a long double, then ABI
421 alignment, and then ABI preferred alignment.</li>
426 <!-- *********************************************************************** -->
427 <div class="doc_section">
428 <a name="TargetRegistration">Target Registration</a>
430 <!-- *********************************************************************** -->
432 <div class="doc_text">
435 You must also register your target with the <tt>TargetRegistry</tt>, which is
436 what other LLVM tools use to be able to lookup and use your target at
437 runtime. The <tt>TargetRegistry</tt> can be used directly, but for most targets
438 there are helper templates which should take care of the work for you.</p>
441 All targets should declare a global <tt>Target</tt> object which is used to
442 represent the target during registration. Then, in the target's TargetInfo
443 library, the target should define that object and use
444 the <tt>RegisterTarget</tt> template to register the target. For example, the Sparc registration code looks like this:
447 <div class="doc_code">
449 Target llvm::TheSparcTarget;
451 extern "C" void LLVMInitializeSparcTargetInfo() {
452 RegisterTarget<Triple::sparc, /*HasJIT=*/false>
453 X(TheSparcTarget, "sparc", "Sparc");
459 This allows the <tt>TargetRegistry</tt> to look up the target by name or by
460 target triple. In addition, most targets will also register additional features
461 which are available in separate libraries. These registration steps are
462 separate, because some clients may wish to only link in some parts of the target
463 -- the JIT code generator does not require the use of the assembler printer, for
464 example. Here is an example of registering the Sparc assembly printer:
467 <div class="doc_code">
469 extern "C" void LLVMInitializeSparcAsmPrinter() {
470 RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
476 For more information, see
477 "<a href="/doxygen/TargetRegistry_8h-source.html">llvm/Target/TargetRegistry.h</a>".
482 <!-- *********************************************************************** -->
483 <div class="doc_section">
484 <a name="RegisterSet">Register Set and Register Classes</a>
486 <!-- *********************************************************************** -->
488 <div class="doc_text">
491 You should describe a concrete target-specific class that represents the
492 register file of a target machine. This class is called <tt>XXXRegisterInfo</tt>
493 (where <tt>XXX</tt> identifies the target) and represents the class register
494 file data that is used for register allocation. It also describes the
495 interactions between registers.
499 You also need to define register classes to categorize related registers. A
500 register class should be added for groups of registers that are all treated the
501 same way for some instruction. Typical examples are register classes for
502 integer, floating-point, or vector registers. A register allocator allows an
503 instruction to use any register in a specified register class to perform the
504 instruction in a similar manner. Register classes allocate virtual registers to
505 instructions from these sets, and register classes let the target-independent
506 register allocator automatically choose the actual registers.
510 Much of the code for registers, including register definition, register aliases,
511 and register classes, is generated by TableGen from <tt>XXXRegisterInfo.td</tt>
512 input files and placed in <tt>XXXGenRegisterInfo.h.inc</tt> and
513 <tt>XXXGenRegisterInfo.inc</tt> output files. Some of the code in the
514 implementation of <tt>XXXRegisterInfo</tt> requires hand-coding.
519 <!-- ======================================================================= -->
520 <div class="doc_subsection">
521 <a name="RegisterDef">Defining a Register</a>
524 <div class="doc_text">
527 The <tt>XXXRegisterInfo.td</tt> file typically starts with register definitions
528 for a target machine. The <tt>Register</tt> class (specified
529 in <tt>Target.td</tt>) is used to define an object for each register. The
530 specified string <tt>n</tt> becomes the <tt>Name</tt> of the register. The
531 basic <tt>Register</tt> object does not have any subregisters and does not
535 <div class="doc_code">
537 class Register<string n> {
538 string Namespace = "";
542 int SpillAlignment = 0;
543 list<Register> Aliases = [];
544 list<Register> SubRegs = [];
545 list<int> DwarfNumbers = [];
551 For example, in the <tt>X86RegisterInfo.td</tt> file, there are register
552 definitions that utilize the Register class, such as:
555 <div class="doc_code">
557 def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
562 This defines the register <tt>AL</tt> and assigns it values (with
563 <tt>DwarfRegNum</tt>) that are used by <tt>gcc</tt>, <tt>gdb</tt>, or a debug
564 information writer to identify a register. For register
565 <tt>AL</tt>, <tt>DwarfRegNum</tt> takes an array of 3 values representing 3
566 different modes: the first element is for X86-64, the second for exception
567 handling (EH) on X86-32, and the third is generic. -1 is a special Dwarf number
568 that indicates the gcc number is undefined, and -2 indicates the register number
569 is invalid for this mode.
573 From the previously described line in the <tt>X86RegisterInfo.td</tt> file,
574 TableGen generates this code in the <tt>X86GenRegisterInfo.inc</tt> file:
577 <div class="doc_code">
579 static const unsigned GR8[] = { X86::AL, ... };
581 const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
583 const TargetRegisterDesc RegisterDescriptors[] = {
585 { "AL", "AL", AL_AliasSet, Empty_SubRegsSet, Empty_SubRegsSet, AL_SuperRegsSet }, ...
590 From the register info file, TableGen generates a <tt>TargetRegisterDesc</tt>
591 object for each register. <tt>TargetRegisterDesc</tt> is defined in
592 <tt>include/llvm/Target/TargetRegisterInfo.h</tt> with the following fields:
595 <div class="doc_code">
597 struct TargetRegisterDesc {
598 const char *AsmName; // Assembly language name for the register
599 const char *Name; // Printable name for the reg (for debugging)
600 const unsigned *AliasSet; // Register Alias Set
601 const unsigned *SubRegs; // Sub-register set
602 const unsigned *ImmSubRegs; // Immediate sub-register set
603 const unsigned *SuperRegs; // Super-register set
608 TableGen uses the entire target description file (<tt>.td</tt>) to determine
609 text names for the register (in the <tt>AsmName</tt> and <tt>Name</tt> fields of
610 <tt>TargetRegisterDesc</tt>) and the relationships of other registers to the
611 defined register (in the other <tt>TargetRegisterDesc</tt> fields). In this
612 example, other definitions establish the registers "<tt>AX</tt>",
613 "<tt>EAX</tt>", and "<tt>RAX</tt>" as aliases for one another, so TableGen
614 generates a null-terminated array (<tt>AL_AliasSet</tt>) for this register alias
619 The <tt>Register</tt> class is commonly used as a base class for more complex
620 classes. In <tt>Target.td</tt>, the <tt>Register</tt> class is the base for the
621 <tt>RegisterWithSubRegs</tt> class that is used to define registers that need to
622 specify subregisters in the <tt>SubRegs</tt> list, as shown here:
625 <div class="doc_code">
627 class RegisterWithSubRegs<string n,
628 list<Register> subregs> : Register<n> {
629 let SubRegs = subregs;
635 In <tt>SparcRegisterInfo.td</tt>, additional register classes are defined for
636 SPARC: a Register subclass, SparcReg, and further subclasses: <tt>Ri</tt>,
637 <tt>Rf</tt>, and <tt>Rd</tt>. SPARC registers are identified by 5-bit ID
638 numbers, which is a feature common to these subclasses. Note the use of
639 '<tt>let</tt>' expressions to override values that are initially defined in a
640 superclass (such as <tt>SubRegs</tt> field in the <tt>Rd</tt> class).
643 <div class="doc_code">
645 class SparcReg<string n> : Register<n> {
646 field bits<5> Num;
647 let Namespace = "SP";
649 // Ri - 32-bit integer registers
650 class Ri<bits<5> num, string n> :
654 // Rf - 32-bit floating-point registers
655 class Rf<bits<5> num, string n> :
659 // Rd - Slots in the FP register file for 64-bit
660 floating-point values.
661 class Rd<bits<5> num, string n,
662 list<Register> subregs> : SparcReg<n> {
664 let SubRegs = subregs;
670 In the <tt>SparcRegisterInfo.td</tt> file, there are register definitions that
671 utilize these subclasses of <tt>Register</tt>, such as:
674 <div class="doc_code">
676 def G0 : Ri< 0, "G0">,
677 DwarfRegNum<[0]>;
678 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
680 def F0 : Rf< 0, "F0">,
681 DwarfRegNum<[32]>;
682 def F1 : Rf< 1, "F1">,
683 DwarfRegNum<[33]>;
685 def D0 : Rd< 0, "F0", [F0, F1]>,
686 DwarfRegNum<[32]>;
687 def D1 : Rd< 2, "F2", [F2, F3]>,
688 DwarfRegNum<[34]>;
693 The last two registers shown above (<tt>D0</tt> and <tt>D1</tt>) are
694 double-precision floating-point registers that are aliases for pairs of
695 single-precision floating-point sub-registers. In addition to aliases, the
696 sub-register and super-register relationships of the defined register are in
697 fields of a register's TargetRegisterDesc.
702 <!-- ======================================================================= -->
703 <div class="doc_subsection">
704 <a name="RegisterClassDef">Defining a Register Class</a>
707 <div class="doc_text">
710 The <tt>RegisterClass</tt> class (specified in <tt>Target.td</tt>) is used to
711 define an object that represents a group of related registers and also defines
712 the default allocation order of the registers. A target description file
713 <tt>XXXRegisterInfo.td</tt> that uses <tt>Target.td</tt> can construct register
714 classes using the following class:
717 <div class="doc_code">
719 class RegisterClass<string namespace,
720 list<ValueType> regTypes, int alignment,
721 list<Register> regList> {
722 string Namespace = namespace;
723 list<ValueType> RegTypes = regTypes;
724 int Size = 0; // spill size, in bits; zero lets tblgen pick the size
725 int Alignment = alignment;
727 // CopyCost is the cost of copying a value between two registers
728 // default value 1 means a single instruction
729 // A negative value means copying is extremely expensive or impossible
731 list<Register> MemberList = regList;
733 // for register classes that are subregisters of this class
734 list<RegisterClass> SubRegClassList = [];
736 code MethodProtos = [{}]; // to insert arbitrary code
737 code MethodBodies = [{}];
742 <p>To define a RegisterClass, use the following 4 arguments:</p>
745 <li>The first argument of the definition is the name of the namespace.</li>
747 <li>The second argument is a list of <tt>ValueType</tt> register type values
748 that are defined in <tt>include/llvm/CodeGen/ValueTypes.td</tt>. Defined
749 values include integer types (such as <tt>i16</tt>, <tt>i32</tt>,
750 and <tt>i1</tt> for Boolean), floating-point types
751 (<tt>f32</tt>, <tt>f64</tt>), and vector types (for example, <tt>v8i16</tt>
752 for an <tt>8 x i16</tt> vector). All registers in a <tt>RegisterClass</tt>
753 must have the same <tt>ValueType</tt>, but some registers may store vector
754 data in different configurations. For example a register that can process a
755 128-bit vector may be able to handle 16 8-bit integer elements, 8 16-bit
756 integers, 4 32-bit integers, and so on. </li>
758 <li>The third argument of the <tt>RegisterClass</tt> definition specifies the
759 alignment required of the registers when they are stored or loaded to
762 <li>The final argument, <tt>regList</tt>, specifies which registers are in this
763 class. If an <tt>allocation_order_*</tt> method is not specified,
764 then <tt>regList</tt> also defines the order of allocation used by the
765 register allocator.</li>
769 In <tt>SparcRegisterInfo.td</tt>, three RegisterClass objects are defined:
770 <tt>FPRegs</tt>, <tt>DFPRegs</tt>, and <tt>IntRegs</tt>. For all three register
771 classes, the first argument defines the namespace with the string
772 '<tt>SP</tt>'. <tt>FPRegs</tt> defines a group of 32 single-precision
773 floating-point registers (<tt>F0</tt> to <tt>F31</tt>); <tt>DFPRegs</tt> defines
774 a group of 16 double-precision registers
775 (<tt>D0-D15</tt>). For <tt>IntRegs</tt>, the <tt>MethodProtos</tt>
776 and <tt>MethodBodies</tt> methods are used by TableGen to insert the specified
777 code into generated output.
780 <div class="doc_code">
782 def FPRegs : RegisterClass<"SP", [f32], 32,
783 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,
784 F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
786 def DFPRegs : RegisterClass<"SP", [f64], 64,
787 [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15]>;
789 def IntRegs : RegisterClass<"SP", [i32], 32,
790 [L0, L1, L2, L3, L4, L5, L6, L7,
791 I0, I1, I2, I3, I4, I5,
792 O0, O1, O2, O3, O4, O5, O7,
794 // Non-allocatable regs:
798 I7, // return address
800 G5, G6, G7 // reserved for kernel
802 let MethodProtos = [{
803 iterator allocation_order_end(const MachineFunction &MF) const;
805 let MethodBodies = [{
806 IntRegsClass::iterator
807 IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
808 return end() - 10 // Don't allocate special registers
817 Using <tt>SparcRegisterInfo.td</tt> with TableGen generates several output files
818 that are intended for inclusion in other source code that you write.
819 <tt>SparcRegisterInfo.td</tt> generates <tt>SparcGenRegisterInfo.h.inc</tt>,
820 which should be included in the header file for the implementation of the SPARC
821 register implementation that you write (<tt>SparcRegisterInfo.h</tt>). In
822 <tt>SparcGenRegisterInfo.h.inc</tt> a new structure is defined called
823 <tt>SparcGenRegisterInfo</tt> that uses <tt>TargetRegisterInfo</tt> as its
824 base. It also specifies types, based upon the defined register
825 classes: <tt>DFPRegsClass</tt>, <tt>FPRegsClass</tt>, and <tt>IntRegsClass</tt>.
829 <tt>SparcRegisterInfo.td</tt> also generates <tt>SparcGenRegisterInfo.inc</tt>,
830 which is included at the bottom of <tt>SparcRegisterInfo.cpp</tt>, the SPARC
831 register implementation. The code below shows only the generated integer
832 registers and associated register classes. The order of registers
833 in <tt>IntRegs</tt> reflects the order in the definition of <tt>IntRegs</tt> in
834 the target description file. Take special note of the use
835 of <tt>MethodBodies</tt> in <tt>SparcRegisterInfo.td</tt> to create code in
836 <tt>SparcGenRegisterInfo.inc</tt>. <tt>MethodProtos</tt> generates similar code
837 in <tt>SparcGenRegisterInfo.h.inc</tt>.
840 <div class="doc_code">
841 <pre> // IntRegs Register Class...
842 static const unsigned IntRegs[] = {
843 SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5,
844 SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3,
845 SP::I4, SP::I5, SP::O0, SP::O1, SP::O2, SP::O3,
846 SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3,
847 SP::G4, SP::O6, SP::I6, SP::I7, SP::G0, SP::G5,
851 // IntRegsVTs Register Class Value Types...
852 static const MVT::ValueType IntRegsVTs[] = {
856 namespace SP { // Register class instances
857 DFPRegsClass DFPRegsRegClass;
858 FPRegsClass FPRegsRegClass;
859 IntRegsClass IntRegsRegClass;
861 // IntRegs Sub-register Classess...
862 static const TargetRegisterClass* const IntRegsSubRegClasses [] = {
866 // IntRegs Super-register Classess...
867 static const TargetRegisterClass* const IntRegsSuperRegClasses [] = {
871 // IntRegs Register Class sub-classes...
872 static const TargetRegisterClass* const IntRegsSubclasses [] = {
876 // IntRegs Register Class super-classes...
877 static const TargetRegisterClass* const IntRegsSuperclasses [] = {
881 IntRegsClass::iterator
882 IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
883 return end()-10 // Don't allocate special registers
887 IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID,
888 IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses,
889 IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
896 <!-- ======================================================================= -->
897 <div class="doc_subsection">
898 <a name="implementRegister">Implement a subclass of</a>
899 <a href="http://www.llvm.org/docs/CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a>
902 <div class="doc_text">
905 The final step is to hand code portions of <tt>XXXRegisterInfo</tt>, which
906 implements the interface described in <tt>TargetRegisterInfo.h</tt>. These
907 functions return <tt>0</tt>, <tt>NULL</tt>, or <tt>false</tt>, unless
908 overridden. Here is a list of functions that are overridden for the SPARC
909 implementation in <tt>SparcRegisterInfo.cpp</tt>:
913 <li><tt>getCalleeSavedRegs</tt> — Returns a list of callee-saved registers
914 in the order of the desired callee-save stack frame offset.</li>
916 <li><tt>getReservedRegs</tt> — Returns a bitset indexed by physical
917 register numbers, indicating if a particular register is unavailable.</li>
919 <li><tt>hasFP</tt> — Return a Boolean indicating if a function should have
920 a dedicated frame pointer register.</li>
922 <li><tt>eliminateCallFramePseudoInstr</tt> — If call frame setup or
923 destroy pseudo instructions are used, this can be called to eliminate
926 <li><tt>eliminateFrameIndex</tt> — Eliminate abstract frame indices from
927 instructions that may use them.</li>
929 <li><tt>emitPrologue</tt> — Insert prologue code into the function.</li>
931 <li><tt>emitEpilogue</tt> — Insert epilogue code into the function.</li>
936 <!-- *********************************************************************** -->
937 <div class="doc_section">
938 <a name="InstructionSet">Instruction Set</a>
941 <!-- *********************************************************************** -->
942 <div class="doc_text">
945 During the early stages of code generation, the LLVM IR code is converted to a
946 <tt>SelectionDAG</tt> with nodes that are instances of the <tt>SDNode</tt> class
947 containing target instructions. An <tt>SDNode</tt> has an opcode, operands, type
948 requirements, and operation properties. For example, is an operation
949 commutative, does an operation load from memory. The various operation node
950 types are described in the <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>
951 file (values of the <tt>NodeType</tt> enum in the <tt>ISD</tt> namespace).
955 TableGen uses the following target description (<tt>.td</tt>) input files to
956 generate much of the code for instruction definition:
960 <li><tt>Target.td</tt> — Where the <tt>Instruction</tt>, <tt>Operand</tt>,
961 <tt>InstrInfo</tt>, and other fundamental classes are defined.</li>
963 <li><tt>TargetSelectionDAG.td</tt>— Used by <tt>SelectionDAG</tt>
964 instruction selection generators, contains <tt>SDTC*</tt> classes (selection
965 DAG type constraint), definitions of <tt>SelectionDAG</tt> nodes (such as
966 <tt>imm</tt>, <tt>cond</tt>, <tt>bb</tt>, <tt>add</tt>, <tt>fadd</tt>,
967 <tt>sub</tt>), and pattern support (<tt>Pattern</tt>, <tt>Pat</tt>,
968 <tt>PatFrag</tt>, <tt>PatLeaf</tt>, <tt>ComplexPattern</tt>.</li>
970 <li><tt>XXXInstrFormats.td</tt> — Patterns for definitions of
971 target-specific instructions.</li>
973 <li><tt>XXXInstrInfo.td</tt> — Target-specific definitions of instruction
974 templates, condition codes, and instructions of an instruction set. For
975 architecture modifications, a different file name may be used. For example,
976 for Pentium with SSE instruction, this file is <tt>X86InstrSSE.td</tt>, and
977 for Pentium with MMX, this file is <tt>X86InstrMMX.td</tt>.</li>
981 There is also a target-specific <tt>XXX.td</tt> file, where <tt>XXX</tt> is the
982 name of the target. The <tt>XXX.td</tt> file includes the other <tt>.td</tt>
983 input files, but its contents are only directly important for subtargets.
987 You should describe a concrete target-specific class <tt>XXXInstrInfo</tt> that
988 represents machine instructions supported by a target machine.
989 <tt>XXXInstrInfo</tt> contains an array of <tt>XXXInstrDescriptor</tt> objects,
990 each of which describes one instruction. An instruction descriptor defines:</p>
993 <li>Opcode mnemonic</li>
995 <li>Number of operands</li>
997 <li>List of implicit register definitions and uses</li>
999 <li>Target-independent properties (such as memory access, is commutable)</li>
1001 <li>Target-specific flags </li>
1005 The Instruction class (defined in <tt>Target.td</tt>) is mostly used as a base
1006 for more complex instruction classes.
1009 <div class="doc_code">
1010 <pre>class Instruction {
1011 string Namespace = "";
1012 dag OutOperandList; // An dag containing the MI def operand list.
1013 dag InOperandList; // An dag containing the MI use operand list.
1014 string AsmString = ""; // The .s format to print the instruction with.
1015 list<dag> Pattern; // Set to the DAG pattern for this instruction
1016 list<Register> Uses = [];
1017 list<Register> Defs = [];
1018 list<Predicate> Predicates = []; // predicates turned into isel match code
1019 ... remainder not shown for space ...
1025 A <tt>SelectionDAG</tt> node (<tt>SDNode</tt>) should contain an object
1026 representing a target-specific instruction that is defined
1027 in <tt>XXXInstrInfo.td</tt>. The instruction objects should represent
1028 instructions from the architecture manual of the target machine (such as the
1029 SPARC Architecture Manual for the SPARC target).
1033 A single instruction from the architecture manual is often modeled as multiple
1034 target instructions, depending upon its operands. For example, a manual might
1035 describe an add instruction that takes a register or an immediate operand. An
1036 LLVM target could model this with two instructions named <tt>ADDri</tt> and
1041 You should define a class for each instruction category and define each opcode
1042 as a subclass of the category with appropriate parameters such as the fixed
1043 binary encoding of opcodes and extended opcodes. You should map the register
1044 bits to the bits of the instruction in which they are encoded (for the
1045 JIT). Also you should specify how the instruction should be printed when the
1046 automatic assembly printer is used.
1050 As is described in the SPARC Architecture Manual, Version 8, there are three
1051 major 32-bit formats for instructions. Format 1 is only for the <tt>CALL</tt>
1052 instruction. Format 2 is for branch on condition codes and <tt>SETHI</tt> (set
1053 high bits of a register) instructions. Format 3 is for other instructions.
1057 Each of these formats has corresponding classes in <tt>SparcInstrFormat.td</tt>.
1058 <tt>InstSP</tt> is a base class for other instruction classes. Additional base
1059 classes are specified for more precise formats: for example
1060 in <tt>SparcInstrFormat.td</tt>, <tt>F2_1</tt> is for <tt>SETHI</tt>,
1061 and <tt>F2_2</tt> is for branches. There are three other base
1062 classes: <tt>F3_1</tt> for register/register operations, <tt>F3_2</tt> for
1063 register/immediate operations, and <tt>F3_3</tt> for floating-point
1064 operations. <tt>SparcInstrInfo.td</tt> also adds the base class Pseudo for
1065 synthetic SPARC instructions.
1069 <tt>SparcInstrInfo.td</tt> largely consists of operand and instruction
1070 definitions for the SPARC target. In <tt>SparcInstrInfo.td</tt>, the following
1071 target description file entry, <tt>LDrr</tt>, defines the Load Integer
1072 instruction for a Word (the <tt>LD</tt> SPARC opcode) from a memory address to a
1073 register. The first parameter, the value 3 (<tt>11<sub>2</sub></tt>), is the
1074 operation value for this category of operation. The second parameter
1075 (<tt>000000<sub>2</sub></tt>) is the specific operation value
1076 for <tt>LD</tt>/Load Word. The third parameter is the output destination, which
1077 is a register operand and defined in the <tt>Register</tt> target description
1078 file (<tt>IntRegs</tt>).
1081 <div class="doc_code">
1082 <pre>def LDrr : F3_1 <3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr),
1084 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
1089 The fourth parameter is the input source, which uses the address
1090 operand <tt>MEMrr</tt> that is defined earlier in <tt>SparcInstrInfo.td</tt>:
1093 <div class="doc_code">
1094 <pre>def MEMrr : Operand<i32> {
1095 let PrintMethod = "printMemOperand";
1096 let MIOperandInfo = (ops IntRegs, IntRegs);
1102 The fifth parameter is a string that is used by the assembly printer and can be
1103 left as an empty string until the assembly printer interface is implemented. The
1104 sixth and final parameter is the pattern used to match the instruction during
1105 the SelectionDAG Select Phase described in
1106 (<a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
1107 Target-Independent Code Generator</a>). This parameter is detailed in the next
1108 section, <a href="#InstructionSelector">Instruction Selector</a>.
1112 Instruction class definitions are not overloaded for different operand types, so
1113 separate versions of instructions are needed for register, memory, or immediate
1114 value operands. For example, to perform a Load Integer instruction for a Word
1115 from an immediate operand to a register, the following instruction class is
1119 <div class="doc_code">
1120 <pre>def LDri : F3_2 <3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr),
1122 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
1127 Writing these definitions for so many similar instructions can involve a lot of
1128 cut and paste. In td files, the <tt>multiclass</tt> directive enables the
1129 creation of templates to define several instruction classes at once (using
1130 the <tt>defm</tt> directive). For example in <tt>SparcInstrInfo.td</tt>, the
1131 <tt>multiclass</tt> pattern <tt>F3_12</tt> is defined to create 2 instruction
1132 classes each time <tt>F3_12</tt> is invoked:
1135 <div class="doc_code">
1136 <pre>multiclass F3_12 <string OpcStr, bits<6> Op3Val, SDNode OpNode> {
1137 def rr : F3_1 <2, Op3Val,
1138 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1139 !strconcat(OpcStr, " $b, $c, $dst"),
1140 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
1141 def ri : F3_2 <2, Op3Val,
1142 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
1143 !strconcat(OpcStr, " $b, $c, $dst"),
1144 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
1150 So when the <tt>defm</tt> directive is used for the <tt>XOR</tt>
1151 and <tt>ADD</tt> instructions, as seen below, it creates four instruction
1152 objects: <tt>XORrr</tt>, <tt>XORri</tt>, <tt>ADDrr</tt>, and <tt>ADDri</tt>.
1155 <div class="doc_code">
1157 defm XOR : F3_12<"xor", 0b000011, xor>;
1158 defm ADD : F3_12<"add", 0b000000, add>;
1163 <tt>SparcInstrInfo.td</tt> also includes definitions for condition codes that
1164 are referenced by branch instructions. The following definitions
1165 in <tt>SparcInstrInfo.td</tt> indicate the bit location of the SPARC condition
1166 code. For example, the 10<sup>th</sup> bit represents the 'greater than'
1167 condition for integers, and the 22<sup>nd</sup> bit represents the 'greater
1168 than' condition for floats.
1171 <div class="doc_code">
1173 def ICC_NE : ICC_VAL< 9>; // Not Equal
1174 def ICC_E : ICC_VAL< 1>; // Equal
1175 def ICC_G : ICC_VAL<10>; // Greater
1177 def FCC_U : FCC_VAL<23>; // Unordered
1178 def FCC_G : FCC_VAL<22>; // Greater
1179 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
1185 (Note that <tt>Sparc.h</tt> also defines enums that correspond to the same SPARC
1186 condition codes. Care must be taken to ensure the values in <tt>Sparc.h</tt>
1187 correspond to the values in <tt>SparcInstrInfo.td</tt>. I.e.,
1188 <tt>SPCC::ICC_NE = 9</tt>, <tt>SPCC::FCC_U = 23</tt> and so on.)
1193 <!-- ======================================================================= -->
1194 <div class="doc_subsection">
1195 <a name="operandMapping">Instruction Operand Mapping</a>
1198 <div class="doc_text">
1201 The code generator backend maps instruction operands to fields in the
1202 instruction. Operands are assigned to unbound fields in the instruction in the
1203 order they are defined. Fields are bound when they are assigned a value. For
1204 example, the Sparc target defines the <tt>XNORrr</tt> instruction as
1205 a <tt>F3_1</tt> format instruction having three operands.
1208 <div class="doc_code">
1210 def XNORrr : F3_1<2, 0b000111,
1211 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
1212 "xnor $b, $c, $dst",
1213 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
1218 The instruction templates in <tt>SparcInstrFormats.td</tt> show the base class
1219 for <tt>F3_1</tt> is <tt>InstSP</tt>.
1222 <div class="doc_code">
1224 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
1225 field bits<32> Inst;
1226 let Namespace = "SP";
1228 let Inst{31-30} = op;
1229 dag OutOperandList = outs;
1230 dag InOperandList = ins;
1231 let AsmString = asmstr;
1232 let Pattern = pattern;
1237 <p><tt>InstSP</tt> leaves the <tt>op</tt> field unbound.</p>
1239 <div class="doc_code">
1241 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
1242 : InstSP<outs, ins, asmstr, pattern> {
1246 let op{1} = 1; // Op = 2 or 3
1247 let Inst{29-25} = rd;
1248 let Inst{24-19} = op3;
1249 let Inst{18-14} = rs1;
1255 <tt>F3</tt> binds the <tt>op</tt> field and defines the <tt>rd</tt>,
1256 <tt>op3</tt>, and <tt>rs1</tt> fields. <tt>F3</tt> format instructions will
1257 bind the operands <tt>rd</tt>, <tt>op3</tt>, and <tt>rs1</tt> fields.
1260 <div class="doc_code">
1262 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
1263 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
1264 bits<8> asi = 0; // asi not currently used
1268 let Inst{13} = 0; // i field = 0
1269 let Inst{12-5} = asi; // address space identifier
1270 let Inst{4-0} = rs2;
1276 <tt>F3_1</tt> binds the <tt>op3</tt> field and defines the <tt>rs2</tt>
1277 fields. <tt>F3_1</tt> format instructions will bind the operands to the <tt>rd</tt>,
1278 <tt>rs1</tt>, and <tt>rs2</tt> fields. This results in the <tt>XNORrr</tt>
1279 instruction binding <tt>$dst</tt>, <tt>$b</tt>, and <tt>$c</tt> operands to
1280 the <tt>rd</tt>, <tt>rs1</tt>, and <tt>rs2</tt> fields respectively.
1285 <!-- ======================================================================= -->
1286 <div class="doc_subsection">
1287 <a name="implementInstr">Implement a subclass of </a>
1288 <a href="http://www.llvm.org/docs/CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a>
1291 <div class="doc_text">
1294 The final step is to hand code portions of <tt>XXXInstrInfo</tt>, which
1295 implements the interface described in <tt>TargetInstrInfo.h</tt>. These
1296 functions return <tt>0</tt> or a Boolean or they assert, unless
1297 overridden. Here's a list of functions that are overridden for the SPARC
1298 implementation in <tt>SparcInstrInfo.cpp</tt>:
1302 <li><tt>isMoveInstr</tt> — Return true if the instruction is a register to
1303 register move; false, otherwise.</li>
1305 <li><tt>isLoadFromStackSlot</tt> — If the specified machine instruction is
1306 a direct load from a stack slot, return the register number of the
1307 destination and the <tt>FrameIndex</tt> of the stack slot.</li>
1309 <li><tt>isStoreToStackSlot</tt> — If the specified machine instruction is
1310 a direct store to a stack slot, return the register number of the
1311 destination and the <tt>FrameIndex</tt> of the stack slot.</li>
1313 <li><tt>copyRegToReg</tt> — Copy values between a pair of registers.</li>
1315 <li><tt>storeRegToStackSlot</tt> — Store a register value to a stack
1318 <li><tt>loadRegFromStackSlot</tt> — Load a register value from a stack
1321 <li><tt>storeRegToAddr</tt> — Store a register value to memory.</li>
1323 <li><tt>loadRegFromAddr</tt> — Load a register value from memory.</li>
1325 <li><tt>foldMemoryOperand</tt> — Attempt to combine instructions of any
1326 load or store instruction for the specified operand(s).</li>
1331 <!-- ======================================================================= -->
1332 <div class="doc_subsection">
1333 <a name="branchFolding">Branch Folding and If Conversion</a>
1335 <div class="doc_text">
1338 Performance can be improved by combining instructions or by eliminating
1339 instructions that are never reached. The <tt>AnalyzeBranch</tt> method
1340 in <tt>XXXInstrInfo</tt> may be implemented to examine conditional instructions
1341 and remove unnecessary instructions. <tt>AnalyzeBranch</tt> looks at the end of
1342 a machine basic block (MBB) for opportunities for improvement, such as branch
1343 folding and if conversion. The <tt>BranchFolder</tt> and <tt>IfConverter</tt>
1344 machine function passes (see the source files <tt>BranchFolding.cpp</tt> and
1345 <tt>IfConversion.cpp</tt> in the <tt>lib/CodeGen</tt> directory) call
1346 <tt>AnalyzeBranch</tt> to improve the control flow graph that represents the
1351 Several implementations of <tt>AnalyzeBranch</tt> (for ARM, Alpha, and X86) can
1352 be examined as models for your own <tt>AnalyzeBranch</tt> implementation. Since
1353 SPARC does not implement a useful <tt>AnalyzeBranch</tt>, the ARM target
1354 implementation is shown below.
1357 <p><tt>AnalyzeBranch</tt> returns a Boolean value and takes four parameters:</p>
1360 <li><tt>MachineBasicBlock &MBB</tt> — The incoming block to be
1363 <li><tt>MachineBasicBlock *&TBB</tt> — A destination block that is
1364 returned. For a conditional branch that evaluates to true, <tt>TBB</tt> is
1365 the destination.</li>
1367 <li><tt>MachineBasicBlock *&FBB</tt> — For a conditional branch that
1368 evaluates to false, <tt>FBB</tt> is returned as the destination.</li>
1370 <li><tt>std::vector<MachineOperand> &Cond</tt> — List of
1371 operands to evaluate a condition for a conditional branch.</li>
1375 In the simplest case, if a block ends without a branch, then it falls through to
1376 the successor block. No destination blocks are specified for either <tt>TBB</tt>
1377 or <tt>FBB</tt>, so both parameters return <tt>NULL</tt>. The start of
1378 the <tt>AnalyzeBranch</tt> (see code below for the ARM target) shows the
1379 function parameters and the code for the simplest case.
1382 <div class="doc_code">
1383 <pre>bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1384 MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
1385 std::vector<MachineOperand> &Cond) const
1387 MachineBasicBlock::iterator I = MBB.end();
1388 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
1394 If a block ends with a single unconditional branch instruction, then
1395 <tt>AnalyzeBranch</tt> (shown below) should return the destination of that
1396 branch in the <tt>TBB</tt> parameter.
1399 <div class="doc_code">
1401 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
1402 TBB = LastInst->getOperand(0).getMBB();
1409 If a block ends with two unconditional branches, then the second branch is never
1410 reached. In that situation, as shown below, remove the last branch instruction
1411 and return the penultimate branch in the <tt>TBB</tt> parameter.
1414 <div class="doc_code">
1416 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
1417 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
1418 TBB = SecondLastInst->getOperand(0).getMBB();
1420 I->eraseFromParent();
1427 A block may end with a single conditional branch instruction that falls through
1428 to successor block if the condition evaluates to false. In that case,
1429 <tt>AnalyzeBranch</tt> (shown below) should return the destination of that
1430 conditional branch in the <tt>TBB</tt> parameter and a list of operands in
1431 the <tt>Cond</tt> parameter to evaluate the condition.
1434 <div class="doc_code">
1436 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
1437 // Block ends with fall-through condbranch.
1438 TBB = LastInst->getOperand(0).getMBB();
1439 Cond.push_back(LastInst->getOperand(1));
1440 Cond.push_back(LastInst->getOperand(2));
1447 If a block ends with both a conditional branch and an ensuing unconditional
1448 branch, then <tt>AnalyzeBranch</tt> (shown below) should return the conditional
1449 branch destination (assuming it corresponds to a conditional evaluation of
1450 '<tt>true</tt>') in the <tt>TBB</tt> parameter and the unconditional branch
1451 destination in the <tt>FBB</tt> (corresponding to a conditional evaluation of
1452 '<tt>false</tt>'). A list of operands to evaluate the condition should be
1453 returned in the <tt>Cond</tt> parameter.
1456 <div class="doc_code">
1458 unsigned SecondLastOpc = SecondLastInst->getOpcode();
1460 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
1461 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
1462 TBB = SecondLastInst->getOperand(0).getMBB();
1463 Cond.push_back(SecondLastInst->getOperand(1));
1464 Cond.push_back(SecondLastInst->getOperand(2));
1465 FBB = LastInst->getOperand(0).getMBB();
1472 For the last two cases (ending with a single conditional branch or ending with
1473 one conditional and one unconditional branch), the operands returned in
1474 the <tt>Cond</tt> parameter can be passed to methods of other instructions to
1475 create new branches or perform other operations. An implementation
1476 of <tt>AnalyzeBranch</tt> requires the helper methods <tt>RemoveBranch</tt>
1477 and <tt>InsertBranch</tt> to manage subsequent operations.
1481 <tt>AnalyzeBranch</tt> should return false indicating success in most circumstances.
1482 <tt>AnalyzeBranch</tt> should only return true when the method is stumped about what to
1483 do, for example, if a block has three terminating branches. <tt>AnalyzeBranch</tt> may
1484 return true if it encounters a terminator it cannot handle, such as an indirect
1490 <!-- *********************************************************************** -->
1491 <div class="doc_section">
1492 <a name="InstructionSelector">Instruction Selector</a>
1494 <!-- *********************************************************************** -->
1496 <div class="doc_text">
1499 LLVM uses a <tt>SelectionDAG</tt> to represent LLVM IR instructions, and nodes
1500 of the <tt>SelectionDAG</tt> ideally represent native target
1501 instructions. During code generation, instruction selection passes are performed
1502 to convert non-native DAG instructions into native target-specific
1503 instructions. The pass described in <tt>XXXISelDAGToDAG.cpp</tt> is used to
1504 match patterns and perform DAG-to-DAG instruction selection. Optionally, a pass
1505 may be defined (in <tt>XXXBranchSelector.cpp</tt>) to perform similar DAG-to-DAG
1506 operations for branch instructions. Later, the code in
1507 <tt>XXXISelLowering.cpp</tt> replaces or removes operations and data types not
1508 supported natively (legalizes) in a <tt>SelectionDAG</tt>.
1512 TableGen generates code for instruction selection using the following target
1513 description input files:
1517 <li><tt>XXXInstrInfo.td</tt> — Contains definitions of instructions in a
1518 target-specific instruction set, generates <tt>XXXGenDAGISel.inc</tt>, which
1519 is included in <tt>XXXISelDAGToDAG.cpp</tt>.</li>
1521 <li><tt>XXXCallingConv.td</tt> — Contains the calling and return value
1522 conventions for the target architecture, and it generates
1523 <tt>XXXGenCallingConv.inc</tt>, which is included in
1524 <tt>XXXISelLowering.cpp</tt>.</li>
1528 The implementation of an instruction selection pass must include a header that
1529 declares the <tt>FunctionPass</tt> class or a subclass of <tt>FunctionPass</tt>. In
1530 <tt>XXXTargetMachine.cpp</tt>, a Pass Manager (PM) should add each instruction
1531 selection pass into the queue of passes to run.
1535 The LLVM static compiler (<tt>llc</tt>) is an excellent tool for visualizing the
1536 contents of DAGs. To display the <tt>SelectionDAG</tt> before or after specific
1537 processing phases, use the command line options for <tt>llc</tt>, described
1538 at <a href="http://llvm.org/docs/CodeGenerator.html#selectiondag_process">
1539 SelectionDAG Instruction Selection Process</a>.
1543 To describe instruction selector behavior, you should add patterns for lowering
1544 LLVM code into a <tt>SelectionDAG</tt> as the last parameter of the instruction
1545 definitions in <tt>XXXInstrInfo.td</tt>. For example, in
1546 <tt>SparcInstrInfo.td</tt>, this entry defines a register store operation, and
1547 the last parameter describes a pattern with the store DAG operator.
1550 <div class="doc_code">
1552 def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
1553 "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>;
1558 <tt>ADDRrr</tt> is a memory mode that is also defined in
1559 <tt>SparcInstrInfo.td</tt>:
1562 <div class="doc_code">
1564 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
1569 The definition of <tt>ADDRrr</tt> refers to <tt>SelectADDRrr</tt>, which is a
1570 function defined in an implementation of the Instructor Selector (such
1571 as <tt>SparcISelDAGToDAG.cpp</tt>).
1575 In <tt>lib/Target/TargetSelectionDAG.td</tt>, the DAG operator for store is
1579 <div class="doc_code">
1581 def store : PatFrag<(ops node:$val, node:$ptr),
1582 (st node:$val, node:$ptr), [{
1583 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
1584 return !ST->isTruncatingStore() &&
1585 ST->getAddressingMode() == ISD::UNINDEXED;
1592 <tt>XXXInstrInfo.td</tt> also generates (in <tt>XXXGenDAGISel.inc</tt>) the
1593 <tt>SelectCode</tt> method that is used to call the appropriate processing
1594 method for an instruction. In this example, <tt>SelectCode</tt>
1595 calls <tt>Select_ISD_STORE</tt> for the <tt>ISD::STORE</tt> opcode.
1598 <div class="doc_code">
1600 SDNode *SelectCode(SDValue N) {
1602 MVT::ValueType NVT = N.getNode()->getValueType(0);
1603 switch (N.getOpcode()) {
1607 return Select_ISD_STORE(N);
1617 The pattern for <tt>STrr</tt> is matched, so elsewhere in
1618 <tt>XXXGenDAGISel.inc</tt>, code for <tt>STrr</tt> is created for
1619 <tt>Select_ISD_STORE</tt>. The <tt>Emit_22</tt> method is also generated
1620 in <tt>XXXGenDAGISel.inc</tt> to complete the processing of this
1624 <div class="doc_code">
1626 SDNode *Select_ISD_STORE(const SDValue &N) {
1627 SDValue Chain = N.getOperand(0);
1628 if (Predicate_store(N.getNode())) {
1629 SDValue N1 = N.getOperand(1);
1630 SDValue N2 = N.getOperand(2);
1634 // Pattern: (st:void IntRegs:i32:$src,
1635 // ADDRrr:i32:$addr)<<P:Predicate_store>>
1636 // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
1637 // Pattern complexity = 13 cost = 1 size = 0
1638 if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &&
1639 N1.getNode()->getValueType(0) == MVT::i32 &&
1640 N2.getNode()->getValueType(0) == MVT::i32) {
1641 return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
1649 <!-- ======================================================================= -->
1650 <div class="doc_subsection">
1651 <a name="LegalizePhase">The SelectionDAG Legalize Phase</a>
1654 <div class="doc_text">
1657 The Legalize phase converts a DAG to use types and operations that are natively
1658 supported by the target. For natively unsupported types and operations, you need
1659 to add code to the target-specific XXXTargetLowering implementation to convert
1660 unsupported types and operations to supported ones.
1664 In the constructor for the <tt>XXXTargetLowering</tt> class, first use the
1665 <tt>addRegisterClass</tt> method to specify which types are supports and which
1666 register classes are associated with them. The code for the register classes are
1667 generated by TableGen from <tt>XXXRegisterInfo.td</tt> and placed
1668 in <tt>XXXGenRegisterInfo.h.inc</tt>. For example, the implementation of the
1669 constructor for the SparcTargetLowering class (in
1670 <tt>SparcISelLowering.cpp</tt>) starts with the following code:
1673 <div class="doc_code">
1675 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
1676 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
1677 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
1682 You should examine the node types in the <tt>ISD</tt> namespace
1683 (<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>) and determine which
1684 operations the target natively supports. For operations that do <b>not</b> have
1685 native support, add a callback to the constructor for the XXXTargetLowering
1686 class, so the instruction selection process knows what to do. The TargetLowering
1687 class callback methods (declared in <tt>llvm/Target/TargetLowering.h</tt>) are:
1691 <li><tt>setOperationAction</tt> — General operation.</li>
1693 <li><tt>setLoadExtAction</tt> — Load with extension.</li>
1695 <li><tt>setTruncStoreAction</tt> — Truncating store.</li>
1697 <li><tt>setIndexedLoadAction</tt> — Indexed load.</li>
1699 <li><tt>setIndexedStoreAction</tt> — Indexed store.</li>
1701 <li><tt>setConvertAction</tt> — Type conversion.</li>
1703 <li><tt>setCondCodeAction</tt> — Support for a given condition code.</li>
1707 Note: on older releases, <tt>setLoadXAction</tt> is used instead
1708 of <tt>setLoadExtAction</tt>. Also, on older releases,
1709 <tt>setCondCodeAction</tt> may not be supported. Examine your release
1710 to see what methods are specifically supported.
1714 These callbacks are used to determine that an operation does or does not work
1715 with a specified type (or types). And in all cases, the third parameter is
1716 a <tt>LegalAction</tt> type enum value: <tt>Promote</tt>, <tt>Expand</tt>,
1717 <tt>Custom</tt>, or <tt>Legal</tt>. <tt>SparcISelLowering.cpp</tt>
1718 contains examples of all four <tt>LegalAction</tt> values.
1723 <!-- _______________________________________________________________________ -->
1724 <div class="doc_subsubsection">
1725 <a name="promote">Promote</a>
1728 <div class="doc_text">
1731 For an operation without native support for a given type, the specified type may
1732 be promoted to a larger type that is supported. For example, SPARC does not
1733 support a sign-extending load for Boolean values (<tt>i1</tt> type), so
1734 in <tt>SparcISelLowering.cpp</tt> the third parameter below, <tt>Promote</tt>,
1735 changes <tt>i1</tt> type values to a large type before loading.
1738 <div class="doc_code">
1740 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1746 <!-- _______________________________________________________________________ -->
1747 <div class="doc_subsubsection">
1748 <a name="expand">Expand</a>
1751 <div class="doc_text">
1754 For a type without native support, a value may need to be broken down further,
1755 rather than promoted. For an operation without native support, a combination of
1756 other operations may be used to similar effect. In SPARC, the floating-point
1757 sine and cosine trig operations are supported by expansion to other operations,
1758 as indicated by the third parameter, <tt>Expand</tt>, to
1759 <tt>setOperationAction</tt>:
1762 <div class="doc_code">
1764 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1765 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1771 <!-- _______________________________________________________________________ -->
1772 <div class="doc_subsubsection">
1773 <a name="custom">Custom</a>
1776 <div class="doc_text">
1779 For some operations, simple type promotion or operation expansion may be
1780 insufficient. In some cases, a special intrinsic function must be implemented.
1784 For example, a constant value may require special treatment, or an operation may
1785 require spilling and restoring registers in the stack and working with register
1790 As seen in <tt>SparcISelLowering.cpp</tt> code below, to perform a type
1791 conversion from a floating point value to a signed integer, first the
1792 <tt>setOperationAction</tt> should be called with <tt>Custom</tt> as the third
1796 <div class="doc_code">
1798 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1803 In the <tt>LowerOperation</tt> method, for each <tt>Custom</tt> operation, a
1804 case statement should be added to indicate what function to call. In the
1805 following code, an <tt>FP_TO_SINT</tt> opcode will call
1806 the <tt>LowerFP_TO_SINT</tt> method:
1809 <div class="doc_code">
1811 SDValue SparcTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1812 switch (Op.getOpcode()) {
1813 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1821 Finally, the <tt>LowerFP_TO_SINT</tt> method is implemented, using an FP
1822 register to convert the floating-point value to an integer.
1825 <div class="doc_code">
1827 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
1828 assert(Op.getValueType() == MVT::i32);
1829 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
1830 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1837 <!-- _______________________________________________________________________ -->
1838 <div class="doc_subsubsection">
1839 <a name="legal">Legal</a>
1842 <div class="doc_text">
1845 The <tt>Legal</tt> LegalizeAction enum value simply indicates that an
1846 operation <b>is</b> natively supported. <tt>Legal</tt> represents the default
1847 condition, so it is rarely used. In <tt>SparcISelLowering.cpp</tt>, the action
1848 for <tt>CTPOP</tt> (an operation to count the bits set in an integer) is
1849 natively supported only for SPARC v9. The following code enables
1850 the <tt>Expand</tt> conversion technique for non-v9 SPARC implementations.
1853 <div class="doc_code">
1855 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1857 if (TM.getSubtarget<SparcSubtarget>().isV9())
1858 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1859 case ISD::SETULT: return SPCC::ICC_CS;
1860 case ISD::SETULE: return SPCC::ICC_LEU;
1861 case ISD::SETUGT: return SPCC::ICC_GU;
1862 case ISD::SETUGE: return SPCC::ICC_CC;
1870 <!-- ======================================================================= -->
1871 <div class="doc_subsection">
1872 <a name="callingConventions">Calling Conventions</a>
1875 <div class="doc_text">
1878 To support target-specific calling conventions, <tt>XXXGenCallingConv.td</tt>
1879 uses interfaces (such as CCIfType and CCAssignToReg) that are defined in
1880 <tt>lib/Target/TargetCallingConv.td</tt>. TableGen can take the target
1881 descriptor file <tt>XXXGenCallingConv.td</tt> and generate the header
1882 file <tt>XXXGenCallingConv.inc</tt>, which is typically included
1883 in <tt>XXXISelLowering.cpp</tt>. You can use the interfaces in
1884 <tt>TargetCallingConv.td</tt> to specify:
1888 <li>The order of parameter allocation.</li>
1890 <li>Where parameters and return values are placed (that is, on the stack or in
1893 <li>Which registers may be used.</li>
1895 <li>Whether the caller or callee unwinds the stack.</li>
1899 The following example demonstrates the use of the <tt>CCIfType</tt> and
1900 <tt>CCAssignToReg</tt> interfaces. If the <tt>CCIfType</tt> predicate is true
1901 (that is, if the current argument is of type <tt>f32</tt> or <tt>f64</tt>), then
1902 the action is performed. In this case, the <tt>CCAssignToReg</tt> action assigns
1903 the argument value to the first available register: either <tt>R0</tt>
1907 <div class="doc_code">
1909 CCIfType<[f32,f64], CCAssignToReg<[R0, R1]>>
1914 <tt>SparcCallingConv.td</tt> contains definitions for a target-specific
1915 return-value calling convention (RetCC_Sparc32) and a basic 32-bit C calling
1916 convention (<tt>CC_Sparc32</tt>). The definition of <tt>RetCC_Sparc32</tt>
1917 (shown below) indicates which registers are used for specified scalar return
1918 types. A single-precision float is returned to register <tt>F0</tt>, and a
1919 double-precision float goes to register <tt>D0</tt>. A 32-bit integer is
1920 returned in register <tt>I0</tt> or <tt>I1</tt>.
1923 <div class="doc_code">
1925 def RetCC_Sparc32 : CallingConv<[
1926 CCIfType<[i32], CCAssignToReg<[I0, I1]>>,
1927 CCIfType<[f32], CCAssignToReg<[F0]>>,
1928 CCIfType<[f64], CCAssignToReg<[D0]>>
1934 The definition of <tt>CC_Sparc32</tt> in <tt>SparcCallingConv.td</tt> introduces
1935 <tt>CCAssignToStack</tt>, which assigns the value to a stack slot with the
1936 specified size and alignment. In the example below, the first parameter, 4,
1937 indicates the size of the slot, and the second parameter, also 4, indicates the
1938 stack alignment along 4-byte units. (Special cases: if size is zero, then the
1939 ABI size is used; if alignment is zero, then the ABI alignment is used.)
1942 <div class="doc_code">
1944 def CC_Sparc32 : CallingConv<[
1945 // All arguments get passed in integer registers if there is space.
1946 CCIfType<[i32, f32, f64], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
1947 CCAssignToStack<4, 4>
1953 <tt>CCDelegateTo</tt> is another commonly used interface, which tries to find a
1954 specified sub-calling convention, and, if a match is found, it is invoked. In
1955 the following example (in <tt>X86CallingConv.td</tt>), the definition of
1956 <tt>RetCC_X86_32_C</tt> ends with <tt>CCDelegateTo</tt>. After the current value
1957 is assigned to the register <tt>ST0</tt> or <tt>ST1</tt>,
1958 the <tt>RetCC_X86Common</tt> is invoked.
1961 <div class="doc_code">
1963 def RetCC_X86_32_C : CallingConv<[
1964 CCIfType<[f32], CCAssignToReg<[ST0, ST1]>>,
1965 CCIfType<[f64], CCAssignToReg<[ST0, ST1]>>,
1966 CCDelegateTo<RetCC_X86Common>
1972 <tt>CCIfCC</tt> is an interface that attempts to match the given name to the
1973 current calling convention. If the name identifies the current calling
1974 convention, then a specified action is invoked. In the following example (in
1975 <tt>X86CallingConv.td</tt>), if the <tt>Fast</tt> calling convention is in use,
1976 then <tt>RetCC_X86_32_Fast</tt> is invoked. If the <tt>SSECall</tt> calling
1977 convention is in use, then <tt>RetCC_X86_32_SSE</tt> is invoked.
1980 <div class="doc_code">
1982 def RetCC_X86_32 : CallingConv<[
1983 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
1984 CCIfCC<"CallingConv::X86_SSECall", CCDelegateTo<RetCC_X86_32_SSE>>,
1985 CCDelegateTo<RetCC_X86_32_C>
1990 <p>Other calling convention interfaces include:</p>
1993 <li><tt>CCIf <predicate, action></tt> — If the predicate matches,
1994 apply the action.</li>
1996 <li><tt>CCIfInReg <action></tt> — If the argument is marked with the
1997 '<tt>inreg</tt>' attribute, then apply the action.</li>
1999 <li><tt>CCIfNest <action></tt> — Inf the argument is marked with the
2000 '<tt>nest</tt>' attribute, then apply the action.</li>
2002 <li><tt>CCIfNotVarArg <action></tt> — If the current function does
2003 not take a variable number of arguments, apply the action.</li>
2005 <li><tt>CCAssignToRegWithShadow <registerList, shadowList></tt> —
2006 similar to <tt>CCAssignToReg</tt>, but with a shadow list of registers.</li>
2008 <li><tt>CCPassByVal <size, align></tt> — Assign value to a stack
2009 slot with the minimum specified size and alignment.</li>
2011 <li><tt>CCPromoteToType <type></tt> — Promote the current value to
2012 the specified type.</li>
2014 <li><tt>CallingConv <[actions]></tt> — Define each calling
2015 convention that is supported.</li>
2020 <!-- *********************************************************************** -->
2021 <div class="doc_section">
2022 <a name="assemblyPrinter">Assembly Printer</a>
2024 <!-- *********************************************************************** -->
2026 <div class="doc_text">
2029 During the code emission stage, the code generator may utilize an LLVM pass to
2030 produce assembly output. To do this, you want to implement the code for a
2031 printer that converts LLVM IR to a GAS-format assembly language for your target
2032 machine, using the following steps:
2036 <li>Define all the assembly strings for your target, adding them to the
2037 instructions defined in the <tt>XXXInstrInfo.td</tt> file.
2038 (See <a href="#InstructionSet">Instruction Set</a>.) TableGen will produce
2039 an output file (<tt>XXXGenAsmWriter.inc</tt>) with an implementation of
2040 the <tt>printInstruction</tt> method for the XXXAsmPrinter class.</li>
2042 <li>Write <tt>XXXTargetAsmInfo.h</tt>, which contains the bare-bones declaration
2043 of the <tt>XXXTargetAsmInfo</tt> class (a subclass
2044 of <tt>TargetAsmInfo</tt>).</li>
2046 <li>Write <tt>XXXTargetAsmInfo.cpp</tt>, which contains target-specific values
2047 for <tt>TargetAsmInfo</tt> properties and sometimes new implementations for
2050 <li>Write <tt>XXXAsmPrinter.cpp</tt>, which implements the <tt>AsmPrinter</tt>
2051 class that performs the LLVM-to-assembly conversion.</li>
2055 The code in <tt>XXXTargetAsmInfo.h</tt> is usually a trivial declaration of the
2056 <tt>XXXTargetAsmInfo</tt> class for use in <tt>XXXTargetAsmInfo.cpp</tt>.
2057 Similarly, <tt>XXXTargetAsmInfo.cpp</tt> usually has a few declarations of
2058 <tt>XXXTargetAsmInfo</tt> replacement values that override the default values
2059 in <tt>TargetAsmInfo.cpp</tt>. For example in <tt>SparcTargetAsmInfo.cpp</tt>:
2062 <div class="doc_code">
2064 SparcTargetAsmInfo::SparcTargetAsmInfo(const SparcTargetMachine &TM) {
2065 Data16bitsDirective = "\t.half\t";
2066 Data32bitsDirective = "\t.word\t";
2067 Data64bitsDirective = 0; // .xword is only supported by V9.
2068 ZeroDirective = "\t.skip\t";
2069 CommentString = "!";
2070 ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
2076 The X86 assembly printer implementation (<tt>X86TargetAsmInfo</tt>) is an
2077 example where the target specific <tt>TargetAsmInfo</tt> class uses an
2078 overridden methods: <tt>ExpandInlineAsm</tt>.
2082 A target-specific implementation of AsmPrinter is written in
2083 <tt>XXXAsmPrinter.cpp</tt>, which implements the <tt>AsmPrinter</tt> class that
2084 converts the LLVM to printable assembly. The implementation must include the
2085 following headers that have declarations for the <tt>AsmPrinter</tt> and
2086 <tt>MachineFunctionPass</tt> classes. The <tt>MachineFunctionPass</tt> is a
2087 subclass of <tt>FunctionPass</tt>.
2090 <div class="doc_code">
2092 #include "llvm/CodeGen/AsmPrinter.h"
2093 #include "llvm/CodeGen/MachineFunctionPass.h"
2098 As a <tt>FunctionPass</tt>, <tt>AsmPrinter</tt> first
2099 calls <tt>doInitialization</tt> to set up the <tt>AsmPrinter</tt>. In
2100 <tt>SparcAsmPrinter</tt>, a <tt>Mangler</tt> object is instantiated to process
2105 In <tt>XXXAsmPrinter.cpp</tt>, the <tt>runOnMachineFunction</tt> method
2106 (declared in <tt>MachineFunctionPass</tt>) must be implemented
2107 for <tt>XXXAsmPrinter</tt>. In <tt>MachineFunctionPass</tt>,
2108 the <tt>runOnFunction</tt> method invokes <tt>runOnMachineFunction</tt>.
2109 Target-specific implementations of <tt>runOnMachineFunction</tt> differ, but
2110 generally do the following to process each machine function:
2114 <li>Call <tt>SetupMachineFunction</tt> to perform initialization.</li>
2116 <li>Call <tt>EmitConstantPool</tt> to print out (to the output stream) constants
2117 which have been spilled to memory.</li>
2119 <li>Call <tt>EmitJumpTableInfo</tt> to print out jump tables used by the current
2122 <li>Print out the label for the current function.</li>
2124 <li>Print out the code for the function, including basic block labels and the
2125 assembly for the instruction (using <tt>printInstruction</tt>)</li>
2129 The <tt>XXXAsmPrinter</tt> implementation must also include the code generated
2130 by TableGen that is output in the <tt>XXXGenAsmWriter.inc</tt> file. The code
2131 in <tt>XXXGenAsmWriter.inc</tt> contains an implementation of the
2132 <tt>printInstruction</tt> method that may call these methods:
2136 <li><tt>printOperand</tt></li>
2138 <li><tt>printMemOperand</tt></li>
2140 <li><tt>printCCOperand (for conditional statements)</tt></li>
2142 <li><tt>printDataDirective</tt></li>
2144 <li><tt>printDeclare</tt></li>
2146 <li><tt>printImplicitDef</tt></li>
2148 <li><tt>printInlineAsm</tt></li>
2152 The implementations of <tt>printDeclare</tt>, <tt>printImplicitDef</tt>,
2153 <tt>printInlineAsm</tt>, and <tt>printLabel</tt> in <tt>AsmPrinter.cpp</tt> are
2154 generally adequate for printing assembly and do not need to be
2159 The <tt>printOperand</tt> method is implemented with a long switch/case
2160 statement for the type of operand: register, immediate, basic block, external
2161 symbol, global address, constant pool index, or jump table index. For an
2162 instruction with a memory address operand, the <tt>printMemOperand</tt> method
2163 should be implemented to generate the proper output. Similarly,
2164 <tt>printCCOperand</tt> should be used to print a conditional operand.
2167 <p><tt>doFinalization</tt> should be overridden in <tt>XXXAsmPrinter</tt>, and
2168 it should be called to shut down the assembly printer. During
2169 <tt>doFinalization</tt>, global variables and constants are printed to
2175 <!-- *********************************************************************** -->
2176 <div class="doc_section">
2177 <a name="subtargetSupport">Subtarget Support</a>
2179 <!-- *********************************************************************** -->
2181 <div class="doc_text">
2184 Subtarget support is used to inform the code generation process of instruction
2185 set variations for a given chip set. For example, the LLVM SPARC implementation
2186 provided covers three major versions of the SPARC microprocessor architecture:
2187 Version 8 (V8, which is a 32-bit architecture), Version 9 (V9, a 64-bit
2188 architecture), and the UltraSPARC architecture. V8 has 16 double-precision
2189 floating-point registers that are also usable as either 32 single-precision or 8
2190 quad-precision registers. V8 is also purely big-endian. V9 has 32
2191 double-precision floating-point registers that are also usable as 16
2192 quad-precision registers, but cannot be used as single-precision registers. The
2193 UltraSPARC architecture combines V9 with UltraSPARC Visual Instruction Set
2198 If subtarget support is needed, you should implement a target-specific
2199 XXXSubtarget class for your architecture. This class should process the
2200 command-line options <tt>-mcpu=</tt> and <tt>-mattr=</tt>.
2204 TableGen uses definitions in the <tt>Target.td</tt> and <tt>Sparc.td</tt> files
2205 to generate code in <tt>SparcGenSubtarget.inc</tt>. In <tt>Target.td</tt>, shown
2206 below, the <tt>SubtargetFeature</tt> interface is defined. The first 4 string
2207 parameters of the <tt>SubtargetFeature</tt> interface are a feature name, an
2208 attribute set by the feature, the value of the attribute, and a description of
2209 the feature. (The fifth parameter is a list of features whose presence is
2210 implied, and its default value is an empty array.)
2213 <div class="doc_code">
2215 class SubtargetFeature<string n, string a, string v, string d,
2216 list<SubtargetFeature> i = []> {
2218 string Attribute = a;
2221 list<SubtargetFeature> Implies = i;
2227 In the <tt>Sparc.td</tt> file, the SubtargetFeature is used to define the
2231 <div class="doc_code">
2233 def FeatureV9 : SubtargetFeature<"v9", "IsV9", "true",
2234 "Enable SPARC-V9 instructions">;
2235 def FeatureV8Deprecated : SubtargetFeature<"deprecated-v8",
2236 "V8DeprecatedInsts", "true",
2237 "Enable deprecated V8 instructions in V9 mode">;
2238 def FeatureVIS : SubtargetFeature<"vis", "IsVIS", "true",
2239 "Enable UltraSPARC Visual Instruction Set extensions">;
2244 Elsewhere in <tt>Sparc.td</tt>, the Proc class is defined and then is used to
2245 define particular SPARC processor subtypes that may have the previously
2249 <div class="doc_code">
2251 class Proc<string Name, list<SubtargetFeature> Features>
2252 : Processor<Name, NoItineraries, Features>;
2254 def : Proc<"generic", []>;
2255 def : Proc<"v8", []>;
2256 def : Proc<"supersparc", []>;
2257 def : Proc<"sparclite", []>;
2258 def : Proc<"f934", []>;
2259 def : Proc<"hypersparc", []>;
2260 def : Proc<"sparclite86x", []>;
2261 def : Proc<"sparclet", []>;
2262 def : Proc<"tsc701", []>;
2263 def : Proc<"v9", [FeatureV9]>;
2264 def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
2265 def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
2266 def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
2271 From <tt>Target.td</tt> and <tt>Sparc.td</tt> files, the resulting
2272 SparcGenSubtarget.inc specifies enum values to identify the features, arrays of
2273 constants to represent the CPU features and CPU subtypes, and the
2274 ParseSubtargetFeatures method that parses the features string that sets
2275 specified subtarget options. The generated <tt>SparcGenSubtarget.inc</tt> file
2276 should be included in the <tt>SparcSubtarget.cpp</tt>. The target-specific
2277 implementation of the XXXSubtarget method should follow this pseudocode:
2280 <div class="doc_code">
2282 XXXSubtarget::XXXSubtarget(const Module &M, const std::string &FS) {
2283 // Set the default features
2284 // Determine default and user specified characteristics of the CPU
2285 // Call ParseSubtargetFeatures(FS, CPU) to parse the features string
2286 // Perform any additional operations
2293 <!-- *********************************************************************** -->
2294 <div class="doc_section">
2295 <a name="jitSupport">JIT Support</a>
2297 <!-- *********************************************************************** -->
2299 <div class="doc_text">
2302 The implementation of a target machine optionally includes a Just-In-Time (JIT)
2303 code generator that emits machine code and auxiliary structures as binary output
2304 that can be written directly to memory. To do this, implement JIT code
2305 generation by performing the following steps:
2309 <li>Write an <tt>XXXCodeEmitter.cpp</tt> file that contains a machine function
2310 pass that transforms target-machine instructions into relocatable machine
2313 <li>Write an <tt>XXXJITInfo.cpp</tt> file that implements the JIT interfaces for
2314 target-specific code-generation activities, such as emitting machine code
2317 <li>Modify <tt>XXXTargetMachine</tt> so that it provides a
2318 <tt>TargetJITInfo</tt> object through its <tt>getJITInfo</tt> method.</li>
2322 There are several different approaches to writing the JIT support code. For
2323 instance, TableGen and target descriptor files may be used for creating a JIT
2324 code generator, but are not mandatory. For the Alpha and PowerPC target
2325 machines, TableGen is used to generate <tt>XXXGenCodeEmitter.inc</tt>, which
2326 contains the binary coding of machine instructions and the
2327 <tt>getBinaryCodeForInstr</tt> method to access those codes. Other JIT
2328 implementations do not.
2332 Both <tt>XXXJITInfo.cpp</tt> and <tt>XXXCodeEmitter.cpp</tt> must include the
2333 <tt>llvm/CodeGen/MachineCodeEmitter.h</tt> header file that defines the
2334 <tt>MachineCodeEmitter</tt> class containing code for several callback functions
2335 that write data (in bytes, words, strings, etc.) to the output stream.
2340 <!-- ======================================================================= -->
2341 <div class="doc_subsection">
2342 <a name="mce">Machine Code Emitter</a>
2345 <div class="doc_text">
2348 In <tt>XXXCodeEmitter.cpp</tt>, a target-specific of the <tt>Emitter</tt> class
2349 is implemented as a function pass (subclass
2350 of <tt>MachineFunctionPass</tt>). The target-specific implementation
2351 of <tt>runOnMachineFunction</tt> (invoked by
2352 <tt>runOnFunction</tt> in <tt>MachineFunctionPass</tt>) iterates through the
2353 <tt>MachineBasicBlock</tt> calls <tt>emitInstruction</tt> to process each
2354 instruction and emit binary code. <tt>emitInstruction</tt> is largely
2355 implemented with case statements on the instruction types defined in
2356 <tt>XXXInstrInfo.h</tt>. For example, in <tt>X86CodeEmitter.cpp</tt>,
2357 the <tt>emitInstruction</tt> method is built around the following switch/case
2361 <div class="doc_code">
2363 switch (Desc->TSFlags & X86::FormMask) {
2364 case X86II::Pseudo: // for not yet implemented instructions
2365 ... // or pseudo-instructions
2367 case X86II::RawFrm: // for instructions with a fixed opcode value
2370 case X86II::AddRegFrm: // for instructions that have one register operand
2371 ... // added to their opcode
2373 case X86II::MRMDestReg:// for instructions that use the Mod/RM byte
2374 ... // to specify a destination (register)
2376 case X86II::MRMDestMem:// for instructions that use the Mod/RM byte
2377 ... // to specify a destination (memory)
2379 case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte
2380 ... // to specify a source (register)
2382 case X86II::MRMSrcMem: // for instructions that use the Mod/RM byte
2383 ... // to specify a source (memory)
2385 case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
2386 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
2387 case X86II::MRM4r: case X86II::MRM5r: // use the Mod/RM byte and a field
2388 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
2391 case X86II::MRM0m: case X86II::MRM1m: // for instructions that operate on
2392 case X86II::MRM2m: case X86II::MRM3m: // a MEMORY r/m operand and
2393 case X86II::MRM4m: case X86II::MRM5m: // use the Mod/RM byte and a field
2394 case X86II::MRM6m: case X86II::MRM7m: // to hold extended opcode data
2397 case X86II::MRMInitReg: // for instructions whose source and
2398 ... // destination are the same register
2405 The implementations of these case statements often first emit the opcode and
2406 then get the operand(s). Then depending upon the operand, helper methods may be
2407 called to process the operand(s). For example, in <tt>X86CodeEmitter.cpp</tt>,
2408 for the <tt>X86II::AddRegFrm</tt> case, the first data emitted
2409 (by <tt>emitByte</tt>) is the opcode added to the register operand. Then an
2410 object representing the machine operand, <tt>MO1</tt>, is extracted. The helper
2411 methods such as <tt>isImmediate</tt>,
2412 <tt>isGlobalAddress</tt>, <tt>isExternalSymbol</tt>, <tt>isConstantPoolIndex</tt>, and
2413 <tt>isJumpTableIndex</tt> determine the operand
2414 type. (<tt>X86CodeEmitter.cpp</tt> also has private methods such
2415 as <tt>emitConstant</tt>, <tt>emitGlobalAddress</tt>,
2416 <tt>emitExternalSymbolAddress</tt>, <tt>emitConstPoolAddress</tt>,
2417 and <tt>emitJumpTableAddress</tt> that emit the data into the output stream.)
2420 <div class="doc_code">
2422 case X86II::AddRegFrm:
2423 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
2425 if (CurOp != NumOps) {
2426 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2427 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2428 if (MO1.isImmediate())
2429 emitConstant(MO1.getImm(), Size);
2431 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
2432 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
2433 if (Opcode == X86::MOV64ri)
2434 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
2435 if (MO1.isGlobalAddress()) {
2436 bool NeedStub = isa<Function>(MO1.getGlobal());
2437 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
2438 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
2440 } else if (MO1.isExternalSymbol())
2441 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
2442 else if (MO1.isConstantPoolIndex())
2443 emitConstPoolAddress(MO1.getIndex(), rt);
2444 else if (MO1.isJumpTableIndex())
2445 emitJumpTableAddress(MO1.getIndex(), rt);
2453 In the previous example, <tt>XXXCodeEmitter.cpp</tt> uses the
2454 variable <tt>rt</tt>, which is a RelocationType enum that may be used to
2455 relocate addresses (for example, a global address with a PIC base offset). The
2456 <tt>RelocationType</tt> enum for that target is defined in the short
2457 target-specific <tt>XXXRelocations.h</tt> file. The <tt>RelocationType</tt> is used by
2458 the <tt>relocate</tt> method defined in <tt>XXXJITInfo.cpp</tt> to rewrite
2459 addresses for referenced global symbols.
2463 For example, <tt>X86Relocations.h</tt> specifies the following relocation types
2464 for the X86 addresses. In all four cases, the relocated value is added to the
2465 value already in memory. For <tt>reloc_pcrel_word</tt>
2466 and <tt>reloc_picrel_word</tt>, there is an additional initial adjustment.
2469 <div class="doc_code">
2471 enum RelocationType {
2472 reloc_pcrel_word = 0, // add reloc value after adjusting for the PC loc
2473 reloc_picrel_word = 1, // add reloc value after adjusting for the PIC base
2474 reloc_absolute_word = 2, // absolute relocation; no additional adjustment
2475 reloc_absolute_dword = 3 // absolute relocation; no additional adjustment
2482 <!-- ======================================================================= -->
2483 <div class="doc_subsection">
2484 <a name="targetJITInfo">Target JIT Info</a>
2487 <div class="doc_text">
2490 <tt>XXXJITInfo.cpp</tt> implements the JIT interfaces for target-specific
2491 code-generation activities, such as emitting machine code and stubs. At minimum,
2492 a target-specific version of <tt>XXXJITInfo</tt> implements the following:
2496 <li><tt>getLazyResolverFunction</tt> — Initializes the JIT, gives the
2497 target a function that is used for compilation.</li>
2499 <li><tt>emitFunctionStub</tt> — Returns a native function with a specified
2500 address for a callback function.</li>
2502 <li><tt>relocate</tt> — Changes the addresses of referenced globals, based
2503 on relocation types.</li>
2505 <li>Callback function that are wrappers to a function stub that is used when the
2506 real target is not initially known.</li>
2510 <tt>getLazyResolverFunction</tt> is generally trivial to implement. It makes the
2511 incoming parameter as the global <tt>JITCompilerFunction</tt> and returns the
2512 callback function that will be used a function wrapper. For the Alpha target
2513 (in <tt>AlphaJITInfo.cpp</tt>), the <tt>getLazyResolverFunction</tt>
2514 implementation is simply:
2517 <div class="doc_code">
2519 TargetJITInfo::LazyResolverFn AlphaJITInfo::getLazyResolverFunction(
2521 JITCompilerFunction = F;
2522 return AlphaCompilationCallback;
2528 For the X86 target, the <tt>getLazyResolverFunction</tt> implementation is a
2529 little more complication, because it returns a different callback function for
2530 processors with SSE instructions and XMM registers.
2534 The callback function initially saves and later restores the callee register
2535 values, incoming arguments, and frame and return address. The callback function
2536 needs low-level access to the registers or stack, so it is typically implemented
2542 <!-- *********************************************************************** -->
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