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5 <title>Writing an LLVM backend</title>
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11 <div class="doc_title">
12 Writing an LLVM backend
16 <li><a href="#intro">Introduction</a>
17 <li><a href="#backends">Writing a backend</a>
19 <li><a href="#machine">Machine backends</a>
21 <li><a href="#machineTOC">Outline</a></li>
22 <li><a href="#machineDetails">Implementation details</a></li>
24 <li><a href="#lang">Language backends</a></li>
26 <li><a href="#related">Related reading material</a>
29 <div class="doc_author">
30 <p>Written by <a href="http://misha.brukman.net">Misha Brukman</a></p>
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34 <div class="doc_section">
35 <a name="intro">Introduction</a>
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39 <div class="doc_text">
41 <p>This document describes techniques for writing backends for LLVM which
42 convert the LLVM representation to machine assembly code or other languages.</p>
46 <!-- *********************************************************************** -->
47 <div class="doc_section">
48 <a name="backends">Writing a backend</a>
50 <!-- *********************************************************************** -->
52 <!-- ======================================================================= -->
53 <div class="doc_subsection">
54 <a name="machine">Machine backends</a>
57 <!-- _______________________________________________________________________ -->
58 <div class="doc_subsubsection">
59 <a name="machineTOC">Outline</a>
62 <div class="doc_text">
64 <p>In general, you want to follow the format of X86 or PowerPC (in
65 <tt>lib/Target</tt>).</p>
67 <p>To create a static compiler (one that emits text assembly), you need to
68 implement the following:</p>
71 <li>Describe the register set.
73 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
74 the register set and register classes</li>
75 <li>Implement a subclass of <tt><a
76 href="CodeGenerator.html#mregisterinfo">MRegisterInfo</a></tt></li>
78 <li>Describe the instruction set.
80 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
81 the instruction set</li>
82 <li>Implement a subclass of <tt><a
83 href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a></tt></li>
85 <li>Describe the target machine.
87 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
88 the target that describes the pointer size and references the instruction
90 <li>Implement a subclass of <tt><a
91 href="CodeGenerator.html#targetmachine">TargetMachine</a></tt>, which
92 configures <tt><a href="CodeGenerator.html#targetdata">TargetData</a></tt>
94 <li>Register your new target using the <tt>RegisterTarget</tt>
96 <div class="doc_code"><pre>
97 RegisterTarget<<em>MyTargetMachine</em>> M("short_name", " Target name");
99 <br>Here, <em>MyTargetMachine</em> is the name of your implemented
101 href="CodeGenerator.html#targetmachine">TargetMachine</a></tt>,
102 <em>short_name</em> is the option that will be active following
103 <tt>-march=</tt> to select a target in llc and lli, and the last string
104 is the description of your target to appear in <tt>-help</tt>
107 <li>Implement the assembly printer for the architecture.
109 <li>Define all of the assembly strings for your target, adding them to the
110 instructions in your *InstrInfo.td file.</li>
111 <li>Implement the <tt>llvm::AsmPrinter</tt> interface.</li>
114 <li>Implement an instruction selector for the architecture.
116 <li>The recommended method is the <a href="CodeGenerator.html#instselect">
117 pattern-matching DAG-to-DAG instruction selector</a> (for example, see
118 the PowerPC backend in PPCISelDAGtoDAG.cpp). Parts of instruction
119 selector creation can be performed by adding patterns to the instructions
120 in your <tt>.td</tt> file.</li>
123 <li>Optionally, add subtarget support.
125 <li>If your target has multiple subtargets (e.g. variants with different
126 capabilities), implement the <tt>llvm::TargetSubtarget</tt> interface
127 for your architecture. This allows you to add <tt>-mcpu=</tt> and
128 <tt>-mattr=</tt> options.</li>
130 <li>Optionally, add JIT support.
132 <li>Create a subclass of <tt><a
133 href="CodeGenerator.html#targetjitinfo">TargetJITInfo</a></tt></li>
134 <li>Create a machine code emitter that will be used to emit binary code
135 directly into memory, given <tt>MachineInstr</tt>s</li>
140 <!-- _______________________________________________________________________ -->
141 <div class="doc_subsubsection">
142 <a name="machineDetails">Implementation details</a>
145 <div class="doc_text">
149 <li><p><b>TableGen register info description</b> - describe a class which
150 will store the register's number in the binary encoding of the instruction
151 (e.g., for JIT purposes).</p>
153 <p>You also need to define register classes to contain these registers, such as
154 the integer register class and floating-point register class, so that you can
155 allocate virtual registers to instructions from these sets, and let the
156 target-independent register allocator automatically choose the actual
157 architected registers.</p>
159 <div class="doc_code">
161 // class Register is defined in Target.td
162 <b>class</b> <em>Target</em>Reg<string name> : Register<name> {
163 <b>let</b> Namespace = "<em>Target</em>";
166 <b>class</b> IntReg<<b>bits</b><5> num, string name> : <em>Target</em>Reg<name> {
167 <b>field</b> <b>bits</b><5> Num = num;
170 <b>def</b> R0 : IntReg<0, "%R0">;
173 // class RegisterClass is defined in Target.td
174 <b>def</b> IReg : RegisterClass<i64, 64, [R0, ... ]>;
179 <li><p><b>TableGen instruction info description</b> - break up instructions into
180 classes, usually that's already done by the manufacturer (see instruction
181 manual). Define a class for each instruction category. Define each opcode as a
182 subclass of the category, with appropriate parameters such as the fixed binary
183 encoding of opcodes and extended opcodes, and map the register bits to the bits
184 of the instruction which they are encoded in (for the JIT). Also specify how
185 the instruction should be printed so it can use the automatic assembly printer,
188 <div class="doc_code">
190 // class Instruction is defined in Target.td
191 <b>class</b> Form<<b>bits</b><6> opcode, <b>dag</b> OL, <b>string</b> asmstr> : Instruction {
192 <b>field</b> <b>bits</b><42> Inst;
194 <b>let</b> Namespace = "<em>Target</em>";
195 <b>let</b> Inst{0-6} = opcode;
196 <b>let</b> OperandList = OL;
197 <b>let</b> AsmString = asmstr;
200 <b>def</b> ADD : Form<42, (ops IReg:$rD, IReg:$rA, IReg:$rB), "add $rD, $rA, $rB">;
209 <!-- ======================================================================= -->
210 <div class="doc_subsection">
211 <a name="lang">Language backends</a>
214 <div class="doc_text">
216 <p>For now, just take a look at <tt>lib/Target/CBackend</tt> for an example of
217 how the C backend is written.</p>
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222 <div class="doc_section">
223 <a name="related">Related reading material</a>
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227 <div class="doc_text">
230 <li><a href="CodeGenerator.html">Code generator</a> -
231 describes some of the classes in code generation at a high level, but
232 it is not (yet) complete</li>
233 <li><a href="TableGenFundamentals.html">TableGen fundamentals</a> -
234 describes how to use TableGen to describe your target information
236 <li><a href="HowToSubmitABug.html#codegen">Debugging code generation with
237 bugpoint</a> - shows bugpoint usage scenarios to simplify backend
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252 <a href="http://misha.brukman.net">Misha Brukman</a><br>
253 <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a>
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