1 =======================
2 Writing an LLVM Backend
3 =======================
16 This document describes techniques for writing compiler backends that convert
17 the LLVM Intermediate Representation (IR) to code for a specified machine or
18 other languages. Code intended for a specific machine can take the form of
19 either assembly code or binary code (usable for a JIT compiler).
21 The backend of LLVM features a target-independent code generator that may
22 create output for several types of target CPUs --- including X86, PowerPC,
23 ARM, and SPARC. The backend may also be used to generate code targeted at SPUs
24 of the Cell processor or GPUs to support the execution of compute kernels.
26 The document focuses on existing examples found in subdirectories of
27 ``llvm/lib/Target`` in a downloaded LLVM release. In particular, this document
28 focuses on the example of creating a static compiler (one that emits text
29 assembly) for a SPARC target, because SPARC has fairly standard
30 characteristics, such as a RISC instruction set and straightforward calling
36 The audience for this document is anyone who needs to write an LLVM backend to
37 generate code for a specific hardware or software target.
42 These essential documents must be read before reading this document:
44 * `LLVM Language Reference Manual <LangRef.html>`_ --- a reference manual for
45 the LLVM assembly language.
47 * :doc:`CodeGenerator` --- a guide to the components (classes and code
48 generation algorithms) for translating the LLVM internal representation into
49 machine code for a specified target. Pay particular attention to the
50 descriptions of code generation stages: Instruction Selection, Scheduling and
51 Formation, SSA-based Optimization, Register Allocation, Prolog/Epilog Code
52 Insertion, Late Machine Code Optimizations, and Code Emission.
54 * :doc:`TableGenFundamentals` --- a document that describes the TableGen
55 (``tblgen``) application that manages domain-specific information to support
56 LLVM code generation. TableGen processes input from a target description
57 file (``.td`` suffix) and generates C++ code that can be used for code
60 * :doc:`WritingAnLLVMPass` --- The assembly printer is a ``FunctionPass``, as
61 are several ``SelectionDAG`` processing steps.
63 To follow the SPARC examples in this document, have a copy of `The SPARC
64 Architecture Manual, Version 8 <http://www.sparc.org/standards/V8.pdf>`_ for
65 reference. For details about the ARM instruction set, refer to the `ARM
66 Architecture Reference Manual <http://infocenter.arm.com/>`_. For more about
67 the GNU Assembler format (``GAS``), see `Using As
68 <http://sourceware.org/binutils/docs/as/index.html>`_, especially for the
69 assembly printer. "Using As" contains a list of target machine dependent
75 To write a compiler backend for LLVM that converts the LLVM IR to code for a
76 specified target (machine or other language), follow these steps:
78 * Create a subclass of the ``TargetMachine`` class that describes
79 characteristics of your target machine. Copy existing examples of specific
80 ``TargetMachine`` class and header files; for example, start with
81 ``SparcTargetMachine.cpp`` and ``SparcTargetMachine.h``, but change the file
82 names for your target. Similarly, change code that references "``Sparc``" to
83 reference your target.
85 * Describe the register set of the target. Use TableGen to generate code for
86 register definition, register aliases, and register classes from a
87 target-specific ``RegisterInfo.td`` input file. You should also write
88 additional code for a subclass of the ``TargetRegisterInfo`` class that
89 represents the class register file data used for register allocation and also
90 describes the interactions between registers.
92 * Describe the instruction set of the target. Use TableGen to generate code
93 for target-specific instructions from target-specific versions of
94 ``TargetInstrFormats.td`` and ``TargetInstrInfo.td``. You should write
95 additional code for a subclass of the ``TargetInstrInfo`` class to represent
96 machine instructions supported by the target machine.
98 * Describe the selection and conversion of the LLVM IR from a Directed Acyclic
99 Graph (DAG) representation of instructions to native target-specific
100 instructions. Use TableGen to generate code that matches patterns and
101 selects instructions based on additional information in a target-specific
102 version of ``TargetInstrInfo.td``. Write code for ``XXXISelDAGToDAG.cpp``,
103 where ``XXX`` identifies the specific target, to perform pattern matching and
104 DAG-to-DAG instruction selection. Also write code in ``XXXISelLowering.cpp``
105 to replace or remove operations and data types that are not supported
106 natively in a SelectionDAG.
108 * Write code for an assembly printer that converts LLVM IR to a GAS format for
109 your target machine. You should add assembly strings to the instructions
110 defined in your target-specific version of ``TargetInstrInfo.td``. You
111 should also write code for a subclass of ``AsmPrinter`` that performs the
112 LLVM-to-assembly conversion and a trivial subclass of ``TargetAsmInfo``.
114 * Optionally, add support for subtargets (i.e., variants with different
115 capabilities). You should also write code for a subclass of the
116 ``TargetSubtarget`` class, which allows you to use the ``-mcpu=`` and
117 ``-mattr=`` command-line options.
119 * Optionally, add JIT support and create a machine code emitter (subclass of
120 ``TargetJITInfo``) that is used to emit binary code directly into memory.
122 In the ``.cpp`` and ``.h``. files, initially stub up these methods and then
123 implement them later. Initially, you may not know which private members that
124 the class will need and which components will need to be subclassed.
129 To actually create your compiler backend, you need to create and modify a few
130 files. The absolute minimum is discussed here. But to actually use the LLVM
131 target-independent code generator, you must perform the steps described in the
132 :doc:`LLVM Target-Independent Code Generator <CodeGenerator>` document.
134 First, you should create a subdirectory under ``lib/Target`` to hold all the
135 files related to your target. If your target is called "Dummy", create the
136 directory ``lib/Target/Dummy``.
138 In this new directory, create a ``Makefile``. It is easiest to copy a
139 ``Makefile`` of another target and modify it. It should at least contain the
140 ``LEVEL``, ``LIBRARYNAME`` and ``TARGET`` variables, and then include
141 ``$(LEVEL)/Makefile.common``. The library can be named ``LLVMDummy`` (for
142 example, see the MIPS target). Alternatively, you can split the library into
143 ``LLVMDummyCodeGen`` and ``LLVMDummyAsmPrinter``, the latter of which should be
144 implemented in a subdirectory below ``lib/Target/Dummy`` (for example, see the
147 Note that these two naming schemes are hardcoded into ``llvm-config``. Using
148 any other naming scheme will confuse ``llvm-config`` and produce a lot of
149 (seemingly unrelated) linker errors when linking ``llc``.
151 To make your target actually do something, you need to implement a subclass of
152 ``TargetMachine``. This implementation should typically be in the file
153 ``lib/Target/DummyTargetMachine.cpp``, but any file in the ``lib/Target``
154 directory will be built and should work. To use LLVM's target independent code
155 generator, you should do what all current machine backends do: create a
156 subclass of ``LLVMTargetMachine``. (To create a target from scratch, create a
157 subclass of ``TargetMachine``.)
159 To get LLVM to actually build and link your target, you need to add it to the
160 ``TARGETS_TO_BUILD`` variable. To do this, you modify the configure script to
161 know about your target when parsing the ``--enable-targets`` option. Search
162 the configure script for ``TARGETS_TO_BUILD``, add your target to the lists
163 there (some creativity required), and then reconfigure. Alternatively, you can
164 change ``autotools/configure.ac`` and regenerate configure by running
165 ``./autoconf/AutoRegen.sh``.
170 ``LLVMTargetMachine`` is designed as a base class for targets implemented with
171 the LLVM target-independent code generator. The ``LLVMTargetMachine`` class
172 should be specialized by a concrete target class that implements the various
173 virtual methods. ``LLVMTargetMachine`` is defined as a subclass of
174 ``TargetMachine`` in ``include/llvm/Target/TargetMachine.h``. The
175 ``TargetMachine`` class implementation (``TargetMachine.cpp``) also processes
176 numerous command-line options.
178 To create a concrete target-specific subclass of ``LLVMTargetMachine``, start
179 by copying an existing ``TargetMachine`` class and header. You should name the
180 files that you create to reflect your specific target. For instance, for the
181 SPARC target, name the files ``SparcTargetMachine.h`` and
182 ``SparcTargetMachine.cpp``.
184 For a target machine ``XXX``, the implementation of ``XXXTargetMachine`` must
185 have access methods to obtain objects that represent target components. These
186 methods are named ``get*Info``, and are intended to obtain the instruction set
187 (``getInstrInfo``), register set (``getRegisterInfo``), stack frame layout
188 (``getFrameInfo``), and similar information. ``XXXTargetMachine`` must also
189 implement the ``getDataLayout`` method to access an object with target-specific
190 data characteristics, such as data type size and alignment requirements.
192 For instance, for the SPARC target, the header file ``SparcTargetMachine.h``
193 declares prototypes for several ``get*Info`` and ``getDataLayout`` methods that
194 simply return a class member.
202 class SparcTargetMachine : public LLVMTargetMachine {
203 const DataLayout DataLayout; // Calculates type size & alignment
204 SparcSubtarget Subtarget;
205 SparcInstrInfo InstrInfo;
206 TargetFrameInfo FrameInfo;
209 virtual const TargetAsmInfo *createTargetAsmInfo() const;
212 SparcTargetMachine(const Module &M, const std::string &FS);
214 virtual const SparcInstrInfo *getInstrInfo() const {return &InstrInfo; }
215 virtual const TargetFrameInfo *getFrameInfo() const {return &FrameInfo; }
216 virtual const TargetSubtarget *getSubtargetImpl() const{return &Subtarget; }
217 virtual const TargetRegisterInfo *getRegisterInfo() const {
218 return &InstrInfo.getRegisterInfo();
220 virtual const DataLayout *getDataLayout() const { return &DataLayout; }
221 static unsigned getModuleMatchQuality(const Module &M);
223 // Pass Pipeline Configuration
224 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
225 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
228 } // end namespace llvm
231 * ``getRegisterInfo()``
233 * ``getDataLayout()``
234 * ``getSubtargetImpl()``
236 For some targets, you also need to support the following methods:
238 * ``getTargetLowering()``
241 In addition, the ``XXXTargetMachine`` constructor should specify a
242 ``TargetDescription`` string that determines the data layout for the target
243 machine, including characteristics such as pointer size, alignment, and
244 endianness. For example, the constructor for ``SparcTargetMachine`` contains
249 SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS)
250 : DataLayout("E-p:32:32-f128:128:128"),
251 Subtarget(M, FS), InstrInfo(Subtarget),
252 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
255 Hyphens separate portions of the ``TargetDescription`` string.
257 * An upper-case "``E``" in the string indicates a big-endian target data model.
258 A lower-case "``e``" indicates little-endian.
260 * "``p:``" is followed by pointer information: size, ABI alignment, and
261 preferred alignment. If only two figures follow "``p:``", then the first
262 value is pointer size, and the second value is both ABI and preferred
265 * Then a letter for numeric type alignment: "``i``", "``f``", "``v``", or
266 "``a``" (corresponding to integer, floating point, vector, or aggregate).
267 "``i``", "``v``", or "``a``" are followed by ABI alignment and preferred
268 alignment. "``f``" is followed by three values: the first indicates the size
269 of a long double, then ABI alignment, and then ABI preferred alignment.
274 You must also register your target with the ``TargetRegistry``, which is what
275 other LLVM tools use to be able to lookup and use your target at runtime. The
276 ``TargetRegistry`` can be used directly, but for most targets there are helper
277 templates which should take care of the work for you.
279 All targets should declare a global ``Target`` object which is used to
280 represent the target during registration. Then, in the target's ``TargetInfo``
281 library, the target should define that object and use the ``RegisterTarget``
282 template to register the target. For example, the Sparc registration code
287 Target llvm::TheSparcTarget;
289 extern "C" void LLVMInitializeSparcTargetInfo() {
290 RegisterTarget<Triple::sparc, /*HasJIT=*/false>
291 X(TheSparcTarget, "sparc", "Sparc");
294 This allows the ``TargetRegistry`` to look up the target by name or by target
295 triple. In addition, most targets will also register additional features which
296 are available in separate libraries. These registration steps are separate,
297 because some clients may wish to only link in some parts of the target --- the
298 JIT code generator does not require the use of the assembler printer, for
299 example. Here is an example of registering the Sparc assembly printer:
303 extern "C" void LLVMInitializeSparcAsmPrinter() {
304 RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
307 For more information, see "`llvm/Target/TargetRegistry.h
308 </doxygen/TargetRegistry_8h-source.html>`_".
310 Register Set and Register Classes
311 =================================
313 You should describe a concrete target-specific class that represents the
314 register file of a target machine. This class is called ``XXXRegisterInfo``
315 (where ``XXX`` identifies the target) and represents the class register file
316 data that is used for register allocation. It also describes the interactions
319 You also need to define register classes to categorize related registers. A
320 register class should be added for groups of registers that are all treated the
321 same way for some instruction. Typical examples are register classes for
322 integer, floating-point, or vector registers. A register allocator allows an
323 instruction to use any register in a specified register class to perform the
324 instruction in a similar manner. Register classes allocate virtual registers
325 to instructions from these sets, and register classes let the
326 target-independent register allocator automatically choose the actual
329 Much of the code for registers, including register definition, register
330 aliases, and register classes, is generated by TableGen from
331 ``XXXRegisterInfo.td`` input files and placed in ``XXXGenRegisterInfo.h.inc``
332 and ``XXXGenRegisterInfo.inc`` output files. Some of the code in the
333 implementation of ``XXXRegisterInfo`` requires hand-coding.
338 The ``XXXRegisterInfo.td`` file typically starts with register definitions for
339 a target machine. The ``Register`` class (specified in ``Target.td``) is used
340 to define an object for each register. The specified string ``n`` becomes the
341 ``Name`` of the register. The basic ``Register`` object does not have any
342 subregisters and does not specify any aliases.
346 class Register<string n> {
347 string Namespace = "";
351 int SpillAlignment = 0;
352 list<Register> Aliases = [];
353 list<Register> SubRegs = [];
354 list<int> DwarfNumbers = [];
357 For example, in the ``X86RegisterInfo.td`` file, there are register definitions
358 that utilize the ``Register`` class, such as:
362 def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
364 This defines the register ``AL`` and assigns it values (with ``DwarfRegNum``)
365 that are used by ``gcc``, ``gdb``, or a debug information writer to identify a
366 register. For register ``AL``, ``DwarfRegNum`` takes an array of 3 values
367 representing 3 different modes: the first element is for X86-64, the second for
368 exception handling (EH) on X86-32, and the third is generic. -1 is a special
369 Dwarf number that indicates the gcc number is undefined, and -2 indicates the
370 register number is invalid for this mode.
372 From the previously described line in the ``X86RegisterInfo.td`` file, TableGen
373 generates this code in the ``X86GenRegisterInfo.inc`` file:
377 static const unsigned GR8[] = { X86::AL, ... };
379 const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
381 const TargetRegisterDesc RegisterDescriptors[] = {
383 { "AL", "AL", AL_AliasSet, Empty_SubRegsSet, Empty_SubRegsSet, AL_SuperRegsSet }, ...
385 From the register info file, TableGen generates a ``TargetRegisterDesc`` object
386 for each register. ``TargetRegisterDesc`` is defined in
387 ``include/llvm/Target/TargetRegisterInfo.h`` with the following fields:
391 struct TargetRegisterDesc {
392 const char *AsmName; // Assembly language name for the register
393 const char *Name; // Printable name for the reg (for debugging)
394 const unsigned *AliasSet; // Register Alias Set
395 const unsigned *SubRegs; // Sub-register set
396 const unsigned *ImmSubRegs; // Immediate sub-register set
397 const unsigned *SuperRegs; // Super-register set
400 TableGen uses the entire target description file (``.td``) to determine text
401 names for the register (in the ``AsmName`` and ``Name`` fields of
402 ``TargetRegisterDesc``) and the relationships of other registers to the defined
403 register (in the other ``TargetRegisterDesc`` fields). In this example, other
404 definitions establish the registers "``AX``", "``EAX``", and "``RAX``" as
405 aliases for one another, so TableGen generates a null-terminated array
406 (``AL_AliasSet``) for this register alias set.
408 The ``Register`` class is commonly used as a base class for more complex
409 classes. In ``Target.td``, the ``Register`` class is the base for the
410 ``RegisterWithSubRegs`` class that is used to define registers that need to
411 specify subregisters in the ``SubRegs`` list, as shown here:
415 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
416 let SubRegs = subregs;
419 In ``SparcRegisterInfo.td``, additional register classes are defined for SPARC:
420 a ``Register`` subclass, ``SparcReg``, and further subclasses: ``Ri``, ``Rf``,
421 and ``Rd``. SPARC registers are identified by 5-bit ID numbers, which is a
422 feature common to these subclasses. Note the use of "``let``" expressions to
423 override values that are initially defined in a superclass (such as ``SubRegs``
424 field in the ``Rd`` class).
428 class SparcReg<string n> : Register<n> {
430 let Namespace = "SP";
432 // Ri - 32-bit integer registers
433 class Ri<bits<5> num, string n> :
437 // Rf - 32-bit floating-point registers
438 class Rf<bits<5> num, string n> :
442 // Rd - Slots in the FP register file for 64-bit floating-point values.
443 class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
445 let SubRegs = subregs;
448 In the ``SparcRegisterInfo.td`` file, there are register definitions that
449 utilize these subclasses of ``Register``, such as:
453 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
454 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
456 def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>;
457 def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>;
459 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
460 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;
462 The last two registers shown above (``D0`` and ``D1``) are double-precision
463 floating-point registers that are aliases for pairs of single-precision
464 floating-point sub-registers. In addition to aliases, the sub-register and
465 super-register relationships of the defined register are in fields of a
466 register's ``TargetRegisterDesc``.
468 Defining a Register Class
469 -------------------------
471 The ``RegisterClass`` class (specified in ``Target.td``) is used to define an
472 object that represents a group of related registers and also defines the
473 default allocation order of the registers. A target description file
474 ``XXXRegisterInfo.td`` that uses ``Target.td`` can construct register classes
475 using the following class:
479 class RegisterClass<string namespace,
480 list<ValueType> regTypes, int alignment, dag regList> {
481 string Namespace = namespace;
482 list<ValueType> RegTypes = regTypes;
483 int Size = 0; // spill size, in bits; zero lets tblgen pick the size
484 int Alignment = alignment;
486 // CopyCost is the cost of copying a value between two registers
487 // default value 1 means a single instruction
488 // A negative value means copying is extremely expensive or impossible
490 dag MemberList = regList;
492 // for register classes that are subregisters of this class
493 list<RegisterClass> SubRegClassList = [];
495 code MethodProtos = [{}]; // to insert arbitrary code
496 code MethodBodies = [{}];
499 To define a ``RegisterClass``, use the following 4 arguments:
501 * The first argument of the definition is the name of the namespace.
503 * The second argument is a list of ``ValueType`` register type values that are
504 defined in ``include/llvm/CodeGen/ValueTypes.td``. Defined values include
505 integer types (such as ``i16``, ``i32``, and ``i1`` for Boolean),
506 floating-point types (``f32``, ``f64``), and vector types (for example,
507 ``v8i16`` for an ``8 x i16`` vector). All registers in a ``RegisterClass``
508 must have the same ``ValueType``, but some registers may store vector data in
509 different configurations. For example a register that can process a 128-bit
510 vector may be able to handle 16 8-bit integer elements, 8 16-bit integers, 4
511 32-bit integers, and so on.
513 * The third argument of the ``RegisterClass`` definition specifies the
514 alignment required of the registers when they are stored or loaded to
517 * The final argument, ``regList``, specifies which registers are in this class.
518 If an alternative allocation order method is not specified, then ``regList``
519 also defines the order of allocation used by the register allocator. Besides
520 simply listing registers with ``(add R0, R1, ...)``, more advanced set
521 operators are available. See ``include/llvm/Target/Target.td`` for more
524 In ``SparcRegisterInfo.td``, three ``RegisterClass`` objects are defined:
525 ``FPRegs``, ``DFPRegs``, and ``IntRegs``. For all three register classes, the
526 first argument defines the namespace with the string "``SP``". ``FPRegs``
527 defines a group of 32 single-precision floating-point registers (``F0`` to
528 ``F31``); ``DFPRegs`` defines a group of 16 double-precision registers
533 // F0, F1, F2, ..., F31
534 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
536 def DFPRegs : RegisterClass<"SP", [f64], 64,
537 (add D0, D1, D2, D3, D4, D5, D6, D7, D8,
538 D9, D10, D11, D12, D13, D14, D15)>;
540 def IntRegs : RegisterClass<"SP", [i32], 32,
541 (add L0, L1, L2, L3, L4, L5, L6, L7,
542 I0, I1, I2, I3, I4, I5,
543 O0, O1, O2, O3, O4, O5, O7,
545 // Non-allocatable regs:
549 I7, // return address
551 G5, G6, G7 // reserved for kernel
554 Using ``SparcRegisterInfo.td`` with TableGen generates several output files
555 that are intended for inclusion in other source code that you write.
556 ``SparcRegisterInfo.td`` generates ``SparcGenRegisterInfo.h.inc``, which should
557 be included in the header file for the implementation of the SPARC register
558 implementation that you write (``SparcRegisterInfo.h``). In
559 ``SparcGenRegisterInfo.h.inc`` a new structure is defined called
560 ``SparcGenRegisterInfo`` that uses ``TargetRegisterInfo`` as its base. It also
561 specifies types, based upon the defined register classes: ``DFPRegsClass``,
562 ``FPRegsClass``, and ``IntRegsClass``.
564 ``SparcRegisterInfo.td`` also generates ``SparcGenRegisterInfo.inc``, which is
565 included at the bottom of ``SparcRegisterInfo.cpp``, the SPARC register
566 implementation. The code below shows only the generated integer registers and
567 associated register classes. The order of registers in ``IntRegs`` reflects
568 the order in the definition of ``IntRegs`` in the target description file.
572 // IntRegs Register Class...
573 static const unsigned IntRegs[] = {
574 SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5,
575 SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3,
576 SP::I4, SP::I5, SP::O0, SP::O1, SP::O2, SP::O3,
577 SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3,
578 SP::G4, SP::O6, SP::I6, SP::I7, SP::G0, SP::G5,
582 // IntRegsVTs Register Class Value Types...
583 static const MVT::ValueType IntRegsVTs[] = {
587 namespace SP { // Register class instances
588 DFPRegsClass DFPRegsRegClass;
589 FPRegsClass FPRegsRegClass;
590 IntRegsClass IntRegsRegClass;
592 // IntRegs Sub-register Classess...
593 static const TargetRegisterClass* const IntRegsSubRegClasses [] = {
597 // IntRegs Super-register Classess...
598 static const TargetRegisterClass* const IntRegsSuperRegClasses [] = {
602 // IntRegs Register Class sub-classes...
603 static const TargetRegisterClass* const IntRegsSubclasses [] = {
607 // IntRegs Register Class super-classes...
608 static const TargetRegisterClass* const IntRegsSuperclasses [] = {
612 IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID,
613 IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, IntRegsSubRegClasses,
614 IntRegsSuperRegClasses, 4, 4, 1, IntRegs, IntRegs + 32) {}
617 The register allocators will avoid using reserved registers, and callee saved
618 registers are not used until all the volatile registers have been used. That
619 is usually good enough, but in some cases it may be necessary to provide custom
622 Implement a subclass of ``TargetRegisterInfo``
623 ----------------------------------------------
625 The final step is to hand code portions of ``XXXRegisterInfo``, which
626 implements the interface described in ``TargetRegisterInfo.h`` (see
627 :ref:`TargetRegisterInfo`). These functions return ``0``, ``NULL``, or
628 ``false``, unless overridden. Here is a list of functions that are overridden
629 for the SPARC implementation in ``SparcRegisterInfo.cpp``:
631 * ``getCalleeSavedRegs`` --- Returns a list of callee-saved registers in the
632 order of the desired callee-save stack frame offset.
634 * ``getReservedRegs`` --- Returns a bitset indexed by physical register
635 numbers, indicating if a particular register is unavailable.
637 * ``hasFP`` --- Return a Boolean indicating if a function should have a
638 dedicated frame pointer register.
640 * ``eliminateCallFramePseudoInstr`` --- If call frame setup or destroy pseudo
641 instructions are used, this can be called to eliminate them.
643 * ``eliminateFrameIndex`` --- Eliminate abstract frame indices from
644 instructions that may use them.
646 * ``emitPrologue`` --- Insert prologue code into the function.
648 * ``emitEpilogue`` --- Insert epilogue code into the function.
655 During the early stages of code generation, the LLVM IR code is converted to a
656 ``SelectionDAG`` with nodes that are instances of the ``SDNode`` class
657 containing target instructions. An ``SDNode`` has an opcode, operands, type
658 requirements, and operation properties. For example, is an operation
659 commutative, does an operation load from memory. The various operation node
660 types are described in the ``include/llvm/CodeGen/SelectionDAGNodes.h`` file
661 (values of the ``NodeType`` enum in the ``ISD`` namespace).
663 TableGen uses the following target description (``.td``) input files to
664 generate much of the code for instruction definition:
666 * ``Target.td`` --- Where the ``Instruction``, ``Operand``, ``InstrInfo``, and
667 other fundamental classes are defined.
669 * ``TargetSelectionDAG.td`` --- Used by ``SelectionDAG`` instruction selection
670 generators, contains ``SDTC*`` classes (selection DAG type constraint),
671 definitions of ``SelectionDAG`` nodes (such as ``imm``, ``cond``, ``bb``,
672 ``add``, ``fadd``, ``sub``), and pattern support (``Pattern``, ``Pat``,
673 ``PatFrag``, ``PatLeaf``, ``ComplexPattern``.
675 * ``XXXInstrFormats.td`` --- Patterns for definitions of target-specific
678 * ``XXXInstrInfo.td`` --- Target-specific definitions of instruction templates,
679 condition codes, and instructions of an instruction set. For architecture
680 modifications, a different file name may be used. For example, for Pentium
681 with SSE instruction, this file is ``X86InstrSSE.td``, and for Pentium with
682 MMX, this file is ``X86InstrMMX.td``.
684 There is also a target-specific ``XXX.td`` file, where ``XXX`` is the name of
685 the target. The ``XXX.td`` file includes the other ``.td`` input files, but
686 its contents are only directly important for subtargets.
688 You should describe a concrete target-specific class ``XXXInstrInfo`` that
689 represents machine instructions supported by a target machine.
690 ``XXXInstrInfo`` contains an array of ``XXXInstrDescriptor`` objects, each of
691 which describes one instruction. An instruction descriptor defines:
695 * List of implicit register definitions and uses
696 * Target-independent properties (such as memory access, is commutable)
697 * Target-specific flags
699 The Instruction class (defined in ``Target.td``) is mostly used as a base for
700 more complex instruction classes.
705 string Namespace = "";
706 dag OutOperandList; // A dag containing the MI def operand list.
707 dag InOperandList; // A dag containing the MI use operand list.
708 string AsmString = ""; // The .s format to print the instruction with.
709 list<dag> Pattern; // Set to the DAG pattern for this instruction.
710 list<Register> Uses = [];
711 list<Register> Defs = [];
712 list<Predicate> Predicates = []; // predicates turned into isel match code
713 ... remainder not shown for space ...
716 A ``SelectionDAG`` node (``SDNode``) should contain an object representing a
717 target-specific instruction that is defined in ``XXXInstrInfo.td``. The
718 instruction objects should represent instructions from the architecture manual
719 of the target machine (such as the SPARC Architecture Manual for the SPARC
722 A single instruction from the architecture manual is often modeled as multiple
723 target instructions, depending upon its operands. For example, a manual might
724 describe an add instruction that takes a register or an immediate operand. An
725 LLVM target could model this with two instructions named ``ADDri`` and
728 You should define a class for each instruction category and define each opcode
729 as a subclass of the category with appropriate parameters such as the fixed
730 binary encoding of opcodes and extended opcodes. You should map the register
731 bits to the bits of the instruction in which they are encoded (for the JIT).
732 Also you should specify how the instruction should be printed when the
733 automatic assembly printer is used.
735 As is described in the SPARC Architecture Manual, Version 8, there are three
736 major 32-bit formats for instructions. Format 1 is only for the ``CALL``
737 instruction. Format 2 is for branch on condition codes and ``SETHI`` (set high
738 bits of a register) instructions. Format 3 is for other instructions.
740 Each of these formats has corresponding classes in ``SparcInstrFormat.td``.
741 ``InstSP`` is a base class for other instruction classes. Additional base
742 classes are specified for more precise formats: for example in
743 ``SparcInstrFormat.td``, ``F2_1`` is for ``SETHI``, and ``F2_2`` is for
744 branches. There are three other base classes: ``F3_1`` for register/register
745 operations, ``F3_2`` for register/immediate operations, and ``F3_3`` for
746 floating-point operations. ``SparcInstrInfo.td`` also adds the base class
747 ``Pseudo`` for synthetic SPARC instructions.
749 ``SparcInstrInfo.td`` largely consists of operand and instruction definitions
750 for the SPARC target. In ``SparcInstrInfo.td``, the following target
751 description file entry, ``LDrr``, defines the Load Integer instruction for a
752 Word (the ``LD`` SPARC opcode) from a memory address to a register. The first
753 parameter, the value 3 (``11``\ :sub:`2`), is the operation value for this
754 category of operation. The second parameter (``000000``\ :sub:`2`) is the
755 specific operation value for ``LD``/Load Word. The third parameter is the
756 output destination, which is a register operand and defined in the ``Register``
757 target description file (``IntRegs``).
761 def LDrr : F3_1 <3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr),
763 [(set i32:$dst, (load ADDRrr:$addr))]>;
765 The fourth parameter is the input source, which uses the address operand
766 ``MEMrr`` that is defined earlier in ``SparcInstrInfo.td``:
770 def MEMrr : Operand<i32> {
771 let PrintMethod = "printMemOperand";
772 let MIOperandInfo = (ops IntRegs, IntRegs);
775 The fifth parameter is a string that is used by the assembly printer and can be
776 left as an empty string until the assembly printer interface is implemented.
777 The sixth and final parameter is the pattern used to match the instruction
778 during the SelectionDAG Select Phase described in :doc:`CodeGenerator`.
779 This parameter is detailed in the next section, :ref:`instruction-selector`.
781 Instruction class definitions are not overloaded for different operand types,
782 so separate versions of instructions are needed for register, memory, or
783 immediate value operands. For example, to perform a Load Integer instruction
784 for a Word from an immediate operand to a register, the following instruction
789 def LDri : F3_2 <3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr),
791 [(set i32:$dst, (load ADDRri:$addr))]>;
793 Writing these definitions for so many similar instructions can involve a lot of
794 cut and paste. In ``.td`` files, the ``multiclass`` directive enables the
795 creation of templates to define several instruction classes at once (using the
796 ``defm`` directive). For example in ``SparcInstrInfo.td``, the ``multiclass``
797 pattern ``F3_12`` is defined to create 2 instruction classes each time
798 ``F3_12`` is invoked:
802 multiclass F3_12 <string OpcStr, bits<6> Op3Val, SDNode OpNode> {
803 def rr : F3_1 <2, Op3Val,
804 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
805 !strconcat(OpcStr, " $b, $c, $dst"),
806 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
807 def ri : F3_2 <2, Op3Val,
808 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
809 !strconcat(OpcStr, " $b, $c, $dst"),
810 [(set i32:$dst, (OpNode i32:$b, simm13:$c))]>;
813 So when the ``defm`` directive is used for the ``XOR`` and ``ADD``
814 instructions, as seen below, it creates four instruction objects: ``XORrr``,
815 ``XORri``, ``ADDrr``, and ``ADDri``.
819 defm XOR : F3_12<"xor", 0b000011, xor>;
820 defm ADD : F3_12<"add", 0b000000, add>;
822 ``SparcInstrInfo.td`` also includes definitions for condition codes that are
823 referenced by branch instructions. The following definitions in
824 ``SparcInstrInfo.td`` indicate the bit location of the SPARC condition code.
825 For example, the 10\ :sup:`th` bit represents the "greater than" condition for
826 integers, and the 22\ :sup:`nd` bit represents the "greater than" condition for
831 def ICC_NE : ICC_VAL< 9>; // Not Equal
832 def ICC_E : ICC_VAL< 1>; // Equal
833 def ICC_G : ICC_VAL<10>; // Greater
835 def FCC_U : FCC_VAL<23>; // Unordered
836 def FCC_G : FCC_VAL<22>; // Greater
837 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
840 (Note that ``Sparc.h`` also defines enums that correspond to the same SPARC
841 condition codes. Care must be taken to ensure the values in ``Sparc.h``
842 correspond to the values in ``SparcInstrInfo.td``. I.e., ``SPCC::ICC_NE = 9``,
843 ``SPCC::FCC_U = 23`` and so on.)
845 Instruction Operand Mapping
846 ---------------------------
848 The code generator backend maps instruction operands to fields in the
849 instruction. Operands are assigned to unbound fields in the instruction in the
850 order they are defined. Fields are bound when they are assigned a value. For
851 example, the Sparc target defines the ``XNORrr`` instruction as a ``F3_1``
852 format instruction having three operands.
856 def XNORrr : F3_1<2, 0b000111,
857 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
859 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
861 The instruction templates in ``SparcInstrFormats.td`` show the base class for
862 ``F3_1`` is ``InstSP``.
866 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
868 let Namespace = "SP";
870 let Inst{31-30} = op;
871 dag OutOperandList = outs;
872 dag InOperandList = ins;
873 let AsmString = asmstr;
874 let Pattern = pattern;
877 ``InstSP`` leaves the ``op`` field unbound.
881 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
882 : InstSP<outs, ins, asmstr, pattern> {
886 let op{1} = 1; // Op = 2 or 3
887 let Inst{29-25} = rd;
888 let Inst{24-19} = op3;
889 let Inst{18-14} = rs1;
892 ``F3`` binds the ``op`` field and defines the ``rd``, ``op3``, and ``rs1``
893 fields. ``F3`` format instructions will bind the operands ``rd``, ``op3``, and
898 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
899 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
900 bits<8> asi = 0; // asi not currently used
904 let Inst{13} = 0; // i field = 0
905 let Inst{12-5} = asi; // address space identifier
909 ``F3_1`` binds the ``op3`` field and defines the ``rs2`` fields. ``F3_1``
910 format instructions will bind the operands to the ``rd``, ``rs1``, and ``rs2``
911 fields. This results in the ``XNORrr`` instruction binding ``$dst``, ``$b``,
912 and ``$c`` operands to the ``rd``, ``rs1``, and ``rs2`` fields respectively.
914 TableGen will also generate a function called getNamedOperandIdx() which
915 can be used to look up an operand's index in a MachineInstr based on its
916 TableGen name. Setting the UseNamedOperandTable bit in an instruction's
917 TableGen definition will add all of its operands to an enumeration in the
918 llvm::XXX:OpName namespace and also add an entry for it into the OperandMap
919 table, which can be queried using getNamedOperandIdx()
923 int DstIndex = SP::getNamedOperandIdx(SP::XNORrr, SP::OpName::dst); // => 0
924 int BIndex = SP::getNamedOperandIdx(SP::XNORrr, SP::OpName::b); // => 1
925 int CIndex = SP::getNamedOperandIdx(SP::XNORrr, SP::OpName::c); // => 2
926 int DIndex = SP::getNamedOperandIdx(SP::XNORrr, SP::OpName::d); // => -1
930 The entries in the OpName enum are taken verbatim from the TableGen definitions,
931 so operands with lowercase names will have lower case entries in the enum.
933 To include the getNamedOperandIdx() function in your backend, you will need
934 to define a few preprocessor macros in XXXInstrInfo.cpp and XXXInstrInfo.h.
941 #define GET_INSTRINFO_NAMED_OPS // For getNamedOperandIdx() function
942 #include "XXXGenInstrInfo.inc"
948 #define GET_INSTRINFO_OPERAND_ENUM // For OpName enum
949 #include "XXXGenInstrInfo.inc"
952 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
953 } // End namespace XXX
955 Instruction Relation Mapping
956 ----------------------------
958 This TableGen feature is used to relate instructions with each other. It is
959 particularly useful when you have multiple instruction formats and need to
960 switch between them after instruction selection. This entire feature is driven
961 by relation models which can be defined in ``XXXInstrInfo.td`` files
962 according to the target-specific instruction set. Relation models are defined
963 using ``InstrMapping`` class as a base. TableGen parses all the models
964 and generates instruction relation maps using the specified information.
965 Relation maps are emitted as tables in the ``XXXGenInstrInfo.inc`` file
966 along with the functions to query them. For the detailed information on how to
967 use this feature, please refer to :doc:`HowToUseInstrMappings`.
969 Implement a subclass of ``TargetInstrInfo``
970 -------------------------------------------
972 The final step is to hand code portions of ``XXXInstrInfo``, which implements
973 the interface described in ``TargetInstrInfo.h`` (see :ref:`TargetInstrInfo`).
974 These functions return ``0`` or a Boolean or they assert, unless overridden.
975 Here's a list of functions that are overridden for the SPARC implementation in
976 ``SparcInstrInfo.cpp``:
978 * ``isLoadFromStackSlot`` --- If the specified machine instruction is a direct
979 load from a stack slot, return the register number of the destination and the
980 ``FrameIndex`` of the stack slot.
982 * ``isStoreToStackSlot`` --- If the specified machine instruction is a direct
983 store to a stack slot, return the register number of the destination and the
984 ``FrameIndex`` of the stack slot.
986 * ``copyPhysReg`` --- Copy values between a pair of physical registers.
988 * ``storeRegToStackSlot`` --- Store a register value to a stack slot.
990 * ``loadRegFromStackSlot`` --- Load a register value from a stack slot.
992 * ``storeRegToAddr`` --- Store a register value to memory.
994 * ``loadRegFromAddr`` --- Load a register value from memory.
996 * ``foldMemoryOperand`` --- Attempt to combine instructions of any load or
997 store instruction for the specified operand(s).
999 Branch Folding and If Conversion
1000 --------------------------------
1002 Performance can be improved by combining instructions or by eliminating
1003 instructions that are never reached. The ``AnalyzeBranch`` method in
1004 ``XXXInstrInfo`` may be implemented to examine conditional instructions and
1005 remove unnecessary instructions. ``AnalyzeBranch`` looks at the end of a
1006 machine basic block (MBB) for opportunities for improvement, such as branch
1007 folding and if conversion. The ``BranchFolder`` and ``IfConverter`` machine
1008 function passes (see the source files ``BranchFolding.cpp`` and
1009 ``IfConversion.cpp`` in the ``lib/CodeGen`` directory) call ``AnalyzeBranch``
1010 to improve the control flow graph that represents the instructions.
1012 Several implementations of ``AnalyzeBranch`` (for ARM, Alpha, and X86) can be
1013 examined as models for your own ``AnalyzeBranch`` implementation. Since SPARC
1014 does not implement a useful ``AnalyzeBranch``, the ARM target implementation is
1017 ``AnalyzeBranch`` returns a Boolean value and takes four parameters:
1019 * ``MachineBasicBlock &MBB`` --- The incoming block to be examined.
1021 * ``MachineBasicBlock *&TBB`` --- A destination block that is returned. For a
1022 conditional branch that evaluates to true, ``TBB`` is the destination.
1024 * ``MachineBasicBlock *&FBB`` --- For a conditional branch that evaluates to
1025 false, ``FBB`` is returned as the destination.
1027 * ``std::vector<MachineOperand> &Cond`` --- List of operands to evaluate a
1028 condition for a conditional branch.
1030 In the simplest case, if a block ends without a branch, then it falls through
1031 to the successor block. No destination blocks are specified for either ``TBB``
1032 or ``FBB``, so both parameters return ``NULL``. The start of the
1033 ``AnalyzeBranch`` (see code below for the ARM target) shows the function
1034 parameters and the code for the simplest case.
1038 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1039 MachineBasicBlock *&TBB,
1040 MachineBasicBlock *&FBB,
1041 std::vector<MachineOperand> &Cond) const
1043 MachineBasicBlock::iterator I = MBB.end();
1044 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
1047 If a block ends with a single unconditional branch instruction, then
1048 ``AnalyzeBranch`` (shown below) should return the destination of that branch in
1049 the ``TBB`` parameter.
1053 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
1054 TBB = LastInst->getOperand(0).getMBB();
1058 If a block ends with two unconditional branches, then the second branch is
1059 never reached. In that situation, as shown below, remove the last branch
1060 instruction and return the penultimate branch in the ``TBB`` parameter.
1064 if ((SecondLastOpc == ARM::B || SecondLastOpc == ARM::tB) &&
1065 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
1066 TBB = SecondLastInst->getOperand(0).getMBB();
1068 I->eraseFromParent();
1072 A block may end with a single conditional branch instruction that falls through
1073 to successor block if the condition evaluates to false. In that case,
1074 ``AnalyzeBranch`` (shown below) should return the destination of that
1075 conditional branch in the ``TBB`` parameter and a list of operands in the
1076 ``Cond`` parameter to evaluate the condition.
1080 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
1081 // Block ends with fall-through condbranch.
1082 TBB = LastInst->getOperand(0).getMBB();
1083 Cond.push_back(LastInst->getOperand(1));
1084 Cond.push_back(LastInst->getOperand(2));
1088 If a block ends with both a conditional branch and an ensuing unconditional
1089 branch, then ``AnalyzeBranch`` (shown below) should return the conditional
1090 branch destination (assuming it corresponds to a conditional evaluation of
1091 "``true``") in the ``TBB`` parameter and the unconditional branch destination
1092 in the ``FBB`` (corresponding to a conditional evaluation of "``false``"). A
1093 list of operands to evaluate the condition should be returned in the ``Cond``
1098 unsigned SecondLastOpc = SecondLastInst->getOpcode();
1100 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
1101 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
1102 TBB = SecondLastInst->getOperand(0).getMBB();
1103 Cond.push_back(SecondLastInst->getOperand(1));
1104 Cond.push_back(SecondLastInst->getOperand(2));
1105 FBB = LastInst->getOperand(0).getMBB();
1109 For the last two cases (ending with a single conditional branch or ending with
1110 one conditional and one unconditional branch), the operands returned in the
1111 ``Cond`` parameter can be passed to methods of other instructions to create new
1112 branches or perform other operations. An implementation of ``AnalyzeBranch``
1113 requires the helper methods ``RemoveBranch`` and ``InsertBranch`` to manage
1114 subsequent operations.
1116 ``AnalyzeBranch`` should return false indicating success in most circumstances.
1117 ``AnalyzeBranch`` should only return true when the method is stumped about what
1118 to do, for example, if a block has three terminating branches.
1119 ``AnalyzeBranch`` may return true if it encounters a terminator it cannot
1120 handle, such as an indirect branch.
1122 .. _instruction-selector:
1124 Instruction Selector
1125 ====================
1127 LLVM uses a ``SelectionDAG`` to represent LLVM IR instructions, and nodes of
1128 the ``SelectionDAG`` ideally represent native target instructions. During code
1129 generation, instruction selection passes are performed to convert non-native
1130 DAG instructions into native target-specific instructions. The pass described
1131 in ``XXXISelDAGToDAG.cpp`` is used to match patterns and perform DAG-to-DAG
1132 instruction selection. Optionally, a pass may be defined (in
1133 ``XXXBranchSelector.cpp``) to perform similar DAG-to-DAG operations for branch
1134 instructions. Later, the code in ``XXXISelLowering.cpp`` replaces or removes
1135 operations and data types not supported natively (legalizes) in a
1138 TableGen generates code for instruction selection using the following target
1139 description input files:
1141 * ``XXXInstrInfo.td`` --- Contains definitions of instructions in a
1142 target-specific instruction set, generates ``XXXGenDAGISel.inc``, which is
1143 included in ``XXXISelDAGToDAG.cpp``.
1145 * ``XXXCallingConv.td`` --- Contains the calling and return value conventions
1146 for the target architecture, and it generates ``XXXGenCallingConv.inc``,
1147 which is included in ``XXXISelLowering.cpp``.
1149 The implementation of an instruction selection pass must include a header that
1150 declares the ``FunctionPass`` class or a subclass of ``FunctionPass``. In
1151 ``XXXTargetMachine.cpp``, a Pass Manager (PM) should add each instruction
1152 selection pass into the queue of passes to run.
1154 The LLVM static compiler (``llc``) is an excellent tool for visualizing the
1155 contents of DAGs. To display the ``SelectionDAG`` before or after specific
1156 processing phases, use the command line options for ``llc``, described at
1157 :ref:`SelectionDAG-Process`.
1159 To describe instruction selector behavior, you should add patterns for lowering
1160 LLVM code into a ``SelectionDAG`` as the last parameter of the instruction
1161 definitions in ``XXXInstrInfo.td``. For example, in ``SparcInstrInfo.td``,
1162 this entry defines a register store operation, and the last parameter describes
1163 a pattern with the store DAG operator.
1165 .. code-block:: llvm
1167 def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
1168 "st $src, [$addr]", [(store i32:$src, ADDRrr:$addr)]>;
1170 ``ADDRrr`` is a memory mode that is also defined in ``SparcInstrInfo.td``:
1172 .. code-block:: llvm
1174 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
1176 The definition of ``ADDRrr`` refers to ``SelectADDRrr``, which is a function
1177 defined in an implementation of the Instructor Selector (such as
1178 ``SparcISelDAGToDAG.cpp``).
1180 In ``lib/Target/TargetSelectionDAG.td``, the DAG operator for store is defined
1183 .. code-block:: llvm
1185 def store : PatFrag<(ops node:$val, node:$ptr),
1186 (st node:$val, node:$ptr), [{
1187 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
1188 return !ST->isTruncatingStore() &&
1189 ST->getAddressingMode() == ISD::UNINDEXED;
1193 ``XXXInstrInfo.td`` also generates (in ``XXXGenDAGISel.inc``) the
1194 ``SelectCode`` method that is used to call the appropriate processing method
1195 for an instruction. In this example, ``SelectCode`` calls ``Select_ISD_STORE``
1196 for the ``ISD::STORE`` opcode.
1200 SDNode *SelectCode(SDValue N) {
1202 MVT::ValueType NVT = N.getNode()->getValueType(0);
1203 switch (N.getOpcode()) {
1207 return Select_ISD_STORE(N);
1214 The pattern for ``STrr`` is matched, so elsewhere in ``XXXGenDAGISel.inc``,
1215 code for ``STrr`` is created for ``Select_ISD_STORE``. The ``Emit_22`` method
1216 is also generated in ``XXXGenDAGISel.inc`` to complete the processing of this
1221 SDNode *Select_ISD_STORE(const SDValue &N) {
1222 SDValue Chain = N.getOperand(0);
1223 if (Predicate_store(N.getNode())) {
1224 SDValue N1 = N.getOperand(1);
1225 SDValue N2 = N.getOperand(2);
1229 // Pattern: (st:void i32:i32:$src,
1230 // ADDRrr:i32:$addr)<<P:Predicate_store>>
1231 // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
1232 // Pattern complexity = 13 cost = 1 size = 0
1233 if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &&
1234 N1.getNode()->getValueType(0) == MVT::i32 &&
1235 N2.getNode()->getValueType(0) == MVT::i32) {
1236 return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
1240 The SelectionDAG Legalize Phase
1241 -------------------------------
1243 The Legalize phase converts a DAG to use types and operations that are natively
1244 supported by the target. For natively unsupported types and operations, you
1245 need to add code to the target-specific ``XXXTargetLowering`` implementation to
1246 convert unsupported types and operations to supported ones.
1248 In the constructor for the ``XXXTargetLowering`` class, first use the
1249 ``addRegisterClass`` method to specify which types are supported and which
1250 register classes are associated with them. The code for the register classes
1251 are generated by TableGen from ``XXXRegisterInfo.td`` and placed in
1252 ``XXXGenRegisterInfo.h.inc``. For example, the implementation of the
1253 constructor for the SparcTargetLowering class (in ``SparcISelLowering.cpp``)
1254 starts with the following code:
1258 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
1259 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
1260 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
1262 You should examine the node types in the ``ISD`` namespace
1263 (``include/llvm/CodeGen/SelectionDAGNodes.h``) and determine which operations
1264 the target natively supports. For operations that do **not** have native
1265 support, add a callback to the constructor for the ``XXXTargetLowering`` class,
1266 so the instruction selection process knows what to do. The ``TargetLowering``
1267 class callback methods (declared in ``llvm/Target/TargetLowering.h``) are:
1269 * ``setOperationAction`` --- General operation.
1270 * ``setLoadExtAction`` --- Load with extension.
1271 * ``setTruncStoreAction`` --- Truncating store.
1272 * ``setIndexedLoadAction`` --- Indexed load.
1273 * ``setIndexedStoreAction`` --- Indexed store.
1274 * ``setConvertAction`` --- Type conversion.
1275 * ``setCondCodeAction`` --- Support for a given condition code.
1277 Note: on older releases, ``setLoadXAction`` is used instead of
1278 ``setLoadExtAction``. Also, on older releases, ``setCondCodeAction`` may not
1279 be supported. Examine your release to see what methods are specifically
1282 These callbacks are used to determine that an operation does or does not work
1283 with a specified type (or types). And in all cases, the third parameter is a
1284 ``LegalAction`` type enum value: ``Promote``, ``Expand``, ``Custom``, or
1285 ``Legal``. ``SparcISelLowering.cpp`` contains examples of all four
1286 ``LegalAction`` values.
1291 For an operation without native support for a given type, the specified type
1292 may be promoted to a larger type that is supported. For example, SPARC does
1293 not support a sign-extending load for Boolean values (``i1`` type), so in
1294 ``SparcISelLowering.cpp`` the third parameter below, ``Promote``, changes
1295 ``i1`` type values to a large type before loading.
1299 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1304 For a type without native support, a value may need to be broken down further,
1305 rather than promoted. For an operation without native support, a combination
1306 of other operations may be used to similar effect. In SPARC, the
1307 floating-point sine and cosine trig operations are supported by expansion to
1308 other operations, as indicated by the third parameter, ``Expand``, to
1309 ``setOperationAction``:
1313 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1314 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1319 For some operations, simple type promotion or operation expansion may be
1320 insufficient. In some cases, a special intrinsic function must be implemented.
1322 For example, a constant value may require special treatment, or an operation
1323 may require spilling and restoring registers in the stack and working with
1324 register allocators.
1326 As seen in ``SparcISelLowering.cpp`` code below, to perform a type conversion
1327 from a floating point value to a signed integer, first the
1328 ``setOperationAction`` should be called with ``Custom`` as the third parameter:
1332 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1334 In the ``LowerOperation`` method, for each ``Custom`` operation, a case
1335 statement should be added to indicate what function to call. In the following
1336 code, an ``FP_TO_SINT`` opcode will call the ``LowerFP_TO_SINT`` method:
1340 SDValue SparcTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1341 switch (Op.getOpcode()) {
1342 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1347 Finally, the ``LowerFP_TO_SINT`` method is implemented, using an FP register to
1348 convert the floating-point value to an integer.
1352 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
1353 assert(Op.getValueType() == MVT::i32);
1354 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
1355 return DAG.getNode(ISD::BITCAST, MVT::i32, Op);
1361 The ``Legal`` ``LegalizeAction`` enum value simply indicates that an operation
1362 **is** natively supported. ``Legal`` represents the default condition, so it
1363 is rarely used. In ``SparcISelLowering.cpp``, the action for ``CTPOP`` (an
1364 operation to count the bits set in an integer) is natively supported only for
1365 SPARC v9. The following code enables the ``Expand`` conversion technique for
1366 non-v9 SPARC implementations.
1370 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1372 if (TM.getSubtarget<SparcSubtarget>().isV9())
1373 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
1378 To support target-specific calling conventions, ``XXXGenCallingConv.td`` uses
1379 interfaces (such as ``CCIfType`` and ``CCAssignToReg``) that are defined in
1380 ``lib/Target/TargetCallingConv.td``. TableGen can take the target descriptor
1381 file ``XXXGenCallingConv.td`` and generate the header file
1382 ``XXXGenCallingConv.inc``, which is typically included in
1383 ``XXXISelLowering.cpp``. You can use the interfaces in
1384 ``TargetCallingConv.td`` to specify:
1386 * The order of parameter allocation.
1388 * Where parameters and return values are placed (that is, on the stack or in
1391 * Which registers may be used.
1393 * Whether the caller or callee unwinds the stack.
1395 The following example demonstrates the use of the ``CCIfType`` and
1396 ``CCAssignToReg`` interfaces. If the ``CCIfType`` predicate is true (that is,
1397 if the current argument is of type ``f32`` or ``f64``), then the action is
1398 performed. In this case, the ``CCAssignToReg`` action assigns the argument
1399 value to the first available register: either ``R0`` or ``R1``.
1401 .. code-block:: llvm
1403 CCIfType<[f32,f64], CCAssignToReg<[R0, R1]>>
1405 ``SparcCallingConv.td`` contains definitions for a target-specific return-value
1406 calling convention (``RetCC_Sparc32``) and a basic 32-bit C calling convention
1407 (``CC_Sparc32``). The definition of ``RetCC_Sparc32`` (shown below) indicates
1408 which registers are used for specified scalar return types. A single-precision
1409 float is returned to register ``F0``, and a double-precision float goes to
1410 register ``D0``. A 32-bit integer is returned in register ``I0`` or ``I1``.
1412 .. code-block:: llvm
1414 def RetCC_Sparc32 : CallingConv<[
1415 CCIfType<[i32], CCAssignToReg<[I0, I1]>>,
1416 CCIfType<[f32], CCAssignToReg<[F0]>>,
1417 CCIfType<[f64], CCAssignToReg<[D0]>>
1420 The definition of ``CC_Sparc32`` in ``SparcCallingConv.td`` introduces
1421 ``CCAssignToStack``, which assigns the value to a stack slot with the specified
1422 size and alignment. In the example below, the first parameter, 4, indicates
1423 the size of the slot, and the second parameter, also 4, indicates the stack
1424 alignment along 4-byte units. (Special cases: if size is zero, then the ABI
1425 size is used; if alignment is zero, then the ABI alignment is used.)
1427 .. code-block:: llvm
1429 def CC_Sparc32 : CallingConv<[
1430 // All arguments get passed in integer registers if there is space.
1431 CCIfType<[i32, f32, f64], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
1432 CCAssignToStack<4, 4>
1435 ``CCDelegateTo`` is another commonly used interface, which tries to find a
1436 specified sub-calling convention, and, if a match is found, it is invoked. In
1437 the following example (in ``X86CallingConv.td``), the definition of
1438 ``RetCC_X86_32_C`` ends with ``CCDelegateTo``. After the current value is
1439 assigned to the register ``ST0`` or ``ST1``, the ``RetCC_X86Common`` is
1442 .. code-block:: llvm
1444 def RetCC_X86_32_C : CallingConv<[
1445 CCIfType<[f32], CCAssignToReg<[ST0, ST1]>>,
1446 CCIfType<[f64], CCAssignToReg<[ST0, ST1]>>,
1447 CCDelegateTo<RetCC_X86Common>
1450 ``CCIfCC`` is an interface that attempts to match the given name to the current
1451 calling convention. If the name identifies the current calling convention,
1452 then a specified action is invoked. In the following example (in
1453 ``X86CallingConv.td``), if the ``Fast`` calling convention is in use, then
1454 ``RetCC_X86_32_Fast`` is invoked. If the ``SSECall`` calling convention is in
1455 use, then ``RetCC_X86_32_SSE`` is invoked.
1457 .. code-block:: llvm
1459 def RetCC_X86_32 : CallingConv<[
1460 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
1461 CCIfCC<"CallingConv::X86_SSECall", CCDelegateTo<RetCC_X86_32_SSE>>,
1462 CCDelegateTo<RetCC_X86_32_C>
1465 Other calling convention interfaces include:
1467 * ``CCIf <predicate, action>`` --- If the predicate matches, apply the action.
1469 * ``CCIfInReg <action>`` --- If the argument is marked with the "``inreg``"
1470 attribute, then apply the action.
1472 * ``CCIfNest <action>`` --- If the argument is marked with the "``nest``"
1473 attribute, then apply the action.
1475 * ``CCIfNotVarArg <action>`` --- If the current function does not take a
1476 variable number of arguments, apply the action.
1478 * ``CCAssignToRegWithShadow <registerList, shadowList>`` --- similar to
1479 ``CCAssignToReg``, but with a shadow list of registers.
1481 * ``CCPassByVal <size, align>`` --- Assign value to a stack slot with the
1482 minimum specified size and alignment.
1484 * ``CCPromoteToType <type>`` --- Promote the current value to the specified
1487 * ``CallingConv <[actions]>`` --- Define each calling convention that is
1493 During the code emission stage, the code generator may utilize an LLVM pass to
1494 produce assembly output. To do this, you want to implement the code for a
1495 printer that converts LLVM IR to a GAS-format assembly language for your target
1496 machine, using the following steps:
1498 * Define all the assembly strings for your target, adding them to the
1499 instructions defined in the ``XXXInstrInfo.td`` file. (See
1500 :ref:`instruction-set`.) TableGen will produce an output file
1501 (``XXXGenAsmWriter.inc``) with an implementation of the ``printInstruction``
1502 method for the ``XXXAsmPrinter`` class.
1504 * Write ``XXXTargetAsmInfo.h``, which contains the bare-bones declaration of
1505 the ``XXXTargetAsmInfo`` class (a subclass of ``TargetAsmInfo``).
1507 * Write ``XXXTargetAsmInfo.cpp``, which contains target-specific values for
1508 ``TargetAsmInfo`` properties and sometimes new implementations for methods.
1510 * Write ``XXXAsmPrinter.cpp``, which implements the ``AsmPrinter`` class that
1511 performs the LLVM-to-assembly conversion.
1513 The code in ``XXXTargetAsmInfo.h`` is usually a trivial declaration of the
1514 ``XXXTargetAsmInfo`` class for use in ``XXXTargetAsmInfo.cpp``. Similarly,
1515 ``XXXTargetAsmInfo.cpp`` usually has a few declarations of ``XXXTargetAsmInfo``
1516 replacement values that override the default values in ``TargetAsmInfo.cpp``.
1517 For example in ``SparcTargetAsmInfo.cpp``:
1521 SparcTargetAsmInfo::SparcTargetAsmInfo(const SparcTargetMachine &TM) {
1522 Data16bitsDirective = "\t.half\t";
1523 Data32bitsDirective = "\t.word\t";
1524 Data64bitsDirective = 0; // .xword is only supported by V9.
1525 ZeroDirective = "\t.skip\t";
1526 CommentString = "!";
1527 ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
1530 The X86 assembly printer implementation (``X86TargetAsmInfo``) is an example
1531 where the target specific ``TargetAsmInfo`` class uses an overridden methods:
1532 ``ExpandInlineAsm``.
1534 A target-specific implementation of ``AsmPrinter`` is written in
1535 ``XXXAsmPrinter.cpp``, which implements the ``AsmPrinter`` class that converts
1536 the LLVM to printable assembly. The implementation must include the following
1537 headers that have declarations for the ``AsmPrinter`` and
1538 ``MachineFunctionPass`` classes. The ``MachineFunctionPass`` is a subclass of
1543 #include "llvm/CodeGen/AsmPrinter.h"
1544 #include "llvm/CodeGen/MachineFunctionPass.h"
1546 As a ``FunctionPass``, ``AsmPrinter`` first calls ``doInitialization`` to set
1547 up the ``AsmPrinter``. In ``SparcAsmPrinter``, a ``Mangler`` object is
1548 instantiated to process variable names.
1550 In ``XXXAsmPrinter.cpp``, the ``runOnMachineFunction`` method (declared in
1551 ``MachineFunctionPass``) must be implemented for ``XXXAsmPrinter``. In
1552 ``MachineFunctionPass``, the ``runOnFunction`` method invokes
1553 ``runOnMachineFunction``. Target-specific implementations of
1554 ``runOnMachineFunction`` differ, but generally do the following to process each
1557 * Call ``SetupMachineFunction`` to perform initialization.
1559 * Call ``EmitConstantPool`` to print out (to the output stream) constants which
1560 have been spilled to memory.
1562 * Call ``EmitJumpTableInfo`` to print out jump tables used by the current
1565 * Print out the label for the current function.
1567 * Print out the code for the function, including basic block labels and the
1568 assembly for the instruction (using ``printInstruction``)
1570 The ``XXXAsmPrinter`` implementation must also include the code generated by
1571 TableGen that is output in the ``XXXGenAsmWriter.inc`` file. The code in
1572 ``XXXGenAsmWriter.inc`` contains an implementation of the ``printInstruction``
1573 method that may call these methods:
1576 * ``printMemOperand``
1577 * ``printCCOperand`` (for conditional statements)
1578 * ``printDataDirective``
1580 * ``printImplicitDef``
1581 * ``printInlineAsm``
1583 The implementations of ``printDeclare``, ``printImplicitDef``,
1584 ``printInlineAsm``, and ``printLabel`` in ``AsmPrinter.cpp`` are generally
1585 adequate for printing assembly and do not need to be overridden.
1587 The ``printOperand`` method is implemented with a long ``switch``/``case``
1588 statement for the type of operand: register, immediate, basic block, external
1589 symbol, global address, constant pool index, or jump table index. For an
1590 instruction with a memory address operand, the ``printMemOperand`` method
1591 should be implemented to generate the proper output. Similarly,
1592 ``printCCOperand`` should be used to print a conditional operand.
1594 ``doFinalization`` should be overridden in ``XXXAsmPrinter``, and it should be
1595 called to shut down the assembly printer. During ``doFinalization``, global
1596 variables and constants are printed to output.
1601 Subtarget support is used to inform the code generation process of instruction
1602 set variations for a given chip set. For example, the LLVM SPARC
1603 implementation provided covers three major versions of the SPARC microprocessor
1604 architecture: Version 8 (V8, which is a 32-bit architecture), Version 9 (V9, a
1605 64-bit architecture), and the UltraSPARC architecture. V8 has 16
1606 double-precision floating-point registers that are also usable as either 32
1607 single-precision or 8 quad-precision registers. V8 is also purely big-endian.
1608 V9 has 32 double-precision floating-point registers that are also usable as 16
1609 quad-precision registers, but cannot be used as single-precision registers.
1610 The UltraSPARC architecture combines V9 with UltraSPARC Visual Instruction Set
1613 If subtarget support is needed, you should implement a target-specific
1614 ``XXXSubtarget`` class for your architecture. This class should process the
1615 command-line options ``-mcpu=`` and ``-mattr=``.
1617 TableGen uses definitions in the ``Target.td`` and ``Sparc.td`` files to
1618 generate code in ``SparcGenSubtarget.inc``. In ``Target.td``, shown below, the
1619 ``SubtargetFeature`` interface is defined. The first 4 string parameters of
1620 the ``SubtargetFeature`` interface are a feature name, an attribute set by the
1621 feature, the value of the attribute, and a description of the feature. (The
1622 fifth parameter is a list of features whose presence is implied, and its
1623 default value is an empty array.)
1625 .. code-block:: llvm
1627 class SubtargetFeature<string n, string a, string v, string d,
1628 list<SubtargetFeature> i = []> {
1630 string Attribute = a;
1633 list<SubtargetFeature> Implies = i;
1636 In the ``Sparc.td`` file, the ``SubtargetFeature`` is used to define the
1639 .. code-block:: llvm
1641 def FeatureV9 : SubtargetFeature<"v9", "IsV9", "true",
1642 "Enable SPARC-V9 instructions">;
1643 def FeatureV8Deprecated : SubtargetFeature<"deprecated-v8",
1644 "V8DeprecatedInsts", "true",
1645 "Enable deprecated V8 instructions in V9 mode">;
1646 def FeatureVIS : SubtargetFeature<"vis", "IsVIS", "true",
1647 "Enable UltraSPARC Visual Instruction Set extensions">;
1649 Elsewhere in ``Sparc.td``, the ``Proc`` class is defined and then is used to
1650 define particular SPARC processor subtypes that may have the previously
1653 .. code-block:: llvm
1655 class Proc<string Name, list<SubtargetFeature> Features>
1656 : Processor<Name, NoItineraries, Features>;
1658 def : Proc<"generic", []>;
1659 def : Proc<"v8", []>;
1660 def : Proc<"supersparc", []>;
1661 def : Proc<"sparclite", []>;
1662 def : Proc<"f934", []>;
1663 def : Proc<"hypersparc", []>;
1664 def : Proc<"sparclite86x", []>;
1665 def : Proc<"sparclet", []>;
1666 def : Proc<"tsc701", []>;
1667 def : Proc<"v9", [FeatureV9]>;
1668 def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
1669 def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
1670 def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
1672 From ``Target.td`` and ``Sparc.td`` files, the resulting
1673 ``SparcGenSubtarget.inc`` specifies enum values to identify the features,
1674 arrays of constants to represent the CPU features and CPU subtypes, and the
1675 ``ParseSubtargetFeatures`` method that parses the features string that sets
1676 specified subtarget options. The generated ``SparcGenSubtarget.inc`` file
1677 should be included in the ``SparcSubtarget.cpp``. The target-specific
1678 implementation of the ``XXXSubtarget`` method should follow this pseudocode:
1682 XXXSubtarget::XXXSubtarget(const Module &M, const std::string &FS) {
1683 // Set the default features
1684 // Determine default and user specified characteristics of the CPU
1685 // Call ParseSubtargetFeatures(FS, CPU) to parse the features string
1686 // Perform any additional operations
1692 The implementation of a target machine optionally includes a Just-In-Time (JIT)
1693 code generator that emits machine code and auxiliary structures as binary
1694 output that can be written directly to memory. To do this, implement JIT code
1695 generation by performing the following steps:
1697 * Write an ``XXXCodeEmitter.cpp`` file that contains a machine function pass
1698 that transforms target-machine instructions into relocatable machine
1701 * Write an ``XXXJITInfo.cpp`` file that implements the JIT interfaces for
1702 target-specific code-generation activities, such as emitting machine code and
1705 * Modify ``XXXTargetMachine`` so that it provides a ``TargetJITInfo`` object
1706 through its ``getJITInfo`` method.
1708 There are several different approaches to writing the JIT support code. For
1709 instance, TableGen and target descriptor files may be used for creating a JIT
1710 code generator, but are not mandatory. For the Alpha and PowerPC target
1711 machines, TableGen is used to generate ``XXXGenCodeEmitter.inc``, which
1712 contains the binary coding of machine instructions and the
1713 ``getBinaryCodeForInstr`` method to access those codes. Other JIT
1714 implementations do not.
1716 Both ``XXXJITInfo.cpp`` and ``XXXCodeEmitter.cpp`` must include the
1717 ``llvm/CodeGen/MachineCodeEmitter.h`` header file that defines the
1718 ``MachineCodeEmitter`` class containing code for several callback functions
1719 that write data (in bytes, words, strings, etc.) to the output stream.
1721 Machine Code Emitter
1722 --------------------
1724 In ``XXXCodeEmitter.cpp``, a target-specific of the ``Emitter`` class is
1725 implemented as a function pass (subclass of ``MachineFunctionPass``). The
1726 target-specific implementation of ``runOnMachineFunction`` (invoked by
1727 ``runOnFunction`` in ``MachineFunctionPass``) iterates through the
1728 ``MachineBasicBlock`` calls ``emitInstruction`` to process each instruction and
1729 emit binary code. ``emitInstruction`` is largely implemented with case
1730 statements on the instruction types defined in ``XXXInstrInfo.h``. For
1731 example, in ``X86CodeEmitter.cpp``, the ``emitInstruction`` method is built
1732 around the following ``switch``/``case`` statements:
1736 switch (Desc->TSFlags & X86::FormMask) {
1737 case X86II::Pseudo: // for not yet implemented instructions
1738 ... // or pseudo-instructions
1740 case X86II::RawFrm: // for instructions with a fixed opcode value
1743 case X86II::AddRegFrm: // for instructions that have one register operand
1744 ... // added to their opcode
1746 case X86II::MRMDestReg:// for instructions that use the Mod/RM byte
1747 ... // to specify a destination (register)
1749 case X86II::MRMDestMem:// for instructions that use the Mod/RM byte
1750 ... // to specify a destination (memory)
1752 case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte
1753 ... // to specify a source (register)
1755 case X86II::MRMSrcMem: // for instructions that use the Mod/RM byte
1756 ... // to specify a source (memory)
1758 case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on
1759 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
1760 case X86II::MRM4r: case X86II::MRM5r: // use the Mod/RM byte and a field
1761 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
1764 case X86II::MRM0m: case X86II::MRM1m: // for instructions that operate on
1765 case X86II::MRM2m: case X86II::MRM3m: // a MEMORY r/m operand and
1766 case X86II::MRM4m: case X86II::MRM5m: // use the Mod/RM byte and a field
1767 case X86II::MRM6m: case X86II::MRM7m: // to hold extended opcode data
1770 case X86II::MRMInitReg: // for instructions whose source and
1771 ... // destination are the same register
1775 The implementations of these case statements often first emit the opcode and
1776 then get the operand(s). Then depending upon the operand, helper methods may
1777 be called to process the operand(s). For example, in ``X86CodeEmitter.cpp``,
1778 for the ``X86II::AddRegFrm`` case, the first data emitted (by ``emitByte``) is
1779 the opcode added to the register operand. Then an object representing the
1780 machine operand, ``MO1``, is extracted. The helper methods such as
1781 ``isImmediate``, ``isGlobalAddress``, ``isExternalSymbol``,
1782 ``isConstantPoolIndex``, and ``isJumpTableIndex`` determine the operand type.
1783 (``X86CodeEmitter.cpp`` also has private methods such as ``emitConstant``,
1784 ``emitGlobalAddress``, ``emitExternalSymbolAddress``, ``emitConstPoolAddress``,
1785 and ``emitJumpTableAddress`` that emit the data into the output stream.)
1789 case X86II::AddRegFrm:
1790 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
1792 if (CurOp != NumOps) {
1793 const MachineOperand &MO1 = MI.getOperand(CurOp++);
1794 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
1795 if (MO1.isImmediate())
1796 emitConstant(MO1.getImm(), Size);
1798 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
1799 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
1800 if (Opcode == X86::MOV64ri)
1801 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
1802 if (MO1.isGlobalAddress()) {
1803 bool NeedStub = isa<Function>(MO1.getGlobal());
1804 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
1805 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
1807 } else if (MO1.isExternalSymbol())
1808 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
1809 else if (MO1.isConstantPoolIndex())
1810 emitConstPoolAddress(MO1.getIndex(), rt);
1811 else if (MO1.isJumpTableIndex())
1812 emitJumpTableAddress(MO1.getIndex(), rt);
1817 In the previous example, ``XXXCodeEmitter.cpp`` uses the variable ``rt``, which
1818 is a ``RelocationType`` enum that may be used to relocate addresses (for
1819 example, a global address with a PIC base offset). The ``RelocationType`` enum
1820 for that target is defined in the short target-specific ``XXXRelocations.h``
1821 file. The ``RelocationType`` is used by the ``relocate`` method defined in
1822 ``XXXJITInfo.cpp`` to rewrite addresses for referenced global symbols.
1824 For example, ``X86Relocations.h`` specifies the following relocation types for
1825 the X86 addresses. In all four cases, the relocated value is added to the
1826 value already in memory. For ``reloc_pcrel_word`` and ``reloc_picrel_word``,
1827 there is an additional initial adjustment.
1831 enum RelocationType {
1832 reloc_pcrel_word = 0, // add reloc value after adjusting for the PC loc
1833 reloc_picrel_word = 1, // add reloc value after adjusting for the PIC base
1834 reloc_absolute_word = 2, // absolute relocation; no additional adjustment
1835 reloc_absolute_dword = 3 // absolute relocation; no additional adjustment
1841 ``XXXJITInfo.cpp`` implements the JIT interfaces for target-specific
1842 code-generation activities, such as emitting machine code and stubs. At
1843 minimum, a target-specific version of ``XXXJITInfo`` implements the following:
1845 * ``getLazyResolverFunction`` --- Initializes the JIT, gives the target a
1846 function that is used for compilation.
1848 * ``emitFunctionStub`` --- Returns a native function with a specified address
1849 for a callback function.
1851 * ``relocate`` --- Changes the addresses of referenced globals, based on
1854 * Callback function that are wrappers to a function stub that is used when the
1855 real target is not initially known.
1857 ``getLazyResolverFunction`` is generally trivial to implement. It makes the
1858 incoming parameter as the global ``JITCompilerFunction`` and returns the
1859 callback function that will be used a function wrapper. For the Alpha target
1860 (in ``AlphaJITInfo.cpp``), the ``getLazyResolverFunction`` implementation is
1865 TargetJITInfo::LazyResolverFn AlphaJITInfo::getLazyResolverFunction(
1867 JITCompilerFunction = F;
1868 return AlphaCompilationCallback;
1871 For the X86 target, the ``getLazyResolverFunction`` implementation is a little
1872 more complicated, because it returns a different callback function for
1873 processors with SSE instructions and XMM registers.
1875 The callback function initially saves and later restores the callee register
1876 values, incoming arguments, and frame and return address. The callback
1877 function needs low-level access to the registers or stack, so it is typically
1878 implemented with assembler.