drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/platform_data/clk-lpss.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/delay.h>
  23
  24 #include "internal.h"
  25
  26 ACPI_MODULE_NAME("acpi_lpss");
  27
  28 #ifdef CONFIG_X86_INTEL_LPSS
  29
  30 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  31
  32 #define LPSS_CLK_SIZE   0x04
  33 #define LPSS_LTR_SIZE   0x18
  34
  35 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  36 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  37 #define LPSS_RESETS                     0x04
  38 #define LPSS_RESETS_RESET_FUNC          BIT(0)
  39 #define LPSS_RESETS_RESET_APB           BIT(1)
  40 #define LPSS_GENERAL                    0x08
  41 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  42 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  43 #define LPSS_SW_LTR                     0x10
  44 #define LPSS_AUTO_LTR                   0x14
  45 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  46 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  47 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  48 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  49 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  50 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  51 #define LPSS_LTR_MAX_VAL                0x3FF
  52 #define LPSS_TX_INT                     0x20
  53 #define LPSS_TX_INT_MASK                BIT(1)
  54
  55 #define LPSS_PRV_REG_COUNT              9
  56
  57 /* LPSS Flags */
  58 #define LPSS_CLK                        BIT(0)
  59 #define LPSS_CLK_GATE                   BIT(1)
  60 #define LPSS_CLK_DIVIDER                BIT(2)
  61 #define LPSS_LTR                        BIT(3)
  62 #define LPSS_SAVE_CTX                   BIT(4)
  63 #define LPSS_NO_D3_DELAY                BIT(5)
  64
  65 struct lpss_private_data;
  66
  67 struct lpss_device_desc {
  68         unsigned int flags;
  69         const char *clk_con_id;
  70         unsigned int prv_offset;
  71         size_t prv_size_override;
  72         void (*setup)(struct lpss_private_data *pdata);
  73 };
  74
  75 static struct lpss_device_desc lpss_dma_desc = {
  76         .flags = LPSS_CLK,
  77 };
  78
  79 struct lpss_private_data {
  80         void __iomem *mmio_base;
  81         resource_size_t mmio_size;
  82         unsigned int fixed_clk_rate;
  83         struct clk *clk;
  84         const struct lpss_device_desc *dev_desc;
  85         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  86 };
  87
  88 /* UART Component Parameter Register */
  89 #define LPSS_UART_CPR                   0xF4
  90 #define LPSS_UART_CPR_AFCE              BIT(4)
  91
  92 static void lpss_uart_setup(struct lpss_private_data *pdata)
  93 {
  94         unsigned int offset;
  95         u32 val;
  96
  97         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
  98         val = readl(pdata->mmio_base + offset);
  99         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
 100
 101         val = readl(pdata->mmio_base + LPSS_UART_CPR);
 102         if (!(val & LPSS_UART_CPR_AFCE)) {
 103                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
 104                 val = readl(pdata->mmio_base + offset);
 105                 val |= LPSS_GENERAL_UART_RTS_OVRD;
 106                 writel(val, pdata->mmio_base + offset);
 107         }
 108 }
 109
 110 static void lpss_deassert_reset(struct lpss_private_data *pdata)
 111 {
 112         unsigned int offset;
 113         u32 val;
 114
 115         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
 116         val = readl(pdata->mmio_base + offset);
 117         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
 118         writel(val, pdata->mmio_base + offset);
 119 }
 120
 121 #define LPSS_I2C_ENABLE                 0x6c
 122
 123 static void byt_i2c_setup(struct lpss_private_data *pdata)
 124 {
 125         lpss_deassert_reset(pdata);
 126
 127         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
 128                 pdata->fixed_clk_rate = 133000000;
 129
 130         writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
 131 }
 132
 133 static const struct lpss_device_desc lpt_dev_desc = {
 134         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 135         .prv_offset = 0x800,
 136 };
 137
 138 static const struct lpss_device_desc lpt_i2c_dev_desc = {
 139         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
 140         .prv_offset = 0x800,
 141 };
 142
 143 static const struct lpss_device_desc lpt_uart_dev_desc = {
 144         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 145         .clk_con_id = "baudclk",
 146         .prv_offset = 0x800,
 147         .setup = lpss_uart_setup,
 148 };
 149
 150 static const struct lpss_device_desc lpt_sdio_dev_desc = {
 151         .flags = LPSS_LTR,
 152         .prv_offset = 0x1000,
 153         .prv_size_override = 0x1018,
 154 };
 155
 156 static const struct lpss_device_desc byt_pwm_dev_desc = {
 157         .flags = LPSS_SAVE_CTX,
 158 };
 159
 160 static const struct lpss_device_desc bsw_pwm_dev_desc = {
 161         .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 162 };
 163
 164 static const struct lpss_device_desc byt_uart_dev_desc = {
 165         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 166         .clk_con_id = "baudclk",
 167         .prv_offset = 0x800,
 168         .setup = lpss_uart_setup,
 169 };
 170
 171 static const struct lpss_device_desc bsw_uart_dev_desc = {
 172         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 173                         | LPSS_NO_D3_DELAY,
 174         .clk_con_id = "baudclk",
 175         .prv_offset = 0x800,
 176         .setup = lpss_uart_setup,
 177 };
 178
 179 static const struct lpss_device_desc byt_spi_dev_desc = {
 180         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 181         .prv_offset = 0x400,
 182 };
 183
 184 static const struct lpss_device_desc byt_sdio_dev_desc = {
 185         .flags = LPSS_CLK,
 186 };
 187
 188 static const struct lpss_device_desc byt_i2c_dev_desc = {
 189         .flags = LPSS_CLK | LPSS_SAVE_CTX,
 190         .prv_offset = 0x800,
 191         .setup = byt_i2c_setup,
 192 };
 193
 194 static const struct lpss_device_desc bsw_i2c_dev_desc = {
 195         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 196         .prv_offset = 0x800,
 197         .setup = byt_i2c_setup,
 198 };
 199
 200 static struct lpss_device_desc bsw_spi_dev_desc = {
 201         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 202                         | LPSS_NO_D3_DELAY,
 203         .prv_offset = 0x400,
 204         .setup = lpss_deassert_reset,
 205 };
 206
 207 #else
 208
 209 #define LPSS_ADDR(desc) (0UL)
 210
 211 #endif /* CONFIG_X86_INTEL_LPSS */
 212
 213 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 214         /* Generic LPSS devices */
 215         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 216
 217         /* Lynxpoint LPSS devices */
 218         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 219         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 220         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 221         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 222         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 223         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 224         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 225         { "INT33C7", },
 226
 227         /* BayTrail LPSS devices */
 228         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 229         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 230         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 231         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 232         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 233         { "INT33B2", },
 234         { "INT33FC", },
 235
 236         /* Braswell LPSS devices */
 237         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
 238         { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
 239         { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
 240         { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
 241
 242         /* Broadwell LPSS devices */
 243         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 244         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 245         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 246         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 247         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 248         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 249         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 250         { "INT3437", },
 251
 252         /* Wildcat Point LPSS devices */
 253         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
 254
 255         { }
 256 };
 257
 258 #ifdef CONFIG_X86_INTEL_LPSS
 259
 260 static int is_memory(struct acpi_resource *res, void *not_used)
 261 {
 262         struct resource r;
 263         return !acpi_dev_resource_memory(res, &r);
 264 }
 265
 266 /* LPSS main clock device. */
 267 static struct platform_device *lpss_clk_dev;
 268
 269 static inline void lpt_register_clock_device(void)
 270 {
 271         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 272 }
 273
 274 static int register_device_clock(struct acpi_device *adev,
 275                                  struct lpss_private_data *pdata)
 276 {
 277         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 278         const char *devname = dev_name(&adev->dev);
 279         struct clk *clk = ERR_PTR(-ENODEV);
 280         struct lpss_clk_data *clk_data;
 281         const char *parent, *clk_name;
 282         void __iomem *prv_base;
 283
 284         if (!lpss_clk_dev)
 285                 lpt_register_clock_device();
 286
 287         clk_data = platform_get_drvdata(lpss_clk_dev);
 288         if (!clk_data)
 289                 return -ENODEV;
 290         clk = clk_data->clk;
 291
 292         if (!pdata->mmio_base
 293             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 294                 return -ENODATA;
 295
 296         parent = clk_data->name;
 297         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 298
 299         if (pdata->fixed_clk_rate) {
 300                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
 301                                               pdata->fixed_clk_rate);
 302                 goto out;
 303         }
 304
 305         if (dev_desc->flags & LPSS_CLK_GATE) {
 306                 clk = clk_register_gate(NULL, devname, parent, 0,
 307                                         prv_base, 0, 0, NULL);
 308                 parent = devname;
 309         }
 310
 311         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
 312                 /* Prevent division by zero */
 313                 if (!readl(prv_base))
 314                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 315
 316                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 317                 if (!clk_name)
 318                         return -ENOMEM;
 319                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 320                                                       0, prv_base,
 321                                                       1, 15, 16, 15, 0, NULL);
 322                 parent = clk_name;
 323
 324                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 325                 if (!clk_name) {
 326                         kfree(parent);
 327                         return -ENOMEM;
 328                 }
 329                 clk = clk_register_gate(NULL, clk_name, parent,
 330                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 331                                         prv_base, 31, 0, NULL);
 332                 kfree(parent);
 333                 kfree(clk_name);
 334         }
 335 out:
 336         if (IS_ERR(clk))
 337                 return PTR_ERR(clk);
 338
 339         pdata->clk = clk;
 340         clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
 341         return 0;
 342 }
 343
 344 static int acpi_lpss_create_device(struct acpi_device *adev,
 345                                    const struct acpi_device_id *id)
 346 {
 347         const struct lpss_device_desc *dev_desc;
 348         struct lpss_private_data *pdata;
 349         struct resource_entry *rentry;
 350         struct list_head resource_list;
 351         struct platform_device *pdev;
 352         int ret;
 353
 354         dev_desc = (const struct lpss_device_desc *)id->driver_data;
 355         if (!dev_desc) {
 356                 pdev = acpi_create_platform_device(adev);
 357                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 358         }
 359         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 360         if (!pdata)
 361                 return -ENOMEM;
 362
 363         INIT_LIST_HEAD(&resource_list);
 364         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 365         if (ret < 0)
 366                 goto err_out;
 367
 368         list_for_each_entry(rentry, &resource_list, node)
 369                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
 370                         if (dev_desc->prv_size_override)
 371                                 pdata->mmio_size = dev_desc->prv_size_override;
 372                         else
 373                                 pdata->mmio_size = resource_size(rentry->res);
 374                         pdata->mmio_base = ioremap(rentry->res->start,
 375                                                    pdata->mmio_size);
 376                         break;
 377                 }
 378
 379         acpi_dev_free_resource_list(&resource_list);
 380
 381         if (!pdata->mmio_base) {
 382                 ret = -ENOMEM;
 383                 goto err_out;
 384         }
 385
 386         pdata->dev_desc = dev_desc;
 387
 388         if (dev_desc->setup)
 389                 dev_desc->setup(pdata);
 390
 391         if (dev_desc->flags & LPSS_CLK) {
 392                 ret = register_device_clock(adev, pdata);
 393                 if (ret) {
 394                         /* Skip the device, but continue the namespace scan. */
 395                         ret = 0;
 396                         goto err_out;
 397                 }
 398         }
 399
 400         /*
 401          * This works around a known issue in ACPI tables where LPSS devices
 402          * have _PS0 and _PS3 without _PSC (and no power resources), so
 403          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 404          */
 405         ret = acpi_device_fix_up_power(adev);
 406         if (ret) {
 407                 /* Skip the device, but continue the namespace scan. */
 408                 ret = 0;
 409                 goto err_out;
 410         }
 411
 412         adev->driver_data = pdata;
 413         pdev = acpi_create_platform_device(adev);
 414         if (!IS_ERR_OR_NULL(pdev)) {
 415                 return 1;
 416         }
 417
 418         ret = PTR_ERR(pdev);
 419         adev->driver_data = NULL;
 420
 421  err_out:
 422         kfree(pdata);
 423         return ret;
 424 }
 425
 426 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 427 {
 428         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 429 }
 430
 431 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 432                              unsigned int reg)
 433 {
 434         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 435 }
 436
 437 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 438 {
 439         struct acpi_device *adev;
 440         struct lpss_private_data *pdata;
 441         unsigned long flags;
 442         int ret;
 443
 444         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 445         if (WARN_ON(ret))
 446                 return ret;
 447
 448         spin_lock_irqsave(&dev->power.lock, flags);
 449         if (pm_runtime_suspended(dev)) {
 450                 ret = -EAGAIN;
 451                 goto out;
 452         }
 453         pdata = acpi_driver_data(adev);
 454         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 455                 ret = -ENODEV;
 456                 goto out;
 457         }
 458         *val = __lpss_reg_read(pdata, reg);
 459
 460  out:
 461         spin_unlock_irqrestore(&dev->power.lock, flags);
 462         return ret;
 463 }
 464
 465 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 466                              char *buf)
 467 {
 468         u32 ltr_value = 0;
 469         unsigned int reg;
 470         int ret;
 471
 472         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 473         ret = lpss_reg_read(dev, reg, &ltr_value);
 474         if (ret)
 475                 return ret;
 476
 477         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 478 }
 479
 480 static ssize_t lpss_ltr_mode_show(struct device *dev,
 481                                   struct device_attribute *attr, char *buf)
 482 {
 483         u32 ltr_mode = 0;
 484         char *outstr;
 485         int ret;
 486
 487         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 488         if (ret)
 489                 return ret;
 490
 491         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 492         return sprintf(buf, "%s\n", outstr);
 493 }
 494
 495 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 496 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 497 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 498
 499 static struct attribute *lpss_attrs[] = {
 500         &dev_attr_auto_ltr.attr,
 501         &dev_attr_sw_ltr.attr,
 502         &dev_attr_ltr_mode.attr,
 503         NULL,
 504 };
 505
 506 static struct attribute_group lpss_attr_group = {
 507         .attrs = lpss_attrs,
 508         .name = "lpss_ltr",
 509 };
 510
 511 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 512 {
 513         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 514         u32 ltr_mode, ltr_val;
 515
 516         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 517         if (val < 0) {
 518                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 519                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 520                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 521                 }
 522                 return;
 523         }
 524         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 525         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 526                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 527                 val = LPSS_LTR_MAX_VAL;
 528         } else if (val > LPSS_LTR_MAX_VAL) {
 529                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 530                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 531         } else {
 532                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 533         }
 534         ltr_val |= val;
 535         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 536         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 537                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 538                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 539         }
 540 }
 541
 542 #ifdef CONFIG_PM
 543 /**
 544  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 545  * @dev: LPSS device
 546  * @pdata: pointer to the private data of the LPSS device
 547  *
 548  * Most LPSS devices have private registers which may loose their context when
 549  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 550  * prv_reg_ctx array.
 551  */
 552 static void acpi_lpss_save_ctx(struct device *dev,
 553                                struct lpss_private_data *pdata)
 554 {
 555         unsigned int i;
 556
 557         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 558                 unsigned long offset = i * sizeof(u32);
 559
 560                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 561                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 562                         pdata->prv_reg_ctx[i], offset);
 563         }
 564 }
 565
 566 /**
 567  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 568  * @dev: LPSS device
 569  * @pdata: pointer to the private data of the LPSS device
 570  *
 571  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 572  */
 573 static void acpi_lpss_restore_ctx(struct device *dev,
 574                                   struct lpss_private_data *pdata)
 575 {
 576         unsigned int i;
 577
 578         /*
 579          * The following delay is needed or the subsequent write operations may
 580          * fail. The LPSS devices are actually PCI devices and the PCI spec
 581          * expects 10ms delay before the device can be accessed after D3 to D0
 582          * transition. However some platforms like BSW does not need this delay.
 583          */
 584         unsigned int delay = 10;        /* default 10ms delay */
 585
 586         if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
 587                 delay = 0;
 588
 589         msleep(delay);
 590
 591         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 592                 unsigned long offset = i * sizeof(u32);
 593
 594                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 595                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 596                         pdata->prv_reg_ctx[i], offset);
 597         }
 598 }
 599
 600 #ifdef CONFIG_PM_SLEEP
 601 static int acpi_lpss_suspend_late(struct device *dev)
 602 {
 603         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 604         int ret;
 605
 606         ret = pm_generic_suspend_late(dev);
 607         if (ret)
 608                 return ret;
 609
 610         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 611                 acpi_lpss_save_ctx(dev, pdata);
 612
 613         return acpi_dev_suspend_late(dev);
 614 }
 615
 616 static int acpi_lpss_resume_early(struct device *dev)
 617 {
 618         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 619         int ret;
 620
 621         ret = acpi_dev_resume_early(dev);
 622         if (ret)
 623                 return ret;
 624
 625         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 626                 acpi_lpss_restore_ctx(dev, pdata);
 627
 628         return pm_generic_resume_early(dev);
 629 }
 630 #endif /* CONFIG_PM_SLEEP */
 631
 632 static int acpi_lpss_runtime_suspend(struct device *dev)
 633 {
 634         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 635         int ret;
 636
 637         ret = pm_generic_runtime_suspend(dev);
 638         if (ret)
 639                 return ret;
 640
 641         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 642                 acpi_lpss_save_ctx(dev, pdata);
 643
 644         return acpi_dev_runtime_suspend(dev);
 645 }
 646
 647 static int acpi_lpss_runtime_resume(struct device *dev)
 648 {
 649         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 650         int ret;
 651
 652         ret = acpi_dev_runtime_resume(dev);
 653         if (ret)
 654                 return ret;
 655
 656         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 657                 acpi_lpss_restore_ctx(dev, pdata);
 658
 659         return pm_generic_runtime_resume(dev);
 660 }
 661 #endif /* CONFIG_PM */
 662
 663 static struct dev_pm_domain acpi_lpss_pm_domain = {
 664         .ops = {
 665 #ifdef CONFIG_PM
 666 #ifdef CONFIG_PM_SLEEP
 667                 .prepare = acpi_subsys_prepare,
 668                 .complete = acpi_subsys_complete,
 669                 .suspend = acpi_subsys_suspend,
 670                 .suspend_late = acpi_lpss_suspend_late,
 671                 .resume_early = acpi_lpss_resume_early,
 672                 .freeze = acpi_subsys_freeze,
 673                 .poweroff = acpi_subsys_suspend,
 674                 .poweroff_late = acpi_lpss_suspend_late,
 675                 .restore_early = acpi_lpss_resume_early,
 676 #endif
 677                 .runtime_suspend = acpi_lpss_runtime_suspend,
 678                 .runtime_resume = acpi_lpss_runtime_resume,
 679 #endif
 680         },
 681 };
 682
 683 static int acpi_lpss_platform_notify(struct notifier_block *nb,
 684                                      unsigned long action, void *data)
 685 {
 686         struct platform_device *pdev = to_platform_device(data);
 687         struct lpss_private_data *pdata;
 688         struct acpi_device *adev;
 689         const struct acpi_device_id *id;
 690
 691         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
 692         if (!id || !id->driver_data)
 693                 return 0;
 694
 695         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
 696                 return 0;
 697
 698         pdata = acpi_driver_data(adev);
 699         if (!pdata)
 700                 return 0;
 701
 702         if (pdata->mmio_base &&
 703             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
 704                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
 705                 return 0;
 706         }
 707
 708         switch (action) {
 709         case BUS_NOTIFY_ADD_DEVICE:
 710                 pdev->dev.pm_domain = &acpi_lpss_pm_domain;
 711                 if (pdata->dev_desc->flags & LPSS_LTR)
 712                         return sysfs_create_group(&pdev->dev.kobj,
 713                                                   &lpss_attr_group);
 714                 break;
 715         case BUS_NOTIFY_DEL_DEVICE:
 716                 if (pdata->dev_desc->flags & LPSS_LTR)
 717                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
 718                 pdev->dev.pm_domain = NULL;
 719                 break;
 720         default:
 721                 break;
 722         }
 723
 724         return 0;
 725 }
 726
 727 static struct notifier_block acpi_lpss_nb = {
 728         .notifier_call = acpi_lpss_platform_notify,
 729 };
 730
 731 static void acpi_lpss_bind(struct device *dev)
 732 {
 733         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 734
 735         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
 736                 return;
 737
 738         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
 739                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
 740         else
 741                 dev_err(dev, "MMIO size insufficient to access LTR\n");
 742 }
 743
 744 static void acpi_lpss_unbind(struct device *dev)
 745 {
 746         dev->power.set_latency_tolerance = NULL;
 747 }
 748
 749 static struct acpi_scan_handler lpss_handler = {
 750         .ids = acpi_lpss_device_ids,
 751         .attach = acpi_lpss_create_device,
 752         .bind = acpi_lpss_bind,
 753         .unbind = acpi_lpss_unbind,
 754 };
 755
 756 void __init acpi_lpss_init(void)
 757 {
 758         if (!lpt_clk_init()) {
 759                 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
 760                 acpi_scan_add_handler(&lpss_handler);
 761         }
 762 }
 763
 764 #else
 765
 766 static struct acpi_scan_handler lpss_handler = {
 767         .ids = acpi_lpss_device_ids,
 768 };
 769
 770 void __init acpi_lpss_init(void)
 771 {
 772         acpi_scan_add_handler(&lpss_handler);
 773 }
 774
 775 #endif /* CONFIG_X86_INTEL_LPSS */